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1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
29 #ifndef RS6000_OPTS_H
31 #endif
33 /* Definitions for the object file format. These are set at
34 compile-time. */
36 #define OBJECT_XCOFF 1
37 #define OBJECT_ELF 2
38 #define OBJECT_PEF 3
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
46 #ifndef TARGET_AIX
47 #define TARGET_AIX 0
48 #endif
50 #ifndef TARGET_AIX_OS
51 #define TARGET_AIX_OS 0
52 #endif
54 /* Control whether function entry points use a "dot" symbol when
55 ABI_AIX. */
56 #define DOT_SYMBOLS 1
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
61 #endif
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
66 #else
67 #define PPC405_ERRATUM77 0
68 #endif
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
72 #endif
82 /* Common ASM definitions used by ASM_SPEC among the various targets for
83 handling -mcpu=xxx switches. There is a parallel list in driver-powerpcspe.c to
84 provide the default assembler options if the user uses -mcpu=native, so if
85 you make changes here, make them also there. */
86 #define ASM_CPU_SPEC \
87 "%{!mcpu*: \
88 %{mpowerpc64*: -mppc64} \
89 %{!mpowerpc64*: %(asm_default)}} \
90 %{mcpu=native: %(asm_cpu_native)} \
91 %{mcpu=cell: -mcell} \
92 %{mcpu=power3: -mppc64} \
93 %{mcpu=power4: -mpower4} \
94 %{mcpu=power5: %(asm_cpu_power5)} \
95 %{mcpu=power5+: %(asm_cpu_power5)} \
96 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
97 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
98 %{mcpu=power7: %(asm_cpu_power7)} \
99 %{mcpu=power8: %(asm_cpu_power8)} \
100 %{mcpu=power9: %(asm_cpu_power9)} \
101 %{mcpu=a2: -ma2} \
102 %{mcpu=powerpc: -mppc} \
103 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
104 %{mcpu=rs64a: -mppc64} \
105 %{mcpu=401: -mppc} \
106 %{mcpu=403: -m403} \
107 %{mcpu=405: -m405} \
108 %{mcpu=405fp: -m405} \
109 %{mcpu=440: -m440} \
110 %{mcpu=440fp: -m440} \
111 %{mcpu=464: -m440} \
112 %{mcpu=464fp: -m440} \
113 %{mcpu=476: %(asm_cpu_476)} \
114 %{mcpu=476fp: %(asm_cpu_476)} \
115 %{mcpu=505: -mppc} \
116 %{mcpu=601: -m601} \
117 %{mcpu=602: -mppc} \
118 %{mcpu=603: -mppc} \
119 %{mcpu=603e: -mppc} \
120 %{mcpu=ec603e: -mppc} \
121 %{mcpu=604: -mppc} \
122 %{mcpu=604e: -mppc} \
123 %{mcpu=620: -mppc64} \
124 %{mcpu=630: -mppc64} \
125 %{mcpu=740: -mppc} \
126 %{mcpu=750: -mppc} \
127 %{mcpu=G3: -mppc} \
128 %{mcpu=7400: -mppc -maltivec} \
129 %{mcpu=7450: -mppc -maltivec} \
130 %{mcpu=G4: -mppc -maltivec} \
131 %{mcpu=801: -mppc} \
132 %{mcpu=821: -mppc} \
133 %{mcpu=823: -mppc} \
134 %{mcpu=860: -mppc} \
135 %{mcpu=970: -mpower4 -maltivec} \
136 %{mcpu=G5: -mpower4 -maltivec} \
137 %{mcpu=8540: -me500} \
138 %{mcpu=8548: -me500} \
139 %{mcpu=e300c2: -me300} \
140 %{mcpu=e300c3: -me300} \
141 %{mcpu=e500mc: -me500mc} \
142 %{mcpu=e500mc64: -me500mc64} \
143 %{mcpu=e5500: -me5500} \
144 %{mcpu=e6500: -me6500} \
145 %{maltivec: -maltivec} \
146 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
147 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
148 -many"
154 /* This macro defines names of additional specifications to put in the specs
155 that can be used in various specifications like CC1_SPEC. Its definition
156 is an initializer with a subgrouping for each command option.
158 Each subgrouping contains a string constant, that defines the
159 specification name, and a string constant that used by the GCC driver
160 program.
162 Do not define this macro if it does not need to do anything. */
164 #define SUBTARGET_EXTRA_SPECS
166 #define EXTRA_SPECS \
178 SUBTARGET_EXTRA_SPECS
180 /* -mcpu=native handling only makes sense with compiler running on
181 an PowerPC chip. If changing this condition, also change
182 the condition in driver-powerpcspe.c. */
183 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
184 /* In driver-powerpcspe.c. */
186 #define EXTRA_SPEC_FUNCTIONS \
188 #define HAVE_LOCAL_CPU_DETECT
191 #else
193 #endif
195 #ifndef CC1_CPU_SPEC
196 #ifdef HAVE_LOCAL_CPU_DETECT
197 #define CC1_CPU_SPEC \
198 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
199 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
200 #else
202 #endif
203 #endif
205 /* Architecture type. */
207 /* Define TARGET_MFCRF if the target assembler does not support the
208 optional field operand for mfcr. */
210 #ifndef HAVE_AS_MFCRF
211 #undef TARGET_MFCRF
212 #define TARGET_MFCRF 0
213 #endif
215 /* Define TARGET_TLS_MARKERS if the target assembler does not support
216 arg markers for __tls_get_addr calls. */
217 #ifndef HAVE_AS_TLS_MARKERS
218 #undef TARGET_TLS_MARKERS
219 #define TARGET_TLS_MARKERS 0
220 #else
221 #define TARGET_TLS_MARKERS tls_markers
222 #endif
224 #ifndef TARGET_SECURE_PLT
225 #define TARGET_SECURE_PLT 0
226 #endif
228 #ifndef TARGET_CMODEL
229 #define TARGET_CMODEL CMODEL_SMALL
230 #endif
232 #define TARGET_32BIT (! TARGET_64BIT)
234 #ifndef HAVE_AS_TLS
235 #define HAVE_AS_TLS 0
236 #endif
238 #ifndef TARGET_LINK_STACK
239 #define TARGET_LINK_STACK 0
240 #endif
242 #ifndef SET_TARGET_LINK_STACK
243 #define SET_TARGET_LINK_STACK(X) do { } while (0)
244 #endif
246 #ifndef TARGET_FLOAT128_ENABLE_TYPE
247 #define TARGET_FLOAT128_ENABLE_TYPE 0
248 #endif
250 /* Return 1 for a symbol ref for a thread-local storage symbol. */
251 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
252 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
254 #ifdef IN_LIBGCC2
255 /* For libgcc2 we make sure this is a compile time constant */
256 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
257 #undef TARGET_POWERPC64
258 #define TARGET_POWERPC64 1
259 #else
260 #undef TARGET_POWERPC64
261 #define TARGET_POWERPC64 0
262 #endif
263 #else
264 /* The option machinery will define this. */
265 #endif
267 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
269 /* FPU operations supported.
270 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
271 also test TARGET_HARD_FLOAT. */
272 #define TARGET_SINGLE_FLOAT 1
273 #define TARGET_DOUBLE_FLOAT 1
274 #define TARGET_SINGLE_FPU 0
275 #define TARGET_SIMPLE_FPU 0
276 #define TARGET_XILINX_FPU 0
278 /* Recast the processor type to the cpu attribute. */
279 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
281 /* Define generic processor types based upon current deployment. */
282 #define PROCESSOR_COMMON PROCESSOR_PPC601
283 #define PROCESSOR_POWERPC PROCESSOR_PPC604
284 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
286 /* Define the default processor. This is overridden by other tm.h files. */
287 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
288 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
290 /* Specify the dialect of assembler to use. Only new mnemonics are supported
291 starting with GCC 4.8, i.e. just one dialect, but for backwards
292 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
293 defined. */
294 #define ASSEMBLER_DIALECT 1
296 /* Debug support */
304 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
305 | MASK_DEBUG_ARG \
306 | MASK_DEBUG_REG \
307 | MASK_DEBUG_ADDR \
308 | MASK_DEBUG_COST \
309 | MASK_DEBUG_TARGET \
310 | MASK_DEBUG_BUILTIN)
312 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
313 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
314 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
315 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
316 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
317 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
318 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
320 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
321 long double format that uses a pair of doubles, or IEEE 128-bit floating
322 point. KFmode was added as a way to represent IEEE 128-bit floating point,
323 even if the default for long double is the IBM long double format.
324 Similarly IFmode is the IBM long double format even if the default is IEEE
325 128-bit. Don't allow IFmode if -msoft-float. */
326 #define FLOAT128_IEEE_P(MODE) \
327 ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
328 || ((MODE) == KFmode) || ((MODE) == KCmode))
330 #define FLOAT128_IBM_P(MODE) \
331 ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
332 || (TARGET_HARD_FLOAT && TARGET_FPRS \
333 && ((MODE) == IFmode || (MODE) == ICmode)))
335 /* Helper macros to say whether a 128-bit floating point type can go in a
336 single vector register, or whether it needs paired scalar values. */
337 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
339 #define FLOAT128_2REG_P(MODE) \
340 (FLOAT128_IBM_P (MODE) \
341 || ((MODE) == TDmode) \
342 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
344 /* Return true for floating point that does not use a vector register. */
345 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
346 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
348 /* Describe the vector unit used for arithmetic operations. */
351 #define VECTOR_UNIT_NONE_P(MODE) \
352 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
354 #define VECTOR_UNIT_VSX_P(MODE) \
355 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
357 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
358 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
360 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
361 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
363 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
364 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
365 (int)VECTOR_VSX, \
366 (int)VECTOR_P8_VECTOR))
368 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
369 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
370 compatible, so allow it as well, rather than changing all of the uses of the
371 macro. */
372 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
373 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
374 (int)VECTOR_ALTIVEC, \
375 (int)VECTOR_P8_VECTOR))
377 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
378 same unit as the vector unit we are using, but we may want to migrate to
379 using VSX style loads even for types handled by altivec. */
382 #define VECTOR_MEM_NONE_P(MODE) \
383 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
385 #define VECTOR_MEM_VSX_P(MODE) \
386 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
388 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
389 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
391 #define VECTOR_MEM_ALTIVEC_P(MODE) \
392 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
394 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
395 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
396 (int)VECTOR_VSX, \
397 (int)VECTOR_P8_VECTOR))
399 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
400 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
401 (int)VECTOR_ALTIVEC, \
402 (int)VECTOR_P8_VECTOR))
404 /* Return the alignment of a given vector type, which is set based on the
405 vector unit use. VSX for instance can load 32 or 64 bit aligned words
406 without problems, while Altivec requires 128-bit aligned vectors. */
409 #define VECTOR_ALIGN(MODE) \
410 ((rs6000_vector_align[(MODE)] != 0) \
411 ? rs6000_vector_align[(MODE)] \
412 : (int)GET_MODE_BITSIZE ((MODE)))
414 /* Determine the element order to use for vector instructions. By
415 default we use big-endian element order when targeting big-endian,
416 and little-endian element order when targeting little-endian. For
417 programs being ported from BE Power to LE Power, it can sometimes
418 be useful to use big-endian element order when targeting little-endian.
419 This is set via -maltivec=be, for example. */
420 #define VECTOR_ELT_ORDER_BIG \
421 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
423 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
424 with scalar instructions. */
425 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
427 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
428 with the ISA 3.0 MFVSRLD instructions. */
429 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
431 /* Alignment options for fields in structures for sub-targets following
432 AIX-like ABI.
433 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
434 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
436 Override the macro definitions when compiling libobjc to avoid undefined
437 reference to rs6000_alignment_flags due to library's use of GCC alignment
438 macros which use the macros below. */
440 #ifndef IN_TARGET_LIBS
441 #define MASK_ALIGN_POWER 0x00000000
442 #define MASK_ALIGN_NATURAL 0x00000001
443 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
444 #else
445 #define TARGET_ALIGN_NATURAL 0
446 #endif
448 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
449 #define TARGET_IEEEQUAD rs6000_ieeequad
450 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
451 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
453 #define TARGET_SPE_ABI 0
454 #define TARGET_SPE 0
455 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
456 #define TARGET_FPRS 1
457 #define TARGET_E500_SINGLE 0
458 #define TARGET_E500_DOUBLE 0
459 #define CHECK_E500_OPTIONS do { } while (0)
461 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
462 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
463 XILINX. */
464 #define TARGET_FCFID (TARGET_POWERPC64 \
469 || TARGET_XILINX_FPU)
471 #define TARGET_FCTIDZ TARGET_FCFID
472 #define TARGET_STFIWX TARGET_PPC_GFXOPT
473 #define TARGET_LFIWAX TARGET_CMPB
474 #define TARGET_LFIWZX TARGET_POPCNTD
475 #define TARGET_FCFIDS TARGET_POPCNTD
476 #define TARGET_FCFIDU TARGET_POPCNTD
477 #define TARGET_FCFIDUS TARGET_POPCNTD
478 #define TARGET_FCTIDUZ TARGET_POPCNTD
479 #define TARGET_FCTIWUZ TARGET_POPCNTD
480 #define TARGET_CTZ TARGET_MODULO
481 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
482 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
484 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
485 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
486 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
487 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
488 && TARGET_POWERPC64)
489 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
490 && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
493 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
494 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
495 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
497 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
498 loads are slow. */
499 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
501 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
502 in power7, so conditionalize them on p8 features. TImode syncs need quad
503 memory support. */
504 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
505 || TARGET_QUAD_MEMORY_ATOMIC \
506 || TARGET_DIRECT_MOVE)
508 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
510 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
511 to allocate the SDmode stack slot to get the value into the proper location
512 in the register. */
513 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
515 /* ISA 3.0 has new min/max functions that don't need fast math that are being
516 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
517 answers if the arguments are not in the normal range. */
518 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \
519 && (TARGET_P9_MINMAX || !flag_trapping_math))
521 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
522 && (TARGET_P9_MINMAX || !flag_trapping_math))
524 /* In switching from using target_flags to using rs6000_isa_flags, the options
525 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
526 OPTION_MASK_<xxx> back into MASK_<xxx>. */
527 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
528 #define MASK_CMPB OPTION_MASK_CMPB
529 #define MASK_CRYPTO OPTION_MASK_CRYPTO
530 #define MASK_DFP OPTION_MASK_DFP
531 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
532 #define MASK_DLMZB OPTION_MASK_DLMZB
533 #define MASK_EABI OPTION_MASK_EABI
534 #define MASK_FLOAT128_TYPE OPTION_MASK_FLOAT128_TYPE
535 #define MASK_FPRND OPTION_MASK_FPRND
536 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
537 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
538 #define MASK_HTM OPTION_MASK_HTM
539 #define MASK_ISEL OPTION_MASK_ISEL
540 #define MASK_MFCRF OPTION_MASK_MFCRF
541 #define MASK_MFPGPR OPTION_MASK_MFPGPR
542 #define MASK_MULHW OPTION_MASK_MULHW
543 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
544 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
545 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
546 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
547 #define MASK_P9_MISC OPTION_MASK_P9_MISC
548 #define MASK_POPCNTB OPTION_MASK_POPCNTB
549 #define MASK_POPCNTD OPTION_MASK_POPCNTD
550 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
551 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
552 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
553 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
554 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
555 #define MASK_STRING OPTION_MASK_STRING
556 #define MASK_UPDATE OPTION_MASK_UPDATE
557 #define MASK_VSX OPTION_MASK_VSX
558 #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
560 #ifndef IN_LIBGCC2
561 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
562 #endif
564 #ifdef TARGET_64BIT
565 #define MASK_64BIT OPTION_MASK_64BIT
566 #endif
568 #ifdef TARGET_LITTLE_ENDIAN
569 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
570 #endif
572 #ifdef TARGET_REGNAMES
573 #define MASK_REGNAMES OPTION_MASK_REGNAMES
574 #endif
576 #ifdef TARGET_PROTOTYPE
577 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
578 #endif
580 #ifdef TARGET_MODULO
581 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
582 #endif
585 /* For power systems, we want to enable Altivec and VSX builtins even if the
586 user did not use -maltivec or -mvsx to allow the builtins to be used inside
587 of #pragma GCC target or the target attribute to change the code level for a
588 given system. The SPE and Paired builtins are only enabled if you configure
589 the compiler for those builtins, and those machines don't support altivec or
590 VSX. */
592 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
593 && ((TARGET_POWERPC64 \
598 || TARGET_ALTIVEC \
599 || TARGET_VSX \
600 || TARGET_HARD_FLOAT)))
602 /* E500 cores only support plain "sync", not lwsync. */
603 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
604 || rs6000_cpu == PROCESSOR_PPC8548)
607 /* Whether SF/DF operations are supported on the E500. */
608 #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
609 && !TARGET_FPRS)
611 #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
612 && !TARGET_FPRS && TARGET_E500_DOUBLE)
614 /* Whether SF/DF operations are supported by the normal floating point unit
615 (or the vector/scalar unit). */
616 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
617 && TARGET_SINGLE_FLOAT)
619 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
620 && TARGET_DOUBLE_FLOAT)
622 /* Whether SF/DF operations are supported by any hardware. */
623 #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
624 #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
626 /* Which machine supports the various reciprocal estimate instructions. */
627 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
628 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
630 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
631 && TARGET_DOUBLE_FLOAT \
632 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
634 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
635 && TARGET_PPC_GFXOPT && TARGET_FPRS \
636 && TARGET_SINGLE_FLOAT)
638 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
639 && TARGET_DOUBLE_FLOAT \
640 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
642 /* Conditions to allow TOC fusion for loading/storing integers. */
643 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
644 && TARGET_TOC_FUSION \
645 && (TARGET_CMODEL != CMODEL_SMALL) \
646 && TARGET_POWERPC64)
648 /* Conditions to allow TOC fusion for loading/storing floating point. */
649 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
650 && TARGET_TOC_FUSION \
651 && (TARGET_CMODEL != CMODEL_SMALL) \
652 && TARGET_POWERPC64 \
653 && TARGET_HARD_FLOAT \
654 && TARGET_FPRS \
655 && TARGET_SINGLE_FLOAT \
656 && TARGET_DOUBLE_FLOAT)
658 /* Macro to say whether we can do optimizations where we need to do parts of
659 the calculation in 64-bit GPRs and then is transfered to the vector
660 registers. Do not allow -maltivec=be for these optimizations, because it
661 adds to the complexity of the code. */
662 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
663 && TARGET_P8_VECTOR \
664 && TARGET_POWERPC64 \
665 && TARGET_UPPER_REGS_DI \
666 && (rs6000_altivec_element_order != 2))
668 /* Whether the various reciprocal divide/square root estimate instructions
669 exist, and whether we should automatically generate code for the instruction
670 by default. */
678 #define RS6000_RECIP_HAVE_RE_P(MODE) \
679 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
681 #define RS6000_RECIP_AUTO_RE_P(MODE) \
682 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
684 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
685 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
687 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
688 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
690 /* The default CPU for TARGET_OPTION_OVERRIDE. */
691 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
693 /* Target pragma. */
694 #define REGISTER_TARGET_PRAGMAS() do { \
696 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
697 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
698 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
699 } while (0)
701 /* Target #defines. */
702 #define TARGET_CPU_CPP_BUILTINS() \
703 rs6000_cpu_cpp_builtins (pfile)
705 /* Target CPU versions for D. */
706 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions
708 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
709 we're compiling for. Some configurations may need to override it. */
710 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
711 do \
712 { \
713 if (BYTES_BIG_ENDIAN) \
714 { \
718 } \
719 else \
720 { \
724 } \
725 } \
726 while (0)
727 \f
728 /* Target machine storage layout. */
730 /* Define this macro if it is advisable to hold scalars in registers
731 in a wider mode than that declared by the program. In such cases,
732 the value is constrained to be within the bounds of the declared
733 type, but kept valid in the wider mode. The signedness of the
734 extension may differ from that of the type. */
736 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
737 if (GET_MODE_CLASS (MODE) == MODE_INT \
738 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
739 (MODE) = TARGET_32BIT ? SImode : DImode;
741 /* Define this if most significant bit is lowest numbered
742 in instructions that operate on numbered bit-fields. */
743 /* That is true on RS/6000. */
744 #define BITS_BIG_ENDIAN 1
746 /* Define this if most significant byte of a word is the lowest numbered. */
747 /* That is true on RS/6000. */
748 #define BYTES_BIG_ENDIAN 1
750 /* Define this if most significant word of a multiword number is lowest
751 numbered.
753 For RS/6000 we can decide arbitrarily since there are no machine
754 instructions for them. Might as well be consistent with bits and bytes. */
755 #define WORDS_BIG_ENDIAN 1
757 /* This says that for the IBM long double the larger magnitude double
758 comes first. It's really a two element double array, and arrays
759 don't index differently between little- and big-endian. */
760 #define LONG_DOUBLE_LARGE_FIRST 1
762 #define MAX_BITS_PER_WORD 64
764 /* Width of a word, in units (bytes). */
765 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
766 #ifdef IN_LIBGCC2
767 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
768 #else
769 #define MIN_UNITS_PER_WORD 4
770 #endif
771 #define UNITS_PER_FP_WORD 8
772 #define UNITS_PER_ALTIVEC_WORD 16
773 #define UNITS_PER_VSX_WORD 16
774 #define UNITS_PER_SPE_WORD 8
775 #define UNITS_PER_PAIRED_WORD 8
777 /* Type used for ptrdiff_t, as a string used in a declaration. */
780 /* Type used for size_t, as a string used in a declaration. */
783 /* Type used for wchar_t, as a string used in a declaration. */
786 /* Width of wchar_t in bits. */
787 #define WCHAR_TYPE_SIZE 16
789 /* A C expression for the size in bits of the type `short' on the
790 target machine. If you don't define this, the default is half a
791 word. (If this would be less than one storage unit, it is
792 rounded up to one unit.) */
793 #define SHORT_TYPE_SIZE 16
795 /* A C expression for the size in bits of the type `int' on the
796 target machine. If you don't define this, the default is one
797 word. */
798 #define INT_TYPE_SIZE 32
800 /* A C expression for the size in bits of the type `long' on the
801 target machine. If you don't define this, the default is one
802 word. */
803 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
805 /* A C expression for the size in bits of the type `long long' on the
806 target machine. If you don't define this, the default is two
807 words. */
808 #define LONG_LONG_TYPE_SIZE 64
810 /* A C expression for the size in bits of the type `float' on the
811 target machine. If you don't define this, the default is one
812 word. */
813 #define FLOAT_TYPE_SIZE 32
815 /* A C expression for the size in bits of the type `double' on the
816 target machine. If you don't define this, the default is two
817 words. */
818 #define DOUBLE_TYPE_SIZE 64
820 /* A C expression for the size in bits of the type `long double' on
821 the target machine. If you don't define this, the default is two
822 words. */
823 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
825 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
826 #define WIDEST_HARDWARE_FP_SIZE 64
828 /* Width in bits of a pointer.
829 See also the macro `Pmode' defined below. */
831 #define POINTER_SIZE rs6000_pointer_size
833 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
834 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
836 /* Boundary (in *bits*) on which stack pointer should be aligned. */
837 #define STACK_BOUNDARY \
838 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
839 ? 64 : 128)
841 /* Allocation boundary (in *bits*) for the code of a function. */
842 #define FUNCTION_BOUNDARY 32
844 /* No data type wants to be aligned rounder than this. */
845 #define BIGGEST_ALIGNMENT 128
847 /* Alignment of field after `int : 0' in a structure. */
848 #define EMPTY_FIELD_BOUNDARY 32
850 /* Every structure's size must be a multiple of this. */
851 #define STRUCTURE_SIZE_BOUNDARY 8
853 /* A bit-field declared as `int' forces `int' alignment for the struct. */
854 #define PCC_BITFIELD_TYPE_MATTERS 1
858 /* A C expression to compute the alignment for a variables in the
859 local store. TYPE is the data type, and ALIGN is the alignment
860 that the object would ordinarily have. */
861 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
862 rs6000_data_alignment (TYPE, ALIGN, align_both)
864 /* Make arrays of chars word-aligned for the same reasons. */
865 #define DATA_ALIGNMENT(TYPE, ALIGN) \
866 rs6000_data_alignment (TYPE, ALIGN, align_opt)
868 /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
869 64 bits. */
870 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
871 rs6000_data_alignment (TYPE, ALIGN, align_abi)
873 /* Nonzero if move instructions will actually fail to work
874 when given unaligned data. */
875 #define STRICT_ALIGNMENT 0
876 \f
877 /* Standard register usage. */
879 /* Number of actual hardware registers.
880 The hardware registers are assigned numbers for the compiler
881 from 0 to just below FIRST_PSEUDO_REGISTER.
882 All registers that the compiler knows about must be given numbers,
883 even those that are not normally considered general registers.
885 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
886 a count register, a link register, and 8 condition register fields,
887 which we view here as separate registers. AltiVec adds 32 vector
888 registers and a VRsave register.
890 In addition, the difference between the frame and argument pointers is
891 a function of the number of registers saved, so we need to have a
892 register for AP that will later be eliminated in favor of SP or FP.
893 This is a normal register, but it is fixed.
895 We also create a pseudo register for float/int conversions, that will
896 really represent the memory location used. It is represented here as
897 a register, in order to work around problems in allocating stack storage
898 in inline functions.
900 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
901 pointer, which is eventually eliminated in favor of SP or FP.
903 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
905 #define FIRST_PSEUDO_REGISTER 149
907 /* This must be included for pre gcc 3.0 glibc compatibility. */
908 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
910 /* True if register is an SPE High register. */
911 #define SPE_HIGH_REGNO_P(N) \
912 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
914 /* SPE high registers added as hard regs.
915 The sfp register and 3 HTM registers
916 aren't included in DWARF_FRAME_REGISTERS. */
917 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
919 /* The SPE has an additional 32 synthetic registers, with DWARF debug
920 info numbering for these registers starting at 1200. While eh_frame
921 register numbering need not be the same as the debug info numbering,
922 we choose to number these regs for eh_frame at 1200 too.
924 We must map them here to avoid huge unwinder tables mostly consisting
925 of unused space. */
926 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
927 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
929 /* Use standard DWARF numbering for DWARF debugging information. */
930 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
932 /* Use gcc hard register numbering for eh_frame. */
933 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
935 /* Map register numbers held in the call frame info that gcc has
936 collected using DWARF_FRAME_REGNUM to those that should be output in
937 .debug_frame and .eh_frame. */
938 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
939 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
941 /* 1 for registers that have pervasive standard uses
942 and are not available for the register allocator.
944 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
945 as a local register; for all other OS's r2 is the TOC pointer.
947 On System V implementations, r13 is fixed and not available for use. */
949 #define FIXED_REGISTERS \
950 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
951 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
952 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
953 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
954 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
956 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
957 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
958 1, 1 \
959 , 1, 1, 1, 1, 1, 1, \
961 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
962 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
963 }
965 /* 1 for registers not available across function calls.
966 These must include the FIXED_REGISTERS and also any
967 registers that can be used without being saved.
968 The latter must include the registers where values are returned
969 and the register where structure-value addresses are passed.
970 Aside from that, you can include as many other registers as you like. */
972 #define CALL_USED_REGISTERS \
973 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
974 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
975 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
976 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
977 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
979 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
980 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
981 1, 1 \
982 , 1, 1, 1, 1, 1, 1, \
984 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
985 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
986 }
988 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
989 the entire set of `FIXED_REGISTERS' be included.
990 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
991 This macro is optional. If not specified, it defaults to the value
992 of `CALL_USED_REGISTERS'. */
994 #define CALL_REALLY_USED_REGISTERS \
995 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
996 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
997 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
998 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
999 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1001 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1002 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1003 0, 0 \
1004 , 0, 0, 0, 0, 0, 0, \
1006 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1007 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1008 }
1010 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1012 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1013 #define FIRST_SAVED_FP_REGNO (14+32)
1014 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1016 /* List the order in which to allocate registers. Each register must be
1017 listed once, even those in FIXED_REGISTERS.
1019 We allocate in the following order:
1020 fp0 (not saved or used for anything)
1021 fp13 - fp2 (not saved; incoming fp arg registers)
1022 fp1 (not saved; return value)
1023 fp31 - fp14 (saved; order given to save least number)
1024 cr7, cr5 (not saved or special)
1025 cr6 (not saved, but used for vector operations)
1026 cr1 (not saved, but used for FP operations)
1027 cr0 (not saved, but used for arithmetic operations)
1028 cr4, cr3, cr2 (saved)
1029 r9 (not saved; best for TImode)
1030 r10, r8-r4 (not saved; highest first for less conflict with params)
1031 r3 (not saved; return value register)
1032 r11 (not saved; later alloc to help shrink-wrap)
1033 r0 (not saved; cannot be base reg)
1034 r31 - r13 (saved; order given to save least number)
1035 r12 (not saved; if used for DImode or DFmode would use r13)
1036 ctr (not saved; when we have the choice ctr is better)
1037 lr (saved)
1038 r1, r2, ap, ca (fixed)
1039 v0 - v1 (not saved or used for anything)
1040 v13 - v3 (not saved; incoming vector arg registers)
1041 v2 (not saved; incoming vector arg reg; return value)
1042 v19 - v14 (not saved or used for anything)
1043 v31 - v20 (saved; order given to save least number)
1044 vrsave, vscr (fixed)
1045 spe_acc, spefscr (fixed)
1046 sfp (fixed)
1047 tfhar (fixed)
1048 tfiar (fixed)
1049 texasr (fixed)
1050 */
1052 #if FIXED_R2 == 1
1053 #define MAYBE_R2_AVAILABLE
1054 #define MAYBE_R2_FIXED 2,
1055 #else
1056 #define MAYBE_R2_AVAILABLE 2,
1057 #define MAYBE_R2_FIXED
1058 #endif
1060 #if FIXED_R13 == 1
1061 #define EARLY_R12 12,
1062 #define LATE_R12
1063 #else
1064 #define EARLY_R12
1065 #define LATE_R12 12,
1066 #endif
1068 #define REG_ALLOC_ORDER \
1069 {32, \
1072 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1073 33, \
1074 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1075 50, 49, 48, 47, 46, \
1076 75, 73, 74, 69, 68, 72, 71, 70, \
1077 MAYBE_R2_AVAILABLE \
1078 9, 10, 8, 7, 6, 5, 4, \
1079 3, EARLY_R12 11, 0, \
1080 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1081 18, 17, 16, 15, 14, 13, LATE_R12 \
1082 66, 65, \
1083 1, MAYBE_R2_FIXED 67, 76, \
1085 77, 78, \
1086 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1087 79, \
1088 96, 95, 94, 93, 92, 91, \
1089 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1090 109, 110, \
1091 111, 112, 113, 114, 115, 116, \
1092 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
1093 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
1094 141, 142, 143, 144, 145, 146, 147, 148 \
1095 }
1097 /* True if register is floating-point. */
1098 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1100 /* True if register is a condition register. */
1101 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1103 /* True if register is a condition register, but not cr0. */
1104 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1106 /* True if register is an integer register. */
1107 #define INT_REGNO_P(N) \
1108 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1110 /* SPE SIMD registers are just the GPRs. */
1111 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1113 /* PAIRED SIMD registers are just the FPRs. */
1114 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1116 /* True if register is the CA register. */
1117 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1119 /* True if register is an AltiVec register. */
1120 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1122 /* True if register is a VSX register. */
1123 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1125 /* Alternate name for any vector register supporting floating point, no matter
1126 which instruction set(s) are available. */
1127 #define VFLOAT_REGNO_P(N) \
1128 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1130 /* Alternate name for any vector register supporting integer, no matter which
1131 instruction set(s) are available. */
1132 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1134 /* Alternate name for any vector register supporting logical operations, no
1135 matter which instruction set(s) are available. Allow GPRs as well as the
1136 vector registers. */
1137 #define VLOGICAL_REGNO_P(N) \
1138 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1139 || (TARGET_VSX && FP_REGNO_P (N))) \
1141 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1142 enough space to account for vectors in FP regs. However, TFmode/TDmode
1143 should not use VSX instructions to do a caller save. */
1144 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1145 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1146 ? (MODE) \
1147 : TARGET_VSX \
1148 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1149 && FP_REGNO_P (REGNO) \
1150 ? V2DFmode \
1151 : TARGET_E500_DOUBLE && (MODE) == SImode \
1152 ? SImode \
1153 : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \
1154 ? DFmode \
1155 : !TARGET_E500_DOUBLE && FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1156 ? DFmode \
1157 : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \
1158 ? DImode \
1159 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1161 #define VSX_VECTOR_MODE(MODE) \
1162 ((MODE) == V4SFmode \
1163 || (MODE) == V2DFmode) \
1165 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1166 really a vector, but we want to treat it as a vector for moves, and
1167 such. */
1169 #define ALTIVEC_VECTOR_MODE(MODE) \
1170 ((MODE) == V16QImode \
1171 || (MODE) == V8HImode \
1172 || (MODE) == V4SFmode \
1173 || (MODE) == V4SImode \
1174 || FLOAT128_VECTOR_P (MODE))
1176 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1177 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1178 || (MODE) == V2DImode || (MODE) == V1TImode)
1180 #define SPE_VECTOR_MODE(MODE) \
1181 ((MODE) == V4HImode \
1182 || (MODE) == V2SFmode \
1183 || (MODE) == V1DImode \
1184 || (MODE) == V2SImode)
1186 #define PAIRED_VECTOR_MODE(MODE) \
1187 ((MODE) == V2SFmode)
1189 /* Post-reload, we can't use any new AltiVec registers, as we already
1190 emitted the vrsave mask. */
1192 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1193 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1195 /* Specify the cost of a branch insn; roughly the number of extra insns that
1196 should be added to avoid a branch.
1198 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1199 unscheduled conditional branch. */
1201 #define BRANCH_COST(speed_p, predictable_p) 3
1203 /* Override BRANCH_COST heuristic which empirically produces worse
1204 performance for removing short circuiting from the logical ops. */
1206 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1208 /* A fixed register used at epilogue generation to address SPE registers
1209 with negative offsets. The 64-bit load/store instructions on the SPE
1210 only take positive offsets (and small ones at that), so we need to
1211 reserve a register for consing up negative offsets. */
1213 #define FIXED_SCRATCH 0
1215 /* Specify the registers used for certain standard purposes.
1216 The values of these macros are register numbers. */
1218 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1219 /* #define PC_REGNUM */
1221 /* Register to use for pushing function arguments. */
1222 #define STACK_POINTER_REGNUM 1
1224 /* Base register for access to local variables of the function. */
1225 #define HARD_FRAME_POINTER_REGNUM 31
1227 /* Base register for access to local variables of the function. */
1228 #define FRAME_POINTER_REGNUM 113
1230 /* Base register for access to arguments of the function. */
1231 #define ARG_POINTER_REGNUM 67
1233 /* Place to put static chain when calling a function that requires it. */
1234 #define STATIC_CHAIN_REGNUM 11
1236 /* Base register for access to thread local storage variables. */
1237 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1239 \f
1240 /* Define the classes of registers for register constraints in the
1241 machine description. Also define ranges of constants.
1243 One of the classes must always be named ALL_REGS and include all hard regs.
1244 If there is more than one class, another class must be named NO_REGS
1245 and contain no registers.
1247 The name GENERAL_REGS must be the name of a class (or an alias for
1248 another name such as ALL_REGS). This is the class of registers
1249 that is allowed by "g" or "r" in a register constraint.
1250 Also, registers outside this class are allocated only when
1251 instructions express preferences for them.
1253 The classes must be numbered in nondecreasing order; that is,
1254 a larger-numbered class must never be contained completely
1255 in a smaller-numbered class.
1257 For any two classes, it is very desirable that there be another
1258 class that represents their union. */
1260 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1261 condition registers, plus three special registers, CTR, and the link
1262 register. AltiVec adds a vector register class. VSX registers overlap the
1263 FPR registers and the Altivec registers.
1265 However, r0 is special in that it cannot be used as a base register.
1266 So make a class for registers valid as base registers.
1268 Also, cr0 is the only condition code register that can be used in
1269 arithmetic insns, so make a separate class for it. */
1271 enum reg_class
1272 {
1273 NO_REGS,
1274 BASE_REGS,
1275 GENERAL_REGS,
1276 FLOAT_REGS,
1277 ALTIVEC_REGS,
1278 VSX_REGS,
1279 VRSAVE_REGS,
1280 VSCR_REGS,
1281 SPE_ACC_REGS,
1282 SPEFSCR_REGS,
1283 SPR_REGS,
1284 NON_SPECIAL_REGS,
1285 LINK_REGS,
1286 CTR_REGS,
1287 LINK_OR_CTR_REGS,
1288 SPECIAL_REGS,
1289 SPEC_OR_GEN_REGS,
1290 CR0_REGS,
1291 CR_REGS,
1292 NON_FLOAT_REGS,
1293 CA_REGS,
1294 SPE_HIGH_REGS,
1295 ALL_REGS,
1296 LIM_REG_CLASSES
1297 };
1299 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1301 /* Give names of register classes as strings for dump file. */
1303 #define REG_CLASS_NAMES \
1304 { \
1328 }
1330 /* Define which registers fit in which classes.
1331 This is an initializer for a vector of HARD_REG_SET
1332 of length N_REG_CLASSES. */
1334 #define REG_CLASS_CONTENTS \
1335 { \
1337 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1339 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1341 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1343 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
1345 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
1347 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
1349 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
1351 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
1353 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
1355 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
1357 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
1359 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
1361 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
1363 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
1365 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
1367 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
1369 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
1371 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
1373 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
1375 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
1377 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
1379 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
1381 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
1382 }
1384 /* The same information, inverted:
1385 Return the class number of the smallest class containing
1386 reg number REGNO. This could be a conditional expression
1387 or could index an array. */
1391 #define REGNO_REG_CLASS(REGNO) \
1392 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1393 rs6000_regno_regclass[(REGNO)])
1395 /* Register classes for various constraints that are based on the target
1396 switches. */
1430 RS6000_CONSTRAINT_MAX
1431 };
1435 /* The class value for index registers, and the one for base regs. */
1436 #define INDEX_REG_CLASS GENERAL_REGS
1437 #define BASE_REG_CLASS BASE_REGS
1439 /* Return whether a given register class can hold VSX objects. */
1440 #define VSX_REG_CLASS_P(CLASS) \
1441 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1443 /* Return whether a given register class targets general purpose registers. */
1444 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1446 /* Given an rtx X being reloaded into a reg required to be
1447 in class CLASS, return the class of reg to actually use.
1448 In general this is just CLASS; but on some machines
1449 in some cases it is preferable to use a more restrictive class.
1451 On the RS/6000, we have to return NO_REGS when we want to reload a
1452 floating-point CONST_DOUBLE to force it to be copied to memory.
1454 We also don't want to reload integer values into floating-point
1455 registers if we can at all help it. In fact, this can
1456 cause reload to die, if it tries to generate a reload of CTR
1457 into a FP register and discovers it doesn't have the memory location
1458 required.
1460 ??? Would it be a good idea to have reload do the converse, that is
1461 try to reload floating modes into FP registers if possible?
1462 */
1464 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1465 rs6000_preferred_reload_class_ptr (X, CLASS)
1467 /* Return the register class of a scratch register needed to copy IN into
1468 or out of a register in CLASS in MODE. If it can be done directly,
1469 NO_REGS is returned. */
1471 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1472 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1474 /* For cpus that cannot load/store SDmode values from the 64-bit
1475 FP registers without using a full 64-bit load/store, we need
1476 to allocate a full 64-bit stack slot for them. */
1478 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1479 rs6000_secondary_memory_needed_rtx (MODE)
1481 /* Return the maximum number of consecutive registers
1482 needed to represent mode MODE in a register of class CLASS.
1484 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1485 a single reg is enough for two words, unless we have VSX, where the FP
1486 registers can hold 128 bits. */
1487 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1489 /* Stack layout; function entry, exit and calling. */
1491 /* Define this if pushing a word on the stack
1492 makes the stack pointer a smaller address. */
1493 #define STACK_GROWS_DOWNWARD 1
1495 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1496 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1498 /* Define this to nonzero if the nominal address of the stack frame
1499 is at the high-address end of the local variables;
1500 that is, each additional local variable allocated
1501 goes at a more negative offset in the frame.
1503 On the RS/6000, we grow upwards, from the area after the outgoing
1504 arguments. */
1505 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1506 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1508 /* Size of the fixed area on the stack */
1509 #define RS6000_SAVE_AREA \
1510 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1511 << (TARGET_64BIT ? 1 : 0))
1513 /* Stack offset for toc save slot. */
1514 #define RS6000_TOC_SAVE_SLOT \
1515 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1517 /* Align an address */
1518 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1520 /* Offset within stack frame to start allocating local variables at.
1521 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1522 first local allocated. Otherwise, it is the offset to the BEGINNING
1523 of the first local allocated.
1525 On the RS/6000, the frame pointer is the same as the stack pointer,
1526 except for dynamic allocations. So we start after the fixed area and
1527 outgoing parameter area.
1529 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1530 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1531 sizes of the fixed area and the parameter area must be a multiple of
1532 STACK_BOUNDARY. */
1534 #define RS6000_STARTING_FRAME_OFFSET \
1535 (cfun->calls_alloca \
1536 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1537 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1538 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1539 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1540 + RS6000_SAVE_AREA))
1542 /* Offset from the stack pointer register to an item dynamically
1543 allocated on the stack, e.g., by `alloca'.
1545 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1546 length of the outgoing arguments. The default is correct for most
1547 machines. See `function.c' for details.
1549 This value must be a multiple of STACK_BOUNDARY (hard coded in
1550 `emit-rtl.c'). */
1551 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1552 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1553 + STACK_POINTER_OFFSET, \
1554 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1556 /* If we generate an insn to push BYTES bytes,
1557 this says how many the stack pointer really advances by.
1558 On RS/6000, don't define this because there are no push insns. */
1559 /* #define PUSH_ROUNDING(BYTES) */
1561 /* Offset of first parameter from the argument pointer register value.
1562 On the RS/6000, we define the argument pointer to the start of the fixed
1563 area. */
1564 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1566 /* Offset from the argument pointer register value to the top of
1567 stack. This is different from FIRST_PARM_OFFSET because of the
1568 register save area. */
1569 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1571 /* Define this if stack space is still allocated for a parameter passed
1572 in a register. The value is the number of bytes allocated to this
1573 area. */
1574 #define REG_PARM_STACK_SPACE(FNDECL) \
1575 rs6000_reg_parm_stack_space ((FNDECL), false)
1577 /* Define this macro if space guaranteed when compiling a function body
1578 is different to space required when making a call, a situation that
1579 can arise with K&R style function definitions. */
1580 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1581 rs6000_reg_parm_stack_space ((FNDECL), true)
1583 /* Define this if the above stack space is to be considered part of the
1584 space allocated by the caller. */
1585 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1587 /* This is the difference between the logical top of stack and the actual sp.
1589 For the RS/6000, sp points past the fixed area. */
1590 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1592 /* Define this if the maximum size of all the outgoing args is to be
1593 accumulated and pushed during the prologue. The amount can be
1594 found in the variable crtl->outgoing_args_size. */
1595 #define ACCUMULATE_OUTGOING_ARGS 1
1597 /* Define how to find the value returned by a library function
1598 assuming the value has mode MODE. */
1600 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1602 /* DRAFT_V4_STRUCT_RET defaults off. */
1603 #define DRAFT_V4_STRUCT_RET 0
1605 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1606 #define DEFAULT_PCC_STRUCT_RETURN 0
1608 /* Mode of stack savearea.
1609 FUNCTION is VOIDmode because calling convention maintains SP.
1610 BLOCK needs Pmode for SP.
1611 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1612 #define STACK_SAVEAREA_MODE(LEVEL) \
1613 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1614 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1616 /* Minimum and maximum general purpose registers used to hold arguments. */
1617 #define GP_ARG_MIN_REG 3
1618 #define GP_ARG_MAX_REG 10
1619 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1621 /* Minimum and maximum floating point registers used to hold arguments. */
1622 #define FP_ARG_MIN_REG 33
1623 #define FP_ARG_AIX_MAX_REG 45
1624 #define FP_ARG_V4_MAX_REG 40
1625 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1626 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1627 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1629 /* Minimum and maximum AltiVec registers used to hold arguments. */
1630 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1631 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1632 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1634 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1635 #define AGGR_ARG_NUM_REG 8
1637 /* Return registers */
1638 #define GP_ARG_RETURN GP_ARG_MIN_REG
1639 #define FP_ARG_RETURN FP_ARG_MIN_REG
1640 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1641 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1642 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1643 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1644 ? (ALTIVEC_ARG_RETURN \
1645 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1646 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1648 /* Flags for the call/call_value rtl operations set up by function_arg */
1650 /* Bits in 0x00000001 are unused. */
1656 /* We don't have prologue and epilogue functions to save/restore
1657 everything for most ABIs. */
1658 #define WORLD_SAVE_P(INFO) 0
1660 /* 1 if N is a possible register number for a function value
1661 as seen by the caller.
1663 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1664 #define FUNCTION_VALUE_REGNO_P(N) \
1665 ((N) == GP_ARG_RETURN \
1666 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1667 && TARGET_HARD_FLOAT && TARGET_FPRS) \
1668 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1669 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1671 /* 1 if N is a possible register number for function argument passing.
1672 On RS/6000, these are r3-r10 and fp1-fp13.
1673 On AltiVec, v2 - v13 are used for passing vectors. */
1674 #define FUNCTION_ARG_REGNO_P(N) \
1675 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1676 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1677 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1678 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1679 && TARGET_HARD_FLOAT && TARGET_FPRS))
1680 \f
1681 /* Define a data type for recording info about an argument list
1682 during the scan of that argument list. This data type should
1683 hold all necessary information about the function itself
1684 and about the args processed so far, enough to enable macros
1685 such as FUNCTION_ARG to determine where the next arg should go.
1687 On the RS/6000, this is a structure. The first element is the number of
1688 total argument words, the second is used to store the next
1689 floating-point register number, and the third says how many more args we
1690 have prototype types for.
1692 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1693 the next available GP register, `fregno' is the next available FP
1694 register, and `words' is the number of words used on the stack.
1696 The varargs/stdarg support requires that this structure's size
1697 be a multiple of sizeof(int). */
1700 {
1712 GPR space (darwin64) */
1718 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1719 for a call to a function whose data type is FNTYPE.
1720 For a library call, FNTYPE is 0. */
1722 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1723 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1724 N_NAMED_ARGS, FNDECL, VOIDmode)
1726 /* Similar, but when scanning the definition of a procedure. We always
1727 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1729 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1730 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1731 1000, current_function_decl, VOIDmode)
1733 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1735 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1736 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1737 0, NULL_TREE, MODE)
1739 #define PAD_VARARGS_DOWN \
1740 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1742 /* Output assembler code to FILE to increment profiler label # LABELNO
1743 for profiling a function entry. */
1745 #define FUNCTION_PROFILER(FILE, LABELNO) \
1746 output_function_profiler ((FILE), (LABELNO));
1748 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1749 the stack pointer does not matter. No definition is equivalent to
1750 always zero.
1752 On the RS/6000, this is nonzero because we can restore the stack from
1753 its backpointer, which we maintain. */
1754 #define EXIT_IGNORE_STACK 1
1756 /* Define this macro as a C expression that is nonzero for registers
1757 that are used by the epilogue or the return' pattern. The stack
1758 and frame pointer registers are already be assumed to be used as
1759 needed. */
1761 #define EPILOGUE_USES(REGNO) \
1762 ((reload_completed && (REGNO) == LR_REGNO) \
1763 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1764 || (crtl->calls_eh_return \
1765 && TARGET_AIX \
1766 && (REGNO) == 2))
1768 \f
1769 /* Length in units of the trampoline for entering a nested function. */
1771 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1772 \f
1773 /* Definitions for __builtin_return_address and __builtin_frame_address.
1774 __builtin_return_address (0) should give link register (LR_REGNO), enable
1775 this. */
1776 /* This should be uncommented, so that the link register is used, but
1777 currently this would result in unmatched insns and spilling fixed
1778 registers so we'll leave it for another day. When these problems are
1779 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1780 (mrs) */
1781 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1783 /* Number of bytes into the frame return addresses can be found. See
1784 rs6000_stack_info in powerpcspe.c for more information on how the different
1785 abi's store the return address. */
1786 #define RETURN_ADDRESS_OFFSET \
1787 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1789 /* The current return address is in link register (65). The return address
1790 of anything farther back is accessed normally at an offset of 8 from the
1791 frame pointer. */
1792 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1793 (rs6000_return_addr (COUNT, FRAME))
1795 \f
1796 /* Definitions for register eliminations.
1798 We have two registers that can be eliminated on the RS/6000. First, the
1799 frame pointer register can often be eliminated in favor of the stack
1800 pointer register. Secondly, the argument pointer register can always be
1801 eliminated; it is replaced with either the stack or frame pointer.
1803 In addition, we use the elimination mechanism to see if r30 is needed
1804 Initially we assume that it isn't. If it is, we spill it. This is done
1805 by making it an eliminable register. We replace it with itself so that
1806 if it isn't needed, then existing uses won't be modified. */
1808 /* This is an array of structures. Each structure initializes one pair
1809 of eliminable registers. The "from" register number is given first,
1810 followed by "to". Eliminations of the same "from" register are listed
1811 in order of preference. */
1812 #define ELIMINABLE_REGS \
1813 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1814 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1815 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1816 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1817 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1818 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1820 /* Define the offset between two registers, one to be eliminated, and the other
1821 its replacement, at the start of a routine. */
1822 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1823 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1824 \f
1825 /* Addressing modes, and classification of registers for them. */
1827 #define HAVE_PRE_DECREMENT 1
1828 #define HAVE_PRE_INCREMENT 1
1829 #define HAVE_PRE_MODIFY_DISP 1
1830 #define HAVE_PRE_MODIFY_REG 1
1832 /* Macros to check register numbers against specific register classes. */
1834 /* These assume that REGNO is a hard or pseudo reg number.
1835 They give nonzero only if REGNO is a hard reg of the suitable class
1836 or a pseudo reg currently allocated to a suitable hard reg.
1837 Since they use reg_renumber, they are safe only once reg_renumber
1838 has been allocated, which happens in reginfo.c during register
1839 allocation. */
1841 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1842 ((REGNO) < FIRST_PSEUDO_REGISTER \
1843 ? (REGNO) <= 31 || (REGNO) == 67 \
1844 || (REGNO) == FRAME_POINTER_REGNUM \
1845 : (reg_renumber[REGNO] >= 0 \
1846 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1847 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1849 #define REGNO_OK_FOR_BASE_P(REGNO) \
1850 ((REGNO) < FIRST_PSEUDO_REGISTER \
1851 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1852 || (REGNO) == FRAME_POINTER_REGNUM \
1853 : (reg_renumber[REGNO] > 0 \
1854 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1855 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1857 /* Nonzero if X is a hard reg that can be used as an index
1858 or if it is a pseudo reg in the non-strict case. */
1859 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1860 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1861 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1863 /* Nonzero if X is a hard reg that can be used as a base reg
1864 or if it is a pseudo reg in the non-strict case. */
1865 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1866 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1867 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1869 \f
1870 /* Maximum number of registers that can appear in a valid memory address. */
1872 #define MAX_REGS_PER_ADDRESS 2
1874 /* Recognize any constant value that is a valid address. */
1876 #define CONSTANT_ADDRESS_P(X) \
1877 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1878 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1879 || GET_CODE (X) == HIGH)
1881 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1882 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1883 && EASY_VECTOR_15((n) >> 1) \
1884 && ((n) & 1) == 0)
1886 #define EASY_VECTOR_MSB(n,mode) \
1887 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1888 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1890 \f
1891 /* Try a machine-dependent way of reloading an illegitimate address
1892 operand. If we find one, push the reload and jump to WIN. This
1893 macro is used in only one place: `find_reloads_address' in reload.c.
1895 Implemented on rs6000 by rs6000_legitimize_reload_address.
1896 Note that (X) is evaluated twice; this is safe in current usage. */
1898 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1899 do { \
1900 int win; \
1901 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1902 (int)(TYPE), (IND_LEVELS), &win); \
1903 if ( win ) \
1904 goto WIN; \
1905 } while (0)
1907 #define FIND_BASE_TERM rs6000_find_base_term
1908 \f
1909 /* The register number of the register used to address a table of
1910 static data addresses in memory. In some cases this register is
1911 defined by a processor's "application binary interface" (ABI).
1912 When this macro is defined, RTL is generated for this register
1913 once, as with the stack pointer and frame pointer registers. If
1914 this macro is not defined, it is up to the machine-dependent files
1915 to allocate such a register (if necessary). */
1917 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1918 #define PIC_OFFSET_TABLE_REGNUM \
1919 (TARGET_TOC ? TOC_REGISTER \
1920 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1921 : INVALID_REGNUM)
1923 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1925 /* Define this macro if the register defined by
1926 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1927 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1929 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1931 /* A C expression that is nonzero if X is a legitimate immediate
1932 operand on the target machine when generating position independent
1933 code. You can assume that X satisfies `CONSTANT_P', so you need
1934 not check this. You can also assume FLAG_PIC is true, so you need
1935 not check it either. You need not define this macro if all
1936 constants (including `SYMBOL_REF') can be immediate operands when
1937 generating position independent code. */
1939 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1940 \f
1941 /* Define this if some processing needs to be done immediately before
1942 emitting code for an insn. */
1944 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1945 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
1947 /* Specify the machine mode that this machine uses
1948 for the index in the tablejump instruction. */
1949 #define CASE_VECTOR_MODE SImode
1951 /* Define as C expression which evaluates to nonzero if the tablejump
1952 instruction expects the table to contain offsets from the address of the
1953 table.
1954 Do not define this if the table should contain absolute addresses. */
1955 #define CASE_VECTOR_PC_RELATIVE 1
1957 /* Define this as 1 if `char' should by default be signed; else as 0. */
1958 #define DEFAULT_SIGNED_CHAR 0
1960 /* An integer expression for the size in bits of the largest integer machine
1961 mode that should actually be used. */
1963 /* Allow pairs of registers to be used, which is the intent of the default. */
1964 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1966 /* Max number of bytes we can move from memory to memory
1967 in one reasonably fast instruction. */
1968 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1969 #define MAX_MOVE_MAX 8
1971 /* Nonzero if access to memory by bytes is no faster than for words.
1972 Also nonzero if doing byte operations (specifically shifts) in registers
1973 is undesirable. */
1974 #define SLOW_BYTE_ACCESS 1
1976 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1977 will either zero-extend or sign-extend. The value of this macro should
1978 be the code that says which one of the two operations is implicitly
1979 done, UNKNOWN if none. */
1980 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1982 /* Define if loading short immediate values into registers sign extends. */
1983 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1984 \f
1985 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1986 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1987 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1989 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1990 zero. The hardware instructions added in Power9 and the sequences using
1991 popcount return 32 or 64. */
1992 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1993 (TARGET_CTZ || TARGET_POPCNTD \
1994 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1995 : ((VALUE) = -1, 2))
1997 /* Specify the machine mode that pointers have.
1998 After generation of rtl, the compiler makes no further distinction
1999 between pointers and any other objects of this machine mode. */
2001 #define Pmode rs6000_pmode
2003 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2004 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2006 /* Mode of a function address in a call instruction (for indexing purposes).
2007 Doesn't matter on RS/6000. */
2008 #define FUNCTION_MODE SImode
2010 /* Define this if addresses of constant functions
2011 shouldn't be put through pseudo regs where they can be cse'd.
2012 Desirable on machines where ordinary constants are expensive
2013 but a CALL with constant address is cheap. */
2014 #define NO_FUNCTION_CSE 1
2016 /* Define this to be nonzero if shift instructions ignore all but the low-order
2017 few bits.
2019 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2020 have been dropped from the PowerPC architecture. */
2021 #define SHIFT_COUNT_TRUNCATED 0
2023 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2024 should be adjusted to reflect any required changes. This macro is used when
2025 there is some systematic length adjustment required that would be difficult
2026 to express in the length attribute. */
2028 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2030 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2031 COMPARE, return the mode to be used for the comparison. For
2032 floating-point, CCFPmode should be used. CCUNSmode should be used
2033 for unsigned comparisons. CCEQmode should be used when we are
2034 doing an inequality comparison on the result of a
2035 comparison. CCmode should be used in all other cases. */
2037 #define SELECT_CC_MODE(OP,X,Y) \
2038 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2039 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2040 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2041 ? CCEQmode : CCmode))
2043 /* Can the condition code MODE be safely reversed? This is safe in
2044 all cases on this port, because at present it doesn't use the
2045 trapping FP comparisons (fcmpo). */
2046 #define REVERSIBLE_CC_MODE(MODE) 1
2048 /* Given a condition code and a mode, return the inverse condition. */
2049 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2051 \f
2052 /* Control the assembler format that we output. */
2054 /* A C string constant describing how to begin a comment in the target
2055 assembler language. The compiler assumes that the comment will end at
2056 the end of the line. */
2059 /* Flag to say the TOC is initialized */
2062 /* Macro to output a special constant pool entry. Go to WIN if we output
2063 it. Otherwise, it is written the usual way.
2065 On the RS/6000, toc entries are handled this way. */
2067 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2068 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2069 { \
2070 output_toc (FILE, X, LABELNO, MODE); \
2071 goto WIN; \
2072 } \
2073 }
2075 #ifdef HAVE_GAS_WEAK
2076 #define RS6000_WEAK 1
2077 #else
2078 #define RS6000_WEAK 0
2079 #endif
2081 #if RS6000_WEAK
2082 /* Used in lieu of ASM_WEAKEN_LABEL. */
2083 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2084 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
2085 #endif
2087 #if HAVE_GAS_WEAKREF
2088 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2089 do \
2090 { \
2092 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2094 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2095 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2096 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2097 { \
2099 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2101 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2102 } \
2104 } while (0)
2105 #endif
2107 /* This implements the `alias' attribute. */
2108 #undef ASM_OUTPUT_DEF_FROM_DECLS
2109 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2110 do \
2111 { \
2112 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2113 const char *name = IDENTIFIER_POINTER (TARGET); \
2114 if (TREE_CODE (DECL) == FUNCTION_DECL \
2115 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2116 { \
2117 if (TREE_PUBLIC (DECL)) \
2118 { \
2119 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2120 { \
2122 RS6000_OUTPUT_BASENAME (FILE, alias); \
2124 } \
2125 } \
2126 else if (TARGET_XCOFF) \
2127 { \
2128 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2129 { \
2131 RS6000_OUTPUT_BASENAME (FILE, alias); \
2134 RS6000_OUTPUT_BASENAME (FILE, alias); \
2136 } \
2137 } \
2139 RS6000_OUTPUT_BASENAME (FILE, alias); \
2141 RS6000_OUTPUT_BASENAME (FILE, name); \
2143 } \
2144 ASM_OUTPUT_DEF (FILE, alias, name); \
2145 } \
2146 while (0)
2148 #define TARGET_ASM_FILE_START rs6000_file_start
2150 /* Output to assembler file text saying following lines
2151 may contain character constants, extra white space, comments, etc. */
2155 /* Output to assembler file text saying following lines
2156 no longer contain unusual constructs. */
2160 /* How to refer to registers in assembler output.
2161 This sequence is indexed by compiler's hard-register-number (see above). */
2165 #define REGISTER_NAMES \
2166 { \
2199 \
2232 \
2237 \
2246 \
2248 \
2289 \
2322 }
2324 /* Table of additional register names to use in user input. */
2326 #define ADDITIONAL_REGISTER_NAMES \
2387 }
2389 /* This is how to output an element of a case-vector that is relative. */
2391 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2392 do { char buf[100]; \
2395 assemble_name (FILE, buf); \
2398 assemble_name (FILE, buf); \
2400 } while (0)
2402 /* This is how to output an assembler line
2403 that says to advance the location counter
2404 to a multiple of 2**LOG bytes. */
2406 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2407 if ((LOG) != 0) \
2410 /* How to align the given loop. */
2411 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2413 /* Alignment guaranteed by __builtin_malloc. */
2414 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2415 However, specifying the stronger guarantee currently leads to
2416 a regression in SPEC CPU2006 437.leslie3d. The stronger
2417 guarantee should be implemented here once that's fixed. */
2418 #define MALLOC_ABI_ALIGNMENT (64)
2420 /* Pick up the return address upon entry to a procedure. Used for
2421 dwarf2 unwind information. This also enables the table driven
2422 mechanism. */
2424 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2425 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2427 /* Describe how we implement __builtin_eh_return. */
2428 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2429 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2431 /* Print operand X (an rtx) in assembler syntax to file FILE.
2432 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2433 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2435 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2437 /* Define which CODE values are valid. */
2441 /* Print a memory address as an operand to reference that memory location. */
2443 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2445 /* For switching between functions with different target attributes. */
2446 #define SWITCHABLE_TARGET 1
2448 /* uncomment for disabling the corresponding default options */
2449 /* #define MACHINE_no_sched_interblock */
2450 /* #define MACHINE_no_sched_speculative */
2451 /* #define MACHINE_no_sched_speculative_load */
2453 /* General flags. */
2456 /* Classification of the builtin functions as to which switches enable the
2457 builtin, and what attributes it should have. We used to use the target
2458 flags macros, but we've run out of bits, so we now map the options into new
2459 settings used here. */
2461 /* Builtin attributes. */
2474 modifies global state. */
2476 state/mem and does
2477 not modify global state. */
2481 /* Miscellaneous information. */
2488 /* Convenience macros to document the instruction type. */
2492 /* Builtin targets. For now, we reuse the masks for those options that are in
2493 target flags, and pick three random bits for SPE, paired and ldbl128 which
2494 aren't in target_flags. */
2518 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2519 | RS6000_BTM_VSX \
2520 | RS6000_BTM_P8_VECTOR \
2521 | RS6000_BTM_P9_VECTOR \
2522 | RS6000_BTM_P9_MISC \
2523 | RS6000_BTM_MODULO \
2524 | RS6000_BTM_CRYPTO \
2525 | RS6000_BTM_FRE \
2526 | RS6000_BTM_FRES \
2527 | RS6000_BTM_FRSQRTE \
2528 | RS6000_BTM_FRSQRTES \
2529 | RS6000_BTM_HTM \
2530 | RS6000_BTM_POPCNTD \
2531 | RS6000_BTM_CELL \
2532 | RS6000_BTM_DFP \
2533 | RS6000_BTM_HARD_FLOAT \
2534 | RS6000_BTM_LDBL128 \
2535 | RS6000_BTM_FLOAT128)
2537 /* Define builtin enum index. */
2539 #undef RS6000_BUILTIN_0
2540 #undef RS6000_BUILTIN_1
2541 #undef RS6000_BUILTIN_2
2542 #undef RS6000_BUILTIN_3
2543 #undef RS6000_BUILTIN_A
2544 #undef RS6000_BUILTIN_D
2545 #undef RS6000_BUILTIN_E
2546 #undef RS6000_BUILTIN_H
2547 #undef RS6000_BUILTIN_P
2548 #undef RS6000_BUILTIN_Q
2549 #undef RS6000_BUILTIN_S
2550 #undef RS6000_BUILTIN_X
2552 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2553 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2554 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2555 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2556 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2557 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2558 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2559 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2560 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2561 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2562 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2563 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2565 enum rs6000_builtins
2566 {
2569 RS6000_BUILTIN_COUNT
2570 };
2572 #undef RS6000_BUILTIN_0
2573 #undef RS6000_BUILTIN_1
2574 #undef RS6000_BUILTIN_2
2575 #undef RS6000_BUILTIN_3
2576 #undef RS6000_BUILTIN_A
2577 #undef RS6000_BUILTIN_D
2578 #undef RS6000_BUILTIN_E
2579 #undef RS6000_BUILTIN_H
2580 #undef RS6000_BUILTIN_P
2581 #undef RS6000_BUILTIN_Q
2582 #undef RS6000_BUILTIN_S
2583 #undef RS6000_BUILTIN_X
2585 enum rs6000_builtin_type_index
2586 {
2587 RS6000_BTI_NOT_OPAQUE,
2588 RS6000_BTI_opaque_V2SI,
2589 RS6000_BTI_opaque_V2SF,
2590 RS6000_BTI_opaque_p_V2SI,
2591 RS6000_BTI_opaque_V4SI,
2592 RS6000_BTI_V16QI,
2593 RS6000_BTI_V1TI,
2594 RS6000_BTI_V2SI,
2595 RS6000_BTI_V2SF,
2596 RS6000_BTI_V2DI,
2597 RS6000_BTI_V2DF,
2598 RS6000_BTI_V4HI,
2599 RS6000_BTI_V4SI,
2600 RS6000_BTI_V4SF,
2601 RS6000_BTI_V8HI,
2602 RS6000_BTI_unsigned_V16QI,
2603 RS6000_BTI_unsigned_V1TI,
2604 RS6000_BTI_unsigned_V8HI,
2605 RS6000_BTI_unsigned_V4SI,
2606 RS6000_BTI_unsigned_V2DI,
2640 RS6000_BTI_MAX
2641 };
2644 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2645 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2646 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2647 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2648 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2649 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2650 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2651 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2652 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2653 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2654 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2655 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2656 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2657 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2658 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2659 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2660 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2661 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2662 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2663 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2664 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2665 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2666 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2667 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2668 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2669 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2670 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2671 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2672 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2674 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2675 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2676 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2677 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2678 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2679 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2680 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2681 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2682 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2683 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2684 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2685 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2686 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2687 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2688 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2689 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2690 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2691 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2692 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2693 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2694 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2695 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2696 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2701 #define TARGET_SUPPORTS_WIDE_INT 1
2703 #if (GCC_VERSION >= 3000)
2704 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2705 #endif