1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((unsigned int *,
344 static void init_reg_last_arrays
PARAMS ((void));
345 static void setup_incoming_promotions
PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
347 static int cant_combine_insn_p
PARAMS ((rtx
));
348 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
349 static int sets_function_arg_p
PARAMS ((rtx
));
350 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
351 static int contains_muldiv
PARAMS ((rtx
));
352 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
353 static void undo_all
PARAMS ((void));
354 static void undo_commit
PARAMS ((void));
355 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
356 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
357 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
358 static rtx simplify_if_then_else
PARAMS ((rtx
));
359 static rtx simplify_set
PARAMS ((rtx
));
360 static rtx simplify_logical
PARAMS ((rtx
, int));
361 static rtx expand_compound_operation
PARAMS ((rtx
));
362 static rtx expand_field_assignment
PARAMS ((rtx
));
363 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
364 rtx
, unsigned HOST_WIDE_INT
, int,
366 static rtx extract_left_shift
PARAMS ((rtx
, int));
367 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
368 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
369 unsigned HOST_WIDE_INT
*));
370 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
371 unsigned HOST_WIDE_INT
, rtx
, int));
372 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
373 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
374 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
375 static rtx make_field_assignment
PARAMS ((rtx
));
376 static rtx apply_distributive_law
PARAMS ((rtx
));
377 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
378 unsigned HOST_WIDE_INT
));
379 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
380 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
381 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
382 enum rtx_code
, HOST_WIDE_INT
,
383 enum machine_mode
, int *));
384 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
386 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
387 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
388 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
390 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
391 static void update_table_tick
PARAMS ((rtx
));
392 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
393 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
394 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
395 static void record_dead_and_set_regs
PARAMS ((rtx
));
396 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
397 static rtx get_last_value
PARAMS ((rtx
));
398 static int use_crosses_set_p
PARAMS ((rtx
, int));
399 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
400 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
401 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
402 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
403 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
404 static void distribute_links
PARAMS ((rtx
));
405 static void mark_used_regs_combine
PARAMS ((rtx
));
406 static int insn_cuid
PARAMS ((rtx
));
407 static void record_promoted_value
PARAMS ((rtx
, rtx
));
408 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
409 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into
, newval
)
424 if (oldval
== newval
)
428 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
430 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
434 buf
->old_contents
.r
= oldval
;
437 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into
, newval
)
448 unsigned int *into
, newval
;
451 unsigned int oldval
= *into
;
453 if (oldval
== newval
)
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.i
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f
, nregs
)
481 register rtx insn
, next
;
486 register rtx links
, nextlinks
;
488 int new_direct_jump_p
= 0;
490 combine_attempts
= 0;
493 combine_successes
= 0;
495 combine_max_regno
= nregs
;
497 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
498 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
500 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
502 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
503 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
506 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
509 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs
* sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
522 if (INSN_UID (insn
) > i
)
525 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
528 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid
= 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn
= NULL_RTX
;
552 setup_incoming_promotions ();
554 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
555 sbitmap_zero (refresh_blocks
);
558 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
560 uid_cuid
[INSN_UID (insn
)] = ++i
;
566 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
568 record_dead_and_set_regs (insn
);
571 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
572 if (REG_NOTE_KIND (links
) == REG_INC
)
573 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
578 if (GET_CODE (insn
) == CODE_LABEL
)
582 nonzero_sign_valid
= 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block
= -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block
+ 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
602 if (GET_CODE (insn
) == CODE_LABEL
)
605 else if (INSN_P (insn
))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn
, PATTERN (insn
));
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0),
615 NULL_RTX
, &new_direct_jump_p
)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
622 rtx link
= XEXP (links
, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in persuing this chain any further. */
626 if (GET_CODE (link
) == NOTE
)
629 for (nextlinks
= LOG_LINKS (link
);
631 nextlinks
= XEXP (nextlinks
, 1))
632 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 &new_direct_jump_p
)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn
) == JUMP_INSN
647 && (prev
= prev_nonnote_insn (insn
)) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
)))
651 if ((next
= try_combine (insn
, prev
,
652 NULL_RTX
, &new_direct_jump_p
)) != 0)
655 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, prev
,
659 &new_direct_jump_p
)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn
) == INSN
665 && (prev
= prev_nonnote_insn (insn
)) != 0
666 && GET_CODE (prev
) == INSN
667 && sets_cc0_p (PATTERN (prev
))
668 && GET_CODE (PATTERN (insn
)) == SET
669 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
671 if ((next
= try_combine (insn
, prev
,
672 NULL_RTX
, &new_direct_jump_p
)) != 0)
675 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
676 nextlinks
= XEXP (nextlinks
, 1))
677 if ((next
= try_combine (insn
, prev
,
679 &new_direct_jump_p
)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
687 if (GET_CODE (XEXP (links
, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
689 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
690 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && (next
= try_combine (insn
, XEXP (links
, 0),
694 prev
, &new_direct_jump_p
)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 for (nextlinks
= XEXP (links
, 1); nextlinks
;
702 nextlinks
= XEXP (nextlinks
, 1))
703 if ((next
= try_combine (insn
, XEXP (links
, 0),
705 &new_direct_jump_p
)) != 0)
708 if (GET_CODE (insn
) != NOTE
)
709 record_dead_and_set_regs (insn
);
718 compute_bb_for_insn (get_max_uid ());
719 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
724 sbitmap_free (refresh_blocks
);
725 free (reg_nonzero_bits
);
726 free (reg_sign_bit_copies
);
727 free (reg_last_death
);
729 free (reg_last_set_value
);
730 free (reg_last_set_table_tick
);
731 free (reg_last_set_label
);
732 free (reg_last_set_invalid
);
733 free (reg_last_set_mode
);
734 free (reg_last_set_nonzero_bits
);
735 free (reg_last_set_sign_bit_copies
);
739 struct undo
*undo
, *next
;
740 for (undo
= undobuf
.frees
; undo
; undo
= next
)
748 total_attempts
+= combine_attempts
;
749 total_merges
+= combine_merges
;
750 total_extras
+= combine_extras
;
751 total_successes
+= combine_successes
;
753 nonzero_sign_valid
= 0;
755 /* Make recognizer allow volatile MEMs again. */
758 return new_direct_jump_p
;
761 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
764 init_reg_last_arrays ()
766 unsigned int nregs
= combine_max_regno
;
768 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
769 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
770 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
771 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
772 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
773 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
774 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
775 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
776 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
779 /* Set up any promoted values for incoming argument registers. */
782 setup_incoming_promotions ()
784 #ifdef PROMOTE_FUNCTION_ARGS
787 enum machine_mode mode
;
789 rtx first
= get_insns ();
791 #ifndef OUTGOING_REGNO
792 #define OUTGOING_REGNO(N) N
794 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
795 /* Check whether this register can hold an incoming pointer
796 argument. FUNCTION_ARG_REGNO_P tests outgoing register
797 numbers, so translate if necessary due to register windows. */
798 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
799 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
802 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
805 gen_rtx_CLOBBER (mode
, const0_rtx
)));
810 /* Called via note_stores. If X is a pseudo that is narrower than
811 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
813 If we are setting only a portion of X and we can't figure out what
814 portion, assume all bits will be used since we don't know what will
817 Similarly, set how many bits of X are known to be copies of the sign bit
818 at all locations in the function. This is the smallest number implied
822 set_nonzero_bits_and_sign_copies (x
, set
, data
)
825 void *data ATTRIBUTE_UNUSED
;
829 if (GET_CODE (x
) == REG
830 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
831 /* If this register is undefined at the start of the file, we can't
832 say what its contents were. */
833 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
834 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
836 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
838 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
839 reg_sign_bit_copies
[REGNO (x
)] = 1;
843 /* If this is a complex assignment, see if we can convert it into a
844 simple assignment. */
845 set
= expand_field_assignment (set
);
847 /* If this is a simple assignment, or we have a paradoxical SUBREG,
848 set what we know about X. */
850 if (SET_DEST (set
) == x
851 || (GET_CODE (SET_DEST (set
)) == SUBREG
852 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
853 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
854 && SUBREG_REG (SET_DEST (set
)) == x
))
856 rtx src
= SET_SRC (set
);
858 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
859 /* If X is narrower than a word and SRC is a non-negative
860 constant that would appear negative in the mode of X,
861 sign-extend it for use in reg_nonzero_bits because some
862 machines (maybe most) will actually do the sign-extension
863 and this is the conservative approach.
865 ??? For 2.5, try to tighten up the MD files in this regard
866 instead of this kludge. */
868 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
869 && GET_CODE (src
) == CONST_INT
871 && 0 != (INTVAL (src
)
873 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
874 src
= GEN_INT (INTVAL (src
)
875 | ((HOST_WIDE_INT
) (-1)
876 << GET_MODE_BITSIZE (GET_MODE (x
))));
879 reg_nonzero_bits
[REGNO (x
)]
880 |= nonzero_bits (src
, nonzero_bits_mode
);
881 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
882 if (reg_sign_bit_copies
[REGNO (x
)] == 0
883 || reg_sign_bit_copies
[REGNO (x
)] > num
)
884 reg_sign_bit_copies
[REGNO (x
)] = num
;
888 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
889 reg_sign_bit_copies
[REGNO (x
)] = 1;
894 /* See if INSN can be combined into I3. PRED and SUCC are optionally
895 insns that were previously combined into I3 or that will be combined
896 into the merger of INSN and I3.
898 Return 0 if the combination is not allowed for any reason.
900 If the combination is allowed, *PDEST will be set to the single
901 destination of INSN and *PSRC to the single source, and this function
905 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
908 rtx pred ATTRIBUTE_UNUSED
;
913 rtx set
= 0, src
, dest
;
918 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
919 && next_active_insn (succ
) == i3
)
920 : next_active_insn (insn
) == i3
);
922 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
923 or a PARALLEL consisting of such a SET and CLOBBERs.
925 If INSN has CLOBBER parallel parts, ignore them for our processing.
926 By definition, these happen during the execution of the insn. When it
927 is merged with another insn, all bets are off. If they are, in fact,
928 needed and aren't also supplied in I3, they may be added by
929 recog_for_combine. Otherwise, it won't match.
931 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
934 Get the source and destination of INSN. If more than one, can't
937 if (GET_CODE (PATTERN (insn
)) == SET
)
938 set
= PATTERN (insn
);
939 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
940 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
942 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
944 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
946 switch (GET_CODE (elt
))
948 /* This is important to combine floating point insns
951 /* Combining an isolated USE doesn't make sense.
952 We depend here on combinable_i3_pat to reject them. */
953 /* The code below this loop only verifies that the inputs of
954 the SET in INSN do not change. We call reg_set_between_p
955 to verify that the REG in the USE does not change betweeen
957 If the USE in INSN was for a pseudo register, the matching
958 insn pattern will likely match any register; combining this
959 with any other USE would only be safe if we knew that the
960 used registers have identical values, or if there was
961 something to tell them apart, e.g. different modes. For
962 now, we forgo such compilcated tests and simply disallow
963 combining of USES of pseudo registers with any other USE. */
964 if (GET_CODE (XEXP (elt
, 0)) == REG
965 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
967 rtx i3pat
= PATTERN (i3
);
968 int i
= XVECLEN (i3pat
, 0) - 1;
969 unsigned int regno
= REGNO (XEXP (elt
, 0));
973 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
975 if (GET_CODE (i3elt
) == USE
976 && GET_CODE (XEXP (i3elt
, 0)) == REG
977 && (REGNO (XEXP (i3elt
, 0)) == regno
978 ? reg_set_between_p (XEXP (elt
, 0),
979 PREV_INSN (insn
), i3
)
980 : regno
>= FIRST_PSEUDO_REGISTER
))
987 /* We can ignore CLOBBERs. */
992 /* Ignore SETs whose result isn't used but not those that
993 have side-effects. */
994 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
995 && ! side_effects_p (elt
))
998 /* If we have already found a SET, this is a second one and
999 so we cannot combine with this insn. */
1007 /* Anything else means we can't combine. */
1013 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1014 so don't do anything with it. */
1015 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1024 set
= expand_field_assignment (set
);
1025 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1027 /* Don't eliminate a store in the stack pointer. */
1028 if (dest
== stack_pointer_rtx
1029 /* If we couldn't eliminate a field assignment, we can't combine. */
1030 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1031 /* Don't combine with an insn that sets a register to itself if it has
1032 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1033 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1034 /* Can't merge an ASM_OPERANDS. */
1035 || GET_CODE (src
) == ASM_OPERANDS
1036 /* Can't merge a function call. */
1037 || GET_CODE (src
) == CALL
1038 /* Don't eliminate a function call argument. */
1039 || (GET_CODE (i3
) == CALL_INSN
1040 && (find_reg_fusage (i3
, USE
, dest
)
1041 || (GET_CODE (dest
) == REG
1042 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1043 && global_regs
[REGNO (dest
)])))
1044 /* Don't substitute into an incremented register. */
1045 || FIND_REG_INC_NOTE (i3
, dest
)
1046 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1048 /* Don't combine the end of a libcall into anything. */
1049 /* ??? This gives worse code, and appears to be unnecessary, since no
1050 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1051 use REG_RETVAL notes for noconflict blocks, but other code here
1052 makes sure that those insns don't disappear. */
1053 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1055 /* Make sure that DEST is not used after SUCC but before I3. */
1056 || (succ
&& ! all_adjacent
1057 && reg_used_between_p (dest
, succ
, i3
))
1058 /* Make sure that the value that is to be substituted for the register
1059 does not use any registers whose values alter in between. However,
1060 If the insns are adjacent, a use can't cross a set even though we
1061 think it might (this can happen for a sequence of insns each setting
1062 the same destination; reg_last_set of that register might point to
1063 a NOTE). If INSN has a REG_EQUIV note, the register is always
1064 equivalent to the memory so the substitution is valid even if there
1065 are intervening stores. Also, don't move a volatile asm or
1066 UNSPEC_VOLATILE across any other insns. */
1068 && (((GET_CODE (src
) != MEM
1069 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1070 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1071 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1072 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1073 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1074 better register allocation by not doing the combine. */
1075 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1076 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1077 /* Don't combine across a CALL_INSN, because that would possibly
1078 change whether the life span of some REGs crosses calls or not,
1079 and it is a pain to update that information.
1080 Exception: if source is a constant, moving it later can't hurt.
1081 Accept that special case, because it helps -fforce-addr a lot. */
1082 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1085 /* DEST must either be a REG or CC0. */
1086 if (GET_CODE (dest
) == REG
)
1088 /* If register alignment is being enforced for multi-word items in all
1089 cases except for parameters, it is possible to have a register copy
1090 insn referencing a hard register that is not allowed to contain the
1091 mode being copied and which would not be valid as an operand of most
1092 insns. Eliminate this problem by not combining with such an insn.
1094 Also, on some machines we don't want to extend the life of a hard
1097 if (GET_CODE (src
) == REG
1098 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1099 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1100 /* Don't extend the life of a hard register unless it is
1101 user variable (if we have few registers) or it can't
1102 fit into the desired register (meaning something special
1104 Also avoid substituting a return register into I3, because
1105 reload can't handle a conflict with constraints of other
1107 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1108 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1111 else if (GET_CODE (dest
) != CC0
)
1114 /* Don't substitute for a register intended as a clobberable operand.
1115 Similarly, don't substitute an expression containing a register that
1116 will be clobbered in I3. */
1117 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1118 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1119 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1120 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1122 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1125 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1126 or not), reject, unless nothing volatile comes between it and I3 */
1128 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1130 /* Make sure succ doesn't contain a volatile reference. */
1131 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1134 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1135 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1139 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1140 to be an explicit register variable, and was chosen for a reason. */
1142 if (GET_CODE (src
) == ASM_OPERANDS
1143 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1146 /* If there are any volatile insns between INSN and I3, reject, because
1147 they might affect machine state. */
1149 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1150 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1153 /* If INSN or I2 contains an autoincrement or autodecrement,
1154 make sure that register is not used between there and I3,
1155 and not already used in I3 either.
1156 Also insist that I3 not be a jump; if it were one
1157 and the incremented register were spilled, we would lose. */
1160 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1161 if (REG_NOTE_KIND (link
) == REG_INC
1162 && (GET_CODE (i3
) == JUMP_INSN
1163 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1164 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1169 /* Don't combine an insn that follows a CC0-setting insn.
1170 An insn that uses CC0 must not be separated from the one that sets it.
1171 We do, however, allow I2 to follow a CC0-setting insn if that insn
1172 is passed as I1; in that case it will be deleted also.
1173 We also allow combining in this case if all the insns are adjacent
1174 because that would leave the two CC0 insns adjacent as well.
1175 It would be more logical to test whether CC0 occurs inside I1 or I2,
1176 but that would be much slower, and this ought to be equivalent. */
1178 p
= prev_nonnote_insn (insn
);
1179 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1184 /* If we get here, we have passed all the tests and the combination is
1193 /* Check if PAT is an insn - or a part of it - used to set up an
1194 argument for a function in a hard register. */
1197 sets_function_arg_p (pat
)
1203 switch (GET_CODE (pat
))
1206 return sets_function_arg_p (PATTERN (pat
));
1209 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1210 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1216 inner_dest
= SET_DEST (pat
);
1217 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1218 || GET_CODE (inner_dest
) == SUBREG
1219 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1220 inner_dest
= XEXP (inner_dest
, 0);
1222 return (GET_CODE (inner_dest
) == REG
1223 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1224 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1233 /* LOC is the location within I3 that contains its pattern or the component
1234 of a PARALLEL of the pattern. We validate that it is valid for combining.
1236 One problem is if I3 modifies its output, as opposed to replacing it
1237 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1238 so would produce an insn that is not equivalent to the original insns.
1242 (set (reg:DI 101) (reg:DI 100))
1243 (set (subreg:SI (reg:DI 101) 0) <foo>)
1245 This is NOT equivalent to:
1247 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1248 (set (reg:DI 101) (reg:DI 100))])
1250 Not only does this modify 100 (in which case it might still be valid
1251 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1253 We can also run into a problem if I2 sets a register that I1
1254 uses and I1 gets directly substituted into I3 (not via I2). In that
1255 case, we would be getting the wrong value of I2DEST into I3, so we
1256 must reject the combination. This case occurs when I2 and I1 both
1257 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1258 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1259 of a SET must prevent combination from occurring.
1261 Before doing the above check, we first try to expand a field assignment
1262 into a set of logical operations.
1264 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1265 we place a register that is both set and used within I3. If more than one
1266 such register is detected, we fail.
1268 Return 1 if the combination is valid, zero otherwise. */
1271 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1277 rtx
*pi3dest_killed
;
1281 if (GET_CODE (x
) == SET
)
1283 rtx set
= expand_field_assignment (x
);
1284 rtx dest
= SET_DEST (set
);
1285 rtx src
= SET_SRC (set
);
1286 rtx inner_dest
= dest
;
1289 rtx inner_src
= src
;
1294 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1295 || GET_CODE (inner_dest
) == SUBREG
1296 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1297 inner_dest
= XEXP (inner_dest
, 0);
1299 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1302 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1303 || GET_CODE (inner_src
) == SUBREG
1304 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1305 inner_src
= XEXP (inner_src
, 0);
1307 /* If it is better that two different modes keep two different pseudos,
1308 avoid combining them. This avoids producing the following pattern
1310 (set (subreg:SI (reg/v:QI 21) 0)
1311 (lshiftrt:SI (reg/v:SI 20)
1313 If that were made, reload could not handle the pair of
1314 reg 20/21, since it would try to get any GENERAL_REGS
1315 but some of them don't handle QImode. */
1317 if (rtx_equal_p (inner_src
, i2dest
)
1318 && GET_CODE (inner_dest
) == REG
1319 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1323 /* Check for the case where I3 modifies its output, as
1325 if ((inner_dest
!= dest
1326 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1327 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1329 /* This is the same test done in can_combine_p except we can't test
1330 all_adjacent; we don't have to, since this instruction will stay
1331 in place, thus we are not considering increasing the lifetime of
1334 Also, if this insn sets a function argument, combining it with
1335 something that might need a spill could clobber a previous
1336 function argument; the all_adjacent test in can_combine_p also
1337 checks this; here, we do a more specific test for this case. */
1339 || (GET_CODE (inner_dest
) == REG
1340 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1341 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1342 GET_MODE (inner_dest
))))
1343 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1346 /* If DEST is used in I3, it is being killed in this insn,
1347 so record that for later.
1348 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1349 STACK_POINTER_REGNUM, since these are always considered to be
1350 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1351 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1352 && reg_referenced_p (dest
, PATTERN (i3
))
1353 && REGNO (dest
) != FRAME_POINTER_REGNUM
1354 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1355 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1357 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1358 && (REGNO (dest
) != ARG_POINTER_REGNUM
1359 || ! fixed_regs
[REGNO (dest
)])
1361 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1363 if (*pi3dest_killed
)
1366 *pi3dest_killed
= dest
;
1370 else if (GET_CODE (x
) == PARALLEL
)
1374 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1375 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1376 i1_not_in_src
, pi3dest_killed
))
1383 /* Return 1 if X is an arithmetic expression that contains a multiplication
1384 and division. We don't count multiplications by powers of two here. */
1390 switch (GET_CODE (x
))
1392 case MOD
: case DIV
: case UMOD
: case UDIV
:
1396 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1397 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1399 switch (GET_RTX_CLASS (GET_CODE (x
)))
1401 case 'c': case '<': case '2':
1402 return contains_muldiv (XEXP (x
, 0))
1403 || contains_muldiv (XEXP (x
, 1));
1406 return contains_muldiv (XEXP (x
, 0));
1414 /* Determine whether INSN can be used in a combination. Return nonzero if
1415 not. This is used in try_combine to detect early some cases where we
1416 can't perform combinations. */
1419 cant_combine_insn_p (insn
)
1425 /* If this isn't really an insn, we can't do anything.
1426 This can occur when flow deletes an insn that it has merged into an
1427 auto-increment address. */
1428 if (! INSN_P (insn
))
1431 /* Never combine loads and stores involving hard regs. The register
1432 allocator can usually handle such reg-reg moves by tying. If we allow
1433 the combiner to make substitutions of hard regs, we risk aborting in
1434 reload on machines that have SMALL_REGISTER_CLASSES.
1435 As an exception, we allow combinations involving fixed regs; these are
1436 not available to the register allocator so there's no risk involved. */
1438 set
= single_set (insn
);
1441 src
= SET_SRC (set
);
1442 dest
= SET_DEST (set
);
1443 if (GET_CODE (src
) == SUBREG
)
1444 src
= SUBREG_REG (src
);
1445 if (GET_CODE (dest
) == SUBREG
)
1446 dest
= SUBREG_REG (dest
);
1447 if (REG_P (src
) && REG_P (dest
)
1448 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1449 && ! fixed_regs
[REGNO (src
)])
1450 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1451 && ! fixed_regs
[REGNO (dest
)])))
1457 /* Try to combine the insns I1 and I2 into I3.
1458 Here I1 and I2 appear earlier than I3.
1459 I1 can be zero; then we combine just I2 into I3.
1461 If we are combining three insns and the resulting insn is not recognized,
1462 try splitting it into two insns. If that happens, I2 and I3 are retained
1463 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1466 Return 0 if the combination does not work. Then nothing is changed.
1467 If we did the combination, return the insn at which combine should
1470 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1471 new direct jump instruction. */
1474 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1475 register rtx i3
, i2
, i1
;
1476 register int *new_direct_jump_p
;
1478 /* New patterns for I3 and I2, respectively. */
1479 rtx newpat
, newi2pat
= 0;
1480 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1481 int added_sets_1
, added_sets_2
;
1482 /* Total number of SETs to put into I3. */
1484 /* Nonzero is I2's body now appears in I3. */
1486 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1487 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1488 /* Contains I3 if the destination of I3 is used in its source, which means
1489 that the old life of I3 is being killed. If that usage is placed into
1490 I2 and not in I3, a REG_DEAD note must be made. */
1491 rtx i3dest_killed
= 0;
1492 /* SET_DEST and SET_SRC of I2 and I1. */
1493 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1494 /* PATTERN (I2), or a copy of it in certain cases. */
1496 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1497 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1498 int i1_feeds_i3
= 0;
1499 /* Notes that must be added to REG_NOTES in I3 and I2. */
1500 rtx new_i3_notes
, new_i2_notes
;
1501 /* Notes that we substituted I3 into I2 instead of the normal case. */
1502 int i3_subst_into_i2
= 0;
1503 /* Notes that I1, I2 or I3 is a MULT operation. */
1511 /* Exit early if one of the insns involved can't be used for
1513 if (cant_combine_insn_p (i3
)
1514 || cant_combine_insn_p (i2
)
1515 || (i1
&& cant_combine_insn_p (i1
))
1516 /* We also can't do anything if I3 has a
1517 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1520 /* ??? This gives worse code, and appears to be unnecessary, since no
1521 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1522 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1528 undobuf
.other_insn
= 0;
1530 /* Reset the hard register usage information. */
1531 CLEAR_HARD_REG_SET (newpat_used_regs
);
1533 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1534 code below, set I1 to be the earlier of the two insns. */
1535 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1536 temp
= i1
, i1
= i2
, i2
= temp
;
1538 added_links_insn
= 0;
1540 /* First check for one important special-case that the code below will
1541 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1542 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1543 we may be able to replace that destination with the destination of I3.
1544 This occurs in the common code where we compute both a quotient and
1545 remainder into a structure, in which case we want to do the computation
1546 directly into the structure to avoid register-register copies.
1548 Note that this case handles both multiple sets in I2 and also
1549 cases where I2 has a number of CLOBBER or PARALLELs.
1551 We make very conservative checks below and only try to handle the
1552 most common cases of this. For example, we only handle the case
1553 where I2 and I3 are adjacent to avoid making difficult register
1556 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1557 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1558 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1559 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1560 && GET_CODE (PATTERN (i2
)) == PARALLEL
1561 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1562 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1563 below would need to check what is inside (and reg_overlap_mentioned_p
1564 doesn't support those codes anyway). Don't allow those destinations;
1565 the resulting insn isn't likely to be recognized anyway. */
1566 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1567 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1568 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1569 SET_DEST (PATTERN (i3
)))
1570 && next_real_insn (i2
) == i3
)
1572 rtx p2
= PATTERN (i2
);
1574 /* Make sure that the destination of I3,
1575 which we are going to substitute into one output of I2,
1576 is not used within another output of I2. We must avoid making this:
1577 (parallel [(set (mem (reg 69)) ...)
1578 (set (reg 69) ...)])
1579 which is not well-defined as to order of actions.
1580 (Besides, reload can't handle output reloads for this.)
1582 The problem can also happen if the dest of I3 is a memory ref,
1583 if another dest in I2 is an indirect memory ref. */
1584 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1585 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1586 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1587 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1588 SET_DEST (XVECEXP (p2
, 0, i
))))
1591 if (i
== XVECLEN (p2
, 0))
1592 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1593 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1594 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1595 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1600 subst_low_cuid
= INSN_CUID (i2
);
1602 added_sets_2
= added_sets_1
= 0;
1603 i2dest
= SET_SRC (PATTERN (i3
));
1605 /* Replace the dest in I2 with our dest and make the resulting
1606 insn the new pattern for I3. Then skip to where we
1607 validate the pattern. Everything was set up above. */
1608 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1609 SET_DEST (PATTERN (i3
)));
1612 i3_subst_into_i2
= 1;
1613 goto validate_replacement
;
1617 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1618 one of those words to another constant, merge them by making a new
1621 && (temp
= single_set (i2
)) != 0
1622 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1623 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1624 && GET_CODE (SET_DEST (temp
)) == REG
1625 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1626 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1627 && GET_CODE (PATTERN (i3
)) == SET
1628 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1629 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1630 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1631 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1632 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1634 HOST_WIDE_INT lo
, hi
;
1636 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1637 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1640 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1641 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1644 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1646 /* We don't handle the case of the target word being wider
1647 than a host wide int. */
1648 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1651 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1652 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1654 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1655 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1656 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1658 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1659 >> (HOST_BITS_PER_WIDE_INT
- 1));
1661 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1662 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1663 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1664 (INTVAL (SET_SRC (PATTERN (i3
)))));
1666 hi
= lo
< 0 ? -1 : 0;
1669 /* We don't handle the case of the higher word not fitting
1670 entirely in either hi or lo. */
1675 subst_low_cuid
= INSN_CUID (i2
);
1676 added_sets_2
= added_sets_1
= 0;
1677 i2dest
= SET_DEST (temp
);
1679 SUBST (SET_SRC (temp
),
1680 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1682 newpat
= PATTERN (i2
);
1683 goto validate_replacement
;
1687 /* If we have no I1 and I2 looks like:
1688 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1690 make up a dummy I1 that is
1693 (set (reg:CC X) (compare:CC Y (const_int 0)))
1695 (We can ignore any trailing CLOBBERs.)
1697 This undoes a previous combination and allows us to match a branch-and-
1700 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1701 && XVECLEN (PATTERN (i2
), 0) >= 2
1702 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1703 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1705 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1706 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1707 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1708 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1709 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1710 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1712 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1713 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1718 /* We make I1 with the same INSN_UID as I2. This gives it
1719 the same INSN_CUID for value tracking. Our fake I1 will
1720 never appear in the insn stream so giving it the same INSN_UID
1721 as I2 will not cause a problem. */
1723 subst_prev_insn
= i1
1724 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1725 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1728 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1729 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1730 SET_DEST (PATTERN (i1
)));
1735 /* Verify that I2 and I1 are valid for combining. */
1736 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1737 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1743 /* Record whether I2DEST is used in I2SRC and similarly for the other
1744 cases. Knowing this will help in register status updating below. */
1745 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1746 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1747 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1749 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1751 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1753 /* Ensure that I3's pattern can be the destination of combines. */
1754 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1755 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1762 /* See if any of the insns is a MULT operation. Unless one is, we will
1763 reject a combination that is, since it must be slower. Be conservative
1765 if (GET_CODE (i2src
) == MULT
1766 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1767 || (GET_CODE (PATTERN (i3
)) == SET
1768 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1771 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1772 We used to do this EXCEPT in one case: I3 has a post-inc in an
1773 output operand. However, that exception can give rise to insns like
1775 which is a famous insn on the PDP-11 where the value of r3 used as the
1776 source was model-dependent. Avoid this sort of thing. */
1779 if (!(GET_CODE (PATTERN (i3
)) == SET
1780 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1781 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1782 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1783 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1784 /* It's not the exception. */
1787 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1788 if (REG_NOTE_KIND (link
) == REG_INC
1789 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1791 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1798 /* See if the SETs in I1 or I2 need to be kept around in the merged
1799 instruction: whenever the value set there is still needed past I3.
1800 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1802 For the SET in I1, we have two cases: If I1 and I2 independently
1803 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1804 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1805 in I1 needs to be kept around unless I1DEST dies or is set in either
1806 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1807 I1DEST. If so, we know I1 feeds into I2. */
1809 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1812 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1813 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1815 /* If the set in I2 needs to be kept around, we must make a copy of
1816 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1817 PATTERN (I2), we are only substituting for the original I1DEST, not into
1818 an already-substituted copy. This also prevents making self-referential
1819 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1822 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1823 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1827 i2pat
= copy_rtx (i2pat
);
1831 /* Substitute in the latest insn for the regs set by the earlier ones. */
1833 maxreg
= max_reg_num ();
1837 /* It is possible that the source of I2 or I1 may be performing an
1838 unneeded operation, such as a ZERO_EXTEND of something that is known
1839 to have the high part zero. Handle that case by letting subst look at
1840 the innermost one of them.
1842 Another way to do this would be to have a function that tries to
1843 simplify a single insn instead of merging two or more insns. We don't
1844 do this because of the potential of infinite loops and because
1845 of the potential extra memory required. However, doing it the way
1846 we are is a bit of a kludge and doesn't catch all cases.
1848 But only do this if -fexpensive-optimizations since it slows things down
1849 and doesn't usually win. */
1851 if (flag_expensive_optimizations
)
1853 /* Pass pc_rtx so no substitutions are done, just simplifications.
1854 The cases that we are interested in here do not involve the few
1855 cases were is_replaced is checked. */
1858 subst_low_cuid
= INSN_CUID (i1
);
1859 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1863 subst_low_cuid
= INSN_CUID (i2
);
1864 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1869 /* Many machines that don't use CC0 have insns that can both perform an
1870 arithmetic operation and set the condition code. These operations will
1871 be represented as a PARALLEL with the first element of the vector
1872 being a COMPARE of an arithmetic operation with the constant zero.
1873 The second element of the vector will set some pseudo to the result
1874 of the same arithmetic operation. If we simplify the COMPARE, we won't
1875 match such a pattern and so will generate an extra insn. Here we test
1876 for this case, where both the comparison and the operation result are
1877 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1878 I2SRC. Later we will make the PARALLEL that contains I2. */
1880 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1881 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1882 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1883 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1885 #ifdef EXTRA_CC_MODES
1887 enum machine_mode compare_mode
;
1890 newpat
= PATTERN (i3
);
1891 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1895 #ifdef EXTRA_CC_MODES
1896 /* See if a COMPARE with the operand we substituted in should be done
1897 with the mode that is currently being used. If not, do the same
1898 processing we do in `subst' for a SET; namely, if the destination
1899 is used only once, try to replace it with a register of the proper
1900 mode and also replace the COMPARE. */
1901 if (undobuf
.other_insn
== 0
1902 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1903 &undobuf
.other_insn
))
1904 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1906 != GET_MODE (SET_DEST (newpat
))))
1908 unsigned int regno
= REGNO (SET_DEST (newpat
));
1909 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1911 if (regno
< FIRST_PSEUDO_REGISTER
1912 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1913 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1915 if (regno
>= FIRST_PSEUDO_REGISTER
)
1916 SUBST (regno_reg_rtx
[regno
], new_dest
);
1918 SUBST (SET_DEST (newpat
), new_dest
);
1919 SUBST (XEXP (*cc_use
, 0), new_dest
);
1920 SUBST (SET_SRC (newpat
),
1921 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1924 undobuf
.other_insn
= 0;
1931 n_occurrences
= 0; /* `subst' counts here */
1933 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1934 need to make a unique copy of I2SRC each time we substitute it
1935 to avoid self-referential rtl. */
1937 subst_low_cuid
= INSN_CUID (i2
);
1938 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1939 ! i1_feeds_i3
&& i1dest_in_i1src
);
1941 /* Record whether i2's body now appears within i3's body. */
1942 i2_is_used
= n_occurrences
;
1945 /* If we already got a failure, don't try to do more. Otherwise,
1946 try to substitute in I1 if we have it. */
1948 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1950 /* Before we can do this substitution, we must redo the test done
1951 above (see detailed comments there) that ensures that I1DEST
1952 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1954 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1962 subst_low_cuid
= INSN_CUID (i1
);
1963 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1966 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1967 to count all the ways that I2SRC and I1SRC can be used. */
1968 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1969 && i2_is_used
+ added_sets_2
> 1)
1970 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1971 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1973 /* Fail if we tried to make a new register (we used to abort, but there's
1974 really no reason to). */
1975 || max_reg_num () != maxreg
1976 /* Fail if we couldn't do something and have a CLOBBER. */
1977 || GET_CODE (newpat
) == CLOBBER
1978 /* Fail if this new pattern is a MULT and we didn't have one before
1979 at the outer level. */
1980 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1987 /* If the actions of the earlier insns must be kept
1988 in addition to substituting them into the latest one,
1989 we must make a new PARALLEL for the latest insn
1990 to hold additional the SETs. */
1992 if (added_sets_1
|| added_sets_2
)
1996 if (GET_CODE (newpat
) == PARALLEL
)
1998 rtvec old
= XVEC (newpat
, 0);
1999 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2000 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2001 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2002 sizeof (old
->elem
[0]) * old
->num_elem
);
2007 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2008 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2009 XVECEXP (newpat
, 0, 0) = old
;
2013 XVECEXP (newpat
, 0, --total_sets
)
2014 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2015 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2019 /* If there is no I1, use I2's body as is. We used to also not do
2020 the subst call below if I2 was substituted into I3,
2021 but that could lose a simplification. */
2023 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2025 /* See comment where i2pat is assigned. */
2026 XVECEXP (newpat
, 0, --total_sets
)
2027 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2031 /* We come here when we are replacing a destination in I2 with the
2032 destination of I3. */
2033 validate_replacement
:
2035 /* Note which hard regs this insn has as inputs. */
2036 mark_used_regs_combine (newpat
);
2038 /* Is the result of combination a valid instruction? */
2039 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2041 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2042 the second SET's destination is a register that is unused. In that case,
2043 we just need the first SET. This can occur when simplifying a divmod
2044 insn. We *must* test for this case here because the code below that
2045 splits two independent SETs doesn't handle this case correctly when it
2046 updates the register status. Also check the case where the first
2047 SET's destination is unused. That would not cause incorrect code, but
2048 does cause an unneeded insn to remain. */
2050 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2051 && XVECLEN (newpat
, 0) == 2
2052 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2053 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2054 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2055 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2056 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2057 && asm_noperands (newpat
) < 0)
2059 newpat
= XVECEXP (newpat
, 0, 0);
2060 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2063 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2064 && XVECLEN (newpat
, 0) == 2
2065 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2066 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2067 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2068 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2069 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2070 && asm_noperands (newpat
) < 0)
2072 newpat
= XVECEXP (newpat
, 0, 1);
2073 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 /* If we were combining three insns and the result is a simple SET
2077 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2078 insns. There are two ways to do this. It can be split using a
2079 machine-specific method (like when you have an addition of a large
2080 constant) or by combine in the function find_split_point. */
2082 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2083 && asm_noperands (newpat
) < 0)
2085 rtx m_split
, *split
;
2086 rtx ni2dest
= i2dest
;
2088 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2089 use I2DEST as a scratch register will help. In the latter case,
2090 convert I2DEST to the mode of the source of NEWPAT if we can. */
2092 m_split
= split_insns (newpat
, i3
);
2094 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2095 inputs of NEWPAT. */
2097 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2098 possible to try that as a scratch reg. This would require adding
2099 more code to make it work though. */
2101 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2103 /* If I2DEST is a hard register or the only use of a pseudo,
2104 we can change its mode. */
2105 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2106 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2107 && GET_CODE (i2dest
) == REG
2108 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2109 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2110 && ! REG_USERVAR_P (i2dest
))))
2111 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2114 m_split
= split_insns (gen_rtx_PARALLEL
2116 gen_rtvec (2, newpat
,
2117 gen_rtx_CLOBBER (VOIDmode
,
2120 /* If the split with the mode-changed register didn't work, try
2121 the original register. */
2122 if (! m_split
&& ni2dest
!= i2dest
)
2125 m_split
= split_insns (gen_rtx_PARALLEL
2127 gen_rtvec (2, newpat
,
2128 gen_rtx_CLOBBER (VOIDmode
,
2134 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2136 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2137 if (insn_code_number
>= 0)
2140 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2141 && XVECLEN (m_split
, 0) == 2
2142 && (next_real_insn (i2
) == i3
2143 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2147 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2148 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2150 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2151 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2153 /* In case we changed the mode of I2DEST, replace it in the
2154 pseudo-register table here. We can't do it above in case this
2155 code doesn't get executed and we do a split the other way. */
2157 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2158 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2160 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2162 /* If I2 or I3 has multiple SETs, we won't know how to track
2163 register status, so don't use these insns. If I2's destination
2164 is used between I2 and I3, we also can't use these insns. */
2166 if (i2_code_number
>= 0 && i2set
&& i3set
2167 && (next_real_insn (i2
) == i3
2168 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2169 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2171 if (insn_code_number
>= 0)
2174 /* It is possible that both insns now set the destination of I3.
2175 If so, we must show an extra use of it. */
2177 if (insn_code_number
>= 0)
2179 rtx new_i3_dest
= SET_DEST (i3set
);
2180 rtx new_i2_dest
= SET_DEST (i2set
);
2182 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2183 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2184 || GET_CODE (new_i3_dest
) == SUBREG
)
2185 new_i3_dest
= XEXP (new_i3_dest
, 0);
2187 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2188 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2189 || GET_CODE (new_i2_dest
) == SUBREG
)
2190 new_i2_dest
= XEXP (new_i2_dest
, 0);
2192 if (GET_CODE (new_i3_dest
) == REG
2193 && GET_CODE (new_i2_dest
) == REG
2194 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2195 REG_N_SETS (REGNO (new_i2_dest
))++;
2199 /* If we can split it and use I2DEST, go ahead and see if that
2200 helps things be recognized. Verify that none of the registers
2201 are set between I2 and I3. */
2202 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2204 && GET_CODE (i2dest
) == REG
2206 /* We need I2DEST in the proper mode. If it is a hard register
2207 or the only use of a pseudo, we can change its mode. */
2208 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2209 || GET_MODE (*split
) == VOIDmode
2210 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2211 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2212 && ! REG_USERVAR_P (i2dest
)))
2213 && (next_real_insn (i2
) == i3
2214 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2215 /* We can't overwrite I2DEST if its value is still used by
2217 && ! reg_referenced_p (i2dest
, newpat
))
2219 rtx newdest
= i2dest
;
2220 enum rtx_code split_code
= GET_CODE (*split
);
2221 enum machine_mode split_mode
= GET_MODE (*split
);
2223 /* Get NEWDEST as a register in the proper mode. We have already
2224 validated that we can do this. */
2225 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2227 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2229 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2230 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2233 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2234 an ASHIFT. This can occur if it was inside a PLUS and hence
2235 appeared to be a memory address. This is a kludge. */
2236 if (split_code
== MULT
2237 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2238 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2240 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2241 XEXP (*split
, 0), GEN_INT (i
)));
2242 /* Update split_code because we may not have a multiply
2244 split_code
= GET_CODE (*split
);
2247 #ifdef INSN_SCHEDULING
2248 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2249 be written as a ZERO_EXTEND. */
2250 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2251 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2252 SUBREG_REG (*split
)));
2255 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2256 SUBST (*split
, newdest
);
2257 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2259 /* If the split point was a MULT and we didn't have one before,
2260 don't use one now. */
2261 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2262 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2266 /* Check for a case where we loaded from memory in a narrow mode and
2267 then sign extended it, but we need both registers. In that case,
2268 we have a PARALLEL with both loads from the same memory location.
2269 We can split this into a load from memory followed by a register-register
2270 copy. This saves at least one insn, more if register allocation can
2273 We cannot do this if the destination of the second assignment is
2274 a register that we have already assumed is zero-extended. Similarly
2275 for a SUBREG of such a register. */
2277 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2278 && GET_CODE (newpat
) == PARALLEL
2279 && XVECLEN (newpat
, 0) == 2
2280 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2281 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2282 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2290 (GET_CODE (temp
) == REG
2291 && reg_nonzero_bits
[REGNO (temp
)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits
[REGNO (temp
)]
2295 != GET_MODE_MASK (word_mode
))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2297 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2298 (GET_CODE (temp
) == REG
2299 && reg_nonzero_bits
[REGNO (temp
)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits
[REGNO (temp
)]
2303 != GET_MODE_MASK (word_mode
)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2305 SET_SRC (XVECEXP (newpat
, 0, 1)))
2306 && ! find_reg_note (i3
, REG_UNUSED
,
2307 SET_DEST (XVECEXP (newpat
, 0, 0))))
2311 newi2pat
= XVECEXP (newpat
, 0, 0);
2312 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2313 newpat
= XVECEXP (newpat
, 0, 1);
2314 SUBST (SET_SRC (newpat
),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2316 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2318 if (i2_code_number
>= 0)
2319 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2321 if (insn_code_number
>= 0)
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3
) = newpat
;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn
= NEXT_INSN (i3
);
2348 insn
&& (this_basic_block
== n_basic_blocks
- 1
2349 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2350 insn
= NEXT_INSN (insn
))
2352 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2354 for (link
= LOG_LINKS (insn
); link
;
2355 link
= XEXP (link
, 1))
2356 if (XEXP (link
, 0) == i3
)
2357 XEXP (link
, 0) = i1
;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2371 && GET_CODE (newpat
) == PARALLEL
2372 && XVECLEN (newpat
, 0) == 2
2373 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2385 XVECEXP (newpat
, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2387 XVECEXP (newpat
, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2395 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2397 newi2pat
= XVECEXP (newpat
, 0, 0);
2398 newpat
= XVECEXP (newpat
, 0, 1);
2403 newi2pat
= XVECEXP (newpat
, 0, 1);
2404 newpat
= XVECEXP (newpat
, 0, 0);
2407 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2409 if (i2_code_number
>= 0)
2410 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2413 /* If it still isn't recognized, fail and change things back the way they
2415 if ((insn_code_number
< 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf
.other_insn
)
2426 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2427 rtx new_other_notes
;
2430 CLEAR_HARD_REG_SET (newpat_used_regs
);
2432 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2435 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2441 PATTERN (undobuf
.other_insn
) = other_pat
;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2448 next
= XEXP (note
, 1);
2450 if (REG_NOTE_KIND (note
) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2453 if (GET_CODE (XEXP (note
, 0)) == REG
)
2454 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2456 remove_note (undobuf
.other_insn
, note
);
2460 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2461 if (GET_CODE (XEXP (note
, 0)) == REG
)
2462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2464 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2465 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p
= prev_nonnote_insn (i3
);
2472 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2473 && sets_cc0_p (newi2pat
))
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes
, i2notes
, i1notes
= 0;
2486 rtx i3links
, i2links
, i1links
= 0;
2489 /* Compute which registers we expect to eliminate. newi2pat may be setting
2490 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2491 same as i3dest, in which case newi2pat may be setting i1dest. */
2492 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2493 || i2dest_in_i2src
|| i2dest_in_i1src
2495 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2496 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2499 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2501 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2502 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2504 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2506 /* Ensure that we do not have something that should not be shared but
2507 occurs multiple times in the new insns. Check this by first
2508 resetting all the `used' flags and then copying anything is shared. */
2510 reset_used_flags (i3notes
);
2511 reset_used_flags (i2notes
);
2512 reset_used_flags (i1notes
);
2513 reset_used_flags (newpat
);
2514 reset_used_flags (newi2pat
);
2515 if (undobuf
.other_insn
)
2516 reset_used_flags (PATTERN (undobuf
.other_insn
));
2518 i3notes
= copy_rtx_if_shared (i3notes
);
2519 i2notes
= copy_rtx_if_shared (i2notes
);
2520 i1notes
= copy_rtx_if_shared (i1notes
);
2521 newpat
= copy_rtx_if_shared (newpat
);
2522 newi2pat
= copy_rtx_if_shared (newi2pat
);
2523 if (undobuf
.other_insn
)
2524 reset_used_flags (PATTERN (undobuf
.other_insn
));
2526 INSN_CODE (i3
) = insn_code_number
;
2527 PATTERN (i3
) = newpat
;
2528 if (undobuf
.other_insn
)
2529 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2531 /* We had one special case above where I2 had more than one set and
2532 we replaced a destination of one of those sets with the destination
2533 of I3. In that case, we have to update LOG_LINKS of insns later
2534 in this basic block. Note that this (expensive) case is rare.
2536 Also, in this case, we must pretend that all REG_NOTEs for I2
2537 actually came from I3, so that REG_UNUSED notes from I2 will be
2538 properly handled. */
2540 if (i3_subst_into_i2
)
2542 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2543 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2544 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2545 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2546 && ! find_reg_note (i2
, REG_UNUSED
,
2547 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2548 for (temp
= NEXT_INSN (i2
);
2549 temp
&& (this_basic_block
== n_basic_blocks
- 1
2550 || BLOCK_HEAD (this_basic_block
) != temp
);
2551 temp
= NEXT_INSN (temp
))
2552 if (temp
!= i3
&& INSN_P (temp
))
2553 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2554 if (XEXP (link
, 0) == i2
)
2555 XEXP (link
, 0) = i3
;
2560 while (XEXP (link
, 1))
2561 link
= XEXP (link
, 1);
2562 XEXP (link
, 1) = i2notes
;
2576 INSN_CODE (i2
) = i2_code_number
;
2577 PATTERN (i2
) = newi2pat
;
2581 PUT_CODE (i2
, NOTE
);
2582 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2583 NOTE_SOURCE_FILE (i2
) = 0;
2590 PUT_CODE (i1
, NOTE
);
2591 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2592 NOTE_SOURCE_FILE (i1
) = 0;
2595 /* Get death notes for everything that is now used in either I3 or
2596 I2 and used to die in a previous insn. If we built two new
2597 patterns, move from I1 to I2 then I2 to I3 so that we get the
2598 proper movement on registers that I2 modifies. */
2602 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2603 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2606 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2609 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2611 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2614 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2620 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2623 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2624 know these are REG_UNUSED and want them to go to the desired insn,
2625 so we always pass it as i3. We have not counted the notes in
2626 reg_n_deaths yet, so we need to do so now. */
2628 if (newi2pat
&& new_i2_notes
)
2630 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2631 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2632 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2634 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2639 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2640 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2641 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2643 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2646 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2647 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2648 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2649 in that case, it might delete I2. Similarly for I2 and I1.
2650 Show an additional death due to the REG_DEAD note we make here. If
2651 we discard it in distribute_notes, we will decrement it again. */
2655 if (GET_CODE (i3dest_killed
) == REG
)
2656 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2658 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2659 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2661 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2665 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2669 if (i2dest_in_i2src
)
2671 if (GET_CODE (i2dest
) == REG
)
2672 REG_N_DEATHS (REGNO (i2dest
))++;
2674 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2675 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2676 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2680 NULL_RTX
, NULL_RTX
);
2683 if (i1dest_in_i1src
)
2685 if (GET_CODE (i1dest
) == REG
)
2686 REG_N_DEATHS (REGNO (i1dest
))++;
2688 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2690 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2694 NULL_RTX
, NULL_RTX
);
2697 distribute_links (i3links
);
2698 distribute_links (i2links
);
2699 distribute_links (i1links
);
2701 if (GET_CODE (i2dest
) == REG
)
2704 rtx i2_insn
= 0, i2_val
= 0, set
;
2706 /* The insn that used to set this register doesn't exist, and
2707 this life of the register may not exist either. See if one of
2708 I3's links points to an insn that sets I2DEST. If it does,
2709 that is now the last known value for I2DEST. If we don't update
2710 this and I2 set the register to a value that depended on its old
2711 contents, we will get confused. If this insn is used, thing
2712 will be set correctly in combine_instructions. */
2714 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2715 if ((set
= single_set (XEXP (link
, 0))) != 0
2716 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2717 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2719 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2721 /* If the reg formerly set in I2 died only once and that was in I3,
2722 zero its use count so it won't make `reload' do any work. */
2724 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2725 && ! i2dest_in_i2src
)
2727 regno
= REGNO (i2dest
);
2728 REG_N_SETS (regno
)--;
2732 if (i1
&& GET_CODE (i1dest
) == REG
)
2735 rtx i1_insn
= 0, i1_val
= 0, set
;
2737 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2738 if ((set
= single_set (XEXP (link
, 0))) != 0
2739 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2740 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2742 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2744 regno
= REGNO (i1dest
);
2745 if (! added_sets_1
&& ! i1dest_in_i1src
)
2746 REG_N_SETS (regno
)--;
2749 /* Update reg_nonzero_bits et al for any changes that may have been made
2750 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2751 important. Because newi2pat can affect nonzero_bits of newpat */
2753 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2754 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2756 /* Set new_direct_jump_p if a new return or simple jump instruction
2759 If I3 is now an unconditional jump, ensure that it has a
2760 BARRIER following it since it may have initially been a
2761 conditional jump. It may also be the last nonnote insn. */
2763 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2765 *new_direct_jump_p
= 1;
2767 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2768 || GET_CODE (temp
) != BARRIER
)
2769 emit_barrier_after (i3
);
2773 combine_successes
++;
2776 /* Clear this here, so that subsequent get_last_value calls are not
2778 subst_prev_insn
= NULL_RTX
;
2780 if (added_links_insn
2781 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2782 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2783 return added_links_insn
;
2785 return newi2pat
? i2
: i3
;
2788 /* Undo all the modifications recorded in undobuf. */
2793 struct undo
*undo
, *next
;
2795 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2799 *undo
->where
.i
= undo
->old_contents
.i
;
2801 *undo
->where
.r
= undo
->old_contents
.r
;
2803 undo
->next
= undobuf
.frees
;
2804 undobuf
.frees
= undo
;
2809 /* Clear this here, so that subsequent get_last_value calls are not
2811 subst_prev_insn
= NULL_RTX
;
2814 /* We've committed to accepting the changes we made. Move all
2815 of the undos to the free list. */
2820 struct undo
*undo
, *next
;
2822 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2825 undo
->next
= undobuf
.frees
;
2826 undobuf
.frees
= undo
;
2832 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2833 where we have an arithmetic expression and return that point. LOC will
2836 try_combine will call this function to see if an insn can be split into
2840 find_split_point (loc
, insn
)
2845 enum rtx_code code
= GET_CODE (x
);
2847 unsigned HOST_WIDE_INT len
= 0;
2848 HOST_WIDE_INT pos
= 0;
2850 rtx inner
= NULL_RTX
;
2852 /* First special-case some codes. */
2856 #ifdef INSN_SCHEDULING
2857 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2859 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2862 return find_split_point (&SUBREG_REG (x
), insn
);
2866 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2867 using LO_SUM and HIGH. */
2868 if (GET_CODE (XEXP (x
, 0)) == CONST
2869 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2872 gen_rtx_LO_SUM (Pmode
,
2873 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2875 return &XEXP (XEXP (x
, 0), 0);
2879 /* If we have a PLUS whose second operand is a constant and the
2880 address is not valid, perhaps will can split it up using
2881 the machine-specific way to split large constants. We use
2882 the first pseudo-reg (one of the virtual regs) as a placeholder;
2883 it will not remain in the result. */
2884 if (GET_CODE (XEXP (x
, 0)) == PLUS
2885 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2886 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2888 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2889 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2892 /* This should have produced two insns, each of which sets our
2893 placeholder. If the source of the second is a valid address,
2894 we can make put both sources together and make a split point
2897 if (seq
&& XVECLEN (seq
, 0) == 2
2898 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2899 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2900 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2901 && ! reg_mentioned_p (reg
,
2902 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2903 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2904 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2905 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2906 && memory_address_p (GET_MODE (x
),
2907 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2909 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2910 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2912 /* Replace the placeholder in SRC2 with SRC1. If we can
2913 find where in SRC2 it was placed, that can become our
2914 split point and we can replace this address with SRC2.
2915 Just try two obvious places. */
2917 src2
= replace_rtx (src2
, reg
, src1
);
2919 if (XEXP (src2
, 0) == src1
)
2920 split
= &XEXP (src2
, 0);
2921 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2922 && XEXP (XEXP (src2
, 0), 0) == src1
)
2923 split
= &XEXP (XEXP (src2
, 0), 0);
2927 SUBST (XEXP (x
, 0), src2
);
2932 /* If that didn't work, perhaps the first operand is complex and
2933 needs to be computed separately, so make a split point there.
2934 This will occur on machines that just support REG + CONST
2935 and have a constant moved through some previous computation. */
2937 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2938 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2939 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2941 return &XEXP (XEXP (x
, 0), 0);
2947 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2948 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2949 we need to put the operand into a register. So split at that
2952 if (SET_DEST (x
) == cc0_rtx
2953 && GET_CODE (SET_SRC (x
)) != COMPARE
2954 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2955 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2956 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2957 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2958 return &SET_SRC (x
);
2961 /* See if we can split SET_SRC as it stands. */
2962 split
= find_split_point (&SET_SRC (x
), insn
);
2963 if (split
&& split
!= &SET_SRC (x
))
2966 /* See if we can split SET_DEST as it stands. */
2967 split
= find_split_point (&SET_DEST (x
), insn
);
2968 if (split
&& split
!= &SET_DEST (x
))
2971 /* See if this is a bitfield assignment with everything constant. If
2972 so, this is an IOR of an AND, so split it into that. */
2973 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2974 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2975 <= HOST_BITS_PER_WIDE_INT
)
2976 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2977 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2978 && GET_CODE (SET_SRC (x
)) == CONST_INT
2979 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2980 + INTVAL (XEXP (SET_DEST (x
), 2)))
2981 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2982 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2984 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2985 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2986 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2987 rtx dest
= XEXP (SET_DEST (x
), 0);
2988 enum machine_mode mode
= GET_MODE (dest
);
2989 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2991 if (BITS_BIG_ENDIAN
)
2992 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2996 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2999 gen_binary (IOR
, mode
,
3000 gen_binary (AND
, mode
, dest
,
3001 GEN_INT (~(mask
<< pos
)
3002 & GET_MODE_MASK (mode
))),
3003 GEN_INT (src
<< pos
)));
3005 SUBST (SET_DEST (x
), dest
);
3007 split
= find_split_point (&SET_SRC (x
), insn
);
3008 if (split
&& split
!= &SET_SRC (x
))
3012 /* Otherwise, see if this is an operation that we can split into two.
3013 If so, try to split that. */
3014 code
= GET_CODE (SET_SRC (x
));
3019 /* If we are AND'ing with a large constant that is only a single
3020 bit and the result is only being used in a context where we
3021 need to know if it is zero or non-zero, replace it with a bit
3022 extraction. This will avoid the large constant, which might
3023 have taken more than one insn to make. If the constant were
3024 not a valid argument to the AND but took only one insn to make,
3025 this is no worse, but if it took more than one insn, it will
3028 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3029 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3030 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3031 && GET_CODE (SET_DEST (x
)) == REG
3032 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3033 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3034 && XEXP (*split
, 0) == SET_DEST (x
)
3035 && XEXP (*split
, 1) == const0_rtx
)
3037 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3038 XEXP (SET_SRC (x
), 0),
3039 pos
, NULL_RTX
, 1, 1, 0, 0);
3040 if (extraction
!= 0)
3042 SUBST (SET_SRC (x
), extraction
);
3043 return find_split_point (loc
, insn
);
3049 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3050 is known to be on, this can be converted into a NEG of a shift. */
3051 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3052 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3053 && 1 <= (pos
= exact_log2
3054 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3055 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3057 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3061 gen_rtx_LSHIFTRT (mode
,
3062 XEXP (SET_SRC (x
), 0),
3065 split
= find_split_point (&SET_SRC (x
), insn
);
3066 if (split
&& split
!= &SET_SRC (x
))
3072 inner
= XEXP (SET_SRC (x
), 0);
3074 /* We can't optimize if either mode is a partial integer
3075 mode as we don't know how many bits are significant
3077 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3078 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3082 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3088 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3089 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3091 inner
= XEXP (SET_SRC (x
), 0);
3092 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3093 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3095 if (BITS_BIG_ENDIAN
)
3096 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3097 unsignedp
= (code
== ZERO_EXTRACT
);
3105 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3107 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3109 /* For unsigned, we have a choice of a shift followed by an
3110 AND or two shifts. Use two shifts for field sizes where the
3111 constant might be too large. We assume here that we can
3112 always at least get 8-bit constants in an AND insn, which is
3113 true for every current RISC. */
3115 if (unsignedp
&& len
<= 8)
3120 (mode
, gen_lowpart_for_combine (mode
, inner
),
3122 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3124 split
= find_split_point (&SET_SRC (x
), insn
);
3125 if (split
&& split
!= &SET_SRC (x
))
3132 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3133 gen_rtx_ASHIFT (mode
,
3134 gen_lowpart_for_combine (mode
, inner
),
3135 GEN_INT (GET_MODE_BITSIZE (mode
)
3137 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3139 split
= find_split_point (&SET_SRC (x
), insn
);
3140 if (split
&& split
!= &SET_SRC (x
))
3145 /* See if this is a simple operation with a constant as the second
3146 operand. It might be that this constant is out of range and hence
3147 could be used as a split point. */
3148 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3149 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3150 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3151 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3152 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3153 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3154 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3156 return &XEXP (SET_SRC (x
), 1);
3158 /* Finally, see if this is a simple operation with its first operand
3159 not in a register. The operation might require this operand in a
3160 register, so return it as a split point. We can always do this
3161 because if the first operand were another operation, we would have
3162 already found it as a split point. */
3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3166 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3167 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3168 return &XEXP (SET_SRC (x
), 0);
3174 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3175 it is better to write this as (not (ior A B)) so we can split it.
3176 Similarly for IOR. */
3177 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3180 gen_rtx_NOT (GET_MODE (x
),
3181 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3183 XEXP (XEXP (x
, 0), 0),
3184 XEXP (XEXP (x
, 1), 0))));
3185 return find_split_point (loc
, insn
);
3188 /* Many RISC machines have a large set of logical insns. If the
3189 second operand is a NOT, put it first so we will try to split the
3190 other operand first. */
3191 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3193 rtx tem
= XEXP (x
, 0);
3194 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3195 SUBST (XEXP (x
, 1), tem
);
3203 /* Otherwise, select our actions depending on our rtx class. */
3204 switch (GET_RTX_CLASS (code
))
3206 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3208 split
= find_split_point (&XEXP (x
, 2), insn
);
3211 /* ... fall through ... */
3215 split
= find_split_point (&XEXP (x
, 1), insn
);
3218 /* ... fall through ... */
3220 /* Some machines have (and (shift ...) ...) insns. If X is not
3221 an AND, but XEXP (X, 0) is, use it as our split point. */
3222 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3223 return &XEXP (x
, 0);
3225 split
= find_split_point (&XEXP (x
, 0), insn
);
3231 /* Otherwise, we don't have a split point. */
3235 /* Throughout X, replace FROM with TO, and return the result.
3236 The result is TO if X is FROM;
3237 otherwise the result is X, but its contents may have been modified.
3238 If they were modified, a record was made in undobuf so that
3239 undo_all will (among other things) return X to its original state.
3241 If the number of changes necessary is too much to record to undo,
3242 the excess changes are not made, so the result is invalid.
3243 The changes already made can still be undone.
3244 undobuf.num_undo is incremented for such changes, so by testing that
3245 the caller can tell whether the result is valid.
3247 `n_occurrences' is incremented each time FROM is replaced.
3249 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3251 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3252 by copying if `n_occurrences' is non-zero. */
3255 subst (x
, from
, to
, in_dest
, unique_copy
)
3256 register rtx x
, from
, to
;
3260 register enum rtx_code code
= GET_CODE (x
);
3261 enum machine_mode op0_mode
= VOIDmode
;
3262 register const char *fmt
;
3263 register int len
, i
;
3266 /* Two expressions are equal if they are identical copies of a shared
3267 RTX or if they are both registers with the same register number
3270 #define COMBINE_RTX_EQUAL_P(X,Y) \
3272 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3273 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3275 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3278 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3281 /* If X and FROM are the same register but different modes, they will
3282 not have been seen as equal above. However, flow.c will make a
3283 LOG_LINKS entry for that case. If we do nothing, we will try to
3284 rerecognize our original insn and, when it succeeds, we will
3285 delete the feeding insn, which is incorrect.
3287 So force this insn not to match in this (rare) case. */
3288 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3289 && REGNO (x
) == REGNO (from
))
3290 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3292 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3293 of which may contain things that can be combined. */
3294 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3297 /* It is possible to have a subexpression appear twice in the insn.
3298 Suppose that FROM is a register that appears within TO.
3299 Then, after that subexpression has been scanned once by `subst',
3300 the second time it is scanned, TO may be found. If we were
3301 to scan TO here, we would find FROM within it and create a
3302 self-referent rtl structure which is completely wrong. */
3303 if (COMBINE_RTX_EQUAL_P (x
, to
))
3306 /* Parallel asm_operands need special attention because all of the
3307 inputs are shared across the arms. Furthermore, unsharing the
3308 rtl results in recognition failures. Failure to handle this case
3309 specially can result in circular rtl.
3311 Solve this by doing a normal pass across the first entry of the
3312 parallel, and only processing the SET_DESTs of the subsequent
3315 if (code
== PARALLEL
3316 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3317 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3319 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3321 /* If this substitution failed, this whole thing fails. */
3322 if (GET_CODE (new) == CLOBBER
3323 && XEXP (new, 0) == const0_rtx
)
3326 SUBST (XVECEXP (x
, 0, 0), new);
3328 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3330 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3332 if (GET_CODE (dest
) != REG
3333 && GET_CODE (dest
) != CC0
3334 && GET_CODE (dest
) != PC
)
3336 new = subst (dest
, from
, to
, 0, unique_copy
);
3338 /* If this substitution failed, this whole thing fails. */
3339 if (GET_CODE (new) == CLOBBER
3340 && XEXP (new, 0) == const0_rtx
)
3343 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3349 len
= GET_RTX_LENGTH (code
);
3350 fmt
= GET_RTX_FORMAT (code
);
3352 /* We don't need to process a SET_DEST that is a register, CC0,
3353 or PC, so set up to skip this common case. All other cases
3354 where we want to suppress replacing something inside a
3355 SET_SRC are handled via the IN_DEST operand. */
3357 && (GET_CODE (SET_DEST (x
)) == REG
3358 || GET_CODE (SET_DEST (x
)) == CC0
3359 || GET_CODE (SET_DEST (x
)) == PC
))
3362 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3365 op0_mode
= GET_MODE (XEXP (x
, 0));
3367 for (i
= 0; i
< len
; i
++)
3372 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3374 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3376 new = (unique_copy
&& n_occurrences
3377 ? copy_rtx (to
) : to
);
3382 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3385 /* If this substitution failed, this whole thing
3387 if (GET_CODE (new) == CLOBBER
3388 && XEXP (new, 0) == const0_rtx
)
3392 SUBST (XVECEXP (x
, i
, j
), new);
3395 else if (fmt
[i
] == 'e')
3397 /* If this is a register being set, ignore it. */
3400 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3401 || code
== ZERO_EXTRACT
)
3403 && GET_CODE (new) == REG
)
3406 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3408 /* In general, don't install a subreg involving two
3409 modes not tieable. It can worsen register
3410 allocation, and can even make invalid reload
3411 insns, since the reg inside may need to be copied
3412 from in the outside mode, and that may be invalid
3413 if it is an fp reg copied in integer mode.
3415 We allow two exceptions to this: It is valid if
3416 it is inside another SUBREG and the mode of that
3417 SUBREG and the mode of the inside of TO is
3418 tieable and it is valid if X is a SET that copies
3421 if (GET_CODE (to
) == SUBREG
3422 && ! MODES_TIEABLE_P (GET_MODE (to
),
3423 GET_MODE (SUBREG_REG (to
)))
3424 && ! (code
== SUBREG
3425 && MODES_TIEABLE_P (GET_MODE (x
),
3426 GET_MODE (SUBREG_REG (to
))))
3428 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3431 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3433 #ifdef CLASS_CANNOT_CHANGE_MODE
3435 && GET_CODE (to
) == REG
3436 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3437 && (TEST_HARD_REG_BIT
3438 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3440 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3442 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3445 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3449 /* If we are in a SET_DEST, suppress most cases unless we
3450 have gone inside a MEM, in which case we want to
3451 simplify the address. We assume here that things that
3452 are actually part of the destination have their inner
3453 parts in the first expression. This is true for SUBREG,
3454 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3455 things aside from REG and MEM that should appear in a
3457 new = subst (XEXP (x
, i
), from
, to
,
3459 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3460 || code
== ZERO_EXTRACT
))
3462 && i
== 0), unique_copy
);
3464 /* If we found that we will have to reject this combination,
3465 indicate that by returning the CLOBBER ourselves, rather than
3466 an expression containing it. This will speed things up as
3467 well as prevent accidents where two CLOBBERs are considered
3468 to be equal, thus producing an incorrect simplification. */
3470 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3473 SUBST (XEXP (x
, i
), new);
3478 /* Try to simplify X. If the simplification changed the code, it is likely
3479 that further simplification will help, so loop, but limit the number
3480 of repetitions that will be performed. */
3482 for (i
= 0; i
< 4; i
++)
3484 /* If X is sufficiently simple, don't bother trying to do anything
3486 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3487 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3489 if (GET_CODE (x
) == code
)
3492 code
= GET_CODE (x
);
3494 /* We no longer know the original mode of operand 0 since we
3495 have changed the form of X) */
3496 op0_mode
= VOIDmode
;
3502 /* Simplify X, a piece of RTL. We just operate on the expression at the
3503 outer level; call `subst' to simplify recursively. Return the new
3506 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3507 will be the iteration even if an expression with a code different from
3508 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3511 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3513 enum machine_mode op0_mode
;
3517 enum rtx_code code
= GET_CODE (x
);
3518 enum machine_mode mode
= GET_MODE (x
);
3523 /* If this is a commutative operation, put a constant last and a complex
3524 expression first. We don't need to do this for comparisons here. */
3525 if (GET_RTX_CLASS (code
) == 'c'
3526 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3529 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3530 SUBST (XEXP (x
, 1), temp
);
3533 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3534 sign extension of a PLUS with a constant, reverse the order of the sign
3535 extension and the addition. Note that this not the same as the original
3536 code, but overflow is undefined for signed values. Also note that the
3537 PLUS will have been partially moved "inside" the sign-extension, so that
3538 the first operand of X will really look like:
3539 (ashiftrt (plus (ashift A C4) C5) C4).
3541 (plus (ashiftrt (ashift A C4) C2) C4)
3542 and replace the first operand of X with that expression. Later parts
3543 of this function may simplify the expression further.
3545 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3546 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3547 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3549 We do this to simplify address expressions. */
3551 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3552 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3553 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3554 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3555 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3556 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3557 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3558 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3559 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3560 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3561 XEXP (XEXP (x
, 0), 1))) != 0)
3564 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3565 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3566 INTVAL (XEXP (XEXP (x
, 0), 1)));
3568 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3569 INTVAL (XEXP (XEXP (x
, 0), 1)));
3571 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3574 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3575 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3576 things. Check for cases where both arms are testing the same
3579 Don't do anything if all operands are very simple. */
3581 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3582 || GET_RTX_CLASS (code
) == '<')
3583 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3584 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3585 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3587 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3588 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3589 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3591 || (GET_RTX_CLASS (code
) == '1'
3592 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3593 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3594 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3597 rtx cond
, true_rtx
, false_rtx
;
3599 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3601 /* If everything is a comparison, what we have is highly unlikely
3602 to be simpler, so don't use it. */
3603 && ! (GET_RTX_CLASS (code
) == '<'
3604 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3605 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3607 rtx cop1
= const0_rtx
;
3608 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3610 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3613 /* Simplify the alternative arms; this may collapse the true and
3614 false arms to store-flag values. */
3615 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3616 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3618 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3619 is unlikely to be simpler. */
3620 if (general_operand (true_rtx
, VOIDmode
)
3621 && general_operand (false_rtx
, VOIDmode
))
3623 /* Restarting if we generate a store-flag expression will cause
3624 us to loop. Just drop through in this case. */
3626 /* If the result values are STORE_FLAG_VALUE and zero, we can
3627 just make the comparison operation. */
3628 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3629 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3630 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3631 x
= gen_binary (reverse_condition (cond_code
),
3634 /* Likewise, we can make the negate of a comparison operation
3635 if the result values are - STORE_FLAG_VALUE and zero. */
3636 else if (GET_CODE (true_rtx
) == CONST_INT
3637 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3638 && false_rtx
== const0_rtx
)
3639 x
= simplify_gen_unary (NEG
, mode
,
3640 gen_binary (cond_code
, mode
, cond
,
3643 else if (GET_CODE (false_rtx
) == CONST_INT
3644 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3645 && true_rtx
== const0_rtx
)
3646 x
= simplify_gen_unary (NEG
, mode
,
3647 gen_binary (reverse_condition
3652 return gen_rtx_IF_THEN_ELSE (mode
,
3653 gen_binary (cond_code
, VOIDmode
,
3655 true_rtx
, false_rtx
);
3657 code
= GET_CODE (x
);
3658 op0_mode
= VOIDmode
;
3663 /* Try to fold this expression in case we have constants that weren't
3666 switch (GET_RTX_CLASS (code
))
3669 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3673 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3674 if (cmp_mode
== VOIDmode
)
3676 cmp_mode
= GET_MODE (XEXP (x
, 1));
3677 if (cmp_mode
== VOIDmode
)
3678 cmp_mode
= op0_mode
;
3680 temp
= simplify_relational_operation (code
, cmp_mode
,
3681 XEXP (x
, 0), XEXP (x
, 1));
3683 #ifdef FLOAT_STORE_FLAG_VALUE
3684 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3686 if (temp
== const0_rtx
)
3687 temp
= CONST0_RTX (mode
);
3689 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3695 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3699 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3700 XEXP (x
, 1), XEXP (x
, 2));
3705 x
= temp
, code
= GET_CODE (temp
), op0_mode
= VOIDmode
;
3707 /* First see if we can apply the inverse distributive law. */
3708 if (code
== PLUS
|| code
== MINUS
3709 || code
== AND
|| code
== IOR
|| code
== XOR
)
3711 x
= apply_distributive_law (x
);
3712 code
= GET_CODE (x
);
3713 op0_mode
= VOIDmode
;
3716 /* If CODE is an associative operation not otherwise handled, see if we
3717 can associate some operands. This can win if they are constants or
3718 if they are logically related (i.e. (a & b) & a). */
3719 if ((code
== PLUS
|| code
== MINUS
3720 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3721 || code
== DIV
|| code
== UDIV
3722 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3723 && INTEGRAL_MODE_P (mode
))
3725 if (GET_CODE (XEXP (x
, 0)) == code
)
3727 rtx other
= XEXP (XEXP (x
, 0), 0);
3728 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3729 rtx inner_op1
= XEXP (x
, 1);
3732 /* Make sure we pass the constant operand if any as the second
3733 one if this is a commutative operation. */
3734 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3736 rtx tem
= inner_op0
;
3737 inner_op0
= inner_op1
;
3740 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3741 : code
== DIV
? MULT
3742 : code
== UDIV
? MULT
3744 mode
, inner_op0
, inner_op1
);
3746 /* For commutative operations, try the other pair if that one
3748 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3750 other
= XEXP (XEXP (x
, 0), 1);
3751 inner
= simplify_binary_operation (code
, mode
,
3752 XEXP (XEXP (x
, 0), 0),
3757 return gen_binary (code
, mode
, other
, inner
);
3761 /* A little bit of algebraic simplification here. */
3765 /* Ensure that our address has any ASHIFTs converted to MULT in case
3766 address-recognizing predicates are called later. */
3767 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3768 SUBST (XEXP (x
, 0), temp
);
3772 if (op0_mode
== VOIDmode
)
3773 op0_mode
= GET_MODE (SUBREG_REG (x
));
3775 /* simplify_subreg can't use gen_lowpart_for_combine. */
3776 if (CONSTANT_P (SUBREG_REG (x
))
3777 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
))
3778 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3782 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3788 /* Note that we cannot do any narrowing for non-constants since
3789 we might have been counting on using the fact that some bits were
3790 zero. We now do this in the SET. */
3795 /* (not (plus X -1)) can become (neg X). */
3796 if (GET_CODE (XEXP (x
, 0)) == PLUS
3797 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3798 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3800 /* Similarly, (not (neg X)) is (plus X -1). */
3801 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3802 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3804 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3805 if (GET_CODE (XEXP (x
, 0)) == XOR
3806 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3807 && (temp
= simplify_unary_operation (NOT
, mode
,
3808 XEXP (XEXP (x
, 0), 1),
3810 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3812 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3813 other than 1, but that is not valid. We could do a similar
3814 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3815 but this doesn't seem common enough to bother with. */
3816 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3817 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3818 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3820 XEXP (XEXP (x
, 0), 1));
3822 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3823 && subreg_lowpart_p (XEXP (x
, 0))
3824 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3825 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3826 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3827 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3829 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3831 x
= gen_rtx_ROTATE (inner_mode
,
3832 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3834 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3835 return gen_lowpart_for_combine (mode
, x
);
3838 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3839 reversing the comparison code if valid. */
3840 if (STORE_FLAG_VALUE
== -1
3841 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3842 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3843 XEXP (XEXP (x
, 0), 1))))
3846 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3847 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3848 perform the above simplification. */
3850 if (STORE_FLAG_VALUE
== -1
3851 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3852 && XEXP (x
, 1) == const1_rtx
3853 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3854 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3855 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3857 /* Apply De Morgan's laws to reduce number of patterns for machines
3858 with negating logical insns (and-not, nand, etc.). If result has
3859 only one NOT, put it first, since that is how the patterns are
3862 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3864 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3865 enum machine_mode op_mode
;
3867 op_mode
= GET_MODE (in1
);
3868 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3870 op_mode
= GET_MODE (in2
);
3871 if (op_mode
== VOIDmode
)
3873 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3875 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3878 in2
= in1
; in1
= tem
;
3881 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3887 /* (neg (plus X 1)) can become (not X). */
3888 if (GET_CODE (XEXP (x
, 0)) == PLUS
3889 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3890 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3892 /* Similarly, (neg (not X)) is (plus X 1). */
3893 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3894 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3896 /* (neg (minus X Y)) can become (minus Y X). */
3897 if (GET_CODE (XEXP (x
, 0)) == MINUS
3898 && (! FLOAT_MODE_P (mode
)
3899 /* x-y != -(y-x) with IEEE floating point. */
3900 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3901 || flag_unsafe_math_optimizations
))
3902 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3903 XEXP (XEXP (x
, 0), 0));
3905 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3906 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3907 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3908 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3910 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3911 if we can then eliminate the NEG (e.g.,
3912 if the operand is a constant). */
3914 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3916 temp
= simplify_unary_operation (NEG
, mode
,
3917 XEXP (XEXP (x
, 0), 0), mode
);
3920 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3925 temp
= expand_compound_operation (XEXP (x
, 0));
3927 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3928 replaced by (lshiftrt X C). This will convert
3929 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3931 if (GET_CODE (temp
) == ASHIFTRT
3932 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3933 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3934 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3935 INTVAL (XEXP (temp
, 1)));
3937 /* If X has only a single bit that might be nonzero, say, bit I, convert
3938 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3939 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3940 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3941 or a SUBREG of one since we'd be making the expression more
3942 complex if it was just a register. */
3944 if (GET_CODE (temp
) != REG
3945 && ! (GET_CODE (temp
) == SUBREG
3946 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3947 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3949 rtx temp1
= simplify_shift_const
3950 (NULL_RTX
, ASHIFTRT
, mode
,
3951 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3952 GET_MODE_BITSIZE (mode
) - 1 - i
),
3953 GET_MODE_BITSIZE (mode
) - 1 - i
);
3955 /* If all we did was surround TEMP with the two shifts, we
3956 haven't improved anything, so don't use it. Otherwise,
3957 we are better off with TEMP1. */
3958 if (GET_CODE (temp1
) != ASHIFTRT
3959 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3960 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3966 /* We can't handle truncation to a partial integer mode here
3967 because we don't know the real bitsize of the partial
3969 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3972 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3973 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3974 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3976 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3977 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3979 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3980 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3981 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3982 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3983 return XEXP (XEXP (x
, 0), 0);
3985 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3986 (OP:SI foo:SI) if OP is NEG or ABS. */
3987 if ((GET_CODE (XEXP (x
, 0)) == ABS
3988 || GET_CODE (XEXP (x
, 0)) == NEG
)
3989 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3990 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3991 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3992 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3993 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3995 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3997 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3998 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3999 && subreg_lowpart_p (XEXP (x
, 0)))
4000 return SUBREG_REG (XEXP (x
, 0));
4002 /* If we know that the value is already truncated, we can
4003 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4004 is nonzero for the corresponding modes. But don't do this
4005 for an (LSHIFTRT (MULT ...)) since this will cause problems
4006 with the umulXi3_highpart patterns. */
4007 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4008 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4009 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4010 >= GET_MODE_BITSIZE (mode
) + 1
4011 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4012 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4013 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4015 /* A truncate of a comparison can be replaced with a subreg if
4016 STORE_FLAG_VALUE permits. This is like the previous test,
4017 but it works even if the comparison is done in a mode larger
4018 than HOST_BITS_PER_WIDE_INT. */
4019 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4020 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4021 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4022 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4024 /* Similarly, a truncate of a register whose value is a
4025 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4027 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4028 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4029 && (temp
= get_last_value (XEXP (x
, 0)))
4030 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4031 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4035 case FLOAT_TRUNCATE
:
4036 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4037 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4038 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4039 return XEXP (XEXP (x
, 0), 0);
4041 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4042 (OP:SF foo:SF) if OP is NEG or ABS. */
4043 if ((GET_CODE (XEXP (x
, 0)) == ABS
4044 || GET_CODE (XEXP (x
, 0)) == NEG
)
4045 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4046 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4047 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4048 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4050 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4051 is (float_truncate:SF x). */
4052 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4053 && subreg_lowpart_p (XEXP (x
, 0))
4054 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4055 return SUBREG_REG (XEXP (x
, 0));
4060 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4061 using cc0, in which case we want to leave it as a COMPARE
4062 so we can distinguish it from a register-register-copy. */
4063 if (XEXP (x
, 1) == const0_rtx
)
4066 /* In IEEE floating point, x-0 is not the same as x. */
4067 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4068 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4069 || flag_unsafe_math_optimizations
)
4070 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4076 /* (const (const X)) can become (const X). Do it this way rather than
4077 returning the inner CONST since CONST can be shared with a
4079 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4080 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4085 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4086 can add in an offset. find_split_point will split this address up
4087 again if it doesn't match. */
4088 if (GET_CODE (XEXP (x
, 0)) == HIGH
4089 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4095 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4096 outermost. That's because that's the way indexed addresses are
4097 supposed to appear. This code used to check many more cases, but
4098 they are now checked elsewhere. */
4099 if (GET_CODE (XEXP (x
, 0)) == PLUS
4100 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4101 return gen_binary (PLUS
, mode
,
4102 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4104 XEXP (XEXP (x
, 0), 1));
4106 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4107 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4108 bit-field and can be replaced by either a sign_extend or a
4109 sign_extract. The `and' may be a zero_extend and the two
4110 <c>, -<c> constants may be reversed. */
4111 if (GET_CODE (XEXP (x
, 0)) == XOR
4112 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4113 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4114 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4115 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4116 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4117 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4118 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4119 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4120 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4121 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4122 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4123 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4124 == (unsigned int) i
+ 1))))
4125 return simplify_shift_const
4126 (NULL_RTX
, ASHIFTRT
, mode
,
4127 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4128 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4129 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4130 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4132 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4133 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4134 is 1. This produces better code than the alternative immediately
4136 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4137 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4138 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4139 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4140 XEXP (XEXP (x
, 0), 0),
4141 XEXP (XEXP (x
, 0), 1))))
4143 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4145 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4146 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4147 the bitsize of the mode - 1. This allows simplification of
4148 "a = (b & 8) == 0;" */
4149 if (XEXP (x
, 1) == constm1_rtx
4150 && GET_CODE (XEXP (x
, 0)) != REG
4151 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4152 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4153 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4154 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4155 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4156 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4157 GET_MODE_BITSIZE (mode
) - 1),
4158 GET_MODE_BITSIZE (mode
) - 1);
4160 /* If we are adding two things that have no bits in common, convert
4161 the addition into an IOR. This will often be further simplified,
4162 for example in cases like ((a & 1) + (a & 2)), which can
4165 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4166 && (nonzero_bits (XEXP (x
, 0), mode
)
4167 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4169 /* Try to simplify the expression further. */
4170 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4171 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4173 /* If we could, great. If not, do not go ahead with the IOR
4174 replacement, since PLUS appears in many special purpose
4175 address arithmetic instructions. */
4176 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4182 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4183 by reversing the comparison code if valid. */
4184 if (STORE_FLAG_VALUE
== 1
4185 && XEXP (x
, 0) == const1_rtx
4186 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4187 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4188 XEXP (XEXP (x
, 1), 0),
4189 XEXP (XEXP (x
, 1), 1))))
4192 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4193 (and <foo> (const_int pow2-1)) */
4194 if (GET_CODE (XEXP (x
, 1)) == AND
4195 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4196 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4197 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4198 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4199 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4201 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4203 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4204 return gen_binary (MINUS
, mode
,
4205 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4206 XEXP (XEXP (x
, 1), 0)),
4207 XEXP (XEXP (x
, 1), 1));
4211 /* If we have (mult (plus A B) C), apply the distributive law and then
4212 the inverse distributive law to see if things simplify. This
4213 occurs mostly in addresses, often when unrolling loops. */
4215 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4217 x
= apply_distributive_law
4218 (gen_binary (PLUS
, mode
,
4219 gen_binary (MULT
, mode
,
4220 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4221 gen_binary (MULT
, mode
,
4222 XEXP (XEXP (x
, 0), 1),
4223 copy_rtx (XEXP (x
, 1)))));
4225 if (GET_CODE (x
) != MULT
)
4231 /* If this is a divide by a power of two, treat it as a shift if
4232 its first operand is a shift. */
4233 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4234 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4235 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4236 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4237 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4238 || GET_CODE (XEXP (x
, 0)) == ROTATE
4239 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4240 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4244 case GT
: case GTU
: case GE
: case GEU
:
4245 case LT
: case LTU
: case LE
: case LEU
:
4246 case UNEQ
: case LTGT
:
4247 case UNGT
: case UNGE
:
4248 case UNLT
: case UNLE
:
4249 case UNORDERED
: case ORDERED
:
4250 /* If the first operand is a condition code, we can't do anything
4252 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4253 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4255 && XEXP (x
, 0) != cc0_rtx
4259 rtx op0
= XEXP (x
, 0);
4260 rtx op1
= XEXP (x
, 1);
4261 enum rtx_code new_code
;
4263 if (GET_CODE (op0
) == COMPARE
)
4264 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4266 /* Simplify our comparison, if possible. */
4267 new_code
= simplify_comparison (code
, &op0
, &op1
);
4269 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4270 if only the low-order bit is possibly nonzero in X (such as when
4271 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4272 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4273 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4276 Remove any ZERO_EXTRACT we made when thinking this was a
4277 comparison. It may now be simpler to use, e.g., an AND. If a
4278 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4279 the call to make_compound_operation in the SET case. */
4281 if (STORE_FLAG_VALUE
== 1
4282 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4283 && op1
== const0_rtx
4284 && mode
== GET_MODE (op0
)
4285 && nonzero_bits (op0
, mode
) == 1)
4286 return gen_lowpart_for_combine (mode
,
4287 expand_compound_operation (op0
));
4289 else if (STORE_FLAG_VALUE
== 1
4290 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4291 && op1
== const0_rtx
4292 && mode
== GET_MODE (op0
)
4293 && (num_sign_bit_copies (op0
, mode
)
4294 == GET_MODE_BITSIZE (mode
)))
4296 op0
= expand_compound_operation (op0
);
4297 return simplify_gen_unary (NEG
, mode
,
4298 gen_lowpart_for_combine (mode
, op0
),
4302 else if (STORE_FLAG_VALUE
== 1
4303 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4304 && op1
== const0_rtx
4305 && mode
== GET_MODE (op0
)
4306 && nonzero_bits (op0
, mode
) == 1)
4308 op0
= expand_compound_operation (op0
);
4309 return gen_binary (XOR
, mode
,
4310 gen_lowpart_for_combine (mode
, op0
),
4314 else if (STORE_FLAG_VALUE
== 1
4315 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4316 && op1
== const0_rtx
4317 && mode
== GET_MODE (op0
)
4318 && (num_sign_bit_copies (op0
, mode
)
4319 == GET_MODE_BITSIZE (mode
)))
4321 op0
= expand_compound_operation (op0
);
4322 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4325 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4327 if (STORE_FLAG_VALUE
== -1
4328 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4329 && op1
== const0_rtx
4330 && (num_sign_bit_copies (op0
, mode
)
4331 == GET_MODE_BITSIZE (mode
)))
4332 return gen_lowpart_for_combine (mode
,
4333 expand_compound_operation (op0
));
4335 else if (STORE_FLAG_VALUE
== -1
4336 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4337 && op1
== const0_rtx
4338 && mode
== GET_MODE (op0
)
4339 && nonzero_bits (op0
, mode
) == 1)
4341 op0
= expand_compound_operation (op0
);
4342 return simplify_gen_unary (NEG
, mode
,
4343 gen_lowpart_for_combine (mode
, op0
),
4347 else if (STORE_FLAG_VALUE
== -1
4348 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4349 && op1
== const0_rtx
4350 && mode
== GET_MODE (op0
)
4351 && (num_sign_bit_copies (op0
, mode
)
4352 == GET_MODE_BITSIZE (mode
)))
4354 op0
= expand_compound_operation (op0
);
4355 return simplify_gen_unary (NOT
, mode
,
4356 gen_lowpart_for_combine (mode
, op0
),
4360 /* If X is 0/1, (eq X 0) is X-1. */
4361 else if (STORE_FLAG_VALUE
== -1
4362 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4363 && op1
== const0_rtx
4364 && mode
== GET_MODE (op0
)
4365 && nonzero_bits (op0
, mode
) == 1)
4367 op0
= expand_compound_operation (op0
);
4368 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4371 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4372 one bit that might be nonzero, we can convert (ne x 0) to
4373 (ashift x c) where C puts the bit in the sign bit. Remove any
4374 AND with STORE_FLAG_VALUE when we are done, since we are only
4375 going to test the sign bit. */
4376 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4377 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4378 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4379 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4380 && op1
== const0_rtx
4381 && mode
== GET_MODE (op0
)
4382 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4384 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4385 expand_compound_operation (op0
),
4386 GET_MODE_BITSIZE (mode
) - 1 - i
);
4387 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4393 /* If the code changed, return a whole new comparison. */
4394 if (new_code
!= code
)
4395 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4397 /* Otherwise, keep this operation, but maybe change its operands.
4398 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4399 SUBST (XEXP (x
, 0), op0
);
4400 SUBST (XEXP (x
, 1), op1
);
4405 return simplify_if_then_else (x
);
4411 /* If we are processing SET_DEST, we are done. */
4415 return expand_compound_operation (x
);
4418 return simplify_set (x
);
4423 return simplify_logical (x
, last
);
4426 /* (abs (neg <foo>)) -> (abs <foo>) */
4427 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4428 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4430 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4432 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4435 /* If operand is something known to be positive, ignore the ABS. */
4436 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4437 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4438 <= HOST_BITS_PER_WIDE_INT
)
4439 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4440 & ((HOST_WIDE_INT
) 1
4441 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4445 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4446 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4447 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4452 /* (ffs (*_extend <X>)) = (ffs <X>) */
4453 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4454 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4455 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4459 /* (float (sign_extend <X>)) = (float <X>). */
4460 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4461 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4469 /* If this is a shift by a constant amount, simplify it. */
4470 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4471 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4472 INTVAL (XEXP (x
, 1)));
4474 #ifdef SHIFT_COUNT_TRUNCATED
4475 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4477 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4479 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4488 rtx op0
= XEXP (x
, 0);
4489 rtx op1
= XEXP (x
, 1);
4492 if (GET_CODE (op1
) != PARALLEL
)
4494 len
= XVECLEN (op1
, 0);
4496 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4497 && GET_CODE (op0
) == VEC_CONCAT
)
4499 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4501 /* Try to find the element in the VEC_CONCAT. */
4504 if (GET_MODE (op0
) == GET_MODE (x
))
4506 if (GET_CODE (op0
) == VEC_CONCAT
)
4508 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4509 if (op0_size
< offset
)
4510 op0
= XEXP (op0
, 0);
4514 op0
= XEXP (op0
, 1);
4532 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4535 simplify_if_then_else (x
)
4538 enum machine_mode mode
= GET_MODE (x
);
4539 rtx cond
= XEXP (x
, 0);
4540 rtx true_rtx
= XEXP (x
, 1);
4541 rtx false_rtx
= XEXP (x
, 2);
4542 enum rtx_code true_code
= GET_CODE (cond
);
4543 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4546 enum rtx_code false_code
;
4549 /* Simplify storing of the truth value. */
4550 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4551 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4553 /* Also when the truth value has to be reversed. */
4555 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4556 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4560 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4561 in it is being compared against certain values. Get the true and false
4562 comparisons and see if that says anything about the value of each arm. */
4565 && ((false_code
= combine_reversed_comparison_code (cond
))
4567 && GET_CODE (XEXP (cond
, 0)) == REG
)
4570 rtx from
= XEXP (cond
, 0);
4571 rtx true_val
= XEXP (cond
, 1);
4572 rtx false_val
= true_val
;
4575 /* If FALSE_CODE is EQ, swap the codes and arms. */
4577 if (false_code
== EQ
)
4579 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4580 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4583 /* If we are comparing against zero and the expression being tested has
4584 only a single bit that might be nonzero, that is its value when it is
4585 not equal to zero. Similarly if it is known to be -1 or 0. */
4587 if (true_code
== EQ
&& true_val
== const0_rtx
4588 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4589 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4590 else if (true_code
== EQ
&& true_val
== const0_rtx
4591 && (num_sign_bit_copies (from
, GET_MODE (from
))
4592 == GET_MODE_BITSIZE (GET_MODE (from
))))
4593 false_code
= EQ
, false_val
= constm1_rtx
;
4595 /* Now simplify an arm if we know the value of the register in the
4596 branch and it is used in the arm. Be careful due to the potential
4597 of locally-shared RTL. */
4599 if (reg_mentioned_p (from
, true_rtx
))
4600 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4602 pc_rtx
, pc_rtx
, 0, 0);
4603 if (reg_mentioned_p (from
, false_rtx
))
4604 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4606 pc_rtx
, pc_rtx
, 0, 0);
4608 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4609 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4611 true_rtx
= XEXP (x
, 1);
4612 false_rtx
= XEXP (x
, 2);
4613 true_code
= GET_CODE (cond
);
4616 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4617 reversed, do so to avoid needing two sets of patterns for
4618 subtract-and-branch insns. Similarly if we have a constant in the true
4619 arm, the false arm is the same as the first operand of the comparison, or
4620 the false arm is more complicated than the true arm. */
4623 && combine_reversed_comparison_code (cond
) != UNKNOWN
4624 && (true_rtx
== pc_rtx
4625 || (CONSTANT_P (true_rtx
)
4626 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4627 || true_rtx
== const0_rtx
4628 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4629 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4630 || (GET_CODE (true_rtx
) == SUBREG
4631 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4632 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4633 || reg_mentioned_p (true_rtx
, false_rtx
)
4634 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4636 true_code
= reversed_comparison_code (cond
, NULL
);
4638 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4641 SUBST (XEXP (x
, 1), false_rtx
);
4642 SUBST (XEXP (x
, 2), true_rtx
);
4644 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4647 /* It is possible that the conditional has been simplified out. */
4648 true_code
= GET_CODE (cond
);
4649 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4652 /* If the two arms are identical, we don't need the comparison. */
4654 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4657 /* Convert a == b ? b : a to "a". */
4658 if (true_code
== EQ
&& ! side_effects_p (cond
)
4659 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4660 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4661 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4663 else if (true_code
== NE
&& ! side_effects_p (cond
)
4664 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4665 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4666 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4669 /* Look for cases where we have (abs x) or (neg (abs X)). */
4671 if (GET_MODE_CLASS (mode
) == MODE_INT
4672 && GET_CODE (false_rtx
) == NEG
4673 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4675 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4676 && ! side_effects_p (true_rtx
))
4681 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4685 simplify_gen_unary (NEG
, mode
,
4686 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4692 /* Look for MIN or MAX. */
4694 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4696 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4697 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4698 && ! side_effects_p (cond
))
4703 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4706 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4709 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4712 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4717 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4718 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4719 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4720 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4721 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4722 neither 1 or -1, but it isn't worth checking for. */
4724 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4725 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4727 rtx t
= make_compound_operation (true_rtx
, SET
);
4728 rtx f
= make_compound_operation (false_rtx
, SET
);
4729 rtx cond_op0
= XEXP (cond
, 0);
4730 rtx cond_op1
= XEXP (cond
, 1);
4731 enum rtx_code op
= NIL
, extend_op
= NIL
;
4732 enum machine_mode m
= mode
;
4733 rtx z
= 0, c1
= NULL_RTX
;
4735 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4736 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4737 || GET_CODE (t
) == ASHIFT
4738 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4739 && rtx_equal_p (XEXP (t
, 0), f
))
4740 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4742 /* If an identity-zero op is commutative, check whether there
4743 would be a match if we swapped the operands. */
4744 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4745 || GET_CODE (t
) == XOR
)
4746 && rtx_equal_p (XEXP (t
, 1), f
))
4747 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4748 else if (GET_CODE (t
) == SIGN_EXTEND
4749 && (GET_CODE (XEXP (t
, 0)) == PLUS
4750 || GET_CODE (XEXP (t
, 0)) == MINUS
4751 || GET_CODE (XEXP (t
, 0)) == IOR
4752 || GET_CODE (XEXP (t
, 0)) == XOR
4753 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4754 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4755 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4756 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4757 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4758 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4759 && (num_sign_bit_copies (f
, GET_MODE (f
))
4760 > (GET_MODE_BITSIZE (mode
)
4761 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4763 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4764 extend_op
= SIGN_EXTEND
;
4765 m
= GET_MODE (XEXP (t
, 0));
4767 else if (GET_CODE (t
) == SIGN_EXTEND
4768 && (GET_CODE (XEXP (t
, 0)) == PLUS
4769 || GET_CODE (XEXP (t
, 0)) == IOR
4770 || GET_CODE (XEXP (t
, 0)) == XOR
)
4771 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4772 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4773 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4774 && (num_sign_bit_copies (f
, GET_MODE (f
))
4775 > (GET_MODE_BITSIZE (mode
)
4776 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4778 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4779 extend_op
= SIGN_EXTEND
;
4780 m
= GET_MODE (XEXP (t
, 0));
4782 else if (GET_CODE (t
) == ZERO_EXTEND
4783 && (GET_CODE (XEXP (t
, 0)) == PLUS
4784 || GET_CODE (XEXP (t
, 0)) == MINUS
4785 || GET_CODE (XEXP (t
, 0)) == IOR
4786 || GET_CODE (XEXP (t
, 0)) == XOR
4787 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4788 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4789 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4790 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4791 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4792 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4793 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4794 && ((nonzero_bits (f
, GET_MODE (f
))
4795 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4798 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4799 extend_op
= ZERO_EXTEND
;
4800 m
= GET_MODE (XEXP (t
, 0));
4802 else if (GET_CODE (t
) == ZERO_EXTEND
4803 && (GET_CODE (XEXP (t
, 0)) == PLUS
4804 || GET_CODE (XEXP (t
, 0)) == IOR
4805 || GET_CODE (XEXP (t
, 0)) == XOR
)
4806 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4807 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4808 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4809 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4810 && ((nonzero_bits (f
, GET_MODE (f
))
4811 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4814 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4815 extend_op
= ZERO_EXTEND
;
4816 m
= GET_MODE (XEXP (t
, 0));
4821 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4822 pc_rtx
, pc_rtx
, 0, 0);
4823 temp
= gen_binary (MULT
, m
, temp
,
4824 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4825 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4826 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4828 if (extend_op
!= NIL
)
4829 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4835 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4836 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4837 negation of a single bit, we can convert this operation to a shift. We
4838 can actually do this more generally, but it doesn't seem worth it. */
4840 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4841 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4842 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4843 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4844 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4845 == GET_MODE_BITSIZE (mode
))
4846 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4848 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4849 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4854 /* Simplify X, a SET expression. Return the new expression. */
4860 rtx src
= SET_SRC (x
);
4861 rtx dest
= SET_DEST (x
);
4862 enum machine_mode mode
4863 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4867 /* (set (pc) (return)) gets written as (return). */
4868 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4871 /* Now that we know for sure which bits of SRC we are using, see if we can
4872 simplify the expression for the object knowing that we only need the
4875 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4877 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4878 SUBST (SET_SRC (x
), src
);
4881 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4882 the comparison result and try to simplify it unless we already have used
4883 undobuf.other_insn. */
4884 if ((GET_CODE (src
) == COMPARE
4889 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4890 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4891 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4892 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4894 enum rtx_code old_code
= GET_CODE (*cc_use
);
4895 enum rtx_code new_code
;
4897 int other_changed
= 0;
4898 enum machine_mode compare_mode
= GET_MODE (dest
);
4900 if (GET_CODE (src
) == COMPARE
)
4901 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4903 op0
= src
, op1
= const0_rtx
;
4905 /* Simplify our comparison, if possible. */
4906 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4908 #ifdef EXTRA_CC_MODES
4909 /* If this machine has CC modes other than CCmode, check to see if we
4910 need to use a different CC mode here. */
4911 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4912 #endif /* EXTRA_CC_MODES */
4914 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4915 /* If the mode changed, we have to change SET_DEST, the mode in the
4916 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4917 a hard register, just build new versions with the proper mode. If it
4918 is a pseudo, we lose unless it is only time we set the pseudo, in
4919 which case we can safely change its mode. */
4920 if (compare_mode
!= GET_MODE (dest
))
4922 unsigned int regno
= REGNO (dest
);
4923 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4925 if (regno
< FIRST_PSEUDO_REGISTER
4926 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4928 if (regno
>= FIRST_PSEUDO_REGISTER
)
4929 SUBST (regno_reg_rtx
[regno
], new_dest
);
4931 SUBST (SET_DEST (x
), new_dest
);
4932 SUBST (XEXP (*cc_use
, 0), new_dest
);
4940 /* If the code changed, we have to build a new comparison in
4941 undobuf.other_insn. */
4942 if (new_code
!= old_code
)
4944 unsigned HOST_WIDE_INT mask
;
4946 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
4949 /* If the only change we made was to change an EQ into an NE or
4950 vice versa, OP0 has only one bit that might be nonzero, and OP1
4951 is zero, check if changing the user of the condition code will
4952 produce a valid insn. If it won't, we can keep the original code
4953 in that insn by surrounding our operation with an XOR. */
4955 if (((old_code
== NE
&& new_code
== EQ
)
4956 || (old_code
== EQ
&& new_code
== NE
))
4957 && ! other_changed
&& op1
== const0_rtx
4958 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4959 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4961 rtx pat
= PATTERN (other_insn
), note
= 0;
4963 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4964 && ! check_asm_operands (pat
)))
4966 PUT_CODE (*cc_use
, old_code
);
4969 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4977 undobuf
.other_insn
= other_insn
;
4980 /* If we are now comparing against zero, change our source if
4981 needed. If we do not use cc0, we always have a COMPARE. */
4982 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4984 SUBST (SET_SRC (x
), op0
);
4990 /* Otherwise, if we didn't previously have a COMPARE in the
4991 correct mode, we need one. */
4992 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4994 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
4999 /* Otherwise, update the COMPARE if needed. */
5000 SUBST (XEXP (src
, 0), op0
);
5001 SUBST (XEXP (src
, 1), op1
);
5006 /* Get SET_SRC in a form where we have placed back any
5007 compound expressions. Then do the checks below. */
5008 src
= make_compound_operation (src
, SET
);
5009 SUBST (SET_SRC (x
), src
);
5012 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5013 and X being a REG or (subreg (reg)), we may be able to convert this to
5014 (set (subreg:m2 x) (op)).
5016 We can always do this if M1 is narrower than M2 because that means that
5017 we only care about the low bits of the result.
5019 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5020 perform a narrower operation than requested since the high-order bits will
5021 be undefined. On machine where it is defined, this transformation is safe
5022 as long as M1 and M2 have the same number of words. */
5024 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5025 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5026 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5028 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5029 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5030 #ifndef WORD_REGISTER_OPERATIONS
5031 && (GET_MODE_SIZE (GET_MODE (src
))
5032 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5034 #ifdef CLASS_CANNOT_CHANGE_MODE
5035 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5036 && (TEST_HARD_REG_BIT
5037 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5039 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5040 GET_MODE (SUBREG_REG (src
))))
5042 && (GET_CODE (dest
) == REG
5043 || (GET_CODE (dest
) == SUBREG
5044 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5046 SUBST (SET_DEST (x
),
5047 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5049 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5051 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5054 #ifdef LOAD_EXTEND_OP
5055 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5056 would require a paradoxical subreg. Replace the subreg with a
5057 zero_extend to avoid the reload that would otherwise be required. */
5059 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5060 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5061 && SUBREG_BYTE (src
) == 0
5062 && (GET_MODE_SIZE (GET_MODE (src
))
5063 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5064 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5067 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5068 GET_MODE (src
), SUBREG_REG (src
)));
5074 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5075 are comparing an item known to be 0 or -1 against 0, use a logical
5076 operation instead. Check for one of the arms being an IOR of the other
5077 arm with some value. We compute three terms to be IOR'ed together. In
5078 practice, at most two will be nonzero. Then we do the IOR's. */
5080 if (GET_CODE (dest
) != PC
5081 && GET_CODE (src
) == IF_THEN_ELSE
5082 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5083 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5084 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5085 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5086 #ifdef HAVE_conditional_move
5087 && ! can_conditionally_move_p (GET_MODE (src
))
5089 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5090 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5091 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5092 && ! side_effects_p (src
))
5094 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5095 ? XEXP (src
, 1) : XEXP (src
, 2));
5096 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5097 ? XEXP (src
, 2) : XEXP (src
, 1));
5098 rtx term1
= const0_rtx
, term2
, term3
;
5100 if (GET_CODE (true_rtx
) == IOR
5101 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5102 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5103 else if (GET_CODE (true_rtx
) == IOR
5104 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5105 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5106 else if (GET_CODE (false_rtx
) == IOR
5107 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5108 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5109 else if (GET_CODE (false_rtx
) == IOR
5110 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5111 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5113 term2
= gen_binary (AND
, GET_MODE (src
),
5114 XEXP (XEXP (src
, 0), 0), true_rtx
);
5115 term3
= gen_binary (AND
, GET_MODE (src
),
5116 simplify_gen_unary (NOT
, GET_MODE (src
),
5117 XEXP (XEXP (src
, 0), 0),
5122 gen_binary (IOR
, GET_MODE (src
),
5123 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5129 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5130 whole thing fail. */
5131 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5133 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5136 /* Convert this into a field assignment operation, if possible. */
5137 return make_field_assignment (x
);
5140 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5141 result. LAST is nonzero if this is the last retry. */
5144 simplify_logical (x
, last
)
5148 enum machine_mode mode
= GET_MODE (x
);
5149 rtx op0
= XEXP (x
, 0);
5150 rtx op1
= XEXP (x
, 1);
5153 switch (GET_CODE (x
))
5156 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5157 insn (and may simplify more). */
5158 if (GET_CODE (op0
) == XOR
5159 && rtx_equal_p (XEXP (op0
, 0), op1
)
5160 && ! side_effects_p (op1
))
5161 x
= gen_binary (AND
, mode
,
5162 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5165 if (GET_CODE (op0
) == XOR
5166 && rtx_equal_p (XEXP (op0
, 1), op1
)
5167 && ! side_effects_p (op1
))
5168 x
= gen_binary (AND
, mode
,
5169 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5172 /* Similarly for (~(A ^ B)) & A. */
5173 if (GET_CODE (op0
) == NOT
5174 && GET_CODE (XEXP (op0
, 0)) == XOR
5175 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5176 && ! side_effects_p (op1
))
5177 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5179 if (GET_CODE (op0
) == NOT
5180 && GET_CODE (XEXP (op0
, 0)) == XOR
5181 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5182 && ! side_effects_p (op1
))
5183 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5185 /* We can call simplify_and_const_int only if we don't lose
5186 any (sign) bits when converting INTVAL (op1) to
5187 "unsigned HOST_WIDE_INT". */
5188 if (GET_CODE (op1
) == CONST_INT
5189 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5190 || INTVAL (op1
) > 0))
5192 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5194 /* If we have (ior (and (X C1) C2)) and the next restart would be
5195 the last, simplify this by making C1 as small as possible
5198 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5199 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5200 && GET_CODE (op1
) == CONST_INT
)
5201 return gen_binary (IOR
, mode
,
5202 gen_binary (AND
, mode
, XEXP (op0
, 0),
5203 GEN_INT (INTVAL (XEXP (op0
, 1))
5204 & ~INTVAL (op1
))), op1
);
5206 if (GET_CODE (x
) != AND
)
5209 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5210 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5211 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5214 /* Convert (A | B) & A to A. */
5215 if (GET_CODE (op0
) == IOR
5216 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5217 || rtx_equal_p (XEXP (op0
, 1), op1
))
5218 && ! side_effects_p (XEXP (op0
, 0))
5219 && ! side_effects_p (XEXP (op0
, 1)))
5222 /* In the following group of tests (and those in case IOR below),
5223 we start with some combination of logical operations and apply
5224 the distributive law followed by the inverse distributive law.
5225 Most of the time, this results in no change. However, if some of
5226 the operands are the same or inverses of each other, simplifications
5229 For example, (and (ior A B) (not B)) can occur as the result of
5230 expanding a bit field assignment. When we apply the distributive
5231 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5232 which then simplifies to (and (A (not B))).
5234 If we have (and (ior A B) C), apply the distributive law and then
5235 the inverse distributive law to see if things simplify. */
5237 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5239 x
= apply_distributive_law
5240 (gen_binary (GET_CODE (op0
), mode
,
5241 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5242 gen_binary (AND
, mode
, XEXP (op0
, 1),
5244 if (GET_CODE (x
) != AND
)
5248 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5249 return apply_distributive_law
5250 (gen_binary (GET_CODE (op1
), mode
,
5251 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5252 gen_binary (AND
, mode
, XEXP (op1
, 1),
5255 /* Similarly, taking advantage of the fact that
5256 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5258 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5259 return apply_distributive_law
5260 (gen_binary (XOR
, mode
,
5261 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5262 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5265 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5266 return apply_distributive_law
5267 (gen_binary (XOR
, mode
,
5268 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5269 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5273 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5274 if (GET_CODE (op1
) == CONST_INT
5275 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5276 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5279 /* Convert (A & B) | A to A. */
5280 if (GET_CODE (op0
) == AND
5281 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5282 || rtx_equal_p (XEXP (op0
, 1), op1
))
5283 && ! side_effects_p (XEXP (op0
, 0))
5284 && ! side_effects_p (XEXP (op0
, 1)))
5287 /* If we have (ior (and A B) C), apply the distributive law and then
5288 the inverse distributive law to see if things simplify. */
5290 if (GET_CODE (op0
) == AND
)
5292 x
= apply_distributive_law
5293 (gen_binary (AND
, mode
,
5294 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5295 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5298 if (GET_CODE (x
) != IOR
)
5302 if (GET_CODE (op1
) == AND
)
5304 x
= apply_distributive_law
5305 (gen_binary (AND
, mode
,
5306 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5307 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5310 if (GET_CODE (x
) != IOR
)
5314 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5315 mode size to (rotate A CX). */
5317 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5318 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5319 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5320 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5321 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5322 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5323 == GET_MODE_BITSIZE (mode
)))
5324 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5325 (GET_CODE (op0
) == ASHIFT
5326 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5328 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5329 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5330 does not affect any of the bits in OP1, it can really be done
5331 as a PLUS and we can associate. We do this by seeing if OP1
5332 can be safely shifted left C bits. */
5333 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5334 && GET_CODE (XEXP (op0
, 0)) == PLUS
5335 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5336 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5337 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5339 int count
= INTVAL (XEXP (op0
, 1));
5340 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5342 if (mask
>> count
== INTVAL (op1
)
5343 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5345 SUBST (XEXP (XEXP (op0
, 0), 1),
5346 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5353 /* If we are XORing two things that have no bits in common,
5354 convert them into an IOR. This helps to detect rotation encoded
5355 using those methods and possibly other simplifications. */
5357 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5358 && (nonzero_bits (op0
, mode
)
5359 & nonzero_bits (op1
, mode
)) == 0)
5360 return (gen_binary (IOR
, mode
, op0
, op1
));
5362 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5363 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5366 int num_negated
= 0;
5368 if (GET_CODE (op0
) == NOT
)
5369 num_negated
++, op0
= XEXP (op0
, 0);
5370 if (GET_CODE (op1
) == NOT
)
5371 num_negated
++, op1
= XEXP (op1
, 0);
5373 if (num_negated
== 2)
5375 SUBST (XEXP (x
, 0), op0
);
5376 SUBST (XEXP (x
, 1), op1
);
5378 else if (num_negated
== 1)
5380 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5384 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5385 correspond to a machine insn or result in further simplifications
5386 if B is a constant. */
5388 if (GET_CODE (op0
) == AND
5389 && rtx_equal_p (XEXP (op0
, 1), op1
)
5390 && ! side_effects_p (op1
))
5391 return gen_binary (AND
, mode
,
5392 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5395 else if (GET_CODE (op0
) == AND
5396 && rtx_equal_p (XEXP (op0
, 0), op1
)
5397 && ! side_effects_p (op1
))
5398 return gen_binary (AND
, mode
,
5399 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5402 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5403 comparison if STORE_FLAG_VALUE is 1. */
5404 if (STORE_FLAG_VALUE
== 1
5405 && op1
== const1_rtx
5406 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5407 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5411 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5412 is (lt foo (const_int 0)), so we can perform the above
5413 simplification if STORE_FLAG_VALUE is 1. */
5415 if (STORE_FLAG_VALUE
== 1
5416 && op1
== const1_rtx
5417 && GET_CODE (op0
) == LSHIFTRT
5418 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5419 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5420 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5422 /* (xor (comparison foo bar) (const_int sign-bit))
5423 when STORE_FLAG_VALUE is the sign bit. */
5424 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5425 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5426 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5427 && op1
== const_true_rtx
5428 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5429 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5442 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5443 operations" because they can be replaced with two more basic operations.
5444 ZERO_EXTEND is also considered "compound" because it can be replaced with
5445 an AND operation, which is simpler, though only one operation.
5447 The function expand_compound_operation is called with an rtx expression
5448 and will convert it to the appropriate shifts and AND operations,
5449 simplifying at each stage.
5451 The function make_compound_operation is called to convert an expression
5452 consisting of shifts and ANDs into the equivalent compound expression.
5453 It is the inverse of this function, loosely speaking. */
5456 expand_compound_operation (x
)
5459 unsigned HOST_WIDE_INT pos
= 0, len
;
5461 unsigned int modewidth
;
5464 switch (GET_CODE (x
))
5469 /* We can't necessarily use a const_int for a multiword mode;
5470 it depends on implicitly extending the value.
5471 Since we don't know the right way to extend it,
5472 we can't tell whether the implicit way is right.
5474 Even for a mode that is no wider than a const_int,
5475 we can't win, because we need to sign extend one of its bits through
5476 the rest of it, and we don't know which bit. */
5477 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5480 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5481 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5482 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5483 reloaded. If not for that, MEM's would very rarely be safe.
5485 Reject MODEs bigger than a word, because we might not be able
5486 to reference a two-register group starting with an arbitrary register
5487 (and currently gen_lowpart might crash for a SUBREG). */
5489 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5492 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5493 /* If the inner object has VOIDmode (the only way this can happen
5494 is if it is a ASM_OPERANDS), we can't do anything since we don't
5495 know how much masking to do. */
5504 /* If the operand is a CLOBBER, just return it. */
5505 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5508 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5509 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5510 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5513 len
= INTVAL (XEXP (x
, 1));
5514 pos
= INTVAL (XEXP (x
, 2));
5516 /* If this goes outside the object being extracted, replace the object
5517 with a (use (mem ...)) construct that only combine understands
5518 and is used only for this purpose. */
5519 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5520 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5522 if (BITS_BIG_ENDIAN
)
5523 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5530 /* Convert sign extension to zero extension, if we know that the high
5531 bit is not set, as this is easier to optimize. It will be converted
5532 back to cheaper alternative in make_extraction. */
5533 if (GET_CODE (x
) == SIGN_EXTEND
5534 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5535 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5536 & ~(((unsigned HOST_WIDE_INT
)
5537 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5541 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5542 return expand_compound_operation (temp
);
5545 /* We can optimize some special cases of ZERO_EXTEND. */
5546 if (GET_CODE (x
) == ZERO_EXTEND
)
5548 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5549 know that the last value didn't have any inappropriate bits
5551 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5552 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5553 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5554 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5555 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5556 return XEXP (XEXP (x
, 0), 0);
5558 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5559 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5560 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5561 && subreg_lowpart_p (XEXP (x
, 0))
5562 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5563 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5564 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5565 return SUBREG_REG (XEXP (x
, 0));
5567 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5568 is a comparison and STORE_FLAG_VALUE permits. This is like
5569 the first case, but it works even when GET_MODE (x) is larger
5570 than HOST_WIDE_INT. */
5571 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5572 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5573 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5574 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5575 <= HOST_BITS_PER_WIDE_INT
)
5576 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5577 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5578 return XEXP (XEXP (x
, 0), 0);
5580 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5581 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5582 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5583 && subreg_lowpart_p (XEXP (x
, 0))
5584 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5585 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5586 <= HOST_BITS_PER_WIDE_INT
)
5587 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5588 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5589 return SUBREG_REG (XEXP (x
, 0));
5593 /* If we reach here, we want to return a pair of shifts. The inner
5594 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5595 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5596 logical depending on the value of UNSIGNEDP.
5598 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5599 converted into an AND of a shift.
5601 We must check for the case where the left shift would have a negative
5602 count. This can happen in a case like (x >> 31) & 255 on machines
5603 that can't shift by a constant. On those machines, we would first
5604 combine the shift with the AND to produce a variable-position
5605 extraction. Then the constant of 31 would be substituted in to produce
5606 a such a position. */
5608 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5609 if (modewidth
+ len
>= pos
)
5610 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5612 simplify_shift_const (NULL_RTX
, ASHIFT
,
5615 modewidth
- pos
- len
),
5618 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5619 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5620 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5623 ((HOST_WIDE_INT
) 1 << len
) - 1);
5625 /* Any other cases we can't handle. */
5628 /* If we couldn't do this for some reason, return the original
5630 if (GET_CODE (tem
) == CLOBBER
)
5636 /* X is a SET which contains an assignment of one object into
5637 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5638 or certain SUBREGS). If possible, convert it into a series of
5641 We half-heartedly support variable positions, but do not at all
5642 support variable lengths. */
5645 expand_field_assignment (x
)
5649 rtx pos
; /* Always counts from low bit. */
5652 enum machine_mode compute_mode
;
5654 /* Loop until we find something we can't simplify. */
5657 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5658 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5660 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5662 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5663 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5664 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5666 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5667 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5669 inner
= XEXP (SET_DEST (x
), 0);
5670 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5671 pos
= XEXP (SET_DEST (x
), 2);
5673 /* If the position is constant and spans the width of INNER,
5674 surround INNER with a USE to indicate this. */
5675 if (GET_CODE (pos
) == CONST_INT
5676 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5677 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5679 if (BITS_BIG_ENDIAN
)
5681 if (GET_CODE (pos
) == CONST_INT
)
5682 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5684 else if (GET_CODE (pos
) == MINUS
5685 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5686 && (INTVAL (XEXP (pos
, 1))
5687 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5688 /* If position is ADJUST - X, new position is X. */
5689 pos
= XEXP (pos
, 0);
5691 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5692 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5698 /* A SUBREG between two modes that occupy the same numbers of words
5699 can be done by moving the SUBREG to the source. */
5700 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5701 /* We need SUBREGs to compute nonzero_bits properly. */
5702 && nonzero_sign_valid
5703 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5704 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5705 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5706 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5708 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5709 gen_lowpart_for_combine
5710 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5717 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5718 inner
= SUBREG_REG (inner
);
5720 compute_mode
= GET_MODE (inner
);
5722 /* Don't attempt bitwise arithmetic on non-integral modes. */
5723 if (! INTEGRAL_MODE_P (compute_mode
))
5725 enum machine_mode imode
;
5727 /* Something is probably seriously wrong if this matches. */
5728 if (! FLOAT_MODE_P (compute_mode
))
5731 /* Try to find an integral mode to pun with. */
5732 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5733 if (imode
== BLKmode
)
5736 compute_mode
= imode
;
5737 inner
= gen_lowpart_for_combine (imode
, inner
);
5740 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5741 if (len
< HOST_BITS_PER_WIDE_INT
)
5742 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5746 /* Now compute the equivalent expression. Make a copy of INNER
5747 for the SET_DEST in case it is a MEM into which we will substitute;
5748 we don't want shared RTL in that case. */
5750 (VOIDmode
, copy_rtx (inner
),
5751 gen_binary (IOR
, compute_mode
,
5752 gen_binary (AND
, compute_mode
,
5753 simplify_gen_unary (NOT
, compute_mode
,
5759 gen_binary (ASHIFT
, compute_mode
,
5760 gen_binary (AND
, compute_mode
,
5761 gen_lowpart_for_combine
5762 (compute_mode
, SET_SRC (x
)),
5770 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5771 it is an RTX that represents a variable starting position; otherwise,
5772 POS is the (constant) starting bit position (counted from the LSB).
5774 INNER may be a USE. This will occur when we started with a bitfield
5775 that went outside the boundary of the object in memory, which is
5776 allowed on most machines. To isolate this case, we produce a USE
5777 whose mode is wide enough and surround the MEM with it. The only
5778 code that understands the USE is this routine. If it is not removed,
5779 it will cause the resulting insn not to match.
5781 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5784 IN_DEST is non-zero if this is a reference in the destination of a
5785 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5786 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5789 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5790 ZERO_EXTRACT should be built even for bits starting at bit 0.
5792 MODE is the desired mode of the result (if IN_DEST == 0).
5794 The result is an RTX for the extraction or NULL_RTX if the target
5798 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5799 unsignedp
, in_dest
, in_compare
)
5800 enum machine_mode mode
;
5804 unsigned HOST_WIDE_INT len
;
5806 int in_dest
, in_compare
;
5808 /* This mode describes the size of the storage area
5809 to fetch the overall value from. Within that, we
5810 ignore the POS lowest bits, etc. */
5811 enum machine_mode is_mode
= GET_MODE (inner
);
5812 enum machine_mode inner_mode
;
5813 enum machine_mode wanted_inner_mode
= byte_mode
;
5814 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5815 enum machine_mode pos_mode
= word_mode
;
5816 enum machine_mode extraction_mode
= word_mode
;
5817 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5820 rtx orig_pos_rtx
= pos_rtx
;
5821 HOST_WIDE_INT orig_pos
;
5823 /* Get some information about INNER and get the innermost object. */
5824 if (GET_CODE (inner
) == USE
)
5825 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5826 /* We don't need to adjust the position because we set up the USE
5827 to pretend that it was a full-word object. */
5828 spans_byte
= 1, inner
= XEXP (inner
, 0);
5829 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5831 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5832 consider just the QI as the memory to extract from.
5833 The subreg adds or removes high bits; its mode is
5834 irrelevant to the meaning of this extraction,
5835 since POS and LEN count from the lsb. */
5836 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5837 is_mode
= GET_MODE (SUBREG_REG (inner
));
5838 inner
= SUBREG_REG (inner
);
5841 inner_mode
= GET_MODE (inner
);
5843 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5844 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5846 /* See if this can be done without an extraction. We never can if the
5847 width of the field is not the same as that of some integer mode. For
5848 registers, we can only avoid the extraction if the position is at the
5849 low-order bit and this is either not in the destination or we have the
5850 appropriate STRICT_LOW_PART operation available.
5852 For MEM, we can avoid an extract if the field starts on an appropriate
5853 boundary and we can change the mode of the memory reference. However,
5854 we cannot directly access the MEM if we have a USE and the underlying
5855 MEM is not TMODE. This combination means that MEM was being used in a
5856 context where bits outside its mode were being referenced; that is only
5857 valid in bit-field insns. */
5859 if (tmode
!= BLKmode
5860 && ! (spans_byte
&& inner_mode
!= tmode
)
5861 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5862 && GET_CODE (inner
) != MEM
5864 || (GET_CODE (inner
) == REG
5865 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5866 != CODE_FOR_nothing
))))
5867 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5869 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5870 : BITS_PER_UNIT
)) == 0
5871 /* We can't do this if we are widening INNER_MODE (it
5872 may not be aligned, for one thing). */
5873 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5874 && (inner_mode
== tmode
5875 || (! mode_dependent_address_p (XEXP (inner
, 0))
5876 && ! MEM_VOLATILE_P (inner
))))))
5878 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5879 field. If the original and current mode are the same, we need not
5880 adjust the offset. Otherwise, we do if bytes big endian.
5882 If INNER is not a MEM, get a piece consisting of just the field
5883 of interest (in this case POS % BITS_PER_WORD must be 0). */
5885 if (GET_CODE (inner
) == MEM
)
5888 /* POS counts from lsb, but make OFFSET count in memory order. */
5889 if (BYTES_BIG_ENDIAN
)
5890 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5892 offset
= pos
/ BITS_PER_UNIT
;
5894 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
5895 MEM_COPY_ATTRIBUTES (new, inner
);
5897 else if (GET_CODE (inner
) == REG
)
5899 /* We can't call gen_lowpart_for_combine here since we always want
5900 a SUBREG and it would sometimes return a new hard register. */
5901 if (tmode
!= inner_mode
)
5903 int final_word
= pos
/ BITS_PER_WORD
;
5905 if (WORDS_BIG_ENDIAN
5906 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
5907 final_word
= ((GET_MODE_SIZE (inner_mode
)
5908 - GET_MODE_SIZE (tmode
))
5909 / UNITS_PER_WORD
) - final_word
;
5911 final_word
*= UNITS_PER_WORD
;
5912 if (BYTES_BIG_ENDIAN
&&
5913 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
5914 final_word
+= (GET_MODE_SIZE (inner_mode
)
5915 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
5917 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
5923 new = force_to_mode (inner
, tmode
,
5924 len
>= HOST_BITS_PER_WIDE_INT
5925 ? ~(unsigned HOST_WIDE_INT
) 0
5926 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5929 /* If this extraction is going into the destination of a SET,
5930 make a STRICT_LOW_PART unless we made a MEM. */
5933 return (GET_CODE (new) == MEM
? new
5934 : (GET_CODE (new) != SUBREG
5935 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5936 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
5941 /* If we know that no extraneous bits are set, and that the high
5942 bit is not set, convert the extraction to the cheaper of
5943 sign and zero extension, that are equivalent in these cases. */
5944 if (flag_expensive_optimizations
5945 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5946 && ((nonzero_bits (new, tmode
)
5947 & ~(((unsigned HOST_WIDE_INT
)
5948 GET_MODE_MASK (tmode
))
5952 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5953 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5955 /* Prefer ZERO_EXTENSION, since it gives more information to
5957 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
5962 /* Otherwise, sign- or zero-extend unless we already are in the
5965 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5969 /* Unless this is a COMPARE or we have a funny memory reference,
5970 don't do anything with zero-extending field extracts starting at
5971 the low-order bit since they are simple AND operations. */
5972 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5973 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5976 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5977 we would be spanning bytes or if the position is not a constant and the
5978 length is not 1. In all other cases, we would only be going outside
5979 our object in cases when an original shift would have been
5981 if (! spans_byte
&& GET_CODE (inner
) == MEM
5982 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5983 || (pos_rtx
!= 0 && len
!= 1)))
5986 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5987 and the mode for the result. */
5991 wanted_inner_reg_mode
5992 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
5993 if (wanted_inner_reg_mode
== VOIDmode
)
5994 wanted_inner_reg_mode
= word_mode
;
5996 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
5997 if (pos_mode
== VOIDmode
)
5998 pos_mode
= word_mode
;
6000 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6001 if (extraction_mode
== VOIDmode
)
6002 extraction_mode
= word_mode
;
6007 if (! in_dest
&& unsignedp
)
6009 wanted_inner_reg_mode
6010 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6011 if (wanted_inner_reg_mode
== VOIDmode
)
6012 wanted_inner_reg_mode
= word_mode
;
6014 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6015 if (pos_mode
== VOIDmode
)
6016 pos_mode
= word_mode
;
6018 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6019 if (extraction_mode
== VOIDmode
)
6020 extraction_mode
= word_mode
;
6025 if (! in_dest
&& ! unsignedp
)
6027 wanted_inner_reg_mode
6028 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6029 if (wanted_inner_reg_mode
== VOIDmode
)
6030 wanted_inner_reg_mode
= word_mode
;
6032 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6033 if (pos_mode
== VOIDmode
)
6034 pos_mode
= word_mode
;
6036 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6037 if (extraction_mode
== VOIDmode
)
6038 extraction_mode
= word_mode
;
6042 /* Never narrow an object, since that might not be safe. */
6044 if (mode
!= VOIDmode
6045 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6046 extraction_mode
= mode
;
6048 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6049 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6050 pos_mode
= GET_MODE (pos_rtx
);
6052 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6053 if we have to change the mode of memory and cannot, the desired mode is
6055 if (GET_CODE (inner
) != MEM
)
6056 wanted_inner_mode
= wanted_inner_reg_mode
;
6057 else if (inner_mode
!= wanted_inner_mode
6058 && (mode_dependent_address_p (XEXP (inner
, 0))
6059 || MEM_VOLATILE_P (inner
)))
6060 wanted_inner_mode
= extraction_mode
;
6064 if (BITS_BIG_ENDIAN
)
6066 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6067 BITS_BIG_ENDIAN style. If position is constant, compute new
6068 position. Otherwise, build subtraction.
6069 Note that POS is relative to the mode of the original argument.
6070 If it's a MEM we need to recompute POS relative to that.
6071 However, if we're extracting from (or inserting into) a register,
6072 we want to recompute POS relative to wanted_inner_mode. */
6073 int width
= (GET_CODE (inner
) == MEM
6074 ? GET_MODE_BITSIZE (is_mode
)
6075 : GET_MODE_BITSIZE (wanted_inner_mode
));
6078 pos
= width
- len
- pos
;
6081 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6082 /* POS may be less than 0 now, but we check for that below.
6083 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6086 /* If INNER has a wider mode, make it smaller. If this is a constant
6087 extract, try to adjust the byte to point to the byte containing
6089 if (wanted_inner_mode
!= VOIDmode
6090 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6091 && ((GET_CODE (inner
) == MEM
6092 && (inner_mode
== wanted_inner_mode
6093 || (! mode_dependent_address_p (XEXP (inner
, 0))
6094 && ! MEM_VOLATILE_P (inner
))))))
6098 /* The computations below will be correct if the machine is big
6099 endian in both bits and bytes or little endian in bits and bytes.
6100 If it is mixed, we must adjust. */
6102 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6103 adjust OFFSET to compensate. */
6104 if (BYTES_BIG_ENDIAN
6106 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6107 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6109 /* If this is a constant position, we can move to the desired byte. */
6112 offset
+= pos
/ BITS_PER_UNIT
;
6113 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6116 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6118 && is_mode
!= wanted_inner_mode
)
6119 offset
= (GET_MODE_SIZE (is_mode
)
6120 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6122 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6124 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6125 plus_constant (XEXP (inner
, 0), offset
));
6127 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6132 /* If INNER is not memory, we can always get it into the proper mode. If we
6133 are changing its mode, POS must be a constant and smaller than the size
6135 else if (GET_CODE (inner
) != MEM
)
6137 if (GET_MODE (inner
) != wanted_inner_mode
6139 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6142 inner
= force_to_mode (inner
, wanted_inner_mode
,
6144 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6145 ? ~(unsigned HOST_WIDE_INT
) 0
6146 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6151 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6152 have to zero extend. Otherwise, we can just use a SUBREG. */
6154 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6156 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6158 /* If we know that no extraneous bits are set, and that the high
6159 bit is not set, convert extraction to cheaper one - eighter
6160 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6162 if (flag_expensive_optimizations
6163 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6164 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6165 & ~(((unsigned HOST_WIDE_INT
)
6166 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6170 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6172 /* Prefer ZERO_EXTENSION, since it gives more information to
6174 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6179 else if (pos_rtx
!= 0
6180 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6181 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6183 /* Make POS_RTX unless we already have it and it is correct. If we don't
6184 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6186 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6187 pos_rtx
= orig_pos_rtx
;
6189 else if (pos_rtx
== 0)
6190 pos_rtx
= GEN_INT (pos
);
6192 /* Make the required operation. See if we can use existing rtx. */
6193 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6194 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6196 new = gen_lowpart_for_combine (mode
, new);
6201 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6202 with any other operations in X. Return X without that shift if so. */
6205 extract_left_shift (x
, count
)
6209 enum rtx_code code
= GET_CODE (x
);
6210 enum machine_mode mode
= GET_MODE (x
);
6216 /* This is the shift itself. If it is wide enough, we will return
6217 either the value being shifted if the shift count is equal to
6218 COUNT or a shift for the difference. */
6219 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6220 && INTVAL (XEXP (x
, 1)) >= count
)
6221 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6222 INTVAL (XEXP (x
, 1)) - count
);
6226 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6227 return simplify_gen_unary (code
, mode
, tem
, mode
);
6231 case PLUS
: case IOR
: case XOR
: case AND
:
6232 /* If we can safely shift this constant and we find the inner shift,
6233 make a new operation. */
6234 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6235 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6236 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6237 return gen_binary (code
, mode
, tem
,
6238 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6249 /* Look at the expression rooted at X. Look for expressions
6250 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6251 Form these expressions.
6253 Return the new rtx, usually just X.
6255 Also, for machines like the Vax that don't have logical shift insns,
6256 try to convert logical to arithmetic shift operations in cases where
6257 they are equivalent. This undoes the canonicalizations to logical
6258 shifts done elsewhere.
6260 We try, as much as possible, to re-use rtl expressions to save memory.
6262 IN_CODE says what kind of expression we are processing. Normally, it is
6263 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6264 being kludges), it is MEM. When processing the arguments of a comparison
6265 or a COMPARE against zero, it is COMPARE. */
6268 make_compound_operation (x
, in_code
)
6270 enum rtx_code in_code
;
6272 enum rtx_code code
= GET_CODE (x
);
6273 enum machine_mode mode
= GET_MODE (x
);
6274 int mode_width
= GET_MODE_BITSIZE (mode
);
6276 enum rtx_code next_code
;
6282 /* Select the code to be used in recursive calls. Once we are inside an
6283 address, we stay there. If we have a comparison, set to COMPARE,
6284 but once inside, go back to our default of SET. */
6286 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6287 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6288 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6289 : in_code
== COMPARE
? SET
: in_code
);
6291 /* Process depending on the code of this operation. If NEW is set
6292 non-zero, it will be returned. */
6297 /* Convert shifts by constants into multiplications if inside
6299 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6300 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6301 && INTVAL (XEXP (x
, 1)) >= 0)
6303 new = make_compound_operation (XEXP (x
, 0), next_code
);
6304 new = gen_rtx_MULT (mode
, new,
6305 GEN_INT ((HOST_WIDE_INT
) 1
6306 << INTVAL (XEXP (x
, 1))));
6311 /* If the second operand is not a constant, we can't do anything
6313 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6316 /* If the constant is a power of two minus one and the first operand
6317 is a logical right shift, make an extraction. */
6318 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6319 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6321 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6322 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6323 0, in_code
== COMPARE
);
6326 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6327 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6328 && subreg_lowpart_p (XEXP (x
, 0))
6329 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6330 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6332 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6334 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6335 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6336 0, in_code
== COMPARE
);
6338 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6339 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6340 || GET_CODE (XEXP (x
, 0)) == IOR
)
6341 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6342 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6343 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6345 /* Apply the distributive law, and then try to make extractions. */
6346 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6347 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6349 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6351 new = make_compound_operation (new, in_code
);
6354 /* If we are have (and (rotate X C) M) and C is larger than the number
6355 of bits in M, this is an extraction. */
6357 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6358 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6359 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6360 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6362 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6363 new = make_extraction (mode
, new,
6364 (GET_MODE_BITSIZE (mode
)
6365 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6366 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6369 /* On machines without logical shifts, if the operand of the AND is
6370 a logical shift and our mask turns off all the propagated sign
6371 bits, we can replace the logical shift with an arithmetic shift. */
6372 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6373 && (lshr_optab
->handlers
[(int) mode
].insn_code
6374 == CODE_FOR_nothing
)
6375 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6376 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6377 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6378 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6379 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6381 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6383 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6384 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6386 gen_rtx_ASHIFTRT (mode
,
6387 make_compound_operation
6388 (XEXP (XEXP (x
, 0), 0), next_code
),
6389 XEXP (XEXP (x
, 0), 1)));
6392 /* If the constant is one less than a power of two, this might be
6393 representable by an extraction even if no shift is present.
6394 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6395 we are in a COMPARE. */
6396 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6397 new = make_extraction (mode
,
6398 make_compound_operation (XEXP (x
, 0),
6400 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6402 /* If we are in a comparison and this is an AND with a power of two,
6403 convert this into the appropriate bit extract. */
6404 else if (in_code
== COMPARE
6405 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6406 new = make_extraction (mode
,
6407 make_compound_operation (XEXP (x
, 0),
6409 i
, NULL_RTX
, 1, 1, 0, 1);
6414 /* If the sign bit is known to be zero, replace this with an
6415 arithmetic shift. */
6416 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6417 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6418 && mode_width
<= HOST_BITS_PER_WIDE_INT
6419 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6421 new = gen_rtx_ASHIFTRT (mode
,
6422 make_compound_operation (XEXP (x
, 0),
6428 /* ... fall through ... */
6434 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6435 this is a SIGN_EXTRACT. */
6436 if (GET_CODE (rhs
) == CONST_INT
6437 && GET_CODE (lhs
) == ASHIFT
6438 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6439 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6441 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6442 new = make_extraction (mode
, new,
6443 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6444 NULL_RTX
, mode_width
- INTVAL (rhs
),
6445 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6449 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6450 If so, try to merge the shifts into a SIGN_EXTEND. We could
6451 also do this for some cases of SIGN_EXTRACT, but it doesn't
6452 seem worth the effort; the case checked for occurs on Alpha. */
6454 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6455 && ! (GET_CODE (lhs
) == SUBREG
6456 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6457 && GET_CODE (rhs
) == CONST_INT
6458 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6459 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6460 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6461 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6462 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6467 /* Call ourselves recursively on the inner expression. If we are
6468 narrowing the object and it has a different RTL code from
6469 what it originally did, do this SUBREG as a force_to_mode. */
6471 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6472 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6473 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6474 && subreg_lowpart_p (x
))
6476 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6479 /* If we have something other than a SUBREG, we might have
6480 done an expansion, so rerun outselves. */
6481 if (GET_CODE (newer
) != SUBREG
)
6482 newer
= make_compound_operation (newer
, in_code
);
6487 /* If this is a paradoxical subreg, and the new code is a sign or
6488 zero extension, omit the subreg and widen the extension. If it
6489 is a regular subreg, we can still get rid of the subreg by not
6490 widening so much, or in fact removing the extension entirely. */
6491 if ((GET_CODE (tem
) == SIGN_EXTEND
6492 || GET_CODE (tem
) == ZERO_EXTEND
)
6493 && subreg_lowpart_p (x
))
6495 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6496 || (GET_MODE_SIZE (mode
) >
6497 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6498 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6500 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6511 x
= gen_lowpart_for_combine (mode
, new);
6512 code
= GET_CODE (x
);
6515 /* Now recursively process each operand of this operation. */
6516 fmt
= GET_RTX_FORMAT (code
);
6517 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6520 new = make_compound_operation (XEXP (x
, i
), next_code
);
6521 SUBST (XEXP (x
, i
), new);
6527 /* Given M see if it is a value that would select a field of bits
6528 within an item, but not the entire word. Return -1 if not.
6529 Otherwise, return the starting position of the field, where 0 is the
6532 *PLEN is set to the length of the field. */
6535 get_pos_from_mask (m
, plen
)
6536 unsigned HOST_WIDE_INT m
;
6537 unsigned HOST_WIDE_INT
*plen
;
6539 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6540 int pos
= exact_log2 (m
& -m
);
6546 /* Now shift off the low-order zero bits and see if we have a power of
6548 len
= exact_log2 ((m
>> pos
) + 1);
6557 /* See if X can be simplified knowing that we will only refer to it in
6558 MODE and will only refer to those bits that are nonzero in MASK.
6559 If other bits are being computed or if masking operations are done
6560 that select a superset of the bits in MASK, they can sometimes be
6563 Return a possibly simplified expression, but always convert X to
6564 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6566 Also, if REG is non-zero and X is a register equal in value to REG,
6569 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6570 are all off in X. This is used when X will be complemented, by either
6571 NOT, NEG, or XOR. */
6574 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6576 enum machine_mode mode
;
6577 unsigned HOST_WIDE_INT mask
;
6581 enum rtx_code code
= GET_CODE (x
);
6582 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6583 enum machine_mode op_mode
;
6584 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6587 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6588 code below will do the wrong thing since the mode of such an
6589 expression is VOIDmode.
6591 Also do nothing if X is a CLOBBER; this can happen if X was
6592 the return value from a call to gen_lowpart_for_combine. */
6593 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6596 /* We want to perform the operation is its present mode unless we know
6597 that the operation is valid in MODE, in which case we do the operation
6599 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6600 && code_to_optab
[(int) code
] != 0
6601 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6602 != CODE_FOR_nothing
))
6603 ? mode
: GET_MODE (x
));
6605 /* It is not valid to do a right-shift in a narrower mode
6606 than the one it came in with. */
6607 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6608 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6609 op_mode
= GET_MODE (x
);
6611 /* Truncate MASK to fit OP_MODE. */
6613 mask
&= GET_MODE_MASK (op_mode
);
6615 /* When we have an arithmetic operation, or a shift whose count we
6616 do not know, we need to assume that all bit the up to the highest-order
6617 bit in MASK will be needed. This is how we form such a mask. */
6619 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6620 ? GET_MODE_MASK (op_mode
)
6621 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6624 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6626 /* Determine what bits of X are guaranteed to be (non)zero. */
6627 nonzero
= nonzero_bits (x
, mode
);
6629 /* If none of the bits in X are needed, return a zero. */
6630 if (! just_select
&& (nonzero
& mask
) == 0)
6633 /* If X is a CONST_INT, return a new one. Do this here since the
6634 test below will fail. */
6635 if (GET_CODE (x
) == CONST_INT
)
6637 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6638 int width
= GET_MODE_BITSIZE (mode
);
6640 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6641 number, sign extend it. */
6642 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6643 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6644 cval
|= (HOST_WIDE_INT
) -1 << width
;
6646 return GEN_INT (cval
);
6649 /* If X is narrower than MODE and we want all the bits in X's mode, just
6650 get X in the proper mode. */
6651 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6652 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6653 return gen_lowpart_for_combine (mode
, x
);
6655 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6656 MASK are already known to be zero in X, we need not do anything. */
6657 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6663 /* If X is a (clobber (const_int)), return it since we know we are
6664 generating something that won't match. */
6668 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6669 spanned the boundary of the MEM. If we are now masking so it is
6670 within that boundary, we don't need the USE any more. */
6671 if (! BITS_BIG_ENDIAN
6672 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6673 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6680 x
= expand_compound_operation (x
);
6681 if (GET_CODE (x
) != code
)
6682 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6686 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6687 || rtx_equal_p (reg
, get_last_value (x
))))
6692 if (subreg_lowpart_p (x
)
6693 /* We can ignore the effect of this SUBREG if it narrows the mode or
6694 if the constant masks to zero all the bits the mode doesn't
6696 && ((GET_MODE_SIZE (GET_MODE (x
))
6697 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6699 & GET_MODE_MASK (GET_MODE (x
))
6700 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6701 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6705 /* If this is an AND with a constant, convert it into an AND
6706 whose constant is the AND of that constant with MASK. If it
6707 remains an AND of MASK, delete it since it is redundant. */
6709 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6711 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6712 mask
& INTVAL (XEXP (x
, 1)));
6714 /* If X is still an AND, see if it is an AND with a mask that
6715 is just some low-order bits. If so, and it is MASK, we don't
6718 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6719 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6722 /* If it remains an AND, try making another AND with the bits
6723 in the mode mask that aren't in MASK turned on. If the
6724 constant in the AND is wide enough, this might make a
6725 cheaper constant. */
6727 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6728 && GET_MODE_MASK (GET_MODE (x
)) != mask
6729 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6731 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6732 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6733 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6736 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6737 number, sign extend it. */
6738 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6739 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6740 cval
|= (HOST_WIDE_INT
) -1 << width
;
6742 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6743 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6753 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6754 low-order bits (as in an alignment operation) and FOO is already
6755 aligned to that boundary, mask C1 to that boundary as well.
6756 This may eliminate that PLUS and, later, the AND. */
6759 unsigned int width
= GET_MODE_BITSIZE (mode
);
6760 unsigned HOST_WIDE_INT smask
= mask
;
6762 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6763 number, sign extend it. */
6765 if (width
< HOST_BITS_PER_WIDE_INT
6766 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6767 smask
|= (HOST_WIDE_INT
) -1 << width
;
6769 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6770 && exact_log2 (- smask
) >= 0)
6774 && (XEXP (x
, 0) == stack_pointer_rtx
6775 || XEXP (x
, 0) == frame_pointer_rtx
))
6777 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6778 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6780 sp_mask
&= ~(sp_alignment
- 1);
6781 if ((sp_mask
& ~smask
) == 0
6782 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6783 return force_to_mode (plus_constant (XEXP (x
, 0),
6784 ((INTVAL (XEXP (x
, 1)) -
6785 STACK_BIAS
) & smask
)
6787 mode
, smask
, reg
, next_select
);
6790 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6791 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6792 return force_to_mode (plus_constant (XEXP (x
, 0),
6793 (INTVAL (XEXP (x
, 1))
6795 mode
, smask
, reg
, next_select
);
6799 /* ... fall through ... */
6802 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6803 most significant bit in MASK since carries from those bits will
6804 affect the bits we are interested in. */
6809 /* If X is (minus C Y) where C's least set bit is larger than any bit
6810 in the mask, then we may replace with (neg Y). */
6811 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6812 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6813 & -INTVAL (XEXP (x
, 0))))
6816 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6818 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6821 /* Similarly, if C contains every bit in the mask, then we may
6822 replace with (not Y). */
6823 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6824 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6825 == INTVAL (XEXP (x
, 0))))
6827 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6828 XEXP (x
, 1), GET_MODE (x
));
6829 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6837 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6838 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6839 operation which may be a bitfield extraction. Ensure that the
6840 constant we form is not wider than the mode of X. */
6842 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6843 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6844 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6845 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6846 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6847 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6848 + floor_log2 (INTVAL (XEXP (x
, 1))))
6849 < GET_MODE_BITSIZE (GET_MODE (x
)))
6850 && (INTVAL (XEXP (x
, 1))
6851 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6853 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6854 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6855 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6856 XEXP (XEXP (x
, 0), 0), temp
);
6857 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6858 XEXP (XEXP (x
, 0), 1));
6859 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6863 /* For most binary operations, just propagate into the operation and
6864 change the mode if we have an operation of that mode. */
6866 op0
= gen_lowpart_for_combine (op_mode
,
6867 force_to_mode (XEXP (x
, 0), mode
, mask
,
6869 op1
= gen_lowpart_for_combine (op_mode
,
6870 force_to_mode (XEXP (x
, 1), mode
, mask
,
6873 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6874 MASK since OP1 might have been sign-extended but we never want
6875 to turn on extra bits, since combine might have previously relied
6876 on them being off. */
6877 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6878 && (INTVAL (op1
) & mask
) != 0)
6879 op1
= GEN_INT (INTVAL (op1
) & mask
);
6881 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6882 x
= gen_binary (code
, op_mode
, op0
, op1
);
6886 /* For left shifts, do the same, but just for the first operand.
6887 However, we cannot do anything with shifts where we cannot
6888 guarantee that the counts are smaller than the size of the mode
6889 because such a count will have a different meaning in a
6892 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6893 && INTVAL (XEXP (x
, 1)) >= 0
6894 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6895 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6896 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6897 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6900 /* If the shift count is a constant and we can do arithmetic in
6901 the mode of the shift, refine which bits we need. Otherwise, use the
6902 conservative form of the mask. */
6903 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6904 && INTVAL (XEXP (x
, 1)) >= 0
6905 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6906 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6907 mask
>>= INTVAL (XEXP (x
, 1));
6911 op0
= gen_lowpart_for_combine (op_mode
,
6912 force_to_mode (XEXP (x
, 0), op_mode
,
6913 mask
, reg
, next_select
));
6915 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6916 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6920 /* Here we can only do something if the shift count is a constant,
6921 this shift constant is valid for the host, and we can do arithmetic
6924 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6925 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6926 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6928 rtx inner
= XEXP (x
, 0);
6929 unsigned HOST_WIDE_INT inner_mask
;
6931 /* Select the mask of the bits we need for the shift operand. */
6932 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6934 /* We can only change the mode of the shift if we can do arithmetic
6935 in the mode of the shift and INNER_MASK is no wider than the
6936 width of OP_MODE. */
6937 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6938 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
6939 op_mode
= GET_MODE (x
);
6941 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6943 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6944 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6947 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6948 shift and AND produces only copies of the sign bit (C2 is one less
6949 than a power of two), we can do this with just a shift. */
6951 if (GET_CODE (x
) == LSHIFTRT
6952 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6953 /* The shift puts one of the sign bit copies in the least significant
6955 && ((INTVAL (XEXP (x
, 1))
6956 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6957 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6958 && exact_log2 (mask
+ 1) >= 0
6959 /* Number of bits left after the shift must be more than the mask
6961 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
6962 <= GET_MODE_BITSIZE (GET_MODE (x
)))
6963 /* Must be more sign bit copies than the mask needs. */
6964 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6965 >= exact_log2 (mask
+ 1)))
6966 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6967 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6968 - exact_log2 (mask
+ 1)));
6973 /* If we are just looking for the sign bit, we don't need this shift at
6974 all, even if it has a variable count. */
6975 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6976 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6977 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6978 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6980 /* If this is a shift by a constant, get a mask that contains those bits
6981 that are not copies of the sign bit. We then have two cases: If
6982 MASK only includes those bits, this can be a logical shift, which may
6983 allow simplifications. If MASK is a single-bit field not within
6984 those bits, we are requesting a copy of the sign bit and hence can
6985 shift the sign bit to the appropriate location. */
6987 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6988 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6992 /* If the considered data is wider then HOST_WIDE_INT, we can't
6993 represent a mask for all its bits in a single scalar.
6994 But we only care about the lower bits, so calculate these. */
6996 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6998 nonzero
= ~(HOST_WIDE_INT
) 0;
7000 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7001 is the number of bits a full-width mask would have set.
7002 We need only shift if these are fewer than nonzero can
7003 hold. If not, we must keep all bits set in nonzero. */
7005 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7006 < HOST_BITS_PER_WIDE_INT
)
7007 nonzero
>>= INTVAL (XEXP (x
, 1))
7008 + HOST_BITS_PER_WIDE_INT
7009 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7013 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7014 nonzero
>>= INTVAL (XEXP (x
, 1));
7017 if ((mask
& ~nonzero
) == 0
7018 || (i
= exact_log2 (mask
)) >= 0)
7020 x
= simplify_shift_const
7021 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7022 i
< 0 ? INTVAL (XEXP (x
, 1))
7023 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7025 if (GET_CODE (x
) != ASHIFTRT
)
7026 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7030 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7031 even if the shift count isn't a constant. */
7033 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7037 /* If this is a zero- or sign-extension operation that just affects bits
7038 we don't care about, remove it. Be sure the call above returned
7039 something that is still a shift. */
7041 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7042 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7043 && INTVAL (XEXP (x
, 1)) >= 0
7044 && (INTVAL (XEXP (x
, 1))
7045 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7046 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7047 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7048 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7049 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7056 /* If the shift count is constant and we can do computations
7057 in the mode of X, compute where the bits we care about are.
7058 Otherwise, we can't do anything. Don't change the mode of
7059 the shift or propagate MODE into the shift, though. */
7060 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7061 && INTVAL (XEXP (x
, 1)) >= 0)
7063 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7064 GET_MODE (x
), GEN_INT (mask
),
7066 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7068 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7069 INTVAL (temp
), reg
, next_select
));
7074 /* If we just want the low-order bit, the NEG isn't needed since it
7075 won't change the low-order bit. */
7077 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7079 /* We need any bits less significant than the most significant bit in
7080 MASK since carries from those bits will affect the bits we are
7086 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7087 same as the XOR case above. Ensure that the constant we form is not
7088 wider than the mode of X. */
7090 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7091 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7092 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7093 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7094 < GET_MODE_BITSIZE (GET_MODE (x
)))
7095 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7097 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7098 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7099 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7101 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7104 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7105 use the full mask inside the NOT. */
7109 op0
= gen_lowpart_for_combine (op_mode
,
7110 force_to_mode (XEXP (x
, 0), mode
, mask
,
7112 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7113 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7117 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7118 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7119 which is equal to STORE_FLAG_VALUE. */
7120 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7121 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7122 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7123 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7128 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7129 written in a narrower mode. We play it safe and do not do so. */
7132 gen_lowpart_for_combine (GET_MODE (x
),
7133 force_to_mode (XEXP (x
, 1), mode
,
7134 mask
, reg
, next_select
)));
7136 gen_lowpart_for_combine (GET_MODE (x
),
7137 force_to_mode (XEXP (x
, 2), mode
,
7138 mask
, reg
,next_select
)));
7145 /* Ensure we return a value of the proper mode. */
7146 return gen_lowpart_for_combine (mode
, x
);
7149 /* Return nonzero if X is an expression that has one of two values depending on
7150 whether some other value is zero or nonzero. In that case, we return the
7151 value that is being tested, *PTRUE is set to the value if the rtx being
7152 returned has a nonzero value, and *PFALSE is set to the other alternative.
7154 If we return zero, we set *PTRUE and *PFALSE to X. */
7157 if_then_else_cond (x
, ptrue
, pfalse
)
7159 rtx
*ptrue
, *pfalse
;
7161 enum machine_mode mode
= GET_MODE (x
);
7162 enum rtx_code code
= GET_CODE (x
);
7163 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7164 unsigned HOST_WIDE_INT nz
;
7166 /* If we are comparing a value against zero, we are done. */
7167 if ((code
== NE
|| code
== EQ
)
7168 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7170 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7171 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7175 /* If this is a unary operation whose operand has one of two values, apply
7176 our opcode to compute those values. */
7177 else if (GET_RTX_CLASS (code
) == '1'
7178 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7180 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7181 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7182 GET_MODE (XEXP (x
, 0)));
7186 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7187 make can't possibly match and would suppress other optimizations. */
7188 else if (code
== COMPARE
)
7191 /* If this is a binary operation, see if either side has only one of two
7192 values. If either one does or if both do and they are conditional on
7193 the same value, compute the new true and false values. */
7194 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7195 || GET_RTX_CLASS (code
) == '<')
7197 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7198 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7200 if ((cond0
!= 0 || cond1
!= 0)
7201 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7203 /* If if_then_else_cond returned zero, then true/false are the
7204 same rtl. We must copy one of them to prevent invalid rtl
7207 true0
= copy_rtx (true0
);
7208 else if (cond1
== 0)
7209 true1
= copy_rtx (true1
);
7211 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7212 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7213 return cond0
? cond0
: cond1
;
7216 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7217 operands is zero when the other is non-zero, and vice-versa,
7218 and STORE_FLAG_VALUE is 1 or -1. */
7220 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7221 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7223 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7225 rtx op0
= XEXP (XEXP (x
, 0), 1);
7226 rtx op1
= XEXP (XEXP (x
, 1), 1);
7228 cond0
= XEXP (XEXP (x
, 0), 0);
7229 cond1
= XEXP (XEXP (x
, 1), 0);
7231 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7232 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7233 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7234 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7235 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7236 || ((swap_condition (GET_CODE (cond0
))
7237 == combine_reversed_comparison_code (cond1
))
7238 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7239 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7240 && ! side_effects_p (x
))
7242 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7243 *pfalse
= gen_binary (MULT
, mode
,
7245 ? simplify_gen_unary (NEG
, mode
, op1
,
7253 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7255 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7256 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7257 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7259 cond0
= XEXP (XEXP (x
, 0), 0);
7260 cond1
= XEXP (XEXP (x
, 1), 0);
7262 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7263 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7264 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7265 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7266 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7267 || ((swap_condition (GET_CODE (cond0
))
7268 == combine_reversed_comparison_code (cond1
))
7269 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7270 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7271 && ! side_effects_p (x
))
7273 *ptrue
= *pfalse
= const0_rtx
;
7279 else if (code
== IF_THEN_ELSE
)
7281 /* If we have IF_THEN_ELSE already, extract the condition and
7282 canonicalize it if it is NE or EQ. */
7283 cond0
= XEXP (x
, 0);
7284 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7285 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7286 return XEXP (cond0
, 0);
7287 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7289 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7290 return XEXP (cond0
, 0);
7296 /* If X is a SUBREG, we can narrow both the true and false values
7297 if the inner expression, if there is a condition. */
7298 else if (code
== SUBREG
7299 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7302 *ptrue
= simplify_gen_subreg (mode
, true0
,
7303 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7304 *pfalse
= simplify_gen_subreg (mode
, false0
,
7305 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7310 /* If X is a constant, this isn't special and will cause confusions
7311 if we treat it as such. Likewise if it is equivalent to a constant. */
7312 else if (CONSTANT_P (x
)
7313 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7316 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7317 will be least confusing to the rest of the compiler. */
7318 else if (mode
== BImode
)
7320 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7324 /* If X is known to be either 0 or -1, those are the true and
7325 false values when testing X. */
7326 else if (x
== constm1_rtx
|| x
== const0_rtx
7327 || (mode
!= VOIDmode
7328 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7330 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7334 /* Likewise for 0 or a single bit. */
7335 else if (mode
!= VOIDmode
7336 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7337 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7339 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7343 /* Otherwise fail; show no condition with true and false values the same. */
7344 *ptrue
= *pfalse
= x
;
7348 /* Return the value of expression X given the fact that condition COND
7349 is known to be true when applied to REG as its first operand and VAL
7350 as its second. X is known to not be shared and so can be modified in
7353 We only handle the simplest cases, and specifically those cases that
7354 arise with IF_THEN_ELSE expressions. */
7357 known_cond (x
, cond
, reg
, val
)
7362 enum rtx_code code
= GET_CODE (x
);
7367 if (side_effects_p (x
))
7370 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7372 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7375 /* If X is (abs REG) and we know something about REG's relationship
7376 with zero, we may be able to simplify this. */
7378 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7381 case GE
: case GT
: case EQ
:
7384 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7386 GET_MODE (XEXP (x
, 0)));
7391 /* The only other cases we handle are MIN, MAX, and comparisons if the
7392 operands are the same as REG and VAL. */
7394 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7396 if (rtx_equal_p (XEXP (x
, 0), val
))
7397 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7399 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7401 if (GET_RTX_CLASS (code
) == '<')
7403 if (comparison_dominates_p (cond
, code
))
7404 return const_true_rtx
;
7406 code
= combine_reversed_comparison_code (x
);
7408 && comparison_dominates_p (cond
, code
))
7413 else if (code
== SMAX
|| code
== SMIN
7414 || code
== UMIN
|| code
== UMAX
)
7416 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7418 /* Do not reverse the condition when it is NE or EQ.
7419 This is because we cannot conclude anything about
7420 the value of 'SMAX (x, y)' when x is not equal to y,
7421 but we can when x equals y. */
7422 if ((code
== SMAX
|| code
== UMAX
)
7423 && ! (cond
== EQ
|| cond
== NE
))
7424 cond
= reverse_condition (cond
);
7429 return unsignedp
? x
: XEXP (x
, 1);
7431 return unsignedp
? x
: XEXP (x
, 0);
7433 return unsignedp
? XEXP (x
, 1) : x
;
7435 return unsignedp
? XEXP (x
, 0) : x
;
7443 fmt
= GET_RTX_FORMAT (code
);
7444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7447 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7448 else if (fmt
[i
] == 'E')
7449 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7450 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7457 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7458 assignment as a field assignment. */
7461 rtx_equal_for_field_assignment_p (x
, y
)
7465 if (x
== y
|| rtx_equal_p (x
, y
))
7468 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7471 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7472 Note that all SUBREGs of MEM are paradoxical; otherwise they
7473 would have been rewritten. */
7474 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7475 && GET_CODE (SUBREG_REG (y
)) == MEM
7476 && rtx_equal_p (SUBREG_REG (y
),
7477 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7480 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7481 && GET_CODE (SUBREG_REG (x
)) == MEM
7482 && rtx_equal_p (SUBREG_REG (x
),
7483 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7486 /* We used to see if get_last_value of X and Y were the same but that's
7487 not correct. In one direction, we'll cause the assignment to have
7488 the wrong destination and in the case, we'll import a register into this
7489 insn that might have already have been dead. So fail if none of the
7490 above cases are true. */
7494 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7495 Return that assignment if so.
7497 We only handle the most common cases. */
7500 make_field_assignment (x
)
7503 rtx dest
= SET_DEST (x
);
7504 rtx src
= SET_SRC (x
);
7509 unsigned HOST_WIDE_INT len
;
7511 enum machine_mode mode
;
7513 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7514 a clear of a one-bit field. We will have changed it to
7515 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7518 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7519 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7520 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7521 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7523 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7526 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7530 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7531 && subreg_lowpart_p (XEXP (src
, 0))
7532 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7533 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7534 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7535 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7536 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7538 assign
= make_extraction (VOIDmode
, dest
, 0,
7539 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7542 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7546 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7548 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7549 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7550 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7552 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7555 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7559 /* The other case we handle is assignments into a constant-position
7560 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7561 a mask that has all one bits except for a group of zero bits and
7562 OTHER is known to have zeros where C1 has ones, this is such an
7563 assignment. Compute the position and length from C1. Shift OTHER
7564 to the appropriate position, force it to the required mode, and
7565 make the extraction. Check for the AND in both operands. */
7567 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7570 rhs
= expand_compound_operation (XEXP (src
, 0));
7571 lhs
= expand_compound_operation (XEXP (src
, 1));
7573 if (GET_CODE (rhs
) == AND
7574 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7575 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7576 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7577 else if (GET_CODE (lhs
) == AND
7578 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7579 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7580 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7584 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7585 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7586 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7587 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7590 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7594 /* The mode to use for the source is the mode of the assignment, or of
7595 what is inside a possible STRICT_LOW_PART. */
7596 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7597 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7599 /* Shift OTHER right POS places and make it the source, restricting it
7600 to the proper length and mode. */
7602 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7603 GET_MODE (src
), other
, pos
),
7605 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7606 ? ~(unsigned HOST_WIDE_INT
) 0
7607 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7610 return gen_rtx_SET (VOIDmode
, assign
, src
);
7613 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7617 apply_distributive_law (x
)
7620 enum rtx_code code
= GET_CODE (x
);
7621 rtx lhs
, rhs
, other
;
7623 enum rtx_code inner_code
;
7625 /* Distributivity is not true for floating point.
7626 It can change the value. So don't do it.
7627 -- rms and moshier@world.std.com. */
7628 if (FLOAT_MODE_P (GET_MODE (x
)))
7631 /* The outer operation can only be one of the following: */
7632 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7633 && code
!= PLUS
&& code
!= MINUS
)
7636 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7638 /* If either operand is a primitive we can't do anything, so get out
7640 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7641 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7644 lhs
= expand_compound_operation (lhs
);
7645 rhs
= expand_compound_operation (rhs
);
7646 inner_code
= GET_CODE (lhs
);
7647 if (inner_code
!= GET_CODE (rhs
))
7650 /* See if the inner and outer operations distribute. */
7657 /* These all distribute except over PLUS. */
7658 if (code
== PLUS
|| code
== MINUS
)
7663 if (code
!= PLUS
&& code
!= MINUS
)
7668 /* This is also a multiply, so it distributes over everything. */
7672 /* Non-paradoxical SUBREGs distributes over all operations, provided
7673 the inner modes and byte offsets are the same, this is an extraction
7674 of a low-order part, we don't convert an fp operation to int or
7675 vice versa, and we would not be converting a single-word
7676 operation into a multi-word operation. The latter test is not
7677 required, but it prevents generating unneeded multi-word operations.
7678 Some of the previous tests are redundant given the latter test, but
7679 are retained because they are required for correctness.
7681 We produce the result slightly differently in this case. */
7683 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7684 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7685 || ! subreg_lowpart_p (lhs
)
7686 || (GET_MODE_CLASS (GET_MODE (lhs
))
7687 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7688 || (GET_MODE_SIZE (GET_MODE (lhs
))
7689 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7690 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7693 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7694 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7695 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7701 /* Set LHS and RHS to the inner operands (A and B in the example
7702 above) and set OTHER to the common operand (C in the example).
7703 These is only one way to do this unless the inner operation is
7705 if (GET_RTX_CLASS (inner_code
) == 'c'
7706 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7707 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7708 else if (GET_RTX_CLASS (inner_code
) == 'c'
7709 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7710 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7711 else if (GET_RTX_CLASS (inner_code
) == 'c'
7712 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7713 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7714 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7715 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7719 /* Form the new inner operation, seeing if it simplifies first. */
7720 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7722 /* There is one exception to the general way of distributing:
7723 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7724 if (code
== XOR
&& inner_code
== IOR
)
7727 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7730 /* We may be able to continuing distributing the result, so call
7731 ourselves recursively on the inner operation before forming the
7732 outer operation, which we return. */
7733 return gen_binary (inner_code
, GET_MODE (x
),
7734 apply_distributive_law (tem
), other
);
7737 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7740 Return an equivalent form, if different from X. Otherwise, return X. If
7741 X is zero, we are to always construct the equivalent form. */
7744 simplify_and_const_int (x
, mode
, varop
, constop
)
7746 enum machine_mode mode
;
7748 unsigned HOST_WIDE_INT constop
;
7750 unsigned HOST_WIDE_INT nonzero
;
7753 /* Simplify VAROP knowing that we will be only looking at some of the
7755 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7757 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7758 CONST_INT, we are done. */
7759 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7762 /* See what bits may be nonzero in VAROP. Unlike the general case of
7763 a call to nonzero_bits, here we don't care about bits outside
7766 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7767 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7769 /* Turn off all bits in the constant that are known to already be zero.
7770 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7771 which is tested below. */
7775 /* If we don't have any bits left, return zero. */
7779 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7780 a power of two, we can replace this with a ASHIFT. */
7781 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7782 && (i
= exact_log2 (constop
)) >= 0)
7783 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7785 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7786 or XOR, then try to apply the distributive law. This may eliminate
7787 operations if either branch can be simplified because of the AND.
7788 It may also make some cases more complex, but those cases probably
7789 won't match a pattern either with or without this. */
7791 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7793 gen_lowpart_for_combine
7795 apply_distributive_law
7796 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7797 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7798 XEXP (varop
, 0), constop
),
7799 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7800 XEXP (varop
, 1), constop
))));
7802 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7803 if we already had one (just check for the simplest cases). */
7804 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7805 && GET_MODE (XEXP (x
, 0)) == mode
7806 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7807 varop
= XEXP (x
, 0);
7809 varop
= gen_lowpart_for_combine (mode
, varop
);
7811 /* If we can't make the SUBREG, try to return what we were given. */
7812 if (GET_CODE (varop
) == CLOBBER
)
7813 return x
? x
: varop
;
7815 /* If we are only masking insignificant bits, return VAROP. */
7816 if (constop
== nonzero
)
7819 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7820 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7821 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7825 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7826 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7827 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7829 SUBST (XEXP (x
, 0), varop
);
7835 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7836 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7837 is less useful. We can't allow both, because that results in exponential
7838 run time recursion. There is a nullstone testcase that triggered
7839 this. This macro avoids accidental uses of num_sign_bit_copies. */
7840 #define num_sign_bit_copies()
7842 /* Given an expression, X, compute which bits in X can be non-zero.
7843 We don't care about bits outside of those defined in MODE.
7845 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7846 a shift, AND, or zero_extract, we can do better. */
7848 static unsigned HOST_WIDE_INT
7849 nonzero_bits (x
, mode
)
7851 enum machine_mode mode
;
7853 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7854 unsigned HOST_WIDE_INT inner_nz
;
7856 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7859 /* For floating-point values, assume all bits are needed. */
7860 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7863 /* If X is wider than MODE, use its mode instead. */
7864 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7866 mode
= GET_MODE (x
);
7867 nonzero
= GET_MODE_MASK (mode
);
7868 mode_width
= GET_MODE_BITSIZE (mode
);
7871 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7872 /* Our only callers in this case look for single bit values. So
7873 just return the mode mask. Those tests will then be false. */
7876 #ifndef WORD_REGISTER_OPERATIONS
7877 /* If MODE is wider than X, but both are a single word for both the host
7878 and target machines, we can compute this from which bits of the
7879 object might be nonzero in its own mode, taking into account the fact
7880 that on many CISC machines, accessing an object in a wider mode
7881 causes the high-order bits to become undefined. So they are
7882 not known to be zero. */
7884 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7885 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7886 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7887 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7889 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7890 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
7895 code
= GET_CODE (x
);
7899 #ifdef POINTERS_EXTEND_UNSIGNED
7900 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7901 all the bits above ptr_mode are known to be zero. */
7902 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7904 nonzero
&= GET_MODE_MASK (ptr_mode
);
7907 #ifdef STACK_BOUNDARY
7908 /* If this is the stack pointer, we may know something about its
7909 alignment. If PUSH_ROUNDING is defined, it is possible for the
7910 stack to be momentarily aligned only to that amount, so we pick
7911 the least alignment. */
7913 /* We can't check for arg_pointer_rtx here, because it is not
7914 guaranteed to have as much alignment as the stack pointer.
7915 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7916 alignment but the argument pointer has only 64 bit alignment. */
7918 if ((x
== frame_pointer_rtx
7919 || x
== stack_pointer_rtx
7920 || x
== hard_frame_pointer_rtx
7921 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7922 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7928 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7930 #ifdef PUSH_ROUNDING
7931 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
7932 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7935 /* We must return here, otherwise we may get a worse result from
7936 one of the choices below. There is nothing useful below as
7937 far as the stack pointer is concerned. */
7938 return nonzero
&= ~(sp_alignment
- 1);
7942 /* If X is a register whose nonzero bits value is current, use it.
7943 Otherwise, if X is a register whose value we can find, use that
7944 value. Otherwise, use the previously-computed global nonzero bits
7945 for this register. */
7947 if (reg_last_set_value
[REGNO (x
)] != 0
7948 && reg_last_set_mode
[REGNO (x
)] == mode
7949 && (reg_last_set_label
[REGNO (x
)] == label_tick
7950 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7951 && REG_N_SETS (REGNO (x
)) == 1
7952 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7954 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7955 return reg_last_set_nonzero_bits
[REGNO (x
)];
7957 tem
= get_last_value (x
);
7961 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7962 /* If X is narrower than MODE and TEM is a non-negative
7963 constant that would appear negative in the mode of X,
7964 sign-extend it for use in reg_nonzero_bits because some
7965 machines (maybe most) will actually do the sign-extension
7966 and this is the conservative approach.
7968 ??? For 2.5, try to tighten up the MD files in this regard
7969 instead of this kludge. */
7971 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7972 && GET_CODE (tem
) == CONST_INT
7974 && 0 != (INTVAL (tem
)
7975 & ((HOST_WIDE_INT
) 1
7976 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7977 tem
= GEN_INT (INTVAL (tem
)
7978 | ((HOST_WIDE_INT
) (-1)
7979 << GET_MODE_BITSIZE (GET_MODE (x
))));
7981 return nonzero_bits (tem
, mode
);
7983 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7984 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7989 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7990 /* If X is negative in MODE, sign-extend the value. */
7991 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7992 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7993 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7999 #ifdef LOAD_EXTEND_OP
8000 /* In many, if not most, RISC machines, reading a byte from memory
8001 zeros the rest of the register. Noticing that fact saves a lot
8002 of extra zero-extends. */
8003 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8004 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8009 case UNEQ
: case LTGT
:
8010 case GT
: case GTU
: case UNGT
:
8011 case LT
: case LTU
: case UNLT
:
8012 case GE
: case GEU
: case UNGE
:
8013 case LE
: case LEU
: case UNLE
:
8014 case UNORDERED
: case ORDERED
:
8016 /* If this produces an integer result, we know which bits are set.
8017 Code here used to clear bits outside the mode of X, but that is
8020 if (GET_MODE_CLASS (mode
) == MODE_INT
8021 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8022 nonzero
= STORE_FLAG_VALUE
;
8027 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8028 and num_sign_bit_copies. */
8029 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8030 == GET_MODE_BITSIZE (GET_MODE (x
)))
8034 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8035 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8040 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8041 and num_sign_bit_copies. */
8042 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8043 == GET_MODE_BITSIZE (GET_MODE (x
)))
8049 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8053 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8054 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8055 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8059 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8060 Otherwise, show all the bits in the outer mode but not the inner
8062 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8063 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8065 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8067 & (((HOST_WIDE_INT
) 1
8068 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8069 inner_nz
|= (GET_MODE_MASK (mode
)
8070 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8073 nonzero
&= inner_nz
;
8077 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8078 & nonzero_bits (XEXP (x
, 1), mode
));
8082 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8083 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8084 | nonzero_bits (XEXP (x
, 1), mode
));
8087 case PLUS
: case MINUS
:
8089 case DIV
: case UDIV
:
8090 case MOD
: case UMOD
:
8091 /* We can apply the rules of arithmetic to compute the number of
8092 high- and low-order zero bits of these operations. We start by
8093 computing the width (position of the highest-order non-zero bit)
8094 and the number of low-order zero bits for each value. */
8096 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8097 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8098 int width0
= floor_log2 (nz0
) + 1;
8099 int width1
= floor_log2 (nz1
) + 1;
8100 int low0
= floor_log2 (nz0
& -nz0
);
8101 int low1
= floor_log2 (nz1
& -nz1
);
8102 HOST_WIDE_INT op0_maybe_minusp
8103 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8104 HOST_WIDE_INT op1_maybe_minusp
8105 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8106 unsigned int result_width
= mode_width
;
8114 && (XEXP (x
, 0) == stack_pointer_rtx
8115 || XEXP (x
, 0) == frame_pointer_rtx
)
8116 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8118 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8120 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8121 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8122 width0
= floor_log2 (nz0
) + 1;
8123 width1
= floor_log2 (nz1
) + 1;
8124 low0
= floor_log2 (nz0
& -nz0
);
8125 low1
= floor_log2 (nz1
& -nz1
);
8128 result_width
= MAX (width0
, width1
) + 1;
8129 result_low
= MIN (low0
, low1
);
8132 result_low
= MIN (low0
, low1
);
8135 result_width
= width0
+ width1
;
8136 result_low
= low0
+ low1
;
8141 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8142 result_width
= width0
;
8147 result_width
= width0
;
8152 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8153 result_width
= MIN (width0
, width1
);
8154 result_low
= MIN (low0
, low1
);
8159 result_width
= MIN (width0
, width1
);
8160 result_low
= MIN (low0
, low1
);
8166 if (result_width
< mode_width
)
8167 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8170 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8172 #ifdef POINTERS_EXTEND_UNSIGNED
8173 /* If pointers extend unsigned and this is an addition or subtraction
8174 to a pointer in Pmode, all the bits above ptr_mode are known to be
8176 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8177 && (code
== PLUS
|| code
== MINUS
)
8178 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8179 nonzero
&= GET_MODE_MASK (ptr_mode
);
8185 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8186 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8187 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8191 /* If this is a SUBREG formed for a promoted variable that has
8192 been zero-extended, we know that at least the high-order bits
8193 are zero, though others might be too. */
8195 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8196 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8197 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8199 /* If the inner mode is a single word for both the host and target
8200 machines, we can compute this from which bits of the inner
8201 object might be nonzero. */
8202 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8203 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8204 <= HOST_BITS_PER_WIDE_INT
))
8206 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8208 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8209 /* If this is a typical RISC machine, we only have to worry
8210 about the way loads are extended. */
8211 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8213 & (((unsigned HOST_WIDE_INT
) 1
8214 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8216 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8219 /* On many CISC machines, accessing an object in a wider mode
8220 causes the high-order bits to become undefined. So they are
8221 not known to be zero. */
8222 if (GET_MODE_SIZE (GET_MODE (x
))
8223 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8224 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8225 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8234 /* The nonzero bits are in two classes: any bits within MODE
8235 that aren't in GET_MODE (x) are always significant. The rest of the
8236 nonzero bits are those that are significant in the operand of
8237 the shift when shifted the appropriate number of bits. This
8238 shows that high-order bits are cleared by the right shift and
8239 low-order bits by left shifts. */
8240 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8241 && INTVAL (XEXP (x
, 1)) >= 0
8242 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8244 enum machine_mode inner_mode
= GET_MODE (x
);
8245 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8246 int count
= INTVAL (XEXP (x
, 1));
8247 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8248 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8249 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8250 unsigned HOST_WIDE_INT outer
= 0;
8252 if (mode_width
> width
)
8253 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8255 if (code
== LSHIFTRT
)
8257 else if (code
== ASHIFTRT
)
8261 /* If the sign bit may have been nonzero before the shift, we
8262 need to mark all the places it could have been copied to
8263 by the shift as possibly nonzero. */
8264 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8265 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8267 else if (code
== ASHIFT
)
8270 inner
= ((inner
<< (count
% width
)
8271 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8273 nonzero
&= (outer
| inner
);
8278 /* This is at most the number of bits in the mode. */
8279 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8283 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8284 | nonzero_bits (XEXP (x
, 2), mode
));
8294 /* See the macro definition above. */
8295 #undef num_sign_bit_copies
8297 /* Return the number of bits at the high-order end of X that are known to
8298 be equal to the sign bit. X will be used in mode MODE; if MODE is
8299 VOIDmode, X will be used in its own mode. The returned value will always
8300 be between 1 and the number of bits in MODE. */
8303 num_sign_bit_copies (x
, mode
)
8305 enum machine_mode mode
;
8307 enum rtx_code code
= GET_CODE (x
);
8308 unsigned int bitwidth
;
8309 int num0
, num1
, result
;
8310 unsigned HOST_WIDE_INT nonzero
;
8313 /* If we weren't given a mode, use the mode of X. If the mode is still
8314 VOIDmode, we don't know anything. Likewise if one of the modes is
8317 if (mode
== VOIDmode
)
8318 mode
= GET_MODE (x
);
8320 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8323 bitwidth
= GET_MODE_BITSIZE (mode
);
8325 /* For a smaller object, just ignore the high bits. */
8326 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8328 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8330 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8333 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8335 #ifndef WORD_REGISTER_OPERATIONS
8336 /* If this machine does not do all register operations on the entire
8337 register and MODE is wider than the mode of X, we can say nothing
8338 at all about the high-order bits. */
8341 /* Likewise on machines that do, if the mode of the object is smaller
8342 than a word and loads of that size don't sign extend, we can say
8343 nothing about the high order bits. */
8344 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8345 #ifdef LOAD_EXTEND_OP
8346 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8357 #ifdef POINTERS_EXTEND_UNSIGNED
8358 /* If pointers extend signed and this is a pointer in Pmode, say that
8359 all the bits above ptr_mode are known to be sign bit copies. */
8360 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8362 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8365 if (reg_last_set_value
[REGNO (x
)] != 0
8366 && reg_last_set_mode
[REGNO (x
)] == mode
8367 && (reg_last_set_label
[REGNO (x
)] == label_tick
8368 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8369 && REG_N_SETS (REGNO (x
)) == 1
8370 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8372 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8373 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8375 tem
= get_last_value (x
);
8377 return num_sign_bit_copies (tem
, mode
);
8379 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8380 return reg_sign_bit_copies
[REGNO (x
)];
8384 #ifdef LOAD_EXTEND_OP
8385 /* Some RISC machines sign-extend all loads of smaller than a word. */
8386 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8387 return MAX (1, ((int) bitwidth
8388 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8393 /* If the constant is negative, take its 1's complement and remask.
8394 Then see how many zero bits we have. */
8395 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8396 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8397 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8398 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8400 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8403 /* If this is a SUBREG for a promoted object that is sign-extended
8404 and we are looking at it in a wider mode, we know that at least the
8405 high-order bits are known to be sign bit copies. */
8407 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8409 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8410 return MAX ((int) bitwidth
8411 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8415 /* For a smaller object, just ignore the high bits. */
8416 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8418 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8419 return MAX (1, (num0
8420 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8424 #ifdef WORD_REGISTER_OPERATIONS
8425 #ifdef LOAD_EXTEND_OP
8426 /* For paradoxical SUBREGs on machines where all register operations
8427 affect the entire register, just look inside. Note that we are
8428 passing MODE to the recursive call, so the number of sign bit copies
8429 will remain relative to that mode, not the inner mode. */
8431 /* This works only if loads sign extend. Otherwise, if we get a
8432 reload for the inner part, it may be loaded from the stack, and
8433 then we lose all sign bit copies that existed before the store
8436 if ((GET_MODE_SIZE (GET_MODE (x
))
8437 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8438 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8439 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8445 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8446 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8450 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8451 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8454 /* For a smaller object, just ignore the high bits. */
8455 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8456 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8460 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8462 case ROTATE
: case ROTATERT
:
8463 /* If we are rotating left by a number of bits less than the number
8464 of sign bit copies, we can just subtract that amount from the
8466 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8467 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8469 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8470 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8471 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8476 /* In general, this subtracts one sign bit copy. But if the value
8477 is known to be positive, the number of sign bit copies is the
8478 same as that of the input. Finally, if the input has just one bit
8479 that might be nonzero, all the bits are copies of the sign bit. */
8480 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8481 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8482 return num0
> 1 ? num0
- 1 : 1;
8484 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8489 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8494 case IOR
: case AND
: case XOR
:
8495 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8496 /* Logical operations will preserve the number of sign-bit copies.
8497 MIN and MAX operations always return one of the operands. */
8498 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8499 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8500 return MIN (num0
, num1
);
8502 case PLUS
: case MINUS
:
8503 /* For addition and subtraction, we can have a 1-bit carry. However,
8504 if we are subtracting 1 from a positive number, there will not
8505 be such a carry. Furthermore, if the positive number is known to
8506 be 0 or 1, we know the result is either -1 or 0. */
8508 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8509 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8511 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8512 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8513 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8514 : bitwidth
- floor_log2 (nonzero
) - 1);
8517 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8518 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8519 result
= MAX (1, MIN (num0
, num1
) - 1);
8521 #ifdef POINTERS_EXTEND_UNSIGNED
8522 /* If pointers extend signed and this is an addition or subtraction
8523 to a pointer in Pmode, all the bits above ptr_mode are known to be
8525 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8526 && (code
== PLUS
|| code
== MINUS
)
8527 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8528 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8529 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8535 /* The number of bits of the product is the sum of the number of
8536 bits of both terms. However, unless one of the terms if known
8537 to be positive, we must allow for an additional bit since negating
8538 a negative number can remove one sign bit copy. */
8540 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8541 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8543 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8545 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8546 || (((nonzero_bits (XEXP (x
, 0), mode
)
8547 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8548 && ((nonzero_bits (XEXP (x
, 1), mode
)
8549 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8552 return MAX (1, result
);
8555 /* The result must be <= the first operand. If the first operand
8556 has the high bit set, we know nothing about the number of sign
8558 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8560 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8561 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8564 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8567 /* The result must be <= the scond operand. */
8568 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8571 /* Similar to unsigned division, except that we have to worry about
8572 the case where the divisor is negative, in which case we have
8574 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8576 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8577 || (nonzero_bits (XEXP (x
, 1), mode
)
8578 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8584 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8586 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8587 || (nonzero_bits (XEXP (x
, 1), mode
)
8588 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8594 /* Shifts by a constant add to the number of bits equal to the
8596 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8597 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8598 && INTVAL (XEXP (x
, 1)) > 0)
8599 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8604 /* Left shifts destroy copies. */
8605 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8606 || INTVAL (XEXP (x
, 1)) < 0
8607 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8610 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8611 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8614 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8615 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8616 return MIN (num0
, num1
);
8618 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8619 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8620 case GEU
: case GTU
: case LEU
: case LTU
:
8621 case UNORDERED
: case ORDERED
:
8622 /* If the constant is negative, take its 1's complement and remask.
8623 Then see how many zero bits we have. */
8624 nonzero
= STORE_FLAG_VALUE
;
8625 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8626 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8627 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8629 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8636 /* If we haven't been able to figure it out by one of the above rules,
8637 see if some of the high-order bits are known to be zero. If so,
8638 count those bits and return one less than that amount. If we can't
8639 safely compute the mask for this mode, always return BITWIDTH. */
8641 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8644 nonzero
= nonzero_bits (x
, mode
);
8645 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8646 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8649 /* Return the number of "extended" bits there are in X, when interpreted
8650 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8651 unsigned quantities, this is the number of high-order zero bits.
8652 For signed quantities, this is the number of copies of the sign bit
8653 minus 1. In both case, this function returns the number of "spare"
8654 bits. For example, if two quantities for which this function returns
8655 at least 1 are added, the addition is known not to overflow.
8657 This function will always return 0 unless called during combine, which
8658 implies that it must be called from a define_split. */
8661 extended_count (x
, mode
, unsignedp
)
8663 enum machine_mode mode
;
8666 if (nonzero_sign_valid
== 0)
8670 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8671 ? (GET_MODE_BITSIZE (mode
) - 1
8672 - floor_log2 (nonzero_bits (x
, mode
)))
8674 : num_sign_bit_copies (x
, mode
) - 1);
8677 /* This function is called from `simplify_shift_const' to merge two
8678 outer operations. Specifically, we have already found that we need
8679 to perform operation *POP0 with constant *PCONST0 at the outermost
8680 position. We would now like to also perform OP1 with constant CONST1
8681 (with *POP0 being done last).
8683 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8684 the resulting operation. *PCOMP_P is set to 1 if we would need to
8685 complement the innermost operand, otherwise it is unchanged.
8687 MODE is the mode in which the operation will be done. No bits outside
8688 the width of this mode matter. It is assumed that the width of this mode
8689 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8691 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8692 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8693 result is simply *PCONST0.
8695 If the resulting operation cannot be expressed as one operation, we
8696 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8699 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8700 enum rtx_code
*pop0
;
8701 HOST_WIDE_INT
*pconst0
;
8703 HOST_WIDE_INT const1
;
8704 enum machine_mode mode
;
8707 enum rtx_code op0
= *pop0
;
8708 HOST_WIDE_INT const0
= *pconst0
;
8710 const0
&= GET_MODE_MASK (mode
);
8711 const1
&= GET_MODE_MASK (mode
);
8713 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8717 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8720 if (op1
== NIL
|| op0
== SET
)
8723 else if (op0
== NIL
)
8724 op0
= op1
, const0
= const1
;
8726 else if (op0
== op1
)
8750 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8751 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8754 /* If the two constants aren't the same, we can't do anything. The
8755 remaining six cases can all be done. */
8756 else if (const0
!= const1
)
8764 /* (a & b) | b == b */
8766 else /* op1 == XOR */
8767 /* (a ^ b) | b == a | b */
8773 /* (a & b) ^ b == (~a) & b */
8774 op0
= AND
, *pcomp_p
= 1;
8775 else /* op1 == IOR */
8776 /* (a | b) ^ b == a & ~b */
8777 op0
= AND
, *pconst0
= ~const0
;
8782 /* (a | b) & b == b */
8784 else /* op1 == XOR */
8785 /* (a ^ b) & b) == (~a) & b */
8792 /* Check for NO-OP cases. */
8793 const0
&= GET_MODE_MASK (mode
);
8795 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8797 else if (const0
== 0 && op0
== AND
)
8799 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8803 /* ??? Slightly redundant with the above mask, but not entirely.
8804 Moving this above means we'd have to sign-extend the mode mask
8805 for the final test. */
8806 const0
= trunc_int_for_mode (const0
, mode
);
8814 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8815 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8816 that we started with.
8818 The shift is normally computed in the widest mode we find in VAROP, as
8819 long as it isn't a different number of words than RESULT_MODE. Exceptions
8820 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8823 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8826 enum machine_mode result_mode
;
8830 enum rtx_code orig_code
= code
;
8831 int orig_count
= input_count
;
8834 enum machine_mode mode
= result_mode
;
8835 enum machine_mode shift_mode
, tmode
;
8836 unsigned int mode_words
8837 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8838 /* We form (outer_op (code varop count) (outer_const)). */
8839 enum rtx_code outer_op
= NIL
;
8840 HOST_WIDE_INT outer_const
= 0;
8842 int complement_p
= 0;
8845 /* If we were given an invalid count, don't do anything except exactly
8846 what was requested. */
8848 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8853 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8856 count
= input_count
;
8858 /* Make sure and truncate the "natural" shift on the way in. We don't
8859 want to do this inside the loop as it makes it more difficult to
8861 #ifdef SHIFT_COUNT_TRUNCATED
8862 if (SHIFT_COUNT_TRUNCATED
)
8863 count
%= GET_MODE_BITSIZE (mode
);
8866 /* Unless one of the branches of the `if' in this loop does a `continue',
8867 we will `break' the loop after the `if'. */
8871 /* If we have an operand of (clobber (const_int 0)), just return that
8873 if (GET_CODE (varop
) == CLOBBER
)
8876 /* If we discovered we had to complement VAROP, leave. Making a NOT
8877 here would cause an infinite loop. */
8881 /* Convert ROTATERT to ROTATE. */
8882 if (code
== ROTATERT
)
8883 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8885 /* We need to determine what mode we will do the shift in. If the
8886 shift is a right shift or a ROTATE, we must always do it in the mode
8887 it was originally done in. Otherwise, we can do it in MODE, the
8888 widest mode encountered. */
8890 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8891 ? result_mode
: mode
);
8893 /* Handle cases where the count is greater than the size of the mode
8894 minus 1. For ASHIFT, use the size minus one as the count (this can
8895 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8896 take the count modulo the size. For other shifts, the result is
8899 Since these shifts are being produced by the compiler by combining
8900 multiple operations, each of which are defined, we know what the
8901 result is supposed to be. */
8903 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8905 if (code
== ASHIFTRT
)
8906 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8907 else if (code
== ROTATE
|| code
== ROTATERT
)
8908 count
%= GET_MODE_BITSIZE (shift_mode
);
8911 /* We can't simply return zero because there may be an
8919 /* An arithmetic right shift of a quantity known to be -1 or 0
8921 if (code
== ASHIFTRT
8922 && (num_sign_bit_copies (varop
, shift_mode
)
8923 == GET_MODE_BITSIZE (shift_mode
)))
8929 /* If we are doing an arithmetic right shift and discarding all but
8930 the sign bit copies, this is equivalent to doing a shift by the
8931 bitsize minus one. Convert it into that shift because it will often
8932 allow other simplifications. */
8934 if (code
== ASHIFTRT
8935 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8936 >= GET_MODE_BITSIZE (shift_mode
)))
8937 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8939 /* We simplify the tests below and elsewhere by converting
8940 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8941 `make_compound_operation' will convert it to a ASHIFTRT for
8942 those machines (such as Vax) that don't have a LSHIFTRT. */
8943 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8945 && ((nonzero_bits (varop
, shift_mode
)
8946 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8950 switch (GET_CODE (varop
))
8956 new = expand_compound_operation (varop
);
8965 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8966 minus the width of a smaller mode, we can do this with a
8967 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8968 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8969 && ! mode_dependent_address_p (XEXP (varop
, 0))
8970 && ! MEM_VOLATILE_P (varop
)
8971 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8972 MODE_INT
, 1)) != BLKmode
)
8974 if (BYTES_BIG_ENDIAN
)
8975 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
8977 new = gen_rtx_MEM (tmode
,
8978 plus_constant (XEXP (varop
, 0),
8979 count
/ BITS_PER_UNIT
));
8981 MEM_COPY_ATTRIBUTES (new, varop
);
8982 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8983 : ZERO_EXTEND
, mode
, new);
8990 /* Similar to the case above, except that we can only do this if
8991 the resulting mode is the same as that of the underlying
8992 MEM and adjust the address depending on the *bits* endianness
8993 because of the way that bit-field extract insns are defined. */
8994 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8995 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8996 MODE_INT
, 1)) != BLKmode
8997 && tmode
== GET_MODE (XEXP (varop
, 0)))
8999 if (BITS_BIG_ENDIAN
)
9000 new = XEXP (varop
, 0);
9003 new = copy_rtx (XEXP (varop
, 0));
9004 SUBST (XEXP (new, 0),
9005 plus_constant (XEXP (new, 0),
9006 count
/ BITS_PER_UNIT
));
9009 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9010 : ZERO_EXTEND
, mode
, new);
9017 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9018 the same number of words as what we've seen so far. Then store
9019 the widest mode in MODE. */
9020 if (subreg_lowpart_p (varop
)
9021 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9022 > GET_MODE_SIZE (GET_MODE (varop
)))
9023 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9024 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9027 varop
= SUBREG_REG (varop
);
9028 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9029 mode
= GET_MODE (varop
);
9035 /* Some machines use MULT instead of ASHIFT because MULT
9036 is cheaper. But it is still better on those machines to
9037 merge two shifts into one. */
9038 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9039 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9042 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9043 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9049 /* Similar, for when divides are cheaper. */
9050 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9051 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9054 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9055 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9061 /* If we are extracting just the sign bit of an arithmetic
9062 right shift, that shift is not needed. However, the sign
9063 bit of a wider mode may be different from what would be
9064 interpreted as the sign bit in a narrower mode, so, if
9065 the result is narrower, don't discard the shift. */
9066 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9067 && (GET_MODE_BITSIZE (result_mode
)
9068 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9070 varop
= XEXP (varop
, 0);
9074 /* ... fall through ... */
9079 /* Here we have two nested shifts. The result is usually the
9080 AND of a new shift with a mask. We compute the result below. */
9081 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9082 && INTVAL (XEXP (varop
, 1)) >= 0
9083 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9084 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9085 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9087 enum rtx_code first_code
= GET_CODE (varop
);
9088 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9089 unsigned HOST_WIDE_INT mask
;
9092 /* We have one common special case. We can't do any merging if
9093 the inner code is an ASHIFTRT of a smaller mode. However, if
9094 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9095 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9096 we can convert it to
9097 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9098 This simplifies certain SIGN_EXTEND operations. */
9099 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9100 && (GET_MODE_BITSIZE (result_mode
)
9101 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9103 /* C3 has the low-order C1 bits zero. */
9105 mask
= (GET_MODE_MASK (mode
)
9106 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9108 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9109 XEXP (varop
, 0), mask
);
9110 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9112 count
= first_count
;
9117 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9118 than C1 high-order bits equal to the sign bit, we can convert
9119 this to either an ASHIFT or a ASHIFTRT depending on the
9122 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9124 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9125 && GET_MODE (varop
) == shift_mode
9126 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9129 varop
= XEXP (varop
, 0);
9131 signed_count
= count
- first_count
;
9132 if (signed_count
< 0)
9133 count
= -signed_count
, code
= ASHIFT
;
9135 count
= signed_count
;
9140 /* There are some cases we can't do. If CODE is ASHIFTRT,
9141 we can only do this if FIRST_CODE is also ASHIFTRT.
9143 We can't do the case when CODE is ROTATE and FIRST_CODE is
9146 If the mode of this shift is not the mode of the outer shift,
9147 we can't do this if either shift is a right shift or ROTATE.
9149 Finally, we can't do any of these if the mode is too wide
9150 unless the codes are the same.
9152 Handle the case where the shift codes are the same
9155 if (code
== first_code
)
9157 if (GET_MODE (varop
) != result_mode
9158 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9162 count
+= first_count
;
9163 varop
= XEXP (varop
, 0);
9167 if (code
== ASHIFTRT
9168 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9169 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9170 || (GET_MODE (varop
) != result_mode
9171 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9172 || first_code
== ROTATE
9173 || code
== ROTATE
)))
9176 /* To compute the mask to apply after the shift, shift the
9177 nonzero bits of the inner shift the same way the
9178 outer shift will. */
9180 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9183 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9186 /* Give up if we can't compute an outer operation to use. */
9188 || GET_CODE (mask_rtx
) != CONST_INT
9189 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9191 result_mode
, &complement_p
))
9194 /* If the shifts are in the same direction, we add the
9195 counts. Otherwise, we subtract them. */
9196 signed_count
= count
;
9197 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9198 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9199 signed_count
+= first_count
;
9201 signed_count
-= first_count
;
9203 /* If COUNT is positive, the new shift is usually CODE,
9204 except for the two exceptions below, in which case it is
9205 FIRST_CODE. If the count is negative, FIRST_CODE should
9207 if (signed_count
> 0
9208 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9209 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9210 code
= first_code
, count
= signed_count
;
9211 else if (signed_count
< 0)
9212 code
= first_code
, count
= -signed_count
;
9214 count
= signed_count
;
9216 varop
= XEXP (varop
, 0);
9220 /* If we have (A << B << C) for any shift, we can convert this to
9221 (A << C << B). This wins if A is a constant. Only try this if
9222 B is not a constant. */
9224 else if (GET_CODE (varop
) == code
9225 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9227 = simplify_binary_operation (code
, mode
,
9231 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9238 /* Make this fit the case below. */
9239 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9240 GEN_INT (GET_MODE_MASK (mode
)));
9246 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9247 with C the size of VAROP - 1 and the shift is logical if
9248 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9249 we have an (le X 0) operation. If we have an arithmetic shift
9250 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9251 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9253 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9254 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9255 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9256 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9257 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9258 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9261 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9264 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9265 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9270 /* If we have (shift (logical)), move the logical to the outside
9271 to allow it to possibly combine with another logical and the
9272 shift to combine with another shift. This also canonicalizes to
9273 what a ZERO_EXTRACT looks like. Also, some machines have
9274 (and (shift)) insns. */
9276 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9277 && (new = simplify_binary_operation (code
, result_mode
,
9279 GEN_INT (count
))) != 0
9280 && GET_CODE (new) == CONST_INT
9281 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9282 INTVAL (new), result_mode
, &complement_p
))
9284 varop
= XEXP (varop
, 0);
9288 /* If we can't do that, try to simplify the shift in each arm of the
9289 logical expression, make a new logical expression, and apply
9290 the inverse distributive law. */
9292 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9293 XEXP (varop
, 0), count
);
9294 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9295 XEXP (varop
, 1), count
);
9297 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9298 varop
= apply_distributive_law (varop
);
9305 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9306 says that the sign bit can be tested, FOO has mode MODE, C is
9307 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9308 that may be nonzero. */
9309 if (code
== LSHIFTRT
9310 && XEXP (varop
, 1) == const0_rtx
9311 && GET_MODE (XEXP (varop
, 0)) == result_mode
9312 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9313 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9314 && ((STORE_FLAG_VALUE
9315 & ((HOST_WIDE_INT
) 1
9316 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9317 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9318 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9319 (HOST_WIDE_INT
) 1, result_mode
,
9322 varop
= XEXP (varop
, 0);
9329 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9330 than the number of bits in the mode is equivalent to A. */
9331 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9332 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9334 varop
= XEXP (varop
, 0);
9339 /* NEG commutes with ASHIFT since it is multiplication. Move the
9340 NEG outside to allow shifts to combine. */
9342 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9343 (HOST_WIDE_INT
) 0, result_mode
,
9346 varop
= XEXP (varop
, 0);
9352 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9353 is one less than the number of bits in the mode is
9354 equivalent to (xor A 1). */
9355 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9356 && XEXP (varop
, 1) == constm1_rtx
9357 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9358 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9359 (HOST_WIDE_INT
) 1, result_mode
,
9363 varop
= XEXP (varop
, 0);
9367 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9368 that might be nonzero in BAR are those being shifted out and those
9369 bits are known zero in FOO, we can replace the PLUS with FOO.
9370 Similarly in the other operand order. This code occurs when
9371 we are computing the size of a variable-size array. */
9373 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9374 && count
< HOST_BITS_PER_WIDE_INT
9375 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9376 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9377 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9379 varop
= XEXP (varop
, 0);
9382 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9383 && count
< HOST_BITS_PER_WIDE_INT
9384 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9385 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9387 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9388 & nonzero_bits (XEXP (varop
, 1),
9391 varop
= XEXP (varop
, 1);
9395 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9397 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9398 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9400 GEN_INT (count
))) != 0
9401 && GET_CODE (new) == CONST_INT
9402 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9403 INTVAL (new), result_mode
, &complement_p
))
9405 varop
= XEXP (varop
, 0);
9411 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9412 with C the size of VAROP - 1 and the shift is logical if
9413 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9414 we have a (gt X 0) operation. If the shift is arithmetic with
9415 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9416 we have a (neg (gt X 0)) operation. */
9418 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9419 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9420 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9421 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9422 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9423 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9424 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9427 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9430 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9431 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9438 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9439 if the truncate does not affect the value. */
9440 if (code
== LSHIFTRT
9441 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9442 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9443 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9444 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9445 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9447 rtx varop_inner
= XEXP (varop
, 0);
9450 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9451 XEXP (varop_inner
, 0),
9453 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9454 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9467 /* We need to determine what mode to do the shift in. If the shift is
9468 a right shift or ROTATE, we must always do it in the mode it was
9469 originally done in. Otherwise, we can do it in MODE, the widest mode
9470 encountered. The code we care about is that of the shift that will
9471 actually be done, not the shift that was originally requested. */
9473 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9474 ? result_mode
: mode
);
9476 /* We have now finished analyzing the shift. The result should be
9477 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9478 OUTER_OP is non-NIL, it is an operation that needs to be applied
9479 to the result of the shift. OUTER_CONST is the relevant constant,
9480 but we must turn off all bits turned off in the shift.
9482 If we were passed a value for X, see if we can use any pieces of
9483 it. If not, make new rtx. */
9485 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9486 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9487 && INTVAL (XEXP (x
, 1)) == count
)
9488 const_rtx
= XEXP (x
, 1);
9490 const_rtx
= GEN_INT (count
);
9492 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9493 && GET_MODE (XEXP (x
, 0)) == shift_mode
9494 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9495 varop
= XEXP (x
, 0);
9496 else if (GET_MODE (varop
) != shift_mode
)
9497 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9499 /* If we can't make the SUBREG, try to return what we were given. */
9500 if (GET_CODE (varop
) == CLOBBER
)
9501 return x
? x
: varop
;
9503 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9508 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9509 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9511 SUBST (XEXP (x
, 0), varop
);
9512 SUBST (XEXP (x
, 1), const_rtx
);
9515 /* If we have an outer operation and we just made a shift, it is
9516 possible that we could have simplified the shift were it not
9517 for the outer operation. So try to do the simplification
9520 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9521 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9522 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9523 INTVAL (XEXP (x
, 1)));
9525 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9526 turn off all the bits that the shift would have turned off. */
9527 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9528 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9529 GET_MODE_MASK (result_mode
) >> orig_count
);
9531 /* Do the remainder of the processing in RESULT_MODE. */
9532 x
= gen_lowpart_for_combine (result_mode
, x
);
9534 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9537 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9539 if (outer_op
!= NIL
)
9541 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9542 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9544 if (outer_op
== AND
)
9545 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9546 else if (outer_op
== SET
)
9547 /* This means that we have determined that the result is
9548 equivalent to a constant. This should be rare. */
9549 x
= GEN_INT (outer_const
);
9550 else if (GET_RTX_CLASS (outer_op
) == '1')
9551 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9553 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9559 /* Like recog, but we receive the address of a pointer to a new pattern.
9560 We try to match the rtx that the pointer points to.
9561 If that fails, we may try to modify or replace the pattern,
9562 storing the replacement into the same pointer object.
9564 Modifications include deletion or addition of CLOBBERs.
9566 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9567 the CLOBBERs are placed.
9569 The value is the final insn code from the pattern ultimately matched,
9573 recog_for_combine (pnewpat
, insn
, pnotes
)
9578 register rtx pat
= *pnewpat
;
9579 int insn_code_number
;
9580 int num_clobbers_to_add
= 0;
9585 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9586 we use to indicate that something didn't match. If we find such a
9587 thing, force rejection. */
9588 if (GET_CODE (pat
) == PARALLEL
)
9589 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9590 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9591 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9594 /* Remove the old notes prior to trying to recognize the new pattern. */
9595 old_notes
= REG_NOTES (insn
);
9596 REG_NOTES (insn
) = 0;
9598 /* Is the result of combination a valid instruction? */
9599 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9601 /* If it isn't, there is the possibility that we previously had an insn
9602 that clobbered some register as a side effect, but the combined
9603 insn doesn't need to do that. So try once more without the clobbers
9604 unless this represents an ASM insn. */
9606 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9607 && GET_CODE (pat
) == PARALLEL
)
9611 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9612 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9615 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9619 SUBST_INT (XVECLEN (pat
, 0), pos
);
9622 pat
= XVECEXP (pat
, 0, 0);
9624 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9627 REG_NOTES (insn
) = old_notes
;
9629 /* If we had any clobbers to add, make a new pattern than contains
9630 them. Then check to make sure that all of them are dead. */
9631 if (num_clobbers_to_add
)
9633 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9634 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9636 + num_clobbers_to_add
)
9637 : num_clobbers_to_add
+ 1));
9639 if (GET_CODE (pat
) == PARALLEL
)
9640 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9641 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9643 XVECEXP (newpat
, 0, 0) = pat
;
9645 add_clobbers (newpat
, insn_code_number
);
9647 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9648 i
< XVECLEN (newpat
, 0); i
++)
9650 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9651 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9653 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9654 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9662 return insn_code_number
;
9665 /* Like gen_lowpart but for use by combine. In combine it is not possible
9666 to create any new pseudoregs. However, it is safe to create
9667 invalid memory addresses, because combine will try to recognize
9668 them and all they will do is make the combine attempt fail.
9670 If for some reason this cannot do its job, an rtx
9671 (clobber (const_int 0)) is returned.
9672 An insn containing that will not be recognized. */
9677 gen_lowpart_for_combine (mode
, x
)
9678 enum machine_mode mode
;
9683 if (GET_MODE (x
) == mode
)
9686 /* We can only support MODE being wider than a word if X is a
9687 constant integer or has a mode the same size. */
9689 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9690 && ! ((GET_MODE (x
) == VOIDmode
9691 && (GET_CODE (x
) == CONST_INT
9692 || GET_CODE (x
) == CONST_DOUBLE
))
9693 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9694 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9696 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9697 won't know what to do. So we will strip off the SUBREG here and
9698 process normally. */
9699 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9702 if (GET_MODE (x
) == mode
)
9706 result
= gen_lowpart_common (mode
, x
);
9707 #ifdef CLASS_CANNOT_CHANGE_MODE
9709 && GET_CODE (result
) == SUBREG
9710 && GET_CODE (SUBREG_REG (result
)) == REG
9711 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9712 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9713 GET_MODE (SUBREG_REG (result
))))
9714 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9720 if (GET_CODE (x
) == MEM
)
9722 register int offset
= 0;
9725 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9727 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9728 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9730 /* If we want to refer to something bigger than the original memref,
9731 generate a perverse subreg instead. That will force a reload
9732 of the original memref X. */
9733 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9734 return gen_rtx_SUBREG (mode
, x
, 0);
9736 if (WORDS_BIG_ENDIAN
)
9737 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9738 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9740 if (BYTES_BIG_ENDIAN
)
9742 /* Adjust the address so that the address-after-the-data is
9744 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9745 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9747 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9748 MEM_COPY_ATTRIBUTES (new, x
);
9752 /* If X is a comparison operator, rewrite it in a new mode. This
9753 probably won't match, but may allow further simplifications. */
9754 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9755 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9757 /* If we couldn't simplify X any other way, just enclose it in a
9758 SUBREG. Normally, this SUBREG won't match, but some patterns may
9759 include an explicit SUBREG or we may simplify it further in combine. */
9765 offset
= subreg_lowpart_offset (mode
, GET_MODE (x
));
9766 res
= simplify_gen_subreg (mode
, x
, GET_MODE (x
), offset
);
9769 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9773 /* These routines make binary and unary operations by first seeing if they
9774 fold; if not, a new expression is allocated. */
9777 gen_binary (code
, mode
, op0
, op1
)
9779 enum machine_mode mode
;
9785 if (GET_RTX_CLASS (code
) == 'c'
9786 && swap_commutative_operands_p (op0
, op1
))
9787 tem
= op0
, op0
= op1
, op1
= tem
;
9789 if (GET_RTX_CLASS (code
) == '<')
9791 enum machine_mode op_mode
= GET_MODE (op0
);
9793 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9794 just (REL_OP X Y). */
9795 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9797 op1
= XEXP (op0
, 1);
9798 op0
= XEXP (op0
, 0);
9799 op_mode
= GET_MODE (op0
);
9802 if (op_mode
== VOIDmode
)
9803 op_mode
= GET_MODE (op1
);
9804 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9807 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9812 /* Put complex operands first and constants second. */
9813 if (GET_RTX_CLASS (code
) == 'c'
9814 && swap_commutative_operands_p (op0
, op1
))
9815 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9817 /* If we are turning off bits already known off in OP0, we need not do
9819 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9820 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9821 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9824 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9827 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9828 comparison code that will be tested.
9830 The result is a possibly different comparison code to use. *POP0 and
9831 *POP1 may be updated.
9833 It is possible that we might detect that a comparison is either always
9834 true or always false. However, we do not perform general constant
9835 folding in combine, so this knowledge isn't useful. Such tautologies
9836 should have been detected earlier. Hence we ignore all such cases. */
9838 static enum rtx_code
9839 simplify_comparison (code
, pop0
, pop1
)
9848 enum machine_mode mode
, tmode
;
9850 /* Try a few ways of applying the same transformation to both operands. */
9853 #ifndef WORD_REGISTER_OPERATIONS
9854 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9855 so check specially. */
9856 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9857 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9858 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9859 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9860 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9861 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9862 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9863 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9864 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9865 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9866 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9867 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9868 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9869 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9870 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9871 && (INTVAL (XEXP (op0
, 1))
9872 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9874 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9876 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9877 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9881 /* If both operands are the same constant shift, see if we can ignore the
9882 shift. We can if the shift is a rotate or if the bits shifted out of
9883 this shift are known to be zero for both inputs and if the type of
9884 comparison is compatible with the shift. */
9885 if (GET_CODE (op0
) == GET_CODE (op1
)
9886 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9887 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9888 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9889 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9890 || (GET_CODE (op0
) == ASHIFTRT
9891 && (code
!= GTU
&& code
!= LTU
9892 && code
!= GEU
&& code
!= LEU
)))
9893 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9894 && INTVAL (XEXP (op0
, 1)) >= 0
9895 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9896 && XEXP (op0
, 1) == XEXP (op1
, 1))
9898 enum machine_mode mode
= GET_MODE (op0
);
9899 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9900 int shift_count
= INTVAL (XEXP (op0
, 1));
9902 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9903 mask
&= (mask
>> shift_count
) << shift_count
;
9904 else if (GET_CODE (op0
) == ASHIFT
)
9905 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9907 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9908 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9909 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9914 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9915 SUBREGs are of the same mode, and, in both cases, the AND would
9916 be redundant if the comparison was done in the narrower mode,
9917 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9918 and the operand's possibly nonzero bits are 0xffffff01; in that case
9919 if we only care about QImode, we don't need the AND). This case
9920 occurs if the output mode of an scc insn is not SImode and
9921 STORE_FLAG_VALUE == 1 (e.g., the 386).
9923 Similarly, check for a case where the AND's are ZERO_EXTEND
9924 operations from some narrower mode even though a SUBREG is not
9927 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9928 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9929 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9931 rtx inner_op0
= XEXP (op0
, 0);
9932 rtx inner_op1
= XEXP (op1
, 0);
9933 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9934 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9937 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9938 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9939 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9940 && (GET_MODE (SUBREG_REG (inner_op0
))
9941 == GET_MODE (SUBREG_REG (inner_op1
)))
9942 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9943 <= HOST_BITS_PER_WIDE_INT
)
9944 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9945 GET_MODE (SUBREG_REG (inner_op0
)))))
9946 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9947 GET_MODE (SUBREG_REG (inner_op1
))))))
9949 op0
= SUBREG_REG (inner_op0
);
9950 op1
= SUBREG_REG (inner_op1
);
9952 /* The resulting comparison is always unsigned since we masked
9953 off the original sign bit. */
9954 code
= unsigned_condition (code
);
9960 for (tmode
= GET_CLASS_NARROWEST_MODE
9961 (GET_MODE_CLASS (GET_MODE (op0
)));
9962 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9963 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9965 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9966 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9967 code
= unsigned_condition (code
);
9976 /* If both operands are NOT, we can strip off the outer operation
9977 and adjust the comparison code for swapped operands; similarly for
9978 NEG, except that this must be an equality comparison. */
9979 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9980 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9981 && (code
== EQ
|| code
== NE
)))
9982 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9988 /* If the first operand is a constant, swap the operands and adjust the
9989 comparison code appropriately, but don't do this if the second operand
9990 is already a constant integer. */
9991 if (swap_commutative_operands_p (op0
, op1
))
9993 tem
= op0
, op0
= op1
, op1
= tem
;
9994 code
= swap_condition (code
);
9997 /* We now enter a loop during which we will try to simplify the comparison.
9998 For the most part, we only are concerned with comparisons with zero,
9999 but some things may really be comparisons with zero but not start
10000 out looking that way. */
10002 while (GET_CODE (op1
) == CONST_INT
)
10004 enum machine_mode mode
= GET_MODE (op0
);
10005 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10006 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10007 int equality_comparison_p
;
10008 int sign_bit_comparison_p
;
10009 int unsigned_comparison_p
;
10010 HOST_WIDE_INT const_op
;
10012 /* We only want to handle integral modes. This catches VOIDmode,
10013 CCmode, and the floating-point modes. An exception is that we
10014 can handle VOIDmode if OP0 is a COMPARE or a comparison
10017 if (GET_MODE_CLASS (mode
) != MODE_INT
10018 && ! (mode
== VOIDmode
10019 && (GET_CODE (op0
) == COMPARE
10020 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10023 /* Get the constant we are comparing against and turn off all bits
10024 not on in our mode. */
10025 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10026 op1
= GEN_INT (const_op
);
10028 /* If we are comparing against a constant power of two and the value
10029 being compared can only have that single bit nonzero (e.g., it was
10030 `and'ed with that bit), we can replace this with a comparison
10033 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10034 || code
== LT
|| code
== LTU
)
10035 && mode_width
<= HOST_BITS_PER_WIDE_INT
10036 && exact_log2 (const_op
) >= 0
10037 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10039 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10040 op1
= const0_rtx
, const_op
= 0;
10043 /* Similarly, if we are comparing a value known to be either -1 or
10044 0 with -1, change it to the opposite comparison against zero. */
10047 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10048 || code
== GEU
|| code
== LTU
)
10049 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10051 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10052 op1
= const0_rtx
, const_op
= 0;
10055 /* Do some canonicalizations based on the comparison code. We prefer
10056 comparisons against zero and then prefer equality comparisons.
10057 If we can reduce the size of a constant, we will do that too. */
10062 /* < C is equivalent to <= (C - 1) */
10066 op1
= GEN_INT (const_op
);
10068 /* ... fall through to LE case below. */
10074 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10078 op1
= GEN_INT (const_op
);
10082 /* If we are doing a <= 0 comparison on a value known to have
10083 a zero sign bit, we can replace this with == 0. */
10084 else if (const_op
== 0
10085 && mode_width
<= HOST_BITS_PER_WIDE_INT
10086 && (nonzero_bits (op0
, mode
)
10087 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10092 /* >= C is equivalent to > (C - 1). */
10096 op1
= GEN_INT (const_op
);
10098 /* ... fall through to GT below. */
10104 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10108 op1
= GEN_INT (const_op
);
10112 /* If we are doing a > 0 comparison on a value known to have
10113 a zero sign bit, we can replace this with != 0. */
10114 else if (const_op
== 0
10115 && mode_width
<= HOST_BITS_PER_WIDE_INT
10116 && (nonzero_bits (op0
, mode
)
10117 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10122 /* < C is equivalent to <= (C - 1). */
10126 op1
= GEN_INT (const_op
);
10128 /* ... fall through ... */
10131 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10132 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10133 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10135 const_op
= 0, op1
= const0_rtx
;
10143 /* unsigned <= 0 is equivalent to == 0 */
10147 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10148 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10149 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10151 const_op
= 0, op1
= const0_rtx
;
10157 /* >= C is equivalent to < (C - 1). */
10161 op1
= GEN_INT (const_op
);
10163 /* ... fall through ... */
10166 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10167 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10168 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10170 const_op
= 0, op1
= const0_rtx
;
10178 /* unsigned > 0 is equivalent to != 0 */
10182 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10183 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10184 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10186 const_op
= 0, op1
= const0_rtx
;
10195 /* Compute some predicates to simplify code below. */
10197 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10198 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10199 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10202 /* If this is a sign bit comparison and we can do arithmetic in
10203 MODE, say that we will only be needing the sign bit of OP0. */
10204 if (sign_bit_comparison_p
10205 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10206 op0
= force_to_mode (op0
, mode
,
10208 << (GET_MODE_BITSIZE (mode
) - 1)),
10211 /* Now try cases based on the opcode of OP0. If none of the cases
10212 does a "continue", we exit this loop immediately after the
10215 switch (GET_CODE (op0
))
10218 /* If we are extracting a single bit from a variable position in
10219 a constant that has only a single bit set and are comparing it
10220 with zero, we can convert this into an equality comparison
10221 between the position and the location of the single bit. */
10223 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10224 && XEXP (op0
, 1) == const1_rtx
10225 && equality_comparison_p
&& const_op
== 0
10226 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10228 if (BITS_BIG_ENDIAN
)
10231 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10232 if (mode
== VOIDmode
)
10234 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10236 i
= BITS_PER_WORD
- 1 - i
;
10240 op0
= XEXP (op0
, 2);
10244 /* Result is nonzero iff shift count is equal to I. */
10245 code
= reverse_condition (code
);
10249 /* ... fall through ... */
10252 tem
= expand_compound_operation (op0
);
10261 /* If testing for equality, we can take the NOT of the constant. */
10262 if (equality_comparison_p
10263 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10265 op0
= XEXP (op0
, 0);
10270 /* If just looking at the sign bit, reverse the sense of the
10272 if (sign_bit_comparison_p
)
10274 op0
= XEXP (op0
, 0);
10275 code
= (code
== GE
? LT
: GE
);
10281 /* If testing for equality, we can take the NEG of the constant. */
10282 if (equality_comparison_p
10283 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10285 op0
= XEXP (op0
, 0);
10290 /* The remaining cases only apply to comparisons with zero. */
10294 /* When X is ABS or is known positive,
10295 (neg X) is < 0 if and only if X != 0. */
10297 if (sign_bit_comparison_p
10298 && (GET_CODE (XEXP (op0
, 0)) == ABS
10299 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10300 && (nonzero_bits (XEXP (op0
, 0), mode
)
10301 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10303 op0
= XEXP (op0
, 0);
10304 code
= (code
== LT
? NE
: EQ
);
10308 /* If we have NEG of something whose two high-order bits are the
10309 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10310 if (num_sign_bit_copies (op0
, mode
) >= 2)
10312 op0
= XEXP (op0
, 0);
10313 code
= swap_condition (code
);
10319 /* If we are testing equality and our count is a constant, we
10320 can perform the inverse operation on our RHS. */
10321 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10322 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10323 op1
, XEXP (op0
, 1))) != 0)
10325 op0
= XEXP (op0
, 0);
10330 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10331 a particular bit. Convert it to an AND of a constant of that
10332 bit. This will be converted into a ZERO_EXTRACT. */
10333 if (const_op
== 0 && sign_bit_comparison_p
10334 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10335 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10337 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10340 - INTVAL (XEXP (op0
, 1)))));
10341 code
= (code
== LT
? NE
: EQ
);
10345 /* Fall through. */
10348 /* ABS is ignorable inside an equality comparison with zero. */
10349 if (const_op
== 0 && equality_comparison_p
)
10351 op0
= XEXP (op0
, 0);
10357 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10358 to (compare FOO CONST) if CONST fits in FOO's mode and we
10359 are either testing inequality or have an unsigned comparison
10360 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10361 if (! unsigned_comparison_p
10362 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10363 <= HOST_BITS_PER_WIDE_INT
)
10364 && ((unsigned HOST_WIDE_INT
) const_op
10365 < (((unsigned HOST_WIDE_INT
) 1
10366 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10368 op0
= XEXP (op0
, 0);
10374 /* Check for the case where we are comparing A - C1 with C2,
10375 both constants are smaller than 1/2 the maximum positive
10376 value in MODE, and the comparison is equality or unsigned.
10377 In that case, if A is either zero-extended to MODE or has
10378 sufficient sign bits so that the high-order bit in MODE
10379 is a copy of the sign in the inner mode, we can prove that it is
10380 safe to do the operation in the wider mode. This simplifies
10381 many range checks. */
10383 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10384 && subreg_lowpart_p (op0
)
10385 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10386 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10387 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10388 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10389 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10390 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10391 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10392 GET_MODE (SUBREG_REG (op0
)))
10393 & ~GET_MODE_MASK (mode
))
10394 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10395 GET_MODE (SUBREG_REG (op0
)))
10396 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10397 - GET_MODE_BITSIZE (mode
)))))
10399 op0
= SUBREG_REG (op0
);
10403 /* If the inner mode is narrower and we are extracting the low part,
10404 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10405 if (subreg_lowpart_p (op0
)
10406 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10407 /* Fall through */ ;
10411 /* ... fall through ... */
10414 if ((unsigned_comparison_p
|| equality_comparison_p
)
10415 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10416 <= HOST_BITS_PER_WIDE_INT
)
10417 && ((unsigned HOST_WIDE_INT
) const_op
10418 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10420 op0
= XEXP (op0
, 0);
10426 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10427 this for equality comparisons due to pathological cases involving
10429 if (equality_comparison_p
10430 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10431 op1
, XEXP (op0
, 1))))
10433 op0
= XEXP (op0
, 0);
10438 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10439 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10440 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10442 op0
= XEXP (XEXP (op0
, 0), 0);
10443 code
= (code
== LT
? EQ
: NE
);
10449 /* We used to optimize signed comparisons against zero, but that
10450 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10451 arrive here as equality comparisons, or (GEU, LTU) are
10452 optimized away. No need to special-case them. */
10454 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10455 (eq B (minus A C)), whichever simplifies. We can only do
10456 this for equality comparisons due to pathological cases involving
10458 if (equality_comparison_p
10459 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10460 XEXP (op0
, 1), op1
)))
10462 op0
= XEXP (op0
, 0);
10467 if (equality_comparison_p
10468 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10469 XEXP (op0
, 0), op1
)))
10471 op0
= XEXP (op0
, 1);
10476 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10477 of bits in X minus 1, is one iff X > 0. */
10478 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10479 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10480 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10481 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10483 op0
= XEXP (op0
, 1);
10484 code
= (code
== GE
? LE
: GT
);
10490 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10491 if C is zero or B is a constant. */
10492 if (equality_comparison_p
10493 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10494 XEXP (op0
, 1), op1
)))
10496 op0
= XEXP (op0
, 0);
10503 case UNEQ
: case LTGT
:
10504 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10505 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10506 case UNORDERED
: case ORDERED
:
10507 /* We can't do anything if OP0 is a condition code value, rather
10508 than an actual data value. */
10511 || XEXP (op0
, 0) == cc0_rtx
10513 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10516 /* Get the two operands being compared. */
10517 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10518 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10520 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10522 /* Check for the cases where we simply want the result of the
10523 earlier test or the opposite of that result. */
10524 if (code
== NE
|| code
== EQ
10525 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10526 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10527 && (STORE_FLAG_VALUE
10528 & (((HOST_WIDE_INT
) 1
10529 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10530 && (code
== LT
|| code
== GE
)))
10532 enum rtx_code new_code
;
10533 if (code
== LT
|| code
== NE
)
10534 new_code
= GET_CODE (op0
);
10536 new_code
= combine_reversed_comparison_code (op0
);
10538 if (new_code
!= UNKNOWN
)
10549 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10551 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10552 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10553 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10555 op0
= XEXP (op0
, 1);
10556 code
= (code
== GE
? GT
: LE
);
10562 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10563 will be converted to a ZERO_EXTRACT later. */
10564 if (const_op
== 0 && equality_comparison_p
10565 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10566 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10568 op0
= simplify_and_const_int
10569 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10571 XEXP (XEXP (op0
, 0), 1)),
10572 (HOST_WIDE_INT
) 1);
10576 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10577 zero and X is a comparison and C1 and C2 describe only bits set
10578 in STORE_FLAG_VALUE, we can compare with X. */
10579 if (const_op
== 0 && equality_comparison_p
10580 && mode_width
<= HOST_BITS_PER_WIDE_INT
10581 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10582 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10583 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10584 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10585 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10587 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10588 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10589 if ((~STORE_FLAG_VALUE
& mask
) == 0
10590 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10591 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10592 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10594 op0
= XEXP (XEXP (op0
, 0), 0);
10599 /* If we are doing an equality comparison of an AND of a bit equal
10600 to the sign bit, replace this with a LT or GE comparison of
10601 the underlying value. */
10602 if (equality_comparison_p
10604 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10605 && mode_width
<= HOST_BITS_PER_WIDE_INT
10606 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10607 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10609 op0
= XEXP (op0
, 0);
10610 code
= (code
== EQ
? GE
: LT
);
10614 /* If this AND operation is really a ZERO_EXTEND from a narrower
10615 mode, the constant fits within that mode, and this is either an
10616 equality or unsigned comparison, try to do this comparison in
10617 the narrower mode. */
10618 if ((equality_comparison_p
|| unsigned_comparison_p
)
10619 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10620 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10621 & GET_MODE_MASK (mode
))
10623 && const_op
>> i
== 0
10624 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10626 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10630 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10631 in both M1 and M2 and the SUBREG is either paradoxical or
10632 represents the low part, permute the SUBREG and the AND and
10634 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10636 #ifdef WORD_REGISTER_OPERATIONS
10638 > (GET_MODE_BITSIZE
10639 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10640 && mode_width
<= BITS_PER_WORD
)
10643 <= (GET_MODE_BITSIZE
10644 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10645 && subreg_lowpart_p (XEXP (op0
, 0))))
10646 #ifndef WORD_REGISTER_OPERATIONS
10647 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10648 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10649 As originally written the upper bits have a defined value
10650 due to the AND operation. However, if we commute the AND
10651 inside the SUBREG then they no longer have defined values
10652 and the meaning of the code has been changed. */
10653 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10654 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10656 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10657 && mode_width
<= HOST_BITS_PER_WIDE_INT
10658 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10659 <= HOST_BITS_PER_WIDE_INT
)
10660 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10661 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10662 & INTVAL (XEXP (op0
, 1)))
10663 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10664 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10665 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10669 = gen_lowpart_for_combine
10671 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10672 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10676 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10677 (eq (and (lshiftrt X) 1) 0). */
10678 if (const_op
== 0 && equality_comparison_p
10679 && XEXP (op0
, 1) == const1_rtx
10680 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10681 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10683 op0
= simplify_and_const_int
10685 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10686 XEXP (XEXP (op0
, 0), 1)),
10687 (HOST_WIDE_INT
) 1);
10688 code
= (code
== NE
? EQ
: NE
);
10694 /* If we have (compare (ashift FOO N) (const_int C)) and
10695 the high order N bits of FOO (N+1 if an inequality comparison)
10696 are known to be zero, we can do this by comparing FOO with C
10697 shifted right N bits so long as the low-order N bits of C are
10699 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10700 && INTVAL (XEXP (op0
, 1)) >= 0
10701 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10702 < HOST_BITS_PER_WIDE_INT
)
10704 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10705 && mode_width
<= HOST_BITS_PER_WIDE_INT
10706 && (nonzero_bits (XEXP (op0
, 0), mode
)
10707 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10708 + ! equality_comparison_p
))) == 0)
10710 /* We must perform a logical shift, not an arithmetic one,
10711 as we want the top N bits of C to be zero. */
10712 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10714 temp
>>= INTVAL (XEXP (op0
, 1));
10715 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10716 op0
= XEXP (op0
, 0);
10720 /* If we are doing a sign bit comparison, it means we are testing
10721 a particular bit. Convert it to the appropriate AND. */
10722 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10723 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10725 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10728 - INTVAL (XEXP (op0
, 1)))));
10729 code
= (code
== LT
? NE
: EQ
);
10733 /* If this an equality comparison with zero and we are shifting
10734 the low bit to the sign bit, we can convert this to an AND of the
10736 if (const_op
== 0 && equality_comparison_p
10737 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10738 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10740 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10741 (HOST_WIDE_INT
) 1);
10747 /* If this is an equality comparison with zero, we can do this
10748 as a logical shift, which might be much simpler. */
10749 if (equality_comparison_p
&& const_op
== 0
10750 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10752 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10754 INTVAL (XEXP (op0
, 1)));
10758 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10759 do the comparison in a narrower mode. */
10760 if (! unsigned_comparison_p
10761 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10762 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10763 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10764 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10765 MODE_INT
, 1)) != BLKmode
10766 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10767 || ((unsigned HOST_WIDE_INT
) -const_op
10768 <= GET_MODE_MASK (tmode
))))
10770 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10774 /* Likewise if OP0 is a PLUS of a sign extension with a
10775 constant, which is usually represented with the PLUS
10776 between the shifts. */
10777 if (! unsigned_comparison_p
10778 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10779 && GET_CODE (XEXP (op0
, 0)) == PLUS
10780 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10781 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10782 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10783 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10784 MODE_INT
, 1)) != BLKmode
10785 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10786 || ((unsigned HOST_WIDE_INT
) -const_op
10787 <= GET_MODE_MASK (tmode
))))
10789 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10790 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10791 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10794 op0
= gen_binary (PLUS
, tmode
,
10795 gen_lowpart_for_combine (tmode
, inner
),
10800 /* ... fall through ... */
10802 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10803 the low order N bits of FOO are known to be zero, we can do this
10804 by comparing FOO with C shifted left N bits so long as no
10805 overflow occurs. */
10806 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10807 && INTVAL (XEXP (op0
, 1)) >= 0
10808 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10809 && mode_width
<= HOST_BITS_PER_WIDE_INT
10810 && (nonzero_bits (XEXP (op0
, 0), mode
)
10811 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10813 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10816 const_op
<<= INTVAL (XEXP (op0
, 1));
10817 op1
= GEN_INT (const_op
);
10818 op0
= XEXP (op0
, 0);
10822 /* If we are using this shift to extract just the sign bit, we
10823 can replace this with an LT or GE comparison. */
10825 && (equality_comparison_p
|| sign_bit_comparison_p
)
10826 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10827 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10829 op0
= XEXP (op0
, 0);
10830 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10842 /* Now make any compound operations involved in this comparison. Then,
10843 check for an outmost SUBREG on OP0 that is not doing anything or is
10844 paradoxical. The latter case can only occur when it is known that the
10845 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10846 We can never remove a SUBREG for a non-equality comparison because the
10847 sign bit is in a different place in the underlying object. */
10849 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10850 op1
= make_compound_operation (op1
, SET
);
10852 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10853 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10854 && (code
== NE
|| code
== EQ
)
10855 && ((GET_MODE_SIZE (GET_MODE (op0
))
10856 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10858 op0
= SUBREG_REG (op0
);
10859 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10862 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10863 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10864 && (code
== NE
|| code
== EQ
)
10865 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10866 <= HOST_BITS_PER_WIDE_INT
)
10867 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10868 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
10869 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10871 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10872 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
10873 op0
= SUBREG_REG (op0
), op1
= tem
;
10875 /* We now do the opposite procedure: Some machines don't have compare
10876 insns in all modes. If OP0's mode is an integer mode smaller than a
10877 word and we can't do a compare in that mode, see if there is a larger
10878 mode for which we can do the compare. There are a number of cases in
10879 which we can use the wider mode. */
10881 mode
= GET_MODE (op0
);
10882 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10883 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10884 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10885 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10887 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10888 tmode
= GET_MODE_WIDER_MODE (tmode
))
10889 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10891 /* If the only nonzero bits in OP0 and OP1 are those in the
10892 narrower mode and this is an equality or unsigned comparison,
10893 we can use the wider mode. Similarly for sign-extended
10894 values, in which case it is true for all comparisons. */
10895 if (((code
== EQ
|| code
== NE
10896 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10897 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
10898 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
10899 || ((num_sign_bit_copies (op0
, tmode
)
10900 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10901 && (num_sign_bit_copies (op1
, tmode
)
10902 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10904 /* If OP0 is an AND and we don't have an AND in MODE either,
10905 make a new AND in the proper mode. */
10906 if (GET_CODE (op0
) == AND
10907 && (add_optab
->handlers
[(int) mode
].insn_code
10908 == CODE_FOR_nothing
))
10909 op0
= gen_binary (AND
, tmode
,
10910 gen_lowpart_for_combine (tmode
,
10912 gen_lowpart_for_combine (tmode
,
10915 op0
= gen_lowpart_for_combine (tmode
, op0
);
10916 op1
= gen_lowpart_for_combine (tmode
, op1
);
10920 /* If this is a test for negative, we can make an explicit
10921 test of the sign bit. */
10923 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10924 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10926 op0
= gen_binary (AND
, tmode
,
10927 gen_lowpart_for_combine (tmode
, op0
),
10928 GEN_INT ((HOST_WIDE_INT
) 1
10929 << (GET_MODE_BITSIZE (mode
) - 1)));
10930 code
= (code
== LT
) ? NE
: EQ
;
10935 #ifdef CANONICALIZE_COMPARISON
10936 /* If this machine only supports a subset of valid comparisons, see if we
10937 can convert an unsupported one into a supported one. */
10938 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10947 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10948 searching backward. */
10949 static enum rtx_code
10950 combine_reversed_comparison_code (exp
)
10953 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10956 if (code1
!= UNKNOWN
10957 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10959 /* Otherwise try and find where the condition codes were last set and
10961 x
= get_last_value (XEXP (exp
, 0));
10962 if (!x
|| GET_CODE (x
) != COMPARE
)
10964 return reversed_comparison_code_parts (GET_CODE (exp
),
10965 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10967 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10968 Return NULL_RTX in case we fail to do the reversal. */
10970 reversed_comparison (exp
, mode
, op0
, op1
)
10972 enum machine_mode mode
;
10974 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10975 if (reversed_code
== UNKNOWN
)
10978 return gen_binary (reversed_code
, mode
, op0
, op1
);
10981 /* Utility function for following routine. Called when X is part of a value
10982 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10983 for each register mentioned. Similar to mention_regs in cse.c */
10986 update_table_tick (x
)
10989 register enum rtx_code code
= GET_CODE (x
);
10990 register const char *fmt
= GET_RTX_FORMAT (code
);
10995 unsigned int regno
= REGNO (x
);
10996 unsigned int endregno
10997 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10998 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11001 for (r
= regno
; r
< endregno
; r
++)
11002 reg_last_set_table_tick
[r
] = label_tick
;
11007 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11008 /* Note that we can't have an "E" in values stored; see
11009 get_last_value_validate. */
11011 update_table_tick (XEXP (x
, i
));
11014 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11015 are saying that the register is clobbered and we no longer know its
11016 value. If INSN is zero, don't update reg_last_set; this is only permitted
11017 with VALUE also zero and is used to invalidate the register. */
11020 record_value_for_reg (reg
, insn
, value
)
11025 unsigned int regno
= REGNO (reg
);
11026 unsigned int endregno
11027 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11028 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11031 /* If VALUE contains REG and we have a previous value for REG, substitute
11032 the previous value. */
11033 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11037 /* Set things up so get_last_value is allowed to see anything set up to
11039 subst_low_cuid
= INSN_CUID (insn
);
11040 tem
= get_last_value (reg
);
11042 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11043 it isn't going to be useful and will take a lot of time to process,
11044 so just use the CLOBBER. */
11048 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11049 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11050 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11051 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11052 tem
= XEXP (tem
, 0);
11054 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11058 /* For each register modified, show we don't know its value, that
11059 we don't know about its bitwise content, that its value has been
11060 updated, and that we don't know the location of the death of the
11062 for (i
= regno
; i
< endregno
; i
++)
11065 reg_last_set
[i
] = insn
;
11067 reg_last_set_value
[i
] = 0;
11068 reg_last_set_mode
[i
] = 0;
11069 reg_last_set_nonzero_bits
[i
] = 0;
11070 reg_last_set_sign_bit_copies
[i
] = 0;
11071 reg_last_death
[i
] = 0;
11074 /* Mark registers that are being referenced in this value. */
11076 update_table_tick (value
);
11078 /* Now update the status of each register being set.
11079 If someone is using this register in this block, set this register
11080 to invalid since we will get confused between the two lives in this
11081 basic block. This makes using this register always invalid. In cse, we
11082 scan the table to invalidate all entries using this register, but this
11083 is too much work for us. */
11085 for (i
= regno
; i
< endregno
; i
++)
11087 reg_last_set_label
[i
] = label_tick
;
11088 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11089 reg_last_set_invalid
[i
] = 1;
11091 reg_last_set_invalid
[i
] = 0;
11094 /* The value being assigned might refer to X (like in "x++;"). In that
11095 case, we must replace it with (clobber (const_int 0)) to prevent
11097 if (value
&& ! get_last_value_validate (&value
, insn
,
11098 reg_last_set_label
[regno
], 0))
11100 value
= copy_rtx (value
);
11101 if (! get_last_value_validate (&value
, insn
,
11102 reg_last_set_label
[regno
], 1))
11106 /* For the main register being modified, update the value, the mode, the
11107 nonzero bits, and the number of sign bit copies. */
11109 reg_last_set_value
[regno
] = value
;
11113 subst_low_cuid
= INSN_CUID (insn
);
11114 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11115 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11116 reg_last_set_sign_bit_copies
[regno
]
11117 = num_sign_bit_copies (value
, GET_MODE (reg
));
11121 /* Called via note_stores from record_dead_and_set_regs to handle one
11122 SET or CLOBBER in an insn. DATA is the instruction in which the
11123 set is occurring. */
11126 record_dead_and_set_regs_1 (dest
, setter
, data
)
11130 rtx record_dead_insn
= (rtx
) data
;
11132 if (GET_CODE (dest
) == SUBREG
)
11133 dest
= SUBREG_REG (dest
);
11135 if (GET_CODE (dest
) == REG
)
11137 /* If we are setting the whole register, we know its value. Otherwise
11138 show that we don't know the value. We can handle SUBREG in
11140 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11141 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11142 else if (GET_CODE (setter
) == SET
11143 && GET_CODE (SET_DEST (setter
)) == SUBREG
11144 && SUBREG_REG (SET_DEST (setter
)) == dest
11145 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11146 && subreg_lowpart_p (SET_DEST (setter
)))
11147 record_value_for_reg (dest
, record_dead_insn
,
11148 gen_lowpart_for_combine (GET_MODE (dest
),
11149 SET_SRC (setter
)));
11151 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11153 else if (GET_CODE (dest
) == MEM
11154 /* Ignore pushes, they clobber nothing. */
11155 && ! push_operand (dest
, GET_MODE (dest
)))
11156 mem_last_set
= INSN_CUID (record_dead_insn
);
11159 /* Update the records of when each REG was most recently set or killed
11160 for the things done by INSN. This is the last thing done in processing
11161 INSN in the combiner loop.
11163 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11164 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11165 and also the similar information mem_last_set (which insn most recently
11166 modified memory) and last_call_cuid (which insn was the most recent
11167 subroutine call). */
11170 record_dead_and_set_regs (insn
)
11176 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11178 if (REG_NOTE_KIND (link
) == REG_DEAD
11179 && GET_CODE (XEXP (link
, 0)) == REG
)
11181 unsigned int regno
= REGNO (XEXP (link
, 0));
11182 unsigned int endregno
11183 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11184 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11187 for (i
= regno
; i
< endregno
; i
++)
11188 reg_last_death
[i
] = insn
;
11190 else if (REG_NOTE_KIND (link
) == REG_INC
)
11191 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11194 if (GET_CODE (insn
) == CALL_INSN
)
11196 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11197 if (call_used_regs
[i
])
11199 reg_last_set_value
[i
] = 0;
11200 reg_last_set_mode
[i
] = 0;
11201 reg_last_set_nonzero_bits
[i
] = 0;
11202 reg_last_set_sign_bit_copies
[i
] = 0;
11203 reg_last_death
[i
] = 0;
11206 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11209 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11212 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11213 register present in the SUBREG, so for each such SUBREG go back and
11214 adjust nonzero and sign bit information of the registers that are
11215 known to have some zero/sign bits set.
11217 This is needed because when combine blows the SUBREGs away, the
11218 information on zero/sign bits is lost and further combines can be
11219 missed because of that. */
11222 record_promoted_value (insn
, subreg
)
11227 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11228 enum machine_mode mode
= GET_MODE (subreg
);
11230 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11233 for (links
= LOG_LINKS (insn
); links
;)
11235 insn
= XEXP (links
, 0);
11236 set
= single_set (insn
);
11238 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11239 || REGNO (SET_DEST (set
)) != regno
11240 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11242 links
= XEXP (links
, 1);
11246 if (reg_last_set
[regno
] == insn
)
11248 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11249 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11252 if (GET_CODE (SET_SRC (set
)) == REG
)
11254 regno
= REGNO (SET_SRC (set
));
11255 links
= LOG_LINKS (insn
);
11262 /* Scan X for promoted SUBREGs. For each one found,
11263 note what it implies to the registers used in it. */
11266 check_promoted_subreg (insn
, x
)
11270 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11271 && GET_CODE (SUBREG_REG (x
)) == REG
)
11272 record_promoted_value (insn
, x
);
11275 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11278 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11282 check_promoted_subreg (insn
, XEXP (x
, i
));
11286 if (XVEC (x
, i
) != 0)
11287 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11288 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11294 /* Utility routine for the following function. Verify that all the registers
11295 mentioned in *LOC are valid when *LOC was part of a value set when
11296 label_tick == TICK. Return 0 if some are not.
11298 If REPLACE is non-zero, replace the invalid reference with
11299 (clobber (const_int 0)) and return 1. This replacement is useful because
11300 we often can get useful information about the form of a value (e.g., if
11301 it was produced by a shift that always produces -1 or 0) even though
11302 we don't know exactly what registers it was produced from. */
11305 get_last_value_validate (loc
, insn
, tick
, replace
)
11312 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11313 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11316 if (GET_CODE (x
) == REG
)
11318 unsigned int regno
= REGNO (x
);
11319 unsigned int endregno
11320 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11321 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11324 for (j
= regno
; j
< endregno
; j
++)
11325 if (reg_last_set_invalid
[j
]
11326 /* If this is a pseudo-register that was only set once and not
11327 live at the beginning of the function, it is always valid. */
11328 || (! (regno
>= FIRST_PSEUDO_REGISTER
11329 && REG_N_SETS (regno
) == 1
11330 && (! REGNO_REG_SET_P
11331 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11332 && reg_last_set_label
[j
] > tick
))
11335 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11341 /* If this is a memory reference, make sure that there were
11342 no stores after it that might have clobbered the value. We don't
11343 have alias info, so we assume any store invalidates it. */
11344 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11345 && INSN_CUID (insn
) <= mem_last_set
)
11348 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11352 for (i
= 0; i
< len
; i
++)
11354 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11355 /* Don't bother with these. They shouldn't occur anyway. */
11359 /* If we haven't found a reason for it to be invalid, it is valid. */
11363 /* Get the last value assigned to X, if known. Some registers
11364 in the value may be replaced with (clobber (const_int 0)) if their value
11365 is known longer known reliably. */
11371 unsigned int regno
;
11374 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11375 then convert it to the desired mode. If this is a paradoxical SUBREG,
11376 we cannot predict what values the "extra" bits might have. */
11377 if (GET_CODE (x
) == SUBREG
11378 && subreg_lowpart_p (x
)
11379 && (GET_MODE_SIZE (GET_MODE (x
))
11380 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11381 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11382 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11384 if (GET_CODE (x
) != REG
)
11388 value
= reg_last_set_value
[regno
];
11390 /* If we don't have a value, or if it isn't for this basic block and
11391 it's either a hard register, set more than once, or it's a live
11392 at the beginning of the function, return 0.
11394 Because if it's not live at the beginnning of the function then the reg
11395 is always set before being used (is never used without being set).
11396 And, if it's set only once, and it's always set before use, then all
11397 uses must have the same last value, even if it's not from this basic
11401 || (reg_last_set_label
[regno
] != label_tick
11402 && (regno
< FIRST_PSEUDO_REGISTER
11403 || REG_N_SETS (regno
) != 1
11404 || (REGNO_REG_SET_P
11405 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11408 /* If the value was set in a later insn than the ones we are processing,
11409 we can't use it even if the register was only set once. */
11410 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11413 /* If the value has all its registers valid, return it. */
11414 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11415 reg_last_set_label
[regno
], 0))
11418 /* Otherwise, make a copy and replace any invalid register with
11419 (clobber (const_int 0)). If that fails for some reason, return 0. */
11421 value
= copy_rtx (value
);
11422 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11423 reg_last_set_label
[regno
], 1))
11429 /* Return nonzero if expression X refers to a REG or to memory
11430 that is set in an instruction more recent than FROM_CUID. */
11433 use_crosses_set_p (x
, from_cuid
)
11437 register const char *fmt
;
11439 register enum rtx_code code
= GET_CODE (x
);
11443 unsigned int regno
= REGNO (x
);
11444 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11445 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11447 #ifdef PUSH_ROUNDING
11448 /* Don't allow uses of the stack pointer to be moved,
11449 because we don't know whether the move crosses a push insn. */
11450 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11453 for (; regno
< endreg
; regno
++)
11454 if (reg_last_set
[regno
]
11455 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11460 if (code
== MEM
&& mem_last_set
> from_cuid
)
11463 fmt
= GET_RTX_FORMAT (code
);
11465 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11470 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11471 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11474 else if (fmt
[i
] == 'e'
11475 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11481 /* Define three variables used for communication between the following
11484 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11485 static int reg_dead_flag
;
11487 /* Function called via note_stores from reg_dead_at_p.
11489 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11490 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11493 reg_dead_at_p_1 (dest
, x
, data
)
11496 void *data ATTRIBUTE_UNUSED
;
11498 unsigned int regno
, endregno
;
11500 if (GET_CODE (dest
) != REG
)
11503 regno
= REGNO (dest
);
11504 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11505 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11507 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11508 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11511 /* Return non-zero if REG is known to be dead at INSN.
11513 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11514 referencing REG, it is dead. If we hit a SET referencing REG, it is
11515 live. Otherwise, see if it is live or dead at the start of the basic
11516 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11517 must be assumed to be always live. */
11520 reg_dead_at_p (reg
, insn
)
11527 /* Set variables for reg_dead_at_p_1. */
11528 reg_dead_regno
= REGNO (reg
);
11529 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11530 ? HARD_REGNO_NREGS (reg_dead_regno
,
11536 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11537 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11539 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11540 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11544 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11545 beginning of function. */
11546 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11547 insn
= prev_nonnote_insn (insn
))
11549 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11551 return reg_dead_flag
== 1 ? 1 : 0;
11553 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11557 /* Get the basic block number that we were in. */
11562 for (block
= 0; block
< n_basic_blocks
; block
++)
11563 if (insn
== BLOCK_HEAD (block
))
11566 if (block
== n_basic_blocks
)
11570 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11571 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11577 /* Note hard registers in X that are used. This code is similar to
11578 that in flow.c, but much simpler since we don't care about pseudos. */
11581 mark_used_regs_combine (x
)
11584 RTX_CODE code
= GET_CODE (x
);
11585 unsigned int regno
;
11597 case ADDR_DIFF_VEC
:
11600 /* CC0 must die in the insn after it is set, so we don't need to take
11601 special note of it here. */
11607 /* If we are clobbering a MEM, mark any hard registers inside the
11608 address as used. */
11609 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11610 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11615 /* A hard reg in a wide mode may really be multiple registers.
11616 If so, mark all of them just like the first. */
11617 if (regno
< FIRST_PSEUDO_REGISTER
)
11619 unsigned int endregno
, r
;
11621 /* None of this applies to the stack, frame or arg pointers */
11622 if (regno
== STACK_POINTER_REGNUM
11623 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11624 || regno
== HARD_FRAME_POINTER_REGNUM
11626 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11627 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11629 || regno
== FRAME_POINTER_REGNUM
)
11632 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11633 for (r
= regno
; r
< endregno
; r
++)
11634 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11640 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11642 register rtx testreg
= SET_DEST (x
);
11644 while (GET_CODE (testreg
) == SUBREG
11645 || GET_CODE (testreg
) == ZERO_EXTRACT
11646 || GET_CODE (testreg
) == SIGN_EXTRACT
11647 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11648 testreg
= XEXP (testreg
, 0);
11650 if (GET_CODE (testreg
) == MEM
)
11651 mark_used_regs_combine (XEXP (testreg
, 0));
11653 mark_used_regs_combine (SET_SRC (x
));
11661 /* Recursively scan the operands of this expression. */
11664 register const char *fmt
= GET_RTX_FORMAT (code
);
11666 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11669 mark_used_regs_combine (XEXP (x
, i
));
11670 else if (fmt
[i
] == 'E')
11674 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11675 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11681 /* Remove register number REGNO from the dead registers list of INSN.
11683 Return the note used to record the death, if there was one. */
11686 remove_death (regno
, insn
)
11687 unsigned int regno
;
11690 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11694 REG_N_DEATHS (regno
)--;
11695 remove_note (insn
, note
);
11701 /* For each register (hardware or pseudo) used within expression X, if its
11702 death is in an instruction with cuid between FROM_CUID (inclusive) and
11703 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11704 list headed by PNOTES.
11706 That said, don't move registers killed by maybe_kill_insn.
11708 This is done when X is being merged by combination into TO_INSN. These
11709 notes will then be distributed as needed. */
11712 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11714 rtx maybe_kill_insn
;
11719 register const char *fmt
;
11720 register int len
, i
;
11721 register enum rtx_code code
= GET_CODE (x
);
11725 unsigned int regno
= REGNO (x
);
11726 register rtx where_dead
= reg_last_death
[regno
];
11727 register rtx before_dead
, after_dead
;
11729 /* Don't move the register if it gets killed in between from and to */
11730 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11731 && ! reg_referenced_p (x
, maybe_kill_insn
))
11734 /* WHERE_DEAD could be a USE insn made by combine, so first we
11735 make sure that we have insns with valid INSN_CUID values. */
11736 before_dead
= where_dead
;
11737 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11738 before_dead
= PREV_INSN (before_dead
);
11740 after_dead
= where_dead
;
11741 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11742 after_dead
= NEXT_INSN (after_dead
);
11744 if (before_dead
&& after_dead
11745 && INSN_CUID (before_dead
) >= from_cuid
11746 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11747 || (where_dead
!= after_dead
11748 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11750 rtx note
= remove_death (regno
, where_dead
);
11752 /* It is possible for the call above to return 0. This can occur
11753 when reg_last_death points to I2 or I1 that we combined with.
11754 In that case make a new note.
11756 We must also check for the case where X is a hard register
11757 and NOTE is a death note for a range of hard registers
11758 including X. In that case, we must put REG_DEAD notes for
11759 the remaining registers in place of NOTE. */
11761 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11762 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11763 > GET_MODE_SIZE (GET_MODE (x
))))
11765 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11766 unsigned int deadend
11767 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11768 GET_MODE (XEXP (note
, 0))));
11769 unsigned int ourend
11770 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11773 for (i
= deadregno
; i
< deadend
; i
++)
11774 if (i
< regno
|| i
>= ourend
)
11775 REG_NOTES (where_dead
)
11776 = gen_rtx_EXPR_LIST (REG_DEAD
,
11777 gen_rtx_REG (reg_raw_mode
[i
], i
),
11778 REG_NOTES (where_dead
));
11781 /* If we didn't find any note, or if we found a REG_DEAD note that
11782 covers only part of the given reg, and we have a multi-reg hard
11783 register, then to be safe we must check for REG_DEAD notes
11784 for each register other than the first. They could have
11785 their own REG_DEAD notes lying around. */
11786 else if ((note
== 0
11788 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11789 < GET_MODE_SIZE (GET_MODE (x
)))))
11790 && regno
< FIRST_PSEUDO_REGISTER
11791 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11793 unsigned int ourend
11794 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11795 unsigned int i
, offset
;
11799 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11803 for (i
= regno
+ offset
; i
< ourend
; i
++)
11804 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11805 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11808 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11810 XEXP (note
, 1) = *pnotes
;
11814 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11816 REG_N_DEATHS (regno
)++;
11822 else if (GET_CODE (x
) == SET
)
11824 rtx dest
= SET_DEST (x
);
11826 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11828 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11829 that accesses one word of a multi-word item, some
11830 piece of everything register in the expression is used by
11831 this insn, so remove any old death. */
11832 /* ??? So why do we test for equality of the sizes? */
11834 if (GET_CODE (dest
) == ZERO_EXTRACT
11835 || GET_CODE (dest
) == STRICT_LOW_PART
11836 || (GET_CODE (dest
) == SUBREG
11837 && (((GET_MODE_SIZE (GET_MODE (dest
))
11838 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11839 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11840 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11842 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11846 /* If this is some other SUBREG, we know it replaces the entire
11847 value, so use that as the destination. */
11848 if (GET_CODE (dest
) == SUBREG
)
11849 dest
= SUBREG_REG (dest
);
11851 /* If this is a MEM, adjust deaths of anything used in the address.
11852 For a REG (the only other possibility), the entire value is
11853 being replaced so the old value is not used in this insn. */
11855 if (GET_CODE (dest
) == MEM
)
11856 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11861 else if (GET_CODE (x
) == CLOBBER
)
11864 len
= GET_RTX_LENGTH (code
);
11865 fmt
= GET_RTX_FORMAT (code
);
11867 for (i
= 0; i
< len
; i
++)
11872 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11873 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11876 else if (fmt
[i
] == 'e')
11877 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11881 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11882 pattern of an insn. X must be a REG. */
11885 reg_bitfield_target_p (x
, body
)
11891 if (GET_CODE (body
) == SET
)
11893 rtx dest
= SET_DEST (body
);
11895 unsigned int regno
, tregno
, endregno
, endtregno
;
11897 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11898 target
= XEXP (dest
, 0);
11899 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11900 target
= SUBREG_REG (XEXP (dest
, 0));
11904 if (GET_CODE (target
) == SUBREG
)
11905 target
= SUBREG_REG (target
);
11907 if (GET_CODE (target
) != REG
)
11910 tregno
= REGNO (target
), regno
= REGNO (x
);
11911 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11912 return target
== x
;
11914 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11915 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11917 return endregno
> tregno
&& regno
< endtregno
;
11920 else if (GET_CODE (body
) == PARALLEL
)
11921 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11922 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11928 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11929 as appropriate. I3 and I2 are the insns resulting from the combination
11930 insns including FROM (I2 may be zero).
11932 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11933 not need REG_DEAD notes because they are being substituted for. This
11934 saves searching in the most common cases.
11936 Each note in the list is either ignored or placed on some insns, depending
11937 on the type of note. */
11940 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11944 rtx elim_i2
, elim_i1
;
11946 rtx note
, next_note
;
11949 for (note
= notes
; note
; note
= next_note
)
11951 rtx place
= 0, place2
= 0;
11953 /* If this NOTE references a pseudo register, ensure it references
11954 the latest copy of that register. */
11955 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11956 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11957 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11959 next_note
= XEXP (note
, 1);
11960 switch (REG_NOTE_KIND (note
))
11964 case REG_EXEC_COUNT
:
11965 /* Doesn't matter much where we put this, as long as it's somewhere.
11966 It is preferable to keep these notes on branches, which is most
11967 likely to be i3. */
11971 case REG_NON_LOCAL_GOTO
:
11972 if (GET_CODE (i3
) == JUMP_INSN
)
11974 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11980 case REG_EH_REGION
:
11981 /* These notes must remain with the call or trapping instruction. */
11982 if (GET_CODE (i3
) == CALL_INSN
)
11984 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11986 else if (flag_non_call_exceptions
)
11988 if (may_trap_p (i3
))
11990 else if (i2
&& may_trap_p (i2
))
11992 /* ??? Otherwise assume we've combined things such that we
11993 can now prove that the instructions can't trap. Drop the
11994 note in this case. */
12000 case REG_EH_RETHROW
:
12002 /* These notes must remain with the call. It should not be
12003 possible for both I2 and I3 to be a call. */
12004 if (GET_CODE (i3
) == CALL_INSN
)
12006 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12013 /* Any clobbers for i3 may still exist, and so we must process
12014 REG_UNUSED notes from that insn.
12016 Any clobbers from i2 or i1 can only exist if they were added by
12017 recog_for_combine. In that case, recog_for_combine created the
12018 necessary REG_UNUSED notes. Trying to keep any original
12019 REG_UNUSED notes from these insns can cause incorrect output
12020 if it is for the same register as the original i3 dest.
12021 In that case, we will notice that the register is set in i3,
12022 and then add a REG_UNUSED note for the destination of i3, which
12023 is wrong. However, it is possible to have REG_UNUSED notes from
12024 i2 or i1 for register which were both used and clobbered, so
12025 we keep notes from i2 or i1 if they will turn into REG_DEAD
12028 /* If this register is set or clobbered in I3, put the note there
12029 unless there is one already. */
12030 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12032 if (from_insn
!= i3
)
12035 if (! (GET_CODE (XEXP (note
, 0)) == REG
12036 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12037 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12040 /* Otherwise, if this register is used by I3, then this register
12041 now dies here, so we must put a REG_DEAD note here unless there
12043 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12044 && ! (GET_CODE (XEXP (note
, 0)) == REG
12045 ? find_regno_note (i3
, REG_DEAD
,
12046 REGNO (XEXP (note
, 0)))
12047 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12049 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12057 /* These notes say something about results of an insn. We can
12058 only support them if they used to be on I3 in which case they
12059 remain on I3. Otherwise they are ignored.
12061 If the note refers to an expression that is not a constant, we
12062 must also ignore the note since we cannot tell whether the
12063 equivalence is still true. It might be possible to do
12064 slightly better than this (we only have a problem if I2DEST
12065 or I1DEST is present in the expression), but it doesn't
12066 seem worth the trouble. */
12068 if (from_insn
== i3
12069 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12074 case REG_NO_CONFLICT
:
12075 /* These notes say something about how a register is used. They must
12076 be present on any use of the register in I2 or I3. */
12077 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12080 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12090 /* This can show up in several ways -- either directly in the
12091 pattern, or hidden off in the constant pool with (or without?)
12092 a REG_EQUAL note. */
12093 /* ??? Ignore the without-reg_equal-note problem for now. */
12094 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12095 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12096 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12097 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12101 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12102 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12103 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12104 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12115 /* These notes say something about the value of a register prior
12116 to the execution of an insn. It is too much trouble to see
12117 if the note is still correct in all situations. It is better
12118 to simply delete it. */
12122 /* If the insn previously containing this note still exists,
12123 put it back where it was. Otherwise move it to the previous
12124 insn. Adjust the corresponding REG_LIBCALL note. */
12125 if (GET_CODE (from_insn
) != NOTE
)
12129 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12130 place
= prev_real_insn (from_insn
);
12132 XEXP (tem
, 0) = place
;
12133 /* If we're deleting the last remaining instruction of a
12134 libcall sequence, don't add the notes. */
12135 else if (XEXP (note
, 0) == from_insn
)
12141 /* This is handled similarly to REG_RETVAL. */
12142 if (GET_CODE (from_insn
) != NOTE
)
12146 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12147 place
= next_real_insn (from_insn
);
12149 XEXP (tem
, 0) = place
;
12150 /* If we're deleting the last remaining instruction of a
12151 libcall sequence, don't add the notes. */
12152 else if (XEXP (note
, 0) == from_insn
)
12158 /* If the register is used as an input in I3, it dies there.
12159 Similarly for I2, if it is non-zero and adjacent to I3.
12161 If the register is not used as an input in either I3 or I2
12162 and it is not one of the registers we were supposed to eliminate,
12163 there are two possibilities. We might have a non-adjacent I2
12164 or we might have somehow eliminated an additional register
12165 from a computation. For example, we might have had A & B where
12166 we discover that B will always be zero. In this case we will
12167 eliminate the reference to A.
12169 In both cases, we must search to see if we can find a previous
12170 use of A and put the death note there. */
12173 && GET_CODE (from_insn
) == CALL_INSN
12174 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12176 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12178 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12179 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12182 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12183 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12188 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12190 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12192 if (! INSN_P (tem
))
12194 if (tem
== bb
->head
)
12199 /* If the register is being set at TEM, see if that is all
12200 TEM is doing. If so, delete TEM. Otherwise, make this
12201 into a REG_UNUSED note instead. */
12202 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12204 rtx set
= single_set (tem
);
12205 rtx inner_dest
= 0;
12207 rtx cc0_setter
= NULL_RTX
;
12211 for (inner_dest
= SET_DEST (set
);
12212 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12213 || GET_CODE (inner_dest
) == SUBREG
12214 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12215 inner_dest
= XEXP (inner_dest
, 0))
12218 /* Verify that it was the set, and not a clobber that
12219 modified the register.
12221 CC0 targets must be careful to maintain setter/user
12222 pairs. If we cannot delete the setter due to side
12223 effects, mark the user with an UNUSED note instead
12226 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12227 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12229 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12230 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12231 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12235 /* Move the notes and links of TEM elsewhere.
12236 This might delete other dead insns recursively.
12237 First set the pattern to something that won't use
12240 PATTERN (tem
) = pc_rtx
;
12242 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12243 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12244 distribute_links (LOG_LINKS (tem
));
12246 PUT_CODE (tem
, NOTE
);
12247 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12248 NOTE_SOURCE_FILE (tem
) = 0;
12251 /* Delete the setter too. */
12254 PATTERN (cc0_setter
) = pc_rtx
;
12256 distribute_notes (REG_NOTES (cc0_setter
),
12257 cc0_setter
, cc0_setter
,
12258 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12259 distribute_links (LOG_LINKS (cc0_setter
));
12261 PUT_CODE (cc0_setter
, NOTE
);
12262 NOTE_LINE_NUMBER (cc0_setter
)
12263 = NOTE_INSN_DELETED
;
12264 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12268 /* If the register is both set and used here, put the
12269 REG_DEAD note here, but place a REG_UNUSED note
12270 here too unless there already is one. */
12271 else if (reg_referenced_p (XEXP (note
, 0),
12276 if (! find_regno_note (tem
, REG_UNUSED
,
12277 REGNO (XEXP (note
, 0))))
12279 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12284 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12286 /* If there isn't already a REG_UNUSED note, put one
12288 if (! find_regno_note (tem
, REG_UNUSED
,
12289 REGNO (XEXP (note
, 0))))
12294 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12295 || (GET_CODE (tem
) == CALL_INSN
12296 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12300 /* If we are doing a 3->2 combination, and we have a
12301 register which formerly died in i3 and was not used
12302 by i2, which now no longer dies in i3 and is used in
12303 i2 but does not die in i2, and place is between i2
12304 and i3, then we may need to move a link from place to
12306 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12307 && INSN_CUID (place
) > INSN_CUID (i2
)
12309 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12310 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12312 rtx links
= LOG_LINKS (place
);
12313 LOG_LINKS (place
) = 0;
12314 distribute_links (links
);
12319 if (tem
== bb
->head
)
12323 /* We haven't found an insn for the death note and it
12324 is still a REG_DEAD note, but we have hit the beginning
12325 of the block. If the existing life info says the reg
12326 was dead, there's nothing left to do. Otherwise, we'll
12327 need to do a global life update after combine. */
12328 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12329 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12330 REGNO (XEXP (note
, 0))))
12332 SET_BIT (refresh_blocks
, this_basic_block
);
12337 /* If the register is set or already dead at PLACE, we needn't do
12338 anything with this note if it is still a REG_DEAD note.
12339 We can here if it is set at all, not if is it totally replace,
12340 which is what `dead_or_set_p' checks, so also check for it being
12343 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12345 unsigned int regno
= REGNO (XEXP (note
, 0));
12347 if (dead_or_set_p (place
, XEXP (note
, 0))
12348 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12350 /* Unless the register previously died in PLACE, clear
12351 reg_last_death. [I no longer understand why this is
12353 if (reg_last_death
[regno
] != place
)
12354 reg_last_death
[regno
] = 0;
12358 reg_last_death
[regno
] = place
;
12360 /* If this is a death note for a hard reg that is occupying
12361 multiple registers, ensure that we are still using all
12362 parts of the object. If we find a piece of the object
12363 that is unused, we must arrange for an appropriate REG_DEAD
12364 note to be added for it. However, we can't just emit a USE
12365 and tag the note to it, since the register might actually
12366 be dead; so we recourse, and the recursive call then finds
12367 the previous insn that used this register. */
12369 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12370 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12372 unsigned int endregno
12373 = regno
+ HARD_REGNO_NREGS (regno
,
12374 GET_MODE (XEXP (note
, 0)));
12378 for (i
= regno
; i
< endregno
; i
++)
12379 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12380 && ! find_regno_fusage (place
, USE
, i
))
12381 || dead_or_set_regno_p (place
, i
))
12386 /* Put only REG_DEAD notes for pieces that are
12387 not already dead or set. */
12389 for (i
= regno
; i
< endregno
;
12390 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12392 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12393 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12395 if (! dead_or_set_p (place
, piece
)
12396 && ! reg_bitfield_target_p (piece
,
12400 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12402 distribute_notes (new_note
, place
, place
,
12403 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12405 else if (! refers_to_regno_p (i
, i
+ 1,
12406 PATTERN (place
), 0)
12407 && ! find_regno_fusage (place
, USE
, i
))
12408 for (tem
= PREV_INSN (place
); ;
12409 tem
= PREV_INSN (tem
))
12411 if (! INSN_P (tem
))
12413 if (tem
== bb
->head
)
12415 SET_BIT (refresh_blocks
,
12422 if (dead_or_set_p (tem
, piece
)
12423 || reg_bitfield_target_p (piece
,
12427 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12442 /* Any other notes should not be present at this point in the
12449 XEXP (note
, 1) = REG_NOTES (place
);
12450 REG_NOTES (place
) = note
;
12452 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12453 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12454 && GET_CODE (XEXP (note
, 0)) == REG
)
12455 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12459 if ((REG_NOTE_KIND (note
) == REG_DEAD
12460 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12461 && GET_CODE (XEXP (note
, 0)) == REG
)
12462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12464 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12465 REG_NOTE_KIND (note
),
12467 REG_NOTES (place2
));
12472 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12473 I3, I2, and I1 to new locations. This is also called in one case to
12474 add a link pointing at I3 when I3's destination is changed. */
12477 distribute_links (links
)
12480 rtx link
, next_link
;
12482 for (link
= links
; link
; link
= next_link
)
12488 next_link
= XEXP (link
, 1);
12490 /* If the insn that this link points to is a NOTE or isn't a single
12491 set, ignore it. In the latter case, it isn't clear what we
12492 can do other than ignore the link, since we can't tell which
12493 register it was for. Such links wouldn't be used by combine
12496 It is not possible for the destination of the target of the link to
12497 have been changed by combine. The only potential of this is if we
12498 replace I3, I2, and I1 by I3 and I2. But in that case the
12499 destination of I2 also remains unchanged. */
12501 if (GET_CODE (XEXP (link
, 0)) == NOTE
12502 || (set
= single_set (XEXP (link
, 0))) == 0)
12505 reg
= SET_DEST (set
);
12506 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12507 || GET_CODE (reg
) == SIGN_EXTRACT
12508 || GET_CODE (reg
) == STRICT_LOW_PART
)
12509 reg
= XEXP (reg
, 0);
12511 /* A LOG_LINK is defined as being placed on the first insn that uses
12512 a register and points to the insn that sets the register. Start
12513 searching at the next insn after the target of the link and stop
12514 when we reach a set of the register or the end of the basic block.
12516 Note that this correctly handles the link that used to point from
12517 I3 to I2. Also note that not much searching is typically done here
12518 since most links don't point very far away. */
12520 for (insn
= NEXT_INSN (XEXP (link
, 0));
12521 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12522 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12523 insn
= NEXT_INSN (insn
))
12524 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12526 if (reg_referenced_p (reg
, PATTERN (insn
)))
12530 else if (GET_CODE (insn
) == CALL_INSN
12531 && find_reg_fusage (insn
, USE
, reg
))
12537 /* If we found a place to put the link, place it there unless there
12538 is already a link to the same insn as LINK at that point. */
12544 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12545 if (XEXP (link2
, 0) == XEXP (link
, 0))
12550 XEXP (link
, 1) = LOG_LINKS (place
);
12551 LOG_LINKS (place
) = link
;
12553 /* Set added_links_insn to the earliest insn we added a
12555 if (added_links_insn
== 0
12556 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12557 added_links_insn
= place
;
12563 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12569 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12570 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12571 insn
= NEXT_INSN (insn
);
12573 if (INSN_UID (insn
) > max_uid_cuid
)
12576 return INSN_CUID (insn
);
12580 dump_combine_stats (file
)
12585 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12586 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12590 dump_combine_total_stats (file
)
12595 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12596 total_attempts
, total_merges
, total_extras
, total_successes
);