gcc/config/m32r/m32r.c

   1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
   2    Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21 #include "config.h"
  22 #include "system.h"
  23 #include "tree.h"
  24 #include "rtl.h"
  25 #include "regs.h"
  26 #include "hard-reg-set.h"
  27 #include "real.h"
  28 #include "insn-config.h"
  29 #include "conditions.h"
  30 #include "output.h"
  31 #include "insn-attr.h"
  32 #include "flags.h"
  33 #include "expr.h"
  34 #include "function.h"
  35 #include "recog.h"
  36 #include "toplev.h"
  37 #include "m32r-protos.h"
  38
  39 /* Save the operands last given to a compare for use when we
  40    generate a scc or bcc insn.  */
  41 rtx m32r_compare_op0, m32r_compare_op1;
  42
  43 /* Array of valid operand punctuation characters.  */
  44 char m32r_punct_chars[256];
  45
  46 /* Selected code model.  */
  47 const char * m32r_model_string = M32R_MODEL_DEFAULT;
  48 enum m32r_model m32r_model;
  49
  50 /* Selected SDA support.  */
  51 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
  52 enum m32r_sdata m32r_sdata;
  53
  54 /* Scheduler support */
  55 int m32r_sched_odd_word_p;
  56
  57 /* Forward declaration.  */
  58 static void init_reg_tables                     PARAMS ((void));
  59
  60 /* Called by OVERRIDE_OPTIONS to initialize various things.  */
  61
  62 void
  63 m32r_init ()
  64 {
  65   init_reg_tables ();
  66
  67   /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
  68   memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
  69   m32r_punct_chars['#'] = 1;
  70   m32r_punct_chars['@'] = 1; /* ??? no longer used */
  71
  72   /* Provide default value if not specified.  */
  73   if (!g_switch_set)
  74     g_switch_value = SDATA_DEFAULT_SIZE;
  75
  76   if (strcmp (m32r_model_string, "small") == 0)
  77     m32r_model = M32R_MODEL_SMALL;
  78   else if (strcmp (m32r_model_string, "medium") == 0)
  79     m32r_model = M32R_MODEL_MEDIUM;
  80   else if (strcmp (m32r_model_string, "large") == 0)
  81     m32r_model = M32R_MODEL_LARGE;
  82   else
  83     error ("bad value (%s) for -mmodel switch", m32r_model_string);
  84
  85   if (strcmp (m32r_sdata_string, "none") == 0)
  86     m32r_sdata = M32R_SDATA_NONE;
  87   else if (strcmp (m32r_sdata_string, "sdata") == 0)
  88     m32r_sdata = M32R_SDATA_SDATA;
  89   else if (strcmp (m32r_sdata_string, "use") == 0)
  90     m32r_sdata = M32R_SDATA_USE;
  91   else
  92     error ("bad value (%s) for -msdata switch", m32r_sdata_string);
  93 }
  94
  95 /* Vectors to keep interesting information about registers where it can easily
  96    be got.  We use to use the actual mode value as the bit number, but there
  97    is (or may be) more than 32 modes now.  Instead we use two tables: one
  98    indexed by hard register number, and one indexed by mode.  */
  99
 100 /* The purpose of m32r_mode_class is to shrink the range of modes so that
 101    they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
 102    mapped into one m32r_mode_class mode.  */
 103
 104 enum m32r_mode_class
 105 {
 106   C_MODE,
 107   S_MODE, D_MODE, T_MODE, O_MODE,
 108   SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
 109 };
 110
 111 /* Modes for condition codes.  */
 112 #define C_MODES (1 << (int) C_MODE)
 113
 114 /* Modes for single-word and smaller quantities.  */
 115 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
 116
 117 /* Modes for double-word and smaller quantities.  */
 118 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
 119
 120 /* Modes for quad-word and smaller quantities.  */
 121 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
 122
 123 /* Modes for accumulators.  */
 124 #define A_MODES (1 << (int) A_MODE)
 125
 126 /* Value is 1 if register/mode pair is acceptable on arc.  */
 127
 128 unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
 129 {
 130   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
 131   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
 132   S_MODES, C_MODES, A_MODES
 133 };
 134
 135 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
 136
 137 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
 138
 139 static void
 140 init_reg_tables ()
 141 {
 142   int i;
 143
 144   for (i = 0; i < NUM_MACHINE_MODES; i++)
 145     {
 146       switch (GET_MODE_CLASS (i))
 147         {
 148         case MODE_INT:
 149         case MODE_PARTIAL_INT:
 150         case MODE_COMPLEX_INT:
 151           if (GET_MODE_SIZE (i) <= 4)
 152             m32r_mode_class[i] = 1 << (int) S_MODE;
 153           else if (GET_MODE_SIZE (i) == 8)
 154             m32r_mode_class[i] = 1 << (int) D_MODE;
 155           else if (GET_MODE_SIZE (i) == 16)
 156             m32r_mode_class[i] = 1 << (int) T_MODE;
 157           else if (GET_MODE_SIZE (i) == 32)
 158             m32r_mode_class[i] = 1 << (int) O_MODE;
 159           else
 160             m32r_mode_class[i] = 0;
 161           break;
 162         case MODE_FLOAT:
 163         case MODE_COMPLEX_FLOAT:
 164           if (GET_MODE_SIZE (i) <= 4)
 165             m32r_mode_class[i] = 1 << (int) SF_MODE;
 166           else if (GET_MODE_SIZE (i) == 8)
 167             m32r_mode_class[i] = 1 << (int) DF_MODE;
 168           else if (GET_MODE_SIZE (i) == 16)
 169             m32r_mode_class[i] = 1 << (int) TF_MODE;
 170           else if (GET_MODE_SIZE (i) == 32)
 171             m32r_mode_class[i] = 1 << (int) OF_MODE;
 172           else
 173             m32r_mode_class[i] = 0;
 174           break;
 175         case MODE_CC:
 176         default:
 177           /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
 178              we must explicitly check for them here.  */
 179           if (i == (int) CCmode)
 180             m32r_mode_class[i] = 1 << (int) C_MODE;
 181           else
 182             m32r_mode_class[i] = 0;
 183           break;
 184         }
 185     }
 186
 187   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 188     {
 189       if (GPR_P (i))
 190         m32r_regno_reg_class[i] = GENERAL_REGS;
 191       else if (i == ARG_POINTER_REGNUM)
 192         m32r_regno_reg_class[i] = GENERAL_REGS;
 193       else
 194         m32r_regno_reg_class[i] = NO_REGS;
 195     }
 196 }
 197 \f
 198 /* M32R specific attribute support.
 199
 200    interrupt - for interrupt functions
 201
 202    model - select code model used to access object
 203
 204         small: addresses use 24 bits, use bl to make calls
 205         medium: addresses use 32 bits, use bl to make calls
 206         large: addresses use 32 bits, use seth/add3/jl to make calls
 207
 208         Grep for MODEL in m32r.h for more info.
 209 */
 210
 211 static tree interrupt_ident1;
 212 static tree interrupt_ident2;
 213 static tree model_ident1;
 214 static tree model_ident2;
 215 static tree small_ident1;
 216 static tree small_ident2;
 217 static tree medium_ident1;
 218 static tree medium_ident2;
 219 static tree large_ident1;
 220 static tree large_ident2;
 221
 222 static void
 223 init_idents PARAMS ((void))
 224 {
 225   if (interrupt_ident1 == 0)
 226     {
 227       interrupt_ident1 = get_identifier ("interrupt");
 228       interrupt_ident2 = get_identifier ("__interrupt__");
 229       model_ident1 = get_identifier ("model");
 230       model_ident2 = get_identifier ("__model__");
 231       small_ident1 = get_identifier ("small");
 232       small_ident2 = get_identifier ("__small__");
 233       medium_ident1 = get_identifier ("medium");
 234       medium_ident2 = get_identifier ("__medium__");
 235       large_ident1 = get_identifier ("large");
 236       large_ident2 = get_identifier ("__large__");
 237     }
 238 }
 239
 240 /* Return nonzero if IDENTIFIER is a valid decl attribute.  */
 241
 242 int
 243 m32r_valid_machine_decl_attribute (type, attributes, identifier, args)
 244      tree type ATTRIBUTE_UNUSED;
 245      tree attributes ATTRIBUTE_UNUSED;
 246      tree identifier;
 247      tree args;
 248 {
 249   init_idents ();
 250
 251   if ((identifier == interrupt_ident1
 252        || identifier == interrupt_ident2)
 253       && list_length (args) == 0)
 254     return 1;
 255
 256   if ((identifier == model_ident1
 257        || identifier == model_ident2)
 258       && list_length (args) == 1
 259       && (TREE_VALUE (args) == small_ident1
 260           || TREE_VALUE (args) == small_ident2
 261           || TREE_VALUE (args) == medium_ident1
 262           || TREE_VALUE (args) == medium_ident2
 263           || TREE_VALUE (args) == large_ident1
 264           || TREE_VALUE (args) == large_ident2))
 265     return 1;
 266
 267   return 0;
 268 }
 269
 270 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
 271    and two if they are nearly compatible (which causes a warning to be
 272    generated).  */
 273
 274 int
 275 m32r_comp_type_attributes (type1, type2)
 276      tree type1 ATTRIBUTE_UNUSED;
 277      tree type2 ATTRIBUTE_UNUSED;
 278 {
 279   return 1;
 280 }
 281
 282 /* Set the default attributes for TYPE.  */
 283
 284 void
 285 m32r_set_default_type_attributes (type)
 286      tree type ATTRIBUTE_UNUSED;
 287 {
 288 }
 289 \f
 290 /* A C statement or statements to switch to the appropriate
 291    section for output of DECL.  DECL is either a `VAR_DECL' node
 292    or a constant of some sort.  RELOC indicates whether forming
 293    the initial value of DECL requires link-time relocations.  */
 294
 295 void
 296 m32r_select_section (decl, reloc)
 297      tree decl;
 298      int reloc;
 299 {
 300   if (TREE_CODE (decl) == STRING_CST)
 301     {
 302       if (! flag_writable_strings)
 303         const_section ();
 304       else
 305         data_section ();
 306     }
 307   else if (TREE_CODE (decl) == VAR_DECL)
 308     {
 309       if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
 310         sdata_section ();
 311       else if ((flag_pic && reloc)
 312                || !TREE_READONLY (decl)
 313                || TREE_SIDE_EFFECTS (decl)
 314                || !DECL_INITIAL (decl)
 315                || (DECL_INITIAL (decl) != error_mark_node
 316                    && !TREE_CONSTANT (DECL_INITIAL (decl))))
 317         data_section ();
 318       else
 319         const_section ();
 320     }
 321   else
 322     const_section ();
 323 }
 324
 325 /* Encode section information of DECL, which is either a VAR_DECL,
 326    FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
 327
 328    For the M32R we want to record:
 329
 330    - whether the object lives in .sdata/.sbss.
 331      objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
 332
 333    - what code model should be used to access the object
 334      small: recorded with no flag - for space efficiency since they'll
 335             be the most common
 336      medium: prefixed with MEDIUM_FLAG_CHAR
 337      large: prefixed with LARGE_FLAG_CHAR
 338 */
 339
 340 void
 341 m32r_encode_section_info (decl)
 342      tree decl;
 343 {
 344   char prefix = 0;
 345   tree model = 0;
 346
 347   switch (TREE_CODE (decl))
 348     {
 349     case VAR_DECL :
 350     case FUNCTION_DECL :
 351       model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
 352       break;
 353     case STRING_CST :
 354     case CONSTRUCTOR :
 355       /* ??? document all others that can appear here */
 356     default :
 357       return;
 358     }
 359
 360   /* Only mark the object as being small data area addressable if
 361      it hasn't been explicitly marked with a code model.
 362
 363      The user can explicitly put an object in the small data area with the
 364      section attribute.  If the object is in sdata/sbss and marked with a
 365      code model do both [put the object in .sdata and mark it as being
 366      addressed with a specific code model - don't mark it as being addressed
 367      with an SDA reloc though].  This is ok and might be useful at times.  If
 368      the object doesn't fit the linker will give an error.  */
 369
 370   if (! model)
 371     {
 372       if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
 373           && DECL_SECTION_NAME (decl) != NULL_TREE)
 374         {
 375           char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
 376           if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
 377             {
 378 #if 0 /* ??? There's no reason to disallow this, is there?  */
 379               if (TREE_READONLY (decl))
 380                 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
 381 #endif
 382               prefix = SDATA_FLAG_CHAR;
 383             }
 384         }
 385       else
 386         {
 387           if (TREE_CODE (decl) == VAR_DECL
 388               && ! TREE_READONLY (decl)
 389               && ! TARGET_SDATA_NONE)
 390             {
 391               int size = int_size_in_bytes (TREE_TYPE (decl));
 392
 393               if (size > 0 && size <= g_switch_value)
 394                 prefix = SDATA_FLAG_CHAR;
 395             }
 396         }
 397     }
 398
 399   /* If data area not decided yet, check for a code model.  */
 400   if (prefix == 0)
 401     {
 402       if (model)
 403         {
 404           tree id;
 405
 406           init_idents ();
 407
 408           id = TREE_VALUE (TREE_VALUE (model));
 409
 410           if (id == small_ident1 || id == small_ident2)
 411             ; /* don't mark the symbol specially */
 412           else if (id == medium_ident1 || id == medium_ident2)
 413             prefix = MEDIUM_FLAG_CHAR;
 414           else if (id == large_ident1 || id == large_ident2)
 415             prefix = LARGE_FLAG_CHAR;
 416           else
 417             abort (); /* shouldn't happen */
 418         }
 419       else
 420         {
 421           if (TARGET_MODEL_SMALL)
 422             ; /* don't mark the symbol specially */
 423           else if (TARGET_MODEL_MEDIUM)
 424             prefix = MEDIUM_FLAG_CHAR;
 425           else if (TARGET_MODEL_LARGE)
 426             prefix = LARGE_FLAG_CHAR;
 427           else
 428             abort (); /* shouldn't happen */
 429         }
 430     }
 431
 432   if (prefix != 0)
 433     {
 434       rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
 435                  ? TREE_CST_RTL (decl) : DECL_RTL (decl));
 436       const char *str = XSTR (XEXP (rtl, 0), 0);
 437       int len = strlen (str);
 438       char *newstr = ggc_alloc (len + 2);
 439       strcpy (newstr + 1, str);
 440       *newstr = prefix;
 441       XSTR (XEXP (rtl, 0), 0) = newstr;
 442     }
 443 }
 444
 445 /* Do anything needed before RTL is emitted for each function.  */
 446
 447 void
 448 m32r_init_expanders ()
 449 {
 450   /* ??? At one point there was code here.  The function is left in
 451      to make it easy to experiment.  */
 452 }
 453 \f
 454 /* Acceptable arguments to the call insn.  */
 455
 456 int
 457 call_address_operand (op, mode)
 458      rtx op;
 459      enum machine_mode mode;
 460 {
 461   return symbolic_operand (op, mode);
 462
 463 /* Constants and values in registers are not OK, because
 464    the m32r BL instruction can only support PC relative branching.  */
 465 }
 466
 467 int
 468 call_operand (op, mode)
 469      rtx op;
 470      enum machine_mode mode;
 471 {
 472   if (GET_CODE (op) != MEM)
 473     return 0;
 474   op = XEXP (op, 0);
 475   return call_address_operand (op, mode);
 476 }
 477
 478 /* Returns 1 if OP is a symbol reference.  */
 479
 480 int
 481 symbolic_operand (op, mode)
 482      rtx op;
 483      enum machine_mode mode ATTRIBUTE_UNUSED;
 484 {
 485   switch (GET_CODE (op))
 486     {
 487     case SYMBOL_REF:
 488     case LABEL_REF:
 489     case CONST :
 490       return 1;
 491
 492     default:
 493       return 0;
 494     }
 495 }
 496
 497 /* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
 498
 499 int
 500 small_data_operand (op, mode)
 501      rtx op;
 502      enum machine_mode mode ATTRIBUTE_UNUSED;
 503 {
 504   if (! TARGET_SDATA_USE)
 505     return 0;
 506
 507   if (GET_CODE (op) == SYMBOL_REF)
 508     return SDATA_NAME_P (XSTR (op, 0));
 509
 510   if (GET_CODE (op) == CONST
 511       && GET_CODE (XEXP (op, 0)) == PLUS
 512       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 513       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 514       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 515     return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
 516
 517   return 0;
 518 }
 519
 520 /* Return 1 if OP is a symbol that can use 24 bit addressing.  */
 521
 522 int
 523 addr24_operand (op, mode)
 524      rtx op;
 525      enum machine_mode mode ATTRIBUTE_UNUSED;
 526 {
 527   if (GET_CODE (op) == LABEL_REF)
 528     return TARGET_ADDR24;
 529
 530   if (GET_CODE (op) == SYMBOL_REF)
 531     return (SMALL_NAME_P (XSTR (op, 0))
 532             || (TARGET_ADDR24
 533                 && (CONSTANT_POOL_ADDRESS_P (op)
 534                     || LIT_NAME_P (XSTR (op, 0)))));
 535
 536   if (GET_CODE (op) == CONST
 537       && GET_CODE (XEXP (op, 0)) == PLUS
 538       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 539       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 540       && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 541     {
 542       rtx sym = XEXP (XEXP (op, 0), 0);
 543       return (SMALL_NAME_P (XSTR (sym, 0))
 544               || (TARGET_ADDR24
 545                   && (CONSTANT_POOL_ADDRESS_P (op)
 546                       || LIT_NAME_P (XSTR (op, 0)))));
 547     }
 548
 549   return 0;
 550 }
 551
 552 /* Return 1 if OP is a symbol that needs 32 bit addressing.  */
 553
 554 int
 555 addr32_operand (op, mode)
 556      rtx op;
 557      enum machine_mode mode;
 558 {
 559   if (GET_CODE (op) == LABEL_REF)
 560     return TARGET_ADDR32;
 561
 562   if (GET_CODE (op) == SYMBOL_REF)
 563     return (! addr24_operand (op, mode)
 564             && ! small_data_operand (op, mode));
 565
 566   if (GET_CODE (op) == CONST
 567       && GET_CODE (XEXP (op, 0)) == PLUS
 568       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 569       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
 570     {
 571       return (! addr24_operand (op, mode)
 572               && ! small_data_operand (op, mode));
 573     }
 574
 575   return 0;
 576 }
 577
 578 /* Return 1 if OP is a function that can be called with the `bl' insn.  */
 579
 580 int
 581 call26_operand (op, mode)
 582      rtx op;
 583      enum machine_mode mode ATTRIBUTE_UNUSED;
 584 {
 585   if (GET_CODE (op) == SYMBOL_REF)
 586     return ! LARGE_NAME_P (XSTR (op, 0));
 587
 588   return TARGET_CALL26;
 589 }
 590
 591 /* Returns 1 if OP is an acceptable operand for seth/add3.  */
 592
 593 int
 594 seth_add3_operand (op, mode)
 595      rtx op;
 596      enum machine_mode mode ATTRIBUTE_UNUSED;
 597 {
 598   if (GET_CODE (op) == SYMBOL_REF
 599       || GET_CODE (op) == LABEL_REF)
 600     return 1;
 601
 602   if (GET_CODE (op) == CONST
 603       && GET_CODE (XEXP (op, 0)) == PLUS
 604       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 605       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 606       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 607     return 1;
 608
 609   return 0;
 610 }
 611
 612 /* Return true if OP is a signed 8 bit immediate value.  */
 613
 614 int
 615 int8_operand (op, mode)
 616      rtx op;
 617      enum machine_mode mode ATTRIBUTE_UNUSED;
 618 {
 619   if (GET_CODE (op) != CONST_INT)
 620     return 0;
 621   return INT8_P (INTVAL (op));
 622 }
 623
 624 /* Return true if OP is a signed 16 bit immediate value
 625    useful in comparisons.  */
 626
 627 int
 628 cmp_int16_operand (op, mode)
 629      rtx op;
 630      enum machine_mode mode ATTRIBUTE_UNUSED;
 631 {
 632   if (GET_CODE (op) != CONST_INT)
 633     return 0;
 634   return CMP_INT16_P (INTVAL (op));
 635 }
 636
 637 /* Return true if OP is an unsigned 16 bit immediate value.  */
 638
 639 int
 640 uint16_operand (op, mode)
 641      rtx op;
 642      enum machine_mode mode ATTRIBUTE_UNUSED;
 643 {
 644   if (GET_CODE (op) != CONST_INT)
 645     return 0;
 646   return UINT16_P (INTVAL (op));
 647 }
 648
 649 /* Return true if OP is a register or signed 16 bit value.  */
 650
 651 int
 652 reg_or_int16_operand (op, mode)
 653      rtx op;
 654      enum machine_mode mode;
 655 {
 656   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 657     return register_operand (op, mode);
 658   if (GET_CODE (op) != CONST_INT)
 659     return 0;
 660   return INT16_P (INTVAL (op));
 661 }
 662
 663 /* Return true if OP is a register or an unsigned 16 bit value.  */
 664
 665 int
 666 reg_or_uint16_operand (op, mode)
 667      rtx op;
 668      enum machine_mode mode;
 669 {
 670   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 671     return register_operand (op, mode);
 672   if (GET_CODE (op) != CONST_INT)
 673     return 0;
 674   return UINT16_P (INTVAL (op));
 675 }
 676
 677 /* Return true if OP is a register or an integer value that can be
 678    used is SEQ/SNE.  We can use either XOR of the value or ADD of
 679    the negative of the value for the constant.  Don't allow 0,
 680    because that is special cased.  */
 681
 682 int
 683 reg_or_eq_int16_operand (op, mode)
 684      rtx op;
 685      enum machine_mode mode;
 686 {
 687   HOST_WIDE_INT value;
 688
 689   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 690     return register_operand (op, mode);
 691
 692   if (GET_CODE (op) != CONST_INT)
 693     return 0;
 694
 695   value = INTVAL (op);
 696   return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
 697 }
 698
 699 /* Return true if OP is a register or signed 16 bit value for compares.  */
 700
 701 int
 702 reg_or_cmp_int16_operand (op, mode)
 703      rtx op;
 704      enum machine_mode mode;
 705 {
 706   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 707     return register_operand (op, mode);
 708   if (GET_CODE (op) != CONST_INT)
 709     return 0;
 710   return CMP_INT16_P (INTVAL (op));
 711 }
 712
 713 /* Return true if OP is a const_int requiring two instructions to load.  */
 714
 715 int
 716 two_insn_const_operand (op, mode)
 717      rtx op;
 718      enum machine_mode mode ATTRIBUTE_UNUSED;
 719 {
 720   if (GET_CODE (op) != CONST_INT)
 721     return 0;
 722   if (INT16_P (INTVAL (op))
 723       || UINT24_P (INTVAL (op))
 724       || UPPER16_P (INTVAL (op)))
 725     return 0;
 726   return 1;
 727 }
 728
 729 /* Return true if OP is an acceptable argument for a single word
 730    move source.  */
 731
 732 int
 733 move_src_operand (op, mode)
 734      rtx op;
 735      enum machine_mode mode;
 736 {
 737   switch (GET_CODE (op))
 738     {
 739     case SYMBOL_REF :
 740     case CONST :
 741       return addr24_operand (op, mode);
 742     case CONST_INT :
 743       /* ??? We allow more cse opportunities if we only allow constants
 744          loadable with one insn, and split the rest into two.  The instances
 745          where this would help should be rare and the current way is
 746          simpler.  */
 747       return INT32_P (INTVAL (op));
 748     case LABEL_REF :
 749       return TARGET_ADDR24;
 750     case CONST_DOUBLE :
 751       if (mode == SFmode)
 752         return 1;
 753       else if (mode == SImode)
 754         {
 755           /* Large unsigned constants are represented as const_double's.  */
 756           unsigned HOST_WIDE_INT low, high;
 757
 758           low = CONST_DOUBLE_LOW (op);
 759           high = CONST_DOUBLE_HIGH (op);
 760           return high == 0 && low <= 0xffffffff;
 761         }
 762       else
 763         return 0;
 764     case REG :
 765       return register_operand (op, mode);
 766     case SUBREG :
 767       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 768          pseudo-reg and is now a stack slot.  */
 769       if (GET_CODE (SUBREG_REG (op)) == MEM)
 770         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 771       else
 772         return register_operand (op, mode);
 773     case MEM :
 774       if (GET_CODE (XEXP (op, 0)) == PRE_INC
 775           || GET_CODE (XEXP (op, 0)) == PRE_DEC)
 776         return 0;               /* loads can't do pre-{inc,dec} */
 777       return address_operand (XEXP (op, 0), mode);
 778     default :
 779       return 0;
 780     }
 781 }
 782
 783 /* Return true if OP is an acceptable argument for a double word
 784    move source.  */
 785
 786 int
 787 move_double_src_operand (op, mode)
 788      rtx op;
 789      enum machine_mode mode;
 790 {
 791   switch (GET_CODE (op))
 792     {
 793     case CONST_INT :
 794     case CONST_DOUBLE :
 795       return 1;
 796     case REG :
 797       return register_operand (op, mode);
 798     case SUBREG :
 799       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 800          pseudo-reg and is now a stack slot.  */
 801       if (GET_CODE (SUBREG_REG (op)) == MEM)
 802         return move_double_src_operand (SUBREG_REG (op), mode);
 803       else
 804         return register_operand (op, mode);
 805     case MEM :
 806       /* Disallow auto inc/dec for now.  */
 807       if (GET_CODE (XEXP (op, 0)) == PRE_DEC
 808           || GET_CODE (XEXP (op, 0)) == PRE_INC)
 809         return 0;
 810       return address_operand (XEXP (op, 0), mode);
 811     default :
 812       return 0;
 813     }
 814 }
 815
 816 /* Return true if OP is an acceptable argument for a move destination.  */
 817
 818 int
 819 move_dest_operand (op, mode)
 820      rtx op;
 821      enum machine_mode mode;
 822 {
 823   switch (GET_CODE (op))
 824     {
 825     case REG :
 826       return register_operand (op, mode);
 827     case SUBREG :
 828       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 829          pseudo-reg and is now a stack slot.  */
 830       if (GET_CODE (SUBREG_REG (op)) == MEM)
 831         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 832       else
 833         return register_operand (op, mode);
 834     case MEM :
 835       if (GET_CODE (XEXP (op, 0)) == POST_INC)
 836         return 0;               /* stores can't do post inc */
 837       return address_operand (XEXP (op, 0), mode);
 838     default :
 839       return 0;
 840     }
 841 }
 842
 843 /* Return 1 if OP is a DImode const we want to handle inline.
 844    This must match the code in the movdi pattern.
 845    It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
 846
 847 int
 848 easy_di_const (op)
 849      rtx op;
 850 {
 851   rtx high_rtx, low_rtx;
 852   HOST_WIDE_INT high, low;
 853
 854   split_double (op, &high_rtx, &low_rtx);
 855   high = INTVAL (high_rtx);
 856   low = INTVAL (low_rtx);
 857   /* Pick constants loadable with 2 16 bit `ldi' insns.  */
 858   if (high >= -128 && high <= 127
 859       && low >= -128 && low <= 127)
 860     return 1;
 861   return 0;
 862 }
 863
 864 /* Return 1 if OP is a DFmode const we want to handle inline.
 865    This must match the code in the movdf pattern.
 866    It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
 867
 868 int
 869 easy_df_const (op)
 870      rtx op;
 871 {
 872   REAL_VALUE_TYPE r;
 873   long l[2];
 874
 875   REAL_VALUE_FROM_CONST_DOUBLE (r, op);
 876   REAL_VALUE_TO_TARGET_DOUBLE (r, l);
 877   if (l[0] == 0 && l[1] == 0)
 878     return 1;
 879   if ((l[0] & 0xffff) == 0 && l[1] == 0)
 880     return 1;
 881   return 0;
 882 }
 883
 884 /* Return 1 if OP is an EQ or NE comparison operator.  */
 885
 886 int
 887 eqne_comparison_operator (op, mode)
 888     rtx op;
 889     enum machine_mode mode ATTRIBUTE_UNUSED;
 890 {
 891   enum rtx_code code = GET_CODE (op);
 892
 893   if (GET_RTX_CLASS (code) != '<')
 894     return 0;
 895   return (code == EQ || code == NE);
 896 }
 897
 898 /* Return 1 if OP is a signed comparison operator.  */
 899
 900 int
 901 signed_comparison_operator (op, mode)
 902     rtx op;
 903     enum machine_mode mode ATTRIBUTE_UNUSED;
 904 {
 905   enum rtx_code code = GET_CODE (op);
 906
 907   if (GET_RTX_CLASS (code) != '<')
 908     return 0;
 909   return (code == EQ || code == NE
 910           || code == LT || code == LE || code == GT || code == GE);
 911 }
 912
 913 /* Return 1 if OP is (mem (reg ...)).
 914    This is used in insn length calcs.  */
 915
 916 int
 917 memreg_operand (op, mode)
 918      rtx op;
 919      enum machine_mode mode ATTRIBUTE_UNUSED;
 920 {
 921   return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
 922 }
 923
 924 /* Return true if OP is an acceptable input argument for a zero/sign extend
 925    operation.  */
 926
 927 int
 928 extend_operand (op, mode)
 929      rtx op;
 930      enum machine_mode mode;
 931 {
 932   rtx addr;
 933
 934   switch (GET_CODE (op))
 935     {
 936     case REG :
 937     case SUBREG :
 938       return register_operand (op, mode);
 939
 940     case MEM :
 941       addr = XEXP (op, 0);
 942       if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
 943         return 0;               /* loads can't do pre inc/pre dec */
 944
 945       return address_operand (addr, mode);
 946
 947     default :
 948       return 0;
 949     }
 950 }
 951
 952 /* Return non-zero if the operand is an insn that is a small insn.
 953    Allow const_int 0 as well, which is a placeholder for NOP slots.  */
 954
 955 int
 956 small_insn_p (op, mode)
 957      rtx op;
 958      enum machine_mode mode ATTRIBUTE_UNUSED;
 959 {
 960   if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
 961     return 1;
 962
 963   if (! INSN_P (op))
 964     return 0;
 965
 966   return get_attr_length (op) == 2;
 967 }
 968
 969 /* Return non-zero if the operand is an insn that is a large insn.  */
 970
 971 int
 972 large_insn_p (op, mode)
 973      rtx op;
 974      enum machine_mode mode ATTRIBUTE_UNUSED;
 975 {
 976   if (! INSN_P (op))
 977     return 0;
 978
 979   return get_attr_length (op) != 2;
 980 }
 981
 982 \f
 983 /* Comparisons.  */
 984
 985 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
 986    return the mode to be used for the comparison.  */
 987
 988 int
 989 m32r_select_cc_mode (op, x, y)
 990      int op ATTRIBUTE_UNUSED;
 991      rtx x ATTRIBUTE_UNUSED;
 992      rtx y ATTRIBUTE_UNUSED;
 993 {
 994   return (int) CCmode;
 995 }
 996
 997 /* X and Y are two things to compare using CODE.  Emit the compare insn and
 998    return the rtx for compare [arg0 of the if_then_else].
 999    If need_compare is true then the comparison insn must be generated, rather
1000    than being susummed into the following branch instruction.  */
1001
1002 rtx
1003 gen_compare (code, x, y, need_compare)
1004      enum rtx_code code;
1005      rtx x, y;
1006      int need_compare;
1007 {
1008   enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1009   enum rtx_code compare_code, branch_code;
1010   rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1011   int must_swap = 0;
1012
1013   switch (code)
1014     {
1015     case EQ:  compare_code = EQ;  branch_code = NE; break;
1016     case NE:  compare_code = EQ;  branch_code = EQ; break;
1017     case LT:  compare_code = LT;  branch_code = NE; break;
1018     case LE:  compare_code = LT;  branch_code = EQ; must_swap = 1; break;
1019     case GT:  compare_code = LT;  branch_code = NE; must_swap = 1; break;
1020     case GE:  compare_code = LT;  branch_code = EQ; break;
1021     case LTU: compare_code = LTU; branch_code = NE; break;
1022     case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1023     case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1024     case GEU: compare_code = LTU; branch_code = EQ; break;
1025
1026     default:
1027       abort ();
1028     }
1029
1030   if (need_compare)
1031     {
1032       switch (compare_code)
1033         {
1034         case EQ:
1035           if (GET_CODE (y) == CONST_INT
1036               && CMP_INT16_P (INTVAL (y))               /* reg equal to small const.  */
1037               && y != const0_rtx)
1038             {
1039               rtx tmp = gen_reg_rtx (SImode);
1040
1041               emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1042               x = tmp;
1043               y = const0_rtx;
1044             }
1045           else if (CONSTANT_P (y))                      /* reg equal to const.  */
1046             {
1047               rtx tmp = force_reg (GET_MODE (x), y);
1048               y = tmp;
1049             }
1050
1051           if (register_operand (y, SImode)              /* reg equal to reg.  */
1052               || y == const0_rtx)                       /* req equal to zero. */
1053             {
1054               emit_insn (gen_cmp_eqsi_insn (x, y));
1055
1056               return gen_rtx (code, mode, cc_reg, const0_rtx);
1057             }
1058           break;
1059
1060         case LT:
1061           if (register_operand (y, SImode)
1062               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1063             {
1064               rtx tmp = gen_reg_rtx (SImode);         /* reg compared to reg. */
1065
1066               switch (code)
1067                 {
1068                 case LT:
1069                   emit_insn (gen_cmp_ltsi_insn (x, y));
1070                   code = EQ;
1071                   break;
1072                 case LE:
1073                   if (y == const0_rtx)
1074                     tmp = const1_rtx;
1075                   else
1076                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1077                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1078                   code = EQ;
1079                   break;
1080                 case GT:
1081                   if (GET_CODE (y) == CONST_INT)
1082                     tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1083                   else
1084                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1085                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1086                   code = NE;
1087                   break;
1088                 case GE:
1089                   emit_insn (gen_cmp_ltsi_insn (x, y));
1090                   code = NE;
1091                   break;
1092                 default:
1093                   abort ();
1094                 }
1095
1096               return gen_rtx (code, mode, cc_reg, const0_rtx);
1097             }
1098           break;
1099
1100         case LTU:
1101           if (register_operand (y, SImode)
1102               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1103             {
1104               rtx tmp = gen_reg_rtx (SImode);         /* reg (unsigned) compared to reg. */
1105
1106               switch (code)
1107                 {
1108                 case LTU:
1109                   emit_insn (gen_cmp_ltusi_insn (x, y));
1110                   code = EQ;
1111                   break;
1112                 case LEU:
1113                   if (y == const0_rtx)
1114                     tmp = const1_rtx;
1115                   else
1116                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1117                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1118                   code = EQ;
1119                   break;
1120                 case GTU:
1121                   if (GET_CODE (y) == CONST_INT)
1122                     tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1123                   else
1124                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1125                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1126                   code = NE;
1127                   break;
1128                 case GEU:
1129                   emit_insn (gen_cmp_ltusi_insn (x, y));
1130                   code = NE;
1131                   break;
1132                 default:
1133                   abort();
1134                 }
1135
1136               return gen_rtx (code, mode, cc_reg, const0_rtx);
1137             }
1138           break;
1139
1140         default:
1141           abort();
1142         }
1143     }
1144   else
1145     {
1146       /* reg/reg equal comparison */
1147       if (compare_code == EQ
1148           && register_operand (y, SImode))
1149         return gen_rtx (code, mode, x, y);
1150
1151       /* reg/zero signed comparison */
1152       if ((compare_code == EQ || compare_code == LT)
1153           && y == const0_rtx)
1154         return gen_rtx (code, mode, x, y);
1155
1156       /* reg/smallconst equal comparison */
1157       if (compare_code == EQ
1158           && GET_CODE (y) == CONST_INT
1159           && CMP_INT16_P (INTVAL (y)))
1160         {
1161           rtx tmp = gen_reg_rtx (SImode);
1162           emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1163           return gen_rtx (code, mode, tmp, const0_rtx);
1164         }
1165
1166       /* reg/const equal comparison */
1167       if (compare_code == EQ
1168           && CONSTANT_P (y))
1169         {
1170           rtx tmp = force_reg (GET_MODE (x), y);
1171           return gen_rtx (code, mode, x, tmp);
1172         }
1173     }
1174
1175   if (CONSTANT_P (y))
1176     {
1177       if (must_swap)
1178         y = force_reg (GET_MODE (x), y);
1179       else
1180         {
1181           int ok_const =
1182             (code == LTU || code == LEU || code == GTU || code == GEU)
1183             ? uint16_operand (y, GET_MODE (y))
1184             : reg_or_cmp_int16_operand (y, GET_MODE (y));
1185
1186           if (! ok_const)
1187             y = force_reg (GET_MODE (x), y);
1188         }
1189     }
1190
1191   switch (compare_code)
1192     {
1193     case EQ :
1194       emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1195       break;
1196     case LT :
1197       emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1198       break;
1199     case LTU :
1200       emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1201       break;
1202
1203     default:
1204       abort ();
1205     }
1206
1207   return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1208 }
1209 \f
1210 /* Split a 2 word move (DI or DF) into component parts.  */
1211
1212 rtx
1213 gen_split_move_double (operands)
1214      rtx operands[];
1215 {
1216   enum machine_mode mode = GET_MODE (operands[0]);
1217   rtx dest = operands[0];
1218   rtx src  = operands[1];
1219   rtx val;
1220
1221   /* We might have (SUBREG (MEM)) here, so just get rid of the
1222      subregs to make this code simpler.  It is safe to call
1223      alter_subreg any time after reload.  */
1224   if (GET_CODE (dest) == SUBREG)
1225     dest = alter_subreg (dest);
1226   if (GET_CODE (src) == SUBREG)
1227     src = alter_subreg (src);
1228
1229   start_sequence ();
1230   if (GET_CODE (dest) == REG)
1231     {
1232       int dregno = REGNO (dest);
1233
1234       /* reg = reg */
1235       if (GET_CODE (src) == REG)
1236         {
1237           int sregno = REGNO (src);
1238
1239           int reverse = (dregno == sregno + 1);
1240
1241           /* We normally copy the low-numbered register first.  However, if
1242              the first register operand 0 is the same as the second register of
1243              operand 1, we must copy in the opposite order.  */
1244           emit_insn (gen_rtx_SET (VOIDmode,
1245                                   operand_subword (dest, reverse, TRUE, mode),
1246                                   operand_subword (src,  reverse, TRUE, mode)));
1247
1248           emit_insn (gen_rtx_SET (VOIDmode,
1249                                   operand_subword (dest, !reverse, TRUE, mode),
1250                                   operand_subword (src,  !reverse, TRUE, mode)));
1251         }
1252
1253       /* reg = constant */
1254       else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1255         {
1256           rtx words[2];
1257           split_double (src, &words[0], &words[1]);
1258           emit_insn (gen_rtx_SET (VOIDmode,
1259                                   operand_subword (dest, 0, TRUE, mode),
1260                                   words[0]));
1261
1262           emit_insn (gen_rtx_SET (VOIDmode,
1263                                   operand_subword (dest, 1, TRUE, mode),
1264                                   words[1]));
1265         }
1266
1267       /* reg = mem */
1268       else if (GET_CODE (src) == MEM)
1269         {
1270           /* If the high-address word is used in the address, we must load it
1271              last.  Otherwise, load it first.  */
1272           rtx addr = XEXP (src, 0);
1273           int reverse = (refers_to_regno_p (dregno, dregno+1, addr, 0) != 0);
1274
1275           /* We used to optimize loads from single registers as
1276
1277                 ld r1,r3+; ld r2,r3
1278
1279              if r3 were not used subsequently.  However, the REG_NOTES aren't
1280              propigated correctly by the reload phase, and it can cause bad
1281              code to be generated.  We could still try:
1282
1283                 ld r1,r3+; ld r2,r3; addi r3,-4
1284
1285              which saves 2 bytes and doesn't force longword alignment.  */
1286           emit_insn (gen_rtx_SET (VOIDmode,
1287                                   operand_subword (dest, reverse, TRUE, mode),
1288                                   change_address (src, SImode,
1289                                                   plus_constant (addr,
1290                                                                  reverse * UNITS_PER_WORD))));
1291
1292           emit_insn (gen_rtx_SET (VOIDmode,
1293                                   operand_subword (dest, !reverse, TRUE, mode),
1294                                   change_address (src, SImode,
1295                                                   plus_constant (addr,
1296                                                                  (!reverse) * UNITS_PER_WORD))));
1297         }
1298
1299       else
1300         abort ();
1301     }
1302
1303   /* mem = reg */
1304   /* We used to optimize loads from single registers as
1305
1306         st r1,r3; st r2,+r3
1307
1308      if r3 were not used subsequently.  However, the REG_NOTES aren't
1309      propigated correctly by the reload phase, and it can cause bad
1310      code to be generated.  We could still try:
1311
1312         st r1,r3; st r2,+r3; addi r3,-4
1313
1314      which saves 2 bytes and doesn't force longword alignment.  */
1315   else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1316     {
1317       rtx addr = XEXP (dest, 0);
1318
1319       emit_insn (gen_rtx_SET (VOIDmode,
1320                               change_address (dest, SImode, addr),
1321                               operand_subword (src, 0, TRUE, mode)));
1322
1323       emit_insn (gen_rtx_SET (VOIDmode,
1324                               change_address (dest, SImode,
1325                                               plus_constant (addr, UNITS_PER_WORD)),
1326                               operand_subword (src, 1, TRUE, mode)));
1327     }
1328
1329   else
1330     abort ();
1331
1332   val = gen_sequence ();
1333   end_sequence ();
1334   return val;
1335 }
1336
1337 \f
1338 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.  */
1339
1340 int
1341 function_arg_partial_nregs (cum, mode, type, named)
1342      CUMULATIVE_ARGS *cum;
1343      enum machine_mode mode;
1344      tree type;
1345      int named ATTRIBUTE_UNUSED;
1346 {
1347   int ret;
1348   int size = (((mode == BLKmode && type)
1349                ? int_size_in_bytes (type)
1350                : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1351
1352   if (*cum >= M32R_MAX_PARM_REGS)
1353     ret = 0;
1354   else if (*cum + size > M32R_MAX_PARM_REGS)
1355     ret = (*cum + size) - M32R_MAX_PARM_REGS;
1356   else
1357     ret = 0;
1358
1359   return ret;
1360 }
1361
1362 /* Do any needed setup for a variadic function.  For the M32R, we must
1363    create a register parameter block, and then copy any anonymous arguments
1364    in registers to memory.
1365
1366    CUM has not been updated for the last named argument which has type TYPE
1367    and mode MODE, and we rely on this fact.  */
1368
1369 void
1370 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1371      CUMULATIVE_ARGS *cum;
1372      enum machine_mode mode;
1373      tree type;
1374      int *pretend_size;
1375      int no_rtl;
1376 {
1377   int first_anon_arg;
1378
1379   if (no_rtl)
1380     return;
1381
1382   /* All BLKmode values are passed by reference.  */
1383   if (mode == BLKmode)
1384     abort ();
1385
1386   /* We must treat `__builtin_va_alist' as an anonymous arg.  */
1387   if (current_function_varargs)
1388     first_anon_arg = *cum;
1389   else
1390     first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1391                       + ROUND_ADVANCE_ARG (mode, type));
1392
1393   if (first_anon_arg < M32R_MAX_PARM_REGS)
1394     {
1395       /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
1396       int first_reg_offset = first_anon_arg;
1397       /* Size in words to "pretend" allocate.  */
1398       int size = M32R_MAX_PARM_REGS - first_reg_offset;
1399       rtx regblock;
1400
1401       regblock = gen_rtx_MEM (BLKmode,
1402                               plus_constant (arg_pointer_rtx,
1403                                              FIRST_PARM_OFFSET (0)));
1404       MEM_ALIAS_SET (regblock) = get_varargs_alias_set ();
1405       move_block_from_reg (first_reg_offset, regblock,
1406                            size, size * UNITS_PER_WORD);
1407
1408       *pretend_size = (size * UNITS_PER_WORD);
1409     }
1410 }
1411
1412 \f
1413 /* Implement `va_arg'.  */
1414
1415 rtx
1416 m32r_va_arg (valist, type)
1417      tree valist, type;
1418 {
1419   HOST_WIDE_INT size, rsize;
1420   tree t;
1421   rtx addr_rtx;
1422
1423   size = int_size_in_bytes (type);
1424   rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1425
1426   if (size > 8)
1427     {
1428       tree type_ptr, type_ptr_ptr;
1429
1430       /* Pass by reference.  */
1431
1432       type_ptr = build_pointer_type (type);
1433       type_ptr_ptr = build_pointer_type (type_ptr);
1434
1435       t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1436                  build_int_2 (UNITS_PER_WORD, 0));
1437       TREE_SIDE_EFFECTS (t) = 1;
1438       t = build1 (NOP_EXPR, type_ptr_ptr, t);
1439       TREE_SIDE_EFFECTS (t) = 1;
1440       t = build1 (INDIRECT_REF, type_ptr, t);
1441
1442       addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1443     }
1444   else
1445     {
1446       /* Pass by value.  */
1447
1448       if (size < UNITS_PER_WORD)
1449         {
1450           /* Care for bigendian correction on the aligned address.  */
1451           t = build (PLUS_EXPR, ptr_type_node, valist,
1452                      build_int_2 (rsize - size, 0));
1453           addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1454           addr_rtx = copy_to_reg (addr_rtx);
1455
1456           /* Increment AP.  */
1457           t = build (PLUS_EXPR, va_list_type_node, valist,
1458                      build_int_2 (rsize, 0));
1459           t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1460           TREE_SIDE_EFFECTS (t) = 1;
1461           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1462         }
1463       else
1464         {
1465           t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1466                      build_int_2 (rsize, 0));
1467           TREE_SIDE_EFFECTS (t) = 1;
1468           addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1469         }
1470     }
1471
1472   return addr_rtx;
1473 }
1474 \f
1475 int
1476 m32r_adjust_cost (insn, link, dep_insn, cost)
1477      rtx insn ATTRIBUTE_UNUSED;
1478      rtx link ATTRIBUTE_UNUSED;
1479      rtx dep_insn ATTRIBUTE_UNUSED;
1480      int cost;
1481 {
1482   return cost;
1483 }
1484
1485 \f
1486 /* Return true if INSN is real instruction bearing insn.  */
1487
1488 static int
1489 m32r_is_insn (insn)
1490      rtx insn;
1491 {
1492   return (INSN_P (insn)
1493           && GET_CODE (PATTERN (insn)) != USE
1494           && GET_CODE (PATTERN (insn)) != CLOBBER
1495           && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1496 }
1497
1498 /* Increase the priority of long instructions so that the
1499    short instructions are scheduled ahead of the long ones.  */
1500
1501 int
1502 m32r_adjust_priority (insn, priority)
1503      rtx insn;
1504      int priority;
1505 {
1506   if (m32r_is_insn (insn)
1507       && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1508     priority <<= 3;
1509
1510   return priority;
1511 }
1512
1513 \f
1514 /* Initialize for scheduling a group of instructions.  */
1515
1516 void
1517 m32r_sched_init (stream, verbose)
1518      FILE * stream ATTRIBUTE_UNUSED;
1519      int verbose ATTRIBUTE_UNUSED;
1520 {
1521   m32r_sched_odd_word_p = FALSE;
1522 }
1523
1524 \f
1525 /* Reorder the schedulers priority list if needed */
1526
1527 void
1528 m32r_sched_reorder (stream, verbose, ready, n_ready)
1529      FILE * stream;
1530      int verbose;
1531      rtx * ready;
1532      int n_ready;
1533 {
1534   if (TARGET_DEBUG)
1535     return;
1536
1537   if (verbose <= 7)
1538     stream = (FILE *)0;
1539
1540   if (stream)
1541     fprintf (stream,
1542              ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1543              n_ready,
1544              (m32r_sched_odd_word_p) ? "odd" : "even");
1545
1546   if (n_ready > 1)
1547     {
1548       rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1549       rtx * long_tail = long_head;
1550       rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1551       rtx * short_tail = short_head;
1552       rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1553       rtx * new_tail = new_head + (n_ready - 1);
1554       int   i;
1555
1556       /* Loop through the instructions, classifing them as short/long.  Try
1557          to keep 2 short together and/or 1 long.  Note, the ready list is
1558          actually ordered backwards, so keep it in that manner.  */
1559       for (i = n_ready-1; i >= 0; i--)
1560         {
1561           rtx insn = ready[i];
1562           enum rtx_code code;
1563
1564           if (! m32r_is_insn (insn))
1565             {
1566               /* Dump all current short/long insns just in case.  */
1567               while (long_head != long_tail)
1568                 *new_tail-- = *long_head++;
1569
1570               while (short_head != short_tail)
1571                 *new_tail-- = *short_head++;
1572
1573               *new_tail-- = insn;
1574               if (stream)
1575                 fprintf (stream,
1576                          ";;\t\t::: Skipping non instruction %d\n",
1577                          INSN_UID (insn));
1578
1579             }
1580
1581           else
1582             {
1583               if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1584                 *long_tail++ = insn;
1585
1586               else
1587                 *short_tail++ = insn;
1588             }
1589         }
1590
1591       /* If we are on an odd word, emit a single short instruction if
1592          we can */
1593       if (m32r_sched_odd_word_p && short_head != short_tail)
1594         *new_tail-- = *short_head++;
1595
1596       /* Now dump out all of the long instructions */
1597       while (long_head != long_tail)
1598         *new_tail-- = *long_head++;
1599
1600       /* Now dump out all of the short instructions */
1601       while (short_head != short_tail)
1602         *new_tail-- = *short_head++;
1603
1604       if (new_tail+1 != new_head)
1605         abort ();
1606
1607       bcopy ((char *) new_head, (char *) ready, sizeof (rtx) * n_ready);
1608       if (stream)
1609         {
1610 #ifdef HAIFA
1611           fprintf (stream, ";;\t\t::: New ready list:               ");
1612           debug_ready_list (ready, n_ready);
1613 #else
1614           int i;
1615           for (i = 0; i < n_ready; i++)
1616             {
1617               rtx insn = ready[i];
1618               enum rtx_code code;
1619
1620               fprintf (stream, " %d", INSN_UID (ready[i]));
1621
1622               if (! m32r_is_insn (insn))
1623                 fputs ("(?)", stream);
1624
1625               else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1626                 fputs ("(l)", stream);
1627
1628               else
1629                 fputs ("(s)", stream);
1630             }
1631
1632           fprintf (stream, "\n");
1633 #endif
1634         }
1635     }
1636 }
1637
1638 \f
1639 /* If we have a machine that can issue a variable # of instructions
1640    per cycle, indicate how many more instructions can be issued
1641    after the current one.  */
1642 int
1643 m32r_sched_variable_issue (stream, verbose, insn, how_many)
1644      FILE * stream;
1645      int verbose;
1646      rtx insn;
1647      int how_many;
1648 {
1649   int orig_odd_word_p = m32r_sched_odd_word_p;
1650   int short_p = FALSE;
1651
1652   how_many--;
1653   if (how_many > 0 && !TARGET_DEBUG)
1654     {
1655       if (! m32r_is_insn (insn))
1656         how_many++;
1657
1658       else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1659         {
1660           how_many = 0;
1661           m32r_sched_odd_word_p = 0;
1662         }
1663       else
1664         {
1665           m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1666           short_p = TRUE;
1667         }
1668     }
1669
1670   if (verbose > 7 && stream)
1671     fprintf (stream,
1672              ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1673              short_p ? "short" : "long",
1674              INSN_UID (insn),
1675              orig_odd_word_p ? "odd" : "even",
1676              how_many);
1677
1678   return how_many;
1679 }
1680 \f
1681 /* Cost functions.  */
1682
1683 /* Provide the costs of an addressing mode that contains ADDR.
1684    If ADDR is not a valid address, its cost is irrelevant.
1685
1686    This function is trivial at the moment.  This code doesn't live
1687    in m32r.h so it's easy to experiment.  */
1688
1689 int
1690 m32r_address_cost (addr)
1691      rtx addr ATTRIBUTE_UNUSED;
1692 {
1693   return 1;
1694 }
1695 \f
1696 /* Type of function DECL.
1697
1698    The result is cached.  To reset the cache at the end of a function,
1699    call with DECL = NULL_TREE.  */
1700
1701 enum m32r_function_type
1702 m32r_compute_function_type (decl)
1703      tree decl;
1704 {
1705   /* Cached value.  */
1706   static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1707   /* Last function we were called for.  */
1708   static tree last_fn = NULL_TREE;
1709
1710   /* Resetting the cached value?  */
1711   if (decl == NULL_TREE)
1712     {
1713       fn_type = M32R_FUNCTION_UNKNOWN;
1714       last_fn = NULL_TREE;
1715       return fn_type;
1716     }
1717
1718   if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1719     return fn_type;
1720
1721   /* Compute function type.  */
1722   fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
1723              ? M32R_FUNCTION_INTERRUPT
1724              : M32R_FUNCTION_NORMAL);
1725
1726   last_fn = decl;
1727   return fn_type;
1728 }
1729 \f/* Function prologue/epilogue handlers.  */
1730
1731 /* M32R stack frames look like:
1732
1733              Before call                       After call
1734         +-----------------------+       +-----------------------+
1735         |                       |       |                       |
1736    high |  local variables,     |       |  local variables,     |
1737    mem  |  reg save area, etc.  |       |  reg save area, etc.  |
1738         |                       |       |                       |
1739         +-----------------------+       +-----------------------+
1740         |                       |       |                       |
1741         |  arguments on stack.  |       |  arguments on stack.  |
1742         |                       |       |                       |
1743   SP+0->+-----------------------+       +-----------------------+
1744                                         |  reg parm save area,  |
1745                                         |  only created for     |
1746                                         |  variable argument    |
1747                                         |  functions            |
1748                                         +-----------------------+
1749                                         |   previous frame ptr  |
1750                                         +-----------------------+
1751                                         |                       |
1752                                         |  register save area   |
1753                                         |                       |
1754                                         +-----------------------+
1755                                         |    return address     |
1756                                         +-----------------------+
1757                                         |                       |
1758                                         |  local variables      |
1759                                         |                       |
1760                                         +-----------------------+
1761                                         |                       |
1762                                         |  alloca allocations   |
1763                                         |                       |
1764                                         +-----------------------+
1765                                         |                       |
1766    low                                  |  arguments on stack   |
1767    memory                               |                       |
1768                                   SP+0->+-----------------------+
1769
1770 Notes:
1771 1) The "reg parm save area" does not exist for non variable argument fns.
1772 2) The "reg parm save area" can be eliminated completely if we saved regs
1773    containing anonymous args separately but that complicates things too
1774    much (so it's not done).
1775 3) The return address is saved after the register save area so as to have as
1776    many insns as possible between the restoration of `lr' and the `jmp lr'.
1777 */
1778
1779 /* Structure to be filled in by m32r_compute_frame_size with register
1780    save masks, and offsets for the current function.  */
1781 struct m32r_frame_info
1782 {
1783   unsigned int total_size;      /* # bytes that the entire frame takes up */
1784   unsigned int extra_size;      /* # bytes of extra stuff */
1785   unsigned int pretend_size;    /* # bytes we push and pretend caller did */
1786   unsigned int args_size;       /* # bytes that outgoing arguments take up */
1787   unsigned int reg_size;        /* # bytes needed to store regs */
1788   unsigned int var_size;        /* # bytes that variables take up */
1789   unsigned int gmask;           /* mask of saved gp registers */
1790   unsigned int save_fp;         /* nonzero if fp must be saved */
1791   unsigned int save_lr;         /* nonzero if lr (return addr) must be saved */
1792   int          initialized;     /* nonzero if frame size already calculated */
1793 };
1794
1795 /* Current frame information calculated by m32r_compute_frame_size.  */
1796 static struct m32r_frame_info current_frame_info;
1797
1798 /* Zero structure to initialize current_frame_info.  */
1799 static struct m32r_frame_info zero_frame_info;
1800
1801 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1802 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1803
1804 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1805    The return address and frame pointer are treated separately.
1806    Don't consider them here.  */
1807 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1808 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1809  && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1810
1811 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1812 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
1813
1814 #define SHORT_INSN_SIZE 2       /* size of small instructions */
1815 #define LONG_INSN_SIZE 4        /* size of long instructions */
1816
1817 /* Return the bytes needed to compute the frame pointer from the current
1818    stack pointer.
1819
1820    SIZE is the size needed for local variables.  */
1821
1822 unsigned int
1823 m32r_compute_frame_size (size)
1824      int size;                  /* # of var. bytes allocated.  */
1825 {
1826   int regno;
1827   unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1828   unsigned int reg_size, frame_size;
1829   unsigned int gmask;
1830   enum m32r_function_type fn_type;
1831   int interrupt_p;
1832
1833   var_size      = M32R_STACK_ALIGN (size);
1834   args_size     = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1835   pretend_size  = current_function_pretend_args_size;
1836   extra_size    = FIRST_PARM_OFFSET (0);
1837   total_size    = extra_size + pretend_size + args_size + var_size;
1838   reg_size      = 0;
1839   gmask         = 0;
1840
1841   /* See if this is an interrupt handler.  Call used registers must be saved
1842      for them too.  */
1843   fn_type = m32r_compute_function_type (current_function_decl);
1844   interrupt_p = M32R_INTERRUPT_P (fn_type);
1845
1846   /* Calculate space needed for registers.  */
1847
1848   for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1849     {
1850       if (MUST_SAVE_REGISTER (regno, interrupt_p))
1851         {
1852           reg_size += UNITS_PER_WORD;
1853           gmask |= 1 << regno;
1854         }
1855     }
1856
1857   current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1858   current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1859
1860   reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1861                * UNITS_PER_WORD);
1862   total_size += reg_size;
1863
1864   /* ??? Not sure this is necessary, and I don't think the epilogue
1865      handler will do the right thing if this changes total_size.  */
1866   total_size = M32R_STACK_ALIGN (total_size);
1867
1868   frame_size = total_size - (pretend_size + reg_size);
1869
1870   /* Save computed information.  */
1871   current_frame_info.total_size   = total_size;
1872   current_frame_info.extra_size   = extra_size;
1873   current_frame_info.pretend_size = pretend_size;
1874   current_frame_info.var_size     = var_size;
1875   current_frame_info.args_size    = args_size;
1876   current_frame_info.reg_size     = reg_size;
1877   current_frame_info.gmask        = gmask;
1878   current_frame_info.initialized  = reload_completed;
1879
1880   /* Ok, we're done.  */
1881   return total_size;
1882 }
1883 \f
1884 /* When the `length' insn attribute is used, this macro specifies the
1885    value to be assigned to the address of the first insn in a
1886    function.  If not specified, 0 is used.  */
1887
1888 int
1889 m32r_first_insn_address ()
1890 {
1891   if (! current_frame_info.initialized)
1892     m32r_compute_frame_size (get_frame_size ());
1893
1894   return 0;
1895 }
1896 \f
1897 /* Expand the m32r prologue as a series of insns.  */
1898
1899 void
1900 m32r_expand_prologue ()
1901 {
1902   int regno;
1903   int frame_size;
1904   unsigned int gmask;
1905
1906   if (! current_frame_info.initialized)
1907     m32r_compute_frame_size (get_frame_size ());
1908
1909   gmask = current_frame_info.gmask;
1910
1911   /* These cases shouldn't happen.  Catch them now.  */
1912   if (current_frame_info.total_size == 0 && gmask)
1913     abort ();
1914
1915   /* Allocate space for register arguments if this is a variadic function.  */
1916   if (current_frame_info.pretend_size != 0)
1917     {
1918       /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1919          the wrong result on a 64-bit host.  */
1920       HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1921       emit_insn (gen_addsi3 (stack_pointer_rtx,
1922                              stack_pointer_rtx,
1923                              GEN_INT (-pretend_size)));
1924     }
1925
1926   /* Save any registers we need to and set up fp.  */
1927
1928   if (current_frame_info.save_fp)
1929     emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1930
1931   gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1932
1933   /* Save any needed call-saved regs (and call-used if this is an
1934      interrupt handler).  */
1935   for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1936     {
1937       if ((gmask & (1 << regno)) != 0)
1938         emit_insn (gen_movsi_push (stack_pointer_rtx,
1939                                    gen_rtx_REG (Pmode, regno)));
1940     }
1941
1942   if (current_frame_info.save_lr)
1943     emit_insn (gen_movsi_push (stack_pointer_rtx,
1944                                gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1945
1946   /* Allocate the stack frame.  */
1947   frame_size = (current_frame_info.total_size
1948                 - (current_frame_info.pretend_size
1949                    + current_frame_info.reg_size));
1950
1951   if (frame_size == 0)
1952     ; /* nothing to do */
1953   else if (frame_size <= 32768)
1954     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1955                            GEN_INT (-frame_size)));
1956   else
1957     {
1958       rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1959       emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1960       emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1961     }
1962
1963   if (frame_pointer_needed)
1964     emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1965
1966   if (profile_flag || profile_block_flag)
1967     emit_insn (gen_blockage ());
1968 }
1969
1970 \f
1971 /* Set up the stack and frame pointer (if desired) for the function.
1972    Note, if this is changed, you need to mirror the changes in
1973    m32r_compute_frame_size which calculates the prolog size.  */
1974
1975 void
1976 m32r_output_function_prologue (file, size)
1977      FILE * file;
1978      int    size;
1979 {
1980   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1981
1982   /* If this is an interrupt handler, mark it as such.  */
1983   if (M32R_INTERRUPT_P (fn_type))
1984     {
1985       fprintf (file, "\t%s interrupt handler\n",
1986                ASM_COMMENT_START);
1987     }
1988
1989   if (! current_frame_info.initialized)
1990     m32r_compute_frame_size (size);
1991
1992   /* This is only for the human reader.  */
1993   fprintf (file,
1994            "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1995            ASM_COMMENT_START,
1996            current_frame_info.var_size,
1997            current_frame_info.reg_size / 4,
1998            current_frame_info.args_size,
1999            current_frame_info.extra_size);
2000 }
2001 \f
2002 /* Do any necessary cleanup after a function to restore stack, frame,
2003    and regs. */
2004
2005 void
2006 m32r_output_function_epilogue (file, size)
2007      FILE * file;
2008      int    size ATTRIBUTE_UNUSED;
2009 {
2010   int regno;
2011   int noepilogue = FALSE;
2012   int total_size;
2013   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2014
2015   /* This is only for the human reader.  */
2016   fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2017
2018   if (!current_frame_info.initialized)
2019     abort ();
2020   total_size = current_frame_info.total_size;
2021
2022   if (total_size == 0)
2023     {
2024       rtx insn = get_last_insn ();
2025
2026       /* If the last insn was a BARRIER, we don't have to write any code
2027          because a jump (aka return) was put there.  */
2028       if (GET_CODE (insn) == NOTE)
2029         insn = prev_nonnote_insn (insn);
2030       if (insn && GET_CODE (insn) == BARRIER)
2031         noepilogue = TRUE;
2032     }
2033
2034   if (!noepilogue)
2035     {
2036       unsigned int var_size = current_frame_info.var_size;
2037       unsigned int args_size = current_frame_info.args_size;
2038       unsigned int gmask = current_frame_info.gmask;
2039       int can_trust_sp_p = !current_function_calls_alloca;
2040       const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2041       const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2042
2043       /* The first thing to do is point the sp at the bottom of the register
2044          save area.  */
2045       if (can_trust_sp_p)
2046         {
2047           unsigned int reg_offset = var_size + args_size;
2048           if (reg_offset == 0)
2049             ; /* nothing to do */
2050           else if (reg_offset < 128)
2051             fprintf (file, "\taddi %s,%s%d\n",
2052                      sp_str, IMMEDIATE_PREFIX, reg_offset);
2053           else if (reg_offset < 32768)
2054             fprintf (file, "\tadd3 %s,%s,%s%d\n",
2055                      sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2056           else
2057             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2058                      reg_names[PROLOGUE_TMP_REGNUM],
2059                      IMMEDIATE_PREFIX, reg_offset,
2060                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2061         }
2062       else if (frame_pointer_needed)
2063         {
2064           unsigned int reg_offset = var_size + args_size;
2065           if (reg_offset == 0)
2066             fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2067           else if (reg_offset < 32768)
2068             fprintf (file, "\tadd3 %s,%s,%s%d\n",
2069                      sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2070           else
2071             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2072                      reg_names[PROLOGUE_TMP_REGNUM],
2073                      IMMEDIATE_PREFIX, reg_offset,
2074                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2075         }
2076       else
2077         abort ();
2078
2079       if (current_frame_info.save_lr)
2080         fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2081
2082       /* Restore any saved registers, in reverse order of course.  */
2083       gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2084       for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2085         {
2086           if ((gmask & (1L << regno)) != 0)
2087             fprintf (file, "\tpop %s\n", reg_names[regno]);
2088         }
2089
2090       if (current_frame_info.save_fp)
2091         fprintf (file, "\tpop %s\n", fp_str);
2092
2093       /* Remove varargs area if present.  */
2094       if (current_frame_info.pretend_size != 0)
2095         fprintf (file, "\taddi %s,%s%d\n",
2096                  sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2097
2098       /* Emit the return instruction.  */
2099       if (M32R_INTERRUPT_P (fn_type))
2100         fprintf (file, "\trte\n");
2101       else
2102         fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2103     }
2104
2105 #if 0 /* no longer needed */
2106   /* Ensure the function cleanly ends on a 32 bit boundary.  */
2107   fprintf (file, "\t.fillinsn\n");
2108 #endif
2109
2110   /* Reset state info for each function.  */
2111   current_frame_info = zero_frame_info;
2112   m32r_compute_function_type (NULL_TREE);
2113 }
2114 \f
2115 /* Return non-zero if this function is known to have a null or 1 instruction
2116    epilogue.  */
2117
2118 int
2119 direct_return ()
2120 {
2121   if (!reload_completed)
2122     return FALSE;
2123
2124   if (! current_frame_info.initialized)
2125     m32r_compute_frame_size (get_frame_size ());
2126
2127   return current_frame_info.total_size == 0;
2128 }
2129
2130 \f
2131 /* PIC */
2132
2133 /* Emit special PIC prologues and epilogues.  */
2134
2135 void
2136 m32r_finalize_pic ()
2137 {
2138   /* nothing to do */
2139 }
2140 \f
2141 /* Nested function support.  */
2142
2143 /* Emit RTL insns to initialize the variable parts of a trampoline.
2144    FNADDR is an RTX for the address of the function's pure code.
2145    CXT is an RTX for the static chain value for the function.  */
2146
2147 void
2148 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2149      rtx tramp ATTRIBUTE_UNUSED;
2150      rtx fnaddr ATTRIBUTE_UNUSED;
2151      rtx cxt ATTRIBUTE_UNUSED;
2152 {
2153 }
2154 \f
2155 /* Set the cpu type and print out other fancy things,
2156    at the top of the file.  */
2157
2158 void
2159 m32r_asm_file_start (file)
2160      FILE * file;
2161 {
2162   if (flag_verbose_asm)
2163     fprintf (file, "%s M32R/D special options: -G %d\n",
2164              ASM_COMMENT_START, g_switch_value);
2165 }
2166 \f
2167 /* Print operand X (an rtx) in assembler syntax to file FILE.
2168    CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2169    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
2170
2171 void
2172 m32r_print_operand (file, x, code)
2173      FILE * file;
2174      rtx    x;
2175      int    code;
2176 {
2177   rtx addr;
2178
2179   switch (code)
2180     {
2181       /* The 's' and 'p' codes are used by output_block_move() to
2182          indicate post-increment 's'tores and 'p're-increment loads.  */
2183     case 's':
2184       if (GET_CODE (x) == REG)
2185         fprintf (file, "@+%s", reg_names [REGNO (x)]);
2186       else
2187         output_operand_lossage ("invalid operand to %s code");
2188       return;
2189
2190     case 'p':
2191       if (GET_CODE (x) == REG)
2192         fprintf (file, "@%s+", reg_names [REGNO (x)]);
2193       else
2194         output_operand_lossage ("invalid operand to %p code");
2195       return;
2196
2197     case 'R' :
2198       /* Write second word of DImode or DFmode reference,
2199          register or memory.  */
2200       if (GET_CODE (x) == REG)
2201         fputs (reg_names[REGNO (x)+1], file);
2202       else if (GET_CODE (x) == MEM)
2203         {
2204           fprintf (file, "@(");
2205           /* Handle possible auto-increment.  Since it is pre-increment and
2206              we have already done it, we can just use an offset of four.  */
2207           /* ??? This is taken from rs6000.c I think.  I don't think it is
2208              currently necessary, but keep it around.  */
2209           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2210               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2211             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2212           else
2213             output_address (plus_constant (XEXP (x, 0), 4));
2214           fputc (')', file);
2215         }
2216       else
2217         output_operand_lossage ("invalid operand to %R code");
2218       return;
2219
2220     case 'H' : /* High word */
2221     case 'L' : /* Low word */
2222       if (GET_CODE (x) == REG)
2223         {
2224           /* L = least significant word, H = most significant word */
2225           if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2226             fputs (reg_names[REGNO (x)], file);
2227           else
2228             fputs (reg_names[REGNO (x)+1], file);
2229         }
2230       else if (GET_CODE (x) == CONST_INT
2231                || GET_CODE (x) == CONST_DOUBLE)
2232         {
2233           rtx first, second;
2234
2235           split_double (x, &first, &second);
2236           fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2237                    code == 'L' ? INTVAL (first) : INTVAL (second));
2238         }
2239       else
2240         output_operand_lossage ("invalid operand to %H/%L code");
2241       return;
2242
2243     case 'A' :
2244       {
2245         REAL_VALUE_TYPE d;
2246         char str[30];
2247
2248         if (GET_CODE (x) != CONST_DOUBLE
2249             || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2250           fatal_insn ("Bad insn for 'A'", x);
2251         REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2252         REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2253         fprintf (file, "%s", str);
2254         return;
2255       }
2256
2257     case 'B' : /* Bottom half */
2258     case 'T' : /* Top half */
2259       /* Output the argument to a `seth' insn (sets the Top half-word).
2260          For constants output arguments to a seth/or3 pair to set Top and
2261          Bottom halves.  For symbols output arguments to a seth/add3 pair to
2262          set Top and Bottom halves.  The difference exists because for
2263          constants seth/or3 is more readable but for symbols we need to use
2264          the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
2265       switch (GET_CODE (x))
2266         {
2267         case CONST_INT :
2268         case CONST_DOUBLE :
2269           {
2270             rtx first, second;
2271
2272             split_double (x, &first, &second);
2273             x = WORDS_BIG_ENDIAN ? second : first;
2274             fprintf (file,
2275 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2276                      "0x%x",
2277 #else
2278                      "0x%lx",
2279 #endif
2280                      (code == 'B'
2281                       ? INTVAL (x) & 0xffff
2282                       : (INTVAL (x) >> 16) & 0xffff));
2283           }
2284           return;
2285         case CONST :
2286         case SYMBOL_REF :
2287           if (code == 'B'
2288               && small_data_operand (x, VOIDmode))
2289             {
2290               fputs ("sda(", file);
2291               output_addr_const (file, x);
2292               fputc (')', file);
2293               return;
2294             }
2295           /* fall through */
2296         case LABEL_REF :
2297           fputs (code == 'T' ? "shigh(" : "low(", file);
2298           output_addr_const (file, x);
2299           fputc (')', file);
2300           return;
2301         default :
2302           output_operand_lossage ("invalid operand to %T/%B code");
2303           return;
2304         }
2305       break;
2306
2307     case 'U' :
2308       /* ??? wip */
2309       /* Output a load/store with update indicator if appropriate.  */
2310       if (GET_CODE (x) == MEM)
2311         {
2312           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2313               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2314             fputs (".a", file);
2315         }
2316       else
2317         output_operand_lossage ("invalid operand to %U code");
2318       return;
2319
2320     case 'N' :
2321       /* Print a constant value negated.  */
2322       if (GET_CODE (x) == CONST_INT)
2323         output_addr_const (file, GEN_INT (- INTVAL (x)));
2324       else
2325         output_operand_lossage ("invalid operand to %N code");
2326       return;
2327
2328     case 'X' :
2329       /* Print a const_int in hex.  Used in comments.  */
2330       if (GET_CODE (x) == CONST_INT)
2331         fprintf (file,
2332 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2333                  "0x%x",
2334 #else
2335                  "0x%lx",
2336 #endif
2337                  INTVAL (x));
2338       return;
2339
2340     case '#' :
2341       fputs (IMMEDIATE_PREFIX, file);
2342       return;
2343
2344 #if 0 /* ??? no longer used */
2345     case '@' :
2346       fputs (reg_names[SDA_REGNUM], file);
2347       return;
2348 #endif
2349
2350     case 0 :
2351       /* Do nothing special.  */
2352       break;
2353
2354     default :
2355       /* Unknown flag.  */
2356       output_operand_lossage ("invalid operand output code");
2357     }
2358
2359   switch (GET_CODE (x))
2360     {
2361     case REG :
2362       fputs (reg_names[REGNO (x)], file);
2363       break;
2364
2365     case MEM :
2366       addr = XEXP (x, 0);
2367       if (GET_CODE (addr) == PRE_INC)
2368         {
2369           if (GET_CODE (XEXP (addr, 0)) != REG)
2370             fatal_insn ("Pre-increment address is not a register", x);
2371
2372           fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2373         }
2374       else if (GET_CODE (addr) == PRE_DEC)
2375         {
2376           if (GET_CODE (XEXP (addr, 0)) != REG)
2377             fatal_insn ("Pre-decrement address is not a register", x);
2378
2379           fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2380         }
2381       else if (GET_CODE (addr) == POST_INC)
2382         {
2383           if (GET_CODE (XEXP (addr, 0)) != REG)
2384             fatal_insn ("Post-increment address is not a register", x);
2385
2386           fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2387         }
2388       else
2389         {
2390           fputs ("@(", file);
2391           output_address (XEXP (x, 0));
2392           fputc (')', file);
2393         }
2394       break;
2395
2396     case CONST_DOUBLE :
2397       /* We handle SFmode constants here as output_addr_const doesn't.  */
2398       if (GET_MODE (x) == SFmode)
2399         {
2400           REAL_VALUE_TYPE d;
2401           long l;
2402
2403           REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2404           REAL_VALUE_TO_TARGET_SINGLE (d, l);
2405           fprintf (file, "0x%08lx", l);
2406           break;
2407         }
2408
2409       /* Fall through.  Let output_addr_const deal with it.  */
2410
2411     default :
2412       output_addr_const (file, x);
2413       break;
2414     }
2415 }
2416
2417 /* Print a memory address as an operand to reference that memory location.  */
2418
2419 void
2420 m32r_print_operand_address (file, addr)
2421      FILE * file;
2422      rtx    addr;
2423 {
2424   register rtx base;
2425   register rtx index = 0;
2426   int          offset = 0;
2427
2428   switch (GET_CODE (addr))
2429     {
2430     case REG :
2431       fputs (reg_names[REGNO (addr)], file);
2432       break;
2433
2434     case PLUS :
2435       if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2436         offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2437       else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2438         offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2439       else
2440         base = XEXP (addr, 0), index = XEXP (addr, 1);
2441       if (GET_CODE (base) == REG)
2442         {
2443           /* Print the offset first (if present) to conform to the manual.  */
2444           if (index == 0)
2445             {
2446               if (offset != 0)
2447                 fprintf (file, "%d,", offset);
2448               fputs (reg_names[REGNO (base)], file);
2449             }
2450           /* The chip doesn't support this, but left in for generality.  */
2451           else if (GET_CODE (index) == REG)
2452             fprintf (file, "%s,%s",
2453                      reg_names[REGNO (base)], reg_names[REGNO (index)]);
2454           /* Not sure this can happen, but leave in for now.  */
2455           else if (GET_CODE (index) == SYMBOL_REF)
2456             {
2457               output_addr_const (file, index);
2458               fputc (',', file);
2459               fputs (reg_names[REGNO (base)], file);
2460             }
2461           else
2462             fatal_insn ("Bad address", addr);
2463         }
2464       else if (GET_CODE (base) == LO_SUM)
2465         {
2466           if (index != 0
2467               || GET_CODE (XEXP (base, 0)) != REG)
2468             abort ();
2469           if (small_data_operand (XEXP (base, 1), VOIDmode))
2470             fputs ("sda(", file);
2471           else
2472             fputs ("low(", file);
2473           output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2474           fputs ("),", file);
2475           fputs (reg_names[REGNO (XEXP (base, 0))], file);
2476         }
2477       else
2478         fatal_insn ("Bad address", addr);
2479       break;
2480
2481     case LO_SUM :
2482       if (GET_CODE (XEXP (addr, 0)) != REG)
2483         fatal_insn ("Lo_sum not of register", addr);
2484       if (small_data_operand (XEXP (addr, 1), VOIDmode))
2485         fputs ("sda(", file);
2486       else
2487         fputs ("low(", file);
2488       output_addr_const (file, XEXP (addr, 1));
2489       fputs ("),", file);
2490       fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2491       break;
2492
2493     case PRE_INC :      /* Assume SImode */
2494       fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2495       break;
2496
2497     case PRE_DEC :      /* Assume SImode */
2498       fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2499       break;
2500
2501     case POST_INC :     /* Assume SImode */
2502       fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2503       break;
2504
2505     default :
2506       output_addr_const (file, addr);
2507       break;
2508     }
2509 }
2510
2511 /* Return true if the operands are the constants 0 and 1.  */
2512 int
2513 zero_and_one (operand1, operand2)
2514      rtx operand1;
2515      rtx operand2;
2516 {
2517   return
2518        GET_CODE (operand1) == CONST_INT
2519     && GET_CODE (operand2) == CONST_INT
2520     && (  ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2521         ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2522 }
2523
2524 /* Return non-zero if the operand is suitable for use in a conditional move sequence.  */
2525 int
2526 conditional_move_operand (operand, mode)
2527      rtx operand;
2528      enum machine_mode mode;
2529 {
2530   /* Only defined for simple integers so far... */
2531   if (mode != SImode && mode != HImode && mode != QImode)
2532     return FALSE;
2533
2534   /* At the moment we can hanndle moving registers and loading constants.  */
2535   /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
2536
2537   switch (GET_CODE (operand))
2538     {
2539     case REG:
2540       return 1;
2541
2542     case CONST_INT:
2543       return INT8_P (INTVAL (operand));
2544
2545     default:
2546 #if 0
2547       fprintf (stderr, "Test for cond move op of type: %s\n",
2548                GET_RTX_NAME (GET_CODE (operand)));
2549 #endif
2550       return 0;
2551     }
2552 }
2553
2554 /* Return true if the code is a test of the carry bit */
2555 int
2556 carry_compare_operand (op, mode)
2557      rtx op;
2558      enum machine_mode mode ATTRIBUTE_UNUSED;
2559 {
2560   rtx x;
2561
2562   if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2563     return FALSE;
2564
2565   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2566     return FALSE;
2567
2568   x = XEXP (op, 0);
2569   if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2570     return FALSE;
2571
2572   x = XEXP (op, 1);
2573   if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2574     return FALSE;
2575
2576   return TRUE;
2577 }
2578
2579 /* Generate the correct assembler code to handle the conditional loading of a
2580    value into a register.  It is known that the operands satisfy the
2581    conditional_move_operand() function above.  The destination is operand[0].
2582    The condition is operand [1].  The 'true' value is operand [2] and the
2583    'false' value is operand [3].  */
2584 char *
2585 emit_cond_move (operands, insn)
2586      rtx * operands;
2587      rtx   insn ATTRIBUTE_UNUSED;
2588 {
2589   static char buffer [100];
2590   const char * dest = reg_names [REGNO (operands [0])];
2591
2592   buffer [0] = 0;
2593
2594   /* Destination must be a register.  */
2595   if (GET_CODE (operands [0]) != REG)
2596     abort();
2597   if (! conditional_move_operand (operands [2], SImode))
2598     abort();
2599   if (! conditional_move_operand (operands [3], SImode))
2600     abort();
2601
2602   /* Check to see if the test is reversed.  */
2603   if (GET_CODE (operands [1]) == NE)
2604     {
2605       rtx tmp = operands [2];
2606       operands [2] = operands [3];
2607       operands [3] = tmp;
2608     }
2609
2610   sprintf (buffer, "mvfc %s, cbr", dest);
2611
2612   /* If the true value was '0' then we need to invert the results of the move.  */
2613   if (INTVAL (operands [2]) == 0)
2614     sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2615              dest, dest);
2616
2617   return buffer;
2618 }
2619
2620 /* Returns true if the registers contained in the two
2621    rtl expressions are different. */
2622 int
2623 m32r_not_same_reg (a, b)
2624      rtx a;
2625      rtx b;
2626 {
2627   int reg_a = -1;
2628   int reg_b = -2;
2629
2630   while (GET_CODE (a) == SUBREG)
2631     a = SUBREG_REG (a);
2632
2633   if (GET_CODE (a) == REG)
2634     reg_a = REGNO (a);
2635
2636   while (GET_CODE (b) == SUBREG)
2637     b = SUBREG_REG (b);
2638
2639   if (GET_CODE (b) == REG)
2640     reg_b = REGNO (b);
2641
2642   return reg_a != reg_b;
2643 }
2644
2645 \f
2646 /* Use a library function to move some bytes.  */
2647 static void
2648 block_move_call (dest_reg, src_reg, bytes_rtx)
2649      rtx dest_reg;
2650      rtx src_reg;
2651      rtx bytes_rtx;
2652 {
2653   /* We want to pass the size as Pmode, which will normally be SImode
2654      but will be DImode if we are using 64 bit longs and pointers.  */
2655   if (GET_MODE (bytes_rtx) != VOIDmode
2656       && GET_MODE (bytes_rtx) != Pmode)
2657     bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2658
2659 #ifdef TARGET_MEM_FUNCTIONS
2660   emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2661                      VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2662                      convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2663                                       TREE_UNSIGNED (sizetype)),
2664                      TYPE_MODE (sizetype));
2665 #else
2666   emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2667                      VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2668                      convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2669                                       TREE_UNSIGNED (integer_type_node)),
2670                      TYPE_MODE (integer_type_node));
2671 #endif
2672 }
2673
2674 /* The maximum number of bytes to copy using pairs of load/store instructions.
2675    If a block is larger than this then a loop will be generated to copy
2676    MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitary choice.
2677    A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2678    string copy in it.  */
2679 #define MAX_MOVE_BYTES 32
2680
2681 /* Expand string/block move operations.
2682
2683    operands[0] is the pointer to the destination.
2684    operands[1] is the pointer to the source.
2685    operands[2] is the number of bytes to move.
2686    operands[3] is the alignment.  */
2687
2688 void
2689 m32r_expand_block_move (operands)
2690      rtx operands[];
2691 {
2692   rtx           orig_dst  = operands[0];
2693   rtx           orig_src  = operands[1];
2694   rtx           bytes_rtx = operands[2];
2695   rtx           align_rtx = operands[3];
2696   int           constp    = GET_CODE (bytes_rtx) == CONST_INT;
2697   HOST_WIDE_INT bytes     = constp ? INTVAL (bytes_rtx) : 0;
2698   int           align     = INTVAL (align_rtx);
2699   int           leftover;
2700   rtx           src_reg;
2701   rtx           dst_reg;
2702
2703   if (constp && bytes <= 0)
2704     return;
2705
2706   /* Move the address into scratch registers.  */
2707   dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2708   src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2709
2710   if (align > UNITS_PER_WORD)
2711     align = UNITS_PER_WORD;
2712
2713   /* If we prefer size over speed, always use a function call.
2714      If we do not know the size, use a function call.
2715      If the blocks are not word aligned, use a function call.  */
2716   if (optimize_size || ! constp || align != UNITS_PER_WORD)
2717     {
2718       block_move_call (dst_reg, src_reg, bytes_rtx);
2719       return;
2720     }
2721
2722   leftover = bytes % MAX_MOVE_BYTES;
2723   bytes   -= leftover;
2724
2725   /* If necessary, generate a loop to handle the bulk of the copy.  */
2726   if (bytes)
2727     {
2728       rtx label;
2729       rtx final_src;
2730       rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2731       rtx rounded_total = GEN_INT (bytes);
2732
2733       /* If we are going to have to perform this loop more than
2734          once, then generate a label and compute the address the
2735          source register will contain upon completion of the final
2736          itteration.  */
2737       if (bytes > MAX_MOVE_BYTES)
2738         {
2739           final_src = gen_reg_rtx (Pmode);
2740
2741           if (INT16_P(bytes))
2742             emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2743           else
2744             {
2745               emit_insn (gen_movsi (final_src, rounded_total));
2746               emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2747             }
2748
2749           label = gen_label_rtx ();
2750           emit_label (label);
2751         }
2752
2753       /* It is known that output_block_move() will update src_reg to point
2754          to the word after the end of the source block, and dst_reg to point
2755          to the last word of the destination block, provided that the block
2756          is MAX_MOVE_BYTES long.  */
2757       emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2758       emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2759
2760       if (bytes > MAX_MOVE_BYTES)
2761         {
2762           emit_insn (gen_cmpsi (src_reg, final_src));
2763           emit_jump_insn (gen_bne (label));
2764         }
2765     }
2766
2767   if (leftover)
2768     emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2769 }
2770
2771 \f
2772 /* Emit load/stores for a small constant word aligned block_move.
2773
2774    operands[0] is the memory address of the destination.
2775    operands[1] is the memory address of the source.
2776    operands[2] is the number of bytes to move.
2777    operands[3] is a temp register.
2778    operands[4] is a temp register.  */
2779
2780 char *
2781 m32r_output_block_move (insn, operands)
2782      rtx insn ATTRIBUTE_UNUSED;
2783      rtx operands[];
2784 {
2785   HOST_WIDE_INT bytes = INTVAL (operands[2]);
2786   int           first_time;
2787   int           got_extra = 0;
2788
2789   if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2790     abort ();
2791
2792   /* We do not have a post-increment store available, so the first set of
2793      stores are done without any increment, then the remaining ones can use
2794      the pre-increment addressing mode.
2795
2796      Note: expand_block_move() also relies upon this behaviour when building
2797      loops to copy large blocks.  */
2798   first_time = 1;
2799
2800   while (bytes > 0)
2801     {
2802       if (bytes >= 8)
2803         {
2804           if (first_time)
2805             {
2806               output_asm_insn ("ld\t%3, %p1", operands);
2807               output_asm_insn ("ld\t%4, %p1", operands);
2808               output_asm_insn ("st\t%3, @%0", operands);
2809               output_asm_insn ("st\t%4, %s0", operands);
2810             }
2811           else
2812             {
2813               output_asm_insn ("ld\t%3, %p1", operands);
2814               output_asm_insn ("ld\t%4, %p1", operands);
2815               output_asm_insn ("st\t%3, %s0", operands);
2816               output_asm_insn ("st\t%4, %s0", operands);
2817             }
2818
2819           bytes -= 8;
2820         }
2821       else if (bytes >= 4)
2822         {
2823           if (bytes > 4)
2824             got_extra = 1;
2825
2826           output_asm_insn ("ld\t%3, %p1", operands);
2827
2828           if (got_extra)
2829             output_asm_insn ("ld\t%4, %p1", operands);
2830
2831           if (first_time)
2832             output_asm_insn ("st\t%3, @%0", operands);
2833           else
2834             output_asm_insn ("st\t%3, %s0", operands);
2835
2836           bytes -= 4;
2837         }
2838       else
2839         {
2840           /* Get the entire next word, even though we do not want all of it.
2841              The saves us from doing several smaller loads, and we assume that
2842              we cannot cause a page fault when at least part of the word is in
2843              valid memory [since we don't get called if things aren't properly
2844              aligned].  */
2845           int dst_offset = first_time ? 0 : 4;
2846           int last_shift;
2847           rtx my_operands[3];
2848
2849           /* If got_extra is true then we have already loaded
2850              the next word as part of loading and storing the previous word.  */
2851           if (! got_extra)
2852             output_asm_insn ("ld\t%4, @%1", operands);
2853
2854           if (bytes >= 2)
2855             {
2856               bytes -= 2;
2857
2858               output_asm_insn ("sra3\t%3, %4, #16", operands);
2859               my_operands[0] = operands[3];
2860               my_operands[1] = GEN_INT (dst_offset);
2861               my_operands[2] = operands[0];
2862               output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2863
2864               /* If there is a byte left to store then increment the
2865                  destination address and shift the contents of the source
2866                  register down by 8 bits.  We could not do the address
2867                  increment in the store half word instruction, because it does
2868                  not have an auto increment mode.  */
2869               if (bytes > 0)  /* assert (bytes == 1) */
2870                 {
2871                   dst_offset += 2;
2872                   last_shift = 8;
2873                 }
2874             }
2875           else
2876             last_shift = 24;
2877
2878           if (bytes > 0)
2879             {
2880               my_operands[0] = operands[4];
2881               my_operands[1] = GEN_INT (last_shift);
2882               output_asm_insn ("srai\t%0, #%1", my_operands);
2883               my_operands[0] = operands[4];
2884               my_operands[1] = GEN_INT (dst_offset);
2885               my_operands[2] = operands[0];
2886               output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2887             }
2888
2889           bytes = 0;
2890         }
2891
2892       first_time = 0;
2893     }
2894
2895   return "";
2896 }
2897
2898 /* Return true if op is an integer constant, less than or equal to
2899    MAX_MOVE_BYTES.  */
2900 int
2901 m32r_block_immediate_operand (op, mode)
2902      rtx op;
2903      enum machine_mode mode ATTRIBUTE_UNUSED;
2904 {
2905   if (GET_CODE (op) != CONST_INT
2906       || INTVAL (op) > MAX_MOVE_BYTES
2907       || INTVAL (op) <= 0)
2908     return 0;
2909
2910   return 1;
2911 }