| blob | c5e5c4c2ccb3e10faad709b113b0f5cb7a482743 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 /* Vector mapping INSN_UIDs to luids.
58 The luids are like uids but increase monotonically always.
59 We use them to see whether a jump comes from outside a given loop. */
63 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
64 number the insn is contained in. */
68 /* 1 + largest uid of any insn. */
72 /* 1 + luid of last insn. */
76 /* Number of loops detected in current function. Used as index to the
77 next few tables. */
81 /* Indexed by register number, contains the number of times the reg
82 is set during the loop being scanned.
83 During code motion, a negative value indicates a reg that has been
84 made a candidate; in particular -2 means that it is an candidate that
85 we know is equal to a constant and -1 means that it is an candidate
86 not known equal to a constant.
87 After code motion, regs moved have 0 (which is accurate now)
88 while the failed candidates have the original number of times set.
90 Therefore, at all times, == 0 indicates an invariant register;
91 < 0 a conditionally invariant one. */
95 /* Original value of set_in_loop; same except that this value
96 is not set negative for a reg whose sets have been made candidates
97 and not set to 0 for a reg that is moved. */
101 /* Index by register number, 1 indicates that the register
102 cannot be moved or strength reduced. */
106 /* Contains the insn in which a register was used if it was used
107 exactly once; contains const0_rtx if it was used more than once. */
111 /* Nonzero means reg N has already been moved out of one loop.
112 This reduces the desire to move it out of another. */
116 /* List of MEMs that are stored in this loop. */
120 /* The insn where the first of these was found. */
129 /* Array of MEMs that are used (read or written) in this loop, but
130 cannot be aliased by anything in this loop, except perhaps
131 themselves. In other words, if loop_mems[i] is altered during the
132 loop, it is altered by an expression that is rtx_equal_p to it. */
136 /* The index of the next available slot in LOOP_MEMS. */
140 /* The number of elements allocated in LOOP_MEMs. */
144 /* Nonzero if we don't know what MEMs were changed in the current
145 loop. This happens if the loop contains a call (in which case
146 `loop_info->has_call' will also be set) or if we store into more
147 than NUM_STORES MEMs. */
151 /* The above doesn't count any readonly memory locations that are stored.
152 This does. */
156 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
159 /* Count of memory write instructions discovered in the loop. */
162 /* Bound on pseudo register number before loop optimization.
163 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
166 /* The value to pass to the next call of reg_scan_update. */
169 /* This obstack is used in product_cheap_p to allocate its rtl. It
170 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
171 If we used the same obstack that it did, we would be deallocating
172 that array. */
176 /* This is where the pointer to the obstack being used for RTL is stored. */
180 #define obstack_chunk_alloc xmalloc
181 #define obstack_chunk_free free
182 \f
183 /* During the analysis of a loop, a chain of `struct movable's
184 is made to record all the movable insns found.
185 Then the entire chain can be scanned to decide which to move. */
187 struct movable
188 {
193 of any registers used within the LIBCALL. */
195 that must be moved with this one. */
198 may be adjusted when matching movables
199 that load the same value are found. */
201 including other movables that force this
202 or match this one. */
206 /* If PARTIAL is 1, GLOBAL means something different:
207 that the reg is live outside the range from where it is set
208 to the following label. */
212 In particular, moving it does not make it
213 invariant. */
215 load SRC, rather than copying INSN. */
217 first insn of a consecutive sets group. */
220 that we should avoid changing when clearing
221 the rest of the reg. */
225 };
231 /* Forward declarations. */
250 #if 0
252 #endif
320 rtx r;
325 rtx r1;
326 rtx r2;
329 /* Nonzero iff INSN is between START and END, inclusive. */
330 #define INSN_IN_RANGE_P(INSN, START, END) \
331 (INSN_UID (INSN) < max_uid_for_loop \
332 && INSN_LUID (INSN) >= INSN_LUID (START) \
333 && INSN_LUID (INSN) <= INSN_LUID (END))
335 /* Indirect_jump_in_function is computed once per function. */
343 \f
344 /* Relative gain of eliminating various kinds of operations. */
346 #if 0
349 #endif
351 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
352 copy the value of the strength reduced giv to its original register. */
355 /* Cost of using a register, to normalize the benefits of a giv. */
358 void
360 {
368 /* We multiply by 2 to reconcile the difference in scale between
369 these two ways of computing costs. Otherwise the cost of a copy
370 will be far less than the cost of an add. */
374 /* Free the objects we just allocated. */
377 /* Initialize the obstack used for rtl in product_cheap_p. */
379 }
380 \f
381 /* Compute the mapping from uids to luids.
382 LUIDs are numbers assigned to insns, like uids,
383 except that luids increase monotonically through the code.
384 Start at insn START and stop just before END. Assign LUIDs
385 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
386 static int
390 {
392 rtx insn;
395 {
398 /* Don't assign luids to line-number NOTEs, so that the distance in
399 luids between two insns is not affected by -g. */
403 else
404 /* Give a line number note the same luid as preceding insn. */
406 }
408 }
409 \f
410 /* Entry point of this file. Perform loop optimization
411 on the current function. F is the first insn of the function
412 and DUMPFILE is a stream for output of a trace of actions taken
413 (or 0 if none should be output). */
415 void
417 /* f is the first instruction of a chain of insns for one function */
418 rtx f;
421 {
437 /* Count the number of loops. */
441 {
444 max_loop_num++;
445 }
447 /* Don't waste time if no loops. */
455 /* Get size to use for tables indexed by uids.
456 Leave some space for labels allocated by find_and_verify_loops. */
463 /* Allocate storage for array of loops. */
467 /* Find and process each loop.
468 First, find them, and record them in order of their beginnings. */
471 /* Allocate and initialize auxiliary loop information. */
476 /* Now find all register lifetimes. This must be done after
477 find_and_verify_loops, because it might reorder the insns in the
478 function. */
481 /* This must occur after reg_scan so that registers created by gcse
482 will have entries in the register tables.
484 We could have added a call to reg_scan after gcse_main in toplev.c,
485 but moving this call to init_alias_analysis is more efficient. */
488 /* See if we went too far. Note that get_max_uid already returns
489 one more that the maximum uid of all insn. */
492 /* Now reset it to the actual size we need. See above. */
495 /* find_and_verify_loops has already called compute_luids, but it
496 might have rearranged code afterwards, so we need to recompute
497 the luids now. */
500 /* Don't leave gaps in uid_luid for insns that have been
501 deleted. It is possible that the first or last insn
502 using some register has been deleted by cross-jumping.
503 Make sure that uid_luid for that former insn's uid
504 points to the general area where that insn used to be. */
506 {
510 }
515 /* Determine if the function has indirect jump. On some systems
516 this prevents low overhead loop instructions from being used. */
519 /* Now scan the loops, last ones first, since this means inner ones are done
520 before outer ones. */
522 {
527 }
529 /* If there were lexical blocks inside the loop, they have been
530 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
531 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
532 the BLOCKs as well. */
538 /* Clean up. */
544 }
545 \f
546 /* Returns the next insn, in execution order, after INSN. START and
547 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
548 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
549 insn-stream; it is used with loops that are entered near the
550 bottom. */
552 static rtx
555 rtx insn;
556 {
560 {
562 /* Go to the top of the loop, and continue there. */
564 else
565 /* We're done. */
567 }
570 /* We're done. */
574 }
576 /* Optimize one loop described by LOOP. */
578 /* ??? Could also move memory writes out of loops if the destination address
579 is invariant, the source is invariant, the memory write is not volatile,
580 and if we can prove that no read inside the loop can read this address
581 before the write occurs. If there is a read of this address after the
582 write, then we can also mark the memory read as invariant. */
584 static void
588 {
592 /* Additional information about the current loop being processed
593 that is used to compute the number of loop iterations for loop
594 unrolling and doloop optimization. */
596 rtx p;
597 /* 1 if we are scanning insns that could be executed zero times. */
599 /* 1 if we are scanning insns that might never be executed
600 due to a subroutine call which might exit before they are reached. */
602 /* Jump insn that enters the loop, or 0 if control drops in. */
604 /* Number of insns in the loop. */
608 /* The SET from an insn, if it is the only SET in the insn. */
610 /* Chain describing insns movable in current loop. */
612 /* Last element in `movables' -- so we can add elements at the end. */
614 /* Ratio of extra register life span we can justify
615 for saving an instruction. More if loop doesn't call subroutines
616 since in that case saving an insn makes more difference
617 and more registers are available. */
619 /* Nonzero if we are scanning instructions in a sub-loop. */
625 /* Determine whether this loop starts with a jump down to a test at
626 the end. This will occur for a small number of loops with a test
627 that is too complex to duplicate in front of the loop.
629 We search for the first insn or label in the loop, skipping NOTEs.
630 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
631 (because we might have a loop executed only once that contains a
632 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
633 (in case we have a degenerate loop).
635 Note that if we mistakenly think that a loop is entered at the top
636 when, in fact, it is entered at the exit test, the only effect will be
637 slightly poorer optimization. Making the opposite error can generate
638 incorrect code. Since very few loops now start with a jump to the
639 exit test, the code here to detect that case is very conservative. */
642 p != loop_end
648 ;
652 /* Set up variables describing this loop. */
656 /* If loop has a jump before the first label,
657 the true entry is the target of that jump.
658 Start scan from there.
659 But record in LOOP->TOP the place where the end-test jumps
660 back to so we can scan that after the end of the loop. */
662 {
665 /* Loop entry must be unconditional jump (and not a RETURN) */
668 /* Check to see whether the jump actually
669 jumps out of the loop (meaning it's no loop).
670 This case can happen for things like
671 do {..} while (0). If this label was generated previously
672 by loop, we can't tell anything about it and have to reject
673 the loop. */
675 {
678 }
679 }
681 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
682 as required by loop_reg_used_before_p. So skip such loops. (This
683 test may never be true, but it's best to play it safe.)
685 Also, skip loops where we do not start scanning at a label. This
686 test also rejects loops starting with a JUMP_INSN that failed the
687 test above. */
691 {
696 }
698 /* Count number of times each reg is set during this loop.
699 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
700 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
702 /* Allocate extra space for REGS that might be created by
703 load_mems. We allocate a little extra slop as well, in the hopes
704 that even after the moving of movables creates some new registers
705 we won't have to reallocate these arrays. However, we do grow
706 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
717 {
720 }
722 #ifdef AVOID_CCMODE_COPIES
723 /* Don't try to move insns which set CC registers if we should not
724 create CCmode register copies. */
728 #endif
734 {
740 }
742 /* Scan through the loop finding insns that are safe to move.
743 Set set_in_loop negative for the reg being set, so that
744 this reg will be considered invariant for subsequent insns.
745 We consider whether subsequent insns use the reg
746 in deciding whether it is worth actually moving.
748 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
749 and therefore it is possible that the insns we are scanning
750 would never be executed. At such times, we must make sure
751 that it is safe to execute the insn once instead of zero times.
752 When MAYBE_NEVER is 0, all insns will be executed at least once
753 so that is not a problem. */
758 {
763 {
770 /* Figure out what to use as a source of this insn. If a REG_EQUIV
771 note is given or if a REG_EQUAL note with a constant operand is
772 specified, use it as the source and mark that we should move
773 this insn by calling emit_move_insn rather that duplicating the
774 insn.
776 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
777 is present. */
781 else
782 {
787 {
789 /* A libcall block can use regs that don't appear in
790 the equivalent expression. To move the libcall,
791 we must move those regs too. */
793 }
794 }
796 /* Don't try to optimize a register that was made
797 by loop-optimization for an inner loop.
798 We don't know its life-span, so we can't compute the benefit. */
800 ;
802 than the one where it is set (meaning that
803 something after this point in the loop might
804 depend on its value before the set). */
806 /* And the set is not guaranteed to be executed one
807 the loop starts, or the value before the set is
808 needed before the set occurs...
810 ??? Note we have quadratic behaviour here, mitigated
811 by the fact that the previous test will often fail for
812 large loops. Rather than re-scanning the entire loop
813 each time for register usage, we should build tables
814 of the register usage and use them here instead. */
815 && (maybe_never
817 /* It is unsafe to move the set.
819 This code used to consider it OK to move a set of a variable
820 which was not created by the user and not used in an exit test.
821 That behavior is incorrect and was removed. */
822 ;
828 || (tem1
829 = consec_sets_invariant_p
832 p)))
833 /* If the insn can cause a trap (such as divide by zero),
834 can't move it unless it's guaranteed to be executed
835 once loop is entered. Even a function call might
836 prevent the trap insn from being reached
837 (since it might exit!) */
840 {
844 /* A potential lossage is where we have a case where two insns
845 can be combined as long as they are both in the loop, but
846 we move one of them outside the loop. For large loops,
847 this can lose. The most common case of this is the address
848 of a function being called.
850 Therefore, if this register is marked as being used exactly
851 once if we are in a loop with calls (a "large loop"), see if
852 we can replace the usage of this register with the source
853 of this SET. If we can, delete this insn.
855 Don't do this if P has a REG_RETVAL note or if we have
856 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
867 && (! SMALL_REGISTER_CLASSES
870 /* This test is not redundant; SET_SRC (set) might be
871 a call-clobbered register and the life of REGNO
872 might span a call. */
874 VARRAY_RTX
878 VARRAY_RTX
880 {
881 /* Replace any usage in a REG_EQUAL note. Must copy the
882 new source, so that we don't get rtx sharing between the
883 SET_SOURCE and REG_NOTES of insn p. */
894 }
913 /* Set M->cond if either loop_invariant_p
914 or consec_sets_invariant_p returned 2
915 (only conditionally invariant). */
927 /* Add M to the end of the chain MOVABLES. */
930 else
935 {
936 /* It is possible for the first instruction to have a
937 REG_EQUAL note but a non-invariant SET_SRC, so we must
938 remember the status of the first instruction in case
939 the last instruction doesn't have a REG_EQUAL note. */
942 /* Skip this insn, not checking REG_LIBCALL notes. */
944 /* Skip the consecutive insns, if there are any. */
946 /* Back up to the last insn of the consecutive group. */
949 /* We must now reset m->move_insn, m->is_equiv, and possibly
950 m->set_src to correspond to the effects of all the
951 insns. */
955 else
956 {
960 else
963 }
965 }
966 }
967 /* If this register is always set within a STRICT_LOW_PART
968 or set to zero, then its high bytes are constant.
969 So clear them outside the loop and within the loop
970 just load the low bytes.
971 We must check that the machine has an instruction to do so.
972 Also, if the value loaded into the register
973 depends on the same register, this cannot be done. */
983 {
986 {
1000 /* If the insn may not be executed on some cycles,
1001 we can't clear the whole reg; clear just high part.
1002 Not even if the reg is used only within this loop.
1003 Consider this:
1004 while (1)
1005 while (s != t) {
1006 if (foo ()) x = *s;
1007 use (x);
1008 }
1009 Clearing x before the inner loop could clobber a value
1010 being saved from the last time around the outer loop.
1011 However, if the reg is not used outside this loop
1012 and all uses of the register are in the same
1013 basic block as the store, there is no problem.
1015 If this insn was made by loop, we don't know its
1016 INSN_LUID and hence must make a conservative
1017 assumption. */
1023 || (labels_in_range_p
1027 else
1036 /* Add M to the end of the chain MOVABLES. */
1039 else
1042 }
1043 }
1044 }
1045 /* Past a call insn, we get to insns which might not be executed
1046 because the call might exit. This matters for insns that trap.
1047 Constant and pure call insns always return, so they don't count. */
1050 /* Past a label or a jump, we get to insns for which we
1051 can't count on whether or how many times they will be
1052 executed during each iteration. Therefore, we can
1053 only move out sets of trivial variables
1054 (those not used after the loop). */
1055 /* Similar code appears twice in strength_reduce. */
1057 /* If we enter the loop in the middle, and scan around to the
1058 beginning, don't set maybe_never for that. This must be an
1059 unconditional jump, otherwise the code at the top of the
1060 loop might never be executed. Unconditional jumps are
1061 followed a by barrier then loop end. */
1067 {
1068 /* At the virtual top of a converted loop, insns are again known to
1069 be executed: logically, the loop begins here even though the exit
1070 code has been duplicated. */
1074 loop_depth++;
1076 loop_depth--;
1077 }
1078 }
1080 /* If one movable subsumes another, ignore that other. */
1084 /* For each movable insn, see if the reg that it loads
1085 leads when it dies right into another conditionally movable insn.
1086 If so, record that the second insn "forces" the first one,
1087 since the second can be moved only if the first is. */
1091 /* See if there are multiple movable insns that load the same value.
1092 If there are, make all but the first point at the first one
1093 through the `match' field, and add the priorities of them
1094 all together as the priority of the first. */
1098 /* Now consider each movable insn to decide whether it is worth moving.
1099 Store 0 in set_in_loop for each reg that is moved.
1101 Generally this increases code size, so do not move moveables when
1102 optimizing for code size. */
1107 /* Now candidates that still are negative are those not moved.
1108 Change set_in_loop to indicate that those are not actually invariant. */
1113 /* Now that we've moved some things out of the loop, we might be able to
1114 hoist even more memory references. */
1121 ;
1128 {
1130 /* Ensure our label doesn't go away. */
1142 }
1148 }
1149 \f
1150 /* Add elements to *OUTPUT to record all the pseudo-regs
1151 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1153 void
1157 {
1165 {
1183 }
1187 {
1191 {
1200 }
1201 }
1202 }
1203 \f
1204 /* Check what regs are referred to in the libcall block ending with INSN,
1205 aside from those mentioned in the equivalent value.
1206 If there are none, return 0.
1207 If there are one or more, return an EXPR_LIST containing all of them. */
1209 rtx
1212 {
1217 /* First, find all the regs used in the libcall block
1218 that are not mentioned as inputs to the result. */
1221 {
1226 }
1229 }
1230 \f
1231 /* Return 1 if all uses of REG
1232 are between INSN and the end of the basic block. */
1234 static int
1237 {
1239 rtx p;
1244 /* Search this basic block for the already recorded last use of the reg. */
1246 {
1248 {
1254 /* Ordinary insn: if this is the last use, we win. */
1260 /* Jump insn: if this is the last use, we win. */
1263 /* Otherwise, it's the end of the basic block, so we lose. */
1268 /* It's the end of the basic block, so we lose. */
1273 }
1274 }
1276 /* The "last use" that was recorded can't be found after the first
1277 use. This can happen when the last use was deleted while
1278 processing an inner loop, this inner loop was then completely
1279 unrolled, and the outer loop is always exited after the inner loop,
1280 so that everything after the first use becomes a single basic block. */
1282 }
1283 \f
1284 /* Compute the benefit of eliminating the insns in the block whose
1285 last insn is LAST. This may be a group of insns used to compute a
1286 value directly or can contain a library call. */
1288 static int
1290 rtx last;
1291 {
1292 rtx insn;
1297 {
1300 routine. */
1304 benefit++;
1305 }
1308 }
1309 \f
1310 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1312 static rtx
1314 rtx insn;
1316 {
1318 {
1319 rtx temp;
1321 /* If first insn of libcall sequence, skip to end. */
1322 /* Do this at start of loop, since INSN is guaranteed to
1323 be an insn here. */
1328 do
1331 }
1334 }
1336 /* Ignore any movable whose insn falls within a libcall
1337 which is part of another movable.
1338 We make use of the fact that the movable for the libcall value
1339 was made later and so appears later on the chain. */
1341 static void
1344 {
1348 {
1349 /* Is this a movable for the value of a libcall? */
1352 {
1353 rtx insn;
1354 /* Check for earlier movables inside that range,
1355 and mark them invalid. We cannot use LUIDs here because
1356 insns created by loop.c for prior loops don't have LUIDs.
1357 Rather than reject all such insns from movables, we just
1358 explicitly check each insn in the libcall (since invariant
1359 libcalls aren't that common). */
1364 }
1365 }
1366 }
1368 /* For each movable insn, see if the reg that it loads
1369 leads when it dies right into another conditionally movable insn.
1370 If so, record that the second insn "forces" the first one,
1371 since the second can be moved only if the first is. */
1373 static void
1376 {
1379 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1381 {
1384 /* ??? Could this be a bug? What if CSE caused the
1385 register of M1 to be used after this insn?
1386 Since CSE does not update regno_last_uid,
1387 this insn M->insn might not be where it dies.
1388 But very likely this doesn't matter; what matters is
1389 that M's reg is computed from M1's reg. */
1394 /* If m->consec, m->set_src isn't valid. */
1398 /* Increase the priority of the moving the first insn
1399 since it permits the second to be moved as well. */
1401 {
1405 }
1406 }
1407 }
1408 \f
1409 /* Find invariant expressions that are equal and can be combined into
1410 one register. */
1412 static void
1416 {
1421 /* Regs that are set more than once are not allowed to match
1422 or be matched. I'm no longer sure why not. */
1423 /* Perhaps testing m->consec_sets would be more appropriate here? */
1428 {
1435 /* We want later insns to match the first one. Don't make the first
1436 one match any later ones. So start this loop at m->next. */
1439 /* A reg used outside the loop mustn't be eliminated. */
1441 /* A reg used for zero-extending mustn't be eliminated. */
1444 ||
1445 (
1446 /* Can combine regs with different modes loaded from the
1447 same constant only if the modes are the same or
1448 if both are integer modes with M wider or the same
1449 width as M1. The check for integer is redundant, but
1450 safe, since the only case of differing destination
1451 modes with equal sources is when both sources are
1452 VOIDmode, i.e., CONST_INT. */
1458 /* See if the source of M1 says it matches M. */
1462 movables))))
1465 {
1471 }
1472 }
1474 /* Now combine the regs used for zero-extension.
1475 This can be done for those not marked `global'
1476 provided their lives don't overlap. */
1480 {
1483 /* Combine all the registers for extension from mode MODE.
1484 Don't combine any that are used outside this loop. */
1488 {
1494 {
1495 /* First one: don't check for overlap, just record it. */
1498 }
1500 /* Make sure they extend to the same mode.
1501 (Almost always true.) */
1505 /* We already have one: check for overlap with those
1506 already combined together. */
1513 /* No overlap: we can combine this with the others. */
1519 overlap:
1520 ;
1521 }
1522 }
1524 /* Clean up. */
1526 }
1527 \f
1528 /* Return 1 if regs X and Y will become the same if moved. */
1530 static int
1534 {
1551 }
1553 /* Return 1 if X and Y are identical-looking rtx's.
1554 This is the Lisp function EQUAL for rtx arguments.
1556 If two registers are matching movables or a movable register and an
1557 equivalent constant, consider them equal. */
1559 static int
1563 {
1577 /* If we have a register and a constant, they may sometimes be
1578 equal. */
1581 {
1586 }
1589 {
1594 }
1596 /* Otherwise, rtx's of different codes cannot be equal. */
1600 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1601 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1606 /* These three types of rtx's can be compared nonrecursively. */
1615 /* Compare the elements. If any pair of corresponding elements
1616 fail to match, return 0 for the whole things. */
1620 {
1622 {
1634 /* Two vectors must have the same length. */
1638 /* And the corresponding elements must match. */
1655 /* These are just backpointers, so they don't matter. */
1661 /* It is believed that rtx's at this level will never
1662 contain anything but integers and other rtx's,
1663 except for within LABEL_REFs and SYMBOL_REFs. */
1666 }
1667 }
1669 }
1670 \f
1671 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1672 insns in INSNS which use the reference. */
1674 static void
1676 rtx x;
1677 rtx insns;
1678 {
1682 rtx insn;
1685 {
1686 /* This code used to ignore labels that referred to dispatch tables to
1687 avoid flow generating (slighly) worse code.
1689 We no longer ignore such label references (see LABEL_REF handling in
1690 mark_jump_label for additional information). */
1695 }
1699 {
1705 }
1706 }
1707 \f
1708 /* Scan MOVABLES, and move the insns that deserve to be moved.
1709 If two matching movables are combined, replace one reg with the
1710 other throughout. */
1712 static void
1719 {
1725 /* Map of pseudo-register replacements to handle combining
1726 when we move several insns that load the same value
1727 into different pseudo-registers. */
1734 {
1735 /* Describe this movable insn. */
1738 {
1759 }
1761 /* Count movables. Value used in heuristics in strength_reduce. */
1762 num_movables++;
1764 /* Ignore the insn if it's already done (it matched something else).
1765 Otherwise, see if it is now safe to move. */
1777 {
1782 /* We have an insn that is safe to move.
1783 Compute its desirability. */
1794 /* An insn MUST be moved if we already moved something else
1795 which is safe only if this one is moved too: that is,
1796 if already_moved[REGNO] is nonzero. */
1798 /* An insn is desirable to move if the new lifetime of the
1799 register is no more than THRESHOLD times the old lifetime.
1800 If it's not desirable, it means the loop is so big
1801 that moving won't speed things up much,
1802 and it is liable to make register usage worse. */
1804 /* It is also desirable to move if it can be moved at no
1805 extra cost because something else was already moved. */
1808 || flag_move_all_movables
1813 {
1818 /* Now move the insns that set the reg. */
1821 {
1824 /* Find the end of this chain of matching regs.
1825 Thus, we load each reg in the chain from that one reg.
1826 And that reg is loaded with 0 directly,
1827 since it has ->match == 0. */
1833 /* Mark the moved, invariant reg as being allowed to
1834 share a hard reg with the other matching invariant. */
1838 regs_may_share
1841 regs_may_share));
1849 }
1850 /* If we are to re-generate the item being moved with a
1851 new move insn, first delete what we have and then emit
1852 the move insn before the loop. */
1854 {
1858 {
1859 /* If this is the first insn of a library call sequence,
1860 skip to the end. */
1865 /* If this is the last insn of a libcall sequence, then
1866 delete every insn in the sequence except the last.
1867 The last insn is handled in the normal manner. */
1870 {
1874 }
1879 /* simplify_giv_expr expects that it can walk the insns
1880 at m->insn forwards and see this old sequence we are
1881 tossing here. delete_insn does preserve the next
1882 pointers, but when we skip over a NOTE we must fix
1883 it up. Otherwise that code walks into the non-deleted
1884 insn stream. */
1887 }
1905 /* The more regs we move, the less we like moving them. */
1907 }
1908 else
1909 {
1911 {
1914 /* If first insn of libcall sequence, skip to end. */
1915 /* Do this at start of loop, since p is guaranteed to
1916 be an insn here. */
1921 /* If last insn of libcall sequence, move all
1922 insns except the last before the loop. The last
1923 insn is handled in the normal manner. */
1926 {
1934 {
1935 rtx body;
1936 rtx n;
1937 rtx next;
1944 /* Find the next insn after TEMP,
1945 not counting USE or NOTE insns. */
1953 /* If that is the call, this may be the insn
1954 that loads the function address.
1956 Extract the function address from the insn
1957 that loads it into a register.
1958 If this insn was cse'd, we get incorrect code.
1960 So emit a new move insn that copies the
1961 function address into the register that the
1962 call insn will use. flow.c will delete any
1963 redundant stores that we have created. */
1968 NULL_RTX)))
1969 {
1975 }
1976 /* We have the call insn.
1977 If it uses the register we suspect it might,
1978 load it with the correct address directly. */
1983 fn_address),
1984 fn_address_insn);
1987 {
1989 /* Because the USAGE information potentially
1990 contains objects other than hard registers
1991 we need to copy it. */
1995 }
1996 else
2004 }
2007 }
2009 {
2010 /* P sets REG to zero; but we should clear only
2011 the bits that are not covered by the mode
2012 m->savemode. */
2014 rtx sequence;
2015 rtx tem;
2018 tem = expand_binop
2031 }
2033 {
2035 /* Because the USAGE information potentially
2036 contains objects other than hard registers
2037 we need to copy it. */
2041 }
2043 {
2044 /* The SET_SRC might not be invariant, so we must
2045 use the REG_EQUAL note. */
2059 }
2060 else
2064 {
2067 /* If there is a REG_EQUAL note present whose value
2068 is not loop invariant, then delete it, since it
2069 may cause problems with later optimization passes.
2070 It is possible for cse to create such notes
2071 like this as a result of record_jump_cond. */
2076 }
2085 /* If library call, now fix the REG_NOTES that contain
2086 insn pointers, namely REG_LIBCALL on FIRST
2087 and REG_RETVAL on I1. */
2089 {
2093 }
2099 /* simplify_giv_expr expects that it can walk the insns
2100 at m->insn forwards and see this old sequence we are
2101 tossing here. delete_insn does preserve the next
2102 pointers, but when we skip over a NOTE we must fix
2103 it up. Otherwise that code walks into the non-deleted
2104 insn stream. */
2107 }
2109 /* The more regs we move, the less we like moving them. */
2111 }
2113 /* Any other movable that loads the same register
2114 MUST be moved. */
2117 /* This reg has been moved out of one loop. */
2120 /* The reg set here is now invariant. */
2126 /* Change the length-of-life info for the register
2127 to say it lives at least the full length of this loop.
2128 This will help guide optimizations in outer loops. */
2131 /* This is the old insn before all the moved insns.
2132 We can't use the moved insn because it is out of range
2133 in uid_luid. Only the old insns have luids. */
2138 /* Combine with this moved insn any other matching movables. */
2143 {
2144 rtx temp;
2146 /* Schedule the reg loaded by M1
2147 for replacement so that shares the reg of M.
2148 If the modes differ (only possible in restricted
2149 circumstances, make a SUBREG.
2151 Note this assumes that the target dependent files
2152 treat REG and SUBREG equally, including within
2153 GO_IF_LEGITIMATE_ADDRESS and in all the
2154 predicates since we never verify that replacing the
2155 original register with a SUBREG results in a
2156 recognizable insn. */
2159 else
2164 /* Get rid of the matching insn
2165 and prevent further processing of it. */
2168 /* if library call, delete all insn except last, which
2169 is deleted below */
2171 NULL_RTX)))
2172 {
2176 }
2179 /* Any other movable that loads the same register
2180 MUST be moved. */
2183 /* The reg merged here is now invariant,
2184 if the reg it matches is invariant. */
2187 }
2188 }
2191 }
2197 }
2202 /* Go through all the instructions in the loop, making
2203 all the register substitutions scheduled in REG_MAP. */
2207 {
2211 }
2213 /* Clean up. */
2216 }
2217 \f
2218 #if 0
2219 /* Scan X and replace the address of any MEM in it with ADDR.
2220 REG is the address that MEM should have before the replacement. */
2222 static void
2225 {
2234 {
2246 /* Short cut for very common case. */
2251 /* Short cut for very common case. */
2256 /* If this MEM uses a reg other than the one we expected,
2257 something is wrong. */
2265 }
2269 {
2273 {
2277 }
2278 }
2279 }
2280 #endif
2281 \f
2282 /* Return the number of memory refs to addresses that vary
2283 in the rtx X. */
2285 static int
2288 rtx x;
2289 {
2300 {
2317 }
2322 {
2326 {
2330 }
2331 }
2333 }
2334 \f
2335 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2336 `has_call', `has_volatile', and `has_tablejump' within LOOP.
2337 Set the global variables `unknown_address_altered',
2338 `unknown_constant_address_altered', and `num_mem_sets'. Also, fill
2339 in the array `loop_mems' and the list `loop_store_mems'. */
2341 static void
2344 {
2346 rtx insn;
2350 /* The label after END. Jumping here is just like falling off the
2351 end of the loop. We use next_nonnote_insn instead of next_label
2352 as a hedge against the (pathological) case where some actual insn
2353 might end up between the two. */
2372 {
2374 {
2376 {
2378 /* Count number of loops contained in this one. */
2380 }
2382 {
2384 }
2385 }
2387 {
2391 }
2393 {
2413 {
2415 {
2418 }
2419 else
2420 {
2422 }
2424 do
2425 {
2427 {
2429 {
2430 /* Something tricky. */
2433 }
2436 {
2437 /* A jump outside the current loop. */
2440 }
2441 }
2445 }
2447 }
2448 }
2451 }
2453 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2455 anywhere. */
2457 /* We don't want loads for MEMs moved to a location before the
2458 one at which their stack memory becomes allocated. (Note
2459 that this is not a problem for malloc, etc., since those
2460 require actual function calls. */
2461 && ! current_function_calls_alloca
2462 /* There are ways to leave the loop other than falling off the
2463 end. */
2469 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2470 that loop_invariant_p and load_mems can use true_dependence
2471 to determine what is really clobbered. */
2473 {
2477 }
2479 {
2484 }
2485 }
2486 \f
2487 /* LOOP->CONT_DOMINATOR is now the last label between the loop start
2488 and the continue note that is a the destination of a (cond)jump after
2489 the continue note. If there is any (cond)jump between the loop start
2490 and what we have so far as LOOP->CONT_DOMINATOR that has a
2491 target between LOOP->CONT_DOMINATOR and the continue note, move
2492 LOOP->CONT_DOMINATOR forward to that label; if a jump's
2493 destination cannot be determined, clear LOOP->CONT_DOMINATOR. */
2495 static void
2498 {
2499 rtx insn;
2502 /* This can happen for an empty loop, e.g. in
2503 gcc.c-torture/compile/920410-2.c */
2506 {
2509 }
2512 {
2515 {
2519 /* If it is not a jump we can easily understand or for
2520 which we do not have jump target information in the JUMP_LABEL
2521 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2522 LOOP->CONT_DOMINATOR. */
2525 {
2528 }
2532 && (label_luid
2535 }
2536 }
2537 }
2539 /* Scan the function looking for loops. Record the start and end of each loop.
2540 Also mark as invalid loops any loops that contain a setjmp or are branched
2541 to from outside the loop. */
2543 static void
2545 rtx f;
2547 {
2548 rtx insn;
2549 rtx label;
2559 /* If there are jumps to undefined labels,
2560 treat them as jumps out of any/all loops.
2561 This also avoids writing past end of tables when there are no loops. */
2564 /* Find boundaries of loops, mark which loops are contained within
2565 loops, and invalidate loops that have setjmp. */
2570 {
2573 {
2577 num_loops++;
2584 /* In this case, we must invalidate our current loop and any
2585 enclosing loop. */
2587 {
2593 }
2615 }
2616 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2617 and NOTE_INSN_LOOP_END notes, update loop->cont_dominator. */
2621 {
2628 do
2629 {
2630 /* First see if we care about this loop. */
2632 {
2633 /* If the jump destination is not known, invalidate
2634 loop->cont_dominator. */
2637 else
2638 /* Check if the destination is between loop start and
2639 cont. */
2644 /* And if there is no later destination already
2645 recorded. */
2650 }
2652 }
2654 }
2656 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2657 enclosing loop, but this doesn't matter. */
2659 }
2661 /* Any loop containing a label used in an initializer must be invalidated,
2662 because it can be jumped into from anywhere. */
2665 {
2669 }
2671 /* Any loop containing a label used for an exception handler must be
2672 invalidated, because it can be jumped into from anywhere. */
2675 {
2679 }
2681 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2682 loop that it is not contained within, that loop is marked invalid.
2683 If any INSN or CALL_INSN uses a label's address, then the loop containing
2684 that label is marked invalid, because it could be jumped into from
2685 anywhere.
2687 Also look for blocks of code ending in an unconditional branch that
2688 exits the loop. If such a block is surrounded by a conditional
2689 branch around the block, move the block elsewhere (see below) and
2690 invert the jump to point to the code block. This may eliminate a
2691 label in our loop and will simplify processing by both us and a
2692 possible second cse pass. */
2696 {
2700 {
2703 {
2707 }
2708 }
2715 /* See if this is an unconditional branch outside the loop. */
2723 {
2724 rtx p;
2730 /* Go backwards until we reach the start of the loop, a label,
2731 or a JUMP_INSN. */
2738 ;
2740 /* Check for the case where we have a jump to an inner nested
2741 loop, and do not perform the optimization in that case. */
2744 {
2747 {
2752 }
2753 }
2755 /* Make sure that the target of P is within the current loop. */
2761 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2762 we have a block of code to try to move.
2764 We look backward and then forward from the target of INSN
2765 to find a BARRIER at the same loop depth as the target.
2766 If we find such a BARRIER, we make a new label for the start
2767 of the block, invert the jump in P and point it to that label,
2768 and move the block of code to the spot we found. */
2773 /* Just ignore jumps to labels that were never emitted.
2774 These always indicate compilation errors. */
2778 /* If it's not safe to move the sequence, then we
2779 mustn't try. */
2782 {
2783 rtx target
2790 /* Don't move things inside a tablejump. */
2803 /* Don't move things inside a tablejump. */
2814 {
2818 /* Ensure our label doesn't go away. */
2821 /* Verify that uid_loop is large enough and that
2822 we can invert P. */
2824 {
2827 /* If no suitable BARRIER was found, create a suitable
2828 one before TARGET. Since TARGET is a fall through
2829 path, we'll need to insert an jump around our block
2830 and a add a BARRIER before TARGET.
2832 This creates an extra unconditional jump outside
2833 the loop. However, the benefits of removing rarely
2834 executed instructions from inside the loop usually
2835 outweighs the cost of the extra unconditional jump
2836 outside the loop. */
2838 {
2839 rtx temp;
2846 }
2848 /* Include the BARRIER after INSN and copy the
2849 block after LOC. */
2851 last_insn_to_move);
2854 /* All those insns are now in TARGET_LOOP. */
2860 /* The label jumped to by INSN is no longer a loop
2861 exit. Unless INSN does not have a label (e.g.,
2862 it is a RETURN insn), search loop->exit_labels
2863 to find its label_ref, and remove it. Also turn
2864 off LABEL_OUTSIDE_LOOP_P bit. */
2866 {
2871 {
2875 else
2878 }
2884 /* If we didn't find it, then something is
2885 wrong. */
2888 }
2890 /* P is now a jump outside the loop, so it must be put
2891 in loop->exit_labels, and marked as such.
2892 The easiest way to do this is to just call
2893 mark_loop_jump again for P. */
2896 /* If INSN now jumps to the insn after it,
2897 delete INSN. */
2902 }
2904 /* Continue the loop after where the conditional
2905 branch used to jump, since the only branch insn
2906 in the block (if it still remains) is an inter-loop
2907 branch and hence needs no processing. */
2913 /* This loop will be continued with NEXT_INSN (insn). */
2915 }
2916 }
2917 }
2918 }
2919 }
2921 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2922 loops it is contained in, mark the target loop invalid.
2924 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2926 static void
2928 rtx x;
2930 {
2936 {
2948 /* There could be a label reference in here. */
2960 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2972 /* Link together all labels that branch outside the loop. This
2973 is used by final_[bg]iv_value and the loop unrolling code. Also
2974 mark this LABEL_REF so we know that this branch should predict
2975 false. */
2977 /* A check to make sure the label is not in an inner nested loop,
2978 since this does not count as a loop exit. */
2980 {
2985 }
2986 else
2990 {
2999 }
3001 /* If this is inside a loop, but not in the current loop or one enclosed
3002 by it, it invalidates at least one loop. */
3007 /* We must invalidate every nested loop containing the target of this
3008 label, except those that also contain the jump insn. */
3011 {
3012 /* Stop when we reach a loop that also contains the jump insn. */
3017 /* If we get here, we know we need to invalidate a loop. */
3024 }
3028 /* If this is not setting pc, ignore. */
3050 /* Strictly speaking this is not a jump into the loop, only a possible
3051 jump out of the loop. However, we have no way to link the destination
3052 of this jump onto the list of exit labels. To be safe we mark this
3053 loop and any containing loops as invalid. */
3055 {
3057 {
3063 }
3064 }
3066 }
3067 }
3068 \f
3069 /* Return nonzero if there is a label in the range from
3070 insn INSN to and including the insn whose luid is END
3071 INSN must have an assigned luid (i.e., it must not have
3072 been previously created by loop.c). */
3074 static int
3076 rtx insn;
3078 {
3080 {
3084 }
3087 }
3089 /* Record that a memory reference X is being set. */
3091 static void
3093 rtx x;
3094 rtx y ATTRIBUTE_UNUSED;
3096 {
3100 /* Count number of memory writes.
3101 This affects heuristics in strength_reduce. */
3102 num_mem_sets++;
3104 /* BLKmode MEM means all memory is clobbered. */
3106 {
3109 else
3113 }
3116 }
3118 /* X is a value modified by an INSN that references a biv inside a loop
3119 exit test (ie, X is somehow related to the value of the biv). If X
3120 is a pseudo that is used more than once, then the biv is (effectively)
3121 used more than once. DATA is really an `int *', and is set if the
3122 biv is used more than once. */
3124 static void
3126 rtx x;
3127 rtx y ATTRIBUTE_UNUSED;
3129 {
3142 /* If we do not have usage information, or if we know the register
3143 is used more than once, note that fact for check_dbra_loop. */
3148 }
3149 \f
3150 /* Return nonzero if the rtx X is invariant over the current loop.
3152 The value is 2 if we refer to something only conditionally invariant.
3154 A memory ref is invariant if it is not volatile and does not conflict
3155 with anything stored in `loop_store_mems'. */
3157 int
3161 {
3166 rtx mem_list_entry;
3172 {
3180 /* A LABEL_REF is normally invariant, however, if we are unrolling
3181 loops, and this label is inside the loop, then it isn't invariant.
3182 This is because each unrolled copy of the loop body will have
3183 a copy of this label. If this was invariant, then an insn loading
3184 the address of this label into a register might get moved outside
3185 the loop, and then each loop body would end up using the same label.
3187 We don't know the loop bounds here though, so just fail for all
3188 labels. */
3191 else
3200 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3201 since the reg might be set by initialization within the loop. */
3218 /* Volatile memory references must be rejected. Do this before
3219 checking for read-only items, so that volatile read-only items
3220 will be rejected also. */
3224 /* See if there is any dependence between a store and this load. */
3227 {
3233 }
3235 /* It's not invalidated by a store in memory
3236 but we must still verify the address is invariant. */
3240 /* Don't mess with insns declared volatile. */
3247 }
3251 {
3253 {
3259 }
3261 {
3264 {
3270 }
3272 }
3273 }
3276 }
3277 \f
3278 /* Return nonzero if all the insns in the loop that set REG
3279 are INSN and the immediately following insns,
3280 and if each of those insns sets REG in an invariant way
3281 (not counting uses of REG in them).
3283 The value is 2 if some of these insns are only conditionally invariant.
3285 We assume that INSN itself is the first set of REG
3286 and that its source is invariant. */
3288 static int
3293 {
3296 rtx temp;
3297 /* Number of sets we have to insist on finding after INSN. */
3303 /* If N_SETS hit the limit, we can't rely on its value. */
3310 {
3312 rtx set;
3317 /* If library call, skip to end of it. */
3326 {
3331 {
3332 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3333 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3334 notes are OK. */
3340 }
3341 }
3343 count--;
3345 {
3348 }
3349 }
3352 /* If loop_invariant_p ever returned 2, we return 2. */
3354 }
3356 #if 0
3357 /* I don't think this condition is sufficient to allow INSN
3358 to be moved, so we no longer test it. */
3360 /* Return 1 if all insns in the basic block of INSN and following INSN
3361 that set REG are invariant according to TABLE. */
3363 static int
3367 {
3372 {
3381 {
3384 }
3385 }
3386 }
3388 \f
3389 /* Look at all uses (not sets) of registers in X. For each, if it is
3390 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3391 a different insn, set USAGE[REGNO] to const0_rtx. */
3393 static void
3395 rtx insn;
3396 rtx x;
3397 varray_type usage;
3398 {
3410 {
3411 /* Don't count SET_DEST if it is a REG; otherwise count things
3412 in SET_DEST because if a register is partially modified, it won't
3413 show up as a potential movable so we don't care how USAGE is set
3414 for it. */
3418 }
3419 else
3421 {
3427 }
3428 }
3429 \f
3430 /* Count and record any set in X which is contained in INSN. Update
3431 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3433 static void
3436 varray_type may_not_move;
3438 {
3440 /* Don't move a reg that has an explicit clobber.
3441 It's not worth the pain to try to do it correctly. */
3445 {
3453 {
3455 /* If this is the first setting of this reg
3456 in current basic block, and it was set before,
3457 it must be set in two basic blocks, so it cannot
3458 be moved out of the loop. */
3462 /* If this is not first setting in current basic block,
3463 see if reg was used in between previous one and this.
3464 If so, neither one can be moved. */
3471 }
3472 }
3473 }
3475 /* Increment SET_IN_LOOP at the index of each register
3476 that is modified by an insn between FROM and TO.
3477 If the value of an element of SET_IN_LOOP becomes 127 or more,
3478 stop incrementing it, to avoid overflow.
3480 Store in SINGLE_USAGE[I] the single insn in which register I is
3481 used, if it is only used once. Otherwise, it is set to 0 (for no
3482 uses) or const0_rtx for more than one use. This parameter may be zero,
3483 in which case this processing is not done.
3485 Store in *COUNT_PTR the number of actual instruction
3486 in the loop. We use this to decide what is worth moving out. */
3488 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3489 In that case, it is the insn that last set reg n. */
3491 static void
3494 varray_type may_not_move;
3495 varray_type single_usage;
3498 {
3505 {
3507 {
3510 /* Record registers that have exactly one use. */
3513 /* Include uses in REG_EQUAL notes. */
3521 {
3526 }
3527 }
3531 }
3534 /* Clean up. */
3536 }
3537 \f
3538 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3539 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3540 contained in insn INSN is used by any insn that precedes INSN in
3541 cyclic order starting from the loop entry point.
3543 We don't want to use INSN_LUID here because if we restrict INSN to those
3544 that have a valid INSN_LUID, it means we cannot move an invariant out
3545 from an inner loop past two loops. */
3547 static int
3551 {
3553 rtx p;
3555 /* Scan forward checking for register usage. If we hit INSN, we
3556 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3558 {
3564 }
3567 }
3568 \f
3569 /* A "basic induction variable" or biv is a pseudo reg that is set
3570 (within this loop) only by incrementing or decrementing it. */
3571 /* A "general induction variable" or giv is a pseudo reg whose
3572 value is a linear function of a biv. */
3574 /* Bivs are recognized by `basic_induction_var';
3575 Givs by `general_induction_var'. */
3577 /* Indexed by register number, indicates whether or not register is an
3578 induction variable, and if so what type. */
3580 varray_type reg_iv_type;
3582 /* Indexed by register number, contains pointer to `struct induction'
3583 if register is an induction variable. This holds general info for
3584 all induction variables. */
3586 varray_type reg_iv_info;
3588 /* Indexed by register number, contains pointer to `struct iv_class'
3589 if register is a basic induction variable. This holds info describing
3590 the class (a related group) of induction variables that the biv belongs
3591 to. */
3595 /* The head of a list which links together (via the next field)
3596 every iv class for the current loop. */
3600 /* Givs made from biv increments are always splittable for loop unrolling.
3601 Since there is no regscan info for them, we have to keep track of them
3602 separately. */
3605 /* Communication with routines called via `note_stores'. */
3609 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3613 /* ??? Unfinished optimizations, and possible future optimizations,
3614 for the strength reduction code. */
3616 /* ??? The interaction of biv elimination, and recognition of 'constant'
3617 bivs, may cause problems. */
3619 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3620 performance problems.
3622 Perhaps don't eliminate things that can be combined with an addressing
3623 mode. Find all givs that have the same biv, mult_val, and add_val;
3624 then for each giv, check to see if its only use dies in a following
3625 memory address. If so, generate a new memory address and check to see
3626 if it is valid. If it is valid, then store the modified memory address,
3627 otherwise, mark the giv as not done so that it will get its own iv. */
3629 /* ??? Could try to optimize branches when it is known that a biv is always
3630 positive. */
3632 /* ??? When replace a biv in a compare insn, we should replace with closest
3633 giv so that an optimized branch can still be recognized by the combiner,
3634 e.g. the VAX acb insn. */
3636 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3637 was rerun in loop_optimize whenever a register was added or moved.
3638 Also, some of the optimizations could be a little less conservative. */
3639 \f
3640 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3641 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3642 callback.
3644 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3645 loop iteration except for the last one.
3647 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3648 loop iteration.
3649 */
3650 void
3653 loop_insn_callback fncall;
3654 {
3655 /* This is 1 if current insn is not executed at least once for every loop
3656 iteration. */
3661 rtx p;
3663 /* If loop_scan_start points to the loop exit test, we have to be wary of
3664 subversive use of gotos inside expression statements. */
3668 /* Scan through loop to find all possible bivs. */
3673 {
3676 /* Past CODE_LABEL, we get to insns that may be executed multiple
3677 times. The only way we can be sure that they can't is if every
3678 jump insn between here and the end of the loop either
3679 returns, exits the loop, is a jump to a location that is still
3680 behind the label, or is a jump to the loop start. */
3683 {
3689 {
3694 {
3697 else
3701 }
3709 {
3712 }
3713 }
3714 }
3716 /* Past a jump, we get to insns for which we can't count
3717 on whether they will be executed during each iteration. */
3718 /* This code appears twice in strength_reduce. There is also similar
3719 code in scan_loop. */
3721 /* If we enter the loop in the middle, and scan around to the
3722 beginning, don't set not_every_iteration for that.
3723 This can be any kind of jump, since we want to know if insns
3724 will be executed if the loop is executed. */
3729 {
3732 /* If this is a jump outside the loop, then it also doesn't
3733 matter. Check to see if the target of this branch is on the
3734 loop->exits_labels list. */
3742 }
3745 {
3746 /* At the virtual top of a converted loop, insns are again known to
3747 be executed each iteration: logically, the loop begins here
3748 even though the exit code has been duplicated.
3750 Insns are also again known to be executed each iteration at
3751 the LOOP_CONT note. */
3757 loop_depth++;
3759 loop_depth--;
3760 }
3762 /* Note if we pass a loop latch. If we do, then we can not clear
3763 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3764 a loop since a jump before the last CODE_LABEL may have started
3765 a new loop iteration.
3767 Note that LOOP_TOP is only set for rotated loops and we need
3768 this check for all loops, so compare against the CODE_LABEL
3769 which immediately follows LOOP_START. */
3774 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3775 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3776 or not an insn is known to be executed each iteration of the
3777 loop, whether or not any iterations are known to occur.
3779 Therefore, if we have just passed a label and have no more labels
3780 between here and the test insn of the loop, and we have not passed
3781 a jump to the top of the loop, then we know these insns will be
3782 executed each iteration. */
3785 && !past_loop_latch
3790 }
3791 }
3792 \f
3793 /* Perform strength reduction and induction variable elimination.
3795 Pseudo registers created during this function will be beyond the last
3796 valid index in several tables including n_times_set and regno_last_uid.
3797 This does not cause a problem here, because the added registers cannot be
3798 givs outside of their loop, and hence will never be reconsidered.
3799 But scan_loop must check regnos to make sure they are in bounds. */
3801 static void
3806 {
3807 rtx p;
3808 /* Temporary list pointers for traversing loop_iv_list. */
3811 /* Ratio of extra register life span we can justify
3812 for saving an instruction. More if loop doesn't call subroutines
3813 since in that case saving an insn makes more difference
3814 and more registers are available. */
3815 /* ??? could set this to last value of threshold in move_movables */
3817 /* Map of pseudo-register replacements. */
3821 rtx test;
3822 rtx end_insert_before;
3837 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3838 must be put before this insn, so that they will appear in the right
3839 order (i.e. loop order).
3841 If loop_end is the end of the current function, then emit a
3842 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3843 dummy note insn. */
3846 else
3851 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3852 Make a sanity check against n_times_set. */
3854 {
3856 /* Above happens if register modified by subreg, etc. */
3857 /* Make sure it is not recognized as a basic induction var: */
3859 /* If never incremented, it is invariant that we decided not to
3860 move. So leave it alone. */
3862 {
3873 }
3874 else
3875 {
3880 }
3881 }
3883 /* Exit if there are no bivs. */
3885 {
3886 /* Can still unroll the loop anyways, but indicate that there is no
3887 strength reduction info available. */
3892 }
3894 /* Find initial value for each biv by searching backwards from loop_start,
3895 halting at first label. Also record any test condition. */
3899 {
3908 /* Record any test of a biv that branches around the loop if no store
3909 between it and the start of loop. We only care about tests with
3910 constants and registers and only certain of those. */
3920 {
3921 /* If an NE test, we have an initial value! */
3923 {
3927 }
3928 else
3930 }
3931 }
3933 /* Look at the each biv and see if we can say anything better about its
3934 initial value from any initializing insns set up above. (This is done
3935 in two passes to avoid missing SETs in a PARALLEL.) */
3937 {
3938 rtx src;
3939 rtx note;
3944 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3945 is a constant, use the value of that. */
3951 else
3962 {
3966 {
3968 {
3971 }
3972 else
3973 {
3976 }
3977 }
3978 }
3979 else
3980 {
3984 /* Biv initial value is not a simple move. If it is the sum of
3985 another biv and a constant, check if both bivs are incremented
3986 in lockstep. Then we are actually looking at a giv.
3987 For simplicity, we only handle the case where there is but a
3988 single increment, and the register is not used elsewhere. */
3996 {
4002 }
4004 /* Now, can we transform this biv into a giv? */
4008 /* init_insn is only set to insns that are before loop_start
4009 without any intervening labels. */
4012 /* The register from BL2 must be set before the register from
4013 BL is set, or we must be able to move the latter set after
4014 the former set. Currently there can't be any labels
4015 in-between when biv_total_increment returns nonzero both times
4016 but we test it here in case some day some real cfg analysis
4017 gets used to set always_computable. */
4026 {
4034 /* Let this giv be discovered by the generic code. */
4037 /* We can get better optimization if we can move the giv setting
4038 before the first giv use. */
4042 dominator)
4045 {
4046 rtx p;
4047 rtx next;
4050 {
4055 #ifdef HAVE_cc0
4057 #endif
4059 }
4063 /* Avoid problems with luids by actually moving the insn
4064 and adjusting all luids in the range. */
4069 /* If the only purpose of the init insn is to initialize
4070 this giv, delete it. */
4074 }
4076 {
4083 }
4084 /* Remove this biv from the chain. */
4086 }
4088 /* If we can't make it a giv,
4089 let biv keep initial value of "itself". */
4092 }
4093 }
4095 /* If a biv is unconditionally incremented several times in a row, convert
4096 all but the last increment into a giv. */
4098 /* Get an upper bound for the number of registers
4099 we might have after all bivs have been processed. */
4104 /* If the loop contains volatile memory references do not allow any
4105 replacements to take place, since this could loose the volatile
4106 markers. */
4108 {
4111 /* Reallocate reg_iv_type and reg_iv_info. */
4116 {
4120 /* The biv increments lists are in reverse order. Fix this
4121 first. */
4123 {
4127 }
4129 /* We must guard against the case that an early exit between v->insn
4130 and next->insn leaves the biv live after the loop, since that
4131 would mean that we'd be missing an increment for the final
4132 value. The following test to set biv_dead_after_loop is like
4133 the first part of the test to set bl->eliminable.
4134 We don't check here if we can calculate the final value, since
4135 this can't succeed if we already know that there is a jump
4136 between v->insn and next->insn, yet next->always_executed is
4137 set and next->maybe_multiple is cleared. Such a combination
4138 implies that the jump destination is outside the loop.
4139 If we want to make this check more sophisticated, we should
4140 check each branch between v->insn and next->insn individually
4141 to see if the biv is dead at its destination. */
4148 #ifdef HAVE_decrement_and_branch_until_zero
4150 #endif
4155 {
4156 HOST_WIDE_INT offset;
4159 rtx next_loc_insn;
4169 || ! (biv_dead_after_loop
4171 {
4174 }
4181 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4182 have been allocated with some slop space, so we may not
4183 actually need to reallocate them. If we do, the following
4184 if statement will be executed just once in this loop. */
4186 {
4187 /* Grow all the remaining arrays. */
4192 }
4194 /* Some bivs are incremented with a multi-insn sequence.
4195 The first insn contains the add. */
4206 {
4209 }
4211 /* Here we can try to eliminate the increment by combining
4212 it into the uses. */
4214 /* Set last_use_insn so that we can check against it. */
4219 {
4223 {
4225 }
4226 }
4228 /* If we can't get the LUIDs for the insns, we can't
4229 calculate the lifetime. This is likely from unrolling
4230 of an inner loop, so there is little point in making this
4231 a DEST_REG giv anyways. */
4235 {
4236 /* Change the increment at NEXT back to what it was. */
4242 }
4276 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4277 it must be replaced. */
4282 /* Remove the increment from the list of biv increments,
4283 and record it as a giv. */
4292 /* Now replace the biv with DEST_REG in all insns between
4293 the replaced increment and the next increment, and
4294 remember the last insn that needed a replacement. */
4298 {
4299 rtx note;
4304 {
4308 }
4310 {
4314 }
4315 }
4319 /* If the lifetime is zero, it means that this register is really
4320 a dead store. So mark this as a giv that can be ignored.
4321 This will not prevent the biv from being eliminated. */
4329 }
4330 }
4331 }
4334 /* Search the loop for general induction variables. */
4338 /* Try to calculate and save the number of loop iterations. This is
4339 set to zero if the actual number can not be calculated. This must
4340 be called after all giv's have been identified, since otherwise it may
4341 fail if the iteration variable is a giv. */
4345 /* Now for each giv for which we still don't know whether or not it is
4346 replaceable, check to see if it is replaceable because its final value
4347 can be calculated. This must be done after loop_iterations is called,
4348 so that final_giv_value will work correctly. */
4351 {
4357 }
4359 /* Try to prove that the loop counter variable (if any) is always
4360 nonnegative; if so, record that fact with a REG_NONNEG note
4361 so that "decrement and branch until zero" insn can be used. */
4364 /* Create reg_map to hold substitutions for replaceable giv regs.
4365 Some givs might have been made from biv increments, so look at
4366 reg_iv_type for a suitable size. */
4370 /* Examine each iv class for feasibility of strength reduction/induction
4371 variable elimination. */
4374 {
4381 /* Test whether it will be possible to eliminate this biv
4382 provided all givs are reduced. This is possible if either
4383 the reg is not used outside the loop, or we can compute
4384 what its final value will be.
4386 For architectures with a decrement_and_branch_until_zero insn,
4387 don't do this if we put a REG_NONNEG note on the endtest for
4388 this biv. */
4390 /* Compare against bl->init_insn rather than loop_start.
4391 We aren't concerned with any uses of the biv between
4392 init_insn and loop_start since these won't be affected
4393 by the value of the biv elsewhere in the function, so
4394 long as init_insn doesn't use the biv itself.
4395 March 14, 1989 -- self@bayes.arc.nasa.gov */
4401 #ifdef HAVE_decrement_and_branch_until_zero
4403 #endif
4406 #ifdef HAVE_decrement_and_branch_until_zero
4408 #endif
4409 ))
4411 insn_count);
4412 else
4413 {
4415 {
4423 }
4424 }
4426 /* Combine all giv's for this iv_class. */
4429 /* This will be true at the end, if all givs which depend on this
4430 biv have been strength reduced.
4431 We can't (currently) eliminate the biv unless this is so. */
4434 /* Check each giv in this class to see if we will benefit by reducing
4435 it. Skip giv's combined with others. */
4437 {
4445 /* Reduce benefit if not replaceable, since we will insert
4446 a move-insn to replace the insn that calculates this giv.
4447 Don't do this unless the giv is a user variable, since it
4448 will often be marked non-replaceable because of the duplication
4449 of the exit code outside the loop. In such a case, the copies
4450 we insert are dead and will be deleted. So they don't have
4451 a cost. Similar situations exist. */
4452 /* ??? The new final_[bg]iv_value code does a much better job
4453 of finding replaceable giv's, and hence this code may no longer
4454 be necessary. */
4459 /* Decrease the benefit to count the add-insns that we will
4460 insert to increment the reduced reg for the giv. */
4463 /* Decide whether to strength-reduce this giv or to leave the code
4464 unchanged (recompute it from the biv each time it is used).
4465 This decision can be made independently for each giv. */
4467 #ifdef AUTO_INC_DEC
4468 /* Attempt to guess whether autoincrement will handle some of the
4469 new add insns; if so, increase BENEFIT (undo the subtraction of
4470 add_cost that was done above). */
4473 {
4486 }
4487 #endif
4489 /* If an insn is not to be strength reduced, then set its ignore
4490 flag, and clear all_reduced. */
4492 /* A giv that depends on a reversed biv must be reduced if it is
4493 used after the loop exit, otherwise, it would have the wrong
4494 value after the loop exit. To make it simple, just reduce all
4495 of such giv's whether or not we know they are used after the loop
4496 exit. */
4500 {
4508 }
4509 else
4510 {
4511 /* Check that we can increment the reduced giv without a
4512 multiply insn. If not, reject it. */
4517 {
4525 }
4526 }
4527 }
4529 /* Check for givs whose first use is their definition and whose
4530 last use is the definition of another giv. If so, it is likely
4531 dead and should not be used to derive another giv nor to
4532 eliminate a biv. */
4534 {
4540 {
4546 }
4549 {
4555 }
4556 }
4558 /* Now that we know which givs will be reduced, try to rearrange the
4559 combinations to reduce register pressure.
4560 recombine_givs calls find_life_end, which needs reg_iv_type and
4561 reg_iv_info to be valid for all pseudos. We do the necessary
4562 reallocation here since it allows to check if there are still
4563 more bivs to process. */
4566 {
4567 /* If there are still more bivs to process, allocate some slack
4568 space so that we're not constantly reallocating these arrays. */
4571 /* Reallocate reg_iv_type and reg_iv_info. */
4574 }
4577 /* Reduce each giv that we decided to reduce. */
4580 {
4583 {
4586 /* If the code for derived givs immediately below has already
4587 allocated a new_reg, we must keep it. */
4592 {
4595 /* In case d->dest_reg is not replaceable, we have
4596 to replace it in v->insn now. */
4603 /* For each place where the biv is incremented, add an
4604 insn to set the new, reduced reg for the giv.
4605 We used to do this only for biv_count != 1, but
4606 this fails when there is a giv after a single biv
4607 increment, e.g. when the last giv was expressed as
4608 pre-decrement. */
4610 {
4611 /* We always emit reduced giv increments before the
4612 biv increment when bl->biv_count != 1. So by
4613 emitting the add insns for derived givs after the
4614 biv increment, they pick up the updated value of
4615 the reduced giv.
4616 If the reduced giv is processed with
4617 auto_inc_opt == 1, then it is incremented earlier
4618 than the biv, hence we'll still pick up the right
4619 value.
4620 If it's processed with auto_inc_opt == -1,
4621 that implies that the biv increment is before the
4622 first reduced giv's use. The derived giv's lifetime
4623 is after the reduced giv's lifetime, hence in this
4624 case, the biv increment doesn't matter. */
4626 }
4628 }
4630 #ifdef AUTO_INC_DEC
4631 /* If the target has auto-increment addressing modes, and
4632 this is an address giv, then try to put the increment
4633 immediately after its use, so that flow can create an
4634 auto-increment addressing mode. */
4637 /* We don't handle reversed biv's because bl->biv->insn
4638 does not have a valid INSN_LUID. */
4642 {
4643 /* If other giv's have been combined with this one, then
4644 this will work only if all uses of the other giv's occur
4645 before this giv's insn. This is difficult to check.
4647 We simplify this by looking for the common case where
4648 there is one DEST_REG giv, and this giv's insn is the
4649 last use of the dest_reg of that DEST_REG giv. If the
4650 increment occurs after the address giv, then we can
4651 perform the optimization. (Otherwise, the increment
4652 would have to go before other_giv, and we would not be
4653 able to combine it with the address giv to get an
4654 auto-inc address.) */
4656 {
4661 {
4664 else
4666 }
4673 }
4674 /* Check for case where increment is before the address
4675 giv. Do this test in "loop order". */
4684 else
4687 #ifdef HAVE_cc0
4688 {
4689 rtx prev;
4691 /* We can't put an insn immediately after one setting
4692 cc0, or immediately before one using cc0. */
4699 }
4700 #endif
4704 }
4705 #endif
4707 /* For each place where the biv is incremented, add an insn
4708 to increment the new, reduced reg for the giv. */
4710 {
4711 rtx insert_before;
4717 else
4724 /* A multiply is acceptable here
4725 since this is presumed to be seldom executed. */
4728 }
4730 /* Add code at loop start to initialize giv's reduced reg. */
4734 }
4735 }
4737 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4738 as not reduced.
4740 For each giv register that can be reduced now: if replaceable,
4741 substitute reduced reg wherever the old giv occurs;
4742 else add new move insn "giv_reg = reduced_reg". */
4745 {
4752 /* Update expression if this was combined, in case other giv was
4753 replaced. */
4759 /* Store reduced reg as the address in the memref where we found
4760 this giv. */
4763 {
4766 #if 0
4767 /* I can no longer duplicate the original problem. Perhaps
4768 this is unnecessary now? */
4770 /* Replaceable; it isn't strictly necessary to delete the old
4771 insn and emit a new one, because v->dest_reg is now dead.
4773 However, especially when unrolling loops, the special
4774 handling for (set REG0 REG1) in the second cse pass may
4775 make v->dest_reg live again. To avoid this problem, emit
4776 an insn to set the original giv reg from the reduced giv.
4777 We can not delete the original insn, since it may be part
4778 of a LIBCALL, and the code in flow that eliminates dead
4779 libcalls will fail if it is deleted. */
4782 #endif
4783 }
4784 else
4785 {
4786 /* Not replaceable; emit an insn to set the original giv reg from
4787 the reduced giv, same as above. */
4790 }
4792 /* When a loop is reversed, givs which depend on the reversed
4793 biv, and which are live outside the loop, must be set to their
4794 correct final value. This insn is only needed if the giv is
4795 not replaceable. The correct final value is the same as the
4796 value that the giv starts the reversed loop with. */
4801 {
4802 rtx insert_before;
4804 /* If the loop has multiple exits, emit the insn before the
4805 loop to ensure that it will always be executed no matter
4806 how the loop exits. Otherwise, emit the insn after the loop,
4807 since this is slightly more efficient. */
4810 else
4813 insert_before);
4815 #if 0
4816 /* If the insn to set the final value of the giv was emitted
4817 before the loop, then we must delete the insn inside the loop
4818 that sets it. If this is a LIBCALL, then we must delete
4819 every insn in the libcall. Note, however, that
4820 final_giv_value will only succeed when there are multiple
4821 exits if the giv is dead at each exit, hence it does not
4822 matter that the original insn remains because it is dead
4823 anyways. */
4824 /* Delete the insn inside the loop that sets the giv since
4825 the giv is now set before (or after) the loop. */
4827 #endif
4828 }
4831 {
4836 }
4837 }
4839 /* All the givs based on the biv bl have been reduced if they
4840 merit it. */
4842 /* For each giv not marked as maybe dead that has been combined with a
4843 second giv, clear any "maybe dead" mark on that second giv.
4844 v->new_reg will either be or refer to the register of the giv it
4845 combined with.
4847 Doing this clearing avoids problems in biv elimination where a
4848 giv's new_reg is a complex value that can't be put in the insn but
4849 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4850 Since the register will be used in either case, we'd prefer it be
4851 used from the simpler giv. */
4857 /* Try to eliminate the biv, if it is a candidate.
4858 This won't work if ! all_reduced,
4859 since the givs we planned to use might not have been reduced.
4861 We have to be careful that we didn't initially think we could eliminate
4862 this biv because of a giv that we now think may be dead and shouldn't
4863 be used as a biv replacement.
4865 Also, there is the possibility that we may have a giv that looks
4866 like it can be used to eliminate a biv, but the resulting insn
4867 isn't valid. This can happen, for example, on the 88k, where a
4868 JUMP_INSN can compare a register only with zero. Attempts to
4869 replace it with a compare with a constant will fail.
4871 Note that in cases where this call fails, we may have replaced some
4872 of the occurrences of the biv with a giv, but no harm was done in
4873 doing so in the rare cases where it can occur. */
4877 {
4878 /* ?? If we created a new test to bypass the loop entirely,
4879 or otherwise drop straight in, based on this test, then
4880 we might want to rewrite it also. This way some later
4881 pass has more hope of removing the initialization of this
4882 biv entirely. */
4884 /* If final_value != 0, then the biv may be used after loop end
4885 and we must emit an insn to set it just in case.
4887 Reversed bivs already have an insn after the loop setting their
4888 value, so we don't need another one. We can't calculate the
4889 proper final value for such a biv here anyways. */
4891 {
4892 rtx insert_before;
4894 /* If the loop has multiple exits, emit the insn before the
4895 loop to ensure that it will always be executed no matter
4896 how the loop exits. Otherwise, emit the insn after the
4897 loop, since this is slightly more efficient. */
4900 else
4904 end_insert_before);
4905 }
4907 #if 0
4908 /* Delete all of the instructions inside the loop which set
4909 the biv, as they are all dead. If is safe to delete them,
4910 because an insn setting a biv will never be part of a libcall. */
4911 /* However, deleting them will invalidate the regno_last_uid info,
4912 so keeping them around is more convenient. Final_biv_value
4913 will only succeed when there are multiple exits if the biv
4914 is dead at each exit, hence it does not matter that the original
4915 insn remains, because it is dead anyways. */
4918 #endif
4923 }
4924 }
4926 /* Go through all the instructions in the loop, making all the
4927 register substitutions scheduled in REG_MAP. */
4932 {
4936 }
4939 {
4940 /* When we completely unroll a loop we will likely not need the increment
4941 of the loop BIV and we will not need the conditional branch at the
4942 end of the loop. */
4945 #ifdef HAVE_cc0
4946 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4947 need the comparison before the conditional branch at the end of the
4948 loop. */
4950 #endif
4952 /* We'll need one copy for each loop iteration. */
4955 /* A little slop to account for the ability to remove initialization
4956 code, better CSE, and other secondary benefits of completely
4957 unrolling some loops. */
4960 /* Clamp the value. */
4963 }
4965 /* Unroll loops from within strength reduction so that we can use the
4966 induction variable information that strength_reduce has already
4967 collected. Always unroll loops that would be as small or smaller
4968 unrolled than when rolled. */
4974 #ifdef HAVE_doloop_end
4982 egress:
4988 }
4989 \f
4990 /*Record all basic induction variables calculated in the insn. */
4991 static rtx
4994 rtx p;
4997 {
4998 rtx set;
4999 rtx dest_reg;
5000 rtx inc_val;
5001 rtx mult_val;
5007 {
5012 {
5017 {
5018 /* It is a possible basic induction variable.
5019 Create and initialize an induction structure for it. */
5027 }
5030 }
5031 }
5033 }
5034 \f
5035 /* Record all givs calculated in the insn.
5036 A register is a giv if: it is only set once, it is a function of a
5037 biv and a constant (or invariant), and it is not a biv. */
5038 static rtx
5041 rtx p;
5044 {
5045 rtx set;
5046 /* Look for a general induction variable in a register. */
5051 {
5052 rtx src_reg;
5053 rtx dest_reg;
5054 rtx add_val;
5055 rtx mult_val;
5058 rtx last_consec_insn;
5067 /* Equivalent expression is a giv. */
5072 /* Don't try to handle any regs made by loop optimization.
5073 We have nothing on them in regno_first_uid, etc. */
5075 /* Don't recognize a BASIC_INDUCT_VAR here. */
5077 /* This must be the only place where the register is set. */
5079 /* or all sets must be consecutive and make a giv. */
5084 {
5088 /* If this is a library call, increase benefit. */
5092 /* Skip the consecutive insns, if there are any. */
5100 }
5101 }
5103 #ifndef DONT_REDUCE_ADDR
5104 /* Look for givs which are memory addresses. */
5105 /* This resulted in worse code on a VAX 8600. I wonder if it
5106 still does. */
5109 maybe_multiple);
5110 #endif
5112 /* Update the status of whether giv can derive other givs. This can
5113 change when we pass a label or an insn that updates a biv. */
5118 }
5119 \f
5120 /* Return 1 if X is a valid source for an initial value (or as value being
5121 compared against in an initial test).
5123 X must be either a register or constant and must not be clobbered between
5124 the current insn and the start of the loop.
5126 INSN is the insn containing X. */
5128 static int
5130 rtx x;
5131 rtx insn;
5133 rtx loop_start;
5134 {
5138 /* Only consider pseudos we know about initialized in insns whose luids
5139 we know. */
5144 /* Don't use call-clobbered registers across a call which clobbers it. On
5145 some machines, don't use any hard registers at all. */
5147 && (SMALL_REGISTER_CLASSES
5151 /* Don't use registers that have been clobbered before the start of the
5152 loop. */
5157 }
5158 \f
5159 /* Scan X for memory refs and check each memory address
5160 as a possible giv. INSN is the insn whose pattern X comes from.
5161 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5162 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5163 more thanonce in each loop iteration. */
5165 static void
5168 rtx x;
5169 rtx insn;
5171 {
5181 {
5197 {
5198 rtx src_reg;
5199 rtx add_val;
5200 rtx mult_val;
5203 /* This code used to disable creating GIVs with mult_val == 1 and
5204 add_val == 0. However, this leads to lost optimizations when
5205 it comes time to combine a set of related DEST_ADDR GIVs, since
5206 this one would not be seen. */
5210 {
5211 /* Found one; record it. */
5220 }
5221 }
5226 }
5228 /* Recursively scan the subexpressions for other mem refs. */
5234 maybe_multiple);
5238 maybe_multiple);
5239 }
5240 \f
5241 /* Fill in the data about one biv update.
5242 V is the `struct induction' in which we record the biv. (It is
5243 allocated by the caller, with alloca.)
5244 INSN is the insn that sets it.
5245 DEST_REG is the biv's reg.
5247 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5248 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5249 being set to INC_VAL.
5251 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5252 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5253 can be executed more than once per iteration. If MAYBE_MULTIPLE
5254 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5255 executed exactly once per iteration. */
5257 static void
5261 rtx insn;
5262 rtx dest_reg;
5263 rtx inc_val;
5264 rtx mult_val;
5268 {
5282 /* Add this to the reg's iv_class, creating a class
5283 if this is the first incrementation of the reg. */
5287 {
5288 /* Create and initialize new iv_class. */
5298 /* Set initial value to the reg itself. */
5300 /* We haven't seen the initializing insn yet */
5310 /* Add this class to loop_iv_list. */
5314 /* Put it in the array of biv register classes. */
5316 }
5318 /* Update IV_CLASS entry for this biv. */
5326 {
5331 {
5335 }
5336 else
5337 {
5341 }
5342 }
5343 }
5344 \f
5345 /* Fill in the data about one giv.
5346 V is the `struct induction' in which we record the giv. (It is
5347 allocated by the caller, with alloca.)
5348 INSN is the insn that sets it.
5349 BENEFIT estimates the savings from deleting this insn.
5350 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5351 into a register or is used as a memory address.
5353 SRC_REG is the biv reg which the giv is computed from.
5354 DEST_REG is the giv's reg (if the giv is stored in a reg).
5355 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5356 LOCATION points to the place where this giv's value appears in INSN. */
5358 static void
5363 rtx insn;
5364 rtx src_reg;
5365 rtx dest_reg;
5371 {
5375 rtx temp;
5377 /* Attempt to prove constantness of the values. */
5406 /* The v->always_computable field is used in update_giv_derive, to
5407 determine whether a giv can be used to derive another giv. For a
5408 DEST_REG giv, INSN computes a new value for the giv, so its value
5409 isn't computable if INSN insn't executed every iteration.
5410 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5411 it does not compute a new value. Hence the value is always computable
5412 regardless of whether INSN is executed each iteration. */
5416 else
5422 {
5425 }
5427 {
5433 /* If the lifetime is zero, it means that this register is
5434 really a dead store. So mark this as a giv that can be
5435 ignored. This will not prevent the biv from being eliminated. */
5441 }
5443 /* Add the giv to the class of givs computed from one biv. */
5447 {
5450 /* Don't count DEST_ADDR. This is supposed to count the number of
5451 insns that calculate givs. */
5455 }
5456 else
5457 /* Fatal error, biv missing for this giv? */
5462 else
5463 {
5464 /* The giv can be replaced outright by the reduced register only if all
5465 of the following conditions are true:
5466 - the insn that sets the giv is always executed on any iteration
5467 on which the giv is used at all
5468 (there are two ways to deduce this:
5469 either the insn is executed on every iteration,
5470 or all uses follow that insn in the same basic block),
5471 - the giv is not used outside the loop
5472 - no assignments to the biv occur during the giv's lifetime. */
5475 /* Previous line always fails if INSN was moved by loop opt. */
5478 && (! not_every_iteration
5480 {
5481 /* Now check that there are no assignments to the biv within the
5482 giv's lifetime. This requires two separate checks. */
5484 /* Check each biv update, and fail if any are between the first
5485 and last use of the giv.
5487 If this loop contains an inner loop that was unrolled, then
5488 the insn modifying the biv may have been emitted by the loop
5489 unrolling code, and hence does not have a valid luid. Just
5490 mark the biv as not replaceable in this case. It is not very
5491 useful as a biv, because it is used in two different loops.
5492 It is very unlikely that we would be able to optimize the giv
5493 using this biv anyways. */
5497 {
5503 {
5507 }
5508 }
5510 /* If there are any backwards branches that go from after the
5511 biv update to before it, then this giv is not replaceable. */
5515 {
5519 }
5520 }
5521 else
5522 {
5523 /* May still be replaceable, we don't have enough info here to
5524 decide. */
5527 }
5528 }
5530 /* Record whether the add_val contains a const_int, for later use by
5531 combine_givs. */
5532 {
5537 ;
5541 {
5543 {
5548 else
5550 }
5553 }
5554 }
5557 {
5561 else
5577 {
5580 }
5581 else
5582 {
5585 }
5588 {
5591 }
5592 else
5593 {
5596 }
5597 }
5602 }
5604 /* All this does is determine whether a giv can be made replaceable because
5605 its final value can be calculated. This code can not be part of record_giv
5606 above, because final_giv_value requires that the number of loop iterations
5607 be known, and that can not be accurately calculated until after all givs
5608 have been identified. */
5610 static void
5614 {
5620 /* DEST_ADDR givs will never reach here, because they are always marked
5621 replaceable above in record_giv. */
5623 /* The giv can be replaced outright by the reduced register only if all
5624 of the following conditions are true:
5625 - the insn that sets the giv is always executed on any iteration
5626 on which the giv is used at all
5627 (there are two ways to deduce this:
5628 either the insn is executed on every iteration,
5629 or all uses follow that insn in the same basic block),
5630 - its final value can be calculated (this condition is different
5631 than the one above in record_giv)
5632 - no assignments to the biv occur during the giv's lifetime. */
5634 #if 0
5635 /* This is only called now when replaceable is known to be false. */
5636 /* Clear replaceable, so that it won't confuse final_giv_value. */
5638 #endif
5642 {
5645 rtx last_giv_use;
5649 /* When trying to determine whether or not a biv increment occurs
5650 during the lifetime of the giv, we can ignore uses of the variable
5651 outside the loop because final_value is true. Hence we can not
5652 use regno_last_uid and regno_first_uid as above in record_giv. */
5654 /* Search the loop to determine whether any assignments to the
5655 biv occur during the giv's lifetime. Start with the insn
5656 that sets the giv, and search around the loop until we come
5657 back to that insn again.
5659 Also fail if there is a jump within the giv's lifetime that jumps
5660 to somewhere outside the lifetime but still within the loop. This
5661 catches spaghetti code where the execution order is not linear, and
5662 hence the above test fails. Here we assume that the giv lifetime
5663 does not extend from one iteration of the loop to the next, so as
5664 to make the test easier. Since the lifetime isn't known yet,
5665 this requires two loops. See also record_giv above. */
5670 {
5679 {
5680 /* It is possible for the BIV increment to use the GIV if we
5681 have a cycle. Thus we must be sure to check each insn for
5682 both BIV and GIV uses, and we must check for BIV uses
5683 first. */
5690 {
5692 {
5696 }
5698 }
5699 }
5700 }
5702 /* Now that the lifetime of the giv is known, check for branches
5703 from within the lifetime to outside the lifetime if it is still
5704 replaceable. */
5707 {
5710 {
5723 {
5732 }
5733 }
5734 }
5736 /* If it is replaceable, then save the final value. */
5739 }
5744 }
5745 \f
5746 /* Update the status of whether a giv can derive other givs.
5748 We need to do something special if there is or may be an update to the biv
5749 between the time the giv is defined and the time it is used to derive
5750 another giv.
5752 In addition, a giv that is only conditionally set is not allowed to
5753 derive another giv once a label has been passed.
5755 The cases we look at are when a label or an update to a biv is passed. */
5757 static void
5760 rtx p;
5761 {
5764 rtx tem;
5767 /* Search all IV classes, then all bivs, and finally all givs.
5769 There are three cases we are concerned with. First we have the situation
5770 of a giv that is only updated conditionally. In that case, it may not
5771 derive any givs after a label is passed.
5773 The second case is when a biv update occurs, or may occur, after the
5774 definition of a giv. For certain biv updates (see below) that are
5775 known to occur between the giv definition and use, we can adjust the
5776 giv definition. For others, or when the biv update is conditional,
5777 we must prevent the giv from deriving any other givs. There are two
5778 sub-cases within this case.
5780 If this is a label, we are concerned with any biv update that is done
5781 conditionally, since it may be done after the giv is defined followed by
5782 a branch here (actually, we need to pass both a jump and a label, but
5783 this extra tracking doesn't seem worth it).
5785 If this is a jump, we are concerned about any biv update that may be
5786 executed multiple times. We are actually only concerned about
5787 backward jumps, but it is probably not worth performing the test
5788 on the jump again here.
5790 If this is a biv update, we must adjust the giv status to show that a
5791 subsequent biv update was performed. If this adjustment cannot be done,
5792 the giv cannot derive further givs. */
5798 {
5800 {
5801 /* If cant_derive is already true, there is no point in
5802 checking all of these conditions again. */
5806 /* If this giv is conditionally set and we have passed a label,
5807 it cannot derive anything. */
5811 /* Skip givs that have mult_val == 0, since
5812 they are really invariants. Also skip those that are
5813 replaceable, since we know their lifetime doesn't contain
5814 any biv update. */
5818 /* The only way we can allow this giv to derive another
5819 is if this is a biv increment and we can form the product
5820 of biv->add_val and giv->mult_val. In this case, we will
5821 be able to compute a compensation. */
5823 {
5834 tem = simplify_giv_expr
5841 else
5843 }
5847 }
5848 }
5849 }
5850 \f
5851 /* Check whether an insn is an increment legitimate for a basic induction var.
5852 X is the source of insn P, or a part of it.
5853 MODE is the mode in which X should be interpreted.
5855 DEST_REG is the putative biv, also the destination of the insn.
5856 We accept patterns of these forms:
5857 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5858 REG = INVARIANT + REG
5860 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5861 store the additive term into *INC_VAL, and store the place where
5862 we found the additive term into *LOCATION.
5864 If X is an assignment of an invariant into DEST_REG, we set
5865 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5867 We also want to detect a BIV when it corresponds to a variable
5868 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5869 of the variable may be a PLUS that adds a SUBREG of that variable to
5870 an invariant and then sign- or zero-extends the result of the PLUS
5871 into the variable.
5873 Most GIVs in such cases will be in the promoted mode, since that is the
5874 probably the natural computation mode (and almost certainly the mode
5875 used for addresses) on the machine. So we view the pseudo-reg containing
5876 the variable as the BIV, as if it were simply incremented.
5878 Note that treating the entire pseudo as a BIV will result in making
5879 simple increments to any GIVs based on it. However, if the variable
5880 overflows in its declared mode but not its promoted mode, the result will
5881 be incorrect. This is acceptable if the variable is signed, since
5882 overflows in such cases are undefined, but not if it is unsigned, since
5883 those overflows are defined. So we only check for SIGN_EXTEND and
5884 not ZERO_EXTEND.
5886 If we cannot find a biv, we return 0. */
5888 static int
5893 rtx dest_reg;
5894 rtx p;
5898 {
5906 {
5912 {
5914 }
5919 {
5921 }
5922 else
5935 /* If this is a SUBREG for a promoted variable, check the inner
5936 value. */
5944 /* If this register is assigned in a previous insn, look at its
5945 source, but don't go outside the loop or past a label. */
5947 /* If this sets a register to itself, we would repeat any previous
5948 biv increment if we applied this strategy blindly. */
5954 {
5955 do
5956 {
5958 }
5982 }
5983 /* ... fall through ... */
5985 /* Can accept constant setting of biv only when inside inner most loop.
5986 Otherwise, a biv of an inner loop may be incorrectly recognized
5987 as a biv of the outer loop,
5988 causing code to be moved INTO the inner loop. */
5995 /* convert_modes aborts if we try to convert to or from CCmode, so just
5996 exclude that case. It is very unlikely that a condition code value
5997 would be a useful iterator anyways. */
6001 {
6002 /* Possible bug here? Perhaps we don't know the mode of X. */
6006 }
6007 else
6015 /* Similar, since this can be a sign extension. */
6020 ;
6034 location);
6039 }
6040 }
6041 \f
6042 /* A general induction variable (giv) is any quantity that is a linear
6043 function of a basic induction variable,
6044 i.e. giv = biv * mult_val + add_val.
6045 The coefficients can be any loop invariant quantity.
6046 A giv need not be computed directly from the biv;
6047 it can be computed by way of other givs. */
6049 /* Determine whether X computes a giv.
6050 If it does, return a nonzero value
6051 which is the benefit from eliminating the computation of X;
6052 set *SRC_REG to the register of the biv that it is computed from;
6053 set *ADD_VAL and *MULT_VAL to the coefficients,
6054 such that the value of X is biv * mult + add; */
6056 static int
6060 rtx x;
6067 {
6071 /* If this is an invariant, forget it, it isn't a giv. */
6075 /* See if the expression could be a giv and get its form.
6076 Mark our place on the obstack in case we don't find a giv. */
6081 {
6084 }
6087 {
6090 /* Since this is now an invariant and wasn't before, it must be a giv
6091 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6092 with. */
6099 /* This is equivalent to a BIV. */
6106 /* Either (plus (biv) (invar)) or
6107 (plus (mult (biv) (invar_1)) (invar_2)). */
6109 {
6112 }
6113 else
6114 {
6117 }
6122 /* ADD_VAL is zero. */
6130 }
6132 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6133 unless they are CONST_INT). */
6141 else
6144 /* Always return true if this is a giv so it will be detected as such,
6145 even if the benefit is zero or negative. This allows elimination
6146 of bivs that might otherwise not be eliminated. */
6148 }
6149 \f
6150 /* Given an expression, X, try to form it as a linear function of a biv.
6151 We will canonicalize it to be of the form
6152 (plus (mult (BIV) (invar_1))
6153 (invar_2))
6154 with possible degeneracies.
6156 The invariant expressions must each be of a form that can be used as a
6157 machine operand. We surround then with a USE rtx (a hack, but localized
6158 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6159 routine; it is the caller's responsibility to strip them.
6161 If no such canonicalization is possible (i.e., two biv's are used or an
6162 expression that is neither invariant nor a biv or giv), this routine
6163 returns 0.
6165 For a non-zero return, the result will have a code of CONST_INT, USE,
6166 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6168 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6175 static rtx
6178 rtx x;
6180 {
6183 rtx tem;
6185 /* If this is not an integer mode, or if we cannot do arithmetic in this
6186 mode, this can't be a giv. */
6193 {
6200 /* Put constant last, CONST_INT last if both constant. */
6208 /* Handle addition of zero, then addition of an invariant. */
6213 {
6216 /* Adding two invariants must result in an invariant, so enclose
6217 addition operation inside a USE and return it. */
6227 else
6236 /* biv + invar or mult + invar. Return sum. */
6240 /* (a + invar_1) + invar_2. Associate. */
6241 return
6247 arg1)),
6248 benefit);
6252 }
6254 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6255 MULT to reduce cases. */
6261 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6262 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6263 Recurse to associate the second PLUS. */
6268 return
6274 benefit);
6276 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6289 benefit);
6292 /* Handle "a - b" as "a + b * (-1)". */
6298 constm1_rtx)),
6299 benefit);
6307 /* Put constant last, CONST_INT last if both constant. */
6312 /* If second argument is not now constant, not giv. */
6316 /* Handle multiply by 0 or 1. */
6324 {
6326 /* biv * invar. Done. */
6330 /* Product of two constants. */
6334 /* invar * invar is a giv, but attempt to simplify it somehow. */
6340 {
6341 /* (invar_0 * invar_1) * invar_2. Associate. */
6348 arg1)),
6349 benefit);
6350 }
6351 /* Porpagate the MULT expressions to the intermost nodes. */
6353 {
6354 /* (invar_0 + invar_1) * invar_2. Distribute. */
6360 arg1),
6364 arg1)),
6365 benefit);
6366 }
6370 /* (a * invar_1) * invar_2. Associate. */
6376 arg1)),
6377 benefit);
6380 /* (a + invar_1) * invar_2. Distribute. */
6385 arg1),
6388 arg1)),
6389 benefit);
6393 }
6396 /* Shift by constant is multiply by power of two. */
6400 return
6406 benefit);
6409 /* "-a" is "a * (-1)" */
6412 benefit);
6415 /* "~a" is "-a - 1". Silly, but easy. */
6419 const1_rtx),
6420 benefit);
6423 /* Already in proper form for invariant. */
6427 /* If this is a new register, we can't deal with it. */
6431 /* Check for biv or giv. */
6433 {
6437 {
6440 /* Form expression from giv and add benefit. Ensure this giv
6441 can derive another and subtract any needed adjustment if so. */
6453 }
6456 /* If it isn't an induction variable, and it is invariant, we
6457 may be able to simplify things further by looking through
6458 the bits we just moved outside the loop. */
6460 {
6465 {
6466 /* Ok, we found a match. Substitute and simplify. */
6468 /* If we match another movable, we must use that, as
6469 this one is going away. */
6472 benefit);
6474 /* If consec is non-zero, this is a member of a group of
6475 instructions that were moved together. We handle this
6476 case only to the point of seeking to the last insn and
6477 looking for a REG_EQUAL. Fail if we don't find one. */
6479 {
6487 }
6488 else
6489 {
6493 }
6496 {
6497 /* What we are most interested in is pointer
6498 arithmetic on invariants -- only take
6499 patterns we may be able to do something with. */
6505 {
6509 }
6514 {
6516 benefit);
6519 }
6520 }
6522 }
6523 }
6525 }
6527 /* Fall through to general case. */
6529 /* If invariant, return as USE (unless CONST_INT).
6530 Otherwise, not giv. */
6535 {
6544 }
6545 else
6547 }
6548 }
6550 /* This routine folds invariants such that there is only ever one
6551 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6553 static rtx
6556 {
6562 {
6565 }
6568 {
6571 }
6572 else
6573 {
6576 }
6577 }
6579 static rtx
6583 {
6585 {
6589 else
6592 }
6595 else
6598 }
6599 \f
6600 /* Help detect a giv that is calculated by several consecutive insns;
6601 for example,
6602 giv = biv * M
6603 giv = giv + A
6604 The caller has already identified the first insn P as having a giv as dest;
6605 we check that all other insns that set the same register follow
6606 immediately after P, that they alter nothing else,
6607 and that the result of the last is still a giv.
6609 The value is 0 if the reg set in P is not really a giv.
6610 Otherwise, the value is the amount gained by eliminating
6611 all the consecutive insns that compute the value.
6613 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6614 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6616 The coefficients of the ultimate giv value are stored in
6617 *MULT_VAL and *ADD_VAL. */
6619 static int
6624 rtx p;
6625 rtx src_reg;
6626 rtx dest_reg;
6630 {
6634 rtx temp;
6635 rtx set;
6637 /* Indicate that this is a giv so that we can update the value produced in
6638 each insn of the multi-insn sequence.
6640 This induction structure will be used only by the call to
6641 general_induction_var below, so we can allocate it on our stack.
6642 If this is a giv, our caller will replace the induct var entry with
6643 a new induction structure. */
6659 {
6663 /* If libcall, skip to end of call sequence. */
6673 /* Giv created by equivalent expression. */
6677 VOIDmode)))
6679 {
6683 count--;
6687 }
6689 {
6690 /* Allow insns that set something other than this giv to a
6691 constant. Such insns are needed on machines which cannot
6692 include long constants and should not disqualify a giv. */
6701 }
6702 }
6706 }
6707 \f
6708 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6709 represented by G1. If no such expression can be found, or it is clear that
6710 it cannot possibly be a valid address, 0 is returned.
6712 To perform the computation, we note that
6713 G1 = x * v + a and
6714 G2 = y * v + b
6715 where `v' is the biv.
6717 So G2 = (y/b) * G1 + (b - a*y/x).
6719 Note that MULT = y/x.
6721 Update: A and B are now allowed to be additive expressions such that
6722 B contains all variables in A. That is, computing B-A will not require
6723 subtracting variables. */
6725 static rtx
6728 {
6729 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6734 /* If MULT is not 1, we cannot handle A with non-constants, since we
6735 would then be required to subtract multiples of the registers in A.
6736 This is theoretically possible, and may even apply to some Fortran
6737 constructs, but it is a lot of work and we do not attempt it here. */
6742 /* In general these structures are sorted top to bottom (down the PLUS
6743 chain), but not left to right across the PLUS. If B is a higher
6744 order giv than A, we can strip one level and recurse. If A is higher
6745 order, we'll eventually bail out, but won't know that until the end.
6746 If they are the same, we'll strip one level around this loop. */
6749 {
6761 /* We matched: remove one reg completely. */
6764 /* An alternate match. */
6767 /* An alternate match. */
6769 else
6770 {
6771 /* Indicates an extra register in B. Strip one level from B and
6772 recurse, hoping B was the higher order expression. */
6777 }
6778 }
6780 /* Here we are at the last level of A, go through the cases hoping to
6781 get rid of everything but a constant. */
6784 {
6797 }
6799 {
6801 }
6803 {
6804 return simplify_gen_binary (MINUS, GET_MODE (b) != VOIDmode ? GET_MODE (b) : GET_MODE (a), const0_rtx, a);
6805 }
6807 {
6812 else
6814 }
6819 }
6821 rtx
6824 {
6827 /* The value that G1 will be multiplied by must be a constant integer. Also,
6828 the only chance we have of getting a valid address is if b*c/a (see above
6829 for notation) is also an integer. */
6832 {
6837 }
6840 else
6841 {
6842 /* ??? Find out if the one is a multiple of the other? */
6844 }
6848 {
6849 /* Failed. If we've got a multiplication factor between G1 and G2,
6850 scale G1's addend and try again. */
6852 {
6856 {
6857 HOST_WIDE_INT m;
6861 }
6862 else
6863 {
6865 mult);
6866 }
6869 }
6870 }
6874 /* Form simplified final result. */
6879 else
6884 else
6885 {
6888 {
6892 }
6895 }
6896 }
6897 \f
6898 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6899 represented by G1. This indicates that G2 should be combined with G1 and
6900 that G2 can use (either directly or via an address expression) a register
6901 used to represent G1. */
6903 static rtx
6906 {
6909 /* If these givs are identical, they can be combined. We use the results
6910 of express_from because the addends are not in a canonical form, so
6911 rtx_equal_p is a weaker test. */
6912 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6913 combination to be the other way round. */
6916 {
6918 }
6920 /* If G2 can be expressed as a function of G1 and that function is valid
6921 as an address and no more expensive than using a register for G2,
6922 the expression of G2 in terms of G1 can be used. */
6926 /* ??? Looses, especially with -fforce-addr, where *g2->location
6927 will always be a register, and so anything more complicated
6928 gets discarded. */
6929 #if 0
6930 #ifdef ADDRESS_COST
6932 #else
6934 #endif
6935 #endif
6936 )
6937 {
6939 }
6942 }
6943 \f
6944 struct combine_givs_stats
6945 {
6948 };
6950 static int
6954 {
6961 /* Stabilize the sort. */
6965 }
6967 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6968 any other. If so, point SAME to the giv combined with and set NEW_REG to
6969 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6970 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6972 static void
6975 {
6976 /* Additional benefit to add for being combined multiple times. */
6984 /* Count givs, because bl->giv_count is incorrect here. */
6988 giv_count++;
6990 giv_array
7001 {
7003 rtx single_use;
7008 /* If a DEST_REG GIV is used only once, do not allow it to combine
7009 with anything, for in doing so we will gain nothing that cannot
7010 be had by simply letting the GIV with which we would have combined
7011 to be reduced on its own. The losage shows up in particular with
7012 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7013 be seen elsewhere as well. */
7020 /* Add an additional weight for zero addends. */
7025 {
7026 rtx this_combine;
7031 {
7034 }
7035 }
7037 }
7039 /* Iterate, combining until we can't. */
7040 restart:
7044 {
7047 {
7053 }
7055 }
7058 {
7064 /* If it has already been combined, skip. */
7069 {
7072 /* If it has already been combined, skip. */
7074 {
7084 /* ??? The new final_[bg]iv_value code does a much better job
7085 of finding replaceable giv's, and hence this code may no
7086 longer be necessary. */
7090 /* To help optimize the next set of combinations, remove
7091 this giv from the benefits of other potential mates. */
7093 {
7097 }
7103 }
7104 }
7106 /* To help optimize the next set of combinations, remove
7107 this giv from the benefits of other potential mates. */
7109 {
7111 {
7115 }
7119 /* We've finished with this giv, and everything it touched.
7120 Restart the combination so that proper weights for the
7121 rest of the givs are properly taken into account. */
7122 /* ??? Ideally we would compact the arrays at this point, so
7123 as to not cover old ground. But sanely compacting
7124 can_combine is tricky. */
7126 }
7127 }
7129 /* Clean up. */
7132 }
7133 \f
7134 struct recombine_givs_stats
7135 {
7138 };
7140 /* Used below as comparison function for qsort. We want a ascending luid
7141 when scanning the array starting at the end, thus the arguments are
7142 used in reverse. */
7143 static int
7147 {
7154 /* Stabilize the sort. */
7158 }
7160 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7161 look for the start of life of a giv where the start has not been seen
7162 yet to unlock the search for the end of its life.
7163 Only consider givs that belong to BIV.
7164 Return the total number of lifetime ends that have been found. */
7165 static int
7169 {
7177 {
7179 {
7182 {
7190 {
7191 /* If we see a 0 here for end_luid, it means that we have
7192 scanned the entire loop without finding any use at all.
7193 We must not predicate this code on a start_luid match
7194 since that would make the test fail for givs that have
7195 been hoisted out of inner loops. */
7197 {
7200 }
7203 }
7205 }
7207 }
7209 {
7217 {
7222 }
7224 }
7232 }
7236 {
7243 }
7245 }
7247 /* For each giv that has been combined with another, look if
7248 we can combine it with the most recently used one instead.
7249 This tends to shorten giv lifetimes, and helps the next step:
7250 try to derive givs from other givs. */
7251 static void
7256 {
7264 {
7266 giv_count++;
7267 }
7268 giv_array
7272 /* Initialize stats and set up the ix field for each giv in stats to name
7273 the corresponding index into stats. */
7275 {
7276 rtx p;
7282 /* If this giv has been hoisted out of an inner loop, use the luid of
7283 the previous insn. */
7287 i++;
7288 }
7292 /* Set up the ix field for each giv in stats to name
7293 the corresponding index into stats, and
7294 do the actual most-recently-used recombination. */
7296 {
7300 {
7302 rtx new_combine;
7304 /* combine_givs_p actually says if we can make this transformation.
7305 The other tests are here only to avoid keeping a giv alive
7306 that could otherwise be eliminated. */
7312 {
7317 /* No need to update lifetimes / benefits here since we have
7318 already decided what to reduce. */
7321 {
7327 }
7329 }
7331 }
7339 }
7342 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7343 lifetime ends from regscan info. */
7345 {
7350 {
7351 /* Loop unrolling of an inner loop can even create new DEST_REG
7352 givs. */
7353 rtx p;
7359 }
7361 {
7363 {
7366 }
7368 {
7369 rtx p;
7370 /* This insn has been created by loop optimization on an inner
7371 loop. We don't have a proper start_luid that will match
7372 when we see the first set. But we do know that there will
7373 be no use before the set, so we can set end_luid to 0 so that
7374 we'll start looking for the last use right away. */
7379 ends_need_computing++;
7380 }
7381 else
7382 {
7387 /* Find the first insn that sets the giv, so that we can verify
7388 if this giv's lifetime wraps around the loop. We also need
7389 the luid of the first setting insn in order to detect the
7390 last use properly. */
7392 {
7395 count--;
7396 }
7400 {
7402 ends_need_computing++;
7403 }
7404 else
7405 {
7408 {
7410 ends_need_computing++;
7411 }
7412 }
7413 }
7414 }
7415 }
7417 /* If the regscan information was unconclusive for one or more DEST_REG
7418 givs, scan the all insn in the loop to find out lifetime ends. */
7420 {
7424 do
7425 {
7432 }
7434 }
7436 /* Set start_luid back to the last insn that sets the giv. This allows
7437 more combinations. */
7439 {
7445 }
7447 /* Now adjust lifetime ends by taking combined givs into account. */
7449 {
7457 {
7460 /* Use unsigned arithmetic to model loop wrap-around. */
7464 }
7465 }
7469 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7470 same mult_val and non-overlapping lifetime. This reduces register
7471 pressure.
7472 Once we find a DEST_REG giv that is suitable to derive others from,
7473 we set last_giv to this giv, and try to derive as many other DEST_REG
7474 givs from it without joining overlapping lifetimes. If we then
7475 encounter a DEST_REG giv that we can't derive, we set rescan to the
7476 index for this giv (unless rescan is already set).
7477 When we are finished with the current LAST_GIV (i.e. the inner loop
7478 terminates), we start again with rescan, which then becomes the new
7479 LAST_GIV. */
7481 {
7485 {
7486 rtx sum;
7492 {
7493 /* Don't use a giv that's likely to be dead to derive
7494 others - that would be likely to keep that giv alive. */
7496 {
7500 }
7502 }
7503 /* Use unsigned arithmetic to model loop wrap around. */
7508 /* Check that the giv insn we're about to use for deriving
7509 precedes all uses of that giv. Note that initializing the
7510 derived giv would defeat the purpose of reducing register
7511 pressure.
7512 ??? We could arrange to move the insn. */
7516 /* ??? Could handle libcalls, but would need more logic. */
7518 /* We would really like to know if for any giv that v
7519 is combined with, v->insn or any intervening biv increment
7520 dominates that combined giv. However, we
7521 don't have this detailed control flow information.
7522 N.B. since last_giv will be reduced, it is valid
7523 anywhere in the loop, so we don't need to check the
7524 validity of last_giv.
7525 We rely here on the fact that v->always_executed implies that
7526 there is no jump to someplace else in the loop before the
7527 giv insn, and hence any insn that is executed before the
7528 giv insn in the loop will have a lower luid. */
7531 /* Make sure we don't make the add more expensive. ADD_COST
7532 doesn't take different costs of registers and constants into
7533 account, so compare the cost of the actual SET_SRCs. */
7536 /* ??? unroll can't understand anything but reg + const_int
7537 sums. It would be cleaner to fix unroll. */
7544 {
7549 {
7555 }
7556 }
7559 }
7560 }
7562 /* Clean up. */
7565 }
7566 \f
7567 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7569 void
7575 rtx insert_before;
7576 {
7577 rtx seq;
7578 rtx result;
7580 /* Prevent unexpected sharing of these rtx. */
7584 /* Increase the lifetime of any invariants moved further in code. */
7598 /* It is entirely possible that the expansion created lots of new
7599 registers. Iterate over the sequence we just created and
7600 record them all. */
7603 {
7606 {
7610 }
7611 }
7615 }
7616 \f
7617 /* Test whether A * B can be computed without
7618 an actual multiply insn. Value is 1 if so. */
7620 static int
7622 rtx a;
7623 rtx b;
7624 {
7626 rtx tmp;
7631 /* If only one is constant, make it B. */
7635 /* If first constant, both constant, so don't need multiply. */
7639 /* If second not constant, neither is constant, so would need multiply. */
7643 /* One operand is constant, so might not need multiply insn. Generate the
7644 code for the multiply and see if a call or multiply, or long sequence
7645 of insns is generated. */
7654 {
7659 else
7661 {
7670 {
7673 }
7674 }
7675 }
7684 /* Free any storage we obtained in generating this multiply and restore rtl
7685 allocation to its normal obstack. */
7690 }
7691 \f
7692 /* Check to see if loop can be terminated by a "decrement and branch until
7693 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7694 Also try reversing an increment loop to a decrement loop
7695 to see if the optimization can be performed.
7696 Value is nonzero if optimization was performed. */
7698 /* This is useful even if the architecture doesn't have such an insn,
7699 because it might change a loops which increments from 0 to n to a loop
7700 which decrements from n to 0. A loop that decrements to zero is usually
7701 faster than one that increments from zero. */
7703 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7704 such as approx_final_value, biv_total_increment, loop_iterations, and
7705 final_[bg]iv_value. */
7707 static int
7711 {
7713 rtx reg;
7714 rtx jump_label;
7715 rtx final_value;
7716 rtx start_value;
7717 rtx new_add_val;
7718 rtx comparison;
7719 rtx before_comparison;
7720 rtx p;
7721 rtx jump;
7722 rtx first_compare;
7728 /* If last insn is a conditional branch, and the insn before tests a
7729 register value, try to optimize it. Otherwise, we can't do anything. */
7738 /* Try to compute whether the compare/branch at the loop end is one or
7739 two instructions. */
7745 else
7748 {
7749 /* If more than one condition is present to control the loop, then
7750 do not proceed, as this function does not know how to rewrite
7751 loop tests with more than one condition.
7753 Look backwards from the first insn in the last comparison
7754 sequence and see if we've got another comparison sequence. */
7756 rtx jump1;
7760 }
7762 /* Check all of the bivs to see if the compare uses one of them.
7763 Skip biv's set more than once because we can't guarantee that
7764 it will be zero on the last iteration. Also skip if the biv is
7765 used between its update and the test insn. */
7768 {
7773 first_compare))
7775 }
7780 /* Look for the case where the basic induction variable is always
7781 nonnegative, and equals zero on the last iteration.
7782 In this case, add a reg_note REG_NONNEG, which allows the
7783 m68k DBRA instruction to be used. */
7791 {
7792 /* Initial value must be greater than 0,
7793 init_val % -dec_value == 0 to ensure that it equals zero on
7794 the last iteration */
7800 {
7801 /* register always nonnegative, add REG_NOTE to branch */
7809 }
7811 /* If the decrement is 1 and the value was tested as >= 0 before
7812 the loop, then we can safely optimize. */
7814 {
7827 {
7835 }
7836 }
7837 }
7840 {
7841 /* Try to change inc to dec, so can apply above optimization. */
7842 /* Can do this if:
7843 all registers modified are induction variables or invariant,
7844 all memory references have non-overlapping addresses
7845 (obviously true if only one write)
7846 allow 2 insns for the compare/jump at the end of the loop. */
7847 /* Also, we must avoid any instructions which use both the reversed
7848 biv and another biv. Such instructions will fail if the loop is
7849 reversed. We meet this condition by requiring that either
7850 no_use_except_counting is true, or else that there is only
7851 one biv. */
7853 /* 1 if the iteration var is used only to count iterations. */
7855 /* 1 if the loop has no memory store, or it has a single memory store
7856 which is reversible. */
7860 {
7863 /* If there are no givs for this biv, and the only exit is the
7864 fall through at the end of the loop, then
7865 see if perhaps there are no uses except to count. */
7869 {
7874 /* An insn that sets the biv is okay. */
7875 ;
7879 {
7880 /* If either of these insns uses the biv and sets a pseudo
7881 that has more than one usage, then the biv has uses
7882 other than counting since it's used to derive a value
7883 that is used more than one time. */
7888 {
7891 }
7892 }
7894 {
7897 }
7898 }
7899 }
7902 /* No need to worry about MEMs. */
7903 ;
7905 {
7910 /* If the loop has a single store, and the destination address is
7911 invariant, then we can't reverse the loop, because this address
7912 might then have the wrong value at loop exit.
7913 This would work if the source was invariant also, however, in that
7914 case, the insn should have been moved out of the loop. */
7917 {
7920 reversible_mem_store
7921 = (! unknown_address_altered
7922 && ! unknown_constant_address_altered
7927 /* If the store depends on a register that is set after the
7928 store, it depends on the initial value, and is thus not
7929 reversible. */
7931 {
7937 }
7938 }
7939 }
7940 else
7943 /* This code only acts for innermost loops. Also it simplifies
7944 the memory address check by only reversing loops with
7945 zero or one memory access.
7946 Two memory accesses could involve parts of the same array,
7947 and that can't be reversed.
7948 If the biv is used only for counting, than we don't need to worry
7949 about all these things. */
7954 && reversible_mem_store
7959 {
7960 rtx tem;
7962 /* Loop can be reversed. */
7966 /* Now check other conditions:
7968 The increment must be a constant, as must the initial value,
7969 and the comparison code must be LT.
7971 This test can probably be improved since +/- 1 in the constant
7972 can be obtained by changing LT to LE and vice versa; this is
7973 confusing. */
7976 /* for constants, LE gets turned into LT */
7980 {
7991 comparison_const_width
7993 else
7994 comparison_const_width
7998 comparison_sign_mask
8001 /* If the comparison value is not a loop invariant, then we
8002 can not reverse this loop.
8004 ??? If the insns which initialize the comparison value as
8005 a whole compute an invariant result, then we could move
8006 them out of the loop and proceed with loop reversal. */
8014 /* Normalize the initial value if it is an integer and
8015 has no other use except as a counter. This will allow
8016 a few more loops to be reversed. */
8020 {
8022 /* The code below requires comparison_val to be a multiple
8023 of add_val in order to do the loop reversal, so
8024 round up comparison_val to a multiple of add_val.
8025 Since comparison_value is constant, we know that the
8026 current comparison code is LT. */
8028 comparison_val
8030 /* We postpone overflow checks for COMPARISON_VAL here;
8031 even if there is an overflow, we might still be able to
8032 reverse the loop, if converting the loop exit test to
8033 NE is possible. */
8035 }
8037 /* First check if we can do a vanilla loop reversal. */
8039 /* If we have a decrement_and_branch_on_count,
8040 prefer the NE test, since this will allow that
8041 instruction to be generated. Note that we must
8042 use a vanilla loop reversal if the biv is used to
8043 calculate a giv or has a non-counting use. */
8044 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8045 && defined (HAVE_decrement_and_branch_on_count)
8049 #endif
8051 /* Now do postponed overflow checks on COMPARISON_VAL. */
8054 {
8055 /* Register will always be nonnegative, with value
8056 0 on last iteration */
8060 }
8064 {
8067 }
8068 else
8074 /* If the initial value is not zero, or if the comparison
8075 value is not an exact multiple of the increment, then we
8076 can not reverse this loop. */
8079 {
8082 }
8083 else
8084 {
8087 }
8091 /* Reset these in case we normalized the initial value
8092 and comparison value above. */
8095 {
8097 final_value
8099 }
8102 /* Save some info needed to produce the new insns. */
8109 /* Set start_value; if this is not a CONST_INT, we need
8110 to generate a SUB.
8111 Initialize biv to start_value before loop start.
8112 The old initializing insn will be deleted as a
8113 dead store by flow.c. */
8116 {
8119 loop_start);
8120 }
8122 {
8125 enum insn_code icode
8134 start_value
8138 loop_start);
8142 }
8144 {
8146 enum insn_code icode
8154 start_value
8158 loop_start);
8159 }
8160 else
8161 /* We could handle the other cases too, but it'll be
8162 better to have a testcase first. */
8165 /* We may not have a single insn which can increment a reg, so
8166 create a sequence to hold all the insns from expand_inc. */
8175 /* Update biv info to reflect its new status. */
8180 /* Update loop info. */
8189 /* Inc LABEL_NUSES so that delete_insn will
8190 not delete the label. */
8193 /* Emit an insn after the end of the loop to set the biv's
8194 proper exit value if it is used anywhere outside the loop. */
8199 loop_end);
8201 /* Delete compare/branch at end of loop. */
8206 /* Add new compare/branch insn at end of loop. */
8218 ;
8224 {
8226 {
8227 /* Increment of LABEL_NUSES done above. */
8228 /* Register is now always nonnegative,
8229 so add REG_NONNEG note to the branch. */
8232 }
8234 }
8236 /* No insn may reference both the reversed and another biv or it
8237 will fail (see comment near the top of the loop reversal
8238 code).
8239 Earlier on, we have verified that the biv has no use except
8240 counting, or it is the only biv in this function.
8241 However, the code that computes no_use_except_counting does
8242 not verify reg notes. It's possible to have an insn that
8243 references another biv, and has a REG_EQUAL note with an
8244 expression based on the reversed biv. To avoid this case,
8245 remove all REG_EQUAL notes based on the reversed biv
8246 here. */
8249 {
8252 /* If this is a set of a GIV based on the reversed biv, any
8253 REG_EQUAL notes should still be correct. */
8260 {
8265 else
8267 }
8268 }
8270 /* Mark that this biv has been reversed. Each giv which depends
8271 on this biv, and which is also live past the end of the loop
8272 will have to be fixed up. */
8277 {
8281 else
8283 }
8286 }
8287 }
8288 }
8291 }
8292 \f
8293 /* Verify whether the biv BL appears to be eliminable,
8294 based on the insns in the loop that refer to it.
8296 If ELIMINATE_P is non-zero, actually do the elimination.
8298 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8299 determine whether invariant insns should be placed inside or at the
8300 start of the loop. */
8302 static int
8308 {
8312 rtx p;
8314 /* Scan all insns in the loop, stopping if we find one that uses the
8315 biv in a way that we cannot eliminate. */
8318 {
8322 /* If this is a libcall that sets a giv, skip ahead to its end. */
8324 {
8328 {
8333 {
8340 }
8341 }
8342 }
8347 {
8353 }
8354 }
8357 {
8362 }
8365 }
8366 \f
8367 /* INSN and REFERENCE are instructions in the same insn chain.
8368 Return non-zero if INSN is first. */
8370 int
8373 {
8377 {
8378 /* Start with test for not first so that INSN == REFERENCE yields not
8379 first. */
8385 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8386 previous insn, hence the <= comparison below does not work if
8387 P is a note. */
8398 }
8399 }
8401 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8402 the offset that we have to take into account due to auto-increment /
8403 div derivation is zero. */
8404 static int
8407 rtx insn;
8408 {
8409 /* If the giv V had the auto-inc address optimization applied
8410 to it, and INSN occurs between the giv insn and the biv
8411 insn, then we'd have to adjust the value used here.
8412 This is rare, so we don't bother to make this possible. */
8420 /* If the giv V was derived from another giv, and INSN does
8421 not occur between the giv insn and the biv insn, then we'd
8422 have to adjust the value used here. This is rare, so we don't
8423 bother to make this possible. */
8437 }
8439 /* If BL appears in X (part of the pattern of INSN), see if we can
8440 eliminate its use. If so, return 1. If not, return 0.
8442 If BIV does not appear in X, return 1.
8444 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8445 where extra insns should be added. Depending on how many items have been
8446 moved out of the loop, it will either be before INSN or at the start of
8447 the loop. */
8449 static int
8455 rtx where;
8456 {
8462 #ifdef HAVE_cc0
8464 #endif
8470 {
8472 /* If we haven't already been able to do something with this BIV,
8473 we can't eliminate it. */
8479 /* If this sets the BIV, it is not a problem. */
8483 /* If this is an insn that defines a giv, it is also ok because
8484 it will go away when the giv is reduced. */
8489 #ifdef HAVE_cc0
8491 {
8492 /* Can replace with any giv that was reduced and
8493 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8494 Require a constant for MULT_VAL, so we know it's nonzero.
8495 ??? We disable this optimization to avoid potential
8496 overflows. */
8504 {
8511 /* If the giv has the opposite direction of change,
8512 then reverse the comparison. */
8516 else
8519 /* We can probably test that giv's reduced reg. */
8522 }
8524 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8525 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8526 Require a constant for MULT_VAL, so we know it's nonzero.
8527 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8528 overflow problem. */
8540 {
8547 /* If the giv has the opposite direction of change,
8548 then reverse the comparison. */
8552 else
8556 /* Replace biv with the giv's reduced register. */
8561 /* Insn doesn't support that constant or invariant. Copy it
8562 into a register (it will be a loop invariant.) */
8566 where);
8568 /* Substitute the new register for its invariant value in
8569 the compare expression. */
8573 }
8574 }
8575 #endif
8582 /* See if either argument is the biv. */
8587 else
8591 {
8592 /* First try to replace with any giv that has constant positive
8593 mult_val and constant add_val. We might be able to support
8594 negative mult_val, but it seems complex to do it in general. */
8606 {
8613 /* Replace biv with the giv's reduced reg. */
8616 /* If all constants are actually constant integers and
8617 the derived constant can be directly placed in the COMPARE,
8618 do so. */
8622 {
8627 }
8628 else
8629 {
8630 /* Otherwise, load it into a register. */
8634 }
8637 }
8639 /* Look for giv with positive constant mult_val and nonconst add_val.
8640 Insert insns to calculate new compare value.
8641 ??? Turn this off due to possible overflow. */
8649 {
8650 rtx tem;
8660 /* Replace biv with giv's reduced register. */
8664 /* Compute value to compare against. */
8666 /* Use it in this insn. */
8670 }
8671 }
8673 {
8675 {
8676 /* Look for giv with constant positive mult_val and nonconst
8677 add_val. Insert insns to compute new compare value.
8678 ??? Turn this off due to possible overflow. */
8685 {
8686 rtx tem;
8696 /* Replace biv with giv's reduced register. */
8700 /* Compute value to compare against. */
8706 }
8707 }
8709 /* This code has problems. Basically, you can't know when
8710 seeing if we will eliminate BL, whether a particular giv
8711 of ARG will be reduced. If it isn't going to be reduced,
8712 we can't eliminate BL. We can try forcing it to be reduced,
8713 but that can generate poor code.
8715 The problem is that the benefit of reducing TV, below should
8716 be increased if BL can actually be eliminated, but this means
8717 we might have to do a topological sort of the order in which
8718 we try to process biv. It doesn't seem worthwhile to do
8719 this sort of thing now. */
8721 #if 0
8722 /* Otherwise the reg compared with had better be a biv. */
8727 /* Look for a pair of givs, one for each biv,
8728 with identical coefficients. */
8730 {
8741 {
8748 /* Replace biv with its giv's reduced reg. */
8750 /* Replace other operand with the other giv's
8751 reduced reg. */
8754 }
8755 }
8756 #endif
8757 }
8759 /* If we get here, the biv can't be eliminated. */
8763 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8764 biv is used in it, since it will be replaced. */
8772 }
8774 /* See if any subexpression fails elimination. */
8777 {
8779 {
8792 }
8793 }
8796 }
8797 \f
8798 /* Return nonzero if the last use of REG
8799 is in an insn following INSN in the same basic block. */
8801 static int
8803 rtx reg;
8804 rtx insn;
8805 {
8806 rtx n;
8810 {
8813 }
8815 }
8816 \f
8817 /* Called via `note_stores' to record the initial value of a biv. Here we
8818 just record the location of the set and process it later. */
8820 static void
8822 rtx dest;
8823 rtx set;
8825 {
8835 /* If this is the first set found, record it. */
8837 {
8840 }
8841 }
8842 \f
8843 /* If any of the registers in X are "old" and currently have a last use earlier
8844 than INSN, update them to have a last use of INSN. Their actual last use
8845 will be the previous insn but it will not have a valid uid_luid so we can't
8846 use it. */
8848 static void
8850 rtx x;
8851 rtx insn;
8852 {
8853 /* Check for the case where INSN does not have a valid luid. In this case,
8854 there is no need to modify the regno_last_uid, as this can only happen
8855 when code is inserted after the loop_end to set a pseudo's final value,
8856 and hence this insn will never be the last use of x. */
8861 else
8862 {
8866 {
8872 }
8873 }
8874 }
8875 \f
8876 /* Given an insn INSN and condition COND, return the condition in a
8877 canonical form to simplify testing by callers. Specifically:
8879 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8880 (2) Both operands will be machine operands; (cc0) will have been replaced.
8881 (3) If an operand is a constant, it will be the second operand.
8882 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8883 for GE, GEU, and LEU.
8885 If the condition cannot be understood, or is an inequality floating-point
8886 comparison which needs to be reversed, 0 will be returned.
8888 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8890 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8891 insn used in locating the condition was found. If a replacement test
8892 of the condition is desired, it should be placed in front of that
8893 insn and we will be sure that the inputs are still valid.
8895 If WANT_REG is non-zero, we wish the condition to be relative to that
8896 register, if possible. Therefore, do not canonicalize the condition
8897 further. */
8899 rtx
8901 rtx insn;
8902 rtx cond;
8905 rtx want_reg;
8906 {
8909 rtx set;
8910 rtx tem;
8922 {
8925 }
8930 /* If we are comparing a register with zero, see if the register is set
8931 in the previous insn to a COMPARE or a comparison operation. Perform
8932 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8933 in cse.c */
8938 {
8939 /* Set non-zero when we find something of interest. */
8942 #ifdef HAVE_cc0
8943 /* If comparison with cc0, import actual comparison from compare
8944 insn. */
8946 {
8957 }
8958 #endif
8960 /* If this is a COMPARE, pick up the two things being compared. */
8962 {
8966 }
8970 /* Go back to the previous insn. Stop if it is not an INSN. We also
8971 stop if it isn't a single set or if it has a REG_INC note because
8972 we don't want to bother dealing with it. */
8980 /* If this is setting OP0, get what it sets it to if it looks
8981 relevant. */
8983 {
8986 /* ??? We may not combine comparisons done in a CCmode with
8987 comparisons not done in a CCmode. This is to aid targets
8988 like Alpha that have an IEEE compliant EQ instruction, and
8989 a non-IEEE compliant BEQ instruction. The use of CCmode is
8990 actually artificial, simply to prevent the combination, but
8991 should not affect other platforms.
8993 However, we must allow VOIDmode comparisons to match either
8994 CCmode or non-CCmode comparison, because some ports have
8995 modeless comparisons inside branch patterns.
8997 ??? This mode check should perhaps look more like the mode check
8998 in simplify_comparison in combine. */
9006 && (STORE_FLAG_VALUE
9009 #ifdef FLOAT_STORE_FLAG_VALUE
9012 && (REAL_VALUE_NEGATIVE
9014 #endif
9015 ))
9026 && (STORE_FLAG_VALUE
9029 #ifdef FLOAT_STORE_FLAG_VALUE
9032 && (REAL_VALUE_NEGATIVE
9034 #endif
9035 ))
9041 {
9042 /* We might have reversed a LT to get a GE here. But this wasn't
9043 actually the comparison of data, so we don't flag that we
9044 have had to reverse the condition. */
9048 }
9049 else
9051 }
9054 /* If this sets OP0, but not directly, we have to give up. */
9058 {
9062 {
9068 }
9073 }
9074 }
9076 /* If constant is first, put it last. */
9080 /* If OP0 is the result of a comparison, we weren't able to find what
9081 was really being compared, so fail. */
9085 /* Canonicalize any ordered comparison with integers involving equality
9086 if we can do computations in the relevant mode and we do not
9087 overflow. */
9092 {
9095 unsigned HOST_WIDE_INT max_val
9099 {
9105 /* When cross-compiling, const_val might be sign-extended from
9106 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9126 }
9127 }
9129 /* If this was floating-point and we reversed anything other than an
9130 EQ or NE or (UN)ORDERED, return zero. */
9132 && did_reverse_condition
9134 && ! flag_fast_math
9138 #ifdef HAVE_cc0
9139 /* Never return CC0; return zero instead. */
9142 #endif
9145 }
9147 /* Given a jump insn JUMP, return the condition that will cause it to branch
9148 to its JUMP_LABEL. If the condition cannot be understood, or is an
9149 inequality floating-point comparison which needs to be reversed, 0 will
9150 be returned.
9152 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9153 insn used in locating the condition was found. If a replacement test
9154 of the condition is desired, it should be placed in front of that
9155 insn and we will be sure that the inputs are still valid. */
9157 rtx
9159 rtx jump;
9161 {
9162 rtx cond;
9164 rtx set;
9166 /* If this is not a standard conditional jump, we can't parse it. */
9174 /* If this branches to JUMP_LABEL when the condition is false, reverse
9175 the condition. */
9176 reverse
9181 }
9183 /* Similar to above routine, except that we also put an invariant last
9184 unless both operands are invariants. */
9186 rtx
9189 rtx x;
9190 {
9200 }
9202 /* Scan the function and determine whether it has indirect (computed) jumps.
9204 This is taken mostly from flow.c; similar code exists elsewhere
9205 in the compiler. It may be useful to put this into rtlanal.c. */
9206 static int
9208 rtx start;
9209 {
9210 rtx insn;
9217 }
9219 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9220 documentation for LOOP_MEMS for the definition of `appropriate'.
9221 This function is called from prescan_loop via for_each_rtx. */
9223 static int
9227 {
9235 {
9240 /* We're not interested in MEMs that are only clobbered. */
9244 /* We're not interested in the MEM associated with a
9245 CONST_DOUBLE, so there's no need to traverse into this. */
9249 /* We're not interested in any MEMs that only appear in notes. */
9253 /* This is not a MEM. */
9255 }
9257 /* See if we've already seen this MEM. */
9260 {
9262 /* The modes of the two memory accesses are different. If
9263 this happens, something tricky is going on, and we just
9264 don't optimize accesses to this MEM. */
9268 }
9270 /* Resize the array, if necessary. */
9272 {
9275 else
9281 }
9283 /* Actually insert the MEM. */
9285 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9286 because we can't put it in a register. We still store it in the
9287 table, though, so that if we see the same address later, but in a
9288 non-BLK mode, we'll not think we can optimize it at that point. */
9294 }
9296 /* Like load_mems, but also ensures that SET_IN_LOOP,
9297 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9298 values after load_mems. */
9300 static void
9304 {
9309 /* Recalculate set_in_loop and friends since load_mems may have
9310 created new registers. */
9312 {
9320 {
9321 /* Grow all the arrays. */
9326 }
9327 /* Clear the arrays */
9336 {
9339 }
9341 #ifdef AVOID_CCMODE_COPIES
9342 /* Don't try to move insns which set CC registers if we should not
9343 create CCmode register copies. */
9347 #endif
9349 /* Set n_times_set for the new registers. */
9353 }
9354 }
9356 /* Move MEMs into registers for the duration of the loop. */
9358 static void
9361 {
9364 rtx p;
9367 /* Nonzero if the next instruction may never be executed. */
9374 /* Find start of the extended basic block that enters the loop. */
9378 ;
9382 /* Build table of mems that get set to constant values before the
9383 loop. */
9387 /* Check to see if it's possible that some instructions in the
9388 loop are never executed. */
9392 {
9396 /* If we enter the loop in the middle, and scan
9397 around to the beginning, don't set maybe_never
9398 for that. This must be an unconditional jump,
9399 otherwise the code at the top of the loop might
9400 never be executed. Unconditional jumps are
9401 followed a by barrier then loop end. */
9406 {
9408 /* Something complicated. */
9410 else
9411 /* If there are any more instructions in the loop, they
9412 might not be reached. */
9414 }
9417 }
9419 /* Actually move the MEMs. */
9421 {
9422 regset_head load_copies;
9423 regset_head store_copies;
9425 rtx reg;
9427 rtx mem_list_entry;
9431 /* There's no telling whether or not MEM is modified. */
9434 /* Go through the MEMs written to in the loop to see if this
9435 one is aliased by one of them. */
9438 {
9443 {
9444 /* MEM is indeed aliased by this store. */
9447 }
9449 }
9455 /* If this MEM is written to, we must be sure that there
9456 are no reads from another MEM that aliases this one. */
9458 {
9462 {
9466 VOIDmode,
9468 rtx_varies_p))
9469 {
9470 /* It's not safe to hoist loop_mems[i] out of
9471 the loop because writes to it might not be
9472 seen by reads from loop_mems[j]. */
9475 }
9476 }
9477 }
9480 /* We can't access the MEM outside the loop; it might
9481 cause a trap that wouldn't have happened otherwise. */
9485 /* We thought we were going to lift this MEM out of the
9486 loop, but later discovered that we could not. */
9492 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9493 order to keep scan_loop from moving stores to this MEM
9494 out of the loop just because this REG is neither a
9495 user-variable nor used in the loop test. */
9500 /* Now, replace all references to the MEM with the
9501 corresponding pesudos. */
9506 {
9507 rtx_and_int ri;
9510 {
9511 rtx set;
9515 /* See if this copies the mem into a register that isn't
9516 modified afterwards. We'll try to do copy propagation
9517 a little further on. */
9519 /* @@@ This test is _way_ too conservative. */
9520 && ! maybe_never
9528 /* See if this copies the mem from a register that isn't
9529 modified afterwards. We'll try to remove the
9530 redundant copy later on by doing a little register
9531 renaming and copy propagation. This will help
9532 to untangle things for the BIV detection code. */
9534 && ! maybe_never
9542 /* Replace the memory reference with the shadow register. */
9546 }
9551 }
9554 /* We couldn't replace all occurrences of the MEM. */
9556 else
9557 {
9558 /* Load the memory immediately before LOOP->START, which is
9559 the NOTE_LOOP_BEG. */
9561 rtx set;
9567 {
9571 {
9575 /* Extending hard register lifetimes cuases crash
9576 on SRC targets. Doing so on non-SRC is
9577 probably also not good idea, since we most
9578 probably have pseudoregister equivalence as
9579 well. */
9582 }
9583 /* Use the constant equivalence if that is cheap enough. */
9589 {
9592 }
9594 /* If best_equiv is nonzero, we know that MEM is set to a
9595 constant or register before the loop. We will use this
9596 knowledge to initialize the shadow register with that
9597 constant or reg rather than by loading from MEM. */
9600 }
9609 {
9611 {
9612 /* We must compute the former
9613 right-after-the-end label before we insert
9614 the new one. */
9618 }
9620 /* Store the memory immediately after END, which is
9621 the NOTE_LOOP_END. */
9624 }
9627 {
9632 }
9634 /* Attempt a bit of copy propagation. This helps untangle the
9635 data flow, and enables {basic,general}_induction_var to find
9636 more bivs/givs. */
9637 EXECUTE_IF_SET_IN_REG_SET
9639 {
9641 });
9644 EXECUTE_IF_SET_IN_REG_SET
9646 {
9648 });
9650 }
9651 }
9654 {
9655 /* Now, we need to replace all references to the previous exit
9656 label with the new one. */
9657 rtx_pair rr;
9662 {
9665 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9666 field. This is not handled by for_each_rtx because it doesn't
9667 handle unprinted ('0') fields. We need to update JUMP_LABEL
9668 because the immediately following unroll pass will use it.
9669 replace_label would not work anyways, because that only handles
9670 LABEL_REFs. */
9673 }
9674 }
9677 }
9679 /* For communication between note_reg_stored and its caller. */
9680 struct note_reg_stored_arg
9681 {
9683 rtx reg;
9684 };
9686 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9687 is equal to ARG. */
9688 static void
9692 {
9696 }
9698 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9699 There must be exactly one insn that sets this pseudo; it will be
9700 deleted if all replacements succeed and we can prove that the register
9701 is not used after the loop. */
9703 static void
9706 rtx replacement;
9708 {
9709 /* This is the reg that we are copying from. */
9712 rtx insn;
9713 /* These help keep track of whether we replaced all uses of the reg. */
9720 {
9721 rtx set;
9723 /* Only substitute within one extended basic block from the initializing
9724 insn. */
9731 /* Is this the initializing insn? */
9736 {
9743 }
9745 /* Only substitute after seeing the initializing insn. */
9747 {
9758 /* Stop replacing when REPLACEMENT is modified. */
9764 }
9765 }
9769 {
9773 {
9779 }
9782 }
9783 }
9786 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9787 loop LOOP if the order of the sets of these registers can be
9788 swapped. There must be exactly one insn within the loop that sets
9789 this pseudo followed immediately by a move insn that sets
9790 REPLACEMENT with REGNO. */
9791 static void
9794 rtx replacement;
9796 {
9797 rtx insn;
9798 rtx set;
9806 {
9807 /* Search for the insn that copies REGNO to NEW_REGNO? */
9815 }
9818 {
9819 rtx prev_insn;
9820 rtx prev_set;
9822 /* Some DEF-USE info would come in handy here to make this
9823 function more general. For now, just check the previous insn
9824 which is the most likely candidate for setting REGNO. */
9832 {
9833 /* We have:
9834 (set (reg regno) (expr))
9835 (set (reg new_regno) (reg regno))
9837 so try converting this to:
9838 (set (reg new_regno) (expr))
9839 (set (reg regno) (reg new_regno))
9841 The former construct is often generated when a global
9842 variable used for an induction variable is shadowed by a
9843 register (NEW_REGNO). The latter construct improves the
9844 chances of GIV replacement and BIV elimination. */
9854 {
9861 /* Update first use of REGNO. */
9865 /* Now perform copy propagation to hopefully
9866 remove all uses of REGNO within the loop. */
9868 }
9869 }
9870 }
9871 }
9874 /* Replace MEM with its associated pseudo register. This function is
9875 called from load_mems via for_each_rtx. DATA is actually an
9876 rtx_and_int * describing the instruction currently being scanned
9877 and the MEM we are currently replacing. */
9879 static int
9883 {
9885 rtx insn;
9893 {
9898 /* We're not interested in the MEM associated with a
9899 CONST_DOUBLE, so there's no need to traverse into one. */
9903 /* This is not a MEM. */
9905 }
9911 /* This is not the MEM we are currently replacing. */
9916 /* Actually replace the MEM. */
9920 }
9922 /* Replace one register with another. Called through for_each_rtx; PX points
9923 to the rtx being scanned. DATA is actually an array of three rtx's; the
9924 first one is the one to be replaced, and the second one the replacement.
9925 The third one is the current insn. */
9927 static int
9931 {
9942 }
9944 /* Replace occurrences of the old exit label for the loop with the new
9945 one. DATA is an rtx_pair containing the old and new labels,
9946 respectively. */
9948 static int
9952 {
9971 }
9972 \f
9973 #define LOOP_BLOCK_NUM_1(INSN) \
9974 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9976 /* The notes do not have an assigned block, so look at the next insn. */
9977 #define LOOP_BLOCK_NUM(INSN) \
9978 ((INSN) ? (GET_CODE (INSN) == NOTE \
9979 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9980 : LOOP_BLOCK_NUM_1 (INSN)) \
9981 : -1)
9983 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9989 {
9990 rtx label;
9995 /* Print diagnostics to compare our concept of a loop with
9996 what the loop notes say. */
10011 {
10031 {
10034 {
10037 }
10038 }
10041 /* This can happen when a marked loop appears as two nested loops,
10042 say from while (a || b) {}. The inner loop won't match
10043 the loop markers but the outer one will. */
10046 }
10047 }
10050 /* Call this function from the debugger to dump LOOP. */
10052 void
10055 {
10057 }