1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
,
42 unsigned HOST_WIDE_INT
, rtx
);
43 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
, rtx
);
45 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
, rtx
, int);
49 static rtx
mask_rtx (enum machine_mode
, int, int, int);
50 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
51 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int);
53 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
54 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
55 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
57 /* Test whether a value is zero of a power of two. */
58 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
60 /* Nonzero means divides or modulus operations are relatively cheap for
61 powers of two, so don't use branches; emit the operation instead.
62 Usually, this will mean that the MD file will emit non-branch
65 static bool sdiv_pow2_cheap
[NUM_MACHINE_MODES
];
66 static bool smod_pow2_cheap
[NUM_MACHINE_MODES
];
68 #ifndef SLOW_UNALIGNED_ACCESS
69 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
72 /* For compilers that support multiple targets with different word sizes,
73 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
74 is the H8/300(H) compiler. */
76 #ifndef MAX_BITS_PER_WORD
77 #define MAX_BITS_PER_WORD BITS_PER_WORD
80 /* Reduce conditional compilation elsewhere. */
83 #define CODE_FOR_insv CODE_FOR_nothing
84 #define gen_insv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extv CODE_FOR_nothing
89 #define gen_extv(a,b,c,d) NULL_RTX
93 #define CODE_FOR_extzv CODE_FOR_nothing
94 #define gen_extzv(a,b,c,d) NULL_RTX
97 /* Cost of various pieces of RTL. Note that some of these are indexed by
98 shift count and some by mode. */
100 static int add_cost
[NUM_MACHINE_MODES
];
101 static int neg_cost
[NUM_MACHINE_MODES
];
102 static int shift_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
103 static int shiftadd_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
104 static int shiftsub_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
105 static int mul_cost
[NUM_MACHINE_MODES
];
106 static int div_cost
[NUM_MACHINE_MODES
];
107 static int mul_widen_cost
[NUM_MACHINE_MODES
];
108 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
115 struct rtx_def reg
; rtunion reg_fld
[2];
116 struct rtx_def plus
; rtunion plus_fld1
;
118 struct rtx_def udiv
; rtunion udiv_fld1
;
119 struct rtx_def mult
; rtunion mult_fld1
;
120 struct rtx_def div
; rtunion div_fld1
;
121 struct rtx_def mod
; rtunion mod_fld1
;
123 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
124 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
125 struct rtx_def wide_trunc
;
126 struct rtx_def shift
; rtunion shift_fld1
;
127 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
128 struct rtx_def shift_add
; rtunion shift_add_fld1
;
129 struct rtx_def shift_sub
; rtunion shift_sub_fld1
;
132 rtx pow2
[MAX_BITS_PER_WORD
];
133 rtx cint
[MAX_BITS_PER_WORD
];
135 enum machine_mode mode
, wider_mode
;
137 zero_cost
= rtx_cost (const0_rtx
, 0);
139 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
141 pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
142 cint
[m
] = GEN_INT (m
);
145 memset (&all
, 0, sizeof all
);
147 PUT_CODE (&all
.reg
, REG
);
148 REGNO (&all
.reg
) = 10000;
150 PUT_CODE (&all
.plus
, PLUS
);
151 XEXP (&all
.plus
, 0) = &all
.reg
;
152 XEXP (&all
.plus
, 1) = &all
.reg
;
154 PUT_CODE (&all
.neg
, NEG
);
155 XEXP (&all
.neg
, 0) = &all
.reg
;
157 PUT_CODE (&all
.udiv
, UDIV
);
158 XEXP (&all
.udiv
, 0) = &all
.reg
;
159 XEXP (&all
.udiv
, 1) = &all
.reg
;
161 PUT_CODE (&all
.mult
, MULT
);
162 XEXP (&all
.mult
, 0) = &all
.reg
;
163 XEXP (&all
.mult
, 1) = &all
.reg
;
165 PUT_CODE (&all
.div
, DIV
);
166 XEXP (&all
.div
, 0) = &all
.reg
;
167 XEXP (&all
.div
, 1) = 32 < MAX_BITS_PER_WORD
? cint
[32] : GEN_INT (32);
169 PUT_CODE (&all
.mod
, MOD
);
170 XEXP (&all
.mod
, 0) = &all
.reg
;
171 XEXP (&all
.mod
, 1) = XEXP (&all
.div
, 1);
173 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
174 XEXP (&all
.zext
, 0) = &all
.reg
;
176 PUT_CODE (&all
.wide_mult
, MULT
);
177 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
178 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
180 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
181 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
183 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
184 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
186 PUT_CODE (&all
.shift
, ASHIFT
);
187 XEXP (&all
.shift
, 0) = &all
.reg
;
189 PUT_CODE (&all
.shift_mult
, MULT
);
190 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
192 PUT_CODE (&all
.shift_add
, PLUS
);
193 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
194 XEXP (&all
.shift_add
, 1) = &all
.reg
;
196 PUT_CODE (&all
.shift_sub
, MINUS
);
197 XEXP (&all
.shift_sub
, 0) = &all
.shift_mult
;
198 XEXP (&all
.shift_sub
, 1) = &all
.reg
;
200 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
202 mode
= GET_MODE_WIDER_MODE (mode
))
204 PUT_MODE (&all
.reg
, mode
);
205 PUT_MODE (&all
.plus
, mode
);
206 PUT_MODE (&all
.neg
, mode
);
207 PUT_MODE (&all
.udiv
, mode
);
208 PUT_MODE (&all
.mult
, mode
);
209 PUT_MODE (&all
.div
, mode
);
210 PUT_MODE (&all
.mod
, mode
);
211 PUT_MODE (&all
.wide_trunc
, mode
);
212 PUT_MODE (&all
.shift
, mode
);
213 PUT_MODE (&all
.shift_mult
, mode
);
214 PUT_MODE (&all
.shift_add
, mode
);
215 PUT_MODE (&all
.shift_sub
, mode
);
217 add_cost
[mode
] = rtx_cost (&all
.plus
, SET
);
218 neg_cost
[mode
] = rtx_cost (&all
.neg
, SET
);
219 div_cost
[mode
] = rtx_cost (&all
.udiv
, SET
);
220 mul_cost
[mode
] = rtx_cost (&all
.mult
, SET
);
222 sdiv_pow2_cheap
[mode
] = (rtx_cost (&all
.div
, SET
) <= 2 * add_cost
[mode
]);
223 smod_pow2_cheap
[mode
] = (rtx_cost (&all
.mod
, SET
) <= 4 * add_cost
[mode
]);
225 wider_mode
= GET_MODE_WIDER_MODE (mode
);
226 if (wider_mode
!= VOIDmode
)
228 PUT_MODE (&all
.zext
, wider_mode
);
229 PUT_MODE (&all
.wide_mult
, wider_mode
);
230 PUT_MODE (&all
.wide_lshr
, wider_mode
);
231 XEXP (&all
.wide_lshr
, 1) = GEN_INT (GET_MODE_BITSIZE (mode
));
233 mul_widen_cost
[wider_mode
] = rtx_cost (&all
.wide_mult
, SET
);
234 mul_highpart_cost
[mode
] = rtx_cost (&all
.wide_trunc
, SET
);
237 shift_cost
[mode
][0] = 0;
238 shiftadd_cost
[mode
][0] = shiftsub_cost
[mode
][0] = add_cost
[mode
];
240 n
= MIN (MAX_BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
241 for (m
= 1; m
< n
; m
++)
243 XEXP (&all
.shift
, 1) = cint
[m
];
244 XEXP (&all
.shift_mult
, 1) = pow2
[m
];
246 shift_cost
[mode
][m
] = rtx_cost (&all
.shift
, SET
);
247 shiftadd_cost
[mode
][m
] = rtx_cost (&all
.shift_add
, SET
);
248 shiftsub_cost
[mode
][m
] = rtx_cost (&all
.shift_sub
, SET
);
253 /* Return an rtx representing minus the value of X.
254 MODE is the intended mode of the result,
255 useful if X is a CONST_INT. */
258 negate_rtx (enum machine_mode mode
, rtx x
)
260 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
263 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
268 /* Report on the availability of insv/extv/extzv and the desired mode
269 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
270 is false; else the mode of the specified operand. If OPNO is -1,
271 all the caller cares about is whether the insn is available. */
273 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
275 const struct insn_data
*data
;
282 data
= &insn_data
[CODE_FOR_insv
];
285 return MAX_MACHINE_MODE
;
290 data
= &insn_data
[CODE_FOR_extv
];
293 return MAX_MACHINE_MODE
;
298 data
= &insn_data
[CODE_FOR_extzv
];
301 return MAX_MACHINE_MODE
;
310 /* Everyone who uses this function used to follow it with
311 if (result == VOIDmode) result = word_mode; */
312 if (data
->operand
[opno
].mode
== VOIDmode
)
314 return data
->operand
[opno
].mode
;
318 /* Generate code to store value from rtx VALUE
319 into a bit-field within structure STR_RTX
320 containing BITSIZE bits starting at bit BITNUM.
321 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
322 ALIGN is the alignment that STR_RTX is known to have.
323 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
325 /* ??? Note that there are two different ideas here for how
326 to determine the size to count bits within, for a register.
327 One is BITS_PER_WORD, and the other is the size of operand 3
330 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
331 else, we use the mode of operand 3. */
334 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
335 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
339 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
340 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
341 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
346 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
348 while (GET_CODE (op0
) == SUBREG
)
350 /* The following line once was done only if WORDS_BIG_ENDIAN,
351 but I think that is a mistake. WORDS_BIG_ENDIAN is
352 meaningful at a much higher level; when structures are copied
353 between memory and regs, the higher-numbered regs
354 always get higher addresses. */
355 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
356 /* We used to adjust BITPOS here, but now we do the whole adjustment
357 right after the loop. */
358 op0
= SUBREG_REG (op0
);
361 /* Use vec_set patterns for inserting parts of vectors whenever
363 if (VECTOR_MODE_P (GET_MODE (op0
))
365 && (vec_set_optab
->handlers
[GET_MODE (op0
)].insn_code
367 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
368 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
369 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
371 enum machine_mode outermode
= GET_MODE (op0
);
372 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
373 int icode
= (int) vec_set_optab
->handlers
[outermode
].insn_code
;
374 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
375 rtx rtxpos
= GEN_INT (pos
);
379 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
380 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
381 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
385 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
386 src
= copy_to_mode_reg (mode1
, src
);
388 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
389 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
391 /* We could handle this, but we should always be called with a pseudo
392 for our targets and all insns should take them as outputs. */
393 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
394 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
395 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
396 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
409 int old_generating_concat_p
= generating_concat_p
;
410 generating_concat_p
= 0;
411 value
= force_not_mem (value
);
412 generating_concat_p
= old_generating_concat_p
;
415 /* If the target is a register, overwriting the entire object, or storing
416 a full-word or multi-word field can be done with just a SUBREG.
418 If the target is memory, storing any naturally aligned field can be
419 done with a simple store. For targets that support fast unaligned
420 memory, any naturally sized, unit aligned field can be done directly. */
422 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
423 + (offset
* UNITS_PER_WORD
);
426 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
428 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
429 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
430 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
431 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
432 || (offset
* BITS_PER_UNIT
% bitsize
== 0
433 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
435 if (GET_MODE (op0
) != fieldmode
)
438 op0
= adjust_address (op0
, fieldmode
, offset
);
440 op0
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
443 emit_move_insn (op0
, value
);
447 /* Make sure we are playing with integral modes. Pun with subregs
448 if we aren't. This must come after the entire register case above,
449 since that case is valid for any mode. The following cases are only
450 valid for integral modes. */
452 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
453 if (imode
!= GET_MODE (op0
))
456 op0
= adjust_address (op0
, imode
, 0);
459 gcc_assert (imode
!= BLKmode
);
460 op0
= gen_lowpart (imode
, op0
);
465 /* We may be accessing data outside the field, which means
466 we can alias adjacent data. */
469 op0
= shallow_copy_rtx (op0
);
470 set_mem_alias_set (op0
, 0);
471 set_mem_expr (op0
, 0);
474 /* If OP0 is a register, BITPOS must count within a word.
475 But as we have it, it counts within whatever size OP0 now has.
476 On a bigendian machine, these are not the same, so convert. */
479 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
480 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
482 /* Storing an lsb-aligned field in a register
483 can be done with a movestrict instruction. */
486 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
487 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
488 && (movstrict_optab
->handlers
[fieldmode
].insn_code
489 != CODE_FOR_nothing
))
491 int icode
= movstrict_optab
->handlers
[fieldmode
].insn_code
;
493 /* Get appropriate low part of the value being stored. */
494 if (GET_CODE (value
) == CONST_INT
|| REG_P (value
))
495 value
= gen_lowpart (fieldmode
, value
);
496 else if (!(GET_CODE (value
) == SYMBOL_REF
497 || GET_CODE (value
) == LABEL_REF
498 || GET_CODE (value
) == CONST
))
499 value
= convert_to_mode (fieldmode
, value
, 0);
501 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
502 value
= copy_to_mode_reg (fieldmode
, value
);
504 if (GET_CODE (op0
) == SUBREG
)
506 /* Else we've got some float mode source being extracted into
507 a different float mode destination -- this combination of
508 subregs results in Severe Tire Damage. */
509 gcc_assert (GET_MODE (SUBREG_REG (op0
)) == fieldmode
510 || GET_MODE_CLASS (fieldmode
) == MODE_INT
511 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
512 op0
= SUBREG_REG (op0
);
515 emit_insn (GEN_FCN (icode
)
516 (gen_rtx_SUBREG (fieldmode
, op0
,
517 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
518 + (offset
* UNITS_PER_WORD
)),
524 /* Handle fields bigger than a word. */
526 if (bitsize
> BITS_PER_WORD
)
528 /* Here we transfer the words of the field
529 in the order least significant first.
530 This is because the most significant word is the one which may
532 However, only do that if the value is not BLKmode. */
534 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
535 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
538 /* This is the mode we must force value to, so that there will be enough
539 subwords to extract. Note that fieldmode will often (always?) be
540 VOIDmode, because that is what store_field uses to indicate that this
541 is a bit field, but passing VOIDmode to operand_subword_force will
542 result in an abort. */
543 fieldmode
= GET_MODE (value
);
544 if (fieldmode
== VOIDmode
)
545 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
547 for (i
= 0; i
< nwords
; i
++)
549 /* If I is 0, use the low-order word in both field and target;
550 if I is 1, use the next to lowest word; and so on. */
551 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
552 unsigned int bit_offset
= (backwards
553 ? MAX ((int) bitsize
- ((int) i
+ 1)
556 : (int) i
* BITS_PER_WORD
);
558 store_bit_field (op0
, MIN (BITS_PER_WORD
,
559 bitsize
- i
* BITS_PER_WORD
),
560 bitnum
+ bit_offset
, word_mode
,
561 operand_subword_force (value
, wordnum
, fieldmode
));
566 /* From here on we can assume that the field to be stored in is
567 a full-word (whatever type that is), since it is shorter than a word. */
569 /* OFFSET is the number of words or bytes (UNIT says which)
570 from STR_RTX to the first word or byte containing part of the field. */
575 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
579 /* Since this is a destination (lvalue), we can't copy it to a
580 pseudo. We can trivially remove a SUBREG that does not
581 change the size of the operand. Such a SUBREG may have been
582 added above. Otherwise, abort. */
583 gcc_assert (GET_CODE (op0
) == SUBREG
584 && (GET_MODE_SIZE (GET_MODE (op0
))
585 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))));
586 op0
= SUBREG_REG (op0
);
588 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
589 op0
, (offset
* UNITS_PER_WORD
));
594 /* If VALUE has a floating-point or complex mode, access it as an
595 integer of the corresponding size. This can occur on a machine
596 with 64 bit registers that uses SFmode for float. It can also
597 occur for unaligned float or complex fields. */
599 if (GET_MODE (value
) != VOIDmode
600 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
601 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
603 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
604 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
607 /* Now OFFSET is nonzero only if OP0 is memory
608 and is therefore always measured in bytes. */
611 && GET_MODE (value
) != BLKmode
612 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
613 /* Ensure insv's size is wide enough for this field. */
614 && (GET_MODE_BITSIZE (op_mode
) >= bitsize
)
615 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
616 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
618 int xbitpos
= bitpos
;
621 rtx last
= get_last_insn ();
623 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
624 int save_volatile_ok
= volatile_ok
;
628 /* If this machine's insv can only insert into a register, copy OP0
629 into a register and save it back later. */
630 /* This used to check flag_force_mem, but that was a serious
631 de-optimization now that flag_force_mem is enabled by -O2. */
633 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
637 enum machine_mode bestmode
;
639 /* Get the mode to use for inserting into this field. If OP0 is
640 BLKmode, get the smallest mode consistent with the alignment. If
641 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
642 mode. Otherwise, use the smallest mode containing the field. */
644 if (GET_MODE (op0
) == BLKmode
645 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
647 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
648 MEM_VOLATILE_P (op0
));
650 bestmode
= GET_MODE (op0
);
652 if (bestmode
== VOIDmode
653 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
654 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
657 /* Adjust address to point to the containing unit of that mode.
658 Compute offset as multiple of this unit, counting in bytes. */
659 unit
= GET_MODE_BITSIZE (bestmode
);
660 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
661 bitpos
= bitnum
% unit
;
662 op0
= adjust_address (op0
, bestmode
, offset
);
664 /* Fetch that unit, store the bitfield in it, then store
666 tempreg
= copy_to_reg (op0
);
667 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, orig_value
);
668 emit_move_insn (op0
, tempreg
);
671 volatile_ok
= save_volatile_ok
;
673 /* Add OFFSET into OP0's address. */
675 xop0
= adjust_address (xop0
, byte_mode
, offset
);
677 /* If xop0 is a register, we need it in MAXMODE
678 to make it acceptable to the format of insv. */
679 if (GET_CODE (xop0
) == SUBREG
)
680 /* We can't just change the mode, because this might clobber op0,
681 and we will need the original value of op0 if insv fails. */
682 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
683 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
684 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
686 /* On big-endian machines, we count bits from the most significant.
687 If the bit field insn does not, we must invert. */
689 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
690 xbitpos
= unit
- bitsize
- xbitpos
;
692 /* We have been counting XBITPOS within UNIT.
693 Count instead within the size of the register. */
694 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
695 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
697 unit
= GET_MODE_BITSIZE (maxmode
);
699 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
701 if (GET_MODE (value
) != maxmode
)
703 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
705 /* Optimization: Don't bother really extending VALUE
706 if it has all the bits we will actually use. However,
707 if we must narrow it, be sure we do it correctly. */
709 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
713 tmp
= simplify_subreg (maxmode
, value1
, GET_MODE (value
), 0);
715 tmp
= simplify_gen_subreg (maxmode
,
716 force_reg (GET_MODE (value
),
718 GET_MODE (value
), 0);
722 value1
= gen_lowpart (maxmode
, value1
);
724 else if (GET_CODE (value
) == CONST_INT
)
725 value1
= gen_int_mode (INTVAL (value
), maxmode
);
727 /* Parse phase is supposed to make VALUE's data type
728 match that of the component reference, which is a type
729 at least as wide as the field; so VALUE should have
730 a mode that corresponds to that type. */
731 gcc_assert (CONSTANT_P (value
));
734 /* If this machine's insv insists on a register,
735 get VALUE1 into a register. */
736 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
738 value1
= force_reg (maxmode
, value1
);
740 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
745 delete_insns_since (last
);
746 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
751 /* Insv is not available; store using shifts and boolean ops. */
752 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
756 /* Use shifts and boolean operations to store VALUE
757 into a bit field of width BITSIZE
758 in a memory location specified by OP0 except offset by OFFSET bytes.
759 (OFFSET must be 0 if OP0 is a register.)
760 The field starts at position BITPOS within the byte.
761 (If OP0 is a register, it may be a full word or a narrower mode,
762 but BITPOS still counts within a full word,
763 which is significant on bigendian machines.) */
766 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT offset
,
767 unsigned HOST_WIDE_INT bitsize
,
768 unsigned HOST_WIDE_INT bitpos
, rtx value
)
770 enum machine_mode mode
;
771 unsigned int total_bits
= BITS_PER_WORD
;
776 /* There is a case not handled here:
777 a structure with a known alignment of just a halfword
778 and a field split across two aligned halfwords within the structure.
779 Or likewise a structure with a known alignment of just a byte
780 and a field split across two bytes.
781 Such cases are not supposed to be able to occur. */
783 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
785 gcc_assert (!offset
);
786 /* Special treatment for a bit field split across two registers. */
787 if (bitsize
+ bitpos
> BITS_PER_WORD
)
789 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
795 /* Get the proper mode to use for this field. We want a mode that
796 includes the entire field. If such a mode would be larger than
797 a word, we won't be doing the extraction the normal way.
798 We don't want a mode bigger than the destination. */
800 mode
= GET_MODE (op0
);
801 if (GET_MODE_BITSIZE (mode
) == 0
802 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
804 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
805 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
807 if (mode
== VOIDmode
)
809 /* The only way this should occur is if the field spans word
811 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
816 total_bits
= GET_MODE_BITSIZE (mode
);
818 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
819 be in the range 0 to total_bits-1, and put any excess bytes in
821 if (bitpos
>= total_bits
)
823 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
824 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
828 /* Get ref to an aligned byte, halfword, or word containing the field.
829 Adjust BITPOS to be position within a word,
830 and OFFSET to be the offset of that word.
831 Then alter OP0 to refer to that word. */
832 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
833 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
834 op0
= adjust_address (op0
, mode
, offset
);
837 mode
= GET_MODE (op0
);
839 /* Now MODE is either some integral mode for a MEM as OP0,
840 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
841 The bit field is contained entirely within OP0.
842 BITPOS is the starting bit number within OP0.
843 (OP0's mode may actually be narrower than MODE.) */
845 if (BYTES_BIG_ENDIAN
)
846 /* BITPOS is the distance between our msb
847 and that of the containing datum.
848 Convert it to the distance from the lsb. */
849 bitpos
= total_bits
- bitsize
- bitpos
;
851 /* Now BITPOS is always the distance between our lsb
854 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
855 we must first convert its mode to MODE. */
857 if (GET_CODE (value
) == CONST_INT
)
859 HOST_WIDE_INT v
= INTVAL (value
);
861 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
862 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
866 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
867 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
868 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
871 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
875 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
876 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
878 if (GET_MODE (value
) != mode
)
880 if ((REG_P (value
) || GET_CODE (value
) == SUBREG
)
881 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
882 value
= gen_lowpart (mode
, value
);
884 value
= convert_to_mode (mode
, value
, 1);
888 value
= expand_binop (mode
, and_optab
, value
,
889 mask_rtx (mode
, 0, bitsize
, 0),
890 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
892 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
893 build_int_cst (NULL_TREE
, bitpos
), NULL_RTX
, 1);
896 /* Now clear the chosen bits in OP0,
897 except that if VALUE is -1 we need not bother. */
899 subtarget
= (REG_P (op0
) || ! flag_force_mem
) ? op0
: 0;
903 temp
= expand_binop (mode
, and_optab
, op0
,
904 mask_rtx (mode
, bitpos
, bitsize
, 1),
905 subtarget
, 1, OPTAB_LIB_WIDEN
);
911 /* Now logical-or VALUE into OP0, unless it is zero. */
914 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
915 subtarget
, 1, OPTAB_LIB_WIDEN
);
917 emit_move_insn (op0
, temp
);
920 /* Store a bit field that is split across multiple accessible memory objects.
922 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
923 BITSIZE is the field width; BITPOS the position of its first bit
925 VALUE is the value to store.
927 This does not yet handle fields wider than BITS_PER_WORD. */
930 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
931 unsigned HOST_WIDE_INT bitpos
, rtx value
)
934 unsigned int bitsdone
= 0;
936 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
938 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
939 unit
= BITS_PER_WORD
;
941 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
943 /* If VALUE is a constant other than a CONST_INT, get it into a register in
944 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
945 that VALUE might be a floating-point constant. */
946 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
948 rtx word
= gen_lowpart_common (word_mode
, value
);
950 if (word
&& (value
!= word
))
953 value
= gen_lowpart_common (word_mode
,
954 force_reg (GET_MODE (value
) != VOIDmode
956 : word_mode
, value
));
959 while (bitsdone
< bitsize
)
961 unsigned HOST_WIDE_INT thissize
;
963 unsigned HOST_WIDE_INT thispos
;
964 unsigned HOST_WIDE_INT offset
;
966 offset
= (bitpos
+ bitsdone
) / unit
;
967 thispos
= (bitpos
+ bitsdone
) % unit
;
969 /* THISSIZE must not overrun a word boundary. Otherwise,
970 store_fixed_bit_field will call us again, and we will mutually
972 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
973 thissize
= MIN (thissize
, unit
- thispos
);
975 if (BYTES_BIG_ENDIAN
)
979 /* We must do an endian conversion exactly the same way as it is
980 done in extract_bit_field, so that the two calls to
981 extract_fixed_bit_field will have comparable arguments. */
982 if (!MEM_P (value
) || GET_MODE (value
) == BLKmode
)
983 total_bits
= BITS_PER_WORD
;
985 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
987 /* Fetch successively less significant portions. */
988 if (GET_CODE (value
) == CONST_INT
)
989 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
990 >> (bitsize
- bitsdone
- thissize
))
991 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
993 /* The args are chosen so that the last part includes the
994 lsb. Give extract_bit_field the value it needs (with
995 endianness compensation) to fetch the piece we want. */
996 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
997 total_bits
- bitsize
+ bitsdone
,
1002 /* Fetch successively more significant portions. */
1003 if (GET_CODE (value
) == CONST_INT
)
1004 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1006 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1008 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1009 bitsdone
, NULL_RTX
, 1);
1012 /* If OP0 is a register, then handle OFFSET here.
1014 When handling multiword bitfields, extract_bit_field may pass
1015 down a word_mode SUBREG of a larger REG for a bitfield that actually
1016 crosses a word boundary. Thus, for a SUBREG, we must find
1017 the current word starting from the base register. */
1018 if (GET_CODE (op0
) == SUBREG
)
1020 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1021 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1022 GET_MODE (SUBREG_REG (op0
)));
1025 else if (REG_P (op0
))
1027 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1033 /* OFFSET is in UNITs, and UNIT is in bits.
1034 store_fixed_bit_field wants offset in bytes. */
1035 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
1037 bitsdone
+= thissize
;
1041 /* Generate code to extract a byte-field from STR_RTX
1042 containing BITSIZE bits, starting at BITNUM,
1043 and put it in TARGET if possible (if TARGET is nonzero).
1044 Regardless of TARGET, we return the rtx for where the value is placed.
1046 STR_RTX is the structure containing the byte (a REG or MEM).
1047 UNSIGNEDP is nonzero if this is an unsigned bit field.
1048 MODE is the natural mode of the field value once extracted.
1049 TMODE is the mode the caller would like the value to have;
1050 but the value may be returned with type MODE instead.
1052 TOTAL_SIZE is the size in bytes of the containing structure,
1055 If a TARGET is specified and we can store in it at no extra cost,
1056 we do so, and return TARGET.
1057 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1058 if they are equally easy. */
1061 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1062 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1063 enum machine_mode mode
, enum machine_mode tmode
)
1066 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1067 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
1068 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
1070 rtx spec_target
= target
;
1071 rtx spec_target_subreg
= 0;
1072 enum machine_mode int_mode
;
1073 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1074 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1075 enum machine_mode mode1
;
1078 if (tmode
== VOIDmode
)
1081 while (GET_CODE (op0
) == SUBREG
)
1083 bitpos
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1086 offset
+= (bitpos
/ unit
);
1089 op0
= SUBREG_REG (op0
);
1093 && mode
== GET_MODE (op0
)
1095 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1097 /* We're trying to extract a full register from itself. */
1101 /* Use vec_extract patterns for extracting parts of vectors whenever
1103 if (VECTOR_MODE_P (GET_MODE (op0
))
1105 && (vec_extract_optab
->handlers
[GET_MODE (op0
)].insn_code
1106 != CODE_FOR_nothing
)
1107 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1108 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1110 enum machine_mode outermode
= GET_MODE (op0
);
1111 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1112 int icode
= (int) vec_extract_optab
->handlers
[outermode
].insn_code
;
1113 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1114 rtx rtxpos
= GEN_INT (pos
);
1116 rtx dest
= NULL
, pat
, seq
;
1117 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
1118 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
1119 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
1121 if (innermode
== tmode
|| innermode
== mode
)
1125 dest
= gen_reg_rtx (innermode
);
1129 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
))
1130 dest
= copy_to_mode_reg (mode0
, dest
);
1132 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
1133 src
= copy_to_mode_reg (mode1
, src
);
1135 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1136 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
1138 /* We could handle this, but we should always be called with a pseudo
1139 for our targets and all insns should take them as outputs. */
1140 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
1141 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
1142 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
1144 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
1155 /* Make sure we are playing with integral modes. Pun with subregs
1158 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1159 if (imode
!= GET_MODE (op0
))
1161 op0
= gen_lowpart (imode
, op0
);
1163 /* If we got a SUBREG, force it into a register since we aren't going
1164 to be able to do another SUBREG on it. */
1165 if (GET_CODE (op0
) == SUBREG
)
1166 op0
= force_reg (imode
, op0
);
1170 /* We may be accessing data outside the field, which means
1171 we can alias adjacent data. */
1174 op0
= shallow_copy_rtx (op0
);
1175 set_mem_alias_set (op0
, 0);
1176 set_mem_expr (op0
, 0);
1179 /* Extraction of a full-word or multi-word value from a structure
1180 in a register or aligned memory can be done with just a SUBREG.
1181 A subword value in the least significant part of a register
1182 can also be extracted with a SUBREG. For this, we need the
1183 byte offset of the value in op0. */
1185 byte_offset
= bitpos
/ BITS_PER_UNIT
+ offset
* UNITS_PER_WORD
;
1187 /* If OP0 is a register, BITPOS must count within a word.
1188 But as we have it, it counts within whatever size OP0 now has.
1189 On a bigendian machine, these are not the same, so convert. */
1190 if (BYTES_BIG_ENDIAN
1192 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1193 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1195 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1196 If that's wrong, the solution is to test for it and set TARGET to 0
1199 /* Only scalar integer modes can be converted via subregs. There is an
1200 additional problem for FP modes here in that they can have a precision
1201 which is different from the size. mode_for_size uses precision, but
1202 we want a mode based on the size, so we must avoid calling it for FP
1204 mode1
= (SCALAR_INT_MODE_P (tmode
)
1205 ? mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0)
1208 if (((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1209 && bitpos
% BITS_PER_WORD
== 0)
1210 || (mode1
!= BLKmode
1211 /* ??? The big endian test here is wrong. This is correct
1212 if the value is in a register, and if mode_for_size is not
1213 the same mode as op0. This causes us to get unnecessarily
1214 inefficient code from the Thumb port when -mbig-endian. */
1215 && (BYTES_BIG_ENDIAN
1216 ? bitpos
+ bitsize
== BITS_PER_WORD
1219 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1220 GET_MODE_BITSIZE (GET_MODE (op0
)))
1221 && GET_MODE_SIZE (mode1
) != 0
1222 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1224 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1225 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1226 && MEM_ALIGN (op0
) % bitsize
== 0)))))
1228 if (mode1
!= GET_MODE (op0
))
1231 op0
= adjust_address (op0
, mode1
, offset
);
1234 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1237 goto no_subreg_mode_swap
;
1242 return convert_to_mode (tmode
, op0
, unsignedp
);
1245 no_subreg_mode_swap
:
1247 /* Handle fields bigger than a word. */
1249 if (bitsize
> BITS_PER_WORD
)
1251 /* Here we transfer the words of the field
1252 in the order least significant first.
1253 This is because the most significant word is the one which may
1254 be less than full. */
1256 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1259 if (target
== 0 || !REG_P (target
))
1260 target
= gen_reg_rtx (mode
);
1262 /* Indicate for flow that the entire target reg is being set. */
1263 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1265 for (i
= 0; i
< nwords
; i
++)
1267 /* If I is 0, use the low-order word in both field and target;
1268 if I is 1, use the next to lowest word; and so on. */
1269 /* Word number in TARGET to use. */
1270 unsigned int wordnum
1272 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1274 /* Offset from start of field in OP0. */
1275 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1276 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1277 * (int) BITS_PER_WORD
))
1278 : (int) i
* BITS_PER_WORD
);
1279 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1281 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1282 bitsize
- i
* BITS_PER_WORD
),
1283 bitnum
+ bit_offset
, 1, target_part
, mode
,
1286 gcc_assert (target_part
);
1288 if (result_part
!= target_part
)
1289 emit_move_insn (target_part
, result_part
);
1294 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1295 need to be zero'd out. */
1296 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1298 unsigned int i
, total_words
;
1300 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1301 for (i
= nwords
; i
< total_words
; i
++)
1303 (operand_subword (target
,
1304 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1311 /* Signed bit field: sign-extend with two arithmetic shifts. */
1312 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1313 build_int_cst (NULL_TREE
,
1314 GET_MODE_BITSIZE (mode
) - bitsize
),
1316 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1317 build_int_cst (NULL_TREE
,
1318 GET_MODE_BITSIZE (mode
) - bitsize
),
1322 /* From here on we know the desired field is smaller than a word. */
1324 /* Check if there is a correspondingly-sized integer field, so we can
1325 safely extract it as one size of integer, if necessary; then
1326 truncate or extend to the size that is wanted; then use SUBREGs or
1327 convert_to_mode to get one of the modes we really wanted. */
1329 int_mode
= int_mode_for_mode (tmode
);
1330 if (int_mode
== BLKmode
)
1331 int_mode
= int_mode_for_mode (mode
);
1332 /* Should probably push op0 out to memory and then do a load. */
1333 gcc_assert (int_mode
!= BLKmode
);
1335 /* OFFSET is the number of words or bytes (UNIT says which)
1336 from STR_RTX to the first word or byte containing part of the field. */
1340 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1343 op0
= copy_to_reg (op0
);
1344 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1345 op0
, (offset
* UNITS_PER_WORD
));
1350 /* Now OFFSET is nonzero only for memory operands. */
1355 && (GET_MODE_BITSIZE (extzv_mode
) >= bitsize
)
1356 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1357 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1359 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1360 rtx bitsize_rtx
, bitpos_rtx
;
1361 rtx last
= get_last_insn ();
1363 rtx xtarget
= target
;
1364 rtx xspec_target
= spec_target
;
1365 rtx xspec_target_subreg
= spec_target_subreg
;
1367 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1371 int save_volatile_ok
= volatile_ok
;
1374 /* Is the memory operand acceptable? */
1375 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1376 (xop0
, GET_MODE (xop0
))))
1378 /* No, load into a reg and extract from there. */
1379 enum machine_mode bestmode
;
1381 /* Get the mode to use for inserting into this field. If
1382 OP0 is BLKmode, get the smallest mode consistent with the
1383 alignment. If OP0 is a non-BLKmode object that is no
1384 wider than MAXMODE, use its mode. Otherwise, use the
1385 smallest mode containing the field. */
1387 if (GET_MODE (xop0
) == BLKmode
1388 || (GET_MODE_SIZE (GET_MODE (op0
))
1389 > GET_MODE_SIZE (maxmode
)))
1390 bestmode
= get_best_mode (bitsize
, bitnum
,
1391 MEM_ALIGN (xop0
), maxmode
,
1392 MEM_VOLATILE_P (xop0
));
1394 bestmode
= GET_MODE (xop0
);
1396 if (bestmode
== VOIDmode
1397 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1398 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1401 /* Compute offset as multiple of this unit,
1402 counting in bytes. */
1403 unit
= GET_MODE_BITSIZE (bestmode
);
1404 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1405 xbitpos
= bitnum
% unit
;
1406 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1408 /* Fetch it to a register in that size. */
1409 xop0
= force_reg (bestmode
, xop0
);
1411 /* XBITPOS counts within UNIT, which is what is expected. */
1414 /* Get ref to first byte containing part of the field. */
1415 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1417 volatile_ok
= save_volatile_ok
;
1420 /* If op0 is a register, we need it in MAXMODE (which is usually
1421 SImode). to make it acceptable to the format of extzv. */
1422 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1424 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1425 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1427 /* On big-endian machines, we count bits from the most significant.
1428 If the bit field insn does not, we must invert. */
1429 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1430 xbitpos
= unit
- bitsize
- xbitpos
;
1432 /* Now convert from counting within UNIT to counting in MAXMODE. */
1433 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1434 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1436 unit
= GET_MODE_BITSIZE (maxmode
);
1439 || (flag_force_mem
&& MEM_P (xtarget
)))
1440 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1442 if (GET_MODE (xtarget
) != maxmode
)
1444 if (REG_P (xtarget
))
1446 int wider
= (GET_MODE_SIZE (maxmode
)
1447 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1448 xtarget
= gen_lowpart (maxmode
, xtarget
);
1450 xspec_target_subreg
= xtarget
;
1453 xtarget
= gen_reg_rtx (maxmode
);
1456 /* If this machine's extzv insists on a register target,
1457 make sure we have one. */
1458 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1459 (xtarget
, maxmode
)))
1460 xtarget
= gen_reg_rtx (maxmode
);
1462 bitsize_rtx
= GEN_INT (bitsize
);
1463 bitpos_rtx
= GEN_INT (xbitpos
);
1465 pat
= gen_extzv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1470 spec_target
= xspec_target
;
1471 spec_target_subreg
= xspec_target_subreg
;
1475 delete_insns_since (last
);
1476 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1482 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1488 && (GET_MODE_BITSIZE (extv_mode
) >= bitsize
)
1489 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1490 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1492 int xbitpos
= bitpos
, xoffset
= offset
;
1493 rtx bitsize_rtx
, bitpos_rtx
;
1494 rtx last
= get_last_insn ();
1495 rtx xop0
= op0
, xtarget
= target
;
1496 rtx xspec_target
= spec_target
;
1497 rtx xspec_target_subreg
= spec_target_subreg
;
1499 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1503 /* Is the memory operand acceptable? */
1504 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1505 (xop0
, GET_MODE (xop0
))))
1507 /* No, load into a reg and extract from there. */
1508 enum machine_mode bestmode
;
1510 /* Get the mode to use for inserting into this field. If
1511 OP0 is BLKmode, get the smallest mode consistent with the
1512 alignment. If OP0 is a non-BLKmode object that is no
1513 wider than MAXMODE, use its mode. Otherwise, use the
1514 smallest mode containing the field. */
1516 if (GET_MODE (xop0
) == BLKmode
1517 || (GET_MODE_SIZE (GET_MODE (op0
))
1518 > GET_MODE_SIZE (maxmode
)))
1519 bestmode
= get_best_mode (bitsize
, bitnum
,
1520 MEM_ALIGN (xop0
), maxmode
,
1521 MEM_VOLATILE_P (xop0
));
1523 bestmode
= GET_MODE (xop0
);
1525 if (bestmode
== VOIDmode
1526 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1527 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1530 /* Compute offset as multiple of this unit,
1531 counting in bytes. */
1532 unit
= GET_MODE_BITSIZE (bestmode
);
1533 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1534 xbitpos
= bitnum
% unit
;
1535 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1537 /* Fetch it to a register in that size. */
1538 xop0
= force_reg (bestmode
, xop0
);
1540 /* XBITPOS counts within UNIT, which is what is expected. */
1543 /* Get ref to first byte containing part of the field. */
1544 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1547 /* If op0 is a register, we need it in MAXMODE (which is usually
1548 SImode) to make it acceptable to the format of extv. */
1549 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1551 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1552 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1554 /* On big-endian machines, we count bits from the most significant.
1555 If the bit field insn does not, we must invert. */
1556 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1557 xbitpos
= unit
- bitsize
- xbitpos
;
1559 /* XBITPOS counts within a size of UNIT.
1560 Adjust to count within a size of MAXMODE. */
1561 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1562 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1564 unit
= GET_MODE_BITSIZE (maxmode
);
1567 || (flag_force_mem
&& MEM_P (xtarget
)))
1568 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1570 if (GET_MODE (xtarget
) != maxmode
)
1572 if (REG_P (xtarget
))
1574 int wider
= (GET_MODE_SIZE (maxmode
)
1575 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1576 xtarget
= gen_lowpart (maxmode
, xtarget
);
1578 xspec_target_subreg
= xtarget
;
1581 xtarget
= gen_reg_rtx (maxmode
);
1584 /* If this machine's extv insists on a register target,
1585 make sure we have one. */
1586 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1587 (xtarget
, maxmode
)))
1588 xtarget
= gen_reg_rtx (maxmode
);
1590 bitsize_rtx
= GEN_INT (bitsize
);
1591 bitpos_rtx
= GEN_INT (xbitpos
);
1593 pat
= gen_extv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1598 spec_target
= xspec_target
;
1599 spec_target_subreg
= xspec_target_subreg
;
1603 delete_insns_since (last
);
1604 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1610 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1613 if (target
== spec_target
)
1615 if (target
== spec_target_subreg
)
1617 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1619 /* If the target mode is not a scalar integral, first convert to the
1620 integer mode of that size and then access it as a floating-point
1621 value via a SUBREG. */
1622 if (!SCALAR_INT_MODE_P (tmode
))
1624 enum machine_mode smode
1625 = mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1626 target
= convert_to_mode (smode
, target
, unsignedp
);
1627 target
= force_reg (smode
, target
);
1628 return gen_lowpart (tmode
, target
);
1631 return convert_to_mode (tmode
, target
, unsignedp
);
1636 /* Extract a bit field using shifts and boolean operations
1637 Returns an rtx to represent the value.
1638 OP0 addresses a register (word) or memory (byte).
1639 BITPOS says which bit within the word or byte the bit field starts in.
1640 OFFSET says how many bytes farther the bit field starts;
1641 it is 0 if OP0 is a register.
1642 BITSIZE says how many bits long the bit field is.
1643 (If OP0 is a register, it may be narrower than a full word,
1644 but BITPOS still counts within a full word,
1645 which is significant on bigendian machines.)
1647 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1648 If TARGET is nonzero, attempts to store the value there
1649 and return TARGET, but this is not guaranteed.
1650 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1653 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1654 unsigned HOST_WIDE_INT offset
,
1655 unsigned HOST_WIDE_INT bitsize
,
1656 unsigned HOST_WIDE_INT bitpos
, rtx target
,
1659 unsigned int total_bits
= BITS_PER_WORD
;
1660 enum machine_mode mode
;
1662 if (GET_CODE (op0
) == SUBREG
|| REG_P (op0
))
1664 /* Special treatment for a bit field split across two registers. */
1665 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1666 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1670 /* Get the proper mode to use for this field. We want a mode that
1671 includes the entire field. If such a mode would be larger than
1672 a word, we won't be doing the extraction the normal way. */
1674 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1675 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1677 if (mode
== VOIDmode
)
1678 /* The only way this should occur is if the field spans word
1680 return extract_split_bit_field (op0
, bitsize
,
1681 bitpos
+ offset
* BITS_PER_UNIT
,
1684 total_bits
= GET_MODE_BITSIZE (mode
);
1686 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1687 be in the range 0 to total_bits-1, and put any excess bytes in
1689 if (bitpos
>= total_bits
)
1691 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1692 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1696 /* Get ref to an aligned byte, halfword, or word containing the field.
1697 Adjust BITPOS to be position within a word,
1698 and OFFSET to be the offset of that word.
1699 Then alter OP0 to refer to that word. */
1700 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1701 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1702 op0
= adjust_address (op0
, mode
, offset
);
1705 mode
= GET_MODE (op0
);
1707 if (BYTES_BIG_ENDIAN
)
1708 /* BITPOS is the distance between our msb and that of OP0.
1709 Convert it to the distance from the lsb. */
1710 bitpos
= total_bits
- bitsize
- bitpos
;
1712 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1713 We have reduced the big-endian case to the little-endian case. */
1719 /* If the field does not already start at the lsb,
1720 shift it so it does. */
1721 tree amount
= build_int_cst (NULL_TREE
, bitpos
);
1722 /* Maybe propagate the target for the shift. */
1723 /* But not if we will return it--could confuse integrate.c. */
1724 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1725 if (tmode
!= mode
) subtarget
= 0;
1726 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1728 /* Convert the value to the desired mode. */
1730 op0
= convert_to_mode (tmode
, op0
, 1);
1732 /* Unless the msb of the field used to be the msb when we shifted,
1733 mask out the upper bits. */
1735 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1736 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1737 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1738 target
, 1, OPTAB_LIB_WIDEN
);
1742 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1743 then arithmetic-shift its lsb to the lsb of the word. */
1744 op0
= force_reg (mode
, op0
);
1748 /* Find the narrowest integer mode that contains the field. */
1750 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1751 mode
= GET_MODE_WIDER_MODE (mode
))
1752 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1754 op0
= convert_to_mode (mode
, op0
, 0);
1758 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1761 = build_int_cst (NULL_TREE
,
1762 GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
));
1763 /* Maybe propagate the target for the shift. */
1764 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1765 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1768 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1769 build_int_cst (NULL_TREE
,
1770 GET_MODE_BITSIZE (mode
) - bitsize
),
1774 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1775 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1776 complement of that if COMPLEMENT. The mask is truncated if
1777 necessary to the width of mode MODE. The mask is zero-extended if
1778 BITSIZE+BITPOS is too small for MODE. */
1781 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1783 HOST_WIDE_INT masklow
, maskhigh
;
1787 else if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1788 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1792 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1793 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1794 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1796 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1799 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1803 else if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1804 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1805 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1811 maskhigh
= ~maskhigh
;
1815 return immed_double_const (masklow
, maskhigh
, mode
);
1818 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1819 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1822 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1824 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1825 HOST_WIDE_INT low
, high
;
1827 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1828 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1830 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1833 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1838 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1841 return immed_double_const (low
, high
, mode
);
1844 /* Extract a bit field from a memory by forcing the alignment of the
1845 memory. This efficient only if the field spans at least 4 boundaries.
1848 BITSIZE is the field width; BITPOS is the position of the first bit.
1849 UNSIGNEDP is true if the result should be zero-extended. */
1852 extract_force_align_mem_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1853 unsigned HOST_WIDE_INT bitpos
,
1856 enum machine_mode mode
, dmode
;
1857 unsigned int m_bitsize
, m_size
;
1858 unsigned int sign_shift_up
, sign_shift_dn
;
1859 rtx base
, a1
, a2
, v1
, v2
, comb
, shift
, result
, start
;
1861 /* Choose a mode that will fit BITSIZE. */
1862 mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
1863 m_size
= GET_MODE_SIZE (mode
);
1864 m_bitsize
= GET_MODE_BITSIZE (mode
);
1866 /* Choose a mode twice as wide. Fail if no such mode exists. */
1867 dmode
= mode_for_size (m_bitsize
* 2, MODE_INT
, false);
1868 if (dmode
== BLKmode
)
1871 do_pending_stack_adjust ();
1872 start
= get_last_insn ();
1874 /* At the end, we'll need an additional shift to deal with sign/zero
1875 extension. By default this will be a left+right shift of the
1876 appropriate size. But we may be able to eliminate one of them. */
1877 sign_shift_up
= sign_shift_dn
= m_bitsize
- bitsize
;
1879 if (STRICT_ALIGNMENT
)
1881 base
= plus_constant (XEXP (op0
, 0), bitpos
/ BITS_PER_UNIT
);
1882 bitpos
%= BITS_PER_UNIT
;
1884 /* We load two values to be concatenate. There's an edge condition
1885 that bears notice -- an aligned value at the end of a page can
1886 only load one value lest we segfault. So the two values we load
1887 are at "base & -size" and "(base + size - 1) & -size". If base
1888 is unaligned, the addresses will be aligned and sequential; if
1889 base is aligned, the addresses will both be equal to base. */
1891 a1
= expand_simple_binop (Pmode
, AND
, force_operand (base
, NULL
),
1892 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1893 NULL
, true, OPTAB_LIB_WIDEN
);
1894 mark_reg_pointer (a1
, m_bitsize
);
1895 v1
= gen_rtx_MEM (mode
, a1
);
1896 set_mem_align (v1
, m_bitsize
);
1897 v1
= force_reg (mode
, validize_mem (v1
));
1899 a2
= plus_constant (base
, GET_MODE_SIZE (mode
) - 1);
1900 a2
= expand_simple_binop (Pmode
, AND
, force_operand (a2
, NULL
),
1901 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1902 NULL
, true, OPTAB_LIB_WIDEN
);
1903 v2
= gen_rtx_MEM (mode
, a2
);
1904 set_mem_align (v2
, m_bitsize
);
1905 v2
= force_reg (mode
, validize_mem (v2
));
1907 /* Combine these two values into a double-word value. */
1908 if (m_bitsize
== BITS_PER_WORD
)
1910 comb
= gen_reg_rtx (dmode
);
1911 emit_insn (gen_rtx_CLOBBER (VOIDmode
, comb
));
1912 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, 0), v1
);
1913 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, m_size
), v2
);
1917 if (BYTES_BIG_ENDIAN
)
1918 comb
= v1
, v1
= v2
, v2
= comb
;
1919 v1
= convert_modes (dmode
, mode
, v1
, true);
1922 v2
= convert_modes (dmode
, mode
, v2
, true);
1923 v2
= expand_simple_binop (dmode
, ASHIFT
, v2
, GEN_INT (m_bitsize
),
1924 NULL
, true, OPTAB_LIB_WIDEN
);
1927 comb
= expand_simple_binop (dmode
, IOR
, v1
, v2
, NULL
,
1928 true, OPTAB_LIB_WIDEN
);
1933 shift
= expand_simple_binop (Pmode
, AND
, base
, GEN_INT (m_size
- 1),
1934 NULL
, true, OPTAB_LIB_WIDEN
);
1935 shift
= expand_mult (Pmode
, shift
, GEN_INT (BITS_PER_UNIT
), NULL
, 1);
1939 if (sign_shift_up
<= bitpos
)
1940 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1941 shift
= expand_simple_binop (Pmode
, PLUS
, shift
, GEN_INT (bitpos
),
1942 NULL
, true, OPTAB_LIB_WIDEN
);
1947 unsigned HOST_WIDE_INT offset
= bitpos
/ BITS_PER_UNIT
;
1948 bitpos
%= BITS_PER_UNIT
;
1950 /* When strict alignment is not required, we can just load directly
1951 from memory without masking. If the remaining BITPOS offset is
1952 small enough, we may be able to do all operations in MODE as
1953 opposed to DMODE. */
1954 if (bitpos
+ bitsize
<= m_bitsize
)
1956 comb
= adjust_address (op0
, dmode
, offset
);
1958 if (sign_shift_up
<= bitpos
)
1959 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1960 shift
= GEN_INT (bitpos
);
1963 /* Shift down the double-word such that the requested value is at bit 0. */
1964 if (shift
!= const0_rtx
)
1965 comb
= expand_simple_binop (dmode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1966 comb
, shift
, NULL
, unsignedp
, OPTAB_LIB_WIDEN
);
1970 /* If the field exactly matches MODE, then all we need to do is return the
1971 lowpart. Otherwise, shift to get the sign bits set properly. */
1972 result
= force_reg (mode
, gen_lowpart (mode
, comb
));
1975 result
= expand_simple_binop (mode
, ASHIFT
, result
,
1976 GEN_INT (sign_shift_up
),
1977 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1979 result
= expand_simple_binop (mode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1980 result
, GEN_INT (sign_shift_dn
),
1981 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1986 delete_insns_since (start
);
1990 /* Extract a bit field that is split across two words
1991 and return an RTX for the result.
1993 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1994 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1995 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1998 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1999 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
2002 unsigned int bitsdone
= 0;
2003 rtx result
= NULL_RTX
;
2006 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2008 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2009 unit
= BITS_PER_WORD
;
2012 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2013 if (0 && bitsize
/ unit
> 2)
2015 rtx tmp
= extract_force_align_mem_bit_field (op0
, bitsize
, bitpos
,
2022 while (bitsdone
< bitsize
)
2024 unsigned HOST_WIDE_INT thissize
;
2026 unsigned HOST_WIDE_INT thispos
;
2027 unsigned HOST_WIDE_INT offset
;
2029 offset
= (bitpos
+ bitsdone
) / unit
;
2030 thispos
= (bitpos
+ bitsdone
) % unit
;
2032 /* THISSIZE must not overrun a word boundary. Otherwise,
2033 extract_fixed_bit_field will call us again, and we will mutually
2035 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2036 thissize
= MIN (thissize
, unit
- thispos
);
2038 /* If OP0 is a register, then handle OFFSET here.
2040 When handling multiword bitfields, extract_bit_field may pass
2041 down a word_mode SUBREG of a larger REG for a bitfield that actually
2042 crosses a word boundary. Thus, for a SUBREG, we must find
2043 the current word starting from the base register. */
2044 if (GET_CODE (op0
) == SUBREG
)
2046 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
2047 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
2048 GET_MODE (SUBREG_REG (op0
)));
2051 else if (REG_P (op0
))
2053 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
2059 /* Extract the parts in bit-counting order,
2060 whose meaning is determined by BYTES_PER_UNIT.
2061 OFFSET is in UNITs, and UNIT is in bits.
2062 extract_fixed_bit_field wants offset in bytes. */
2063 part
= extract_fixed_bit_field (word_mode
, word
,
2064 offset
* unit
/ BITS_PER_UNIT
,
2065 thissize
, thispos
, 0, 1);
2066 bitsdone
+= thissize
;
2068 /* Shift this part into place for the result. */
2069 if (BYTES_BIG_ENDIAN
)
2071 if (bitsize
!= bitsdone
)
2072 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2073 build_int_cst (NULL_TREE
, bitsize
- bitsdone
),
2078 if (bitsdone
!= thissize
)
2079 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2080 build_int_cst (NULL_TREE
,
2081 bitsdone
- thissize
), 0, 1);
2087 /* Combine the parts with bitwise or. This works
2088 because we extracted each part as an unsigned bit field. */
2089 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2095 /* Unsigned bit field: we are done. */
2098 /* Signed bit field: sign-extend with two arithmetic shifts. */
2099 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2100 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2102 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2103 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2107 /* Add INC into TARGET. */
2110 expand_inc (rtx target
, rtx inc
)
2112 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2114 target
, 0, OPTAB_LIB_WIDEN
);
2115 if (value
!= target
)
2116 emit_move_insn (target
, value
);
2119 /* Subtract DEC from TARGET. */
2122 expand_dec (rtx target
, rtx dec
)
2124 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2126 target
, 0, OPTAB_LIB_WIDEN
);
2127 if (value
!= target
)
2128 emit_move_insn (target
, value
);
2131 /* Output a shift instruction for expression code CODE,
2132 with SHIFTED being the rtx for the value to shift,
2133 and AMOUNT the tree for the amount to shift by.
2134 Store the result in the rtx TARGET, if that is convenient.
2135 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2136 Return the rtx for where the value is. */
2139 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2140 tree amount
, rtx target
, int unsignedp
)
2143 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2144 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2147 /* Previously detected shift-counts computed by NEGATE_EXPR
2148 and shifted in the other direction; but that does not work
2151 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
2153 if (SHIFT_COUNT_TRUNCATED
)
2155 if (GET_CODE (op1
) == CONST_INT
2156 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2157 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2158 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2159 % GET_MODE_BITSIZE (mode
));
2160 else if (GET_CODE (op1
) == SUBREG
2161 && subreg_lowpart_p (op1
))
2162 op1
= SUBREG_REG (op1
);
2165 if (op1
== const0_rtx
)
2168 /* Check whether its cheaper to implement a left shift by a constant
2169 bit count by a sequence of additions. */
2170 if (code
== LSHIFT_EXPR
2171 && GET_CODE (op1
) == CONST_INT
2173 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
)
2174 && shift_cost
[mode
][INTVAL (op1
)] > INTVAL (op1
) * add_cost
[mode
])
2177 for (i
= 0; i
< INTVAL (op1
); i
++)
2179 temp
= force_reg (mode
, shifted
);
2180 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2181 unsignedp
, OPTAB_LIB_WIDEN
);
2186 for (try = 0; temp
== 0 && try < 3; try++)
2188 enum optab_methods methods
;
2191 methods
= OPTAB_DIRECT
;
2193 methods
= OPTAB_WIDEN
;
2195 methods
= OPTAB_LIB_WIDEN
;
2199 /* Widening does not work for rotation. */
2200 if (methods
== OPTAB_WIDEN
)
2202 else if (methods
== OPTAB_LIB_WIDEN
)
2204 /* If we have been unable to open-code this by a rotation,
2205 do it as the IOR of two shifts. I.e., to rotate A
2206 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2207 where C is the bitsize of A.
2209 It is theoretically possible that the target machine might
2210 not be able to perform either shift and hence we would
2211 be making two libcalls rather than just the one for the
2212 shift (similarly if IOR could not be done). We will allow
2213 this extremely unlikely lossage to avoid complicating the
2216 rtx subtarget
= target
== shifted
? 0 : target
;
2218 tree type
= TREE_TYPE (amount
);
2219 tree new_amount
= make_tree (type
, op1
);
2221 = fold (build2 (MINUS_EXPR
, type
, convert
2222 (type
, build_int_cst
2223 (NULL_TREE
, GET_MODE_BITSIZE (mode
))),
2226 shifted
= force_reg (mode
, shifted
);
2228 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2229 mode
, shifted
, new_amount
, subtarget
, 1);
2230 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2231 mode
, shifted
, other_amount
, 0, 1);
2232 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2233 unsignedp
, methods
);
2236 temp
= expand_binop (mode
,
2237 left
? rotl_optab
: rotr_optab
,
2238 shifted
, op1
, target
, unsignedp
, methods
);
2240 /* If we don't have the rotate, but we are rotating by a constant
2241 that is in range, try a rotate in the opposite direction. */
2243 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
2245 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
2246 temp
= expand_binop (mode
,
2247 left
? rotr_optab
: rotl_optab
,
2249 GEN_INT (GET_MODE_BITSIZE (mode
)
2251 target
, unsignedp
, methods
);
2254 temp
= expand_binop (mode
,
2255 left
? ashl_optab
: lshr_optab
,
2256 shifted
, op1
, target
, unsignedp
, methods
);
2258 /* Do arithmetic shifts.
2259 Also, if we are going to widen the operand, we can just as well
2260 use an arithmetic right-shift instead of a logical one. */
2261 if (temp
== 0 && ! rotate
2262 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2264 enum optab_methods methods1
= methods
;
2266 /* If trying to widen a log shift to an arithmetic shift,
2267 don't accept an arithmetic shift of the same size. */
2269 methods1
= OPTAB_MUST_WIDEN
;
2271 /* Arithmetic shift */
2273 temp
= expand_binop (mode
,
2274 left
? ashl_optab
: ashr_optab
,
2275 shifted
, op1
, target
, unsignedp
, methods1
);
2278 /* We used to try extzv here for logical right shifts, but that was
2279 only useful for one machine, the VAX, and caused poor code
2280 generation there for lshrdi3, so the code was deleted and a
2281 define_expand for lshrsi3 was added to vax.md. */
2288 enum alg_code
{ alg_unknown
, alg_zero
, alg_m
, alg_shift
,
2289 alg_add_t_m2
, alg_sub_t_m2
,
2290 alg_add_factor
, alg_sub_factor
,
2291 alg_add_t2_m
, alg_sub_t2_m
};
2293 /* This structure holds the "cost" of a multiply sequence. The
2294 "cost" field holds the total rtx_cost of every operator in the
2295 synthetic multiplication sequence, hence cost(a op b) is defined
2296 as rtx_cost(op) + cost(a) + cost(b), where cost(leaf) is zero.
2297 The "latency" field holds the minimum possible latency of the
2298 synthetic multiply, on a hypothetical infinitely parallel CPU.
2299 This is the critical path, or the maximum height, of the expression
2300 tree which is the sum of rtx_costs on the most expensive path from
2301 any leaf to the root. Hence latency(a op b) is defined as zero for
2302 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */
2305 short cost
; /* Total rtx_cost of the multiplication sequence. */
2306 short latency
; /* The latency of the multiplication sequence. */
2309 /* This macro is used to compare a pointer to a mult_cost against an
2310 single integer "rtx_cost" value. This is equivalent to the macro
2311 CHEAPER_MULT_COST(X,Z) where Z = {Y,Y}. */
2312 #define MULT_COST_LESS(X,Y) ((X)->cost < (Y) \
2313 || ((X)->cost == (Y) && (X)->latency < (Y)))
2315 /* This macro is used to compare two pointers to mult_costs against
2316 each other. The macro returns true if X is cheaper than Y.
2317 Currently, the cheaper of two mult_costs is the one with the
2318 lower "cost". If "cost"s are tied, the lower latency is cheaper. */
2319 #define CHEAPER_MULT_COST(X,Y) ((X)->cost < (Y)->cost \
2320 || ((X)->cost == (Y)->cost \
2321 && (X)->latency < (Y)->latency))
2323 /* This structure records a sequence of operations.
2324 `ops' is the number of operations recorded.
2325 `cost' is their total cost.
2326 The operations are stored in `op' and the corresponding
2327 logarithms of the integer coefficients in `log'.
2329 These are the operations:
2330 alg_zero total := 0;
2331 alg_m total := multiplicand;
2332 alg_shift total := total * coeff
2333 alg_add_t_m2 total := total + multiplicand * coeff;
2334 alg_sub_t_m2 total := total - multiplicand * coeff;
2335 alg_add_factor total := total * coeff + total;
2336 alg_sub_factor total := total * coeff - total;
2337 alg_add_t2_m total := total * coeff + multiplicand;
2338 alg_sub_t2_m total := total * coeff - multiplicand;
2340 The first operand must be either alg_zero or alg_m. */
2344 struct mult_cost cost
;
2346 /* The size of the OP and LOG fields are not directly related to the
2347 word size, but the worst-case algorithms will be if we have few
2348 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2349 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2350 in total wordsize operations. */
2351 enum alg_code op
[MAX_BITS_PER_WORD
];
2352 char log
[MAX_BITS_PER_WORD
];
2355 /* The entry for our multiplication cache/hash table. */
2356 struct alg_hash_entry
{
2357 /* The number we are multiplying by. */
2360 /* The mode in which we are multiplying something by T. */
2361 enum machine_mode mode
;
2363 /* The best multiplication algorithm for t. */
2367 /* The number of cache/hash entries. */
2368 #define NUM_ALG_HASH_ENTRIES 307
2370 /* Each entry of ALG_HASH caches alg_code for some integer. This is
2371 actually a hash table. If we have a collision, that the older
2372 entry is kicked out. */
2373 static struct alg_hash_entry alg_hash
[NUM_ALG_HASH_ENTRIES
];
2375 /* Indicates the type of fixup needed after a constant multiplication.
2376 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2377 the result should be negated, and ADD_VARIANT means that the
2378 multiplicand should be added to the result. */
2379 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2381 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2382 const struct mult_cost
*, enum machine_mode mode
);
2383 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2384 struct algorithm
*, enum mult_variant
*, int);
2385 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2386 const struct algorithm
*, enum mult_variant
);
2387 static unsigned HOST_WIDE_INT
choose_multiplier (unsigned HOST_WIDE_INT
, int,
2388 int, unsigned HOST_WIDE_INT
*,
2390 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2391 static rtx
extract_high_half (enum machine_mode
, rtx
);
2392 static rtx
expand_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2393 static rtx
expand_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2395 /* Compute and return the best algorithm for multiplying by T.
2396 The algorithm must cost less than cost_limit
2397 If retval.cost >= COST_LIMIT, no algorithm was found and all
2398 other field of the returned struct are undefined.
2399 MODE is the machine mode of the multiplication. */
2402 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2403 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2406 struct algorithm
*alg_in
, *best_alg
;
2407 struct mult_cost best_cost
;
2408 struct mult_cost new_limit
;
2409 int op_cost
, op_latency
;
2410 unsigned HOST_WIDE_INT q
;
2411 int maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
2413 bool cache_hit
= false;
2414 enum alg_code cache_alg
= alg_zero
;
2416 /* Indicate that no algorithm is yet found. If no algorithm
2417 is found, this value will be returned and indicate failure. */
2418 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2419 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2421 if (cost_limit
->cost
< 0
2422 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2425 /* Restrict the bits of "t" to the multiplication's mode. */
2426 t
&= GET_MODE_MASK (mode
);
2428 /* t == 1 can be done in zero cost. */
2432 alg_out
->cost
.cost
= 0;
2433 alg_out
->cost
.latency
= 0;
2434 alg_out
->op
[0] = alg_m
;
2438 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2442 if (MULT_COST_LESS (cost_limit
, zero_cost
))
2447 alg_out
->cost
.cost
= zero_cost
;
2448 alg_out
->cost
.latency
= zero_cost
;
2449 alg_out
->op
[0] = alg_zero
;
2454 /* We'll be needing a couple extra algorithm structures now. */
2456 alg_in
= alloca (sizeof (struct algorithm
));
2457 best_alg
= alloca (sizeof (struct algorithm
));
2458 best_cost
= *cost_limit
;
2460 /* Compute the hash index. */
2461 hash_index
= (t
^ (unsigned int) mode
) % NUM_ALG_HASH_ENTRIES
;
2463 /* See if we already know what to do for T. */
2464 if (alg_hash
[hash_index
].t
== t
2465 && alg_hash
[hash_index
].mode
== mode
2466 && alg_hash
[hash_index
].alg
!= alg_unknown
)
2469 cache_alg
= alg_hash
[hash_index
].alg
;
2477 goto do_alg_addsub_t_m2
;
2479 case alg_add_factor
:
2480 case alg_sub_factor
:
2481 goto do_alg_addsub_factor
;
2484 goto do_alg_add_t2_m
;
2487 goto do_alg_sub_t2_m
;
2494 /* If we have a group of zero bits at the low-order part of T, try
2495 multiplying by the remaining bits and then doing a shift. */
2500 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2504 /* The function expand_shift will choose between a shift and
2505 a sequence of additions, so the observed cost is given as
2506 MIN (m * add_cost[mode], shift_cost[mode][m]). */
2507 op_cost
= m
* add_cost
[mode
];
2508 if (shift_cost
[mode
][m
] < op_cost
)
2509 op_cost
= shift_cost
[mode
][m
];
2510 new_limit
.cost
= best_cost
.cost
- op_cost
;
2511 new_limit
.latency
= best_cost
.latency
- op_cost
;
2512 synth_mult (alg_in
, q
, &new_limit
, mode
);
2514 alg_in
->cost
.cost
+= op_cost
;
2515 alg_in
->cost
.latency
+= op_cost
;
2516 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2518 struct algorithm
*x
;
2519 best_cost
= alg_in
->cost
;
2520 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2521 best_alg
->log
[best_alg
->ops
] = m
;
2522 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2529 /* If we have an odd number, add or subtract one. */
2532 unsigned HOST_WIDE_INT w
;
2535 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2537 /* If T was -1, then W will be zero after the loop. This is another
2538 case where T ends with ...111. Handling this with (T + 1) and
2539 subtract 1 produces slightly better code and results in algorithm
2540 selection much faster than treating it like the ...0111 case
2544 /* Reject the case where t is 3.
2545 Thus we prefer addition in that case. */
2548 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2550 op_cost
= add_cost
[mode
];
2551 new_limit
.cost
= best_cost
.cost
- op_cost
;
2552 new_limit
.latency
= best_cost
.latency
- op_cost
;
2553 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2555 alg_in
->cost
.cost
+= op_cost
;
2556 alg_in
->cost
.latency
+= op_cost
;
2557 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2559 struct algorithm
*x
;
2560 best_cost
= alg_in
->cost
;
2561 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2562 best_alg
->log
[best_alg
->ops
] = 0;
2563 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2568 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2570 op_cost
= add_cost
[mode
];
2571 new_limit
.cost
= best_cost
.cost
- op_cost
;
2572 new_limit
.latency
= best_cost
.latency
- op_cost
;
2573 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2575 alg_in
->cost
.cost
+= op_cost
;
2576 alg_in
->cost
.latency
+= op_cost
;
2577 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2579 struct algorithm
*x
;
2580 best_cost
= alg_in
->cost
;
2581 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2582 best_alg
->log
[best_alg
->ops
] = 0;
2583 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2590 /* Look for factors of t of the form
2591 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2592 If we find such a factor, we can multiply by t using an algorithm that
2593 multiplies by q, shift the result by m and add/subtract it to itself.
2595 We search for large factors first and loop down, even if large factors
2596 are less probable than small; if we find a large factor we will find a
2597 good sequence quickly, and therefore be able to prune (by decreasing
2598 COST_LIMIT) the search. */
2600 do_alg_addsub_factor
:
2601 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2603 unsigned HOST_WIDE_INT d
;
2605 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2606 if (t
% d
== 0 && t
> d
&& m
< maxm
2607 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2609 /* If the target has a cheap shift-and-add instruction use
2610 that in preference to a shift insn followed by an add insn.
2611 Assume that the shift-and-add is "atomic" with a latency
2612 equal to its cost, otherwise assume that on superscalar
2613 hardware the shift may be executed concurrently with the
2614 earlier steps in the algorithm. */
2615 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2616 if (shiftadd_cost
[mode
][m
] < op_cost
)
2618 op_cost
= shiftadd_cost
[mode
][m
];
2619 op_latency
= op_cost
;
2622 op_latency
= add_cost
[mode
];
2624 new_limit
.cost
= best_cost
.cost
- op_cost
;
2625 new_limit
.latency
= best_cost
.latency
- op_latency
;
2626 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2628 alg_in
->cost
.cost
+= op_cost
;
2629 alg_in
->cost
.latency
+= op_latency
;
2630 if (alg_in
->cost
.latency
< op_cost
)
2631 alg_in
->cost
.latency
= op_cost
;
2632 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2634 struct algorithm
*x
;
2635 best_cost
= alg_in
->cost
;
2636 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2637 best_alg
->log
[best_alg
->ops
] = m
;
2638 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2640 /* Other factors will have been taken care of in the recursion. */
2644 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2645 if (t
% d
== 0 && t
> d
&& m
< maxm
2646 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2648 /* If the target has a cheap shift-and-subtract insn use
2649 that in preference to a shift insn followed by a sub insn.
2650 Assume that the shift-and-sub is "atomic" with a latency
2651 equal to it's cost, otherwise assume that on superscalar
2652 hardware the shift may be executed concurrently with the
2653 earlier steps in the algorithm. */
2654 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2655 if (shiftsub_cost
[mode
][m
] < op_cost
)
2657 op_cost
= shiftsub_cost
[mode
][m
];
2658 op_latency
= op_cost
;
2661 op_latency
= add_cost
[mode
];
2663 new_limit
.cost
= best_cost
.cost
- op_cost
;
2664 new_limit
.latency
= best_cost
.latency
- op_latency
;
2665 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2667 alg_in
->cost
.cost
+= op_cost
;
2668 alg_in
->cost
.latency
+= op_latency
;
2669 if (alg_in
->cost
.latency
< op_cost
)
2670 alg_in
->cost
.latency
= op_cost
;
2671 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2673 struct algorithm
*x
;
2674 best_cost
= alg_in
->cost
;
2675 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2676 best_alg
->log
[best_alg
->ops
] = m
;
2677 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2685 /* Try shift-and-add (load effective address) instructions,
2686 i.e. do a*3, a*5, a*9. */
2693 if (m
>= 0 && m
< maxm
)
2695 op_cost
= shiftadd_cost
[mode
][m
];
2696 new_limit
.cost
= best_cost
.cost
- op_cost
;
2697 new_limit
.latency
= best_cost
.latency
- op_cost
;
2698 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2700 alg_in
->cost
.cost
+= op_cost
;
2701 alg_in
->cost
.latency
+= op_cost
;
2702 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2704 struct algorithm
*x
;
2705 best_cost
= alg_in
->cost
;
2706 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2707 best_alg
->log
[best_alg
->ops
] = m
;
2708 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2718 if (m
>= 0 && m
< maxm
)
2720 op_cost
= shiftsub_cost
[mode
][m
];
2721 new_limit
.cost
= best_cost
.cost
- op_cost
;
2722 new_limit
.latency
= best_cost
.latency
- op_cost
;
2723 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2725 alg_in
->cost
.cost
+= op_cost
;
2726 alg_in
->cost
.latency
+= op_cost
;
2727 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2729 struct algorithm
*x
;
2730 best_cost
= alg_in
->cost
;
2731 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2732 best_alg
->log
[best_alg
->ops
] = m
;
2733 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2741 /* If best_cost has not decreased, we have not found any algorithm. */
2742 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2745 /* Cache the result. */
2748 alg_hash
[hash_index
].t
= t
;
2749 alg_hash
[hash_index
].mode
= mode
;
2750 alg_hash
[hash_index
].alg
= best_alg
->op
[best_alg
->ops
];
2753 /* If we are getting a too long sequence for `struct algorithm'
2754 to record, make this search fail. */
2755 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2758 /* Copy the algorithm from temporary space to the space at alg_out.
2759 We avoid using structure assignment because the majority of
2760 best_alg is normally undefined, and this is a critical function. */
2761 alg_out
->ops
= best_alg
->ops
+ 1;
2762 alg_out
->cost
= best_cost
;
2763 memcpy (alg_out
->op
, best_alg
->op
,
2764 alg_out
->ops
* sizeof *alg_out
->op
);
2765 memcpy (alg_out
->log
, best_alg
->log
,
2766 alg_out
->ops
* sizeof *alg_out
->log
);
2769 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2770 Try three variations:
2772 - a shift/add sequence based on VAL itself
2773 - a shift/add sequence based on -VAL, followed by a negation
2774 - a shift/add sequence based on VAL - 1, followed by an addition.
2776 Return true if the cheapest of these cost less than MULT_COST,
2777 describing the algorithm in *ALG and final fixup in *VARIANT. */
2780 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2781 struct algorithm
*alg
, enum mult_variant
*variant
,
2784 struct algorithm alg2
;
2785 struct mult_cost limit
;
2788 *variant
= basic_variant
;
2789 limit
.cost
= mult_cost
;
2790 limit
.latency
= mult_cost
;
2791 synth_mult (alg
, val
, &limit
, mode
);
2793 /* This works only if the inverted value actually fits in an
2795 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2797 op_cost
= neg_cost
[mode
];
2798 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2800 limit
.cost
= alg
->cost
.cost
- op_cost
;
2801 limit
.latency
= alg
->cost
.latency
- op_cost
;
2805 limit
.cost
= mult_cost
- op_cost
;
2806 limit
.latency
= mult_cost
- op_cost
;
2809 synth_mult (&alg2
, -val
, &limit
, mode
);
2810 alg2
.cost
.cost
+= op_cost
;
2811 alg2
.cost
.latency
+= op_cost
;
2812 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2813 *alg
= alg2
, *variant
= negate_variant
;
2816 /* This proves very useful for division-by-constant. */
2817 op_cost
= add_cost
[mode
];
2818 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2820 limit
.cost
= alg
->cost
.cost
- op_cost
;
2821 limit
.latency
= alg
->cost
.latency
- op_cost
;
2825 limit
.cost
= mult_cost
- op_cost
;
2826 limit
.latency
= mult_cost
- op_cost
;
2829 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2830 alg2
.cost
.cost
+= op_cost
;
2831 alg2
.cost
.latency
+= op_cost
;
2832 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2833 *alg
= alg2
, *variant
= add_variant
;
2835 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2838 /* A subroutine of expand_mult, used for constant multiplications.
2839 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2840 convenient. Use the shift/add sequence described by ALG and apply
2841 the final fixup specified by VARIANT. */
2844 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2845 rtx target
, const struct algorithm
*alg
,
2846 enum mult_variant variant
)
2848 HOST_WIDE_INT val_so_far
;
2849 rtx insn
, accum
, tem
;
2851 enum machine_mode nmode
;
2853 /* Avoid referencing memory over and over.
2854 For speed, but also for correctness when mem is volatile. */
2856 op0
= force_reg (mode
, op0
);
2858 /* ACCUM starts out either as OP0 or as a zero, depending on
2859 the first operation. */
2861 if (alg
->op
[0] == alg_zero
)
2863 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2866 else if (alg
->op
[0] == alg_m
)
2868 accum
= copy_to_mode_reg (mode
, op0
);
2874 for (opno
= 1; opno
< alg
->ops
; opno
++)
2876 int log
= alg
->log
[opno
];
2877 rtx shift_subtarget
= optimize
? 0 : accum
;
2879 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2882 rtx accum_target
= optimize
? 0 : accum
;
2884 switch (alg
->op
[opno
])
2887 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2888 build_int_cst (NULL_TREE
, log
),
2894 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2895 build_int_cst (NULL_TREE
, log
),
2897 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2898 add_target
? add_target
: accum_target
);
2899 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2903 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2904 build_int_cst (NULL_TREE
, log
),
2906 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2907 add_target
? add_target
: accum_target
);
2908 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2912 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2913 build_int_cst (NULL_TREE
, log
),
2916 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2917 add_target
? add_target
: accum_target
);
2918 val_so_far
= (val_so_far
<< log
) + 1;
2922 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2923 build_int_cst (NULL_TREE
, log
),
2924 shift_subtarget
, 0);
2925 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2926 add_target
? add_target
: accum_target
);
2927 val_so_far
= (val_so_far
<< log
) - 1;
2930 case alg_add_factor
:
2931 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2932 build_int_cst (NULL_TREE
, log
),
2934 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2935 add_target
? add_target
: accum_target
);
2936 val_so_far
+= val_so_far
<< log
;
2939 case alg_sub_factor
:
2940 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2941 build_int_cst (NULL_TREE
, log
),
2943 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2945 ? add_target
: (optimize
? 0 : tem
)));
2946 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2953 /* Write a REG_EQUAL note on the last insn so that we can cse
2954 multiplication sequences. Note that if ACCUM is a SUBREG,
2955 we've set the inner register and must properly indicate
2958 tem
= op0
, nmode
= mode
;
2959 if (GET_CODE (accum
) == SUBREG
)
2961 nmode
= GET_MODE (SUBREG_REG (accum
));
2962 tem
= gen_lowpart (nmode
, op0
);
2965 insn
= get_last_insn ();
2966 set_unique_reg_note (insn
, REG_EQUAL
,
2967 gen_rtx_MULT (nmode
, tem
, GEN_INT (val_so_far
)));
2970 if (variant
== negate_variant
)
2972 val_so_far
= -val_so_far
;
2973 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2975 else if (variant
== add_variant
)
2977 val_so_far
= val_so_far
+ 1;
2978 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2981 /* Compare only the bits of val and val_so_far that are significant
2982 in the result mode, to avoid sign-/zero-extension confusion. */
2983 val
&= GET_MODE_MASK (mode
);
2984 val_so_far
&= GET_MODE_MASK (mode
);
2985 gcc_assert (val
== val_so_far
);
2990 /* Perform a multiplication and return an rtx for the result.
2991 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2992 TARGET is a suggestion for where to store the result (an rtx).
2994 We check specially for a constant integer as OP1.
2995 If you want this check for OP0 as well, then before calling
2996 you should swap the two operands if OP0 would be constant. */
2999 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3002 rtx const_op1
= op1
;
3003 enum mult_variant variant
;
3004 struct algorithm algorithm
;
3006 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3007 less than or equal in size to `unsigned int' this doesn't matter.
3008 If the mode is larger than `unsigned int', then synth_mult works only
3009 if the constant value exactly fits in an `unsigned int' without any
3010 truncation. This means that multiplying by negative values does
3011 not work; results are off by 2^32 on a 32 bit machine. */
3013 /* If we are multiplying in DImode, it may still be a win
3014 to try to work with shifts and adds. */
3015 if (GET_CODE (op1
) == CONST_DOUBLE
3016 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
3017 && HOST_BITS_PER_INT
>= BITS_PER_WORD
3018 && CONST_DOUBLE_HIGH (op1
) == 0)
3019 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
3020 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
3021 && GET_CODE (op1
) == CONST_INT
3022 && INTVAL (op1
) < 0)
3025 /* We used to test optimize here, on the grounds that it's better to
3026 produce a smaller program when -O is not used.
3027 But this causes such a terrible slowdown sometimes
3028 that it seems better to use synth_mult always. */
3030 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
3031 && (unsignedp
|| !flag_trapv
))
3033 HOST_WIDE_INT coeff
= INTVAL (const_op1
);
3036 /* Special case powers of two. */
3037 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3043 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3044 build_int_cst (NULL_TREE
, floor_log2 (coeff
)),
3048 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
3049 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3051 return expand_mult_const (mode
, op0
, coeff
, target
,
3052 &algorithm
, variant
);
3055 if (GET_CODE (op0
) == CONST_DOUBLE
)
3062 /* Expand x*2.0 as x+x. */
3063 if (GET_CODE (op1
) == CONST_DOUBLE
3064 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3067 REAL_VALUE_FROM_CONST_DOUBLE (d
, op1
);
3069 if (REAL_VALUES_EQUAL (d
, dconst2
))
3071 op0
= force_reg (GET_MODE (op0
), op0
);
3072 return expand_binop (mode
, add_optab
, op0
, op0
,
3073 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3077 /* This used to use umul_optab if unsigned, but for non-widening multiply
3078 there is no difference between signed and unsigned. */
3079 op0
= expand_binop (mode
,
3081 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
3082 ? smulv_optab
: smul_optab
,
3083 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3088 /* Return the smallest n such that 2**n >= X. */
3091 ceil_log2 (unsigned HOST_WIDE_INT x
)
3093 return floor_log2 (x
- 1) + 1;
3096 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3097 replace division by D, and put the least significant N bits of the result
3098 in *MULTIPLIER_PTR and return the most significant bit.
3100 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3101 needed precision is in PRECISION (should be <= N).
3103 PRECISION should be as small as possible so this function can choose
3104 multiplier more freely.
3106 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3107 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3109 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3110 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3113 unsigned HOST_WIDE_INT
3114 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3115 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3116 int *post_shift_ptr
, int *lgup_ptr
)
3118 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
3119 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
3120 int lgup
, post_shift
;
3122 unsigned HOST_WIDE_INT nl
, dummy1
;
3123 HOST_WIDE_INT nh
, dummy2
;
3125 /* lgup = ceil(log2(divisor)); */
3126 lgup
= ceil_log2 (d
);
3128 gcc_assert (lgup
<= n
);
3131 pow2
= n
+ lgup
- precision
;
3133 /* We could handle this with some effort, but this case is much
3134 better handled directly with a scc insn, so rely on caller using
3136 gcc_assert (pow
!= 2 * HOST_BITS_PER_WIDE_INT
);
3138 /* mlow = 2^(N + lgup)/d */
3139 if (pow
>= HOST_BITS_PER_WIDE_INT
)
3141 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
3147 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
3149 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3150 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
3152 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3153 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
3154 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
3156 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
3157 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3158 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
3160 gcc_assert (!mhigh_hi
|| nh
- d
< d
);
3161 gcc_assert (mhigh_hi
<= 1 && mlow_hi
<= 1);
3162 /* Assert that mlow < mhigh. */
3163 gcc_assert (mlow_hi
< mhigh_hi
3164 || (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
));
3166 /* If precision == N, then mlow, mhigh exceed 2^N
3167 (but they do not exceed 2^(N+1)). */
3169 /* Reduce to lowest terms. */
3170 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3172 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
3173 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
3183 *post_shift_ptr
= post_shift
;
3185 if (n
< HOST_BITS_PER_WIDE_INT
)
3187 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3188 *multiplier_ptr
= mhigh_lo
& mask
;
3189 return mhigh_lo
>= mask
;
3193 *multiplier_ptr
= mhigh_lo
;
3198 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3199 congruent to 1 (mod 2**N). */
3201 static unsigned HOST_WIDE_INT
3202 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3204 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3206 /* The algorithm notes that the choice y = x satisfies
3207 x*y == 1 mod 2^3, since x is assumed odd.
3208 Each iteration doubles the number of bits of significance in y. */
3210 unsigned HOST_WIDE_INT mask
;
3211 unsigned HOST_WIDE_INT y
= x
;
3214 mask
= (n
== HOST_BITS_PER_WIDE_INT
3215 ? ~(unsigned HOST_WIDE_INT
) 0
3216 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3220 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3226 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3227 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3228 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3229 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3232 The result is put in TARGET if that is convenient.
3234 MODE is the mode of operation. */
3237 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3238 rtx op1
, rtx target
, int unsignedp
)
3241 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3243 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3244 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3246 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3248 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3251 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3252 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3254 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3255 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3261 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3264 extract_high_half (enum machine_mode mode
, rtx op
)
3266 enum machine_mode wider_mode
;
3268 if (mode
== word_mode
)
3269 return gen_highpart (mode
, op
);
3271 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3272 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3273 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
)), 0, 1);
3274 return convert_modes (mode
, wider_mode
, op
, 0);
3277 /* Like expand_mult_highpart, but only consider using a multiplication
3278 optab. OP1 is an rtx for the constant operand. */
3281 expand_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3282 rtx target
, int unsignedp
, int max_cost
)
3284 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3285 enum machine_mode wider_mode
;
3290 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3291 size
= GET_MODE_BITSIZE (mode
);
3293 /* Firstly, try using a multiplication insn that only generates the needed
3294 high part of the product, and in the sign flavor of unsignedp. */
3295 if (mul_highpart_cost
[mode
] < max_cost
)
3297 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3298 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3299 unsignedp
, OPTAB_DIRECT
);
3304 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3305 Need to adjust the result after the multiplication. */
3306 if (size
- 1 < BITS_PER_WORD
3307 && (mul_highpart_cost
[mode
] + 2 * shift_cost
[mode
][size
-1]
3308 + 4 * add_cost
[mode
] < max_cost
))
3310 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3311 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3312 unsignedp
, OPTAB_DIRECT
);
3314 /* We used the wrong signedness. Adjust the result. */
3315 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3319 /* Try widening multiplication. */
3320 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3321 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3322 && mul_widen_cost
[wider_mode
] < max_cost
)
3324 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3325 unsignedp
, OPTAB_WIDEN
);
3327 return extract_high_half (mode
, tem
);
3330 /* Try widening the mode and perform a non-widening multiplication. */
3331 moptab
= smul_optab
;
3332 if (smul_optab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3333 && size
- 1 < BITS_PER_WORD
3334 && mul_cost
[wider_mode
] + shift_cost
[mode
][size
-1] < max_cost
)
3336 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
, 0,
3337 unsignedp
, OPTAB_WIDEN
);
3339 return extract_high_half (mode
, tem
);
3342 /* Try widening multiplication of opposite signedness, and adjust. */
3343 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3344 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3345 && size
- 1 < BITS_PER_WORD
3346 && (mul_widen_cost
[wider_mode
] + 2 * shift_cost
[mode
][size
-1]
3347 + 4 * add_cost
[mode
] < max_cost
))
3349 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3350 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3353 tem
= extract_high_half (mode
, tem
);
3354 /* We used the wrong signedness. Adjust the result. */
3355 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3363 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3364 putting the high half of the result in TARGET if that is convenient,
3365 and return where the result is. If the operation can not be performed,
3368 MODE is the mode of operation and result.
3370 UNSIGNEDP nonzero means unsigned multiply.
3372 MAX_COST is the total allowed cost for the expanded RTL. */
3375 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3376 rtx target
, int unsignedp
, int max_cost
)
3378 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3379 unsigned HOST_WIDE_INT cnst1
;
3381 bool sign_adjust
= false;
3382 enum mult_variant variant
;
3383 struct algorithm alg
;
3386 /* We can't support modes wider than HOST_BITS_PER_INT. */
3387 gcc_assert (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
);
3389 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3391 /* We can't optimize modes wider than BITS_PER_WORD.
3392 ??? We might be able to perform double-word arithmetic if
3393 mode == word_mode, however all the cost calculations in
3394 synth_mult etc. assume single-word operations. */
3395 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3396 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3397 unsignedp
, max_cost
);
3399 extra_cost
= shift_cost
[mode
][GET_MODE_BITSIZE (mode
) - 1];
3401 /* Check whether we try to multiply by a negative constant. */
3402 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3405 extra_cost
+= add_cost
[mode
];
3408 /* See whether shift/add multiplication is cheap enough. */
3409 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3410 max_cost
- extra_cost
))
3412 /* See whether the specialized multiplication optabs are
3413 cheaper than the shift/add version. */
3414 tem
= expand_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3415 alg
.cost
.cost
+ extra_cost
);
3419 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3420 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3421 tem
= extract_high_half (mode
, tem
);
3423 /* Adjust result for signedness. */
3425 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3429 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3430 unsignedp
, max_cost
);
3434 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3437 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3439 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3440 rtx result
, temp
, shift
, label
;
3443 logd
= floor_log2 (d
);
3444 result
= gen_reg_rtx (mode
);
3446 /* Avoid conditional branches when they're expensive. */
3447 if (BRANCH_COST
>= 2
3450 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3454 signmask
= force_reg (mode
, signmask
);
3455 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3456 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3458 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3459 which instruction sequence to use. If logical right shifts
3460 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3461 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3463 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3464 if (lshr_optab
->handlers
[mode
].insn_code
== CODE_FOR_nothing
3465 || rtx_cost (temp
, SET
) > COSTS_N_INSNS (2))
3467 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3468 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3469 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3470 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3471 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3472 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3473 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3474 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3475 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3476 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3480 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3481 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3482 signmask
= force_reg (mode
, signmask
);
3484 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3485 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3486 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3487 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3488 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3489 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3495 /* Mask contains the mode's signbit and the significant bits of the
3496 modulus. By including the signbit in the operation, many targets
3497 can avoid an explicit compare operation in the following comparison
3500 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3501 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3503 masklow
|= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1);
3507 maskhigh
= (HOST_WIDE_INT
) -1
3508 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3510 temp
= expand_binop (mode
, and_optab
, op0
,
3511 immed_double_const (masklow
, maskhigh
, mode
),
3512 result
, 1, OPTAB_LIB_WIDEN
);
3514 emit_move_insn (result
, temp
);
3516 label
= gen_label_rtx ();
3517 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3519 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3520 0, OPTAB_LIB_WIDEN
);
3521 masklow
= (HOST_WIDE_INT
) -1 << logd
;
3523 temp
= expand_binop (mode
, ior_optab
, temp
,
3524 immed_double_const (masklow
, maskhigh
, mode
),
3525 result
, 1, OPTAB_LIB_WIDEN
);
3526 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3527 0, OPTAB_LIB_WIDEN
);
3529 emit_move_insn (result
, temp
);
3534 /* Expand signed division of OP0 by a power of two D in mode MODE.
3535 This routine is only called for positive values of D. */
3538 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3544 logd
= floor_log2 (d
);
3545 shift
= build_int_cst (NULL_TREE
, logd
);
3547 if (d
== 2 && BRANCH_COST
>= 1)
3549 temp
= gen_reg_rtx (mode
);
3550 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3551 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3552 0, OPTAB_LIB_WIDEN
);
3553 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3556 #ifdef HAVE_conditional_move
3557 if (BRANCH_COST
>= 2)
3561 /* ??? emit_conditional_move forces a stack adjustment via
3562 compare_from_rtx so, if the sequence is discarded, it will
3563 be lost. Do it now instead. */
3564 do_pending_stack_adjust ();
3567 temp2
= copy_to_mode_reg (mode
, op0
);
3568 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3569 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3570 temp
= force_reg (mode
, temp
);
3572 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3573 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3574 mode
, temp
, temp2
, mode
, 0);
3577 rtx seq
= get_insns ();
3580 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, shift
, NULL_RTX
, 0);
3586 if (BRANCH_COST
>= 2)
3588 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3590 temp
= gen_reg_rtx (mode
);
3591 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3592 if (shift_cost
[mode
][ushift
] > COSTS_N_INSNS (1))
3593 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3594 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3596 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3597 build_int_cst (NULL_TREE
, ushift
),
3599 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3600 0, OPTAB_LIB_WIDEN
);
3601 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3604 label
= gen_label_rtx ();
3605 temp
= copy_to_mode_reg (mode
, op0
);
3606 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3607 expand_inc (temp
, GEN_INT (d
- 1));
3609 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3612 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3613 if that is convenient, and returning where the result is.
3614 You may request either the quotient or the remainder as the result;
3615 specify REM_FLAG nonzero to get the remainder.
3617 CODE is the expression code for which kind of division this is;
3618 it controls how rounding is done. MODE is the machine mode to use.
3619 UNSIGNEDP nonzero means do unsigned division. */
3621 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3622 and then correct it by or'ing in missing high bits
3623 if result of ANDI is nonzero.
3624 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3625 This could optimize to a bfexts instruction.
3626 But C doesn't use these operations, so their optimizations are
3628 /* ??? For modulo, we don't actually need the highpart of the first product,
3629 the low part will do nicely. And for small divisors, the second multiply
3630 can also be a low-part only multiply or even be completely left out.
3631 E.g. to calculate the remainder of a division by 3 with a 32 bit
3632 multiply, multiply with 0x55555556 and extract the upper two bits;
3633 the result is exact for inputs up to 0x1fffffff.
3634 The input range can be reduced by using cross-sum rules.
3635 For odd divisors >= 3, the following table gives right shift counts
3636 so that if a number is shifted by an integer multiple of the given
3637 amount, the remainder stays the same:
3638 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3639 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3640 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3641 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3642 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3644 Cross-sum rules for even numbers can be derived by leaving as many bits
3645 to the right alone as the divisor has zeros to the right.
3646 E.g. if x is an unsigned 32 bit number:
3647 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3651 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3652 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3654 enum machine_mode compute_mode
;
3656 rtx quotient
= 0, remainder
= 0;
3660 optab optab1
, optab2
;
3661 int op1_is_constant
, op1_is_pow2
= 0;
3662 int max_cost
, extra_cost
;
3663 static HOST_WIDE_INT last_div_const
= 0;
3664 static HOST_WIDE_INT ext_op1
;
3666 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3667 if (op1_is_constant
)
3669 ext_op1
= INTVAL (op1
);
3671 ext_op1
&= GET_MODE_MASK (mode
);
3672 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3673 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3677 This is the structure of expand_divmod:
3679 First comes code to fix up the operands so we can perform the operations
3680 correctly and efficiently.
3682 Second comes a switch statement with code specific for each rounding mode.
3683 For some special operands this code emits all RTL for the desired
3684 operation, for other cases, it generates only a quotient and stores it in
3685 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3686 to indicate that it has not done anything.
3688 Last comes code that finishes the operation. If QUOTIENT is set and
3689 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3690 QUOTIENT is not set, it is computed using trunc rounding.
3692 We try to generate special code for division and remainder when OP1 is a
3693 constant. If |OP1| = 2**n we can use shifts and some other fast
3694 operations. For other values of OP1, we compute a carefully selected
3695 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3698 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3699 half of the product. Different strategies for generating the product are
3700 implemented in expand_mult_highpart.
3702 If what we actually want is the remainder, we generate that by another
3703 by-constant multiplication and a subtraction. */
3705 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3706 code below will malfunction if we are, so check here and handle
3707 the special case if so. */
3708 if (op1
== const1_rtx
)
3709 return rem_flag
? const0_rtx
: op0
;
3711 /* When dividing by -1, we could get an overflow.
3712 negv_optab can handle overflows. */
3713 if (! unsignedp
&& op1
== constm1_rtx
)
3717 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3718 ? negv_optab
: neg_optab
, op0
, target
, 0);
3722 /* Don't use the function value register as a target
3723 since we have to read it as well as write it,
3724 and function-inlining gets confused by this. */
3725 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3726 /* Don't clobber an operand while doing a multi-step calculation. */
3727 || ((rem_flag
|| op1_is_constant
)
3728 && (reg_mentioned_p (target
, op0
)
3729 || (MEM_P (op0
) && MEM_P (target
))))
3730 || reg_mentioned_p (target
, op1
)
3731 || (MEM_P (op1
) && MEM_P (target
))))
3734 /* Get the mode in which to perform this computation. Normally it will
3735 be MODE, but sometimes we can't do the desired operation in MODE.
3736 If so, pick a wider mode in which we can do the operation. Convert
3737 to that mode at the start to avoid repeated conversions.
3739 First see what operations we need. These depend on the expression
3740 we are evaluating. (We assume that divxx3 insns exist under the
3741 same conditions that modxx3 insns and that these insns don't normally
3742 fail. If these assumptions are not correct, we may generate less
3743 efficient code in some cases.)
3745 Then see if we find a mode in which we can open-code that operation
3746 (either a division, modulus, or shift). Finally, check for the smallest
3747 mode for which we can do the operation with a library call. */
3749 /* We might want to refine this now that we have division-by-constant
3750 optimization. Since expand_mult_highpart tries so many variants, it is
3751 not straightforward to generalize this. Maybe we should make an array
3752 of possible modes in init_expmed? Save this for GCC 2.7. */
3754 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3755 ? (unsignedp
? lshr_optab
: ashr_optab
)
3756 : (unsignedp
? udiv_optab
: sdiv_optab
));
3757 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3759 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3761 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3762 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3763 if (optab1
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
3764 || optab2
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
)
3767 if (compute_mode
== VOIDmode
)
3768 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3769 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3770 if (optab1
->handlers
[compute_mode
].libfunc
3771 || optab2
->handlers
[compute_mode
].libfunc
)
3774 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3776 if (compute_mode
== VOIDmode
)
3777 compute_mode
= mode
;
3779 if (target
&& GET_MODE (target
) == compute_mode
)
3782 tquotient
= gen_reg_rtx (compute_mode
);
3784 size
= GET_MODE_BITSIZE (compute_mode
);
3786 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3787 (mode), and thereby get better code when OP1 is a constant. Do that
3788 later. It will require going over all usages of SIZE below. */
3789 size
= GET_MODE_BITSIZE (mode
);
3792 /* Only deduct something for a REM if the last divide done was
3793 for a different constant. Then set the constant of the last
3795 max_cost
= div_cost
[compute_mode
]
3796 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3797 && INTVAL (op1
) == last_div_const
)
3798 ? mul_cost
[compute_mode
] + add_cost
[compute_mode
]
3801 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3803 /* Now convert to the best mode to use. */
3804 if (compute_mode
!= mode
)
3806 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3807 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3809 /* convert_modes may have placed op1 into a register, so we
3810 must recompute the following. */
3811 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3812 op1_is_pow2
= (op1_is_constant
3813 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3815 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3818 /* If one of the operands is a volatile MEM, copy it into a register. */
3820 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3821 op0
= force_reg (compute_mode
, op0
);
3822 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3823 op1
= force_reg (compute_mode
, op1
);
3825 /* If we need the remainder or if OP1 is constant, we need to
3826 put OP0 in a register in case it has any queued subexpressions. */
3827 if (rem_flag
|| op1_is_constant
)
3828 op0
= force_reg (compute_mode
, op0
);
3830 last
= get_last_insn ();
3832 /* Promote floor rounding to trunc rounding for unsigned operations. */
3835 if (code
== FLOOR_DIV_EXPR
)
3836 code
= TRUNC_DIV_EXPR
;
3837 if (code
== FLOOR_MOD_EXPR
)
3838 code
= TRUNC_MOD_EXPR
;
3839 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3840 code
= TRUNC_DIV_EXPR
;
3843 if (op1
!= const0_rtx
)
3846 case TRUNC_MOD_EXPR
:
3847 case TRUNC_DIV_EXPR
:
3848 if (op1_is_constant
)
3852 unsigned HOST_WIDE_INT mh
, ml
;
3853 int pre_shift
, post_shift
;
3855 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
3856 & GET_MODE_MASK (compute_mode
));
3858 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3860 pre_shift
= floor_log2 (d
);
3864 = expand_binop (compute_mode
, and_optab
, op0
,
3865 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3869 return gen_lowpart (mode
, remainder
);
3871 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3872 build_int_cst (NULL_TREE
,
3876 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3878 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3880 /* Most significant bit of divisor is set; emit an scc
3882 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3883 compute_mode
, 1, 1);
3889 /* Find a suitable multiplier and right shift count
3890 instead of multiplying with D. */
3892 mh
= choose_multiplier (d
, size
, size
,
3893 &ml
, &post_shift
, &dummy
);
3895 /* If the suggested multiplier is more than SIZE bits,
3896 we can do better for even divisors, using an
3897 initial right shift. */
3898 if (mh
!= 0 && (d
& 1) == 0)
3900 pre_shift
= floor_log2 (d
& -d
);
3901 mh
= choose_multiplier (d
>> pre_shift
, size
,
3903 &ml
, &post_shift
, &dummy
);
3913 if (post_shift
- 1 >= BITS_PER_WORD
)
3917 = (shift_cost
[compute_mode
][post_shift
- 1]
3918 + shift_cost
[compute_mode
][1]
3919 + 2 * add_cost
[compute_mode
]);
3920 t1
= gen_int_mode (ml
, compute_mode
);
3921 t1
= expand_mult_highpart (compute_mode
, op0
, t1
,
3923 max_cost
- extra_cost
);
3926 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3930 (RSHIFT_EXPR
, compute_mode
, t2
,
3931 build_int_cst (NULL_TREE
, 1),
3933 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3936 quotient
= expand_shift
3937 (RSHIFT_EXPR
, compute_mode
, t4
,
3938 build_int_cst (NULL_TREE
, post_shift
- 1),
3945 if (pre_shift
>= BITS_PER_WORD
3946 || post_shift
>= BITS_PER_WORD
)
3950 (RSHIFT_EXPR
, compute_mode
, op0
,
3951 build_int_cst (NULL_TREE
, pre_shift
),
3954 = (shift_cost
[compute_mode
][pre_shift
]
3955 + shift_cost
[compute_mode
][post_shift
]);
3956 t2
= gen_int_mode (ml
, compute_mode
);
3957 t2
= expand_mult_highpart (compute_mode
, t1
, t2
,
3959 max_cost
- extra_cost
);
3962 quotient
= expand_shift
3963 (RSHIFT_EXPR
, compute_mode
, t2
,
3964 build_int_cst (NULL_TREE
, post_shift
),
3969 else /* Too wide mode to use tricky code */
3972 insn
= get_last_insn ();
3974 && (set
= single_set (insn
)) != 0
3975 && SET_DEST (set
) == quotient
)
3976 set_unique_reg_note (insn
,
3978 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3980 else /* TRUNC_DIV, signed */
3982 unsigned HOST_WIDE_INT ml
;
3983 int lgup
, post_shift
;
3984 HOST_WIDE_INT d
= INTVAL (op1
);
3985 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3987 /* n rem d = n rem -d */
3988 if (rem_flag
&& d
< 0)
3991 op1
= gen_int_mode (abs_d
, compute_mode
);
3997 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3999 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4001 /* This case is not handled correctly below. */
4002 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4003 compute_mode
, 1, 1);
4007 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4008 && (rem_flag
? smod_pow2_cheap
[compute_mode
]
4009 : sdiv_pow2_cheap
[compute_mode
])
4010 /* We assume that cheap metric is true if the
4011 optab has an expander for this mode. */
4012 && (((rem_flag
? smod_optab
: sdiv_optab
)
4013 ->handlers
[compute_mode
].insn_code
4014 != CODE_FOR_nothing
)
4015 || (sdivmod_optab
->handlers
[compute_mode
]
4016 .insn_code
!= CODE_FOR_nothing
)))
4018 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4022 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4024 return gen_lowpart (mode
, remainder
);
4027 if (sdiv_pow2_cheap
[compute_mode
]
4028 && ((sdiv_optab
->handlers
[compute_mode
].insn_code
4029 != CODE_FOR_nothing
)
4030 || (sdivmod_optab
->handlers
[compute_mode
].insn_code
4031 != CODE_FOR_nothing
)))
4032 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4034 gen_int_mode (abs_d
,
4038 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4040 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4041 negate the quotient. */
4044 insn
= get_last_insn ();
4046 && (set
= single_set (insn
)) != 0
4047 && SET_DEST (set
) == quotient
4048 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4049 << (HOST_BITS_PER_WIDE_INT
- 1)))
4050 set_unique_reg_note (insn
,
4052 gen_rtx_DIV (compute_mode
,
4059 quotient
= expand_unop (compute_mode
, neg_optab
,
4060 quotient
, quotient
, 0);
4063 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4065 choose_multiplier (abs_d
, size
, size
- 1,
4066 &ml
, &post_shift
, &lgup
);
4067 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4071 if (post_shift
>= BITS_PER_WORD
4072 || size
- 1 >= BITS_PER_WORD
)
4075 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4076 + shift_cost
[compute_mode
][size
- 1]
4077 + add_cost
[compute_mode
]);
4078 t1
= gen_int_mode (ml
, compute_mode
);
4079 t1
= expand_mult_highpart (compute_mode
, op0
, t1
,
4081 max_cost
- extra_cost
);
4085 (RSHIFT_EXPR
, compute_mode
, t1
,
4086 build_int_cst (NULL_TREE
, post_shift
),
4089 (RSHIFT_EXPR
, compute_mode
, op0
,
4090 build_int_cst (NULL_TREE
, size
- 1),
4094 = force_operand (gen_rtx_MINUS (compute_mode
,
4099 = force_operand (gen_rtx_MINUS (compute_mode
,
4107 if (post_shift
>= BITS_PER_WORD
4108 || size
- 1 >= BITS_PER_WORD
)
4111 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4112 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4113 + shift_cost
[compute_mode
][size
- 1]
4114 + 2 * add_cost
[compute_mode
]);
4115 t1
= gen_int_mode (ml
, compute_mode
);
4116 t1
= expand_mult_highpart (compute_mode
, op0
, t1
,
4118 max_cost
- extra_cost
);
4121 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4125 (RSHIFT_EXPR
, compute_mode
, t2
,
4126 build_int_cst (NULL_TREE
, post_shift
),
4129 (RSHIFT_EXPR
, compute_mode
, op0
,
4130 build_int_cst (NULL_TREE
, size
- 1),
4134 = force_operand (gen_rtx_MINUS (compute_mode
,
4139 = force_operand (gen_rtx_MINUS (compute_mode
,
4144 else /* Too wide mode to use tricky code */
4147 insn
= get_last_insn ();
4149 && (set
= single_set (insn
)) != 0
4150 && SET_DEST (set
) == quotient
)
4151 set_unique_reg_note (insn
,
4153 gen_rtx_DIV (compute_mode
, op0
, op1
));
4158 delete_insns_since (last
);
4161 case FLOOR_DIV_EXPR
:
4162 case FLOOR_MOD_EXPR
:
4163 /* We will come here only for signed operations. */
4164 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4166 unsigned HOST_WIDE_INT mh
, ml
;
4167 int pre_shift
, lgup
, post_shift
;
4168 HOST_WIDE_INT d
= INTVAL (op1
);
4172 /* We could just as easily deal with negative constants here,
4173 but it does not seem worth the trouble for GCC 2.6. */
4174 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4176 pre_shift
= floor_log2 (d
);
4179 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
4180 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4181 remainder
, 0, OPTAB_LIB_WIDEN
);
4183 return gen_lowpart (mode
, remainder
);
4185 quotient
= expand_shift
4186 (RSHIFT_EXPR
, compute_mode
, op0
,
4187 build_int_cst (NULL_TREE
, pre_shift
),
4194 mh
= choose_multiplier (d
, size
, size
- 1,
4195 &ml
, &post_shift
, &lgup
);
4198 if (post_shift
< BITS_PER_WORD
4199 && size
- 1 < BITS_PER_WORD
)
4202 (RSHIFT_EXPR
, compute_mode
, op0
,
4203 build_int_cst (NULL_TREE
, size
- 1),
4205 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4206 NULL_RTX
, 0, OPTAB_WIDEN
);
4207 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4208 + shift_cost
[compute_mode
][size
- 1]
4209 + 2 * add_cost
[compute_mode
]);
4210 t3
= gen_int_mode (ml
, compute_mode
);
4211 t3
= expand_mult_highpart (compute_mode
, t2
, t3
,
4213 max_cost
- extra_cost
);
4217 (RSHIFT_EXPR
, compute_mode
, t3
,
4218 build_int_cst (NULL_TREE
, post_shift
),
4220 quotient
= expand_binop (compute_mode
, xor_optab
,
4221 t4
, t1
, tquotient
, 0,
4229 rtx nsign
, t1
, t2
, t3
, t4
;
4230 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4231 op0
, constm1_rtx
), NULL_RTX
);
4232 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4234 nsign
= expand_shift
4235 (RSHIFT_EXPR
, compute_mode
, t2
,
4236 build_int_cst (NULL_TREE
, size
- 1),
4238 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4240 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4245 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4247 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4256 delete_insns_since (last
);
4258 /* Try using an instruction that produces both the quotient and
4259 remainder, using truncation. We can easily compensate the quotient
4260 or remainder to get floor rounding, once we have the remainder.
4261 Notice that we compute also the final remainder value here,
4262 and return the result right away. */
4263 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4264 target
= gen_reg_rtx (compute_mode
);
4269 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4270 quotient
= gen_reg_rtx (compute_mode
);
4275 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4276 remainder
= gen_reg_rtx (compute_mode
);
4279 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4280 quotient
, remainder
, 0))
4282 /* This could be computed with a branch-less sequence.
4283 Save that for later. */
4285 rtx label
= gen_label_rtx ();
4286 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4287 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4288 NULL_RTX
, 0, OPTAB_WIDEN
);
4289 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4290 expand_dec (quotient
, const1_rtx
);
4291 expand_inc (remainder
, op1
);
4293 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4296 /* No luck with division elimination or divmod. Have to do it
4297 by conditionally adjusting op0 *and* the result. */
4299 rtx label1
, label2
, label3
, label4
, label5
;
4303 quotient
= gen_reg_rtx (compute_mode
);
4304 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4305 label1
= gen_label_rtx ();
4306 label2
= gen_label_rtx ();
4307 label3
= gen_label_rtx ();
4308 label4
= gen_label_rtx ();
4309 label5
= gen_label_rtx ();
4310 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4311 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4312 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4313 quotient
, 0, OPTAB_LIB_WIDEN
);
4314 if (tem
!= quotient
)
4315 emit_move_insn (quotient
, tem
);
4316 emit_jump_insn (gen_jump (label5
));
4318 emit_label (label1
);
4319 expand_inc (adjusted_op0
, const1_rtx
);
4320 emit_jump_insn (gen_jump (label4
));
4322 emit_label (label2
);
4323 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4324 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4325 quotient
, 0, OPTAB_LIB_WIDEN
);
4326 if (tem
!= quotient
)
4327 emit_move_insn (quotient
, tem
);
4328 emit_jump_insn (gen_jump (label5
));
4330 emit_label (label3
);
4331 expand_dec (adjusted_op0
, const1_rtx
);
4332 emit_label (label4
);
4333 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4334 quotient
, 0, OPTAB_LIB_WIDEN
);
4335 if (tem
!= quotient
)
4336 emit_move_insn (quotient
, tem
);
4337 expand_dec (quotient
, const1_rtx
);
4338 emit_label (label5
);
4346 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4349 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4350 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4351 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4353 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4355 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4356 t3
= gen_reg_rtx (compute_mode
);
4357 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4358 compute_mode
, 1, 1);
4362 lab
= gen_label_rtx ();
4363 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4364 expand_inc (t1
, const1_rtx
);
4369 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4375 /* Try using an instruction that produces both the quotient and
4376 remainder, using truncation. We can easily compensate the
4377 quotient or remainder to get ceiling rounding, once we have the
4378 remainder. Notice that we compute also the final remainder
4379 value here, and return the result right away. */
4380 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4381 target
= gen_reg_rtx (compute_mode
);
4385 remainder
= (REG_P (target
)
4386 ? target
: gen_reg_rtx (compute_mode
));
4387 quotient
= gen_reg_rtx (compute_mode
);
4391 quotient
= (REG_P (target
)
4392 ? target
: gen_reg_rtx (compute_mode
));
4393 remainder
= gen_reg_rtx (compute_mode
);
4396 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4399 /* This could be computed with a branch-less sequence.
4400 Save that for later. */
4401 rtx label
= gen_label_rtx ();
4402 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4403 compute_mode
, label
);
4404 expand_inc (quotient
, const1_rtx
);
4405 expand_dec (remainder
, op1
);
4407 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4410 /* No luck with division elimination or divmod. Have to do it
4411 by conditionally adjusting op0 *and* the result. */
4414 rtx adjusted_op0
, tem
;
4416 quotient
= gen_reg_rtx (compute_mode
);
4417 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4418 label1
= gen_label_rtx ();
4419 label2
= gen_label_rtx ();
4420 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4421 compute_mode
, label1
);
4422 emit_move_insn (quotient
, const0_rtx
);
4423 emit_jump_insn (gen_jump (label2
));
4425 emit_label (label1
);
4426 expand_dec (adjusted_op0
, const1_rtx
);
4427 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4428 quotient
, 1, OPTAB_LIB_WIDEN
);
4429 if (tem
!= quotient
)
4430 emit_move_insn (quotient
, tem
);
4431 expand_inc (quotient
, const1_rtx
);
4432 emit_label (label2
);
4437 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4438 && INTVAL (op1
) >= 0)
4440 /* This is extremely similar to the code for the unsigned case
4441 above. For 2.7 we should merge these variants, but for
4442 2.6.1 I don't want to touch the code for unsigned since that
4443 get used in C. The signed case will only be used by other
4447 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4448 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4449 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4451 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4453 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4454 t3
= gen_reg_rtx (compute_mode
);
4455 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4456 compute_mode
, 1, 1);
4460 lab
= gen_label_rtx ();
4461 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4462 expand_inc (t1
, const1_rtx
);
4467 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4473 /* Try using an instruction that produces both the quotient and
4474 remainder, using truncation. We can easily compensate the
4475 quotient or remainder to get ceiling rounding, once we have the
4476 remainder. Notice that we compute also the final remainder
4477 value here, and return the result right away. */
4478 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4479 target
= gen_reg_rtx (compute_mode
);
4482 remainder
= (REG_P (target
)
4483 ? target
: gen_reg_rtx (compute_mode
));
4484 quotient
= gen_reg_rtx (compute_mode
);
4488 quotient
= (REG_P (target
)
4489 ? target
: gen_reg_rtx (compute_mode
));
4490 remainder
= gen_reg_rtx (compute_mode
);
4493 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4496 /* This could be computed with a branch-less sequence.
4497 Save that for later. */
4499 rtx label
= gen_label_rtx ();
4500 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4501 compute_mode
, label
);
4502 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4503 NULL_RTX
, 0, OPTAB_WIDEN
);
4504 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4505 expand_inc (quotient
, const1_rtx
);
4506 expand_dec (remainder
, op1
);
4508 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4511 /* No luck with division elimination or divmod. Have to do it
4512 by conditionally adjusting op0 *and* the result. */
4514 rtx label1
, label2
, label3
, label4
, label5
;
4518 quotient
= gen_reg_rtx (compute_mode
);
4519 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4520 label1
= gen_label_rtx ();
4521 label2
= gen_label_rtx ();
4522 label3
= gen_label_rtx ();
4523 label4
= gen_label_rtx ();
4524 label5
= gen_label_rtx ();
4525 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4526 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4527 compute_mode
, label1
);
4528 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4529 quotient
, 0, OPTAB_LIB_WIDEN
);
4530 if (tem
!= quotient
)
4531 emit_move_insn (quotient
, tem
);
4532 emit_jump_insn (gen_jump (label5
));
4534 emit_label (label1
);
4535 expand_dec (adjusted_op0
, const1_rtx
);
4536 emit_jump_insn (gen_jump (label4
));
4538 emit_label (label2
);
4539 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4540 compute_mode
, label3
);
4541 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4542 quotient
, 0, OPTAB_LIB_WIDEN
);
4543 if (tem
!= quotient
)
4544 emit_move_insn (quotient
, tem
);
4545 emit_jump_insn (gen_jump (label5
));
4547 emit_label (label3
);
4548 expand_inc (adjusted_op0
, const1_rtx
);
4549 emit_label (label4
);
4550 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4551 quotient
, 0, OPTAB_LIB_WIDEN
);
4552 if (tem
!= quotient
)
4553 emit_move_insn (quotient
, tem
);
4554 expand_inc (quotient
, const1_rtx
);
4555 emit_label (label5
);
4560 case EXACT_DIV_EXPR
:
4561 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4563 HOST_WIDE_INT d
= INTVAL (op1
);
4564 unsigned HOST_WIDE_INT ml
;
4568 pre_shift
= floor_log2 (d
& -d
);
4569 ml
= invert_mod2n (d
>> pre_shift
, size
);
4570 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4571 build_int_cst (NULL_TREE
, pre_shift
),
4572 NULL_RTX
, unsignedp
);
4573 quotient
= expand_mult (compute_mode
, t1
,
4574 gen_int_mode (ml
, compute_mode
),
4577 insn
= get_last_insn ();
4578 set_unique_reg_note (insn
,
4580 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4586 case ROUND_DIV_EXPR
:
4587 case ROUND_MOD_EXPR
:
4592 label
= gen_label_rtx ();
4593 quotient
= gen_reg_rtx (compute_mode
);
4594 remainder
= gen_reg_rtx (compute_mode
);
4595 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4598 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4599 quotient
, 1, OPTAB_LIB_WIDEN
);
4600 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4601 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4602 remainder
, 1, OPTAB_LIB_WIDEN
);
4604 tem
= plus_constant (op1
, -1);
4605 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4606 build_int_cst (NULL_TREE
, 1),
4608 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4609 expand_inc (quotient
, const1_rtx
);
4610 expand_dec (remainder
, op1
);
4615 rtx abs_rem
, abs_op1
, tem
, mask
;
4617 label
= gen_label_rtx ();
4618 quotient
= gen_reg_rtx (compute_mode
);
4619 remainder
= gen_reg_rtx (compute_mode
);
4620 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4623 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4624 quotient
, 0, OPTAB_LIB_WIDEN
);
4625 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4626 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4627 remainder
, 0, OPTAB_LIB_WIDEN
);
4629 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4630 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4631 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4632 build_int_cst (NULL_TREE
, 1),
4634 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4635 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4636 NULL_RTX
, 0, OPTAB_WIDEN
);
4637 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4638 build_int_cst (NULL_TREE
, size
- 1),
4640 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4641 NULL_RTX
, 0, OPTAB_WIDEN
);
4642 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4643 NULL_RTX
, 0, OPTAB_WIDEN
);
4644 expand_inc (quotient
, tem
);
4645 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4646 NULL_RTX
, 0, OPTAB_WIDEN
);
4647 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4648 NULL_RTX
, 0, OPTAB_WIDEN
);
4649 expand_dec (remainder
, tem
);
4652 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4660 if (target
&& GET_MODE (target
) != compute_mode
)
4665 /* Try to produce the remainder without producing the quotient.
4666 If we seem to have a divmod pattern that does not require widening,
4667 don't try widening here. We should really have a WIDEN argument
4668 to expand_twoval_binop, since what we'd really like to do here is
4669 1) try a mod insn in compute_mode
4670 2) try a divmod insn in compute_mode
4671 3) try a div insn in compute_mode and multiply-subtract to get
4673 4) try the same things with widening allowed. */
4675 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4678 ((optab2
->handlers
[compute_mode
].insn_code
4679 != CODE_FOR_nothing
)
4680 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4683 /* No luck there. Can we do remainder and divide at once
4684 without a library call? */
4685 remainder
= gen_reg_rtx (compute_mode
);
4686 if (! expand_twoval_binop ((unsignedp
4690 NULL_RTX
, remainder
, unsignedp
))
4695 return gen_lowpart (mode
, remainder
);
4698 /* Produce the quotient. Try a quotient insn, but not a library call.
4699 If we have a divmod in this mode, use it in preference to widening
4700 the div (for this test we assume it will not fail). Note that optab2
4701 is set to the one of the two optabs that the call below will use. */
4703 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4704 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4706 ((optab2
->handlers
[compute_mode
].insn_code
4707 != CODE_FOR_nothing
)
4708 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4712 /* No luck there. Try a quotient-and-remainder insn,
4713 keeping the quotient alone. */
4714 quotient
= gen_reg_rtx (compute_mode
);
4715 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4717 quotient
, NULL_RTX
, unsignedp
))
4721 /* Still no luck. If we are not computing the remainder,
4722 use a library call for the quotient. */
4723 quotient
= sign_expand_binop (compute_mode
,
4724 udiv_optab
, sdiv_optab
,
4726 unsignedp
, OPTAB_LIB_WIDEN
);
4733 if (target
&& GET_MODE (target
) != compute_mode
)
4738 /* No divide instruction either. Use library for remainder. */
4739 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4741 unsignedp
, OPTAB_LIB_WIDEN
);
4742 /* No remainder function. Try a quotient-and-remainder
4743 function, keeping the remainder. */
4746 remainder
= gen_reg_rtx (compute_mode
);
4747 if (!expand_twoval_binop_libfunc
4748 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4750 NULL_RTX
, remainder
,
4751 unsignedp
? UMOD
: MOD
))
4752 remainder
= NULL_RTX
;
4757 /* We divided. Now finish doing X - Y * (X / Y). */
4758 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4759 NULL_RTX
, unsignedp
);
4760 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4761 remainder
, target
, unsignedp
,
4766 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4769 /* Return a tree node with data type TYPE, describing the value of X.
4770 Usually this is an VAR_DECL, if there is no obvious better choice.
4771 X may be an expression, however we only support those expressions
4772 generated by loop.c. */
4775 make_tree (tree type
, rtx x
)
4779 switch (GET_CODE (x
))
4783 HOST_WIDE_INT hi
= 0;
4786 && !(TYPE_UNSIGNED (type
)
4787 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4788 < HOST_BITS_PER_WIDE_INT
)))
4791 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4797 if (GET_MODE (x
) == VOIDmode
)
4798 t
= build_int_cst_wide (type
,
4799 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4804 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4805 t
= build_real (type
, d
);
4816 units
= CONST_VECTOR_NUNITS (x
);
4818 /* Build a tree with vector elements. */
4819 for (i
= units
- 1; i
>= 0; --i
)
4821 elt
= CONST_VECTOR_ELT (x
, i
);
4822 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4825 return build_vector (type
, t
);
4829 return fold (build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4830 make_tree (type
, XEXP (x
, 1))));
4833 return fold (build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4834 make_tree (type
, XEXP (x
, 1))));
4837 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4840 return fold (build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4841 make_tree (type
, XEXP (x
, 1))));
4844 return fold (build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4845 make_tree (type
, XEXP (x
, 1))));
4848 t
= lang_hooks
.types
.unsigned_type (type
);
4849 return fold (convert (type
,
4850 build2 (RSHIFT_EXPR
, t
,
4851 make_tree (t
, XEXP (x
, 0)),
4852 make_tree (type
, XEXP (x
, 1)))));
4855 t
= lang_hooks
.types
.signed_type (type
);
4856 return fold (convert (type
,
4857 build2 (RSHIFT_EXPR
, t
,
4858 make_tree (t
, XEXP (x
, 0)),
4859 make_tree (type
, XEXP (x
, 1)))));
4862 if (TREE_CODE (type
) != REAL_TYPE
)
4863 t
= lang_hooks
.types
.signed_type (type
);
4867 return fold (convert (type
,
4868 build2 (TRUNC_DIV_EXPR
, t
,
4869 make_tree (t
, XEXP (x
, 0)),
4870 make_tree (t
, XEXP (x
, 1)))));
4872 t
= lang_hooks
.types
.unsigned_type (type
);
4873 return fold (convert (type
,
4874 build2 (TRUNC_DIV_EXPR
, t
,
4875 make_tree (t
, XEXP (x
, 0)),
4876 make_tree (t
, XEXP (x
, 1)))));
4880 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
4881 GET_CODE (x
) == ZERO_EXTEND
);
4882 return fold (convert (type
, make_tree (t
, XEXP (x
, 0))));
4885 t
= build_decl (VAR_DECL
, NULL_TREE
, type
);
4887 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4888 ptr_mode. So convert. */
4889 if (POINTER_TYPE_P (type
))
4890 x
= convert_memory_address (TYPE_MODE (type
), x
);
4892 /* Note that we do *not* use SET_DECL_RTL here, because we do not
4893 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
4900 /* Check whether the multiplication X * MULT + ADD overflows.
4901 X, MULT and ADD must be CONST_*.
4902 MODE is the machine mode for the computation.
4903 X and MULT must have mode MODE. ADD may have a different mode.
4904 So can X (defaults to same as MODE).
4905 UNSIGNEDP is nonzero to do unsigned multiplication. */
4908 const_mult_add_overflow_p (rtx x
, rtx mult
, rtx add
,
4909 enum machine_mode mode
, int unsignedp
)
4911 tree type
, mult_type
, add_type
, result
;
4913 type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4915 /* In order to get a proper overflow indication from an unsigned
4916 type, we have to pretend that it's a sizetype. */
4920 /* FIXME:It would be nice if we could step directly from this
4921 type to its sizetype equivalent. */
4922 mult_type
= build_distinct_type_copy (type
);
4923 TYPE_IS_SIZETYPE (mult_type
) = 1;
4926 add_type
= (GET_MODE (add
) == VOIDmode
? mult_type
4927 : lang_hooks
.types
.type_for_mode (GET_MODE (add
), unsignedp
));
4929 result
= fold (build2 (PLUS_EXPR
, mult_type
,
4930 fold (build2 (MULT_EXPR
, mult_type
,
4931 make_tree (mult_type
, x
),
4932 make_tree (mult_type
, mult
))),
4933 make_tree (add_type
, add
)));
4935 return TREE_CONSTANT_OVERFLOW (result
);
4938 /* Return an rtx representing the value of X * MULT + ADD.
4939 TARGET is a suggestion for where to store the result (an rtx).
4940 MODE is the machine mode for the computation.
4941 X and MULT must have mode MODE. ADD may have a different mode.
4942 So can X (defaults to same as MODE).
4943 UNSIGNEDP is nonzero to do unsigned multiplication.
4944 This may emit insns. */
4947 expand_mult_add (rtx x
, rtx target
, rtx mult
, rtx add
, enum machine_mode mode
,
4950 tree type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4951 tree add_type
= (GET_MODE (add
) == VOIDmode
4952 ? type
: lang_hooks
.types
.type_for_mode (GET_MODE (add
),
4954 tree result
= fold (build2 (PLUS_EXPR
, type
,
4955 fold (build2 (MULT_EXPR
, type
,
4956 make_tree (type
, x
),
4957 make_tree (type
, mult
))),
4958 make_tree (add_type
, add
)));
4960 return expand_expr (result
, target
, VOIDmode
, 0);
4963 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4964 and returning TARGET.
4966 If TARGET is 0, a pseudo-register or constant is returned. */
4969 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
4973 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
4974 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
4976 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4980 else if (tem
!= target
)
4981 emit_move_insn (target
, tem
);
4985 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4986 and storing in TARGET. Normally return TARGET.
4987 Return 0 if that cannot be done.
4989 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4990 it is VOIDmode, they cannot both be CONST_INT.
4992 UNSIGNEDP is for the case where we have to widen the operands
4993 to perform the operation. It says to use zero-extension.
4995 NORMALIZEP is 1 if we should convert the result to be either zero
4996 or one. Normalize is -1 if we should convert the result to be
4997 either zero or -1. If NORMALIZEP is zero, the result will be left
4998 "raw" out of the scc insn. */
5001 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5002 enum machine_mode mode
, int unsignedp
, int normalizep
)
5005 enum insn_code icode
;
5006 enum machine_mode compare_mode
;
5007 enum machine_mode target_mode
= GET_MODE (target
);
5009 rtx last
= get_last_insn ();
5010 rtx pattern
, comparison
;
5013 code
= unsigned_condition (code
);
5015 /* If one operand is constant, make it the second one. Only do this
5016 if the other operand is not constant as well. */
5018 if (swap_commutative_operands_p (op0
, op1
))
5023 code
= swap_condition (code
);
5026 if (mode
== VOIDmode
)
5027 mode
= GET_MODE (op0
);
5029 /* For some comparisons with 1 and -1, we can convert this to
5030 comparisons with zero. This will often produce more opportunities for
5031 store-flag insns. */
5036 if (op1
== const1_rtx
)
5037 op1
= const0_rtx
, code
= LE
;
5040 if (op1
== constm1_rtx
)
5041 op1
= const0_rtx
, code
= LT
;
5044 if (op1
== const1_rtx
)
5045 op1
= const0_rtx
, code
= GT
;
5048 if (op1
== constm1_rtx
)
5049 op1
= const0_rtx
, code
= GE
;
5052 if (op1
== const1_rtx
)
5053 op1
= const0_rtx
, code
= NE
;
5056 if (op1
== const1_rtx
)
5057 op1
= const0_rtx
, code
= EQ
;
5063 /* If we are comparing a double-word integer with zero or -1, we can
5064 convert the comparison into one involving a single word. */
5065 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5066 && GET_MODE_CLASS (mode
) == MODE_INT
5067 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5069 if ((code
== EQ
|| code
== NE
)
5070 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5072 rtx op00
, op01
, op0both
;
5074 /* Do a logical OR or AND of the two words and compare the result. */
5075 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5076 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5077 op0both
= expand_binop (word_mode
,
5078 op1
== const0_rtx
? ior_optab
: and_optab
,
5079 op00
, op01
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
5082 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
5083 unsignedp
, normalizep
);
5085 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5089 /* If testing the sign bit, can just test on high word. */
5090 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5091 subreg_highpart_offset (word_mode
, mode
));
5092 return emit_store_flag (target
, code
, op0h
, op1
, word_mode
,
5093 unsignedp
, normalizep
);
5097 /* From now on, we won't change CODE, so set ICODE now. */
5098 icode
= setcc_gen_code
[(int) code
];
5100 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5101 complement of A (for GE) and shifting the sign bit to the low bit. */
5102 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5103 && GET_MODE_CLASS (mode
) == MODE_INT
5104 && (normalizep
|| STORE_FLAG_VALUE
== 1
5105 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5106 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5107 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
5111 /* If the result is to be wider than OP0, it is best to convert it
5112 first. If it is to be narrower, it is *incorrect* to convert it
5114 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5116 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5120 if (target_mode
!= mode
)
5124 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5125 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5126 ? 0 : subtarget
), 0);
5128 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5129 /* If we are supposed to produce a 0/1 value, we want to do
5130 a logical shift from the sign bit to the low-order bit; for
5131 a -1/0 value, we do an arithmetic shift. */
5132 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5133 size_int (GET_MODE_BITSIZE (mode
) - 1),
5134 subtarget
, normalizep
!= -1);
5136 if (mode
!= target_mode
)
5137 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5142 if (icode
!= CODE_FOR_nothing
)
5144 insn_operand_predicate_fn pred
;
5146 /* We think we may be able to do this with a scc insn. Emit the
5147 comparison and then the scc insn. */
5149 do_pending_stack_adjust ();
5150 last
= get_last_insn ();
5153 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
5154 if (CONSTANT_P (comparison
))
5156 switch (GET_CODE (comparison
))
5159 if (comparison
== const0_rtx
)
5163 #ifdef FLOAT_STORE_FLAG_VALUE
5165 if (comparison
== CONST0_RTX (GET_MODE (comparison
)))
5173 if (normalizep
== 1)
5175 if (normalizep
== -1)
5177 return const_true_rtx
;
5180 /* The code of COMPARISON may not match CODE if compare_from_rtx
5181 decided to swap its operands and reverse the original code.
5183 We know that compare_from_rtx returns either a CONST_INT or
5184 a new comparison code, so it is safe to just extract the
5185 code from COMPARISON. */
5186 code
= GET_CODE (comparison
);
5188 /* Get a reference to the target in the proper mode for this insn. */
5189 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
5191 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
5192 if (optimize
|| ! (*pred
) (subtarget
, compare_mode
))
5193 subtarget
= gen_reg_rtx (compare_mode
);
5195 pattern
= GEN_FCN (icode
) (subtarget
);
5198 emit_insn (pattern
);
5200 /* If we are converting to a wider mode, first convert to
5201 TARGET_MODE, then normalize. This produces better combining
5202 opportunities on machines that have a SIGN_EXTRACT when we are
5203 testing a single bit. This mostly benefits the 68k.
5205 If STORE_FLAG_VALUE does not have the sign bit set when
5206 interpreted in COMPARE_MODE, we can do this conversion as
5207 unsigned, which is usually more efficient. */
5208 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
5210 convert_move (target
, subtarget
,
5211 (GET_MODE_BITSIZE (compare_mode
)
5212 <= HOST_BITS_PER_WIDE_INT
)
5213 && 0 == (STORE_FLAG_VALUE
5214 & ((HOST_WIDE_INT
) 1
5215 << (GET_MODE_BITSIZE (compare_mode
) -1))));
5217 compare_mode
= target_mode
;
5222 /* If we want to keep subexpressions around, don't reuse our
5228 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
5229 we don't have to do anything. */
5230 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5232 /* STORE_FLAG_VALUE might be the most negative number, so write
5233 the comparison this way to avoid a compiler-time warning. */
5234 else if (- normalizep
== STORE_FLAG_VALUE
)
5235 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
5237 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
5238 makes it hard to use a value of just the sign bit due to
5239 ANSI integer constant typing rules. */
5240 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
5241 && (STORE_FLAG_VALUE
5242 & ((HOST_WIDE_INT
) 1
5243 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
5244 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
5245 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
5246 subtarget
, normalizep
== 1);
5249 gcc_assert (STORE_FLAG_VALUE
& 1);
5251 op0
= expand_and (compare_mode
, op0
, const1_rtx
, subtarget
);
5252 if (normalizep
== -1)
5253 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
5256 /* If we were converting to a smaller mode, do the
5258 if (target_mode
!= compare_mode
)
5260 convert_move (target
, op0
, 0);
5268 delete_insns_since (last
);
5270 /* If optimizing, use different pseudo registers for each insn, instead
5271 of reusing the same pseudo. This leads to better CSE, but slows
5272 down the compiler, since there are more pseudos */
5273 subtarget
= (!optimize
5274 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5276 /* If we reached here, we can't do this with a scc insn. However, there
5277 are some comparisons that can be done directly. For example, if
5278 this is an equality comparison of integers, we can try to exclusive-or
5279 (or subtract) the two operands and use a recursive call to try the
5280 comparison with zero. Don't do any of these cases if branches are
5284 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
5285 && op1
!= const0_rtx
)
5287 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5291 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5294 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5295 mode
, unsignedp
, normalizep
);
5297 delete_insns_since (last
);
5301 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5302 the constant zero. Reject all other comparisons at this point. Only
5303 do LE and GT if branches are expensive since they are expensive on
5304 2-operand machines. */
5306 if (BRANCH_COST
== 0
5307 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
5308 || (code
!= EQ
&& code
!= NE
5309 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
5312 /* See what we need to return. We can only return a 1, -1, or the
5315 if (normalizep
== 0)
5317 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5318 normalizep
= STORE_FLAG_VALUE
;
5320 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5321 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5322 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
5328 /* Try to put the result of the comparison in the sign bit. Assume we can't
5329 do the necessary operation below. */
5333 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5334 the sign bit set. */
5338 /* This is destructive, so SUBTARGET can't be OP0. */
5339 if (rtx_equal_p (subtarget
, op0
))
5342 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5345 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5349 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5350 number of bits in the mode of OP0, minus one. */
5354 if (rtx_equal_p (subtarget
, op0
))
5357 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5358 size_int (GET_MODE_BITSIZE (mode
) - 1),
5360 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5364 if (code
== EQ
|| code
== NE
)
5366 /* For EQ or NE, one way to do the comparison is to apply an operation
5367 that converts the operand into a positive number if it is nonzero
5368 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5369 for NE we negate. This puts the result in the sign bit. Then we
5370 normalize with a shift, if needed.
5372 Two operations that can do the above actions are ABS and FFS, so try
5373 them. If that doesn't work, and MODE is smaller than a full word,
5374 we can use zero-extension to the wider mode (an unsigned conversion)
5375 as the operation. */
5377 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5378 that is compensated by the subsequent overflow when subtracting
5381 if (abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5382 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5383 else if (ffs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5384 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5385 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5387 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5394 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5397 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5400 /* If we couldn't do it that way, for NE we can "or" the two's complement
5401 of the value with itself. For EQ, we take the one's complement of
5402 that "or", which is an extra insn, so we only handle EQ if branches
5405 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
5407 if (rtx_equal_p (subtarget
, op0
))
5410 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5411 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5414 if (tem
&& code
== EQ
)
5415 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5419 if (tem
&& normalizep
)
5420 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5421 size_int (GET_MODE_BITSIZE (mode
) - 1),
5422 subtarget
, normalizep
== 1);
5426 if (GET_MODE (tem
) != target_mode
)
5428 convert_move (target
, tem
, 0);
5431 else if (!subtarget
)
5433 emit_move_insn (target
, tem
);
5438 delete_insns_since (last
);
5443 /* Like emit_store_flag, but always succeeds. */
5446 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5447 enum machine_mode mode
, int unsignedp
, int normalizep
)
5451 /* First see if emit_store_flag can do the job. */
5452 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5456 if (normalizep
== 0)
5459 /* If this failed, we have to do this with set/compare/jump/set code. */
5462 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5463 target
= gen_reg_rtx (GET_MODE (target
));
5465 emit_move_insn (target
, const1_rtx
);
5466 label
= gen_label_rtx ();
5467 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5470 emit_move_insn (target
, const0_rtx
);
5476 /* Perform possibly multi-word comparison and conditional jump to LABEL
5477 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
5479 The algorithm is based on the code in expr.c:do_jump.
5481 Note that this does not perform a general comparison. Only variants
5482 generated within expmed.c are correctly handled, others abort (but could
5483 be handled if needed). */
5486 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5489 /* If this mode is an integer too wide to compare properly,
5490 compare word by word. Rely on cse to optimize constant cases. */
5492 if (GET_MODE_CLASS (mode
) == MODE_INT
5493 && ! can_compare_p (op
, mode
, ccp_jump
))
5495 rtx label2
= gen_label_rtx ();
5500 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
5504 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
5508 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
5512 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
5516 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
5519 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
5520 that's the only equality operations we do */
5522 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5523 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
5527 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5528 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
5535 emit_label (label2
);
5538 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);