1 /* Target Code for R8C/M16C/M32C
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
48 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree
interrupt_handler (tree
*, tree
, tree
, int, bool *);
64 static int interrupt_p (tree node
);
65 static bool m32c_asm_integer (rtx
, unsigned int, int);
66 static int m32c_comp_type_attributes (tree
, tree
);
67 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
68 static struct machine_function
*m32c_init_machine_status (void);
69 static void m32c_insert_attributes (tree
, tree
*);
70 static bool m32c_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
72 static bool m32c_promote_prototypes (tree
);
73 static int m32c_pushm_popm (Push_Pop_Type
);
74 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS
*);
75 static rtx
m32c_struct_value_rtx (tree
, int);
76 static rtx
m32c_subreg (enum machine_mode
, rtx
, enum machine_mode
, int);
77 static int need_to_save (int);
79 #define streq(a,b) (strcmp ((a), (b)) == 0)
81 /* Internal support routines */
83 /* Debugging statements are tagged with DEBUG0 only so that they can
84 be easily enabled individually, by replacing the '0' with '1' as
90 /* This is needed by some of the commented-out debug statements
92 static char const *class_names
[LIM_REG_CLASSES
] = REG_CLASS_NAMES
;
94 static int class_contents
[LIM_REG_CLASSES
][1] = REG_CLASS_CONTENTS
;
96 /* These are all to support encode_pattern(). */
97 static char pattern
[30], *patternp
;
98 static GTY(()) rtx patternr
[30];
99 #define RTX_IS(x) (streq (pattern, x))
101 /* Some macros to simplify the logic throughout this file. */
102 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
103 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
105 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
106 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
108 /* We do most RTX matching by converting the RTX into a string, and
109 using string compares. This vastly simplifies the logic in many of
110 the functions in this file.
112 On exit, pattern[] has the encoded string (use RTX_IS("...") to
113 compare it) and patternr[] has pointers to the nodes in the RTX
114 corresponding to each character in the encoded string. The latter
115 is mostly used by print_operand().
117 Unrecognized patterns have '?' in them; this shows up when the
118 assembler complains about syntax errors.
122 encode_pattern_1 (rtx x
)
126 if (patternp
== pattern
+ sizeof (pattern
) - 2)
132 patternr
[patternp
- pattern
] = x
;
134 switch (GET_CODE (x
))
140 if (GET_MODE_SIZE (GET_MODE (x
)) !=
141 GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))))
143 encode_pattern_1 (XEXP (x
, 0));
148 encode_pattern_1 (XEXP (x
, 0));
152 encode_pattern_1 (XEXP (x
, 0));
153 encode_pattern_1 (XEXP (x
, 1));
157 encode_pattern_1 (XEXP (x
, 0));
161 encode_pattern_1 (XEXP (x
, 0));
165 encode_pattern_1 (XEXP (x
, 0));
166 encode_pattern_1 (XEXP (x
, 1));
170 encode_pattern_1 (XEXP (x
, 0));
187 *patternp
++ = '0' + XCINT (x
, 1, UNSPEC
);
188 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
189 encode_pattern_1 (XVECEXP (x
, 0, i
));
196 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
197 encode_pattern_1 (XVECEXP (x
, 0, i
));
201 encode_pattern_1 (XEXP (x
, 0));
203 encode_pattern_1 (XEXP (x
, 1));
208 fprintf (stderr
, "can't encode pattern %s\n",
209 GET_RTX_NAME (GET_CODE (x
)));
218 encode_pattern (rtx x
)
221 encode_pattern_1 (x
);
225 /* Since register names indicate the mode they're used in, we need a
226 way to determine which name to refer to the register with. Called
227 by print_operand(). */
230 reg_name_with_mode (int regno
, enum machine_mode mode
)
232 int mlen
= GET_MODE_SIZE (mode
);
233 if (regno
== R0_REGNO
&& mlen
== 1)
235 if (regno
== R0_REGNO
&& (mlen
== 3 || mlen
== 4))
237 if (regno
== R0_REGNO
&& mlen
== 6)
239 if (regno
== R0_REGNO
&& mlen
== 8)
241 if (regno
== R1_REGNO
&& mlen
== 1)
243 if (regno
== R1_REGNO
&& (mlen
== 3 || mlen
== 4))
245 if (regno
== A0_REGNO
&& TARGET_A16
&& (mlen
== 3 || mlen
== 4))
247 return reg_names
[regno
];
250 /* How many bytes a register uses on stack when it's pushed. We need
251 to know this because the push opcode needs to explicitly indicate
252 the size of the register, even though the name of the register
253 already tells it that. Used by m32c_output_reg_{push,pop}, which
254 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
257 reg_push_size (int regno
)
282 static int *class_sizes
= 0;
284 /* Given two register classes, find the largest intersection between
285 them. If there is no intersection, return RETURNED_IF_EMPTY
288 reduce_class (int original_class
, int limiting_class
, int returned_if_empty
)
290 int cc
= class_contents
[original_class
][0];
291 int i
, best
= NO_REGS
;
294 if (original_class
== limiting_class
)
295 return original_class
;
300 class_sizes
= (int *) xmalloc (LIM_REG_CLASSES
* sizeof (int));
301 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
304 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
305 if (class_contents
[i
][0] & (1 << r
))
310 cc
&= class_contents
[limiting_class
][0];
311 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
313 int ic
= class_contents
[i
][0];
316 if (best_size
< class_sizes
[i
])
319 best_size
= class_sizes
[i
];
324 return returned_if_empty
;
328 /* Returns TRUE If there are any registers that exist in both register
331 classes_intersect (int class1
, int class2
)
333 return class_contents
[class1
][0] & class_contents
[class2
][0];
336 /* Used by m32c_register_move_cost to determine if a move is
337 impossibly expensive. */
339 class_can_hold_mode (int class, enum machine_mode mode
)
341 /* Cache the results: 0=untested 1=no 2=yes */
342 static char results
[LIM_REG_CLASSES
][MAX_MACHINE_MODE
];
343 if (results
[class][mode
] == 0)
346 results
[class][mode
] = 1;
347 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
348 if (class_contents
[class][0] & (1 << r
)
349 && HARD_REGNO_MODE_OK (r
, mode
))
352 n
= HARD_REGNO_NREGS (r
, mode
);
353 for (i
= 1; i
< n
; i
++)
354 if (!(class_contents
[class][0] & (1 << (r
+ i
))))
358 results
[class][mode
] = 2;
364 fprintf (stderr
, "class %s can hold %s? %s\n",
365 class_names
[class], mode_name
[mode
],
366 (results
[class][mode
] == 2) ? "yes" : "no");
368 return results
[class][mode
] == 2;
371 /* Run-time Target Specification. */
373 /* Memregs are memory locations that gcc treats like general
374 registers, as there are a limited number of true registers and the
375 m32c families can use memory in most places that registers can be
378 However, since memory accesses are more expensive than registers,
379 we allow the user to limit the number of memregs available, in
380 order to try to persuade gcc to try harder to use real registers.
382 Memregs are provided by m32c-lib1.S.
385 int target_memregs
= 16;
386 static bool target_memregs_set
= FALSE
;
387 int ok_to_change_target_memregs
= TRUE
;
389 #undef TARGET_HANDLE_OPTION
390 #define TARGET_HANDLE_OPTION m32c_handle_option
392 m32c_handle_option (size_t code
,
393 const char *arg ATTRIBUTE_UNUSED
,
394 int value ATTRIBUTE_UNUSED
)
396 if (code
== OPT_memregs_
)
398 target_memregs_set
= TRUE
;
399 target_memregs
= atoi (arg
);
404 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
405 provide a default. */
407 m32c_override_options (void)
409 if (target_memregs_set
)
411 if (target_memregs
< 0 || target_memregs
> 16)
412 error ("invalid target memregs value '%d'", target_memregs
);
418 /* Defining data structures for per-function information */
420 /* The usual; we set up our machine_function data. */
421 static struct machine_function
*
422 m32c_init_machine_status (void)
424 struct machine_function
*machine
;
426 (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
431 /* Implements INIT_EXPANDERS. We just set up to call the above
434 m32c_init_expanders (void)
436 init_machine_status
= m32c_init_machine_status
;
441 #undef TARGET_PROMOTE_FUNCTION_RETURN
442 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
444 m32c_promote_function_return (tree fntype ATTRIBUTE_UNUSED
)
449 /* Register Basics */
451 /* Basic Characteristics of Registers */
453 /* Whether a mode fits in a register is complex enough to warrant a
462 } nregs_table
[FIRST_PSEUDO_REGISTER
] =
464 { 1, 1, 2, 2, 4 }, /* r0 */
465 { 0, 1, 0, 0, 0 }, /* r2 */
466 { 1, 1, 2, 2, 0 }, /* r1 */
467 { 0, 1, 0, 0, 0 }, /* r3 */
468 { 0, 1, 1, 0, 0 }, /* a0 */
469 { 0, 1, 1, 0, 0 }, /* a1 */
470 { 0, 1, 1, 0, 0 }, /* sb */
471 { 0, 1, 1, 0, 0 }, /* fb */
472 { 0, 1, 1, 0, 0 }, /* sp */
473 { 1, 1, 1, 0, 0 }, /* pc */
474 { 0, 0, 0, 0, 0 }, /* fl */
475 { 1, 1, 1, 0, 0 }, /* ap */
476 { 1, 1, 2, 2, 4 }, /* mem0 */
477 { 1, 1, 2, 2, 4 }, /* mem1 */
478 { 1, 1, 2, 2, 4 }, /* mem2 */
479 { 1, 1, 2, 2, 4 }, /* mem3 */
480 { 1, 1, 2, 2, 4 }, /* mem4 */
481 { 1, 1, 2, 2, 0 }, /* mem5 */
482 { 1, 1, 2, 2, 0 }, /* mem6 */
483 { 1, 1, 0, 0, 0 }, /* mem7 */
486 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
487 available memregs, and select which registers need to be preserved
488 across calls based on the chip family. */
491 m32c_conditional_register_usage (void)
495 if (0 <= target_memregs
&& target_memregs
<= 16)
497 /* The command line option is bytes, but our "registers" are
499 for (i
= target_memregs
/2; i
< 8; i
++)
501 fixed_regs
[MEM0_REGNO
+ i
] = 1;
502 CLEAR_HARD_REG_BIT (reg_class_contents
[MEM_REGS
], MEM0_REGNO
+ i
);
506 /* M32CM and M32C preserve more registers across function calls. */
509 call_used_regs
[R1_REGNO
] = 0;
510 call_used_regs
[R2_REGNO
] = 0;
511 call_used_regs
[R3_REGNO
] = 0;
512 call_used_regs
[A0_REGNO
] = 0;
513 call_used_regs
[A1_REGNO
] = 0;
517 /* How Values Fit in Registers */
519 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
520 different registers are different sizes from each other, *and* may
521 be different sizes in different chip families. */
523 m32c_hard_regno_nregs (int regno
, enum machine_mode mode
)
525 if (regno
== FLG_REGNO
&& mode
== CCmode
)
527 if (regno
>= FIRST_PSEUDO_REGISTER
)
528 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
530 if (regno
>= MEM0_REGNO
&& regno
<= MEM7_REGNO
)
531 return (GET_MODE_SIZE (mode
) + 1) / 2;
533 if (GET_MODE_SIZE (mode
) <= 1)
534 return nregs_table
[regno
].qi_regs
;
535 if (GET_MODE_SIZE (mode
) <= 2)
536 return nregs_table
[regno
].hi_regs
;
537 if (regno
== A0_REGNO
&& mode
== PSImode
&& TARGET_A16
)
539 if ((GET_MODE_SIZE (mode
) <= 3 || mode
== PSImode
) && TARGET_A24
)
540 return nregs_table
[regno
].pi_regs
;
541 if (GET_MODE_SIZE (mode
) <= 4)
542 return nregs_table
[regno
].si_regs
;
543 if (GET_MODE_SIZE (mode
) <= 8)
544 return nregs_table
[regno
].di_regs
;
548 /* Implements HARD_REGNO_MODE_OK. The above function does the work
549 already; just test its return value. */
551 m32c_hard_regno_ok (int regno
, enum machine_mode mode
)
553 return m32c_hard_regno_nregs (regno
, mode
) != 0;
556 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
557 registers are all different sizes. However, since most modes are
558 bigger than our registers anyway, it's easier to implement this
559 function that way, leaving QImode as the only unique case. */
561 m32c_modes_tieable_p (enum machine_mode m1
, enum machine_mode m2
)
563 if (GET_MODE_SIZE (m1
) == GET_MODE_SIZE (m2
))
567 if (m1
== QImode
|| m2
== QImode
)
574 /* Register Classes */
576 /* Implements REGNO_REG_CLASS. */
578 m32c_regno_reg_class (int regno
)
602 if (IS_MEM_REGNO (regno
))
608 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
609 for certain chip families. */
611 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED
, const char *s
)
613 if (memcmp (s
, "Rsp", 3) == 0)
615 if (memcmp (s
, "Rfb", 3) == 0)
617 if (memcmp (s
, "Rsb", 3) == 0)
619 if (memcmp (s
, "Rcr", 3) == 0)
620 return TARGET_A16
? CR_REGS
: NO_REGS
;
621 if (memcmp (s
, "Rcl", 3) == 0)
622 return TARGET_A24
? CR_REGS
: NO_REGS
;
623 if (memcmp (s
, "R0w", 3) == 0)
625 if (memcmp (s
, "R1w", 3) == 0)
627 if (memcmp (s
, "R2w", 3) == 0)
629 if (memcmp (s
, "R3w", 3) == 0)
631 if (memcmp (s
, "R02", 3) == 0)
633 if (memcmp (s
, "R03", 3) == 0)
635 if (memcmp (s
, "Rdi", 3) == 0)
637 if (memcmp (s
, "Rhl", 3) == 0)
639 if (memcmp (s
, "R23", 3) == 0)
641 if (memcmp (s
, "Ra0", 3) == 0)
643 if (memcmp (s
, "Ra1", 3) == 0)
645 if (memcmp (s
, "Raa", 3) == 0)
647 if (memcmp (s
, "Raw", 3) == 0)
648 return TARGET_A16
? A_REGS
: NO_REGS
;
649 if (memcmp (s
, "Ral", 3) == 0)
650 return TARGET_A24
? A_REGS
: NO_REGS
;
651 if (memcmp (s
, "Rqi", 3) == 0)
653 if (memcmp (s
, "Rad", 3) == 0)
655 if (memcmp (s
, "Rsi", 3) == 0)
657 if (memcmp (s
, "Rhi", 3) == 0)
659 if (memcmp (s
, "Rhc", 3) == 0)
661 if (memcmp (s
, "Rra", 3) == 0)
663 if (memcmp (s
, "Rfl", 3) == 0)
665 if (memcmp (s
, "Rmm", 3) == 0)
667 if (fixed_regs
[MEM0_REGNO
])
672 /* PSImode registers - i.e. whatever can hold a pointer. */
673 if (memcmp (s
, "Rpi", 3) == 0)
678 return RA_REGS
; /* r2r0 and r3r1 can hold pointers. */
681 /* We handle this one as an EXTRA_CONSTRAINT. */
682 if (memcmp (s
, "Rpa", 3) == 0)
687 fprintf(stderr
, "unrecognized R constraint: %.3s\n", s
);
694 /* Implements REGNO_OK_FOR_BASE_P. */
696 m32c_regno_ok_for_base_p (int regno
)
698 if (regno
== A0_REGNO
699 || regno
== A1_REGNO
|| regno
>= FIRST_PSEUDO_REGISTER
)
704 #define DEBUG_RELOAD 0
706 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
707 registers of the appropriate size. */
709 m32c_preferred_reload_class (rtx x
, int rclass
)
711 int newclass
= rclass
;
714 fprintf (stderr
, "\npreferred_reload_class for %s is ",
715 class_names
[rclass
]);
717 if (rclass
== NO_REGS
)
718 rclass
= GET_MODE (x
) == QImode
? HL_REGS
: R03_REGS
;
720 if (classes_intersect (rclass
, CR_REGS
))
722 switch (GET_MODE (x
))
728 /* newclass = HI_REGS; */
733 else if (newclass
== QI_REGS
&& GET_MODE_SIZE (GET_MODE (x
)) > 2)
735 else if (GET_MODE_SIZE (GET_MODE (x
)) > 4
736 && ~class_contents
[rclass
][0] & 0x000f)
739 rclass
= reduce_class (rclass
, newclass
, rclass
);
741 if (GET_MODE (x
) == QImode
)
742 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
745 fprintf (stderr
, "%s\n", class_names
[rclass
]);
748 if (GET_CODE (x
) == MEM
749 && GET_CODE (XEXP (x
, 0)) == PLUS
750 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
751 fprintf (stderr
, "Glorm!\n");
756 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
758 m32c_preferred_output_reload_class (rtx x
, int rclass
)
760 return m32c_preferred_reload_class (x
, rclass
);
763 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
764 address registers for reloads since they're needed for address
767 m32c_limit_reload_class (enum machine_mode mode
, int rclass
)
770 fprintf (stderr
, "limit_reload_class for %s: %s ->",
771 mode_name
[mode
], class_names
[rclass
]);
775 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
776 else if (mode
== HImode
)
777 rclass
= reduce_class (rclass
, HI_REGS
, rclass
);
778 else if (mode
== SImode
)
779 rclass
= reduce_class (rclass
, SI_REGS
, rclass
);
781 if (rclass
!= A_REGS
)
782 rclass
= reduce_class (rclass
, DI_REGS
, rclass
);
785 fprintf (stderr
, " %s\n", class_names
[rclass
]);
790 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
791 r0 or r1, as those are the only real QImode registers. CR regs get
792 reloaded through appropriately sized general or address
795 m32c_secondary_reload_class (int rclass
, enum machine_mode mode
, rtx x
)
797 int cc
= class_contents
[rclass
][0];
799 fprintf (stderr
, "\nsecondary reload class %s %s\n",
800 class_names
[rclass
], mode_name
[mode
]);
804 && GET_CODE (x
) == MEM
&& (cc
& ~class_contents
[R23_REGS
][0]) == 0)
806 if (classes_intersect (rclass
, CR_REGS
)
807 && GET_CODE (x
) == REG
808 && REGNO (x
) >= SB_REGNO
&& REGNO (x
) <= SP_REGNO
)
809 return TARGET_A16
? HI_REGS
: A_REGS
;
813 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
816 m32c_class_likely_spilled_p (int regclass
)
818 if (regclass
== A_REGS
)
820 return reg_class_size
[regclass
] == 1;
823 /* Implements CLASS_MAX_NREGS. We calculate this according to its
824 documented meaning, to avoid potential inconsistencies with actual
825 class definitions. */
827 m32c_class_max_nregs (int regclass
, enum machine_mode mode
)
831 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
832 if (class_contents
[regclass
][0] & (1 << rn
))
834 int n
= m32c_hard_regno_nregs (rn
, mode
);
841 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
842 QI (r0l, r1l) because the chip doesn't support QI ops on other
843 registers (well, it does on a0/a1 but if we let gcc do that, reload
844 suffers). Otherwise, we allow changes to larger modes. */
846 m32c_cannot_change_mode_class (enum machine_mode from
,
847 enum machine_mode to
, int rclass
)
851 fprintf (stderr
, "cannot change from %s to %s in %s\n",
852 mode_name
[from
], mode_name
[to
], class_names
[rclass
]);
855 /* If the larger mode isn't allowed in any of these registers, we
856 can't allow the change. */
857 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
858 if (class_contents
[rclass
][0] & (1 << rn
))
859 if (! m32c_hard_regno_ok (rn
, to
))
863 return (class_contents
[rclass
][0] & 0x1ffa);
865 if (class_contents
[rclass
][0] & 0x0005 /* r0, r1 */
866 && GET_MODE_SIZE (from
) > 1)
868 if (GET_MODE_SIZE (from
) > 2) /* all other regs */
874 /* Helpers for the rest of the file. */
875 /* TRUE if the rtx is a REG rtx for the given register. */
876 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
877 && REGNO (rtx) == regno)
878 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
879 base register in address calculations (hence the "strict"
881 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
882 && (REGNO (rtx) == AP_REGNO \
883 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
885 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
886 constraints start with 'I', with the next two characters indicating
887 the type and size of the range allowed. */
889 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value
,
890 char c ATTRIBUTE_UNUSED
, const char *str
)
892 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
893 [sun] bits [SUN] bytes, p=pointer size
894 I[-0-9][0-9] matches that number */
895 if (memcmp (str
, "Is3", 3) == 0)
897 return (-8 <= value
&& value
<= 7);
899 if (memcmp (str
, "IS1", 3) == 0)
901 return (-128 <= value
&& value
<= 127);
903 if (memcmp (str
, "IS2", 3) == 0)
905 return (-32768 <= value
&& value
<= 32767);
907 if (memcmp (str
, "IU2", 3) == 0)
909 return (0 <= value
&& value
<= 65535);
911 if (memcmp (str
, "IU3", 3) == 0)
913 return (0 <= value
&& value
<= 0x00ffffff);
915 if (memcmp (str
, "In4", 3) == 0)
917 return (-8 <= value
&& value
&& value
<= 8);
919 if (memcmp (str
, "In5", 3) == 0)
921 return (-16 <= value
&& value
&& value
<= 16);
923 if (memcmp (str
, "In6", 3) == 0)
925 return (-32 <= value
&& value
&& value
<= 32);
927 if (memcmp (str
, "IM2", 3) == 0)
929 return (-65536 <= value
&& value
&& value
<= -1);
931 if (memcmp (str
, "Ilb", 3) == 0)
933 int b
= exact_log2 (value
);
934 return (b
>= 0 && b
<= 7);
936 if (memcmp (str
, "Imb", 3) == 0)
938 int b
= exact_log2 ((value
^ 0xff) & 0xff);
939 return (b
>= 0 && b
<= 7);
941 if (memcmp (str
, "Ilw", 3) == 0)
943 int b
= exact_log2 (value
);
944 return (b
>= 0 && b
<= 15);
946 if (memcmp (str
, "Imw", 3) == 0)
948 int b
= exact_log2 ((value
^ 0xffff) & 0xffff);
949 return (b
>= 0 && b
<= 15);
951 if (memcmp (str
, "I00", 3) == 0)
958 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
959 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
960 call return values. */
962 m32c_extra_constraint_p2 (rtx value
, char c ATTRIBUTE_UNUSED
, const char *str
)
964 encode_pattern (value
);
965 if (memcmp (str
, "Sd", 2) == 0)
967 /* This is the common "src/dest" address */
969 if (GET_CODE (value
) == MEM
&& CONSTANT_P (XEXP (value
, 0)))
971 if (RTX_IS ("ms") || RTX_IS ("m+si"))
973 if (RTX_IS ("m++rii"))
975 if (REGNO (patternr
[3]) == FB_REGNO
976 && INTVAL (patternr
[4]) == 0)
981 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
985 if (REGNO (r
) == SP_REGNO
)
987 return m32c_legitimate_address_p (GET_MODE (value
), XEXP (value
, 0), 1);
989 else if (memcmp (str
, "Sa", 2) == 0)
994 else if (RTX_IS ("m+ri"))
998 return (IS_REG (r
, A0_REGNO
) || IS_REG (r
, A1_REGNO
));
1000 else if (memcmp (str
, "Si", 2) == 0)
1002 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1004 else if (memcmp (str
, "Ss", 2) == 0)
1006 return ((RTX_IS ("mr")
1007 && (IS_REG (patternr
[1], SP_REGNO
)))
1008 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SP_REGNO
))));
1010 else if (memcmp (str
, "Sf", 2) == 0)
1012 return ((RTX_IS ("mr")
1013 && (IS_REG (patternr
[1], FB_REGNO
)))
1014 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], FB_REGNO
))));
1016 else if (memcmp (str
, "Sb", 2) == 0)
1018 return ((RTX_IS ("mr")
1019 && (IS_REG (patternr
[1], SB_REGNO
)))
1020 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SB_REGNO
))));
1022 else if (memcmp (str
, "Sp", 2) == 0)
1024 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1025 return (RTX_IS ("mi")
1026 && !(INTVAL (patternr
[1]) & ~0x1fff));
1028 else if (memcmp (str
, "S1", 2) == 0)
1030 return r1h_operand (value
, QImode
);
1033 gcc_assert (str
[0] != 'S');
1035 if (memcmp (str
, "Rpa", 2) == 0)
1036 return GET_CODE (value
) == PARALLEL
;
1041 /* This is for when we're debugging the above. */
1043 m32c_extra_constraint_p (rtx value
, char c
, const char *str
)
1045 int rv
= m32c_extra_constraint_p2 (value
, c
, str
);
1047 fprintf (stderr
, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c
, str
), str
,
1054 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1055 starting with 'S'. */
1057 m32c_extra_memory_constraint (char c
, const char *str ATTRIBUTE_UNUSED
)
1062 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1063 but don't currently define any. */
1065 m32c_extra_address_constraint (char c
, const char *str ATTRIBUTE_UNUSED
)
1070 /* STACK AND CALLING */
1074 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1075 (yes, THREE bytes) onto the stack for the return address, but we
1076 don't support pointers bigger than 16 bits on those chips. This
1077 will likely wreak havoc with exception unwinding. FIXME. */
1079 m32c_return_addr_rtx (int count
)
1081 enum machine_mode mode
;
1087 /* we want 2[$fb] */
1096 /* FIXME: it's really 3 bytes */
1102 gen_rtx_MEM (mode
, plus_constant (gen_rtx_REG (Pmode
, FP_REGNO
), offset
));
1103 return copy_to_mode_reg (mode
, ra_mem
);
1106 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1108 m32c_incoming_return_addr_rtx (void)
1111 return gen_rtx_MEM (PSImode
, gen_rtx_REG (PSImode
, SP_REGNO
));
1114 /* Exception Handling Support */
1116 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1119 m32c_eh_return_data_regno (int n
)
1128 return INVALID_REGNUM
;
1132 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1133 m32c_emit_eh_epilogue. */
1135 m32c_eh_return_stackadj_rtx (void)
1137 if (!cfun
->machine
->eh_stack_adjust
)
1141 sa
= gen_reg_rtx (Pmode
);
1142 cfun
->machine
->eh_stack_adjust
= sa
;
1144 return cfun
->machine
->eh_stack_adjust
;
1147 /* Registers That Address the Stack Frame */
1149 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1150 the original spec called for dwarf numbers to vary with register
1151 width as well, for example, r0l, r0, and r2r0 would each have
1152 different dwarf numbers. GCC doesn't support this, and we don't do
1153 it, and gdb seems to like it this way anyway. */
1155 m32c_dwarf_frame_regnum (int n
)
1181 return DWARF_FRAME_REGISTERS
+ 1;
1185 /* The frame looks like this:
1187 ap -> +------------------------------
1188 | Return address (3 or 4 bytes)
1189 | Saved FB (2 or 4 bytes)
1190 fb -> +------------------------------
1193 | through r0 as needed
1194 sp -> +------------------------------
1197 /* We use this to wrap all emitted insns in the prologue. */
1201 RTX_FRAME_RELATED_P (x
) = 1;
1205 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1206 how much the stack pointer moves for each, for each cpu family. */
1215 /* These are in reverse push (nearest-to-sp) order. */
1216 { R0_REGNO
, 0x80, 2, 2 },
1217 { R1_REGNO
, 0x40, 2, 2 },
1218 { R2_REGNO
, 0x20, 2, 2 },
1219 { R3_REGNO
, 0x10, 2, 2 },
1220 { A0_REGNO
, 0x08, 2, 4 },
1221 { A1_REGNO
, 0x04, 2, 4 },
1222 { SB_REGNO
, 0x02, 2, 4 },
1223 { FB_REGNO
, 0x01, 2, 4 }
1226 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1228 /* Returns TRUE if we need to save/restore the given register. We
1229 save everything for exception handlers, so that any register can be
1230 unwound. For interrupt handlers, we save everything if the handler
1231 calls something else (because we don't know what *that* function
1232 might do), but try to be a bit smarter if the handler is a leaf
1233 function. We always save $a0, though, because we use that in the
1234 epilogue to copy $fb to $sp. */
1236 need_to_save (int regno
)
1238 if (fixed_regs
[regno
])
1240 if (cfun
->calls_eh_return
)
1242 if (regno
== FP_REGNO
)
1244 if (cfun
->machine
->is_interrupt
1245 && (!cfun
->machine
->is_leaf
|| regno
== A0_REGNO
))
1247 if (regs_ever_live
[regno
]
1248 && (!call_used_regs
[regno
] || cfun
->machine
->is_interrupt
))
1253 /* This function contains all the intelligence about saving and
1254 restoring registers. It always figures out the register save set.
1255 When called with PP_justcount, it merely returns the size of the
1256 save set (for eliminating the frame pointer, for example). When
1257 called with PP_pushm or PP_popm, it emits the appropriate
1258 instructions for saving (pushm) or restoring (popm) the
1261 m32c_pushm_popm (Push_Pop_Type ppt
)
1264 int byte_count
= 0, bytes
;
1266 rtx dwarf_set
[PUSHM_N
];
1268 int nosave_mask
= 0;
1270 if (cfun
->return_rtx
1271 && GET_CODE (cfun
->return_rtx
) == PARALLEL
1272 && !(cfun
->calls_eh_return
|| cfun
->machine
->is_interrupt
))
1274 rtx exp
= XVECEXP (cfun
->return_rtx
, 0, 0);
1275 rtx rv
= XEXP (exp
, 0);
1276 int rv_bytes
= GET_MODE_SIZE (GET_MODE (rv
));
1279 nosave_mask
|= 0x20; /* PSI, SI */
1281 nosave_mask
|= 0xf0; /* DF */
1283 nosave_mask
|= 0x50; /* DI */
1286 for (i
= 0; i
< (int) PUSHM_N
; i
++)
1288 /* Skip if neither register needs saving. */
1289 if (!need_to_save (pushm_info
[i
].reg1
))
1292 if (pushm_info
[i
].bit
& nosave_mask
)
1295 reg_mask
|= pushm_info
[i
].bit
;
1296 bytes
= TARGET_A16
? pushm_info
[i
].a16_bytes
: pushm_info
[i
].a24_bytes
;
1298 if (ppt
== PP_pushm
)
1300 enum machine_mode mode
= (bytes
== 2) ? HImode
: SImode
;
1303 /* Always use stack_pointer_rtx instead of calling
1304 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1305 that there is a single rtx representing the stack pointer,
1306 namely stack_pointer_rtx, and uses == to recognize it. */
1307 addr
= stack_pointer_rtx
;
1309 if (byte_count
!= 0)
1310 addr
= gen_rtx_PLUS (GET_MODE (addr
), addr
, GEN_INT (byte_count
));
1312 dwarf_set
[n_dwarfs
++] =
1313 gen_rtx_SET (VOIDmode
,
1314 gen_rtx_MEM (mode
, addr
),
1315 gen_rtx_REG (mode
, pushm_info
[i
].reg1
));
1316 F (dwarf_set
[n_dwarfs
- 1]);
1319 byte_count
+= bytes
;
1322 if (cfun
->machine
->is_interrupt
)
1324 cfun
->machine
->intr_pushm
= reg_mask
& 0xfe;
1329 if (cfun
->machine
->is_interrupt
)
1330 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1331 if (need_to_save (i
))
1334 cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
] = 1;
1337 if (ppt
== PP_pushm
&& byte_count
)
1339 rtx note
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (n_dwarfs
+ 1));
1344 XVECEXP (note
, 0, 0)
1345 = gen_rtx_SET (VOIDmode
,
1347 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx
),
1349 GEN_INT (-byte_count
)));
1350 F (XVECEXP (note
, 0, 0));
1352 for (i
= 0; i
< n_dwarfs
; i
++)
1353 XVECEXP (note
, 0, i
+ 1) = dwarf_set
[i
];
1355 pushm
= F (emit_insn (gen_pushm (GEN_INT (reg_mask
))));
1357 REG_NOTES (pushm
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, note
,
1361 if (cfun
->machine
->is_interrupt
)
1362 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1363 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1366 pushm
= emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode
, i
)));
1368 pushm
= emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode
, i
)));
1372 if (ppt
== PP_popm
&& byte_count
)
1374 if (cfun
->machine
->is_interrupt
)
1375 for (i
= MEM7_REGNO
; i
>= MEM0_REGNO
; i
--)
1376 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1379 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, i
)));
1381 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode
, i
)));
1384 emit_insn (gen_popm (GEN_INT (reg_mask
)));
1390 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1391 diagrams our call frame. */
1393 m32c_initial_elimination_offset (int from
, int to
)
1397 if (from
== AP_REGNO
)
1407 ofs
+= m32c_pushm_popm (PP_justcount
);
1408 ofs
+= get_frame_size ();
1411 /* Account for push rounding. */
1413 ofs
= (ofs
+ 1) & ~1;
1415 fprintf (stderr
, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from
,
1421 /* Passing Function Arguments on the Stack */
1423 #undef TARGET_PROMOTE_PROTOTYPES
1424 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1426 m32c_promote_prototypes (tree fntype ATTRIBUTE_UNUSED
)
1431 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1432 M32C has word stacks. */
1434 m32c_push_rounding (int n
)
1436 if (TARGET_R8C
|| TARGET_M16C
)
1438 return (n
+ 1) & ~1;
1441 /* Passing Arguments in Registers */
1443 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1444 partly on stack. If our function returns a struct, a pointer to a
1445 buffer for it is at the top of the stack (last thing pushed). The
1446 first few real arguments may be in registers as follows:
1448 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1449 arg2 in r2 if it's HI (else pushed on stack)
1451 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1454 Structs are not passed in registers, even if they fit. Only
1455 integer and pointer types are passed in registers.
1457 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1460 m32c_function_arg (CUMULATIVE_ARGS
* ca
,
1461 enum machine_mode mode
, tree type
, int named
)
1463 /* Can return a reg, parallel, or 0 for stack */
1466 fprintf (stderr
, "func_arg %d (%s, %d)\n",
1467 ca
->parm_num
, mode_name
[mode
], named
);
1471 if (mode
== VOIDmode
)
1474 if (ca
->force_mem
|| !named
)
1477 fprintf (stderr
, "func arg: force %d named %d, mem\n", ca
->force_mem
,
1483 if (type
&& INTEGRAL_TYPE_P (type
) && POINTER_TYPE_P (type
))
1486 if (type
&& AGGREGATE_TYPE_P (type
))
1489 switch (ca
->parm_num
)
1492 if (GET_MODE_SIZE (mode
) == 1 || GET_MODE_SIZE (mode
) == 2)
1493 rv
= gen_rtx_REG (mode
, TARGET_A16
? R1_REGNO
: R0_REGNO
);
1497 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 2)
1498 rv
= gen_rtx_REG (mode
, R2_REGNO
);
1508 #undef TARGET_PASS_BY_REFERENCE
1509 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1511 m32c_pass_by_reference (CUMULATIVE_ARGS
* ca ATTRIBUTE_UNUSED
,
1512 enum machine_mode mode ATTRIBUTE_UNUSED
,
1513 tree type ATTRIBUTE_UNUSED
,
1514 bool named ATTRIBUTE_UNUSED
)
1519 /* Implements INIT_CUMULATIVE_ARGS. */
1521 m32c_init_cumulative_args (CUMULATIVE_ARGS
* ca
,
1523 rtx libname ATTRIBUTE_UNUSED
,
1525 int n_named_args ATTRIBUTE_UNUSED
)
1527 if (fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
))
1534 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1535 returning structures, so we always reset that. Otherwise, we only
1536 need to know the sequence number of the argument to know what to do
1539 m32c_function_arg_advance (CUMULATIVE_ARGS
* ca
,
1540 enum machine_mode mode ATTRIBUTE_UNUSED
,
1541 tree type ATTRIBUTE_UNUSED
,
1542 int named ATTRIBUTE_UNUSED
)
1550 /* Implements FUNCTION_ARG_REGNO_P. */
1552 m32c_function_arg_regno_p (int r
)
1555 return (r
== R0_REGNO
);
1556 return (r
== R1_REGNO
|| r
== R2_REGNO
);
1559 /* HImode and PSImode are the two "native" modes as far as GCC is
1560 concerned, but the chips also support a 32-bit mode which is used
1561 for some opcodes in R8C/M16C and for reset vectors and such. */
1562 #undef TARGET_VALID_POINTER_MODE
1563 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1565 m32c_valid_pointer_mode (enum machine_mode mode
)
1575 /* How Scalar Function Values Are Returned */
1577 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1578 combination of registers starting there (r2r0 for longs, r3r1r2r0
1579 for long long, r3r2r1r0 for doubles), except that that ABI
1580 currently doesn't work because it ends up using all available
1581 general registers and gcc often can't compile it. So, instead, we
1582 return anything bigger than 16 bits in "mem0" (effectively, a
1583 memory location). */
1585 m32c_libcall_value (enum machine_mode mode
)
1587 /* return reg or parallel */
1589 /* FIXME: GCC has difficulty returning large values in registers,
1590 because that ties up most of the general registers and gives the
1591 register allocator little to work with. Until we can resolve
1592 this, large values are returned in memory. */
1597 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (4));
1598 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1599 gen_rtx_REG (HImode
,
1602 XVECEXP (rv
, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode
,
1603 gen_rtx_REG (HImode
,
1606 XVECEXP (rv
, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode
,
1607 gen_rtx_REG (HImode
,
1610 XVECEXP (rv
, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode
,
1611 gen_rtx_REG (HImode
,
1617 if (TARGET_A24
&& GET_MODE_SIZE (mode
) > 2)
1621 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (1));
1622 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1630 if (GET_MODE_SIZE (mode
) > 2)
1631 return gen_rtx_REG (mode
, MEM0_REGNO
);
1632 return gen_rtx_REG (mode
, R0_REGNO
);
1635 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1638 m32c_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
1640 /* return reg or parallel */
1641 enum machine_mode mode
= TYPE_MODE (valtype
);
1642 return m32c_libcall_value (mode
);
1645 /* How Large Values Are Returned */
1647 /* We return structures by pushing the address on the stack, even if
1648 we use registers for the first few "real" arguments. */
1649 #undef TARGET_STRUCT_VALUE_RTX
1650 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1652 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
1653 int incoming ATTRIBUTE_UNUSED
)
1658 /* Function Entry and Exit */
1660 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1662 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
1664 if (cfun
->machine
->is_interrupt
)
1669 /* Implementing the Varargs Macros */
1671 #undef TARGET_STRICT_ARGUMENT_NAMING
1672 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1674 m32c_strict_argument_naming (CUMULATIVE_ARGS
* ca ATTRIBUTE_UNUSED
)
1679 /* Trampolines for Nested Functions */
1683 1 0000 75C43412 mov.w #0x1234,a0
1684 2 0004 FC000000 jmp.a label
1687 1 0000 BC563412 mov.l:s #0x123456,a0
1688 2 0004 CC000000 jmp.a label
1691 /* Implements TRAMPOLINE_SIZE. */
1693 m32c_trampoline_size (void)
1695 /* Allocate extra space so we can avoid the messy shifts when we
1696 initialize the trampoline; we just write past the end of the
1698 return TARGET_A16
? 8 : 10;
1701 /* Implements TRAMPOLINE_ALIGNMENT. */
1703 m32c_trampoline_alignment (void)
1708 /* Implements INITIALIZE_TRAMPOLINE. */
1710 m32c_initialize_trampoline (rtx tramp
, rtx function
, rtx chainval
)
1712 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1715 /* Note: we subtract a "word" because the moves want signed
1716 constants, not unsigned constants. */
1717 emit_move_insn (A0 (HImode
, 0), GEN_INT (0xc475 - 0x10000));
1718 emit_move_insn (A0 (HImode
, 2), chainval
);
1719 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xfc - 0x100));
1720 /* We use 16-bit addresses here, but store the zero to turn it
1721 into a 24-bit offset. */
1722 emit_move_insn (A0 (HImode
, 5), function
);
1723 emit_move_insn (A0 (QImode
, 7), GEN_INT (0x00));
1727 /* Note that the PSI moves actually write 4 bytes. Make sure we
1728 write stuff out in the right order, and leave room for the
1729 extra byte at the end. */
1730 emit_move_insn (A0 (QImode
, 0), GEN_INT (0xbc - 0x100));
1731 emit_move_insn (A0 (PSImode
, 1), chainval
);
1732 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xcc - 0x100));
1733 emit_move_insn (A0 (PSImode
, 5), function
);
1738 /* Implicit Calls to Library Routines */
1740 #undef TARGET_INIT_LIBFUNCS
1741 #define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1743 m32c_init_libfuncs (void)
1747 /* We do this because the M32C has an HImode operand, but the
1748 M16C has an 8-bit operand. Since gcc looks at the match data
1749 and not the expanded rtl, we have to reset the array so that
1750 the right modes are found. */
1751 setcc_gen_code
[EQ
] = CODE_FOR_seq_24
;
1752 setcc_gen_code
[NE
] = CODE_FOR_sne_24
;
1753 setcc_gen_code
[GT
] = CODE_FOR_sgt_24
;
1754 setcc_gen_code
[GE
] = CODE_FOR_sge_24
;
1755 setcc_gen_code
[LT
] = CODE_FOR_slt_24
;
1756 setcc_gen_code
[LE
] = CODE_FOR_sle_24
;
1757 setcc_gen_code
[GTU
] = CODE_FOR_sgtu_24
;
1758 setcc_gen_code
[GEU
] = CODE_FOR_sgeu_24
;
1759 setcc_gen_code
[LTU
] = CODE_FOR_sltu_24
;
1760 setcc_gen_code
[LEU
] = CODE_FOR_sleu_24
;
1764 /* Addressing Modes */
1766 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1767 wide range of non-orthogonal addressing modes, including the
1768 ability to double-indirect on *some* of them. Not all insns
1769 support all modes, either, but we rely on predicates and
1770 constraints to deal with that. */
1772 m32c_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1778 /* Wide references to memory will be split after reload, so we must
1779 ensure that all parts of such splits remain legitimate
1781 mode_adjust
= GET_MODE_SIZE (mode
) - 1;
1783 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1784 if (GET_CODE (x
) == PRE_DEC
1785 || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_MODIFY
)
1787 return (GET_CODE (XEXP (x
, 0)) == REG
1788 && REGNO (XEXP (x
, 0)) == SP_REGNO
);
1792 /* This is the double indirection detection, but it currently
1793 doesn't work as cleanly as this code implies, so until we've had
1794 a chance to debug it, leave it disabled. */
1795 if (TARGET_A24
&& GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) != PLUS
)
1798 fprintf (stderr
, "double indirect\n");
1807 /* Most indexable registers can be used without displacements,
1808 although some of them will be emitted with an explicit zero
1809 to please the assembler. */
1810 switch (REGNO (patternr
[0]))
1820 if (IS_PSEUDO (patternr
[0], strict
))
1827 /* This is more interesting, because different base registers
1828 allow for different displacements - both range and signedness
1829 - and it differs from chip series to chip series too. */
1830 int rn
= REGNO (patternr
[1]);
1831 HOST_WIDE_INT offs
= INTVAL (patternr
[2]);
1837 /* The syntax only allows positive offsets, but when the
1838 offsets span the entire memory range, we can simulate
1839 negative offsets by wrapping. */
1841 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1843 return (offs
>= 0 && offs
<= 65535 - mode_adjust
);
1845 return (offs
>= -16777216 && offs
<= 16777215);
1849 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1850 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1853 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1856 if (IS_PSEUDO (patternr
[1], strict
))
1861 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1863 rtx reg
= patternr
[1];
1865 /* We don't know where the symbol is, so only allow base
1866 registers which support displacements spanning the whole
1868 switch (REGNO (reg
))
1872 /* $sb needs a secondary reload, but since it's involved in
1873 memory address reloads too, we don't deal with it very
1875 /* case SB_REGNO: */
1878 if (IS_PSEUDO (reg
, strict
))
1886 /* Implements REG_OK_FOR_BASE_P. */
1888 m32c_reg_ok_for_base_p (rtx x
, int strict
)
1890 if (GET_CODE (x
) != REG
)
1901 if (IS_PSEUDO (x
, strict
))
1907 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1908 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1910 EB 4B FF mova -128[$fb],$a0
1911 D8 0C FF FF mov.w:Q #0,-1[$a0]
1913 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1916 77 54 00 01 sub #256,$a0
1917 D8 08 01 mov.w:Q #0,1[$a0]
1919 If we don't offset (i.e. offset by zero), we end up with:
1921 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1923 We have to subtract *something* so that we have a PLUS rtx to mark
1924 that we've done this reload. The -128 offset will never result in
1925 an 8-bit aN offset, and the payoff for the second case is five
1926 loads *if* those loads are within 256 bytes of the other end of the
1927 frame, so the third case seems best. Note that we subtract the
1928 zero, but detect that in the addhi3 pattern. */
1930 #define BIG_FB_ADJ 0
1932 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1933 worry about is frame base offsets, as $fb has a limited
1934 displacement range. We deal with this by attempting to reload $fb
1935 itself into an address register; that seems to result in the best
1938 m32c_legitimize_address (rtx
* x ATTRIBUTE_UNUSED
,
1939 rtx oldx ATTRIBUTE_UNUSED
,
1940 enum machine_mode mode ATTRIBUTE_UNUSED
)
1943 fprintf (stderr
, "m32c_legitimize_address for mode %s\n", mode_name
[mode
]);
1945 fprintf (stderr
, "\n");
1948 if (GET_CODE (*x
) == PLUS
1949 && GET_CODE (XEXP (*x
, 0)) == REG
1950 && REGNO (XEXP (*x
, 0)) == FB_REGNO
1951 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1952 && (INTVAL (XEXP (*x
, 1)) < -128
1953 || INTVAL (XEXP (*x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1955 /* reload FB to A_REGS */
1956 rtx temp
= gen_reg_rtx (Pmode
);
1958 emit_insn (gen_rtx_SET (VOIDmode
, temp
, XEXP (*x
, 0)));
1959 XEXP (*x
, 0) = temp
;
1966 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1968 m32c_legitimize_reload_address (rtx
* x
,
1969 enum machine_mode mode
,
1971 int type
, int ind_levels ATTRIBUTE_UNUSED
)
1974 fprintf (stderr
, "\nm32c_legitimize_reload_address for mode %s\n",
1979 /* At one point, this function tried to get $fb copied to an address
1980 register, which in theory would maximize sharing, but gcc was
1981 *also* still trying to reload the whole address, and we'd run out
1982 of address registers. So we let gcc do the naive (but safe)
1983 reload instead, when the above function doesn't handle it for
1986 The code below is a second attempt at the above. */
1988 if (GET_CODE (*x
) == PLUS
1989 && GET_CODE (XEXP (*x
, 0)) == REG
1990 && REGNO (XEXP (*x
, 0)) == FB_REGNO
1991 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1992 && (INTVAL (XEXP (*x
, 1)) < -128
1993 || INTVAL (XEXP (*x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1996 int offset
= INTVAL (XEXP (*x
, 1));
1997 int adjustment
= -BIG_FB_ADJ
;
1999 sum
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0),
2000 GEN_INT (adjustment
));
2001 *x
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- adjustment
));
2002 if (type
== RELOAD_OTHER
)
2003 type
= RELOAD_FOR_OTHER_ADDRESS
;
2004 push_reload (sum
, NULL_RTX
, &XEXP (*x
, 0), NULL
,
2005 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
2010 if (GET_CODE (*x
) == PLUS
2011 && GET_CODE (XEXP (*x
, 0)) == PLUS
2012 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
2013 && REGNO (XEXP (XEXP (*x
, 0), 0)) == FB_REGNO
2014 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
2015 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
2018 if (type
== RELOAD_OTHER
)
2019 type
= RELOAD_FOR_OTHER_ADDRESS
;
2020 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
2021 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
2029 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2030 so we can allow anything. */
2032 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
2038 /* Condition Code Status */
2040 #undef TARGET_FIXED_CONDITION_CODE_REGS
2041 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2043 m32c_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2046 *p2
= INVALID_REGNUM
;
2050 /* Describing Relative Costs of Operations */
2052 /* Implements REGISTER_MOVE_COST. We make impossible moves
2053 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2054 no opcodes to do that). We also discourage use of mem* registers
2055 since they're really memory. */
2057 m32c_register_move_cost (enum machine_mode mode
, int from
, int to
)
2059 int cost
= COSTS_N_INSNS (3);
2060 int cc
= class_contents
[from
][0] | class_contents
[to
][0];
2061 /* FIXME: pick real values, but not 2 for now. */
2062 if (mode
== QImode
&& (cc
& class_contents
[R23_REGS
][0]))
2064 if (!(cc
& ~class_contents
[R23_REGS
][0]))
2065 cost
= COSTS_N_INSNS (1000);
2067 cost
= COSTS_N_INSNS (80);
2070 if (!class_can_hold_mode (from
, mode
) || !class_can_hold_mode (to
, mode
))
2071 cost
= COSTS_N_INSNS (1000);
2073 if (classes_intersect (from
, CR_REGS
))
2074 cost
+= COSTS_N_INSNS (5);
2076 if (classes_intersect (to
, CR_REGS
))
2077 cost
+= COSTS_N_INSNS (5);
2079 if (from
== MEM_REGS
|| to
== MEM_REGS
)
2080 cost
+= COSTS_N_INSNS (50);
2081 else if (classes_intersect (from
, MEM_REGS
)
2082 || classes_intersect (to
, MEM_REGS
))
2083 cost
+= COSTS_N_INSNS (10);
2086 fprintf (stderr
, "register_move_cost %s from %s to %s = %d\n",
2087 mode_name
[mode
], class_names
[from
], class_names
[to
], cost
);
2092 /* Implements MEMORY_MOVE_COST. */
2094 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2095 int reg_class ATTRIBUTE_UNUSED
,
2096 int in ATTRIBUTE_UNUSED
)
2098 /* FIXME: pick real values. */
2099 return COSTS_N_INSNS (10);
2102 /* Here we try to describe when we use multiple opcodes for one RTX so
2103 that gcc knows when to use them. */
2104 #undef TARGET_RTX_COSTS
2105 #define TARGET_RTX_COSTS m32c_rtx_costs
2107 m32c_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2112 if (REGNO (x
) >= MEM0_REGNO
&& REGNO (x
) <= MEM7_REGNO
)
2113 *total
+= COSTS_N_INSNS (500);
2115 *total
+= COSTS_N_INSNS (1);
2121 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2123 /* mov.b r1l, r1h */
2124 *total
+= COSTS_N_INSNS (1);
2127 if (INTVAL (XEXP (x
, 1)) > 8
2128 || INTVAL (XEXP (x
, 1)) < -8)
2131 /* mov.b r1l, r1h */
2132 *total
+= COSTS_N_INSNS (2);
2147 if (outer_code
== SET
)
2149 *total
+= COSTS_N_INSNS (2);
2156 rtx dest
= XEXP (x
, 0);
2157 rtx addr
= XEXP (dest
, 0);
2158 switch (GET_CODE (addr
))
2161 *total
+= COSTS_N_INSNS (1);
2164 *total
+= COSTS_N_INSNS (3);
2167 *total
+= COSTS_N_INSNS (2);
2175 /* Reasonable default. */
2176 if (TARGET_A16
&& GET_MODE(x
) == SImode
)
2177 *total
+= COSTS_N_INSNS (2);
2183 #undef TARGET_ADDRESS_COST
2184 #define TARGET_ADDRESS_COST m32c_address_cost
2186 m32c_address_cost (rtx addr
)
2188 /* fprintf(stderr, "\naddress_cost\n");
2190 switch (GET_CODE (addr
))
2193 return COSTS_N_INSNS(1);
2195 return COSTS_N_INSNS(3);
2197 return COSTS_N_INSNS(2);
2203 /* Defining the Output Assembler Language */
2205 /* The Overall Framework of an Assembler File */
2207 #undef TARGET_HAVE_NAMED_SECTIONS
2208 #define TARGET_HAVE_NAMED_SECTIONS true
2210 /* Output of Data */
2212 /* We may have 24 bit sizes, which is the native address size.
2213 Currently unused, but provided for completeness. */
2214 #undef TARGET_ASM_INTEGER
2215 #define TARGET_ASM_INTEGER m32c_asm_integer
2217 m32c_asm_integer (rtx x
, unsigned int size
, int aligned_p
)
2222 fprintf (asm_out_file
, "\t.3byte\t");
2223 output_addr_const (asm_out_file
, x
);
2224 fputc ('\n', asm_out_file
);
2227 if (GET_CODE (x
) == SYMBOL_REF
)
2229 fprintf (asm_out_file
, "\t.long\t");
2230 output_addr_const (asm_out_file
, x
);
2231 fputc ('\n', asm_out_file
);
2236 return default_assemble_integer (x
, size
, aligned_p
);
2239 /* Output of Assembler Instructions */
2241 /* We use a lookup table because the addressing modes are non-orthogonal. */
2246 char const *pattern
;
2249 const conversions
[] = {
2252 { 0, "mr", "z[1]" },
2253 { 0, "m+ri", "3[2]" },
2254 { 0, "m+rs", "3[2]" },
2255 { 0, "m+r+si", "4+5[2]" },
2258 { 0, "m+si", "2+3" },
2260 { 0, "mmr", "[z[2]]" },
2261 { 0, "mm+ri", "[4[3]]" },
2262 { 0, "mm+rs", "[4[3]]" },
2263 { 0, "mm+r+si", "[5+6[3]]" },
2264 { 0, "mms", "[[2]]" },
2265 { 0, "mmi", "[[2]]" },
2266 { 0, "mm+si", "[4[3]]" },
2270 { 0, "+si", "#1+2" },
2276 { 'd', "+si", "1+2" },
2279 { 'D', "+si", "1+2" },
2290 /* This is in order according to the bitfield that pushm/popm use. */
2291 static char const *pushm_regs
[] = {
2292 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2295 /* Implements PRINT_OPERAND. */
2297 m32c_print_operand (FILE * file
, rtx x
, int code
)
2302 int unsigned_const
= 0;
2305 /* Multiplies; constants are converted to sign-extended format but
2306 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2318 /* This one is only for debugging; you can put it in a pattern to
2319 force this error. */
2322 fprintf (stderr
, "dj: unreviewed pattern:");
2323 if (current_output_insn
)
2324 debug_rtx (current_output_insn
);
2327 /* PSImode operations are either .w or .l depending on the target. */
2331 fprintf (file
, "w");
2333 fprintf (file
, "l");
2336 /* Inverted conditionals. */
2339 switch (GET_CODE (x
))
2345 fputs ("gtu", file
);
2351 fputs ("geu", file
);
2357 fputs ("leu", file
);
2363 fputs ("ltu", file
);
2376 /* Regular conditionals. */
2379 switch (GET_CODE (x
))
2385 fputs ("leu", file
);
2391 fputs ("ltu", file
);
2397 fputs ("gtu", file
);
2403 fputs ("geu", file
);
2416 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2418 if (code
== 'h' && GET_MODE (x
) == SImode
)
2420 x
= m32c_subreg (HImode
, x
, SImode
, 0);
2423 if (code
== 'H' && GET_MODE (x
) == SImode
)
2425 x
= m32c_subreg (HImode
, x
, SImode
, 2);
2428 if (code
== 'h' && GET_MODE (x
) == HImode
)
2430 x
= m32c_subreg (QImode
, x
, HImode
, 0);
2433 if (code
== 'H' && GET_MODE (x
) == HImode
)
2435 /* We can't actually represent this as an rtx. Do it here. */
2436 if (GET_CODE (x
) == REG
)
2441 fputs ("r0h", file
);
2444 fputs ("r1h", file
);
2450 /* This should be a MEM. */
2451 x
= m32c_subreg (QImode
, x
, HImode
, 1);
2454 /* This is for BMcond, which always wants word register names. */
2455 if (code
== 'h' && GET_MODE (x
) == QImode
)
2457 if (GET_CODE (x
) == REG
)
2458 x
= gen_rtx_REG (HImode
, REGNO (x
));
2461 /* 'x' and 'X' need to be ignored for non-immediates. */
2462 if ((code
== 'x' || code
== 'X') && GET_CODE (x
) != CONST_INT
)
2467 for (i
= 0; conversions
[i
].pattern
; i
++)
2468 if (conversions
[i
].code
== code
2469 && streq (conversions
[i
].pattern
, pattern
))
2471 for (j
= 0; conversions
[i
].format
[j
]; j
++)
2472 /* backslash quotes the next character in the output pattern. */
2473 if (conversions
[i
].format
[j
] == '\\')
2475 fputc (conversions
[i
].format
[j
+ 1], file
);
2478 /* Digits in the output pattern indicate that the
2479 corresponding RTX is to be output at that point. */
2480 else if (ISDIGIT (conversions
[i
].format
[j
]))
2482 rtx r
= patternr
[conversions
[i
].format
[j
] - '0'];
2483 switch (GET_CODE (r
))
2486 fprintf (file
, "%s",
2487 reg_name_with_mode (REGNO (r
), GET_MODE (r
)));
2496 int i
= (int) exact_log2 (v
);
2498 i
= (int) exact_log2 ((v
^ 0xffff) & 0xffff);
2500 i
= (int) exact_log2 ((v
^ 0xff) & 0xff);
2502 fprintf (file
, "%d", i
);
2506 /* Unsigned byte. */
2507 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2511 /* Unsigned word. */
2512 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2513 INTVAL (r
) & 0xffff);
2516 /* pushm and popm encode a register set into a single byte. */
2518 for (b
= 7; b
>= 0; b
--)
2519 if (INTVAL (r
) & (1 << b
))
2521 fprintf (file
, "%s%s", comma
, pushm_regs
[b
]);
2526 /* "Minus". Output -X */
2527 ival
= (-INTVAL (r
) & 0xffff);
2529 ival
= ival
- 0x10000;
2530 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2534 if (conversions
[i
].format
[j
+ 1] == '[' && ival
< 0)
2536 /* We can simulate negative displacements by
2537 taking advantage of address space
2538 wrapping when the offset can span the
2539 entire address range. */
2541 patternr
[conversions
[i
].format
[j
+ 2] - '0'];
2542 if (GET_CODE (base
) == REG
)
2543 switch (REGNO (base
))
2548 ival
= 0x1000000 + ival
;
2550 ival
= 0x10000 + ival
;
2554 ival
= 0x10000 + ival
;
2558 else if (code
== 'd' && ival
< 0 && j
== 0)
2559 /* The "mova" opcode is used to do addition by
2560 computing displacements, but again, we need
2561 displacements to be unsigned *if* they're
2562 the only component of the displacement
2563 (i.e. no "symbol-4" type displacement). */
2564 ival
= (TARGET_A24
? 0x1000000 : 0x10000) + ival
;
2566 if (conversions
[i
].format
[j
] == '0')
2568 /* More conversions to unsigned. */
2569 if (unsigned_const
== 2)
2571 if (unsigned_const
== 1)
2574 if (streq (conversions
[i
].pattern
, "mi")
2575 || streq (conversions
[i
].pattern
, "mmi"))
2577 /* Integers used as addresses are unsigned. */
2578 ival
&= (TARGET_A24
? 0xffffff : 0xffff);
2580 if (force_sign
&& ival
>= 0)
2582 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2587 /* We don't have const_double constants. If it
2588 happens, make it obvious. */
2589 fprintf (file
, "[const_double 0x%lx]",
2590 (unsigned long) CONST_DOUBLE_HIGH (r
));
2593 assemble_name (file
, XSTR (r
, 0));
2596 output_asm_label (r
);
2599 fprintf (stderr
, "don't know how to print this operand:");
2606 if (conversions
[i
].format
[j
] == 'z')
2608 /* Some addressing modes *must* have a displacement,
2609 so insert a zero here if needed. */
2611 for (k
= j
+ 1; conversions
[i
].format
[k
]; k
++)
2612 if (ISDIGIT (conversions
[i
].format
[k
]))
2614 rtx reg
= patternr
[conversions
[i
].format
[k
] - '0'];
2615 if (GET_CODE (reg
) == REG
2616 && (REGNO (reg
) == SB_REGNO
2617 || REGNO (reg
) == FB_REGNO
2618 || REGNO (reg
) == SP_REGNO
))
2623 /* Signed displacements off symbols need to have signs
2625 if (conversions
[i
].format
[j
] == '+'
2626 && (!code
|| code
== 'D' || code
== 'd')
2627 && ISDIGIT (conversions
[i
].format
[j
+ 1])
2628 && (GET_CODE (patternr
[conversions
[i
].format
[j
+ 1] - '0'])
2634 fputc (conversions
[i
].format
[j
], file
);
2638 if (!conversions
[i
].pattern
)
2640 fprintf (stderr
, "unconvertible operand %c `%s'", code
? code
: '-',
2643 fprintf (file
, "[%c.%s]", code
? code
: '-', pattern
);
2649 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2650 above for descriptions of what these do. */
2652 m32c_print_operand_punct_valid_p (int c
)
2654 if (c
== '&' || c
== '!')
2659 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2661 m32c_print_operand_address (FILE * stream
, rtx address
)
2663 gcc_assert (GET_CODE (address
) == MEM
);
2664 m32c_print_operand (stream
, XEXP (address
, 0), 0);
2667 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2668 differently than general registers. */
2670 m32c_output_reg_push (FILE * s
, int regno
)
2672 if (regno
== FLG_REGNO
)
2673 fprintf (s
, "\tpushc\tflg\n");
2675 fprintf (s
, "\tpush.%c\t%s\n",
2676 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2679 /* Likewise for ASM_OUTPUT_REG_POP. */
2681 m32c_output_reg_pop (FILE * s
, int regno
)
2683 if (regno
== FLG_REGNO
)
2684 fprintf (s
, "\tpopc\tflg\n");
2686 fprintf (s
, "\tpop.%c\t%s\n",
2687 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2690 /* Defining target-specific uses of `__attribute__' */
2692 /* Used to simplify the logic below. Find the attributes wherever
2694 #define M32C_ATTRIBUTES(decl) \
2695 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2696 : DECL_ATTRIBUTES (decl) \
2697 ? (DECL_ATTRIBUTES (decl)) \
2698 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2700 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2702 interrupt_p (tree node ATTRIBUTE_UNUSED
)
2704 tree list
= M32C_ATTRIBUTES (node
);
2707 if (is_attribute_p ("interrupt", TREE_PURPOSE (list
)))
2709 list
= TREE_CHAIN (list
);
2715 interrupt_handler (tree
* node ATTRIBUTE_UNUSED
,
2716 tree name ATTRIBUTE_UNUSED
,
2717 tree args ATTRIBUTE_UNUSED
,
2718 int flags ATTRIBUTE_UNUSED
,
2719 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2724 #undef TARGET_ATTRIBUTE_TABLE
2725 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2726 static const struct attribute_spec m32c_attribute_table
[] = {
2727 {"interrupt", 0, 0, false, false, false, interrupt_handler
},
2728 {0, 0, 0, 0, 0, 0, 0}
2731 #undef TARGET_COMP_TYPE_ATTRIBUTES
2732 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2734 m32c_comp_type_attributes (tree type1 ATTRIBUTE_UNUSED
,
2735 tree type2 ATTRIBUTE_UNUSED
)
2737 /* 0=incompatible 1=compatible 2=warning */
2741 #undef TARGET_INSERT_ATTRIBUTES
2742 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2744 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED
,
2745 tree
* attr_ptr ATTRIBUTE_UNUSED
)
2747 /* Nothing to do here. */
2752 /* This is a list of legal subregs of hard regs. */
2753 static const struct {
2754 unsigned char outer_mode_size
;
2755 unsigned char inner_mode_size
;
2756 unsigned char byte_mask
;
2757 unsigned char legal_when
;
2759 } legal_subregs
[] = {
2760 {1, 2, 0x03, 1, R0_REGNO
}, /* r0h r0l */
2761 {1, 2, 0x03, 1, R1_REGNO
}, /* r1h r1l */
2762 {1, 2, 0x01, 1, A0_REGNO
},
2763 {1, 2, 0x01, 1, A1_REGNO
},
2765 {1, 4, 0x01, 1, A0_REGNO
},
2766 {1, 4, 0x01, 1, A1_REGNO
},
2768 {2, 4, 0x05, 1, R0_REGNO
}, /* r2 r0 */
2769 {2, 4, 0x05, 1, R1_REGNO
}, /* r3 r1 */
2770 {2, 4, 0x05, 16, A0_REGNO
}, /* a1 a0 */
2771 {2, 4, 0x01, 24, A0_REGNO
}, /* a1 a0 */
2772 {2, 4, 0x01, 24, A1_REGNO
}, /* a1 a0 */
2774 {4, 8, 0x55, 1, R0_REGNO
}, /* r3 r1 r2 r0 */
2777 /* Returns TRUE if OP is a subreg of a hard reg which we don't
2780 m32c_illegal_subreg_p (rtx op
)
2784 int src_mode
, dest_mode
;
2786 if (GET_CODE (op
) != SUBREG
)
2789 dest_mode
= GET_MODE (op
);
2790 offset
= SUBREG_BYTE (op
);
2791 op
= SUBREG_REG (op
);
2792 src_mode
= GET_MODE (op
);
2794 if (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (src_mode
))
2796 if (GET_CODE (op
) != REG
)
2798 if (REGNO (op
) >= MEM0_REGNO
)
2801 offset
= (1 << offset
);
2803 for (i
= 0; i
< ARRAY_SIZE (legal_subregs
); i
++)
2804 if (legal_subregs
[i
].outer_mode_size
== GET_MODE_SIZE (dest_mode
)
2805 && legal_subregs
[i
].regno
== REGNO (op
)
2806 && legal_subregs
[i
].inner_mode_size
== GET_MODE_SIZE (src_mode
)
2807 && legal_subregs
[i
].byte_mask
& offset
)
2809 switch (legal_subregs
[i
].legal_when
)
2826 /* Returns TRUE if we support a move between the first two operands.
2827 At the moment, we just want to discourage mem to mem moves until
2828 after reload, because reload has a hard time with our limited
2829 number of address registers, and we can get into a situation where
2830 we need three of them when we only have two. */
2832 m32c_mov_ok (rtx
* operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2834 rtx op0
= operands
[0];
2835 rtx op1
= operands
[1];
2840 #define DEBUG_MOV_OK 0
2842 fprintf (stderr
, "m32c_mov_ok %s\n", mode_name
[mode
]);
2847 if (GET_CODE (op0
) == SUBREG
)
2848 op0
= XEXP (op0
, 0);
2849 if (GET_CODE (op1
) == SUBREG
)
2850 op1
= XEXP (op1
, 0);
2852 if (GET_CODE (op0
) == MEM
2853 && GET_CODE (op1
) == MEM
2854 && ! reload_completed
)
2857 fprintf (stderr
, " - no, mem to mem\n");
2863 fprintf (stderr
, " - ok\n");
2868 /* Returns TRUE if two consecutive HImode mov instructions, generated
2869 for moving an immediate double data to a double data type variable
2870 location, can be combined into single SImode mov instruction. */
2872 m32c_immd_dbl_mov (rtx
* operands
,
2873 enum machine_mode mode ATTRIBUTE_UNUSED
)
2875 int flag
= 0, okflag
= 0, offset1
= 0, offset2
= 0, offsetsign
= 0;
2879 if (GET_CODE (XEXP (operands
[0], 0)) == SYMBOL_REF
2880 && MEM_SCALAR_P (operands
[0])
2881 && !MEM_IN_STRUCT_P (operands
[0])
2882 && GET_CODE (XEXP (operands
[2], 0)) == CONST
2883 && GET_CODE (XEXP (XEXP (operands
[2], 0), 0)) == PLUS
2884 && GET_CODE (XEXP (XEXP (XEXP (operands
[2], 0), 0), 0)) == SYMBOL_REF
2885 && GET_CODE (XEXP (XEXP (XEXP (operands
[2], 0), 0), 1)) == CONST_INT
2886 && MEM_SCALAR_P (operands
[2])
2887 && !MEM_IN_STRUCT_P (operands
[2]))
2890 else if (GET_CODE (XEXP (operands
[0], 0)) == CONST
2891 && GET_CODE (XEXP (XEXP (operands
[0], 0), 0)) == PLUS
2892 && GET_CODE (XEXP (XEXP (XEXP (operands
[0], 0), 0), 0)) == SYMBOL_REF
2893 && MEM_SCALAR_P (operands
[0])
2894 && !MEM_IN_STRUCT_P (operands
[0])
2895 && !(XINT (XEXP (XEXP (XEXP (operands
[0], 0), 0), 1), 0) %4)
2896 && GET_CODE (XEXP (operands
[2], 0)) == CONST
2897 && GET_CODE (XEXP (XEXP (operands
[2], 0), 0)) == PLUS
2898 && GET_CODE (XEXP (XEXP (XEXP (operands
[2], 0), 0), 0)) == SYMBOL_REF
2899 && MEM_SCALAR_P (operands
[2])
2900 && !MEM_IN_STRUCT_P (operands
[2]))
2903 else if (GET_CODE (XEXP (operands
[0], 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (operands
[0], 0), 0)) == REG
2905 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == FB_REGNO
2906 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
2907 && MEM_SCALAR_P (operands
[0])
2908 && !MEM_IN_STRUCT_P (operands
[0])
2909 && !(XINT (XEXP (XEXP (operands
[0], 0), 1), 0) %4)
2910 && REGNO (XEXP (XEXP (operands
[2], 0), 0)) == FB_REGNO
2911 && GET_CODE (XEXP (XEXP (operands
[2], 0), 1)) == CONST_INT
2912 && MEM_SCALAR_P (operands
[2])
2913 && !MEM_IN_STRUCT_P (operands
[2]))
2922 str1
= XSTR (XEXP (operands
[0], 0), 0);
2923 str2
= XSTR (XEXP (XEXP (XEXP (operands
[2], 0), 0), 0), 0);
2924 if (strcmp (str1
, str2
) == 0)
2930 str1
= XSTR (XEXP (XEXP (XEXP (operands
[0], 0), 0), 0), 0);
2931 str2
= XSTR (XEXP (XEXP (XEXP (operands
[2], 0), 0), 0), 0);
2932 if (strcmp(str1
,str2
) == 0)
2938 offset1
= XINT (XEXP (XEXP (operands
[0], 0), 1), 0);
2939 offset2
= XINT (XEXP (XEXP (operands
[2], 0), 1), 0);
2940 offsetsign
= offset1
>> ((sizeof (offset1
) * 8) -1);
2941 if (((offset2
-offset1
) == 2) && offsetsign
!= 0)
2953 operands
[4] = gen_rtx_MEM (SImode
, XEXP (operands
[0], 0));
2955 val
= (XINT (operands
[3], 0) << 16) + (XINT (operands
[1], 0) & 0xFFFF);
2956 operands
[5] = gen_rtx_CONST_INT (VOIDmode
, val
);
2966 /* Subregs are non-orthogonal for us, because our registers are all
2969 m32c_subreg (enum machine_mode outer
,
2970 rtx x
, enum machine_mode inner
, int byte
)
2974 /* Converting MEMs to different types that are the same size, we
2975 just rewrite them. */
2976 if (GET_CODE (x
) == SUBREG
2977 && SUBREG_BYTE (x
) == 0
2978 && GET_CODE (SUBREG_REG (x
)) == MEM
2979 && (GET_MODE_SIZE (GET_MODE (x
))
2980 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2983 x
= gen_rtx_MEM (GET_MODE (x
), XEXP (SUBREG_REG (x
), 0));
2984 MEM_COPY_ATTRIBUTES (x
, SUBREG_REG (oldx
));
2987 /* Push/pop get done as smaller push/pops. */
2988 if (GET_CODE (x
) == MEM
2989 && (GET_CODE (XEXP (x
, 0)) == PRE_DEC
2990 || GET_CODE (XEXP (x
, 0)) == POST_INC
))
2991 return gen_rtx_MEM (outer
, XEXP (x
, 0));
2992 if (GET_CODE (x
) == SUBREG
2993 && GET_CODE (XEXP (x
, 0)) == MEM
2994 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PRE_DEC
2995 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == POST_INC
))
2996 return gen_rtx_MEM (outer
, XEXP (XEXP (x
, 0), 0));
2998 if (GET_CODE (x
) != REG
)
2999 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3002 if (r
>= FIRST_PSEUDO_REGISTER
|| r
== AP_REGNO
)
3003 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3005 if (IS_MEM_REGNO (r
))
3006 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3008 /* This is where the complexities of our register layout are
3012 else if (outer
== HImode
)
3014 if (r
== R0_REGNO
&& byte
== 2)
3016 else if (r
== R0_REGNO
&& byte
== 4)
3018 else if (r
== R0_REGNO
&& byte
== 6)
3020 else if (r
== R1_REGNO
&& byte
== 2)
3022 else if (r
== A0_REGNO
&& byte
== 2)
3025 else if (outer
== SImode
)
3027 if (r
== R0_REGNO
&& byte
== 0)
3029 else if (r
== R0_REGNO
&& byte
== 4)
3034 fprintf (stderr
, "m32c_subreg %s %s %d\n",
3035 mode_name
[outer
], mode_name
[inner
], byte
);
3039 return gen_rtx_REG (outer
, nr
);
3042 /* Used to emit move instructions. We split some moves,
3043 and avoid mem-mem moves. */
3045 m32c_prepare_move (rtx
* operands
, enum machine_mode mode
)
3047 if (TARGET_A16
&& mode
== PSImode
)
3048 return m32c_split_move (operands
, mode
, 1);
3049 if ((GET_CODE (operands
[0]) == MEM
)
3050 && (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
))
3052 rtx pmv
= XEXP (operands
[0], 0);
3053 rtx dest_reg
= XEXP (pmv
, 0);
3054 rtx dest_mod
= XEXP (pmv
, 1);
3056 emit_insn (gen_rtx_SET (Pmode
, dest_reg
, dest_mod
));
3057 operands
[0] = gen_rtx_MEM (mode
, dest_reg
);
3059 if (!no_new_pseudos
&& MEM_P (operands
[0]) && MEM_P (operands
[1]))
3060 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
3064 #define DEBUG_SPLIT 0
3066 /* Returns TRUE if the given PSImode move should be split. We split
3067 for all r8c/m16c moves, since it doesn't support them, and for
3068 POP.L as we can only *push* SImode. */
3070 m32c_split_psi_p (rtx
* operands
)
3073 fprintf (stderr
, "\nm32c_split_psi_p\n");
3074 debug_rtx (operands
[0]);
3075 debug_rtx (operands
[1]);
3080 fprintf (stderr
, "yes, A16\n");
3084 if (GET_CODE (operands
[1]) == MEM
3085 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3088 fprintf (stderr
, "yes, pop.l\n");
3093 fprintf (stderr
, "no, default\n");
3098 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3099 (define_expand), 1 if it is not optional (define_insn_and_split),
3100 and 3 for define_split (alternate api). */
3102 m32c_split_move (rtx
* operands
, enum machine_mode mode
, int split_all
)
3105 int parts
, si
, di
, rev
= 0;
3106 int rv
= 0, opi
= 2;
3107 enum machine_mode submode
= HImode
;
3108 rtx
*ops
, local_ops
[10];
3110 /* define_split modifies the existing operands, but the other two
3111 emit new insns. OPS is where we store the operand pairs, which
3122 /* Before splitting mem-mem moves, force one operand into a
3124 if (!no_new_pseudos
&& MEM_P (operands
[0]) && MEM_P (operands
[1]))
3127 fprintf (stderr
, "force_reg...\n");
3128 debug_rtx (operands
[1]);
3130 operands
[1] = force_reg (mode
, operands
[1]);
3132 debug_rtx (operands
[1]);
3139 fprintf (stderr
, "\nsplit_move %d all=%d\n", no_new_pseudos
, split_all
);
3140 debug_rtx (operands
[0]);
3141 debug_rtx (operands
[1]);
3144 /* Note that split_all is not used to select the api after this
3145 point, so it's safe to set it to 3 even with define_insn. */
3146 /* None of the chips can move SI operands to sp-relative addresses,
3147 so we always split those. */
3148 if (m32c_extra_constraint_p (operands
[0], 'S', "Ss"))
3151 /* We don't need to split these. */
3154 && (mode
== SImode
|| mode
== PSImode
)
3155 && !(GET_CODE (operands
[1]) == MEM
3156 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
))
3159 /* First, enumerate the subregs we'll be dealing with. */
3160 for (si
= 0; si
< parts
; si
++)
3163 m32c_subreg (submode
, operands
[0], mode
,
3164 si
* GET_MODE_SIZE (submode
));
3166 m32c_subreg (submode
, operands
[1], mode
,
3167 si
* GET_MODE_SIZE (submode
));
3170 /* Split pushes by emitting a sequence of smaller pushes. */
3171 if (GET_CODE (d
[0]) == MEM
&& GET_CODE (XEXP (d
[0], 0)) == PRE_DEC
)
3173 for (si
= parts
- 1; si
>= 0; si
--)
3175 ops
[opi
++] = gen_rtx_MEM (submode
,
3176 gen_rtx_PRE_DEC (Pmode
,
3184 /* Likewise for pops. */
3185 else if (GET_CODE (s
[0]) == MEM
&& GET_CODE (XEXP (s
[0], 0)) == POST_INC
)
3187 for (di
= 0; di
< parts
; di
++)
3190 ops
[opi
++] = gen_rtx_MEM (submode
,
3191 gen_rtx_POST_INC (Pmode
,
3199 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3200 for (di
= 0; di
< parts
- 1; di
++)
3201 for (si
= di
+ 1; si
< parts
; si
++)
3202 if (reg_mentioned_p (d
[di
], s
[si
]))
3206 for (si
= 0; si
< parts
; si
++)
3212 for (si
= parts
- 1; si
>= 0; si
--)
3219 /* Now emit any moves we may have accumulated. */
3220 if (rv
&& split_all
!= 3)
3223 for (i
= 2; i
< opi
; i
+= 2)
3224 emit_move_insn (ops
[i
], ops
[i
+ 1]);
3229 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3230 the like. For the R8C they expect one of the addresses to be in
3231 R1L:An so we need to arrange for that. Otherwise, it's just a
3232 matter of picking out the operands we want and emitting the right
3233 pattern for them. All these expanders, which correspond to
3234 patterns in blkmov.md, must return nonzero if they expand the insn,
3235 or zero if they should FAIL. */
3237 /* This is a memset() opcode. All operands are implied, so we need to
3238 arrange for them to be in the right registers. The opcode wants
3239 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3240 the count (HI), and $2 the value (QI). */
3242 m32c_expand_setmemhi(rtx
*operands
)
3244 rtx desta
, count
, val
;
3247 desta
= XEXP (operands
[0], 0);
3248 count
= operands
[1];
3251 desto
= gen_reg_rtx (Pmode
);
3252 counto
= gen_reg_rtx (HImode
);
3254 if (GET_CODE (desta
) != REG
3255 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3256 desta
= copy_to_mode_reg (Pmode
, desta
);
3258 /* This looks like an arbitrary restriction, but this is by far the
3259 most common case. For counts 8..14 this actually results in
3260 smaller code with no speed penalty because the half-sized
3261 constant can be loaded with a shorter opcode. */
3262 if (GET_CODE (count
) == CONST_INT
3263 && GET_CODE (val
) == CONST_INT
3264 && ! (INTVAL (count
) & 1)
3265 && (INTVAL (count
) > 1)
3266 && (INTVAL (val
) <= 7 && INTVAL (val
) >= -8))
3268 unsigned v
= INTVAL (val
) & 0xff;
3270 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3271 val
= copy_to_mode_reg (HImode
, GEN_INT (v
));
3273 emit_insn (gen_setmemhi_whi_op (desto
, counto
, val
, desta
, count
));
3275 emit_insn (gen_setmemhi_wpsi_op (desto
, counto
, val
, desta
, count
));
3279 /* This is the generalized memset() case. */
3280 if (GET_CODE (val
) != REG
3281 || REGNO (val
) < FIRST_PSEUDO_REGISTER
)
3282 val
= copy_to_mode_reg (QImode
, val
);
3284 if (GET_CODE (count
) != REG
3285 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3286 count
= copy_to_mode_reg (HImode
, count
);
3289 emit_insn (gen_setmemhi_bhi_op (desto
, counto
, val
, desta
, count
));
3291 emit_insn (gen_setmemhi_bpsi_op (desto
, counto
, val
, desta
, count
));
3296 /* This is a memcpy() opcode. All operands are implied, so we need to
3297 arrange for them to be in the right registers. The opcode wants
3298 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3299 is the source (MEM:BLK), and $2 the count (HI). */
3301 m32c_expand_movmemhi(rtx
*operands
)
3303 rtx desta
, srca
, count
;
3304 rtx desto
, srco
, counto
;
3306 desta
= XEXP (operands
[0], 0);
3307 srca
= XEXP (operands
[1], 0);
3308 count
= operands
[2];
3310 desto
= gen_reg_rtx (Pmode
);
3311 srco
= gen_reg_rtx (Pmode
);
3312 counto
= gen_reg_rtx (HImode
);
3314 if (GET_CODE (desta
) != REG
3315 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3316 desta
= copy_to_mode_reg (Pmode
, desta
);
3318 if (GET_CODE (srca
) != REG
3319 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3320 srca
= copy_to_mode_reg (Pmode
, srca
);
3322 /* Similar to setmem, but we don't need to check the value. */
3323 if (GET_CODE (count
) == CONST_INT
3324 && ! (INTVAL (count
) & 1)
3325 && (INTVAL (count
) > 1))
3327 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3329 emit_insn (gen_movmemhi_whi_op (desto
, srco
, counto
, desta
, srca
, count
));
3331 emit_insn (gen_movmemhi_wpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3335 /* This is the generalized memset() case. */
3336 if (GET_CODE (count
) != REG
3337 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3338 count
= copy_to_mode_reg (HImode
, count
);
3341 emit_insn (gen_movmemhi_bhi_op (desto
, srco
, counto
, desta
, srca
, count
));
3343 emit_insn (gen_movmemhi_bpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3348 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3349 the copy, which should point to the NUL at the end of the string,
3350 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3351 Since our opcode leaves the destination pointing *after* the NUL,
3352 we must emit an adjustment. */
3354 m32c_expand_movstr(rtx
*operands
)
3359 desta
= XEXP (operands
[1], 0);
3360 srca
= XEXP (operands
[2], 0);
3362 desto
= gen_reg_rtx (Pmode
);
3363 srco
= gen_reg_rtx (Pmode
);
3365 if (GET_CODE (desta
) != REG
3366 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3367 desta
= copy_to_mode_reg (Pmode
, desta
);
3369 if (GET_CODE (srca
) != REG
3370 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3371 srca
= copy_to_mode_reg (Pmode
, srca
);
3373 emit_insn (gen_movstr_op (desto
, srco
, desta
, srca
));
3374 /* desto ends up being a1, which allows this type of add through MOVA. */
3375 emit_insn (gen_addpsi3 (operands
[0], desto
, GEN_INT (-1)));
3380 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3381 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3382 $2 is the other (MEM:BLK). We must do the comparison, and then
3383 convert the flags to a signed integer result. */
3385 m32c_expand_cmpstr(rtx
*operands
)
3389 src1a
= XEXP (operands
[1], 0);
3390 src2a
= XEXP (operands
[2], 0);
3392 if (GET_CODE (src1a
) != REG
3393 || REGNO (src1a
) < FIRST_PSEUDO_REGISTER
)
3394 src1a
= copy_to_mode_reg (Pmode
, src1a
);
3396 if (GET_CODE (src2a
) != REG
3397 || REGNO (src2a
) < FIRST_PSEUDO_REGISTER
)
3398 src2a
= copy_to_mode_reg (Pmode
, src2a
);
3400 emit_insn (gen_cmpstrhi_op (src1a
, src2a
, src1a
, src2a
));
3401 emit_insn (gen_cond_to_int (operands
[0]));
3407 typedef rtx (*shift_gen_func
)(rtx
, rtx
, rtx
);
3409 static shift_gen_func
3410 shift_gen_func_for (int mode
, int code
)
3412 #define GFF(m,c,f) if (mode == m && code == c) return f
3413 GFF(QImode
, ASHIFT
, gen_ashlqi3_i
);
3414 GFF(QImode
, ASHIFTRT
, gen_ashrqi3_i
);
3415 GFF(QImode
, LSHIFTRT
, gen_lshrqi3_i
);
3416 GFF(HImode
, ASHIFT
, gen_ashlhi3_i
);
3417 GFF(HImode
, ASHIFTRT
, gen_ashrhi3_i
);
3418 GFF(HImode
, LSHIFTRT
, gen_lshrhi3_i
);
3419 GFF(PSImode
, ASHIFT
, gen_ashlpsi3_i
);
3420 GFF(PSImode
, ASHIFTRT
, gen_ashrpsi3_i
);
3421 GFF(PSImode
, LSHIFTRT
, gen_lshrpsi3_i
);
3422 GFF(SImode
, ASHIFT
, TARGET_A16
? gen_ashlsi3_16
: gen_ashlsi3_24
);
3423 GFF(SImode
, ASHIFTRT
, TARGET_A16
? gen_ashrsi3_16
: gen_ashrsi3_24
);
3424 GFF(SImode
, LSHIFTRT
, TARGET_A16
? gen_lshrsi3_16
: gen_lshrsi3_24
);
3429 /* The m32c only has one shift, but it takes a signed count. GCC
3430 doesn't want this, so we fake it by negating any shift count when
3431 we're pretending to shift the other way. Also, the shift count is
3432 limited to -8..8. It's slightly better to use two shifts for 9..15
3433 than to load the count into r1h, so we do that too. */
3435 m32c_prepare_shift (rtx
* operands
, int scale
, int shift_code
)
3437 enum machine_mode mode
= GET_MODE (operands
[0]);
3438 shift_gen_func func
= shift_gen_func_for (mode
, shift_code
);
3441 if (GET_CODE (operands
[2]) == CONST_INT
)
3443 int maxc
= TARGET_A24
&& (mode
== PSImode
|| mode
== SImode
) ? 32 : 8;
3444 int count
= INTVAL (operands
[2]) * scale
;
3446 while (count
> maxc
)
3448 temp
= gen_reg_rtx (mode
);
3449 emit_insn (func (temp
, operands
[1], GEN_INT (maxc
)));
3453 while (count
< -maxc
)
3455 temp
= gen_reg_rtx (mode
);
3456 emit_insn (func (temp
, operands
[1], GEN_INT (-maxc
)));
3460 emit_insn (func (operands
[0], operands
[1], GEN_INT (count
)));
3464 temp
= gen_reg_rtx (QImode
);
3466 /* The pattern has a NEG that corresponds to this. */
3467 emit_move_insn (temp
, gen_rtx_NEG (QImode
, operands
[2]));
3468 else if (TARGET_A16
&& mode
== SImode
)
3469 /* We do this because the code below may modify this, we don't
3470 want to modify the origin of this value. */
3471 emit_move_insn (temp
, operands
[2]);
3473 /* We'll only use it for the shift, no point emitting a move. */
3476 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 4)
3478 /* The m16c has a limit of -16..16 for SI shifts, even when the
3479 shift count is in a register. Since there are so many targets
3480 of these shifts, it's better to expand the RTL here than to
3481 call a helper function.
3483 The resulting code looks something like this:
3495 We take advantage of the fact that "negative" shifts are
3496 undefined to skip one of the comparisons. */
3499 rtx label
, lref
, insn
, tempvar
;
3501 emit_move_insn (operands
[0], operands
[1]);
3504 label
= gen_label_rtx ();
3505 lref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
3506 LABEL_NUSES (label
) ++;
3508 tempvar
= gen_reg_rtx (mode
);
3510 if (shift_code
== ASHIFT
)
3512 /* This is a left shift. We only need check positive counts. */
3513 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode
, 0, 0),
3514 count
, GEN_INT (16), label
));
3515 emit_insn (func (tempvar
, operands
[0], GEN_INT (8)));
3516 emit_insn (func (operands
[0], tempvar
, GEN_INT (8)));
3517 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (-16)));
3518 emit_label_after (label
, insn
);
3522 /* This is a right shift. We only need check negative counts. */
3523 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode
, 0, 0),
3524 count
, GEN_INT (-16), label
));
3525 emit_insn (func (tempvar
, operands
[0], GEN_INT (-8)));
3526 emit_insn (func (operands
[0], tempvar
, GEN_INT (-8)));
3527 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (16)));
3528 emit_label_after (label
, insn
);
3530 operands
[1] = operands
[0];
3531 emit_insn (func (operands
[0], operands
[0], count
));
3539 /* The m32c has a limited range of operations that work on PSImode
3540 values; we have to expand to SI, do the math, and truncate back to
3541 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3544 m32c_expand_neg_mulpsi3 (rtx
* operands
)
3546 /* operands: a = b * i */
3547 rtx temp1
; /* b as SI */
3548 rtx scale
/* i as SI */;
3549 rtx temp2
; /* a*b as SI */
3551 temp1
= gen_reg_rtx (SImode
);
3552 temp2
= gen_reg_rtx (SImode
);
3553 if (GET_CODE (operands
[2]) != CONST_INT
)
3555 scale
= gen_reg_rtx (SImode
);
3556 emit_insn (gen_zero_extendpsisi2 (scale
, operands
[2]));
3559 scale
= copy_to_mode_reg (SImode
, operands
[2]);
3561 emit_insn (gen_zero_extendpsisi2 (temp1
, operands
[1]));
3562 temp2
= expand_simple_binop (SImode
, MULT
, temp1
, scale
, temp2
, 1, OPTAB_LIB
);
3563 emit_insn (gen_truncsipsi2 (operands
[0], temp2
));
3566 static rtx compare_op0
, compare_op1
;
3569 m32c_pend_compare (rtx
*operands
)
3571 compare_op0
= operands
[0];
3572 compare_op1
= operands
[1];
3576 m32c_unpend_compare (void)
3578 switch (GET_MODE (compare_op0
))
3581 emit_insn (gen_cmpqi_op (compare_op0
, compare_op1
));
3583 emit_insn (gen_cmphi_op (compare_op0
, compare_op1
));
3585 emit_insn (gen_cmppsi_op (compare_op0
, compare_op1
));
3587 /* Just to silence the "missing case" warnings. */ ;
3592 m32c_expand_scc (int code
, rtx
*operands
)
3594 enum machine_mode mode
= TARGET_A16
? QImode
: HImode
;
3596 emit_insn (gen_rtx_SET (mode
,
3598 gen_rtx_fmt_ee (code
,
3604 /* Pattern Output Functions */
3606 /* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
3607 match_operand rtx's OP. */
3609 m32c_cmp_flg_0 (rtx cmp
)
3611 return gen_rtx_fmt_ee (GET_CODE (cmp
),
3613 gen_rtx_REG (CCmode
, FLG_REGNO
),
3618 m32c_expand_movcc (rtx
*operands
)
3620 rtx rel
= operands
[1];
3623 if (GET_CODE (rel
) != EQ
&& GET_CODE (rel
) != NE
)
3625 if (GET_CODE (operands
[2]) != CONST_INT
3626 || GET_CODE (operands
[3]) != CONST_INT
)
3628 emit_insn (gen_cmpqi(XEXP (rel
, 0), XEXP (rel
, 1)));
3629 if (GET_CODE (rel
) == NE
)
3631 rtx tmp
= operands
[2];
3632 operands
[2] = operands
[3];
3636 cmp
= gen_rtx_fmt_ee (GET_CODE (rel
),
3641 emit_move_insn (operands
[0],
3642 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3649 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3651 m32c_expand_insv (rtx
*operands
)
3656 if (INTVAL (operands
[1]) != 1)
3659 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3660 if (GET_CODE (operands
[3]) != CONST_INT
)
3662 if (INTVAL (operands
[3]) != 0
3663 && INTVAL (operands
[3]) != 1
3664 && INTVAL (operands
[3]) != -1)
3667 mask
= 1 << INTVAL (operands
[2]);
3670 if (GET_CODE (op0
) == SUBREG
3671 && SUBREG_BYTE (op0
) == 0)
3673 rtx sub
= SUBREG_REG (op0
);
3674 if (GET_MODE (sub
) == HImode
|| GET_MODE (sub
) == QImode
)
3679 || (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
)))
3683 src0
= gen_reg_rtx (GET_MODE (op0
));
3684 emit_move_insn (src0
, op0
);
3687 if (GET_MODE (op0
) == HImode
3688 && INTVAL (operands
[2]) >= 8
3689 && GET_MODE (op0
) == MEM
)
3691 /* We are little endian. */
3692 rtx new_mem
= gen_rtx_MEM (QImode
, plus_constant (XEXP (op0
, 0), 1));
3693 MEM_COPY_ATTRIBUTES (new_mem
, op0
);
3697 /* First, we generate a mask with the correct polarity. If we are
3698 storing a zero, we want an AND mask, so invert it. */
3699 if (INTVAL (operands
[3]) == 0)
3701 /* Storing a zero, use an AND mask */
3702 if (GET_MODE (op0
) == HImode
)
3707 /* Now we need to properly sign-extend the mask in case we need to
3708 fall back to an AND or OR opcode. */
3709 if (GET_MODE (op0
) == HImode
)
3720 switch ( (INTVAL (operands
[3]) ? 4 : 0)
3721 + ((GET_MODE (op0
) == HImode
) ? 2 : 0)
3722 + (TARGET_A24
? 1 : 0))
3724 case 0: p
= gen_andqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3725 case 1: p
= gen_andqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3726 case 2: p
= gen_andhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3727 case 3: p
= gen_andhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3728 case 4: p
= gen_iorqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3729 case 5: p
= gen_iorqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3730 case 6: p
= gen_iorhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3731 case 7: p
= gen_iorhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3739 m32c_scc_pattern(rtx
*operands
, RTX_CODE code
)
3741 static char buf
[30];
3742 if (GET_CODE (operands
[0]) == REG
3743 && REGNO (operands
[0]) == R0_REGNO
)
3746 return "stzx\t#1,#0,r0l";
3748 return "stzx\t#0,#1,r0l";
3750 sprintf(buf
, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code
));
3754 /* Returns TRUE if the current function is a leaf, and thus we can
3755 determine which registers an interrupt function really needs to
3756 save. The logic below is mostly about finding the insn sequence
3757 that's the function, versus any sequence that might be open for the
3760 m32c_leaf_function_p (void)
3762 rtx saved_first
, saved_last
;
3763 struct sequence_stack
*seq
;
3766 saved_first
= cfun
->emit
->x_first_insn
;
3767 saved_last
= cfun
->emit
->x_last_insn
;
3768 for (seq
= cfun
->emit
->sequence_stack
; seq
&& seq
->next
; seq
= seq
->next
)
3772 cfun
->emit
->x_first_insn
= seq
->first
;
3773 cfun
->emit
->x_last_insn
= seq
->last
;
3776 rv
= leaf_function_p ();
3778 cfun
->emit
->x_first_insn
= saved_first
;
3779 cfun
->emit
->x_last_insn
= saved_last
;
3783 /* Returns TRUE if the current function needs to use the ENTER/EXIT
3784 opcodes. If the function doesn't need the frame base or stack
3785 pointer, it can use the simpler RTS opcode. */
3787 m32c_function_needs_enter (void)
3790 struct sequence_stack
*seq
;
3791 rtx sp
= gen_rtx_REG (Pmode
, SP_REGNO
);
3792 rtx fb
= gen_rtx_REG (Pmode
, FB_REGNO
);
3794 insn
= get_insns ();
3795 for (seq
= cfun
->emit
->sequence_stack
;
3797 insn
= seq
->first
, seq
= seq
->next
);
3801 if (reg_mentioned_p (sp
, insn
))
3803 if (reg_mentioned_p (fb
, insn
))
3805 insn
= NEXT_INSN (insn
);
3810 /* Mark all the subexpressions of the PARALLEL rtx PAR as
3811 frame-related. Return PAR.
3813 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3814 PARALLEL rtx other than the first if they do not have the
3815 FRAME_RELATED flag set on them. So this function is handy for
3816 marking up 'enter' instructions. */
3818 m32c_all_frame_related (rtx par
)
3820 int len
= XVECLEN (par
, 0);
3823 for (i
= 0; i
< len
; i
++)
3824 F (XVECEXP (par
, 0, i
));
3829 /* Emits the prologue. See the frame layout comment earlier in this
3830 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3831 that we manually update sp. */
3833 m32c_emit_prologue (void)
3835 int frame_size
, extra_frame_size
= 0, reg_save_size
;
3836 int complex_prologue
= 0;
3838 cfun
->machine
->is_leaf
= m32c_leaf_function_p ();
3839 if (interrupt_p (cfun
->decl
))
3841 cfun
->machine
->is_interrupt
= 1;
3842 complex_prologue
= 1;
3845 reg_save_size
= m32c_pushm_popm (PP_justcount
);
3847 if (interrupt_p (cfun
->decl
))
3848 emit_insn (gen_pushm (GEN_INT (cfun
->machine
->intr_pushm
)));
3851 m32c_initial_elimination_offset (FB_REGNO
, SP_REGNO
) - reg_save_size
;
3853 && !cfun
->machine
->is_interrupt
3854 && !m32c_function_needs_enter ())
3855 cfun
->machine
->use_rts
= 1;
3857 if (frame_size
> 254)
3859 extra_frame_size
= frame_size
- 254;
3862 if (cfun
->machine
->use_rts
== 0)
3863 F (emit_insn (m32c_all_frame_related
3865 ? gen_prologue_enter_16 (GEN_INT (frame_size
))
3866 : gen_prologue_enter_24 (GEN_INT (frame_size
)))));
3868 if (extra_frame_size
)
3870 complex_prologue
= 1;
3872 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode
, SP_REGNO
),
3873 gen_rtx_REG (HImode
, SP_REGNO
),
3874 GEN_INT (-extra_frame_size
))));
3876 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode
, SP_REGNO
),
3877 gen_rtx_REG (PSImode
, SP_REGNO
),
3878 GEN_INT (-extra_frame_size
))));
3881 complex_prologue
+= m32c_pushm_popm (PP_pushm
);
3883 /* This just emits a comment into the .s file for debugging. */
3884 if (complex_prologue
)
3885 emit_insn (gen_prologue_end ());
3888 /* Likewise, for the epilogue. The only exception is that, for
3889 interrupts, we must manually unwind the frame as the REIT opcode
3892 m32c_emit_epilogue (void)
3894 /* This just emits a comment into the .s file for debugging. */
3895 if (m32c_pushm_popm (PP_justcount
) > 0 || cfun
->machine
->is_interrupt
)
3896 emit_insn (gen_epilogue_start ());
3898 m32c_pushm_popm (PP_popm
);
3900 if (cfun
->machine
->is_interrupt
)
3902 enum machine_mode spmode
= TARGET_A16
? HImode
: PSImode
;
3904 emit_move_insn (gen_rtx_REG (spmode
, A0_REGNO
),
3905 gen_rtx_REG (spmode
, FP_REGNO
));
3906 emit_move_insn (gen_rtx_REG (spmode
, SP_REGNO
),
3907 gen_rtx_REG (spmode
, A0_REGNO
));
3909 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, FP_REGNO
)));
3911 emit_insn (gen_poppsi (gen_rtx_REG (PSImode
, FP_REGNO
)));
3912 emit_insn (gen_popm (GEN_INT (cfun
->machine
->intr_pushm
)));
3913 emit_jump_insn (gen_epilogue_reit (GEN_INT (TARGET_A16
? 4 : 6)));
3915 else if (cfun
->machine
->use_rts
)
3916 emit_jump_insn (gen_epilogue_rts ());
3918 emit_jump_insn (gen_epilogue_exitd (GEN_INT (TARGET_A16
? 2 : 4)));
3923 m32c_emit_eh_epilogue (rtx ret_addr
)
3925 /* R0[R2] has the stack adjustment. R1[R3] has the address to
3926 return to. We have to fudge the stack, pop everything, pop SP
3927 (fudged), and return (fudged). This is actually easier to do in
3928 assembler, so punt to libgcc. */
3929 emit_jump_insn (gen_eh_epilogue (ret_addr
, cfun
->machine
->eh_stack_adjust
));
3930 /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
3934 /* Indicate which flags must be properly set for a given conditional. */
3936 flags_needed_for_conditional (rtx cond
)
3938 switch (GET_CODE (cond
))
3962 /* Returns true if a compare insn is redundant because it would only
3963 set flags that are already set correctly. */
3965 m32c_compare_redundant (rtx cmp
, rtx
*operands
)
3980 fprintf(stderr
, "\n\033[32mm32c_compare_redundant\033[0m\n");
3984 fprintf(stderr
, "operands[%d] = ", i
);
3985 debug_rtx(operands
[i
]);
3989 next
= next_nonnote_insn (cmp
);
3990 if (!next
|| !INSN_P (next
))
3993 fprintf(stderr
, "compare not followed by insn\n");
3998 if (GET_CODE (PATTERN (next
)) == SET
3999 && GET_CODE (XEXP ( PATTERN (next
), 1)) == IF_THEN_ELSE
)
4001 next
= XEXP (XEXP (PATTERN (next
), 1), 0);
4003 else if (GET_CODE (PATTERN (next
)) == SET
)
4005 /* If this is a conditional, flags_needed will be something
4006 other than FLAGS_N, which we test below. */
4007 next
= XEXP (PATTERN (next
), 1);
4012 fprintf(stderr
, "compare not followed by conditional\n");
4018 fprintf(stderr
, "conditional is: ");
4022 flags_needed
= flags_needed_for_conditional (next
);
4023 if (flags_needed
== FLAGS_N
)
4026 fprintf(stderr
, "compare not followed by conditional\n");
4032 /* Compare doesn't set overflow and carry the same way that
4033 arithmetic instructions do, so we can't replace those. */
4034 if (flags_needed
& FLAGS_OC
)
4039 prev
= prev_nonnote_insn (prev
);
4043 fprintf(stderr
, "No previous insn.\n");
4050 fprintf(stderr
, "Previous insn is a non-insn.\n");
4054 pp
= PATTERN (prev
);
4055 if (GET_CODE (pp
) != SET
)
4058 fprintf(stderr
, "Previous insn is not a SET.\n");
4062 pflags
= get_attr_flags (prev
);
4064 /* Looking up attributes of previous insns corrupted the recog
4066 INSN_UID (cmp
) = -1;
4067 recog (PATTERN (cmp
), cmp
, 0);
4069 if (pflags
== FLAGS_N
4070 && reg_mentioned_p (op0
, pp
))
4073 fprintf(stderr
, "intermediate non-flags insn uses op:\n");
4078 } while (pflags
== FLAGS_N
);
4080 fprintf(stderr
, "previous flag-setting insn:\n");
4085 if (GET_CODE (pp
) == SET
4086 && GET_CODE (XEXP (pp
, 0)) == REG
4087 && REGNO (XEXP (pp
, 0)) == FLG_REGNO
4088 && GET_CODE (XEXP (pp
, 1)) == COMPARE
)
4090 /* Adjacent cbranches must have the same operands to be
4092 rtx pop0
= XEXP (XEXP (pp
, 1), 0);
4093 rtx pop1
= XEXP (XEXP (pp
, 1), 1);
4095 fprintf(stderr
, "adjacent cbranches\n");
4099 if (rtx_equal_p (op0
, pop0
)
4100 && rtx_equal_p (op1
, pop1
))
4103 fprintf(stderr
, "prev cmp not same\n");
4108 /* Else the previous insn must be a SET, with either the source or
4109 dest equal to operands[0], and operands[1] must be zero. */
4111 if (!rtx_equal_p (op1
, const0_rtx
))
4114 fprintf(stderr
, "operands[1] not const0_rtx\n");
4118 if (GET_CODE (pp
) != SET
)
4121 fprintf (stderr
, "pp not set\n");
4125 if (!rtx_equal_p (op0
, SET_SRC (pp
))
4126 && !rtx_equal_p (op0
, SET_DEST (pp
)))
4129 fprintf(stderr
, "operands[0] not found in set\n");
4135 fprintf(stderr
, "cmp flags %x prev flags %x\n", flags_needed
, pflags
);
4137 if ((pflags
& flags_needed
) == flags_needed
)
4143 /* Return the pattern for a compare. This will be commented out if
4144 the compare is redundant, else a normal pattern is returned. Thus,
4145 the assembler output says where the compare would have been. */
4147 m32c_output_compare (rtx insn
, rtx
*operands
)
4149 static char template[] = ";cmp.b\t%1,%0";
4152 template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands
[0]))];
4153 if (m32c_compare_redundant (insn
, operands
))
4156 fprintf(stderr
, "cbranch: cmp not needed\n");
4162 fprintf(stderr
, "cbranch: cmp needed: `%s'\n", template);
4164 return template + 1;
4167 /* The Global `targetm' Variable. */
4169 struct gcc_target targetm
= TARGET_INITIALIZER
;
4171 #include "gt-m32c.h"