1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
102 ;; These are used with unspec.
114 ;; These are used with unspec_volatile.
120 (UNSPECV_CONST_END 11)
123 ;; -------------------------------------------------------------------------
125 ;; -------------------------------------------------------------------------
130 "sh1,sh2,sh3,sh3e,sh4"
131 (const (symbol_ref "sh_cpu_attr")))
133 (define_attr "endian" "big,little"
134 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
135 (const_string "little") (const_string "big"))))
137 ;; Indicate if the default fpu mode is single precision.
138 (define_attr "fpu_single" "yes,no"
139 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
140 (const_string "yes") (const_string "no"))))
142 (define_attr "fmovd" "yes,no"
143 (const (if_then_else (symbol_ref "TARGET_FMOVD")
144 (const_string "yes") (const_string "no"))))
146 (define_attr "issues" "1,2"
147 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
149 ;; cbranch conditional branch instructions
150 ;; jump unconditional jumps
151 ;; arith ordinary arithmetic
152 ;; arith3 a compound insn that behaves similarly to a sequence of
153 ;; three insns of type arith
154 ;; arith3b like above, but might end with a redirected branch
156 ;; load_si Likewise, SImode variant for general register.
158 ;; move register to register
159 ;; fmove register to register, floating point
160 ;; smpy word precision integer multiply
161 ;; dmpy longword or doublelongword precision integer multiply
163 ;; pload load of pr reg, which can't be put into delay slot of rts
164 ;; pstore store of pr reg, which can't be put into delay slot of jsr
165 ;; pcload pc relative load of constant value
166 ;; pcload_si Likewise, SImode variant for general register.
167 ;; rte return from exception
168 ;; sfunc special function call with known used registers
169 ;; call function call
171 ;; fdiv floating point divide (or square root)
172 ;; gp_fpul move between general purpose register and fpul
173 ;; dfp_arith, dfp_cmp,dfp_conv
174 ;; dfdiv double precision floating point divide (or square root)
175 ;; nil no-op move, will be deleted.
178 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
179 (const_string "other"))
181 ;; Indicate what precision must be selected in fpscr for this insn, if any.
183 (define_attr "fp_mode" "single,double,none" (const_string "none"))
185 ; If a conditional branch destination is within -252..258 bytes away
186 ; from the instruction it can be 2 bytes long. Something in the
187 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
188 ; branches are initially assumed to be 16 bytes long.
189 ; In machine_dependent_reorg, we split all branches that are longer than
192 ;; The maximum range used for SImode constant pool entrys is 1018. A final
193 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
194 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
195 ;; instruction around the pool table, 2 bytes of alignment before the table,
196 ;; and 30 bytes of alignment after the table. That gives a maximum total
197 ;; pool size of 1058 bytes.
198 ;; Worst case code/pool content size ratio is 1:2 (using asms).
199 ;; Thus, in the worst case, there is one instruction in front of a maximum
200 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
201 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
202 ;; If we have a forward branch, the initial table will be put after the
203 ;; unconditional branch.
205 ;; ??? We could do much better by keeping track of the actual pcloads within
206 ;; the branch range and in the pcload range in front of the branch range.
208 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
210 (define_attr "short_cbranch_p" "no,yes"
211 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
213 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
215 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
217 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
219 ] (const_string "no")))
221 (define_attr "med_branch_p" "no,yes"
222 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
225 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
227 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
230 ] (const_string "no")))
232 (define_attr "med_cbranch_p" "no,yes"
233 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
236 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
238 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
241 ] (const_string "no")))
243 (define_attr "braf_branch_p" "no,yes"
244 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
246 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
249 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
251 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
254 ] (const_string "no")))
256 (define_attr "braf_cbranch_p" "no,yes"
257 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
259 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
262 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
264 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
267 ] (const_string "no")))
269 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
270 ; For wider ranges, we need a combination of a code and a data part.
271 ; If we can get a scratch register for a long range jump, the code
272 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
273 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
274 ; long; otherwise, it must be 6 bytes long.
276 ; All other instructions are two bytes long by default.
278 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
279 ;; but getattrtab doesn't understand this.
280 (define_attr "length" ""
281 (cond [(eq_attr "type" "cbranch")
282 (cond [(eq_attr "short_cbranch_p" "yes")
284 (eq_attr "med_cbranch_p" "yes")
286 (eq_attr "braf_cbranch_p" "yes")
288 ;; ??? using pc is not computed transitively.
289 (ne (match_dup 0) (match_dup 0))
292 (eq_attr "type" "jump")
293 (cond [(eq_attr "med_branch_p" "yes")
295 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
297 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
298 (symbol_ref "code_for_indirect_jump_scratch")))
299 (if_then_else (eq_attr "braf_branch_p" "yes")
302 (eq_attr "braf_branch_p" "yes")
304 ;; ??? using pc is not computed transitively.
305 (ne (match_dup 0) (match_dup 0))
310 ;; (define_function_unit {name} {num-units} {n-users} {test}
311 ;; {ready-delay} {issue-delay} [{conflict-list}])
313 ;; Load and store instructions save a cycle if they are aligned on a
314 ;; four byte boundary. Using a function unit for stores encourages
315 ;; gcc to separate load and store instructions by one instruction,
316 ;; which makes it more likely that the linker will be able to word
317 ;; align them when relaxing.
319 ;; Loads have a latency of two.
320 ;; However, call insns can have a delay slot, so that we want one more
321 ;; insn to be scheduled between the load of the function address and the call.
322 ;; This is equivalent to a latency of three.
323 ;; We cannot use a conflict list for this, because we need to distinguish
324 ;; between the actual call address and the function arguments.
325 ;; ADJUST_COST can only properly handle reductions of the cost, so we
326 ;; use a latency of three here.
327 ;; We only do this for SImode loads of general registers, to make the work
328 ;; for ADJUST_COST easier.
329 (define_function_unit "memory" 1 0
330 (and (eq_attr "issues" "1")
331 (eq_attr "type" "load_si,pcload_si"))
333 (define_function_unit "memory" 1 0
334 (and (eq_attr "issues" "1")
335 (eq_attr "type" "load,pcload,pload,store,pstore"))
338 (define_function_unit "int" 1 0
339 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
341 (define_function_unit "int" 1 0
342 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
344 (define_function_unit "int" 1 0
345 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
347 ;; ??? These are approximations.
348 (define_function_unit "mpy" 1 0
349 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
350 (define_function_unit "mpy" 1 0
351 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
353 (define_function_unit "fp" 1 0
354 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
355 (define_function_unit "fp" 1 0
356 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
360 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
361 ;; costs by at least two.
362 ;; There will be single increments of the modeled that don't correspond
363 ;; to the actual target ;; whenever two insns to be issued depend one a
364 ;; single resource, and the scheduler picks to be the first one.
365 ;; If we multiplied the costs just by two, just two of these single
366 ;; increments would amount to an actual cycle. By picking a larger
367 ;; factor, we can ameliorate the effect; However, we then have to make sure
368 ;; that only two insns are modeled as issued per actual cycle.
369 ;; Moreover, we need a way to specify the latency of insns that don't
370 ;; use an actual function unit.
371 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
373 (define_function_unit "issue" 2 0
374 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
377 (define_function_unit "issue" 2 0
378 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
381 ;; There is no point in providing exact scheduling information about branches,
382 ;; because they are at the starts / ends of basic blocks anyways.
384 ;; Some insns cannot be issued before/after another insn in the same cycle,
385 ;; irrespective of the type of the other insn.
387 ;; default is dual-issue, but can't be paired with an insn that
388 ;; uses multiple function units.
389 (define_function_unit "single_issue" 1 0
390 (and (eq_attr "issues" "2")
391 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
393 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
395 (define_function_unit "single_issue" 1 0
396 (and (eq_attr "issues" "2")
397 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
401 ;; arith3 insns are always pairable at the start, but not inecessarily at
402 ;; the end; however, there doesn;t seem to be a way to express that.
403 (define_function_unit "single_issue" 1 0
404 (and (eq_attr "issues" "2")
405 (eq_attr "type" "arith3"))
409 ;; arith3b insn are pairable at the end and have latency that prevents pairing
410 ;; with the following branch, but we don't want this latency be respected;
411 ;; When the following branch is immediately adjacent, we can redirect the
412 ;; internal branch, which is likly to be a larger win.
413 (define_function_unit "single_issue" 1 0
414 (and (eq_attr "issues" "2")
415 (eq_attr "type" "arith3b"))
419 ;; calls introduce a longisch delay that is likely to flush the pipelines.
420 (define_function_unit "single_issue" 1 0
421 (and (eq_attr "issues" "2")
422 (eq_attr "type" "call,sfunc"))
424 [(eq_attr "type" "!call") (eq_attr "type" "call")])
426 ;; Load and store instructions have no alignment peculiarities for the SH4,
427 ;; but they use the load-store unit, which they share with the fmove type
428 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
429 ;; Loads have a latency of two.
430 ;; However, call insns can only paired with a preceding insn, and have
431 ;; a delay slot, so that we want two more insns to be scheduled between the
432 ;; load of the function address and the call. This is equivalent to a
434 ;; We cannot use a conflict list for this, because we need to distinguish
435 ;; between the actual call address and the function arguments.
436 ;; ADJUST_COST can only properly handle reductions of the cost, so we
437 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
438 ;; We only do this for SImode loads of general registers, to make the work
439 ;; for ADJUST_COST easier.
441 ;; When specifying different latencies for different insns using the
442 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
443 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
444 ;; for an executing insn E and a candidate insn C.
445 ;; Therefore, we define three different function units for load_store:
446 ;; load_store, load and load_si.
448 (define_function_unit "load_si" 1 0
449 (and (eq_attr "issues" "2")
450 (eq_attr "type" "load_si,pcload_si")) 30 10)
451 (define_function_unit "load" 1 0
452 (and (eq_attr "issues" "2")
453 (eq_attr "type" "load,pcload,pload")) 20 10)
454 (define_function_unit "load_store" 1 0
455 (and (eq_attr "issues" "2")
456 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
459 (define_function_unit "int" 1 0
460 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
462 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
463 ;; spurious FIFO constraint; the multiply instructions use the "int"
464 ;; unit actually only for two cycles.
465 (define_function_unit "int" 1 0
466 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
468 ;; We use a fictous "mpy" unit to express the actual latency.
469 (define_function_unit "mpy" 1 0
470 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
472 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
473 ;; spurious FIFO constraint.
474 (define_function_unit "int" 1 0
475 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
477 ;; We use a fictous "gp_fpul" unit to express the actual latency.
478 (define_function_unit "gp_fpul" 1 0
479 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
481 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
482 ;; Thus, a simple single-precision fp operation could finish if issued in
483 ;; the very next cycle, but stalls when issued two or three cycles later.
484 ;; Similarily, a divide / sqrt can work without stalls if issued in
485 ;; the very next cycle, while it would have to block if issued two or
486 ;; three cycles later.
487 ;; There is no way to model this with gcc's function units. This problem is
488 ;; actually mentioned in md.texi. Tackling this problem requires first that
489 ;; it is possible to speak about the target in an open discussion.
491 ;; However, simple double-precision operations always conflict.
493 (define_function_unit "fp" 1 0
494 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
495 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
497 ;; The "fp" unit is for pipeline stages F1 and F2.
499 (define_function_unit "fp" 1 0
500 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
502 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
503 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
505 (define_function_unit "fp" 1 0
506 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
508 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
509 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
510 ;; We also use it to give the actual latency here.
511 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
512 ;; but that will hardly matter in practice for scheduling.
513 (define_function_unit "fdiv" 1 0
514 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
516 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
517 ;; that we can't express.
519 (define_function_unit "fp" 1 0
520 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
522 (define_function_unit "fp" 1 0
523 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
525 (define_function_unit "fp" 1 0
526 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
528 (define_function_unit "fdiv" 1 0
529 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
531 ; Definitions for filling branch delay slots.
533 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
535 ;; ??? This should be (nil) instead of (const_int 0)
536 (define_attr "hit_stack" "yes,no"
537 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
540 (const_string "yes")))
542 (define_attr "interrupt_function" "no,yes"
543 (const (symbol_ref "pragma_interrupt")))
545 (define_attr "in_delay_slot" "yes,no"
546 (cond [(eq_attr "type" "cbranch") (const_string "no")
547 (eq_attr "type" "pcload,pcload_si") (const_string "no")
548 (eq_attr "needs_delay_slot" "yes") (const_string "no")
549 (eq_attr "length" "2") (const_string "yes")
550 ] (const_string "no")))
552 (define_attr "is_sfunc" ""
553 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
556 (eq_attr "needs_delay_slot" "yes")
557 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
559 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
560 ;; and thus we can't put a pop instruction in its delay slot.
561 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
562 ;; instruction can go in the delay slot.
564 ;; Since a normal return (rts) implicitly uses the PR register,
565 ;; we can't allow PR register loads in an rts delay slot.
568 (eq_attr "type" "return")
569 [(and (eq_attr "in_delay_slot" "yes")
570 (ior (and (eq_attr "interrupt_function" "no")
571 (eq_attr "type" "!pload"))
572 (and (eq_attr "interrupt_function" "yes")
573 (eq_attr "hit_stack" "no")))) (nil) (nil)])
575 ;; Since a call implicitly uses the PR register, we can't allow
576 ;; a PR register store in a jsr delay slot.
579 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
580 [(and (eq_attr "in_delay_slot" "yes")
581 (eq_attr "type" "!pstore")) (nil) (nil)])
583 ;; Say that we have annulled true branches, since this gives smaller and
584 ;; faster code when branches are predicted as not taken.
587 (and (eq_attr "type" "cbranch")
588 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
589 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
591 ;; -------------------------------------------------------------------------
592 ;; SImode signed integer comparisons
593 ;; -------------------------------------------------------------------------
597 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
598 (match_operand:SI 1 "arith_operand" "L,r"))
603 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
604 ;; That would still allow reload to create cmpi instructions, but would
605 ;; perhaps allow forcing the constant into a register when that is better.
606 ;; Probably should use r0 for mem/imm compares, but force constant into a
607 ;; register for pseudo/imm compares.
609 (define_insn "cmpeqsi_t"
611 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
612 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
619 (define_insn "cmpgtsi_t"
621 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
622 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
628 (define_insn "cmpgesi_t"
630 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
631 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
637 ;; -------------------------------------------------------------------------
638 ;; SImode unsigned integer comparisons
639 ;; -------------------------------------------------------------------------
641 (define_insn "cmpgeusi_t"
643 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
644 (match_operand:SI 1 "arith_reg_operand" "r")))]
648 (define_insn "cmpgtusi_t"
650 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
651 (match_operand:SI 1 "arith_reg_operand" "r")))]
655 ;; We save the compare operands in the cmpxx patterns and use them when
656 ;; we generate the branch.
658 (define_expand "cmpsi"
660 (compare (match_operand:SI 0 "arith_operand" "")
661 (match_operand:SI 1 "arith_operand" "")))]
665 sh_compare_op0 = operands[0];
666 sh_compare_op1 = operands[1];
670 ;; -------------------------------------------------------------------------
671 ;; DImode signed integer comparisons
672 ;; -------------------------------------------------------------------------
674 ;; ??? Could get better scheduling by splitting the initial test from the
675 ;; rest of the insn after reload. However, the gain would hardly justify
676 ;; the sh.md size increase necessary to do that.
680 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
681 (match_operand:DI 1 "arith_operand" "r"))
684 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
686 [(set_attr "length" "6")
687 (set_attr "type" "arith3b")])
689 (define_insn "cmpeqdi_t"
691 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
692 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
695 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
696 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
697 [(set_attr "length" "6")
698 (set_attr "type" "arith3b")])
702 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
703 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
704 ;; If we applied this split when not optimizing, it would only be
705 ;; applied during the machine-dependent reorg, when no new basic blocks
707 "reload_completed && optimize"
708 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
709 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
710 (label_ref (match_dup 6))
712 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
717 = gen_rtx_REG (SImode,
718 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
720 = (operands[1] == const0_rtx
722 : gen_rtx_REG (SImode,
723 true_regnum (operands[1])
724 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
725 operands[4] = gen_lowpart (SImode, operands[0]);
726 operands[5] = gen_lowpart (SImode, operands[1]);
727 operands[6] = gen_label_rtx ();
730 (define_insn "cmpgtdi_t"
732 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
733 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
736 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
737 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
738 [(set_attr "length" "8")
739 (set_attr "type" "arith3")])
741 (define_insn "cmpgedi_t"
743 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
744 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
747 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
749 [(set_attr "length" "8,2")
750 (set_attr "type" "arith3,arith")])
752 ;; -------------------------------------------------------------------------
753 ;; DImode unsigned integer comparisons
754 ;; -------------------------------------------------------------------------
756 (define_insn "cmpgeudi_t"
758 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
759 (match_operand:DI 1 "arith_reg_operand" "r")))]
761 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
762 [(set_attr "length" "8")
763 (set_attr "type" "arith3")])
765 (define_insn "cmpgtudi_t"
767 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
768 (match_operand:DI 1 "arith_reg_operand" "r")))]
770 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
771 [(set_attr "length" "8")
772 (set_attr "type" "arith3")])
774 ;; We save the compare operands in the cmpxx patterns and use them when
775 ;; we generate the branch.
777 (define_expand "cmpdi"
779 (compare (match_operand:DI 0 "arith_operand" "")
780 (match_operand:DI 1 "arith_operand" "")))]
784 sh_compare_op0 = operands[0];
785 sh_compare_op1 = operands[1];
789 ;; -------------------------------------------------------------------------
790 ;; Addition instructions
791 ;; -------------------------------------------------------------------------
793 ;; ??? This should be a define expand.
795 (define_insn "adddi3"
796 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
797 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
798 (match_operand:DI 2 "arith_reg_operand" "r")))
799 (clobber (reg:SI T_REG))]
802 [(set_attr "length" "6")])
805 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
806 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
807 (match_operand:DI 2 "arith_reg_operand" "r")))
808 (clobber (reg:SI T_REG))]
813 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
814 high0 = gen_rtx_REG (SImode,
815 true_regnum (operands[0])
816 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
817 high2 = gen_rtx_REG (SImode,
818 true_regnum (operands[2])
819 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
820 emit_insn (gen_clrt ());
821 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
822 emit_insn (gen_addc1 (high0, high0, high2));
827 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
828 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
829 (match_operand:SI 2 "arith_reg_operand" "r"))
832 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
835 [(set_attr "type" "arith")])
838 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
839 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
840 (match_operand:SI 2 "arith_reg_operand" "r"))
842 (clobber (reg:SI T_REG))]
845 [(set_attr "type" "arith")])
847 (define_insn "addsi3"
848 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
849 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
850 (match_operand:SI 2 "arith_operand" "rI")))]
853 [(set_attr "type" "arith")])
855 ;; -------------------------------------------------------------------------
856 ;; Subtraction instructions
857 ;; -------------------------------------------------------------------------
859 ;; ??? This should be a define expand.
861 (define_insn "subdi3"
862 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
863 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
864 (match_operand:DI 2 "arith_reg_operand" "r")))
865 (clobber (reg:SI T_REG))]
868 [(set_attr "length" "6")])
871 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
872 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
873 (match_operand:DI 2 "arith_reg_operand" "r")))
874 (clobber (reg:SI T_REG))]
879 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
880 high0 = gen_rtx_REG (SImode,
881 true_regnum (operands[0])
882 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
883 high2 = gen_rtx_REG (SImode,
884 true_regnum (operands[2])
885 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
886 emit_insn (gen_clrt ());
887 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
888 emit_insn (gen_subc1 (high0, high0, high2));
893 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
894 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
895 (match_operand:SI 2 "arith_reg_operand" "r"))
898 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
901 [(set_attr "type" "arith")])
904 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
905 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
906 (match_operand:SI 2 "arith_reg_operand" "r"))
908 (clobber (reg:SI T_REG))]
911 [(set_attr "type" "arith")])
913 (define_insn "*subsi3_internal"
914 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
915 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
916 (match_operand:SI 2 "arith_reg_operand" "r")))]
919 [(set_attr "type" "arith")])
921 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
922 ;; will sometimes save one instruction. Otherwise we might get
923 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
926 (define_expand "subsi3"
927 [(set (match_operand:SI 0 "arith_reg_operand" "")
928 (minus:SI (match_operand:SI 1 "arith_operand" "")
929 (match_operand:SI 2 "arith_reg_operand" "")))]
933 if (GET_CODE (operands[1]) == CONST_INT)
935 emit_insn (gen_negsi2 (operands[0], operands[2]));
936 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
941 ;; -------------------------------------------------------------------------
942 ;; Division instructions
943 ;; -------------------------------------------------------------------------
945 ;; We take advantage of the library routines which don't clobber as many
946 ;; registers as a normal function call would.
948 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
949 ;; also has an effect on the register that holds the address of the sfunc.
950 ;; To make this work, we have an extra dummy insns that shows the use
951 ;; of this register for reorg.
953 (define_insn "use_sfunc_addr"
954 [(set (reg:SI PR_REG)
955 (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
958 [(set_attr "length" "0")])
960 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
961 ;; hard register 0. If we used hard register 0, then the next instruction
962 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
963 ;; gets allocated to a stack slot that needs its address reloaded, then
964 ;; there is nothing to prevent reload from using r0 to reload the address.
965 ;; This reload would clobber the value in r0 we are trying to store.
966 ;; If we let reload allocate r0, then this problem can never happen.
968 (define_insn "udivsi3_i1"
969 [(set (match_operand:SI 0 "register_operand" "=z")
970 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
971 (clobber (reg:SI T_REG))
972 (clobber (reg:SI PR_REG))
973 (clobber (reg:SI R4_REG))
974 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
977 [(set_attr "type" "sfunc")
978 (set_attr "needs_delay_slot" "yes")])
980 (define_insn "udivsi3_i4"
981 [(set (match_operand:SI 0 "register_operand" "=y")
982 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
983 (clobber (reg:SI T_REG))
984 (clobber (reg:SI PR_REG))
985 (clobber (reg:DF DR0_REG))
986 (clobber (reg:DF DR2_REG))
987 (clobber (reg:DF DR4_REG))
988 (clobber (reg:SI R0_REG))
989 (clobber (reg:SI R1_REG))
990 (clobber (reg:SI R4_REG))
991 (clobber (reg:SI R5_REG))
992 (use (reg:PSI FPSCR_REG))
993 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
994 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
996 [(set_attr "type" "sfunc")
997 (set_attr "fp_mode" "double")
998 (set_attr "needs_delay_slot" "yes")])
1000 (define_insn "udivsi3_i4_single"
1001 [(set (match_operand:SI 0 "register_operand" "=y")
1002 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1003 (clobber (reg:SI T_REG))
1004 (clobber (reg:SI PR_REG))
1005 (clobber (reg:DF DR0_REG))
1006 (clobber (reg:DF DR2_REG))
1007 (clobber (reg:DF DR4_REG))
1008 (clobber (reg:SI R0_REG))
1009 (clobber (reg:SI R1_REG))
1010 (clobber (reg:SI R4_REG))
1011 (clobber (reg:SI R5_REG))
1012 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1013 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1015 [(set_attr "type" "sfunc")
1016 (set_attr "needs_delay_slot" "yes")])
1018 (define_expand "udivsi3"
1019 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1020 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1021 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1022 (parallel [(set (match_operand:SI 0 "register_operand" "")
1023 (udiv:SI (reg:SI R4_REG)
1025 (clobber (reg:SI T_REG))
1026 (clobber (reg:SI PR_REG))
1027 (clobber (reg:SI R4_REG))
1028 (use (match_dup 3))])]
1034 operands[3] = gen_reg_rtx(SImode);
1035 /* Emit the move of the address to a pseudo outside of the libcall. */
1036 if (TARGET_HARD_SH4 && TARGET_SH3E)
1038 emit_move_insn (operands[3],
1039 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1040 if (TARGET_FPU_SINGLE)
1041 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1043 last = gen_udivsi3_i4 (operands[0], operands[3]);
1047 emit_move_insn (operands[3],
1048 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1049 last = gen_udivsi3_i1 (operands[0], operands[3]);
1051 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1052 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1053 last = emit_insn (last);
1054 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1055 invariant code motion can move it. */
1056 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1057 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1061 (define_insn "divsi3_i1"
1062 [(set (match_operand:SI 0 "register_operand" "=z")
1063 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1064 (clobber (reg:SI T_REG))
1065 (clobber (reg:SI PR_REG))
1066 (clobber (reg:SI R1_REG))
1067 (clobber (reg:SI R2_REG))
1068 (clobber (reg:SI R3_REG))
1069 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1072 [(set_attr "type" "sfunc")
1073 (set_attr "needs_delay_slot" "yes")])
1075 (define_insn "divsi3_i4"
1076 [(set (match_operand:SI 0 "register_operand" "=y")
1077 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1078 (clobber (reg:SI PR_REG))
1079 (clobber (reg:DF DR0_REG))
1080 (clobber (reg:DF DR2_REG))
1081 (use (reg:PSI FPSCR_REG))
1082 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1083 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1085 [(set_attr "type" "sfunc")
1086 (set_attr "fp_mode" "double")
1087 (set_attr "needs_delay_slot" "yes")])
1089 (define_insn "divsi3_i4_single"
1090 [(set (match_operand:SI 0 "register_operand" "=y")
1091 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1092 (clobber (reg:SI PR_REG))
1093 (clobber (reg:DF DR0_REG))
1094 (clobber (reg:DF DR2_REG))
1095 (clobber (reg:SI R2_REG))
1096 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1097 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1099 [(set_attr "type" "sfunc")
1100 (set_attr "needs_delay_slot" "yes")])
1102 (define_expand "divsi3"
1103 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1104 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1105 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1106 (parallel [(set (match_operand:SI 0 "register_operand" "")
1107 (div:SI (reg:SI R4_REG)
1109 (clobber (reg:SI T_REG))
1110 (clobber (reg:SI PR_REG))
1111 (clobber (reg:SI R1_REG))
1112 (clobber (reg:SI R2_REG))
1113 (clobber (reg:SI R3_REG))
1114 (use (match_dup 3))])]
1120 operands[3] = gen_reg_rtx(SImode);
1121 /* Emit the move of the address to a pseudo outside of the libcall. */
1122 if (TARGET_HARD_SH4 && TARGET_SH3E)
1124 emit_move_insn (operands[3],
1125 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1126 if (TARGET_FPU_SINGLE)
1127 last = gen_divsi3_i4_single (operands[0], operands[3]);
1129 last = gen_divsi3_i4 (operands[0], operands[3]);
1133 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1134 last = gen_divsi3_i1 (operands[0], operands[3]);
1136 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1137 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1138 last = emit_insn (last);
1139 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1140 invariant code motion can move it. */
1141 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1142 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1146 ;; -------------------------------------------------------------------------
1147 ;; Multiplication instructions
1148 ;; -------------------------------------------------------------------------
1150 (define_insn "umulhisi3_i"
1151 [(set (reg:SI MACL_REG)
1152 (mult:SI (zero_extend:SI
1153 (match_operand:HI 0 "arith_reg_operand" "r"))
1155 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1158 [(set_attr "type" "smpy")])
1160 (define_insn "mulhisi3_i"
1161 [(set (reg:SI MACL_REG)
1162 (mult:SI (sign_extend:SI
1163 (match_operand:HI 0 "arith_reg_operand" "r"))
1165 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1168 [(set_attr "type" "smpy")])
1170 (define_expand "mulhisi3"
1171 [(set (reg:SI MACL_REG)
1172 (mult:SI (sign_extend:SI
1173 (match_operand:HI 1 "arith_reg_operand" ""))
1175 (match_operand:HI 2 "arith_reg_operand" ""))))
1176 (set (match_operand:SI 0 "arith_reg_operand" "")
1183 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1184 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1185 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1186 invariant code motion can move it. */
1187 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1188 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1192 (define_expand "umulhisi3"
1193 [(set (reg:SI MACL_REG)
1194 (mult:SI (zero_extend:SI
1195 (match_operand:HI 1 "arith_reg_operand" ""))
1197 (match_operand:HI 2 "arith_reg_operand" ""))))
1198 (set (match_operand:SI 0 "arith_reg_operand" "")
1205 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1206 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1207 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1208 invariant code motion can move it. */
1209 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1210 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1214 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1215 ;; a call to a routine which clobbers known registers.
1218 [(set (match_operand:SI 1 "register_operand" "=z")
1219 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1220 (clobber (reg:SI MACL_REG))
1221 (clobber (reg:SI T_REG))
1222 (clobber (reg:SI PR_REG))
1223 (clobber (reg:SI R3_REG))
1224 (clobber (reg:SI R2_REG))
1225 (clobber (reg:SI R1_REG))
1226 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1229 [(set_attr "type" "sfunc")
1230 (set_attr "needs_delay_slot" "yes")])
1232 (define_expand "mulsi3_call"
1233 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1234 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1235 (parallel[(set (match_operand:SI 0 "register_operand" "")
1236 (mult:SI (reg:SI R4_REG)
1238 (clobber (reg:SI MACL_REG))
1239 (clobber (reg:SI T_REG))
1240 (clobber (reg:SI PR_REG))
1241 (clobber (reg:SI R3_REG))
1242 (clobber (reg:SI R2_REG))
1243 (clobber (reg:SI R1_REG))
1244 (use (match_operand:SI 3 "register_operand" ""))])]
1248 (define_insn "mul_l"
1249 [(set (reg:SI MACL_REG)
1250 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1251 (match_operand:SI 1 "arith_reg_operand" "r")))]
1254 [(set_attr "type" "dmpy")])
1256 (define_expand "mulsi3"
1257 [(set (reg:SI MACL_REG)
1258 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1259 (match_operand:SI 2 "arith_reg_operand" "")))
1260 (set (match_operand:SI 0 "arith_reg_operand" "")
1269 /* The address must be set outside the libcall,
1270 since it goes into a pseudo. */
1271 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1272 rtx addr = force_reg (SImode, sym);
1273 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1275 first = XVECEXP (insns, 0, 0);
1276 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1281 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1283 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1284 /* consec_sets_giv can only recognize the first insn that sets a
1285 giv as the giv insn. So we must tag this also with a REG_EQUAL
1287 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1289 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1290 invariant code motion can move it. */
1291 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1292 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1296 (define_insn "mulsidi3_i"
1297 [(set (reg:SI MACH_REG)
1301 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1302 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1304 (set (reg:SI MACL_REG)
1305 (mult:SI (match_dup 0)
1309 [(set_attr "type" "dmpy")])
1311 (define_insn "mulsidi3"
1312 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1314 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1315 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1316 (clobber (reg:SI MACH_REG))
1317 (clobber (reg:SI MACL_REG))]
1322 [(set (match_operand:DI 0 "arith_reg_operand" "")
1324 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1325 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1326 (clobber (reg:SI MACH_REG))
1327 (clobber (reg:SI MACL_REG))]
1332 rtx low_dst = gen_lowpart (SImode, operands[0]);
1333 rtx high_dst = gen_highpart (SImode, operands[0]);
1335 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1337 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1338 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1339 /* We need something to tag the possible REG_EQUAL notes on to. */
1340 emit_move_insn (operands[0], operands[0]);
1344 (define_insn "umulsidi3_i"
1345 [(set (reg:SI MACH_REG)
1349 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1350 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1352 (set (reg:SI MACL_REG)
1353 (mult:SI (match_dup 0)
1357 [(set_attr "type" "dmpy")])
1359 (define_insn "umulsidi3"
1360 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1362 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1363 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1364 (clobber (reg:SI MACH_REG))
1365 (clobber (reg:SI MACL_REG))]
1370 [(set (match_operand:DI 0 "arith_reg_operand" "")
1371 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1372 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1373 (clobber (reg:SI MACH_REG))
1374 (clobber (reg:SI MACL_REG))]
1379 rtx low_dst = gen_lowpart (SImode, operands[0]);
1380 rtx high_dst = gen_highpart (SImode, operands[0]);
1382 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1384 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1385 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1386 /* We need something to tag the possible REG_EQUAL notes on to. */
1387 emit_move_insn (operands[0], operands[0]);
1391 (define_insn "smulsi3_highpart_i"
1392 [(set (reg:SI MACH_REG)
1396 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1397 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1399 (clobber (reg:SI MACL_REG))]
1402 [(set_attr "type" "dmpy")])
1404 (define_expand "smulsi3_highpart"
1406 [(set (reg:SI MACH_REG)
1410 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1411 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1413 (clobber (reg:SI MACL_REG))])
1414 (set (match_operand:SI 0 "arith_reg_operand" "")
1421 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1422 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1423 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1424 invariant code motion can move it. */
1425 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1426 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1427 /* expand_binop can't find a suitable code in mul_highpart_optab to
1428 make a REG_EQUAL note from, so make one here.
1429 ??? Alternatively, we could put this at the calling site of expand_binop,
1430 i.e. expand_mult_highpart. */
1432 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1437 (define_insn "umulsi3_highpart_i"
1438 [(set (reg:SI MACH_REG)
1442 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1443 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1445 (clobber (reg:SI MACL_REG))]
1448 [(set_attr "type" "dmpy")])
1450 (define_expand "umulsi3_highpart"
1452 [(set (reg:SI MACH_REG)
1456 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1457 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1459 (clobber (reg:SI MACL_REG))])
1460 (set (match_operand:SI 0 "arith_reg_operand" "")
1467 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1468 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1469 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1470 invariant code motion can move it. */
1471 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1472 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1476 ;; -------------------------------------------------------------------------
1477 ;; Logical operations
1478 ;; -------------------------------------------------------------------------
1481 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1482 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1483 (match_operand:SI 2 "logical_operand" "r,L")))]
1486 [(set_attr "type" "arith")])
1488 ;; If the constant is 255, then emit a extu.b instruction instead of an
1489 ;; and, since that will give better code.
1491 (define_expand "andsi3"
1492 [(set (match_operand:SI 0 "arith_reg_operand" "")
1493 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1494 (match_operand:SI 2 "logical_operand" "")))]
1498 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1500 emit_insn (gen_zero_extendqisi2 (operands[0],
1501 gen_lowpart (QImode, operands[1])));
1506 (define_insn "iorsi3"
1507 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1508 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1509 (match_operand:SI 2 "logical_operand" "r,L")))]
1512 [(set_attr "type" "arith")])
1514 (define_insn "xorsi3"
1515 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1516 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1517 (match_operand:SI 2 "logical_operand" "L,r")))]
1520 [(set_attr "type" "arith")])
1522 ;; -------------------------------------------------------------------------
1523 ;; Shifts and rotates
1524 ;; -------------------------------------------------------------------------
1526 (define_insn "rotlsi3_1"
1527 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1528 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1531 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1534 [(set_attr "type" "arith")])
1536 (define_insn "rotlsi3_31"
1537 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1538 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1540 (clobber (reg:SI T_REG))]
1543 [(set_attr "type" "arith")])
1545 (define_insn "rotlsi3_16"
1546 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1547 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1551 [(set_attr "type" "arith")])
1553 (define_expand "rotlsi3"
1554 [(set (match_operand:SI 0 "arith_reg_operand" "")
1555 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1556 (match_operand:SI 2 "immediate_operand" "")))]
1560 static char rot_tab[] = {
1561 000, 000, 000, 000, 000, 000, 010, 001,
1562 001, 001, 011, 013, 003, 003, 003, 003,
1563 003, 003, 003, 003, 003, 013, 012, 002,
1564 002, 002, 010, 000, 000, 000, 000, 000,
1569 if (GET_CODE (operands[2]) != CONST_INT)
1571 count = INTVAL (operands[2]);
1572 choice = rot_tab[count];
1573 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1579 emit_move_insn (operands[0], operands[1]);
1580 count -= (count & 16) * 2;
1583 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1590 parts[0] = gen_reg_rtx (SImode);
1591 parts[1] = gen_reg_rtx (SImode);
1592 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1593 parts[choice-1] = operands[1];
1594 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1595 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1596 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1597 count = (count & ~16) - 8;
1601 for (; count > 0; count--)
1602 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1603 for (; count < 0; count++)
1604 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1609 (define_insn "*rotlhi3_8"
1610 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1611 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1615 [(set_attr "type" "arith")])
1617 (define_expand "rotlhi3"
1618 [(set (match_operand:HI 0 "arith_reg_operand" "")
1619 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1620 (match_operand:HI 2 "immediate_operand" "")))]
1624 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1631 ;; This pattern is used by init_expmed for computing the costs of shift
1634 (define_insn_and_split "ashlsi3_std"
1635 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1636 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1637 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1638 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1640 || (GET_CODE (operands[2]) == CONST_INT
1641 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1648 && GET_CODE (operands[2]) == CONST_INT
1649 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1650 [(set (match_dup 3) (match_dup 2))
1652 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1653 (clobber (match_dup 4))])]
1654 "operands[4] = gen_rtx_SCRATCH (SImode);"
1655 [(set_attr "length" "*,*,*,4")
1656 (set_attr "type" "dyn_shift,arith,arith,arith")])
1658 (define_insn "ashlhi3_k"
1659 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1660 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1661 (match_operand:HI 2 "const_int_operand" "M,K")))]
1662 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1666 [(set_attr "type" "arith")])
1668 (define_insn "ashlsi3_n"
1669 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1670 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1671 (match_operand:SI 2 "const_int_operand" "n")))
1672 (clobber (reg:SI T_REG))]
1673 "! sh_dynamicalize_shift_p (operands[2])"
1675 [(set (attr "length")
1676 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1678 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1680 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1682 (const_string "8")))
1683 (set_attr "type" "arith")])
1686 [(set (match_operand:SI 0 "arith_reg_operand" "")
1687 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1688 (match_operand:SI 2 "const_int_operand" "n")))
1689 (clobber (reg:SI T_REG))]
1691 [(use (reg:SI R0_REG))]
1694 gen_shifty_op (ASHIFT, operands);
1698 (define_expand "ashlsi3"
1699 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1700 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1701 (match_operand:SI 2 "nonmemory_operand" "")))
1702 (clobber (reg:SI T_REG))])]
1706 if (GET_CODE (operands[2]) == CONST_INT
1707 && sh_dynamicalize_shift_p (operands[2]))
1708 operands[2] = force_reg (SImode, operands[2]);
1711 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1714 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1718 (define_insn "ashlhi3"
1719 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1720 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1721 (match_operand:HI 2 "const_int_operand" "n")))
1722 (clobber (reg:SI T_REG))]
1725 [(set (attr "length")
1726 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1728 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1730 (const_string "6")))
1731 (set_attr "type" "arith")])
1734 [(set (match_operand:HI 0 "arith_reg_operand" "")
1735 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1736 (match_operand:HI 2 "const_int_operand" "n")))
1737 (clobber (reg:SI T_REG))]
1739 [(use (reg:SI R0_REG))]
1742 gen_shifty_hi_op (ASHIFT, operands);
1747 ; arithmetic shift right
1750 (define_insn "ashrsi3_k"
1751 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1752 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1753 (match_operand:SI 2 "const_int_operand" "M")))
1754 (clobber (reg:SI T_REG))]
1755 "INTVAL (operands[2]) == 1"
1757 [(set_attr "type" "arith")])
1759 ;; We can't do HImode right shifts correctly unless we start out with an
1760 ;; explicit zero / sign extension; doing that would result in worse overall
1761 ;; code, so just let the machine independent code widen the mode.
1762 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1765 ;; ??? This should be a define expand.
1767 (define_insn "ashrsi2_16"
1768 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1769 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1773 [(set_attr "length" "4")])
1776 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1777 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1780 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1781 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1782 "operands[2] = gen_lowpart (HImode, operands[0]);")
1784 ;; ??? This should be a define expand.
1786 (define_insn "ashrsi2_31"
1787 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1788 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1790 (clobber (reg:SI T_REG))]
1793 [(set_attr "length" "4")])
1796 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1797 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1799 (clobber (reg:SI T_REG))]
1804 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1805 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1809 (define_insn "ashlsi_c"
1810 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1811 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1813 (lt:SI (match_dup 1) (const_int 0)))]
1816 [(set_attr "type" "arith")])
1818 (define_insn "ashrsi3_d"
1819 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1820 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1821 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1824 [(set_attr "type" "dyn_shift")])
1826 (define_insn "ashrsi3_n"
1827 [(set (reg:SI R4_REG)
1828 (ashiftrt:SI (reg:SI R4_REG)
1829 (match_operand:SI 0 "const_int_operand" "i")))
1830 (clobber (reg:SI T_REG))
1831 (clobber (reg:SI PR_REG))
1832 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1835 [(set_attr "type" "sfunc")
1836 (set_attr "needs_delay_slot" "yes")])
1838 (define_expand "ashrsi3"
1839 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1840 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1841 (match_operand:SI 2 "nonmemory_operand" "")))
1842 (clobber (reg:SI T_REG))])]
1844 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1846 ;; logical shift right
1848 (define_insn "lshrsi3_d"
1849 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1850 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1851 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1854 [(set_attr "type" "dyn_shift")])
1856 ;; Only the single bit shift clobbers the T bit.
1858 (define_insn "lshrsi3_m"
1859 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1860 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1861 (match_operand:SI 2 "const_int_operand" "M")))
1862 (clobber (reg:SI T_REG))]
1863 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1865 [(set_attr "type" "arith")])
1867 (define_insn "lshrsi3_k"
1868 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1869 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1870 (match_operand:SI 2 "const_int_operand" "K")))]
1871 "CONST_OK_FOR_K (INTVAL (operands[2]))
1872 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1874 [(set_attr "type" "arith")])
1876 (define_insn "lshrsi3_n"
1877 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1878 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1879 (match_operand:SI 2 "const_int_operand" "n")))
1880 (clobber (reg:SI T_REG))]
1881 "! sh_dynamicalize_shift_p (operands[2])"
1883 [(set (attr "length")
1884 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1886 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1888 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1890 (const_string "8")))
1891 (set_attr "type" "arith")])
1894 [(set (match_operand:SI 0 "arith_reg_operand" "")
1895 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1896 (match_operand:SI 2 "const_int_operand" "n")))
1897 (clobber (reg:SI T_REG))]
1899 [(use (reg:SI R0_REG))]
1902 gen_shifty_op (LSHIFTRT, operands);
1906 (define_expand "lshrsi3"
1907 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1908 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1909 (match_operand:SI 2 "nonmemory_operand" "")))
1910 (clobber (reg:SI T_REG))])]
1914 if (GET_CODE (operands[2]) == CONST_INT
1915 && sh_dynamicalize_shift_p (operands[2]))
1916 operands[2] = force_reg (SImode, operands[2]);
1917 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1919 rtx count = copy_to_mode_reg (SImode, operands[2]);
1920 emit_insn (gen_negsi2 (count, count));
1921 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1924 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1928 ;; ??? This should be a define expand.
1930 (define_insn "ashldi3_k"
1931 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1932 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1934 (clobber (reg:SI T_REG))]
1936 "shll %R0\;rotcl %S0"
1937 [(set_attr "length" "4")
1938 (set_attr "type" "arith")])
1940 (define_expand "ashldi3"
1941 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1942 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1943 (match_operand:DI 2 "immediate_operand" "")))
1944 (clobber (reg:SI T_REG))])]
1946 "{ if (GET_CODE (operands[2]) != CONST_INT
1947 || INTVAL (operands[2]) != 1) FAIL;} ")
1949 ;; ??? This should be a define expand.
1951 (define_insn "lshrdi3_k"
1952 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1953 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1955 (clobber (reg:SI T_REG))]
1957 "shlr %S0\;rotcr %R0"
1958 [(set_attr "length" "4")
1959 (set_attr "type" "arith")])
1961 (define_expand "lshrdi3"
1962 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1963 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1964 (match_operand:DI 2 "immediate_operand" "")))
1965 (clobber (reg:SI T_REG))])]
1967 "{ if (GET_CODE (operands[2]) != CONST_INT
1968 || INTVAL (operands[2]) != 1) FAIL;} ")
1970 ;; ??? This should be a define expand.
1972 (define_insn "ashrdi3_k"
1973 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1974 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1976 (clobber (reg:SI T_REG))]
1978 "shar %S0\;rotcr %R0"
1979 [(set_attr "length" "4")
1980 (set_attr "type" "arith")])
1982 (define_expand "ashrdi3"
1983 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1984 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1985 (match_operand:DI 2 "immediate_operand" "")))
1986 (clobber (reg:SI T_REG))])]
1988 "{ if (GET_CODE (operands[2]) != CONST_INT
1989 || INTVAL (operands[2]) != 1) FAIL; } ")
1991 ;; combined left/right shift
1994 [(set (match_operand:SI 0 "register_operand" "")
1995 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1996 (match_operand:SI 2 "const_int_operand" "n"))
1997 (match_operand:SI 3 "const_int_operand" "n")))]
1998 "(unsigned)INTVAL (operands[2]) < 32"
1999 [(use (reg:SI R0_REG))]
2000 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2004 [(set (match_operand:SI 0 "register_operand" "")
2005 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2006 (match_operand:SI 2 "const_int_operand" "n"))
2007 (match_operand:SI 3 "const_int_operand" "n")))
2008 (clobber (reg:SI T_REG))]
2009 "(unsigned)INTVAL (operands[2]) < 32"
2010 [(use (reg:SI R0_REG))]
2011 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2015 [(set (match_operand:SI 0 "register_operand" "=r")
2016 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2017 (match_operand:SI 2 "const_int_operand" "n"))
2018 (match_operand:SI 3 "const_int_operand" "n")))
2019 (clobber (reg:SI T_REG))]
2020 "shl_and_kind (operands[2], operands[3], 0) == 1"
2022 [(set (attr "length")
2023 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2025 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2027 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2029 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2031 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2033 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2035 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2036 (const_string "16")]
2037 (const_string "18")))
2038 (set_attr "type" "arith")])
2041 [(set (match_operand:SI 0 "register_operand" "=z")
2042 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2043 (match_operand:SI 2 "const_int_operand" "n"))
2044 (match_operand:SI 3 "const_int_operand" "n")))
2045 (clobber (reg:SI T_REG))]
2046 "shl_and_kind (operands[2], operands[3], 0) == 2"
2048 [(set (attr "length")
2049 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2051 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2053 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2055 (const_string "10")))
2056 (set_attr "type" "arith")])
2058 ;; shift left / and combination with a scratch register: The combine pass
2059 ;; does not accept the individual instructions, even though they are
2060 ;; cheap. But it needs a precise description so that it is usable after
2062 (define_insn "and_shl_scratch"
2063 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2067 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2068 (match_operand:SI 2 "const_int_operand" "N,n"))
2069 (match_operand:SI 3 "" "0,r"))
2070 (match_operand:SI 4 "const_int_operand" "n,n"))
2071 (match_operand:SI 5 "const_int_operand" "n,n")))
2072 (clobber (reg:SI T_REG))]
2075 [(set (attr "length")
2076 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2078 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2080 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2082 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2083 (const_string "10")]
2084 (const_string "12")))
2085 (set_attr "type" "arith")])
2088 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2092 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2093 (match_operand:SI 2 "const_int_operand" "N,n"))
2094 (match_operand:SI 3 "register_operand" "0,r"))
2095 (match_operand:SI 4 "const_int_operand" "n,n"))
2096 (match_operand:SI 5 "const_int_operand" "n,n")))
2097 (clobber (reg:SI T_REG))]
2099 [(use (reg:SI R0_REG))]
2102 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2104 if (INTVAL (operands[2]))
2106 gen_shifty_op (LSHIFTRT, operands);
2108 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2109 operands[2] = operands[4];
2110 gen_shifty_op (ASHIFT, operands);
2111 if (INTVAL (operands[5]))
2113 operands[2] = operands[5];
2114 gen_shifty_op (LSHIFTRT, operands);
2119 ;; signed left/right shift combination.
2121 [(set (match_operand:SI 0 "register_operand" "=r")
2123 (ashift:SI (match_operand:SI 1 "register_operand" "r")
2124 (match_operand:SI 2 "const_int_operand" "n"))
2125 (match_operand:SI 3 "const_int_operand" "n")
2127 (clobber (reg:SI T_REG))]
2129 [(use (reg:SI R0_REG))]
2130 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2133 (define_insn "shl_sext_ext"
2134 [(set (match_operand:SI 0 "register_operand" "=r")
2136 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2137 (match_operand:SI 2 "const_int_operand" "n"))
2138 (match_operand:SI 3 "const_int_operand" "n")
2140 (clobber (reg:SI T_REG))]
2141 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2143 [(set (attr "length")
2144 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2146 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2148 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2150 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2152 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2154 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2156 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2158 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2159 (const_string "16")]
2160 (const_string "18")))
2161 (set_attr "type" "arith")])
2163 (define_insn "shl_sext_sub"
2164 [(set (match_operand:SI 0 "register_operand" "=z")
2166 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2167 (match_operand:SI 2 "const_int_operand" "n"))
2168 (match_operand:SI 3 "const_int_operand" "n")
2170 (clobber (reg:SI T_REG))]
2171 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2173 [(set (attr "length")
2174 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2176 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2178 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2180 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2181 (const_string "12")]
2182 (const_string "14")))
2183 (set_attr "type" "arith")])
2185 ;; These patterns are found in expansions of DImode shifts by 16, and
2186 ;; allow the xtrct instruction to be generated from C source.
2188 (define_insn "xtrct_left"
2189 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2190 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2192 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2196 [(set_attr "type" "arith")])
2198 (define_insn "xtrct_right"
2199 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2200 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2202 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2206 [(set_attr "type" "arith")])
2208 ;; -------------------------------------------------------------------------
2210 ;; -------------------------------------------------------------------------
2213 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2214 (neg:SI (plus:SI (reg:SI T_REG)
2215 (match_operand:SI 1 "arith_reg_operand" "r"))))
2217 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2221 [(set_attr "type" "arith")])
2223 (define_expand "negdi2"
2224 [(set (match_operand:DI 0 "arith_reg_operand" "")
2225 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2226 (clobber (reg:SI T_REG))]
2230 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2231 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2233 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2234 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2236 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2237 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2239 emit_insn (gen_clrt ());
2240 emit_insn (gen_negc (low_dst, low_src));
2241 emit_insn (gen_negc (high_dst, high_src));
2245 (define_insn "negsi2"
2246 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2247 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2250 [(set_attr "type" "arith")])
2252 (define_insn "one_cmplsi2"
2253 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2254 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2257 [(set_attr "type" "arith")])
2259 ;; -------------------------------------------------------------------------
2260 ;; Zero extension instructions
2261 ;; -------------------------------------------------------------------------
2263 (define_insn "zero_extendhisi2"
2264 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2265 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2268 [(set_attr "type" "arith")])
2270 (define_insn "zero_extendqisi2"
2271 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2272 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2275 [(set_attr "type" "arith")])
2277 (define_insn "zero_extendqihi2"
2278 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2279 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2282 [(set_attr "type" "arith")])
2284 ;; -------------------------------------------------------------------------
2285 ;; Sign extension instructions
2286 ;; -------------------------------------------------------------------------
2288 ;; ??? This should be a define expand.
2289 ;; ??? Or perhaps it should be dropped?
2291 /* There is no point in defining extendsidi2; convert_move generates good
2294 (define_insn "extendhisi2"
2295 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2296 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2301 [(set_attr "type" "arith,load")])
2303 (define_insn "extendqisi2"
2304 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2305 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2310 [(set_attr "type" "arith,load")])
2312 (define_insn "extendqihi2"
2313 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2314 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2319 [(set_attr "type" "arith,load")])
2321 ;; -------------------------------------------------------------------------
2322 ;; Move instructions
2323 ;; -------------------------------------------------------------------------
2325 ;; define push and pop so it is easy for sh.c
2327 (define_expand "push"
2328 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2329 (match_operand:SI 0 "register_operand" "r,l,x"))]
2333 (define_expand "pop"
2334 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2335 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2339 (define_expand "push_e"
2340 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
2341 (match_operand:SF 0 "" ""))
2342 (use (reg:PSI FPSCR_REG))
2343 (clobber (scratch:SI))])]
2347 (define_insn "push_fpul"
2348 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
2351 [(set_attr "type" "store")
2352 (set_attr "hit_stack" "yes")])
2354 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2356 (define_expand "push_4"
2357 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
2358 (match_operand:DF 0 "" ""))
2359 (use (reg:PSI FPSCR_REG))
2360 (clobber (scratch:SI))])]
2364 (define_expand "pop_e"
2365 [(parallel [(set (match_operand:SF 0 "" "")
2366 (mem:SF (post_inc:SI (reg:SI SP_REG))))
2367 (use (reg:PSI FPSCR_REG))
2368 (clobber (scratch:SI))])]
2372 (define_insn "pop_fpul"
2373 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
2376 [(set_attr "type" "load")
2377 (set_attr "hit_stack" "yes")])
2379 (define_expand "pop_4"
2380 [(parallel [(set (match_operand:DF 0 "" "")
2381 (mem:DF (post_inc:SI (reg:SI SP_REG))))
2382 (use (reg:PSI FPSCR_REG))
2383 (clobber (scratch:SI))])]
2387 ;; These two patterns can happen as the result of optimization, when
2388 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2389 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2392 [(set (reg:SI T_REG) (const_int 0))]
2397 [(set (reg:SI T_REG) (const_int 1))]
2401 ;; t/r must come after r/r, lest reload will try to reload stuff like
2402 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
2403 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
2404 (define_insn "movsi_i"
2405 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r")
2406 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,i"))]
2409 && (register_operand (operands[0], SImode)
2410 || register_operand (operands[1], SImode))"
2425 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
2426 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
2428 ;; t/r must come after r/r, lest reload will try to reload stuff like
2429 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2430 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2431 ;; will require a reload.
2432 (define_insn "movsi_ie"
2433 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,y,r,y,r,y")
2434 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,>,i,r,y,y"))]
2436 && (register_operand (operands[0], SImode)
2437 || register_operand (operands[1], SImode))"
2455 ! move optimized away"
2456 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2457 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2459 (define_insn "movsi_i_lowpart"
2460 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,m,r"))
2461 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,xl,t,r,i"))]
2462 "register_operand (operands[0], SImode)
2463 || register_operand (operands[1], SImode)"
2472 [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
2474 (define_expand "movsi"
2475 [(set (match_operand:SI 0 "general_movdst_operand" "")
2476 (match_operand:SI 1 "general_movsrc_operand" ""))]
2478 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2480 (define_expand "ic_invalidate_line"
2481 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2482 (match_dup 1)] UNSPEC_ICACHE)
2483 (clobber (scratch:SI))])]
2487 operands[0] = force_reg (Pmode, operands[0]);
2488 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2491 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2492 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2493 ;; the requirement *1*00 for associative address writes. The alignment of
2494 ;; %0 implies that its least significant bit is cleared,
2495 ;; thus we clear the V bit of a matching entry if there is one.
2496 (define_insn "ic_invalidate_line_i"
2497 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2498 (match_operand:SI 1 "register_operand" "r")]
2500 (clobber (match_scratch:SI 2 "=&r"))]
2502 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2503 [(set_attr "length" "8")])
2505 (define_insn "movqi_i"
2506 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2507 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2508 "arith_reg_operand (operands[0], QImode)
2509 || arith_reg_operand (operands[1], QImode)"
2517 [(set_attr "type" "move,load,store,move,move,move")])
2519 (define_expand "movqi"
2520 [(set (match_operand:QI 0 "general_operand" "")
2521 (match_operand:QI 1 "general_operand" ""))]
2523 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2525 (define_insn "movhi_i"
2526 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2527 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2528 "arith_reg_operand (operands[0], HImode)
2529 || arith_reg_operand (operands[1], HImode)"
2539 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2541 (define_expand "movhi"
2542 [(set (match_operand:HI 0 "general_movdst_operand" "")
2543 (match_operand:HI 1 "general_movsrc_operand" ""))]
2545 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2547 ;; ??? This should be a define expand.
2549 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2550 ;; compiled with -m2 -ml -O3 -funroll-loops
2552 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2553 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2554 "arith_reg_operand (operands[0], DImode)
2555 || arith_reg_operand (operands[1], DImode)"
2556 "* return output_movedouble (insn, operands, DImode);"
2557 [(set_attr "length" "4")
2558 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2560 ;; If the output is a register and the input is memory or a register, we have
2561 ;; to be careful and see which word needs to be loaded first.
2564 [(set (match_operand:DI 0 "general_movdst_operand" "")
2565 (match_operand:DI 1 "general_movsrc_operand" ""))]
2567 [(set (match_dup 2) (match_dup 3))
2568 (set (match_dup 4) (match_dup 5))]
2573 if ((GET_CODE (operands[0]) == MEM
2574 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2575 || (GET_CODE (operands[1]) == MEM
2576 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2579 if (GET_CODE (operands[0]) == REG)
2580 regno = REGNO (operands[0]);
2581 else if (GET_CODE (operands[0]) == SUBREG)
2582 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2583 else if (GET_CODE (operands[0]) == MEM)
2587 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2589 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2590 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2591 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2592 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2596 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2597 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2598 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2599 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2602 if (operands[2] == 0 || operands[3] == 0
2603 || operands[4] == 0 || operands[5] == 0)
2607 (define_expand "movdi"
2608 [(set (match_operand:DI 0 "general_movdst_operand" "")
2609 (match_operand:DI 1 "general_movsrc_operand" ""))]
2611 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2613 ;; ??? This should be a define expand.
2615 (define_insn "movdf_k"
2616 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2617 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2618 "(! TARGET_SH4 || reload_completed
2619 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2620 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2621 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2622 && (arith_reg_operand (operands[0], DFmode)
2623 || arith_reg_operand (operands[1], DFmode))"
2624 "* return output_movedouble (insn, operands, DFmode);"
2625 [(set_attr "length" "4")
2626 (set_attr "type" "move,pcload,load,store")])
2628 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2629 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2630 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2631 ;; the d/m/c/X alternative, which is split later into single-precision
2632 ;; instructions. And when not optimizing, no splits are done before fixing
2633 ;; up pcloads, so we need usable length information for that.
2634 (define_insn "movdf_i4"
2635 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2636 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2637 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2638 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2640 && (arith_reg_operand (operands[0], DFmode)
2641 || arith_reg_operand (operands[1], DFmode))"
2653 [(set_attr_alternative "length"
2654 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2656 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2657 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2658 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2660 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2661 (const_int 8) (const_int 8)])
2662 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2663 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2664 (const_string "double")
2665 (const_string "none")))])
2667 ;; Moving DFmode between fp/general registers through memory
2668 ;; (the top of the stack) is faster than moving through fpul even for
2669 ;; little endian. Because the type of an instruction is important for its
2670 ;; scheduling, it is beneficial to split these operations, rather than
2671 ;; emitting them in one single chunk, even if this will expose a stack
2672 ;; use that will prevent scheduling of other stack accesses beyond this
2675 [(set (match_operand:DF 0 "register_operand" "")
2676 (match_operand:DF 1 "register_operand" ""))
2677 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2678 (clobber (match_scratch:SI 3 "=X"))]
2679 "TARGET_SH4 && reload_completed
2680 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2686 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2687 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2688 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2689 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2690 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2691 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2695 ;; local-alloc sometimes allocates scratch registers even when not required,
2696 ;; so we must be prepared to handle these.
2698 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2700 [(set (match_operand:DF 0 "general_movdst_operand" "")
2701 (match_operand:DF 1 "general_movsrc_operand" ""))
2702 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2703 (clobber (match_scratch:SI 3 "X"))]
2706 && true_regnum (operands[0]) < 16
2707 && true_regnum (operands[1]) < 16"
2708 [(set (match_dup 0) (match_dup 1))]
2711 /* If this was a reg <-> mem operation with base + index reg addressing,
2712 we have to handle this in a special way. */
2713 rtx mem = operands[0];
2715 if (! memory_operand (mem, DFmode))
2720 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2721 mem = SUBREG_REG (mem);
2722 if (GET_CODE (mem) == MEM)
2724 rtx addr = XEXP (mem, 0);
2725 if (GET_CODE (addr) == PLUS
2726 && GET_CODE (XEXP (addr, 0)) == REG
2727 && GET_CODE (XEXP (addr, 1)) == REG)
2730 rtx reg0 = gen_rtx (REG, Pmode, 0);
2731 rtx regop = operands[store_p], word0 ,word1;
2733 if (GET_CODE (regop) == SUBREG)
2734 regop = alter_subreg (regop);
2735 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2739 mem = copy_rtx (mem);
2740 PUT_MODE (mem, SImode);
2741 word0 = gen_rtx(SUBREG, SImode, regop, 0);
2743 ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
2744 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2745 mem = copy_rtx (mem);
2746 word1 = gen_rtx(SUBREG, SImode, regop, 1);
2748 ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
2749 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2755 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2757 [(set (match_operand:DF 0 "register_operand" "")
2758 (match_operand:DF 1 "memory_operand" ""))
2759 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2760 (clobber (reg:SI R0_REG))]
2761 "TARGET_SH4 && reload_completed"
2762 [(parallel [(set (match_dup 0) (match_dup 1))
2764 (clobber (scratch:SI))])]
2767 (define_expand "reload_indf"
2768 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2769 (match_operand:DF 1 "immediate_operand" "FQ"))
2770 (use (reg:PSI FPSCR_REG))
2771 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2775 (define_expand "reload_outdf"
2776 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2777 (match_operand:DF 1 "register_operand" "af,r"))
2778 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2782 ;; Simplify no-op moves.
2784 [(set (match_operand:SF 0 "register_operand" "")
2785 (match_operand:SF 1 "register_operand" ""))
2786 (use (match_operand:PSI 2 "fpscr_operand" ""))
2787 (clobber (match_scratch:SI 3 "X"))]
2788 "TARGET_SH3E && reload_completed
2789 && true_regnum (operands[0]) == true_regnum (operands[1])"
2790 [(set (match_dup 0) (match_dup 0))]
2793 ;; fmovd substitute post-reload splits
2795 [(set (match_operand:DF 0 "register_operand" "")
2796 (match_operand:DF 1 "register_operand" ""))
2797 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2798 (clobber (match_scratch:SI 3 "X"))]
2799 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2800 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2801 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2805 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2806 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2807 gen_rtx (REG, SFmode, src), operands[2]));
2808 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2809 gen_rtx (REG, SFmode, src + 1), operands[2]));
2814 [(set (match_operand:DF 0 "register_operand" "")
2815 (mem:DF (match_operand:SI 1 "register_operand" "")))
2816 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2817 (clobber (match_scratch:SI 3 "X"))]
2818 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2819 && FP_OR_XD_REGISTER_P (operands[0])
2820 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2824 int regno = true_regnum (operands[0]);
2826 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2828 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2829 regno + !! TARGET_LITTLE_ENDIAN),
2830 mem2, operands[2]));
2831 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2832 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2833 regno + ! TARGET_LITTLE_ENDIAN),
2834 gen_rtx (MEM, SFmode, operands[1]),
2840 [(set (match_operand:DF 0 "register_operand" "")
2841 (match_operand:DF 1 "memory_operand" ""))
2842 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2843 (clobber (match_scratch:SI 3 "X"))]
2844 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2845 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
2849 int regno = true_regnum (operands[0]);
2850 rtx addr, insn, adjust = NULL_RTX;
2851 rtx mem2 = copy_rtx (operands[1]);
2852 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2853 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2855 PUT_MODE (mem2, SFmode);
2856 operands[1] = copy_rtx (mem2);
2857 addr = XEXP (mem2, 0);
2858 if (GET_CODE (addr) != POST_INC)
2860 /* If we have to modify the stack pointer, the value that we have
2861 read with post-increment might be modified by an interrupt,
2862 so write it back. */
2863 if (REGNO (addr) == STACK_POINTER_REGNUM)
2864 adjust = gen_push_e (reg0);
2866 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2867 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2869 addr = XEXP (addr, 0);
2870 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2871 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2872 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2876 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2881 [(set (match_operand:DF 0 "memory_operand" "")
2882 (match_operand:DF 1 "register_operand" ""))
2883 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2884 (clobber (match_scratch:SI 3 "X"))]
2885 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2886 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2890 int regno = true_regnum (operands[1]);
2891 rtx insn, addr, adjust = NULL_RTX;
2893 operands[0] = copy_rtx (operands[0]);
2894 PUT_MODE (operands[0], SFmode);
2895 insn = emit_insn (gen_movsf_ie (operands[0],
2896 gen_rtx (REG, SFmode,
2897 regno + ! TARGET_LITTLE_ENDIAN),
2899 operands[0] = copy_rtx (operands[0]);
2900 addr = XEXP (operands[0], 0);
2901 if (GET_CODE (addr) != PRE_DEC)
2903 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2904 emit_insn_before (adjust, insn);
2905 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2907 addr = XEXP (addr, 0);
2909 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2910 insn = emit_insn (gen_movsf_ie (operands[0],
2911 gen_rtx (REG, SFmode,
2912 regno + !! TARGET_LITTLE_ENDIAN),
2914 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2918 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2920 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2921 ;; to avoid a bogus tertiary reload.
2922 ;; We need a tertiary reload when a floating point register is reloaded
2923 ;; to memory, so the predicate for operand 0 must accept this, while the
2924 ;; constraint of operand 1 must reject the secondary reload register.
2925 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2927 ;; By having the predicate for operand 0 reject any register, we make
2928 ;; sure that the ordinary moves that just need an intermediate register
2929 ;; won't get a bogus tertiary reload.
2930 ;; We use tertiary_reload_operand instead of memory_operand here because
2931 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2932 ;; (mem:SF (plus:SI (reg:SI FP_REG)
2933 ;; (const_int 132)))
2935 (define_expand "reload_outsf"
2936 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2937 (match_operand:SF 1 "register_operand" "y"))
2938 (clobber (scratch:SI))])
2939 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2941 (clobber (scratch:SI))])]
2945 ;; If the output is a register and the input is memory or a register, we have
2946 ;; to be careful and see which word needs to be loaded first.
2949 [(set (match_operand:DF 0 "general_movdst_operand" "")
2950 (match_operand:DF 1 "general_movsrc_operand" ""))]
2952 [(set (match_dup 2) (match_dup 3))
2953 (set (match_dup 4) (match_dup 5))]
2958 if ((GET_CODE (operands[0]) == MEM
2959 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2960 || (GET_CODE (operands[1]) == MEM
2961 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2964 if (GET_CODE (operands[0]) == REG)
2965 regno = REGNO (operands[0]);
2966 else if (GET_CODE (operands[0]) == SUBREG)
2967 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2968 else if (GET_CODE (operands[0]) == MEM)
2972 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2974 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2975 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2976 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2977 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2981 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2982 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2983 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2984 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2987 if (operands[2] == 0 || operands[3] == 0
2988 || operands[4] == 0 || operands[5] == 0)
2992 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2993 ;; used only once, let combine add in the index again.
2996 [(set (match_operand:SI 0 "register_operand" "")
2997 (match_operand:SI 1 "" ""))
2998 (clobber (match_operand 2 "register_operand" ""))]
2999 "! reload_in_progress && ! reload_completed"
3000 [(use (reg:SI R0_REG))]
3003 rtx addr, reg, const_int;
3005 if (GET_CODE (operands[1]) != MEM)
3007 addr = XEXP (operands[1], 0);
3008 if (GET_CODE (addr) != PLUS)
3010 reg = XEXP (addr, 0);
3011 const_int = XEXP (addr, 1);
3012 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3013 && GET_CODE (const_int) == CONST_INT))
3015 emit_move_insn (operands[2], const_int);
3016 emit_move_insn (operands[0],
3017 change_address (operands[1], VOIDmode,
3018 gen_rtx_PLUS (SImode, reg, operands[2])));
3023 [(set (match_operand:SI 1 "" "")
3024 (match_operand:SI 0 "register_operand" ""))
3025 (clobber (match_operand 2 "register_operand" ""))]
3026 "! reload_in_progress && ! reload_completed"
3027 [(use (reg:SI R0_REG))]
3030 rtx addr, reg, const_int;
3032 if (GET_CODE (operands[1]) != MEM)
3034 addr = XEXP (operands[1], 0);
3035 if (GET_CODE (addr) != PLUS)
3037 reg = XEXP (addr, 0);
3038 const_int = XEXP (addr, 1);
3039 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3040 && GET_CODE (const_int) == CONST_INT))
3042 emit_move_insn (operands[2], const_int);
3043 emit_move_insn (change_address (operands[1], VOIDmode,
3044 gen_rtx_PLUS (SImode, reg, operands[2])),
3049 (define_expand "movdf"
3050 [(set (match_operand:DF 0 "general_movdst_operand" "")
3051 (match_operand:DF 1 "general_movsrc_operand" ""))]
3055 if (prepare_move_operands (operands, DFmode)) DONE;
3058 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
3064 (define_insn "movsf_i"
3065 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
3066 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
3069 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
3070 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
3071 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
3072 && (arith_reg_operand (operands[0], SFmode)
3073 || arith_reg_operand (operands[1], SFmode))"
3082 [(set_attr "type" "move,move,pcload,load,store,move,move")])
3084 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
3085 ;; update_flow_info would not know where to put REG_EQUAL notes
3086 ;; when the destination changes mode.
3087 (define_insn "movsf_ie"
3088 [(set (match_operand:SF 0 "general_movdst_operand"
3089 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
3090 (match_operand:SF 1 "general_movsrc_operand"
3091 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
3092 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3093 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
3096 && (arith_reg_operand (operands[0], SFmode)
3097 || arith_reg_operand (operands[1], SFmode))"
3115 ! move optimized away"
3116 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
3117 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")
3118 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3119 (const_string "single")
3120 (const_string "none")))])
3122 [(set (match_operand:SF 0 "register_operand" "")
3123 (match_operand:SF 1 "register_operand" ""))
3124 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3125 (clobber (reg:SI FPUL_REG))]
3127 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
3129 (clobber (scratch:SI))])
3130 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
3132 (clobber (scratch:SI))])]
3135 (define_expand "movsf"
3136 [(set (match_operand:SF 0 "general_movdst_operand" "")
3137 (match_operand:SF 1 "general_movsrc_operand" ""))]
3141 if (prepare_move_operands (operands, SFmode))
3145 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3150 (define_insn "mov_nop"
3151 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3154 [(set_attr "length" "0")
3155 (set_attr "type" "nil")])
3157 (define_expand "reload_insf"
3158 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
3159 (match_operand:SF 1 "immediate_operand" "FQ"))
3160 (use (reg:PSI FPSCR_REG))
3161 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3165 (define_expand "reload_insi"
3166 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3167 (match_operand:SF 1 "immediate_operand" "FQ"))
3168 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3172 (define_insn "*movsi_y"
3173 [(set (match_operand:SI 0 "register_operand" "=y,y")
3174 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3175 (clobber (match_scratch:SI 3 "=&z,r"))]
3177 && (reload_in_progress || reload_completed)"
3179 [(set_attr "length" "4")
3180 (set_attr "type" "pcload,move")])
3183 [(set (match_operand:SI 0 "register_operand" "")
3184 (match_operand:SI 1 "immediate_operand" ""))
3185 (clobber (match_operand:SI 2 "register_operand" ""))]
3187 [(set (match_dup 2) (match_dup 1))
3188 (set (match_dup 0) (match_dup 2))]
3192 [(set (match_operand:SI 0 "register_operand" "")
3193 (match_operand:SI 1 "memory_operand" ""))
3194 (clobber (reg:SI R0_REG))]
3196 [(set (match_dup 0) (match_dup 1))]
3199 ;; ------------------------------------------------------------------------
3200 ;; Define the real conditional branch instructions.
3201 ;; ------------------------------------------------------------------------
3203 (define_insn "branch_true"
3204 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
3205 (label_ref (match_operand 0 "" ""))
3208 "* return output_branch (1, insn, operands);"
3209 [(set_attr "type" "cbranch")])
3211 (define_insn "branch_false"
3212 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
3213 (label_ref (match_operand 0 "" ""))
3216 "* return output_branch (0, insn, operands);"
3217 [(set_attr "type" "cbranch")])
3219 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3220 ;; which destination is too far away.
3221 ;; The const_int_operand is distinct for each branch target; it avoids
3222 ;; unwanted matches with redundant_insn.
3223 (define_insn "block_branch_redirect"
3224 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
3227 [(set_attr "length" "0")])
3229 ;; This one has the additional purpose to record a possible scratch register
3230 ;; for the following branch.
3231 (define_insn "indirect_jump_scratch"
3232 [(set (match_operand 0 "register_operand" "=r")
3233 (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
3236 [(set_attr "length" "0")])
3238 ;; Conditional branch insns
3240 (define_expand "beq"
3242 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3243 (label_ref (match_operand 0 "" ""))
3246 "from_compare (operands, EQ);")
3248 (define_expand "bne"
3250 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3251 (label_ref (match_operand 0 "" ""))
3254 "from_compare (operands, EQ);")
3256 (define_expand "bgt"
3258 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3259 (label_ref (match_operand 0 "" ""))
3262 "from_compare (operands, GT);")
3264 (define_expand "blt"
3266 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3267 (label_ref (match_operand 0 "" ""))
3272 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3274 rtx tmp = sh_compare_op0;
3275 sh_compare_op0 = sh_compare_op1;
3276 sh_compare_op1 = tmp;
3277 emit_insn (gen_bgt (operands[0]));
3280 from_compare (operands, GE);
3283 (define_expand "ble"
3285 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3286 (label_ref (match_operand 0 "" ""))
3293 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3295 rtx tmp = sh_compare_op0;
3296 sh_compare_op0 = sh_compare_op1;
3297 sh_compare_op1 = tmp;
3298 emit_insn (gen_bge (operands[0]));
3301 from_compare (operands, GT);
3304 (define_expand "bge"
3306 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3307 (label_ref (match_operand 0 "" ""))
3314 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3316 rtx tmp = sh_compare_op0;
3317 sh_compare_op0 = sh_compare_op1;
3318 sh_compare_op1 = tmp;
3319 emit_insn (gen_ble (operands[0]));
3322 from_compare (operands, GE);
3325 (define_expand "bgtu"
3327 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3328 (label_ref (match_operand 0 "" ""))
3331 "from_compare (operands, GTU); ")
3333 (define_expand "bltu"
3335 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3336 (label_ref (match_operand 0 "" ""))
3339 "from_compare (operands, GEU);")
3341 (define_expand "bgeu"
3343 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3344 (label_ref (match_operand 0 "" ""))
3347 "from_compare (operands, GEU);")
3349 (define_expand "bleu"
3351 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3352 (label_ref (match_operand 0 "" ""))
3355 "from_compare (operands, GTU);")
3357 ;; ------------------------------------------------------------------------
3358 ;; Jump and linkage insns
3359 ;; ------------------------------------------------------------------------
3363 (label_ref (match_operand 0 "" "")))]
3367 /* The length is 16 if the delay slot is unfilled. */
3368 if (get_attr_length(insn) > 4)
3369 return output_far_jump(insn, operands[0]);
3371 return \"bra %l0%#\";
3373 [(set_attr "type" "jump")
3374 (set_attr "needs_delay_slot" "yes")])
3376 (define_insn "calli"
3377 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3378 (match_operand 1 "" ""))
3379 (use (reg:PSI FPSCR_REG))
3380 (clobber (reg:SI PR_REG))]
3383 [(set_attr "type" "call")
3384 (set (attr "fp_mode")
3385 (if_then_else (eq_attr "fpu_single" "yes")
3386 (const_string "single") (const_string "double")))
3387 (set_attr "needs_delay_slot" "yes")])
3389 ;; This is a pc-rel call, using bsrf, for use with PIC.
3391 (define_insn "calli_pcrel"
3392 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3393 (match_operand 1 "" ""))
3394 (use (reg:PSI FPSCR_REG))
3395 (use (reg:SI PIC_REG))
3396 (use (match_operand 2 "" ""))
3397 (clobber (reg:SI PR_REG))]
3400 [(set_attr "type" "call")
3401 (set (attr "fp_mode")
3402 (if_then_else (eq_attr "fpu_single" "yes")
3403 (const_string "single") (const_string "double")))
3404 (set_attr "needs_delay_slot" "yes")])
3406 (define_insn_and_split "call_pcrel"
3407 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3408 (match_operand 1 "" ""))
3409 (use (reg:PSI FPSCR_REG))
3410 (use (reg:SI PIC_REG))
3411 (clobber (reg:SI PR_REG))
3412 (clobber (match_scratch:SI 2 "=r"))]
3413 "TARGET_SH2 && optimize"
3419 rtx lab = gen_call_site ();
3421 if (SYMBOL_REF_FLAG (operands[0]))
3422 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3424 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
3425 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
3428 [(set_attr "type" "call")
3429 (set (attr "fp_mode")
3430 (if_then_else (eq_attr "fpu_single" "yes")
3431 (const_string "single") (const_string "double")))
3432 (set_attr "needs_delay_slot" "yes")])
3434 (define_insn "call_valuei"
3435 [(set (match_operand 0 "" "=rf")
3436 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3437 (match_operand 2 "" "")))
3438 (use (reg:PSI FPSCR_REG))
3439 (clobber (reg:SI PR_REG))]
3442 [(set_attr "type" "call")
3443 (set (attr "fp_mode")
3444 (if_then_else (eq_attr "fpu_single" "yes")
3445 (const_string "single") (const_string "double")))
3446 (set_attr "needs_delay_slot" "yes")])
3448 (define_insn "call_valuei_pcrel"
3449 [(set (match_operand 0 "" "=rf")
3450 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3451 (match_operand 2 "" "")))
3452 (use (reg:PSI FPSCR_REG))
3453 (use (reg:SI PIC_REG))
3454 (use (match_operand 3 "" ""))
3455 (clobber (reg:SI PR_REG))]
3458 [(set_attr "type" "call")
3459 (set (attr "fp_mode")
3460 (if_then_else (eq_attr "fpu_single" "yes")
3461 (const_string "single") (const_string "double")))
3462 (set_attr "needs_delay_slot" "yes")])
3464 (define_insn_and_split "call_value_pcrel"
3465 [(set (match_operand 0 "" "=rf")
3466 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
3467 (match_operand 2 "" "")))
3468 (use (reg:PSI FPSCR_REG))
3469 (use (reg:SI PIC_REG))
3470 (clobber (reg:SI PR_REG))
3471 (clobber (match_scratch:SI 3 "=r"))]
3472 "TARGET_SH2 && optimize"
3478 rtx lab = gen_call_site ();
3480 if (SYMBOL_REF_FLAG (operands[1]))
3481 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
3483 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
3484 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
3488 [(set_attr "type" "call")
3489 (set (attr "fp_mode")
3490 (if_then_else (eq_attr "fpu_single" "yes")
3491 (const_string "single") (const_string "double")))
3492 (set_attr "needs_delay_slot" "yes")])
3494 (define_expand "call"
3495 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3496 (match_operand 1 "" ""))
3497 (use (reg:PSI FPSCR_REG))
3498 (clobber (reg:SI PR_REG))])]
3502 if (flag_pic && TARGET_SH2 && optimize
3503 && GET_CODE (operands[0]) == MEM
3504 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3506 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
3510 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3513 (define_expand "call_value"
3514 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3515 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3516 (match_operand 2 "" "")))
3517 (use (reg:PSI FPSCR_REG))
3518 (clobber (reg:SI PR_REG))])]
3522 if (flag_pic && TARGET_SH2 && optimize
3523 && GET_CODE (operands[1]) == MEM
3524 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3526 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
3531 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
3534 (define_insn "sibcalli"
3535 ;; FIXME: any call-clobbered register will do
3536 [(call (mem:SI (match_operand:SI 0 "register_operand" "z"))
3537 (match_operand 1 "" ""))
3538 (use (reg:PSI FPSCR_REG))
3542 [(set_attr "needs_delay_slot" "yes")
3543 (set_attr "type" "jump_ind")])
3545 (define_insn "sibcalli_pcrel"
3546 ;; FIXME: any call-clobbered register will do
3547 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "z"))
3548 (match_operand 1 "" ""))
3549 (use (match_operand 2 "" ""))
3550 (use (reg:PSI FPSCR_REG))
3554 [(set_attr "needs_delay_slot" "yes")
3555 (set_attr "type" "jump_ind")])
3557 (define_insn_and_split "sibcall_pcrel"
3558 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3559 (match_operand 1 "" ""))
3560 (use (reg:PSI FPSCR_REG))
3561 ;; FIXME: any call-clobbered register will do
3562 (clobber (match_scratch:SI 2 "=z"))
3564 "TARGET_SH2 && optimize"
3570 rtx lab = gen_call_site ();
3573 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3574 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
3576 SIBLING_CALL_P (call_insn) = 1;
3580 (define_expand "sibcall"
3582 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3583 (match_operand 1 "" ""))
3584 (use (reg:PSI FPSCR_REG))
3589 if (flag_pic && TARGET_SH2 && optimize
3590 && GET_CODE (operands[0]) == MEM
3591 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3592 /* The PLT needs the PIC register, but the epilogue would have
3593 to restore it, so we can only use PC-relative PIC calls for
3594 static functions. */
3595 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3597 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
3601 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3604 (define_expand "sibcall_value"
3605 [(set (match_operand 0 "" "")
3606 (call (match_operand 1 "" "")
3607 (match_operand 2 "" "")))]
3611 emit_call_insn (gen_sibcall (operands[1], operands[2]));
3615 (define_expand "sibcall_epilogue"
3620 sh_expand_epilogue ();
3624 (define_insn "indirect_jump"
3626 (match_operand:SI 0 "arith_reg_operand" "r"))]
3629 [(set_attr "needs_delay_slot" "yes")
3630 (set_attr "type" "jump_ind")])
3632 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3633 ;; which can be present in structured code from indirect jumps which can not
3634 ;; be present in structured code. This allows -fprofile-arcs to work.
3636 ;; For SH1 processors.
3637 (define_insn "casesi_jump_1"
3639 (match_operand:SI 0 "register_operand" "r"))
3640 (use (label_ref (match_operand 1 "" "")))]
3643 [(set_attr "needs_delay_slot" "yes")
3644 (set_attr "type" "jump_ind")])
3646 ;; For all later processors.
3647 (define_insn "casesi_jump_2"
3648 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3649 (label_ref (match_operand 1 "" ""))))
3650 (use (label_ref (match_operand 2 "" "")))]
3651 "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
3653 [(set_attr "needs_delay_slot" "yes")
3654 (set_attr "type" "jump_ind")])
3656 ;; Call subroutine returning any type.
3657 ;; ??? This probably doesn't work.
3659 (define_expand "untyped_call"
3660 [(parallel [(call (match_operand 0 "" "")
3662 (match_operand 1 "" "")
3663 (match_operand 2 "" "")])]
3669 emit_call_insn (gen_call (operands[0], const0_rtx));
3671 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3673 rtx set = XVECEXP (operands[2], 0, i);
3674 emit_move_insn (SET_DEST (set), SET_SRC (set));
3677 /* The optimizer does not know that the call sets the function value
3678 registers we stored in the result block. We avoid problems by
3679 claiming that all hard registers are used and clobbered at this
3681 emit_insn (gen_blockage ());
3686 ;; ------------------------------------------------------------------------
3688 ;; ------------------------------------------------------------------------
3691 [(set (reg:SI T_REG)
3692 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3693 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3696 [(set_attr "type" "arith")])
3703 ;; Load address of a label. This is only generated by the casesi expand,
3704 ;; and by machine_dependent_reorg (fixing up fp moves).
3705 ;; This must use unspec, because this only works for labels that are
3709 [(set (reg:SI R0_REG)
3710 (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
3713 [(set_attr "in_delay_slot" "no")
3714 (set_attr "type" "arith")])
3716 ;; machine_dependent_reorg() will make this a `mova'.
3717 (define_insn "mova_const"
3718 [(set (reg:SI R0_REG)
3719 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
3722 [(set_attr "in_delay_slot" "no")
3723 (set_attr "type" "arith")])
3725 (define_expand "GOTaddr2picreg"
3726 [(set (reg:SI R0_REG)
3727 (unspec [(const (unspec [(match_dup 1)] UNSPEC_PIC))]
3729 (set (match_dup 0) (const (unspec [(match_dup 1)] UNSPEC_PIC)))
3730 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3733 operands[0] = pic_offset_table_rtx;
3734 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3738 (define_expand "call_site"
3739 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
3743 static HOST_WIDE_INT i = 0;
3744 operands[0] = GEN_INT (i);
3748 (define_expand "sym_label2reg"
3749 [(set (match_operand:SI 0 "" "")
3751 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_PIC))
3753 (match_operand:SI 2 "" "")
3757 (define_expand "symGOT2reg"
3758 [(set (match_operand:SI 0 "" "")
3759 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOT)))
3760 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3761 (set (match_dup 0) (mem:SI (match_dup 0)))]
3765 operands[2] = pic_offset_table_rtx;
3768 (define_expand "symGOTOFF2reg"
3769 [(set (match_operand:SI 0 "" "")
3770 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
3771 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3775 operands[2] = pic_offset_table_rtx;
3778 (define_expand "symPLT_label2reg"
3779 [(set (match_operand:SI 0 "" "")
3782 (unspec [(match_operand:SI 1 "" "")] UNSPEC_PLT)
3785 (match_operand:SI 2 "" "")
3787 ;; Even though the PIC register is not really used by the call
3788 ;; sequence in which this is expanded, the PLT code assumes the PIC
3789 ;; register is set, so we must not skip its initialization. Since
3790 ;; we only use this expand as part of calling sequences, and never
3791 ;; to take the address of a function, this is the best point to
3792 ;; insert the (use). Using the PLT to take the address of a
3793 ;; function would be wrong, not only because the PLT entry could
3794 ;; then be called from a function that doesn't initialize the PIC
3795 ;; register to the proper GOT, but also because pointers to the
3796 ;; same function might not compare equal, should they be set by
3797 ;; different shared libraries.
3798 (use (reg:SI PIC_REG))]
3802 ;; case instruction for switch statements.
3804 ;; Operand 0 is index
3805 ;; operand 1 is the minimum bound
3806 ;; operand 2 is the maximum bound - minimum bound + 1
3807 ;; operand 3 is CODE_LABEL for the table;
3808 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3810 (define_expand "casesi"
3811 [(match_operand:SI 0 "arith_reg_operand" "")
3812 (match_operand:SI 1 "arith_reg_operand" "")
3813 (match_operand:SI 2 "arith_reg_operand" "")
3814 (match_operand 3 "" "") (match_operand 4 "" "")]
3818 rtx reg = gen_reg_rtx (SImode);
3819 rtx reg2 = gen_reg_rtx (SImode);
3820 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3821 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3822 /* If optimizing, casesi_worker depends on the mode of the instruction
3823 before label it 'uses' - operands[3]. */
3824 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3826 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3828 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3830 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3831 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3832 operands[3], but to lab. We will fix this up in
3833 machine_dependent_reorg. */
3838 (define_expand "casesi_0"
3839 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3840 (set (match_dup 4) (minus:SI (match_dup 4)
3841 (match_operand:SI 1 "arith_operand" "")))
3843 (gtu:SI (match_dup 4)
3844 (match_operand:SI 2 "arith_reg_operand" "")))
3846 (if_then_else (ne (reg:SI T_REG)
3848 (label_ref (match_operand 3 "" ""))
3853 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3854 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3855 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3857 (define_insn "casesi_worker_0"
3858 [(set (match_operand:SI 0 "register_operand" "=r,r")
3859 (unspec [(match_operand 1 "register_operand" "0,r")
3860 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3861 (clobber (match_scratch:SI 3 "=X,1"))
3862 (clobber (match_scratch:SI 4 "=&z,z"))]
3867 [(set (match_operand:SI 0 "register_operand" "")
3868 (unspec [(match_operand 1 "register_operand" "")
3869 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3870 (clobber (match_scratch:SI 3 ""))
3871 (clobber (match_scratch:SI 4 ""))]
3872 "! TARGET_SH2 && reload_completed"
3873 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3874 (parallel [(set (match_dup 0)
3875 (unspec [(reg:SI R0_REG) (match_dup 1)
3876 (label_ref (match_dup 2))] UNSPEC_CASESI))
3877 (clobber (match_dup 3))])
3878 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3879 "LABEL_NUSES (operands[2])++;")
3882 [(set (match_operand:SI 0 "register_operand" "")
3883 (unspec [(match_operand 1 "register_operand" "")
3884 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3885 (clobber (match_scratch:SI 3 ""))
3886 (clobber (match_scratch:SI 4 ""))]
3887 "TARGET_SH2 && reload_completed"
3888 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3889 (parallel [(set (match_dup 0)
3890 (unspec [(reg:SI R0_REG) (match_dup 1)
3891 (label_ref (match_dup 2))] UNSPEC_CASESI))
3892 (clobber (match_dup 3))])]
3893 "LABEL_NUSES (operands[2])++;")
3895 (define_insn "*casesi_worker"
3896 [(set (match_operand:SI 0 "register_operand" "=r,r")
3897 (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
3898 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3899 (clobber (match_scratch:SI 3 "=X,1"))]
3903 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3905 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3908 switch (GET_MODE (diff_vec))
3911 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3913 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3915 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3916 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3917 return \"mov.b @(r0,%1),%0\";
3922 [(set_attr "length" "4")])
3924 (define_expand "return"
3926 "reload_completed && ! sh_need_epilogue ()"
3929 (define_insn "*return_i"
3933 [(set_attr "type" "return")
3934 (set_attr "needs_delay_slot" "yes")])
3936 (define_expand "prologue"
3939 "sh_expand_prologue (); DONE;")
3941 (define_expand "epilogue"
3944 "sh_expand_epilogue ();")
3946 (define_insn "blockage"
3947 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3950 [(set_attr "length" "0")])
3952 ;; ------------------------------------------------------------------------
3954 ;; ------------------------------------------------------------------------
3957 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3958 (eq:SI (reg:SI T_REG) (const_int 1)))]
3961 [(set_attr "type" "arith")])
3963 (define_expand "seq"
3964 [(set (match_operand:SI 0 "arith_reg_operand" "")
3967 "operands[1] = prepare_scc_operands (EQ);")
3969 (define_expand "slt"
3970 [(set (match_operand:SI 0 "arith_reg_operand" "")
3973 "operands[1] = prepare_scc_operands (LT);")
3975 (define_expand "sle"
3976 [(match_operand:SI 0 "arith_reg_operand" "")]
3980 rtx tmp = sh_compare_op0;
3981 sh_compare_op0 = sh_compare_op1;
3982 sh_compare_op1 = tmp;
3983 emit_insn (gen_sge (operands[0]));
3987 (define_expand "sgt"
3988 [(set (match_operand:SI 0 "arith_reg_operand" "")
3991 "operands[1] = prepare_scc_operands (GT);")
3993 (define_expand "sge"
3994 [(set (match_operand:SI 0 "arith_reg_operand" "")
3999 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
4003 rtx lab = gen_label_rtx ();
4004 prepare_scc_operands (EQ);
4005 emit_jump_insn (gen_branch_true (lab));
4006 prepare_scc_operands (GT);
4008 emit_insn (gen_movt (operands[0]));
4011 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
4014 operands[1] = prepare_scc_operands (GE);
4017 (define_expand "sgtu"
4018 [(set (match_operand:SI 0 "arith_reg_operand" "")
4021 "operands[1] = prepare_scc_operands (GTU);")
4023 (define_expand "sltu"
4024 [(set (match_operand:SI 0 "arith_reg_operand" "")
4027 "operands[1] = prepare_scc_operands (LTU);")
4029 (define_expand "sleu"
4030 [(set (match_operand:SI 0 "arith_reg_operand" "")
4033 "operands[1] = prepare_scc_operands (LEU);")
4035 (define_expand "sgeu"
4036 [(set (match_operand:SI 0 "arith_reg_operand" "")
4039 "operands[1] = prepare_scc_operands (GEU);")
4041 ;; sne moves the complement of the T reg to DEST like this:
4045 ;; This is better than xoring compare result with 1 because it does
4046 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
4049 (define_expand "sne"
4050 [(set (match_dup 2) (const_int -1))
4051 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
4052 (neg:SI (plus:SI (match_dup 1)
4055 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
4060 operands[1] = prepare_scc_operands (EQ);
4061 operands[2] = gen_reg_rtx (SImode);
4064 ;; Use the same trick for FP sle / sge
4065 (define_expand "movnegt"
4066 [(set (match_dup 2) (const_int -1))
4067 (parallel [(set (match_operand 0 "" "")
4068 (neg:SI (plus:SI (match_dup 1)
4071 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
4074 "operands[2] = gen_reg_rtx (SImode);")
4076 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
4077 ;; This prevents a regression that occurred when we switched from xor to
4081 [(set (match_operand:SI 0 "arith_reg_operand" "")
4082 (plus:SI (reg:SI T_REG)
4085 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
4086 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
4089 ;; -------------------------------------------------------------------------
4090 ;; Instructions to cope with inline literal tables
4091 ;; -------------------------------------------------------------------------
4093 ; 2 byte integer in line
4095 (define_insn "consttable_2"
4096 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4101 assemble_integer (operands[0], 2, 1);
4104 [(set_attr "length" "2")
4105 (set_attr "in_delay_slot" "no")])
4107 ; 4 byte integer in line
4109 (define_insn "consttable_4"
4110 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4115 assemble_integer (operands[0], 4, 1);
4118 [(set_attr "length" "4")
4119 (set_attr "in_delay_slot" "no")])
4121 ; 8 byte integer in line
4123 (define_insn "consttable_8"
4124 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4129 assemble_integer (operands[0], 8, 1);
4132 [(set_attr "length" "8")
4133 (set_attr "in_delay_slot" "no")])
4135 ; 4 byte floating point
4137 (define_insn "consttable_sf"
4138 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")]
4143 union real_extract u;
4144 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4145 assemble_real (u.d, SFmode);
4148 [(set_attr "length" "4")
4149 (set_attr "in_delay_slot" "no")])
4151 ; 8 byte floating point
4153 (define_insn "consttable_df"
4154 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")]
4159 union real_extract u;
4160 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4161 assemble_real (u.d, DFmode);
4164 [(set_attr "length" "8")
4165 (set_attr "in_delay_slot" "no")])
4167 ;; Alignment is needed for some constant tables; it may also be added for
4168 ;; Instructions at the start of loops, or after unconditional branches.
4169 ;; ??? We would get more accurate lengths if we did instruction
4170 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
4171 ;; here is too conservative.
4173 ; align to a two byte boundary
4175 (define_expand "align_2"
4176 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
4180 ; align to a four byte boundary
4181 ;; align_4 and align_log are instructions for the starts of loops, or
4182 ;; after unconditional branches, which may take up extra room.
4184 (define_expand "align_4"
4185 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
4189 ; align to a cache line boundary
4191 (define_insn "align_log"
4192 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
4195 [(set_attr "length" "0")
4196 (set_attr "in_delay_slot" "no")])
4198 ; emitted at the end of the literal table, used to emit the
4199 ; 32bit branch labels if needed.
4201 (define_insn "consttable_end"
4202 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
4204 "* return output_jump_label_table ();"
4205 [(set_attr "in_delay_slot" "no")])
4207 ;; -------------------------------------------------------------------------
4209 ;; -------------------------------------------------------------------------
4211 ;; String/block move insn.
4213 (define_expand "movstrsi"
4214 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
4215 (mem:BLK (match_operand:BLK 1 "" "")))
4216 (use (match_operand:SI 2 "nonmemory_operand" ""))
4217 (use (match_operand:SI 3 "immediate_operand" ""))
4218 (clobber (reg:SI PR_REG))
4219 (clobber (reg:SI R4_REG))
4220 (clobber (reg:SI R5_REG))
4221 (clobber (reg:SI R0_REG))])]
4225 if(expand_block_move (operands))
4230 (define_insn "block_move_real"
4231 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4232 (mem:BLK (reg:SI R5_REG)))
4233 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4234 (clobber (reg:SI PR_REG))
4235 (clobber (reg:SI R0_REG))])]
4238 [(set_attr "type" "sfunc")
4239 (set_attr "needs_delay_slot" "yes")])
4241 (define_insn "block_lump_real"
4242 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4243 (mem:BLK (reg:SI R5_REG)))
4244 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4245 (use (reg:SI R6_REG))
4246 (clobber (reg:SI PR_REG))
4247 (clobber (reg:SI T_REG))
4248 (clobber (reg:SI R4_REG))
4249 (clobber (reg:SI R5_REG))
4250 (clobber (reg:SI R6_REG))
4251 (clobber (reg:SI R0_REG))])]
4254 [(set_attr "type" "sfunc")
4255 (set_attr "needs_delay_slot" "yes")])
4257 (define_insn "block_move_real_i4"
4258 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4259 (mem:BLK (reg:SI R5_REG)))
4260 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4261 (clobber (reg:SI PR_REG))
4262 (clobber (reg:SI R0_REG))
4263 (clobber (reg:SI R1_REG))
4264 (clobber (reg:SI R2_REG))])]
4267 [(set_attr "type" "sfunc")
4268 (set_attr "needs_delay_slot" "yes")])
4270 (define_insn "block_lump_real_i4"
4271 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4272 (mem:BLK (reg:SI R5_REG)))
4273 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4274 (use (reg:SI R6_REG))
4275 (clobber (reg:SI PR_REG))
4276 (clobber (reg:SI T_REG))
4277 (clobber (reg:SI R4_REG))
4278 (clobber (reg:SI R5_REG))
4279 (clobber (reg:SI R6_REG))
4280 (clobber (reg:SI R0_REG))
4281 (clobber (reg:SI R1_REG))
4282 (clobber (reg:SI R2_REG))
4283 (clobber (reg:SI R3_REG))])]
4286 [(set_attr "type" "sfunc")
4287 (set_attr "needs_delay_slot" "yes")])
4289 ;; -------------------------------------------------------------------------
4290 ;; Floating point instructions.
4291 ;; -------------------------------------------------------------------------
4293 ;; ??? All patterns should have a type attribute.
4295 (define_expand "fpu_switch0"
4296 [(set (match_operand:SI 0 "" "") (match_dup 2))
4297 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4301 operands[1] = get_fpscr_rtx ();
4302 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4304 operands[2] = legitimize_pic_address (operands[2], SImode,
4305 no_new_pseudos ? operands[0] : 0);
4308 (define_expand "fpu_switch1"
4309 [(set (match_operand:SI 0 "" "") (match_dup 2))
4310 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4311 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4315 operands[1] = get_fpscr_rtx ();
4316 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4318 operands[2] = legitimize_pic_address (operands[2], SImode,
4319 no_new_pseudos ? operands[0] : 0);
4320 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4323 (define_expand "movpsi"
4324 [(set (match_operand:PSI 0 "register_operand" "")
4325 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4329 ;; The c / m alternative is a fake to guide reload to load directly into
4330 ;; fpscr, since reload doesn't know how to use post-increment.
4331 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4332 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4333 ;; predicate after reload.
4334 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4335 ;; like a gpr <-> fpul move.
4336 (define_insn "fpu_switch"
4337 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4338 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4340 || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM
4341 || GET_CODE (XEXP (operands[1], 0)) != PLUS"
4343 ! precision stays the same
4351 [(set_attr "length" "0,2,2,4,2,2,2,2")
4352 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4355 [(set (reg:PSI FPSCR_REG)
4356 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4357 "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4358 [(set (match_dup 0) (match_dup 0))]
4361 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4362 gen_rtx (MEM, PSImode,
4363 gen_rtx (POST_INC, Pmode,
4365 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4369 [(set (reg:PSI FPSCR_REG)
4370 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4372 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4375 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4376 gen_rtx (MEM, PSImode,
4377 gen_rtx (POST_INC, Pmode,
4379 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4382 ;; ??? This uses the fp unit, but has no type indicating that.
4383 ;; If we did that, this would either give a bogus latency or introduce
4384 ;; a bogus FIFO constraint.
4385 ;; Since this insn is currently only used for prologues/epilogues,
4386 ;; it is probably best to claim no function unit, which matches the
4388 (define_insn "toggle_sz"
4389 [(set (reg:PSI FPSCR_REG)
4390 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
4394 (define_expand "addsf3"
4395 [(match_operand:SF 0 "arith_reg_operand" "")
4396 (match_operand:SF 1 "arith_reg_operand" "")
4397 (match_operand:SF 2 "arith_reg_operand" "")]
4399 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4401 (define_insn "addsf3_i"
4402 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4403 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4404 (match_operand:SF 2 "arith_reg_operand" "f")))
4405 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4408 [(set_attr "type" "fp")
4409 (set_attr "fp_mode" "single")])
4411 (define_expand "subsf3"
4412 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4413 (match_operand:SF 1 "fp_arith_reg_operand" "")
4414 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4416 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4418 (define_insn "subsf3_i"
4419 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4420 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4421 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4422 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4425 [(set_attr "type" "fp")
4426 (set_attr "fp_mode" "single")])
4428 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4429 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4430 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4431 ;; SH3E, we use a separate insn for SH3E mulsf3.
4433 (define_expand "mulsf3"
4434 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4435 (match_operand:SF 1 "fp_arith_reg_operand" "")
4436 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4441 expand_sf_binop (&gen_mulsf3_i4, operands);
4443 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4447 (define_insn "mulsf3_i4"
4448 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4449 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4450 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4451 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4454 [(set_attr "type" "fp")
4455 (set_attr "fp_mode" "single")])
4457 (define_insn "mulsf3_ie"
4458 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4459 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4460 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
4461 "TARGET_SH3E && ! TARGET_SH4"
4463 [(set_attr "type" "fp")])
4465 (define_insn "*macsf3"
4466 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4467 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
4468 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
4469 (match_operand:SF 3 "arith_reg_operand" "0")))
4470 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4471 "TARGET_SH3E && ! TARGET_SH4"
4473 [(set_attr "type" "fp")
4474 (set_attr "fp_mode" "single")])
4476 (define_expand "divsf3"
4477 [(match_operand:SF 0 "arith_reg_operand" "")
4478 (match_operand:SF 1 "arith_reg_operand" "")
4479 (match_operand:SF 2 "arith_reg_operand" "")]
4481 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4483 (define_insn "divsf3_i"
4484 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4485 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4486 (match_operand:SF 2 "arith_reg_operand" "f")))
4487 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4490 [(set_attr "type" "fdiv")
4491 (set_attr "fp_mode" "single")])
4493 (define_expand "floatsisf2"
4494 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
4495 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
4501 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4506 (define_insn "floatsisf2_i4"
4507 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4508 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
4509 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4512 [(set_attr "type" "fp")
4513 (set_attr "fp_mode" "single")])
4515 (define_insn "*floatsisf2_ie"
4516 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4517 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
4518 "TARGET_SH3E && ! TARGET_SH4"
4520 [(set_attr "type" "fp")])
4522 (define_expand "fix_truncsfsi2"
4523 [(set (match_operand:SI 0 "fpul_operand" "=y")
4524 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4530 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4535 (define_insn "fix_truncsfsi2_i4"
4536 [(set (match_operand:SI 0 "fpul_operand" "=y")
4537 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4538 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4541 [(set_attr "type" "fp")
4542 (set_attr "fp_mode" "single")])
4544 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4545 ;; fix_truncsfsi2_i4.
4546 ;; (define_insn "fix_truncsfsi2_i4_2"
4547 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4548 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4549 ;; (use (reg:PSI FPSCR_REG))
4550 ;; (clobber (reg:SI FPUL_REG))]
4553 ;; [(set_attr "length" "4")
4554 ;; (set_attr "fp_mode" "single")])
4557 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4558 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4559 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4560 ;; (clobber (reg:SI FPUL_REG))]
4562 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4563 ;; (use (match_dup 2))])
4564 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4566 (define_insn "*fixsfsi"
4567 [(set (match_operand:SI 0 "fpul_operand" "=y")
4568 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4569 "TARGET_SH3E && ! TARGET_SH4"
4571 [(set_attr "type" "fp")])
4573 (define_insn "cmpgtsf_t"
4574 [(set (reg:SI T_REG)
4575 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4576 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4577 "TARGET_SH3E && ! TARGET_SH4"
4579 [(set_attr "type" "fp")
4580 (set_attr "fp_mode" "single")])
4582 (define_insn "cmpeqsf_t"
4583 [(set (reg:SI T_REG)
4584 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4585 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4586 "TARGET_SH3E && ! TARGET_SH4"
4588 [(set_attr "type" "fp")
4589 (set_attr "fp_mode" "single")])
4591 (define_insn "ieee_ccmpeqsf_t"
4592 [(set (reg:SI T_REG)
4593 (ior:SI (reg:SI T_REG)
4594 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4595 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
4596 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4597 "* return output_ieee_ccmpeq (insn, operands);"
4598 [(set_attr "length" "4")])
4601 (define_insn "cmpgtsf_t_i4"
4602 [(set (reg:SI T_REG)
4603 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4604 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4605 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4608 [(set_attr "type" "fp")
4609 (set_attr "fp_mode" "single")])
4611 (define_insn "cmpeqsf_t_i4"
4612 [(set (reg:SI T_REG)
4613 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4614 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4615 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4618 [(set_attr "type" "fp")
4619 (set_attr "fp_mode" "single")])
4621 (define_insn "*ieee_ccmpeqsf_t_4"
4622 [(set (reg:SI T_REG)
4623 (ior:SI (reg:SI T_REG)
4624 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4625 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
4626 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4627 "TARGET_IEEE && TARGET_SH4"
4628 "* return output_ieee_ccmpeq (insn, operands);"
4629 [(set_attr "length" "4")
4630 (set_attr "fp_mode" "single")])
4632 (define_expand "cmpsf"
4633 [(set (reg:SI T_REG)
4634 (compare (match_operand:SF 0 "arith_operand" "")
4635 (match_operand:SF 1 "arith_operand" "")))]
4639 sh_compare_op0 = operands[0];
4640 sh_compare_op1 = operands[1];
4644 (define_expand "negsf2"
4645 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4646 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4648 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4650 (define_insn "negsf2_i"
4651 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4652 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4653 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4656 [(set_attr "type" "fmove")
4657 (set_attr "fp_mode" "single")])
4659 (define_expand "sqrtsf2"
4660 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4661 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4663 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4665 (define_insn "sqrtsf2_i"
4666 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4667 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4668 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4671 [(set_attr "type" "fdiv")
4672 (set_attr "fp_mode" "single")])
4674 (define_expand "abssf2"
4675 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4676 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4678 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4680 (define_insn "abssf2_i"
4681 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4682 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4683 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4686 [(set_attr "type" "fmove")
4687 (set_attr "fp_mode" "single")])
4689 (define_expand "adddf3"
4690 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4691 (match_operand:DF 1 "fp_arith_reg_operand" "")
4692 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4694 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4696 (define_insn "adddf3_i"
4697 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4698 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4699 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4700 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4703 [(set_attr "type" "dfp_arith")
4704 (set_attr "fp_mode" "double")])
4706 (define_expand "subdf3"
4707 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4708 (match_operand:DF 1 "fp_arith_reg_operand" "")
4709 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4711 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4713 (define_insn "subdf3_i"
4714 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4715 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4716 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4717 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4720 [(set_attr "type" "dfp_arith")
4721 (set_attr "fp_mode" "double")])
4723 (define_expand "muldf3"
4724 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4725 (match_operand:DF 1 "fp_arith_reg_operand" "")
4726 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4728 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4730 (define_insn "muldf3_i"
4731 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4732 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4733 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4734 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4737 [(set_attr "type" "dfp_arith")
4738 (set_attr "fp_mode" "double")])
4740 (define_expand "divdf3"
4741 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4742 (match_operand:DF 1 "fp_arith_reg_operand" "")
4743 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4745 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4747 (define_insn "divdf3_i"
4748 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4749 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4750 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4751 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4754 [(set_attr "type" "dfdiv")
4755 (set_attr "fp_mode" "double")])
4757 (define_expand "floatsidf2"
4758 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4759 (match_operand:SI 1 "fpul_operand" "")]
4763 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4767 (define_insn "floatsidf2_i"
4768 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4769 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
4770 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4773 [(set_attr "type" "dfp_conv")
4774 (set_attr "fp_mode" "double")])
4776 (define_expand "fix_truncdfsi2"
4777 [(match_operand:SI 0 "fpul_operand" "")
4778 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4782 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4786 (define_insn "fix_truncdfsi2_i"
4787 [(set (match_operand:SI 0 "fpul_operand" "=y")
4788 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4789 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4792 [(set_attr "type" "dfp_conv")
4793 (set_attr "fp_mode" "double")])
4795 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4796 ;; fix_truncdfsi2_i.
4797 ;; (define_insn "fix_truncdfsi2_i4"
4798 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4799 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4800 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4801 ;; (clobber (reg:SI FPUL_REG))]
4804 ;; [(set_attr "length" "4")
4805 ;; (set_attr "fp_mode" "double")])
4808 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4809 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4810 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4811 ;; (clobber (reg:SI FPUL_REG))]
4813 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4814 ;; (use (match_dup 2))])
4815 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4817 (define_insn "cmpgtdf_t"
4818 [(set (reg:SI T_REG)
4819 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4820 (match_operand:DF 1 "arith_reg_operand" "f")))
4821 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4824 [(set_attr "type" "dfp_cmp")
4825 (set_attr "fp_mode" "double")])
4827 (define_insn "cmpeqdf_t"
4828 [(set (reg:SI T_REG)
4829 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4830 (match_operand:DF 1 "arith_reg_operand" "f")))
4831 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4834 [(set_attr "type" "dfp_cmp")
4835 (set_attr "fp_mode" "double")])
4837 (define_insn "*ieee_ccmpeqdf_t"
4838 [(set (reg:SI T_REG)
4839 (ior:SI (reg:SI T_REG)
4840 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4841 (match_operand:DF 1 "arith_reg_operand" "f"))))
4842 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4843 "TARGET_IEEE && TARGET_SH4"
4844 "* return output_ieee_ccmpeq (insn, operands);"
4845 [(set_attr "length" "4")
4846 (set_attr "fp_mode" "double")])
4848 (define_expand "cmpdf"
4849 [(set (reg:SI T_REG)
4850 (compare (match_operand:DF 0 "arith_operand" "")
4851 (match_operand:DF 1 "arith_operand" "")))]
4855 sh_compare_op0 = operands[0];
4856 sh_compare_op1 = operands[1];
4860 (define_expand "negdf2"
4861 [(match_operand:DF 0 "arith_reg_operand" "")
4862 (match_operand:DF 1 "arith_reg_operand" "")]
4864 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4866 (define_insn "negdf2_i"
4867 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4868 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4869 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4872 [(set_attr "type" "fmove")
4873 (set_attr "fp_mode" "double")])
4875 (define_expand "sqrtdf2"
4876 [(match_operand:DF 0 "arith_reg_operand" "")
4877 (match_operand:DF 1 "arith_reg_operand" "")]
4879 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4881 (define_insn "sqrtdf2_i"
4882 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4883 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4884 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4887 [(set_attr "type" "dfdiv")
4888 (set_attr "fp_mode" "double")])
4890 (define_expand "absdf2"
4891 [(match_operand:DF 0 "arith_reg_operand" "")
4892 (match_operand:DF 1 "arith_reg_operand" "")]
4894 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4896 (define_insn "absdf2_i"
4897 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4898 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4899 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4902 [(set_attr "type" "fmove")
4903 (set_attr "fp_mode" "double")])
4905 (define_expand "extendsfdf2"
4906 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4907 (match_operand:SF 1 "fpul_operand" "")]
4911 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4915 (define_insn "extendsfdf2_i4"
4916 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4917 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
4918 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4921 [(set_attr "type" "fp")
4922 (set_attr "fp_mode" "double")])
4924 (define_expand "truncdfsf2"
4925 [(match_operand:SF 0 "fpul_operand" "")
4926 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4930 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4934 (define_insn "truncdfsf2_i4"
4935 [(set (match_operand:SF 0 "fpul_operand" "=y")
4936 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4937 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4940 [(set_attr "type" "fp")
4941 (set_attr "fp_mode" "double")])
4943 ;; Bit field extract patterns. These give better code for packed bitfields,
4944 ;; because they allow auto-increment addresses to be generated.
4946 (define_expand "insv"
4947 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4948 (match_operand:SI 1 "immediate_operand" "")
4949 (match_operand:SI 2 "immediate_operand" ""))
4950 (match_operand:SI 3 "general_operand" ""))]
4951 "! TARGET_LITTLE_ENDIAN"
4954 rtx addr_target, orig_address, shift_reg;
4957 /* ??? expmed doesn't care for non-register predicates. */
4958 if (! memory_operand (operands[0], VOIDmode)
4959 || ! immediate_operand (operands[1], VOIDmode)
4960 || ! immediate_operand (operands[2], VOIDmode)
4961 || ! general_operand (operands[3], VOIDmode))
4963 /* If this isn't a 16 / 24 / 32 bit field, or if
4964 it doesn't start on a byte boundary, then fail. */
4965 size = INTVAL (operands[1]);
4966 if (size < 16 || size > 32 || size % 8 != 0
4967 || (INTVAL (operands[2]) % 8) != 0)
4971 orig_address = XEXP (operands[0], 0);
4972 shift_reg = gen_reg_rtx (SImode);
4973 emit_insn (gen_movsi (shift_reg, operands[3]));
4974 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
4976 operands[0] = change_address (operands[0], QImode, addr_target);
4977 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
4981 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
4982 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
4983 emit_insn (gen_movqi (operands[0],
4984 gen_rtx_SUBREG (QImode, shift_reg, 0)));
4990 ;; -------------------------------------------------------------------------
4992 ;; -------------------------------------------------------------------------
4994 ;; This matches cases where a stack pointer increment at the start of the
4995 ;; epilogue combines with a stack slot read loading the return value.
4998 [(set (match_operand:SI 0 "arith_reg_operand" "")
4999 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
5000 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
5001 "REGNO (operands[1]) != REGNO (operands[0])"
5004 ;; See the comment on the dt combiner pattern above.
5007 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5008 (plus:SI (match_dup 0)
5011 (eq:SI (match_dup 0)
5016 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
5017 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
5018 ;; reload when the constant is too large for a reg+offset address.
5020 ;; ??? We would get much better code if this was done in reload. This would
5021 ;; require modifying find_reloads_address to recognize that if the constant
5022 ;; is out-of-range for an immediate add, then we get better code by reloading
5023 ;; the constant into a register than by reloading the sum into a register,
5024 ;; since the former is one instruction shorter if the address does not need
5025 ;; to be offsettable. Unfortunately this does not work, because there is
5026 ;; only one register, r0, that can be used as an index register. This register
5027 ;; is also the function return value register. So, if we try to force reload
5028 ;; to use double-reg addresses, then we end up with some instructions that
5029 ;; need to use r0 twice. The only way to fix this is to change the calling
5030 ;; convention so that r0 is not used to return values.
5033 [(set (match_operand:SI 0 "register_operand" "=r")
5034 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5035 (set (mem:SI (match_dup 0))
5036 (match_operand:SI 2 "general_movsrc_operand" ""))]
5037 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5038 "mov.l %2,@(%0,%1)")
5041 [(set (match_operand:SI 0 "register_operand" "=r")
5042 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5043 (set (match_operand:SI 2 "general_movdst_operand" "")
5044 (mem:SI (match_dup 0)))]
5045 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5046 "mov.l @(%0,%1),%2")
5049 [(set (match_operand:SI 0 "register_operand" "=r")
5050 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5051 (set (mem:HI (match_dup 0))
5052 (match_operand:HI 2 "general_movsrc_operand" ""))]
5053 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5054 "mov.w %2,@(%0,%1)")
5057 [(set (match_operand:SI 0 "register_operand" "=r")
5058 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5059 (set (match_operand:HI 2 "general_movdst_operand" "")
5060 (mem:HI (match_dup 0)))]
5061 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5062 "mov.w @(%0,%1),%2")
5065 [(set (match_operand:SI 0 "register_operand" "=r")
5066 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5067 (set (mem:QI (match_dup 0))
5068 (match_operand:QI 2 "general_movsrc_operand" ""))]
5069 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5070 "mov.b %2,@(%0,%1)")
5073 [(set (match_operand:SI 0 "register_operand" "=r")
5074 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5075 (set (match_operand:QI 2 "general_movdst_operand" "")
5076 (mem:QI (match_dup 0)))]
5077 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5078 "mov.b @(%0,%1),%2")
5081 [(set (match_operand:SI 0 "register_operand" "=r")
5082 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5083 (set (mem:SF (match_dup 0))
5084 (match_operand:SF 2 "general_movsrc_operand" ""))]
5085 "REGNO (operands[0]) == 0
5086 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5087 || (GET_CODE (operands[2]) == SUBREG
5088 && REGNO (SUBREG_REG (operands[2])) < 16))
5089 && reg_unused_after (operands[0], insn)"
5090 "mov.l %2,@(%0,%1)")
5093 [(set (match_operand:SI 0 "register_operand" "=r")
5094 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5095 (set (match_operand:SF 2 "general_movdst_operand" "")
5097 (mem:SF (match_dup 0)))]
5098 "REGNO (operands[0]) == 0
5099 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5100 || (GET_CODE (operands[2]) == SUBREG
5101 && REGNO (SUBREG_REG (operands[2])) < 16))
5102 && reg_unused_after (operands[0], insn)"
5103 "mov.l @(%0,%1),%2")
5106 [(set (match_operand:SI 0 "register_operand" "=r")
5107 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5108 (set (mem:SF (match_dup 0))
5109 (match_operand:SF 2 "general_movsrc_operand" ""))]
5110 "REGNO (operands[0]) == 0
5111 && ((GET_CODE (operands[2]) == REG
5112 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5113 || (GET_CODE (operands[2]) == SUBREG
5114 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5115 && reg_unused_after (operands[0], insn)"
5116 "fmov{.s|} %2,@(%0,%1)")
5119 [(set (match_operand:SI 0 "register_operand" "=r")
5120 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5121 (set (match_operand:SF 2 "general_movdst_operand" "")
5123 (mem:SF (match_dup 0)))]
5124 "REGNO (operands[0]) == 0
5125 && ((GET_CODE (operands[2]) == REG
5126 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5127 || (GET_CODE (operands[2]) == SUBREG
5128 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5129 && reg_unused_after (operands[0], insn)"
5130 "fmov{.s|} @(%0,%1),%2")
5132 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
5133 (define_insn "sp_switch_1"
5140 xoperands[0] = sp_switch;
5141 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
5142 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
5143 return \"mov r0,r15\";
5145 [(set_attr "length" "10")])
5147 ;; Switch back to the original stack for interrupt functions with the
5148 ;; sp_switch attribute. */
5149 (define_insn "sp_switch_2"
5152 "mov.l @r15+,r15\;mov.l @r15+,r0"
5153 [(set_attr "length" "4")])