1 ;; GCC machine description for SSE instructions
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;; All vector float modes
23 (define_mode_iterator VF
24 [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")
25 (V8SF "TARGET_AVX") (V4DF "TARGET_AVX")])
27 ;; All SFmode vector float modes
28 (define_mode_iterator VF1
29 [(V4SF "TARGET_SSE") (V8SF "TARGET_AVX")])
31 ;; All DFmode vector float modes
32 (define_mode_iterator VF2
33 [(V2DF "TARGET_SSE2") (V4DF "TARGET_AVX")])
35 ;; All 128bit vector float modes
36 (define_mode_iterator VF_128
37 [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")])
41 ;; Instruction suffix for sign and zero extensions.
42 (define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
44 ;; 16 byte integral modes handled by SSE
45 (define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
47 ;; All 16-byte vector modes handled by SSE
48 (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
49 (define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF])
51 ;; 32 byte integral vector modes handled by AVX
52 (define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
54 ;; All 32-byte vector modes handled by AVX
55 (define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
57 ;; All QI vector modes handled by AVX
58 (define_mode_iterator AVXMODEQI [V32QI V16QI])
60 ;; All DI vector modes handled by AVX
61 (define_mode_iterator AVXMODEDI [V4DI V2DI])
63 ;; All vector modes handled by AVX
64 (define_mode_iterator AVXMODE
65 [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
66 (define_mode_iterator AVXMODE16
67 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
70 (define_mode_iterator SSEMODE12 [V16QI V8HI])
71 (define_mode_iterator SSEMODE24 [V8HI V4SI])
72 (define_mode_iterator SSEMODE14 [V16QI V4SI])
73 (define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
74 (define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
75 (define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
76 (define_mode_iterator SSEMODEF2P [V4SF V2DF])
78 (define_mode_iterator AVX256MODEF2P [V8SF V4DF])
79 (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
80 (define_mode_iterator AVX256MODE24P [V8SI V8SF V4DI V4DF])
81 (define_mode_iterator AVX256MODE4P [V4DI V4DF])
82 (define_mode_iterator AVX256MODE8P [V8SI V8SF])
83 (define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
84 (define_mode_iterator AVXMODEF4P [V4SF V4DF])
85 (define_mode_iterator AVXMODEFDP [V2DF V4DF])
86 (define_mode_iterator AVXMODEFSP [V4SF V8SF])
88 (define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
90 ;; Int-float size matches
91 (define_mode_iterator SSEMODE4S [V4SF V4SI])
92 (define_mode_iterator SSEMODE2D [V2DF V2DI])
94 ;; Modes handled by integer vcond pattern
95 (define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
96 (V2DI "TARGET_SSE4_2")])
98 ;; Modes handled by vec_extract_even/odd pattern.
99 (define_mode_iterator SSEMODE_EO
102 (V2DI "TARGET_SSE2") (V4SI "TARGET_SSE2")
103 (V8HI "TARGET_SSE2") (V16QI "TARGET_SSE2")
104 (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
106 ;; Modes handled by storent patterns.
107 (define_mode_iterator STORENT_MODE
108 [(SF "TARGET_SSE4A") (DF "TARGET_SSE4A")
109 (SI "TARGET_SSE2") (V2DI "TARGET_SSE2") (V2DF "TARGET_SSE2")
111 (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
113 ;; Modes handled by vector extract patterns.
114 (define_mode_iterator VEC_EXTRACT_MODE
115 [(V2DI "TARGET_SSE") (V4SI "TARGET_SSE")
116 (V8HI "TARGET_SSE") (V16QI "TARGET_SSE")
117 (V2DF "TARGET_SSE") (V4SF "TARGET_SSE")
118 (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
120 ;; Mapping from float mode to required SSE level
121 (define_mode_attr sse
122 [(SF "sse") (DF "sse2")
123 (V4SF "sse") (V2DF "sse2")
124 (V8SF "avx") (V4DF "avx")])
126 ;; Mapping from integer vector mode to mnemonic suffix
127 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
129 ;; Mapping of the insn mnemonic suffix
130 (define_mode_attr ssemodesuffix
131 [(SF "ss") (DF "sd") (V4SF "ps") (V2DF "pd") (V8SF "ps") (V4DF "pd")
132 (V8SI "ps") (V4DI "pd")])
133 (define_mode_attr ssescalarmodesuffix
134 [(SF "ss") (DF "sd") (V4SF "ss") (V2DF "sd") (V8SF "ss") (V8SI "ss")
135 (V4DF "sd") (V4SI "d") (V4DI "sd")])
137 ;; Mapping of the max integer size for xop rotate immediate constraint
138 (define_mode_attr sserotatemax [(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
140 ;; Mapping of vector modes back to the scalar modes
141 (define_mode_attr ssescalarmode [(V4SF "SF") (V2DF "DF")
142 (V16QI "QI") (V8HI "HI")
143 (V4SI "SI") (V2DI "DI")])
145 ;; Mapping of vector modes to a vector mode of double size
146 (define_mode_attr ssedoublesizemode
147 [(V2DF "V4DF") (V2DI "V4DI") (V4SF "V8SF") (V4SI "V8SI")
148 (V8HI "V16HI") (V16QI "V32QI")
149 (V4DF "V8DF") (V8SF "V16SF")
150 (V4DI "V8DI") (V8SI "V16SI") (V16HI "V32HI") (V32QI "V64QI")])
152 ;; Number of scalar elements in each vector type
153 (define_mode_attr ssescalarnum
154 [(V4SF "4") (V2DF "2") (V16QI "16") (V8HI "8") (V4SI "4") (V2DI "2")
155 (V8SF "8") (V4DF "4") (V32QI "32") (V16HI "16") (V8SI "8") (V4DI "4")])
158 (define_mode_attr avxvecmode
159 [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
160 (V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF")
161 (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")])
162 (define_mode_attr avxvecpsmode
163 [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
164 (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
165 (define_mode_attr avxhalfvecmode
166 [(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI")
167 (V8SF "V4SF") (V4DF "V2DF")
168 (V16QI "V8QI") (V8HI "V4HI") (V4SI "V2SI") (V4SF "V2SF")])
169 (define_mode_attr avxscalarmode
170 [(V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI") (V4SF "SF") (V2DF "DF")
171 (V32QI "QI") (V16HI "HI") (V8SI "SI") (V4DI "DI") (V8SF "SF") (V4DF "DF")])
172 (define_mode_attr avxcvtvecmode
173 [(V4SF "V4SI") (V8SF "V8SI") (V4SI "V4SF") (V8SI "V8SF")])
174 (define_mode_attr avxpermvecmode
175 [(V2DF "V2DI") (V4SF "V4SI") (V4DF "V4DI") (V8SF "V8SI")])
176 (define_mode_attr avxmodesuffixp
177 [(V2DF "pd") (V4SI "si") (V4SF "ps") (V8SF "ps") (V8SI "si")
179 (define_mode_attr avxmodesuffix
180 [(V16QI "") (V32QI "256") (V4SI "") (V4SF "") (V2DF "")
181 (V8SI "256") (V8SF "256") (V4DF "256")])
183 ;; Mapping of immediate bits for blend instructions
184 (define_mode_attr blendbits
185 [(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
187 ;; Mapping of immediate bits for pinsr instructions
188 (define_mode_attr pinsrbits [(V16QI "32768") (V8HI "128") (V4SI "8")])
190 ;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
192 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
196 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
198 (define_expand "mov<mode>"
199 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
200 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
203 ix86_expand_vector_move (<MODE>mode, operands);
207 (define_insn "*avx_mov<mode>_internal"
208 [(set (match_operand:AVXMODE16 0 "nonimmediate_operand" "=x,x ,m")
209 (match_operand:AVXMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
211 && (register_operand (operands[0], <MODE>mode)
212 || register_operand (operands[1], <MODE>mode))"
214 switch (which_alternative)
217 return standard_sse_constant_opcode (insn, operands[1]);
220 switch (get_attr_mode (insn))
224 if (misaligned_operand (operands[0], <MODE>mode)
225 || misaligned_operand (operands[1], <MODE>mode))
226 return "vmovups\t{%1, %0|%0, %1}";
228 return "vmovaps\t{%1, %0|%0, %1}";
231 if (misaligned_operand (operands[0], <MODE>mode)
232 || misaligned_operand (operands[1], <MODE>mode))
233 return "vmovupd\t{%1, %0|%0, %1}";
234 else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
235 return "vmovaps\t{%1, %0|%0, %1}";
237 return "vmovapd\t{%1, %0|%0, %1}";
239 if (misaligned_operand (operands[0], <MODE>mode)
240 || misaligned_operand (operands[1], <MODE>mode))
241 return "vmovdqu\t{%1, %0|%0, %1}";
242 else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
243 return "vmovaps\t{%1, %0|%0, %1}";
245 return "vmovdqa\t{%1, %0|%0, %1}";
251 [(set_attr "type" "sselog1,ssemov,ssemov")
252 (set_attr "prefix" "vex")
253 (set_attr "mode" "<avxvecmode>")])
255 ;; All of these patterns are enabled for SSE1 as well as SSE2.
256 ;; This is essential for maintaining stable calling conventions.
258 (define_expand "mov<mode>"
259 [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "")
260 (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))]
263 ix86_expand_vector_move (<MODE>mode, operands);
267 (define_insn "*mov<mode>_internal"
268 [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "=x,x ,m")
269 (match_operand:SSEMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
271 && (register_operand (operands[0], <MODE>mode)
272 || register_operand (operands[1], <MODE>mode))"
274 switch (which_alternative)
277 return standard_sse_constant_opcode (insn, operands[1]);
280 switch (get_attr_mode (insn))
283 return "movaps\t{%1, %0|%0, %1}";
285 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
286 return "movaps\t{%1, %0|%0, %1}";
288 return "movapd\t{%1, %0|%0, %1}";
290 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
291 return "movaps\t{%1, %0|%0, %1}";
293 return "movdqa\t{%1, %0|%0, %1}";
299 [(set_attr "type" "sselog1,ssemov,ssemov")
301 (cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
302 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
303 (and (eq_attr "alternative" "2")
304 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
306 (const_string "V4SF")
307 (eq (const_string "<MODE>mode") (const_string "V4SFmode"))
308 (const_string "V4SF")
309 (eq (const_string "<MODE>mode") (const_string "V2DFmode"))
310 (const_string "V2DF")
312 (const_string "TI")))])
314 ;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
315 ;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
316 ;; from memory, we'd prefer to load the memory directly into the %xmm
317 ;; register. To facilitate this happy circumstance, this pattern won't
318 ;; split until after register allocation. If the 64-bit value didn't
319 ;; come from memory, this is the best we can do. This is much better
320 ;; than storing %edx:%eax into a stack temporary and loading an %xmm
323 (define_insn_and_split "movdi_to_sse"
325 [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
326 (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
327 (clobber (match_scratch:V4SI 2 "=&x,X"))])]
328 "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES"
330 "&& reload_completed"
333 if (register_operand (operands[1], DImode))
335 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
336 Assemble the 64-bit DImode value in an xmm register. */
337 emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode),
338 gen_rtx_SUBREG (SImode, operands[1], 0)));
339 emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode),
340 gen_rtx_SUBREG (SImode, operands[1], 4)));
341 emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0],
344 else if (memory_operand (operands[1], DImode))
345 emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]),
346 operands[1], const0_rtx));
352 [(set (match_operand:V4SF 0 "register_operand" "")
353 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
354 "TARGET_SSE && reload_completed"
357 (vec_duplicate:V4SF (match_dup 1))
361 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
362 operands[2] = CONST0_RTX (V4SFmode);
366 [(set (match_operand:V2DF 0 "register_operand" "")
367 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
368 "TARGET_SSE2 && reload_completed"
369 [(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))]
371 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
372 operands[2] = CONST0_RTX (DFmode);
375 (define_expand "push<mode>1"
376 [(match_operand:AVX256MODE 0 "register_operand" "")]
379 ix86_expand_push (<MODE>mode, operands[0]);
383 (define_expand "push<mode>1"
384 [(match_operand:SSEMODE16 0 "register_operand" "")]
387 ix86_expand_push (<MODE>mode, operands[0]);
391 (define_expand "movmisalign<mode>"
392 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
393 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
396 ix86_expand_vector_move_misalign (<MODE>mode, operands);
400 (define_expand "movmisalign<mode>"
401 [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "")
402 (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))]
405 ix86_expand_vector_move_misalign (<MODE>mode, operands);
409 (define_expand "avx_movu<ssemodesuffix><avxmodesuffix>"
410 [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "")
412 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")]
414 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
416 if (MEM_P (operands[0]) && MEM_P (operands[1]))
417 operands[1] = force_reg (<MODE>mode, operands[1]);
420 (define_insn "*avx_movu<ssemodesuffix><avxmodesuffix>"
421 [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
423 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
425 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
426 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
427 "vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"
428 [(set_attr "type" "ssemov")
429 (set_attr "movu" "1")
430 (set_attr "prefix" "vex")
431 (set_attr "mode" "<MODE>")])
433 (define_insn "sse2_movq128"
434 [(set (match_operand:V2DI 0 "register_operand" "=x")
437 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
438 (parallel [(const_int 0)]))
441 "%vmovq\t{%1, %0|%0, %1}"
442 [(set_attr "type" "ssemov")
443 (set_attr "prefix" "maybe_vex")
444 (set_attr "mode" "TI")])
446 (define_expand "<sse>_movu<ssemodesuffix>"
447 [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "")
449 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")]
451 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
453 if (MEM_P (operands[0]) && MEM_P (operands[1]))
454 operands[1] = force_reg (<MODE>mode, operands[1]);
457 (define_insn "*<sse>_movu<ssemodesuffix>"
458 [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
460 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
462 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
463 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
464 "movu<ssemodesuffix>\t{%1, %0|%0, %1}"
465 [(set_attr "type" "ssemov")
466 (set_attr "movu" "1")
467 (set_attr "mode" "<MODE>")])
469 (define_expand "avx_movdqu<avxmodesuffix>"
470 [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "")
472 [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")]
476 if (MEM_P (operands[0]) && MEM_P (operands[1]))
477 operands[1] = force_reg (<MODE>mode, operands[1]);
480 (define_insn "*avx_movdqu<avxmodesuffix>"
481 [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
483 [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
485 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
486 "vmovdqu\t{%1, %0|%0, %1}"
487 [(set_attr "type" "ssemov")
488 (set_attr "movu" "1")
489 (set_attr "prefix" "vex")
490 (set_attr "mode" "<avxvecmode>")])
492 (define_expand "sse2_movdqu"
493 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
494 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")]
498 if (MEM_P (operands[0]) && MEM_P (operands[1]))
499 operands[1] = force_reg (V16QImode, operands[1]);
502 (define_insn "*sse2_movdqu"
503 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
504 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
506 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
507 "movdqu\t{%1, %0|%0, %1}"
508 [(set_attr "type" "ssemov")
509 (set_attr "movu" "1")
510 (set_attr "prefix_data16" "1")
511 (set_attr "mode" "TI")])
513 (define_insn "avx_movnt<mode>"
514 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
516 [(match_operand:AVXMODEF2P 1 "register_operand" "x")]
518 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
519 "vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
520 [(set_attr "type" "ssemov")
521 (set_attr "prefix" "vex")
522 (set_attr "mode" "<MODE>")])
524 (define_insn "<sse>_movnt<mode>"
525 [(set (match_operand:SSEMODEF2P 0 "memory_operand" "=m")
527 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
529 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
530 "movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
531 [(set_attr "type" "ssemov")
532 (set_attr "mode" "<MODE>")])
534 (define_insn "avx_movnt<mode>"
535 [(set (match_operand:AVXMODEDI 0 "memory_operand" "=m")
537 [(match_operand:AVXMODEDI 1 "register_operand" "x")]
540 "vmovntdq\t{%1, %0|%0, %1}"
541 [(set_attr "type" "ssecvt")
542 (set_attr "prefix" "vex")
543 (set_attr "mode" "<avxvecmode>")])
545 (define_insn "sse2_movntv2di"
546 [(set (match_operand:V2DI 0 "memory_operand" "=m")
547 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
550 "movntdq\t{%1, %0|%0, %1}"
551 [(set_attr "type" "ssemov")
552 (set_attr "prefix_data16" "1")
553 (set_attr "mode" "TI")])
555 (define_insn "sse2_movntsi"
556 [(set (match_operand:SI 0 "memory_operand" "=m")
557 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
560 "movnti\t{%1, %0|%0, %1}"
561 [(set_attr "type" "ssemov")
562 (set_attr "prefix_data16" "0")
563 (set_attr "mode" "V2DF")])
565 (define_insn "avx_lddqu<avxmodesuffix>"
566 [(set (match_operand:AVXMODEQI 0 "register_operand" "=x")
568 [(match_operand:AVXMODEQI 1 "memory_operand" "m")]
571 "vlddqu\t{%1, %0|%0, %1}"
572 [(set_attr "type" "ssecvt")
573 (set_attr "movu" "1")
574 (set_attr "prefix" "vex")
575 (set_attr "mode" "<avxvecmode>")])
577 (define_insn "sse3_lddqu"
578 [(set (match_operand:V16QI 0 "register_operand" "=x")
579 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
582 "lddqu\t{%1, %0|%0, %1}"
583 [(set_attr "type" "ssemov")
584 (set_attr "movu" "1")
585 (set_attr "prefix_data16" "0")
586 (set_attr "prefix_rep" "1")
587 (set_attr "mode" "TI")])
589 ; Expand patterns for non-temporal stores. At the moment, only those
590 ; that directly map to insns are defined; it would be possible to
591 ; define patterns for other modes that would expand to several insns.
593 (define_expand "storent<mode>"
594 [(set (match_operand:STORENT_MODE 0 "memory_operand" "")
596 [(match_operand:STORENT_MODE 1 "register_operand" "")]
599 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
601 ;; Parallel floating point arithmetic
603 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
605 (define_expand "<code><mode>2"
606 [(set (match_operand:VF 0 "register_operand" "")
608 (match_operand:VF 1 "register_operand" "")))]
610 "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
612 (define_insn_and_split "*absneg<mode>2"
613 [(set (match_operand:VF 0 "register_operand" "=x,x,x,x")
614 (match_operator:VF 3 "absneg_operator"
615 [(match_operand:VF 1 "nonimmediate_operand" "0, xm,x, m")]))
616 (use (match_operand:VF 2 "nonimmediate_operand" "xm,0, xm,x"))]
622 enum rtx_code absneg_op;
628 if (MEM_P (operands[1]))
629 op1 = operands[2], op2 = operands[1];
631 op1 = operands[1], op2 = operands[2];
636 if (rtx_equal_p (operands[0], operands[1]))
642 absneg_op = GET_CODE (operands[3]) == NEG ? XOR : AND;
643 t = gen_rtx_fmt_ee (absneg_op, <MODE>mode, op1, op2);
644 t = gen_rtx_SET (VOIDmode, operands[0], t);
648 [(set_attr "isa" "noavx,noavx,avx,avx")])
650 (define_expand "<plusminus_insn><mode>3"
651 [(set (match_operand:VF 0 "register_operand" "")
653 (match_operand:VF 1 "nonimmediate_operand" "")
654 (match_operand:VF 2 "nonimmediate_operand" "")))]
656 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
658 (define_insn "*<plusminus_insn><mode>3"
659 [(set (match_operand:VF 0 "register_operand" "=x,x")
661 (match_operand:VF 1 "nonimmediate_operand" "<comm>0,x")
662 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
663 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
665 <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
666 v<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
667 [(set_attr "isa" "noavx,avx")
668 (set_attr "type" "sseadd")
669 (set_attr "prefix" "orig,vex")
670 (set_attr "mode" "<MODE>")])
672 (define_insn "<sse>_vm<plusminus_insn><mode>3"
673 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
676 (match_operand:VF_128 1 "register_operand" "0,x")
677 (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
682 <plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %2}
683 v<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
684 [(set_attr "isa" "noavx,avx")
685 (set_attr "type" "sseadd")
686 (set_attr "prefix" "orig,vex")
687 (set_attr "mode" "<ssescalarmode>")])
689 (define_expand "mul<mode>3"
690 [(set (match_operand:VF 0 "register_operand" "")
692 (match_operand:VF 1 "nonimmediate_operand" "")
693 (match_operand:VF 2 "nonimmediate_operand" "")))]
695 "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
697 (define_insn "*mul<mode>3"
698 [(set (match_operand:VF 0 "register_operand" "=x,x")
700 (match_operand:VF 1 "nonimmediate_operand" "%0,x")
701 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
702 "ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
704 mul<ssemodesuffix>\t{%2, %0|%0, %2}
705 vmul<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
706 [(set_attr "isa" "noavx,avx")
707 (set_attr "type" "ssemul")
708 (set_attr "prefix" "orig,vex")
709 (set_attr "mode" "<MODE>")])
711 (define_insn "<sse>_vmmul<mode>3"
712 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
715 (match_operand:VF_128 1 "register_operand" "0,x")
716 (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
721 mul<ssescalarmodesuffix>\t{%2, %0|%0, %2}
722 vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
723 [(set_attr "isa" "noavx,avx")
724 (set_attr "type" "ssemul")
725 (set_attr "prefix" "orig,vex")
726 (set_attr "mode" "<ssescalarmode>")])
728 (define_expand "div<mode>3"
729 [(set (match_operand:VF2 0 "register_operand" "")
730 (div:VF2 (match_operand:VF2 1 "register_operand" "")
731 (match_operand:VF2 2 "nonimmediate_operand" "")))]
733 "ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
735 (define_expand "div<mode>3"
736 [(set (match_operand:VF1 0 "register_operand" "")
737 (div:VF1 (match_operand:VF1 1 "register_operand" "")
738 (match_operand:VF1 2 "nonimmediate_operand" "")))]
741 ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
743 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
744 && flag_finite_math_only && !flag_trapping_math
745 && flag_unsafe_math_optimizations)
747 ix86_emit_swdivsf (operands[0], operands[1], operands[2], <MODE>mode);
752 (define_insn "<sse>_div<mode>3"
753 [(set (match_operand:VF 0 "register_operand" "=x,x")
755 (match_operand:VF 1 "register_operand" "0,x")
756 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
759 div<ssemodesuffix>\t{%2, %0|%0, %2}
760 vdiv<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
761 [(set_attr "isa" "noavx,avx")
762 (set_attr "type" "ssediv")
763 (set_attr "prefix" "orig,vex")
764 (set_attr "mode" "<MODE>")])
766 (define_insn "<sse>_vmdiv<mode>3"
767 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
770 (match_operand:VF_128 1 "register_operand" "0,x")
771 (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
776 div<ssescalarmodesuffix>\t{%2, %0|%0, %2}
777 vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
778 [(set_attr "isa" "noavx,avx")
779 (set_attr "type" "ssediv")
780 (set_attr "prefix" "orig,vex")
781 (set_attr "mode" "<ssescalarmode>")])
783 (define_insn "<sse>_rcp<mode>2"
784 [(set (match_operand:VF1 0 "register_operand" "=x")
786 [(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
788 "%vrcpps\t{%1, %0|%0, %1}"
789 [(set_attr "type" "sse")
790 (set_attr "atom_sse_attr" "rcp")
791 (set_attr "prefix" "maybe_vex")
792 (set_attr "mode" "<MODE>")])
794 (define_insn "sse_vmrcpv4sf2"
795 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
797 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,xm")]
799 (match_operand:V4SF 2 "register_operand" "0,x")
803 rcpss\t{%1, %0|%0, %1}
804 vrcpss\t{%1, %2, %0|%0, %2, %1}"
805 [(set_attr "isa" "noavx,avx")
806 (set_attr "type" "sse")
807 (set_attr "atom_sse_attr" "rcp")
808 (set_attr "prefix" "orig,vex")
809 (set_attr "mode" "SF")])
811 (define_expand "sqrt<mode>2"
812 [(set (match_operand:VF2 0 "register_operand" "")
813 (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))])
815 (define_expand "sqrt<mode>2"
816 [(set (match_operand:VF1 0 "register_operand" "")
817 (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))]
820 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
821 && flag_finite_math_only && !flag_trapping_math
822 && flag_unsafe_math_optimizations)
824 ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, false);
829 (define_insn "<sse>_sqrt<mode>2"
830 [(set (match_operand:VF 0 "register_operand" "=x")
831 (sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "xm")))]
833 "%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}"
834 [(set_attr "type" "sse")
835 (set_attr "atom_sse_attr" "sqrt")
836 (set_attr "prefix" "maybe_vex")
837 (set_attr "mode" "<MODE>")])
839 (define_insn "<sse>_vmsqrt<mode>2"
840 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
843 (match_operand:VF_128 1 "nonimmediate_operand" "xm,xm"))
844 (match_operand:VF_128 2 "register_operand" "0,x")
848 sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %1}
849 vsqrt<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %1}"
850 [(set_attr "isa" "noavx,avx")
851 (set_attr "type" "sse")
852 (set_attr "atom_sse_attr" "sqrt")
853 (set_attr "prefix" "orig,vex")
854 (set_attr "mode" "<ssescalarmode>")])
856 (define_expand "rsqrt<mode>2"
857 [(set (match_operand:VF1 0 "register_operand" "")
859 [(match_operand:VF1 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
862 ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true);
866 (define_insn "<sse>_rsqrt<mode>2"
867 [(set (match_operand:VF1 0 "register_operand" "=x")
869 [(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
871 "%vrsqrtps\t{%1, %0|%0, %1}"
872 [(set_attr "type" "sse")
873 (set_attr "prefix" "maybe_vex")
874 (set_attr "mode" "<MODE>")])
876 (define_insn "sse_vmrsqrtv4sf2"
877 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
879 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,xm")]
881 (match_operand:V4SF 2 "register_operand" "0,x")
885 rsqrtss\t{%1, %0|%0, %1}
886 vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
887 [(set_attr "isa" "noavx,avx")
888 (set_attr "type" "sse")
889 (set_attr "prefix" "orig,vex")
890 (set_attr "mode" "SF")])
892 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
893 ;; isn't really correct, as those rtl operators aren't defined when
894 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
896 (define_expand "<code><mode>3"
897 [(set (match_operand:VF 0 "register_operand" "")
899 (match_operand:VF 1 "nonimmediate_operand" "")
900 (match_operand:VF 2 "nonimmediate_operand" "")))]
903 if (!flag_finite_math_only)
904 operands[1] = force_reg (<MODE>mode, operands[1]);
905 ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
908 (define_insn "*<code><mode>3_finite"
909 [(set (match_operand:VF 0 "register_operand" "=x,x")
911 (match_operand:VF 1 "nonimmediate_operand" "%0,x")
912 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
913 "flag_finite_math_only
914 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
916 <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
917 v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
918 [(set_attr "isa" "noavx,avx")
919 (set_attr "type" "sseadd")
920 (set_attr "prefix" "orig,vex")
921 (set_attr "mode" "<MODE>")])
923 (define_insn "*<code><mode>3"
924 [(set (match_operand:VF 0 "register_operand" "=x,x")
926 (match_operand:VF 1 "register_operand" "0,x")
927 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
928 "!flag_finite_math_only"
930 <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
931 v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
932 [(set_attr "isa" "noavx,avx")
933 (set_attr "type" "sseadd")
934 (set_attr "prefix" "orig,vex")
935 (set_attr "mode" "<MODE>")])
937 (define_insn "<sse>_vm<code><mode>3"
938 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
941 (match_operand:VF_128 1 "register_operand" "0,x")
942 (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
947 <maxmin_float><ssescalarmodesuffix>\t{%2, %0|%0, %2}
948 v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
949 [(set_attr "isa" "noavx,avx")
950 (set_attr "type" "sse")
951 (set_attr "prefix" "orig,vex")
952 (set_attr "mode" "<ssescalarmode>")])
954 ;; These versions of the min/max patterns implement exactly the operations
955 ;; min = (op1 < op2 ? op1 : op2)
956 ;; max = (!(op1 < op2) ? op1 : op2)
957 ;; Their operands are not commutative, and thus they may be used in the
958 ;; presence of -0.0 and NaN.
960 (define_insn "*ieee_smin<mode>3"
961 [(set (match_operand:VF 0 "register_operand" "=x,x")
963 [(match_operand:VF 1 "register_operand" "0,x")
964 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
968 vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
969 min<ssemodesuffix>\t{%2, %0|%0, %2}"
970 [(set_attr "isa" "noavx,avx")
971 (set_attr "type" "sseadd")
972 (set_attr "prefix" "orig,vex")
973 (set_attr "mode" "<MODE>")])
975 (define_insn "*ieee_smax<mode>3"
976 [(set (match_operand:VF 0 "register_operand" "=x,x")
978 [(match_operand:VF 1 "register_operand" "0,x")
979 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
983 vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
984 max<ssemodesuffix>\t{%2, %0|%0, %2}"
985 [(set_attr "isa" "noavx,avx")
986 (set_attr "type" "sseadd")
987 (set_attr "prefix" "orig,vex")
988 (set_attr "mode" "<MODE>")])
990 (define_insn "avx_addsubv4df3"
991 [(set (match_operand:V4DF 0 "register_operand" "=x")
994 (match_operand:V4DF 1 "register_operand" "x")
995 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
996 (minus:V4DF (match_dup 1) (match_dup 2))
999 "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1000 [(set_attr "type" "sseadd")
1001 (set_attr "prefix" "vex")
1002 (set_attr "mode" "V4DF")])
1004 (define_insn "sse3_addsubv2df3"
1005 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1008 (match_operand:V2DF 1 "register_operand" "0,x")
1009 (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm"))
1010 (minus:V2DF (match_dup 1) (match_dup 2))
1014 addsubpd\t{%2, %0|%0, %2}
1015 vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1016 [(set_attr "isa" "noavx,avx")
1017 (set_attr "type" "sseadd")
1018 (set_attr "atom_unit" "complex")
1019 (set_attr "prefix" "orig,vex")
1020 (set_attr "mode" "V2DF")])
1022 (define_insn "avx_addsubv8sf3"
1023 [(set (match_operand:V8SF 0 "register_operand" "=x")
1026 (match_operand:V8SF 1 "register_operand" "x")
1027 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
1028 (minus:V8SF (match_dup 1) (match_dup 2))
1031 "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1032 [(set_attr "type" "sseadd")
1033 (set_attr "prefix" "vex")
1034 (set_attr "mode" "V8SF")])
1036 (define_insn "sse3_addsubv4sf3"
1037 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1040 (match_operand:V4SF 1 "register_operand" "0,x")
1041 (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
1042 (minus:V4SF (match_dup 1) (match_dup 2))
1046 addsubps\t{%2, %0|%0, %2}
1047 vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1048 [(set_attr "isa" "noavx,avx")
1049 (set_attr "type" "sseadd")
1050 (set_attr "prefix" "orig,vex")
1051 (set_attr "prefix_rep" "1,*")
1052 (set_attr "mode" "V4SF")])
1054 (define_insn "avx_h<plusminus_insn>v4df3"
1055 [(set (match_operand:V4DF 0 "register_operand" "=x")
1060 (match_operand:V4DF 1 "register_operand" "x")
1061 (parallel [(const_int 0)]))
1062 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1064 (vec_select:DF (match_dup 1) (parallel [(const_int 2)]))
1065 (vec_select:DF (match_dup 1) (parallel [(const_int 3)]))))
1069 (match_operand:V4DF 2 "nonimmediate_operand" "xm")
1070 (parallel [(const_int 0)]))
1071 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))
1073 (vec_select:DF (match_dup 2) (parallel [(const_int 2)]))
1074 (vec_select:DF (match_dup 2) (parallel [(const_int 3)]))))))]
1076 "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1077 [(set_attr "type" "sseadd")
1078 (set_attr "prefix" "vex")
1079 (set_attr "mode" "V4DF")])
1081 (define_insn "sse3_h<plusminus_insn>v2df3"
1082 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1086 (match_operand:V2DF 1 "register_operand" "0,x")
1087 (parallel [(const_int 0)]))
1088 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1091 (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")
1092 (parallel [(const_int 0)]))
1093 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1096 h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}
1097 vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1098 [(set_attr "isa" "noavx,avx")
1099 (set_attr "type" "sseadd")
1100 (set_attr "prefix" "orig,vex")
1101 (set_attr "mode" "V2DF")])
1103 (define_insn "avx_h<plusminus_insn>v8sf3"
1104 [(set (match_operand:V8SF 0 "register_operand" "=x")
1110 (match_operand:V8SF 1 "register_operand" "x")
1111 (parallel [(const_int 0)]))
1112 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1114 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1115 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1119 (match_operand:V8SF 2 "nonimmediate_operand" "xm")
1120 (parallel [(const_int 0)]))
1121 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1123 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1124 (vec_select:SF (match_dup 2) (parallel [(const_int 3)])))))
1128 (vec_select:SF (match_dup 1) (parallel [(const_int 4)]))
1129 (vec_select:SF (match_dup 1) (parallel [(const_int 5)])))
1131 (vec_select:SF (match_dup 1) (parallel [(const_int 6)]))
1132 (vec_select:SF (match_dup 1) (parallel [(const_int 7)]))))
1135 (vec_select:SF (match_dup 2) (parallel [(const_int 4)]))
1136 (vec_select:SF (match_dup 2) (parallel [(const_int 5)])))
1138 (vec_select:SF (match_dup 2) (parallel [(const_int 6)]))
1139 (vec_select:SF (match_dup 2) (parallel [(const_int 7)])))))))]
1141 "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1142 [(set_attr "type" "sseadd")
1143 (set_attr "prefix" "vex")
1144 (set_attr "mode" "V8SF")])
1146 (define_insn "sse3_h<plusminus_insn>v4sf3"
1147 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1152 (match_operand:V4SF 1 "register_operand" "0,x")
1153 (parallel [(const_int 0)]))
1154 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1156 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1157 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1161 (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")
1162 (parallel [(const_int 0)]))
1163 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1165 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1166 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
1169 h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}
1170 vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1171 [(set_attr "isa" "noavx,avx")
1172 (set_attr "type" "sseadd")
1173 (set_attr "atom_unit" "complex")
1174 (set_attr "prefix" "orig,vex")
1175 (set_attr "prefix_rep" "1,*")
1176 (set_attr "mode" "V4SF")])
1178 (define_expand "reduc_splus_v4df"
1179 [(match_operand:V4DF 0 "register_operand" "")
1180 (match_operand:V4DF 1 "register_operand" "")]
1183 rtx tmp = gen_reg_rtx (V4DFmode);
1184 rtx tmp2 = gen_reg_rtx (V4DFmode);
1185 emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1]));
1186 emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1)));
1187 emit_insn (gen_addv4df3 (operands[0], tmp, tmp2));
1191 (define_expand "reduc_splus_v2df"
1192 [(match_operand:V2DF 0 "register_operand" "")
1193 (match_operand:V2DF 1 "register_operand" "")]
1196 emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
1200 (define_expand "reduc_splus_v8sf"
1201 [(match_operand:V8SF 0 "register_operand" "")
1202 (match_operand:V8SF 1 "register_operand" "")]
1205 rtx tmp = gen_reg_rtx (V8SFmode);
1206 rtx tmp2 = gen_reg_rtx (V8SFmode);
1207 emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1]));
1208 emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp));
1209 emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1)));
1210 emit_insn (gen_addv8sf3 (operands[0], tmp, tmp2));
1214 (define_expand "reduc_splus_v4sf"
1215 [(match_operand:V4SF 0 "register_operand" "")
1216 (match_operand:V4SF 1 "register_operand" "")]
1221 rtx tmp = gen_reg_rtx (V4SFmode);
1222 emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
1223 emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp));
1226 ix86_expand_reduc_v4sf (gen_addv4sf3, operands[0], operands[1]);
1231 (define_expand "reduc_smax_v4sf"
1232 [(match_operand:V4SF 0 "register_operand" "")
1233 (match_operand:V4SF 1 "register_operand" "")]
1236 ix86_expand_reduc_v4sf (gen_smaxv4sf3, operands[0], operands[1]);
1240 (define_expand "reduc_smin_v4sf"
1241 [(match_operand:V4SF 0 "register_operand" "")
1242 (match_operand:V4SF 1 "register_operand" "")]
1245 ix86_expand_reduc_v4sf (gen_sminv4sf3, operands[0], operands[1]);
1249 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1251 ;; Parallel floating point comparisons
1253 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1255 (define_insn "avx_cmp<mode>3"
1256 [(set (match_operand:VF 0 "register_operand" "=x")
1258 [(match_operand:VF 1 "register_operand" "x")
1259 (match_operand:VF 2 "nonimmediate_operand" "xm")
1260 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1263 "vcmp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1264 [(set_attr "type" "ssecmp")
1265 (set_attr "length_immediate" "1")
1266 (set_attr "prefix" "vex")
1267 (set_attr "mode" "<MODE>")])
1269 (define_insn "avx_vmcmp<mode>3"
1270 [(set (match_operand:VF_128 0 "register_operand" "=x")
1273 [(match_operand:VF_128 1 "register_operand" "x")
1274 (match_operand:VF_128 2 "nonimmediate_operand" "xm")
1275 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1280 "vcmp<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1281 [(set_attr "type" "ssecmp")
1282 (set_attr "length_immediate" "1")
1283 (set_attr "prefix" "vex")
1284 (set_attr "mode" "<ssescalarmode>")])
1286 (define_insn "<sse>_maskcmp<mode>3"
1287 [(set (match_operand:VF 0 "register_operand" "=x,x")
1288 (match_operator:VF 3 "sse_comparison_operator"
1289 [(match_operand:VF 1 "register_operand" "0,x")
1290 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]))]
1293 cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
1294 vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1295 [(set_attr "isa" "noavx,avx")
1296 (set_attr "type" "ssecmp")
1297 (set_attr "length_immediate" "1")
1298 (set_attr "prefix" "orig,vex")
1299 (set_attr "mode" "<MODE>")])
1301 (define_insn "<sse>_vmmaskcmp<mode>3"
1302 [(set (match_operand:VF_128 0 "register_operand" "=x,x")
1304 (match_operator:VF_128 3 "sse_comparison_operator"
1305 [(match_operand:VF_128 1 "register_operand" "0,x")
1306 (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")])
1311 cmp%D3<ssescalarmodesuffix>\t{%2, %0|%0, %2}
1312 vcmp%D3<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1313 [(set_attr "isa" "noavx,avx")
1314 (set_attr "type" "ssecmp")
1315 (set_attr "length_immediate" "1,*")
1316 (set_attr "prefix" "orig,vex")
1317 (set_attr "mode" "<ssescalarmode>")])
1319 (define_insn "<sse>_comi"
1320 [(set (reg:CCFP FLAGS_REG)
1323 (match_operand:<ssevecmode> 0 "register_operand" "x")
1324 (parallel [(const_int 0)]))
1326 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1327 (parallel [(const_int 0)]))))]
1328 "SSE_FLOAT_MODE_P (<MODE>mode)"
1329 "%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1330 [(set_attr "type" "ssecomi")
1331 (set_attr "prefix" "maybe_vex")
1332 (set_attr "prefix_rep" "0")
1333 (set (attr "prefix_data16")
1334 (if_then_else (eq_attr "mode" "DF")
1336 (const_string "0")))
1337 (set_attr "mode" "<MODE>")])
1339 (define_insn "<sse>_ucomi"
1340 [(set (reg:CCFPU FLAGS_REG)
1343 (match_operand:<ssevecmode> 0 "register_operand" "x")
1344 (parallel [(const_int 0)]))
1346 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1347 (parallel [(const_int 0)]))))]
1348 "SSE_FLOAT_MODE_P (<MODE>mode)"
1349 "%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1350 [(set_attr "type" "ssecomi")
1351 (set_attr "prefix" "maybe_vex")
1352 (set_attr "prefix_rep" "0")
1353 (set (attr "prefix_data16")
1354 (if_then_else (eq_attr "mode" "DF")
1356 (const_string "0")))
1357 (set_attr "mode" "<MODE>")])
1359 (define_expand "vcond<mode>"
1360 [(set (match_operand:VF 0 "register_operand" "")
1362 (match_operator 3 ""
1363 [(match_operand:VF 4 "nonimmediate_operand" "")
1364 (match_operand:VF 5 "nonimmediate_operand" "")])
1365 (match_operand:VF 1 "general_operand" "")
1366 (match_operand:VF 2 "general_operand" "")))]
1369 bool ok = ix86_expand_fp_vcond (operands);
1374 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1376 ;; Parallel floating point logical operations
1378 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1380 (define_insn "<sse>_andnot<mode>3"
1381 [(set (match_operand:VF 0 "register_operand" "=x,x")
1384 (match_operand:VF 1 "register_operand" "0,x"))
1385 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
1388 static char buf[32];
1391 = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
1393 switch (which_alternative)
1396 insn = "andn%s\t{%%2, %%0|%%0, %%2}";
1399 insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
1405 snprintf (buf, sizeof (buf), insn, suffix);
1408 [(set_attr "isa" "noavx,avx")
1409 (set_attr "type" "sselog")
1410 (set_attr "prefix" "orig,vex")
1411 (set_attr "mode" "<MODE>")])
1413 (define_expand "<code><mode>3"
1414 [(set (match_operand:VF 0 "register_operand" "")
1416 (match_operand:VF 1 "nonimmediate_operand" "")
1417 (match_operand:VF 2 "nonimmediate_operand" "")))]
1419 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1421 (define_insn "*<code><mode>3"
1422 [(set (match_operand:VF 0 "register_operand" "=x,x")
1424 (match_operand:VF 1 "nonimmediate_operand" "%0,x")
1425 (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
1426 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1428 static char buf[32];
1431 = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
1433 switch (which_alternative)
1436 insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
1439 insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
1445 snprintf (buf, sizeof (buf), insn, suffix);
1448 [(set_attr "isa" "noavx,avx")
1449 (set_attr "type" "sselog")
1450 (set_attr "prefix" "orig,vex")
1451 (set_attr "mode" "<MODE>")])
1453 (define_expand "copysign<mode>3"
1456 (not:VF (match_dup 3))
1457 (match_operand:VF 1 "nonimmediate_operand" "")))
1459 (and:VF (match_dup 3)
1460 (match_operand:VF 2 "nonimmediate_operand" "")))
1461 (set (match_operand:VF 0 "register_operand" "")
1462 (ior:VF (match_dup 4) (match_dup 5)))]
1465 operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
1467 operands[4] = gen_reg_rtx (<MODE>mode);
1468 operands[5] = gen_reg_rtx (<MODE>mode);
1471 ;; Also define scalar versions. These are used for abs, neg, and
1472 ;; conditional move. Using subregs into vector modes causes register
1473 ;; allocation lossage. These patterns do not allow memory operands
1474 ;; because the native instructions read the full 128-bits.
1476 (define_insn "*andnot<mode>3"
1477 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
1480 (match_operand:MODEF 1 "register_operand" "0,x"))
1481 (match_operand:MODEF 2 "register_operand" "x,x")))]
1482 "SSE_FLOAT_MODE_P (<MODE>mode)"
1484 static char buf[32];
1487 = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "s" : "<ssemodefsuffix>";
1489 switch (which_alternative)
1492 insn = "andnp%s\t{%%2, %%0|%%0, %%2}";
1495 insn = "vandnp%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
1501 snprintf (buf, sizeof (buf), insn, suffix);
1504 [(set_attr "isa" "noavx,avx")
1505 (set_attr "type" "sselog")
1506 (set_attr "prefix" "orig,vex")
1507 (set_attr "mode" "<ssevecmode>")])
1509 (define_insn "*<code><mode>3"
1510 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
1512 (match_operand:MODEF 1 "register_operand" "%0,x")
1513 (match_operand:MODEF 2 "register_operand" "x,x")))]
1514 "SSE_FLOAT_MODE_P (<MODE>mode)"
1516 static char buf[32];
1519 = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "s" : "<ssemodefsuffix>";
1521 switch (which_alternative)
1524 insn = "<logic>p%s\t{%%2, %%0|%%0, %%2}";
1527 insn = "v<logic>p%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
1533 snprintf (buf, sizeof (buf), insn, suffix);
1536 [(set_attr "isa" "noavx,avx")
1537 (set_attr "type" "sselog")
1538 (set_attr "prefix" "orig,vex")
1539 (set_attr "mode" "<ssevecmode>")])
1541 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1543 ;; FMA4 floating point multiply/accumulate instructions. This
1544 ;; includes the scalar version of the instructions as well as the
1547 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1549 ;; In order to match (*a * *b) + *c, particularly when vectorizing, allow
1550 ;; combine to generate a multiply/add with two memory references. We then
1551 ;; split this insn, into loading up the destination register with one of the
1552 ;; memory operations. If we don't manage to split the insn, reload will
1553 ;; generate the appropriate moves. The reason this is needed, is that combine
1554 ;; has already folded one of the memory references into both the multiply and
1555 ;; add insns, and it can't generate a new pseudo. I.e.:
1556 ;; (set (reg1) (mem (addr1)))
1557 ;; (set (reg2) (mult (reg1) (mem (addr2))))
1558 ;; (set (reg3) (plus (reg2) (mem (addr3))))
1560 ;; ??? This is historic, pre-dating the gimple fma transformation.
1561 ;; We could now properly represent that only one memory operand is
1562 ;; allowed and not be penalized during optimization.
1564 ;; Intrinsic FMA operations.
1566 ;; The standard names for fma is only available with SSE math enabled.
1567 (define_expand "fma<mode>4"
1568 [(set (match_operand:FMAMODE 0 "register_operand")
1570 (match_operand:FMAMODE 1 "nonimmediate_operand")
1571 (match_operand:FMAMODE 2 "nonimmediate_operand")
1572 (match_operand:FMAMODE 3 "nonimmediate_operand")))]
1573 "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
1576 (define_expand "fms<mode>4"
1577 [(set (match_operand:FMAMODE 0 "register_operand")
1579 (match_operand:FMAMODE 1 "nonimmediate_operand")
1580 (match_operand:FMAMODE 2 "nonimmediate_operand")
1581 (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
1582 "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
1585 (define_expand "fnma<mode>4"
1586 [(set (match_operand:FMAMODE 0 "register_operand")
1588 (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
1589 (match_operand:FMAMODE 2 "nonimmediate_operand")
1590 (match_operand:FMAMODE 3 "nonimmediate_operand")))]
1591 "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
1594 (define_expand "fnms<mode>4"
1595 [(set (match_operand:FMAMODE 0 "register_operand")
1597 (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
1598 (match_operand:FMAMODE 2 "nonimmediate_operand")
1599 (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
1600 "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
1603 ;; The builtin for fma4intrin.h is not constrained by SSE math enabled.
1604 (define_expand "fma4i_fmadd_<mode>"
1605 [(set (match_operand:FMAMODE 0 "register_operand")
1607 (match_operand:FMAMODE 1 "nonimmediate_operand")
1608 (match_operand:FMAMODE 2 "nonimmediate_operand")
1609 (match_operand:FMAMODE 3 "nonimmediate_operand")))]
1610 "TARGET_FMA || TARGET_FMA4"
1613 (define_insn "*fma4i_fmadd_<mode>"
1614 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
1616 (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
1617 (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
1618 (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x")))]
1620 "vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1621 [(set_attr "type" "ssemuladd")
1622 (set_attr "mode" "<MODE>")])
1624 (define_insn "*fma4i_fmsub_<mode>"
1625 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
1627 (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
1628 (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
1630 (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
1632 "vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1633 [(set_attr "type" "ssemuladd")
1634 (set_attr "mode" "<MODE>")])
1636 (define_insn "*fma4i_fnmadd_<mode>"
1637 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
1640 (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
1641 (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
1642 (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x")))]
1644 "vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1645 [(set_attr "type" "ssemuladd")
1646 (set_attr "mode" "<MODE>")])
1648 (define_insn "*fma4i_fnmsub_<mode>"
1649 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
1652 (match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
1653 (match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
1655 (match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
1657 "vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1658 [(set_attr "type" "ssemuladd")
1659 (set_attr "mode" "<MODE>")])
1661 ;; Scalar versions of the above. Unlike ADDSS et al, these write the
1662 ;; entire destination register, with the high-order elements zeroed.
1664 (define_expand "fma4i_vmfmadd_<mode>"
1665 [(set (match_operand:SSEMODEF2P 0 "register_operand")
1666 (vec_merge:SSEMODEF2P
1668 (match_operand:SSEMODEF2P 1 "nonimmediate_operand")
1669 (match_operand:SSEMODEF2P 2 "nonimmediate_operand")
1670 (match_operand:SSEMODEF2P 3 "nonimmediate_operand"))
1675 operands[4] = CONST0_RTX (<MODE>mode);
1678 (define_insn "*fma4i_vmfmadd_<mode>"
1679 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1680 (vec_merge:SSEMODEF2P
1682 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
1683 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
1684 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
1685 (match_operand:SSEMODEF2P 4 "const0_operand" "")
1688 "vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1689 [(set_attr "type" "ssemuladd")
1690 (set_attr "mode" "<MODE>")])
1692 (define_insn "*fma4i_vmfmsub_<mode>"
1693 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1694 (vec_merge:SSEMODEF2P
1696 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
1697 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
1699 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
1700 (match_operand:SSEMODEF2P 4 "const0_operand" "")
1703 "vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1704 [(set_attr "type" "ssemuladd")
1705 (set_attr "mode" "<MODE>")])
1707 (define_insn "*fma4i_vmfnmadd_<mode>"
1708 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1709 (vec_merge:SSEMODEF2P
1712 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
1713 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
1714 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
1715 (match_operand:SSEMODEF2P 4 "const0_operand" "")
1718 "vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1719 [(set_attr "type" "ssemuladd")
1720 (set_attr "mode" "<MODE>")])
1722 (define_insn "*fma4i_vmfnmsub_<mode>"
1723 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1724 (vec_merge:SSEMODEF2P
1727 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
1728 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
1730 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
1731 (match_operand:SSEMODEF2P 4 "const0_operand" "")
1734 "vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1735 [(set_attr "type" "ssemuladd")
1736 (set_attr "mode" "<MODE>")])
1738 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1740 ;; FMA4 Parallel floating point multiply addsub and subadd operations.
1742 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1744 ;; It would be possible to represent these without the UNSPEC as
1747 ;; (fma op1 op2 op3)
1748 ;; (fma op1 op2 (neg op3))
1751 ;; But this doesn't seem useful in practice.
1753 (define_expand "fmaddsub_<mode>"
1754 [(set (match_operand:AVXMODEF2P 0 "register_operand")
1756 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand")
1757 (match_operand:AVXMODEF2P 2 "nonimmediate_operand")
1758 (match_operand:AVXMODEF2P 3 "nonimmediate_operand")]
1760 "TARGET_FMA || TARGET_FMA4"
1763 (define_insn "*fma4_fmaddsub_<mode>"
1764 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
1766 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
1767 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
1768 (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x")]
1771 "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1772 [(set_attr "type" "ssemuladd")
1773 (set_attr "mode" "<MODE>")])
1775 (define_insn "*fma4_fmsubadd_<mode>"
1776 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
1778 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
1779 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
1781 (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x"))]
1784 "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1785 [(set_attr "type" "ssemuladd")
1786 (set_attr "mode" "<MODE>")])
1788 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1790 ;; FMA3 floating point multiply/accumulate instructions.
1792 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1794 (define_insn "*fma_fmadd_<mode>"
1795 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
1797 (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x")
1798 (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
1799 (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0")))]
1802 vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1803 vfmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1804 vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1805 [(set_attr "type" "ssemuladd")
1806 (set_attr "mode" "<MODE>")])
1808 (define_insn "*fma_fmsub_<mode>"
1809 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
1811 (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x")
1812 (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
1814 (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
1817 vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1818 vfmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1819 vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1820 [(set_attr "type" "ssemuladd")
1821 (set_attr "mode" "<MODE>")])
1823 (define_insn "*fma_fmadd_<mode>"
1824 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
1827 (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
1828 (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
1829 (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0")))]
1832 vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1833 vfnmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1834 vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1835 [(set_attr "type" "ssemuladd")
1836 (set_attr "mode" "<MODE>")])
1838 (define_insn "*fma_fmsub_<mode>"
1839 [(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
1842 (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
1843 (match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
1845 (match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
1848 vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1849 vfnmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1850 vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1851 [(set_attr "type" "ssemuladd")
1852 (set_attr "mode" "<MODE>")])
1854 (define_insn "*fma_fmaddsub_<mode>"
1855 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
1857 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
1858 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
1859 (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0")]
1863 vfmaddsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1864 vfmaddsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1865 vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1866 [(set_attr "type" "ssemuladd")
1867 (set_attr "mode" "<MODE>")])
1869 (define_insn "*fma_fmsubadd_<mode>"
1870 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
1872 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
1873 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
1875 (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0"))]
1879 vfmsubadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
1880 vfmsubadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
1881 vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
1882 [(set_attr "type" "ssemuladd")
1883 (set_attr "mode" "<MODE>")])
1885 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1887 ;; Parallel single-precision floating point conversion operations
1889 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1891 (define_insn "sse_cvtpi2ps"
1892 [(set (match_operand:V4SF 0 "register_operand" "=x")
1895 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
1896 (match_operand:V4SF 1 "register_operand" "0")
1899 "cvtpi2ps\t{%2, %0|%0, %2}"
1900 [(set_attr "type" "ssecvt")
1901 (set_attr "mode" "V4SF")])
1903 (define_insn "sse_cvtps2pi"
1904 [(set (match_operand:V2SI 0 "register_operand" "=y")
1906 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
1908 (parallel [(const_int 0) (const_int 1)])))]
1910 "cvtps2pi\t{%1, %0|%0, %1}"
1911 [(set_attr "type" "ssecvt")
1912 (set_attr "unit" "mmx")
1913 (set_attr "mode" "DI")])
1915 (define_insn "sse_cvttps2pi"
1916 [(set (match_operand:V2SI 0 "register_operand" "=y")
1918 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
1919 (parallel [(const_int 0) (const_int 1)])))]
1921 "cvttps2pi\t{%1, %0|%0, %1}"
1922 [(set_attr "type" "ssecvt")
1923 (set_attr "unit" "mmx")
1924 (set_attr "prefix_rep" "0")
1925 (set_attr "mode" "SF")])
1927 (define_insn "sse_cvtsi2ss"
1928 [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
1931 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
1932 (match_operand:V4SF 1 "register_operand" "0,0,x")
1936 cvtsi2ss\t{%2, %0|%0, %2}
1937 cvtsi2ss\t{%2, %0|%0, %2}
1938 vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
1939 [(set_attr "isa" "noavx,noavx,avx")
1940 (set_attr "type" "sseicvt")
1941 (set_attr "athlon_decode" "vector,double,*")
1942 (set_attr "amdfam10_decode" "vector,double,*")
1943 (set_attr "bdver1_decode" "double,direct,*")
1944 (set_attr "prefix" "orig,orig,vex")
1945 (set_attr "mode" "SF")])
1947 (define_insn "sse_cvtsi2ssq"
1948 [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
1951 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
1952 (match_operand:V4SF 1 "register_operand" "0,0,x")
1954 "TARGET_SSE && TARGET_64BIT"
1956 cvtsi2ssq\t{%2, %0|%0, %2}
1957 cvtsi2ssq\t{%2, %0|%0, %2}
1958 vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
1959 [(set_attr "isa" "noavx,noavx,avx")
1960 (set_attr "type" "sseicvt")
1961 (set_attr "athlon_decode" "vector,double,*")
1962 (set_attr "amdfam10_decode" "vector,double,*")
1963 (set_attr "bdver1_decode" "double,direct,*")
1964 (set_attr "length_vex" "*,*,4")
1965 (set_attr "prefix_rex" "1,1,*")
1966 (set_attr "prefix" "orig,orig,vex")
1967 (set_attr "mode" "SF")])
1969 (define_insn "sse_cvtss2si"
1970 [(set (match_operand:SI 0 "register_operand" "=r,r")
1973 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
1974 (parallel [(const_int 0)]))]
1975 UNSPEC_FIX_NOTRUNC))]
1977 "%vcvtss2si\t{%1, %0|%0, %1}"
1978 [(set_attr "type" "sseicvt")
1979 (set_attr "athlon_decode" "double,vector")
1980 (set_attr "bdver1_decode" "double,double")
1981 (set_attr "prefix_rep" "1")
1982 (set_attr "prefix" "maybe_vex")
1983 (set_attr "mode" "SI")])
1985 (define_insn "sse_cvtss2si_2"
1986 [(set (match_operand:SI 0 "register_operand" "=r,r")
1987 (unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
1988 UNSPEC_FIX_NOTRUNC))]
1990 "%vcvtss2si\t{%1, %0|%0, %1}"
1991 [(set_attr "type" "sseicvt")
1992 (set_attr "athlon_decode" "double,vector")
1993 (set_attr "amdfam10_decode" "double,double")
1994 (set_attr "bdver1_decode" "double,double")
1995 (set_attr "prefix_rep" "1")
1996 (set_attr "prefix" "maybe_vex")
1997 (set_attr "mode" "SI")])
1999 (define_insn "sse_cvtss2siq"
2000 [(set (match_operand:DI 0 "register_operand" "=r,r")
2003 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2004 (parallel [(const_int 0)]))]
2005 UNSPEC_FIX_NOTRUNC))]
2006 "TARGET_SSE && TARGET_64BIT"
2007 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2008 [(set_attr "type" "sseicvt")
2009 (set_attr "athlon_decode" "double,vector")
2010 (set_attr "bdver1_decode" "double,double")
2011 (set_attr "prefix_rep" "1")
2012 (set_attr "prefix" "maybe_vex")
2013 (set_attr "mode" "DI")])
2015 (define_insn "sse_cvtss2siq_2"
2016 [(set (match_operand:DI 0 "register_operand" "=r,r")
2017 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
2018 UNSPEC_FIX_NOTRUNC))]
2019 "TARGET_SSE && TARGET_64BIT"
2020 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2021 [(set_attr "type" "sseicvt")
2022 (set_attr "athlon_decode" "double,vector")
2023 (set_attr "amdfam10_decode" "double,double")
2024 (set_attr "bdver1_decode" "double,double")
2025 (set_attr "prefix_rep" "1")
2026 (set_attr "prefix" "maybe_vex")
2027 (set_attr "mode" "DI")])
2029 (define_insn "sse_cvttss2si"
2030 [(set (match_operand:SI 0 "register_operand" "=r,r")
2033 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2034 (parallel [(const_int 0)]))))]
2036 "%vcvttss2si\t{%1, %0|%0, %1}"
2037 [(set_attr "type" "sseicvt")
2038 (set_attr "athlon_decode" "double,vector")
2039 (set_attr "amdfam10_decode" "double,double")
2040 (set_attr "bdver1_decode" "double,double")
2041 (set_attr "prefix_rep" "1")
2042 (set_attr "prefix" "maybe_vex")
2043 (set_attr "mode" "SI")])
2045 (define_insn "sse_cvttss2siq"
2046 [(set (match_operand:DI 0 "register_operand" "=r,r")
2049 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2050 (parallel [(const_int 0)]))))]
2051 "TARGET_SSE && TARGET_64BIT"
2052 "%vcvttss2si{q}\t{%1, %0|%0, %1}"
2053 [(set_attr "type" "sseicvt")
2054 (set_attr "athlon_decode" "double,vector")
2055 (set_attr "amdfam10_decode" "double,double")
2056 (set_attr "bdver1_decode" "double,double")
2057 (set_attr "prefix_rep" "1")
2058 (set_attr "prefix" "maybe_vex")
2059 (set_attr "mode" "DI")])
2061 (define_insn "avx_cvtdq2ps256"
2062 [(set (match_operand:V8SF 0 "register_operand" "=x")
2063 (float:V8SF (match_operand:V8SI 1 "nonimmediate_operand" "xm")))]
2065 "vcvtdq2ps\t{%1, %0|%0, %1}"
2066 [(set_attr "type" "ssecvt")
2067 (set_attr "prefix" "vex")
2068 (set_attr "mode" "V8SF")])
2070 (define_insn "sse2_cvtdq2ps"
2071 [(set (match_operand:V4SF 0 "register_operand" "=x")
2072 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
2074 "%vcvtdq2ps\t{%1, %0|%0, %1}"
2075 [(set_attr "type" "ssecvt")
2076 (set_attr "prefix" "maybe_vex")
2077 (set_attr "mode" "V4SF")])
2079 (define_expand "sse2_cvtudq2ps"
2081 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "")))
2083 (lt:V4SF (match_dup 5) (match_dup 3)))
2085 (and:V4SF (match_dup 6) (match_dup 4)))
2086 (set (match_operand:V4SF 0 "register_operand" "")
2087 (plus:V4SF (match_dup 5) (match_dup 7)))]
2090 REAL_VALUE_TYPE TWO32r;
2094 real_ldexp (&TWO32r, &dconst1, 32);
2095 x = const_double_from_real_value (TWO32r, SFmode);
2097 operands[3] = force_reg (V4SFmode, CONST0_RTX (V4SFmode));
2098 operands[4] = force_reg (V4SFmode,
2099 ix86_build_const_vector (V4SFmode, 1, x));
2101 for (i = 5; i < 8; i++)
2102 operands[i] = gen_reg_rtx (V4SFmode);
2105 (define_insn "avx_cvtps2dq256"
2106 [(set (match_operand:V8SI 0 "register_operand" "=x")
2107 (unspec:V8SI [(match_operand:V8SF 1 "nonimmediate_operand" "xm")]
2108 UNSPEC_FIX_NOTRUNC))]
2110 "vcvtps2dq\t{%1, %0|%0, %1}"
2111 [(set_attr "type" "ssecvt")
2112 (set_attr "prefix" "vex")
2113 (set_attr "mode" "OI")])
2115 (define_insn "sse2_cvtps2dq"
2116 [(set (match_operand:V4SI 0 "register_operand" "=x")
2117 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
2118 UNSPEC_FIX_NOTRUNC))]
2120 "%vcvtps2dq\t{%1, %0|%0, %1}"
2121 [(set_attr "type" "ssecvt")
2122 (set (attr "prefix_data16")
2124 (ne (symbol_ref "TARGET_AVX") (const_int 0))
2126 (const_string "1")))
2127 (set_attr "prefix" "maybe_vex")
2128 (set_attr "mode" "TI")])
2130 (define_insn "avx_cvttps2dq256"
2131 [(set (match_operand:V8SI 0 "register_operand" "=x")
2132 (fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
2134 "vcvttps2dq\t{%1, %0|%0, %1}"
2135 [(set_attr "type" "ssecvt")
2136 (set_attr "prefix" "vex")
2137 (set_attr "mode" "OI")])
2139 (define_insn "sse2_cvttps2dq"
2140 [(set (match_operand:V4SI 0 "register_operand" "=x")
2141 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
2143 "%vcvttps2dq\t{%1, %0|%0, %1}"
2144 [(set_attr "type" "ssecvt")
2145 (set (attr "prefix_rep")
2147 (ne (symbol_ref "TARGET_AVX") (const_int 0))
2149 (const_string "1")))
2150 (set (attr "prefix_data16")
2152 (ne (symbol_ref "TARGET_AVX") (const_int 0))
2154 (const_string "0")))
2155 (set_attr "prefix_data16" "0")
2156 (set_attr "prefix" "maybe_vex")
2157 (set_attr "mode" "TI")])
2159 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2161 ;; Parallel double-precision floating point conversion operations
2163 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2165 (define_insn "sse2_cvtpi2pd"
2166 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2167 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "y,m")))]
2169 "cvtpi2pd\t{%1, %0|%0, %1}"
2170 [(set_attr "type" "ssecvt")
2171 (set_attr "unit" "mmx,*")
2172 (set_attr "prefix_data16" "1,*")
2173 (set_attr "mode" "V2DF")])
2175 (define_insn "sse2_cvtpd2pi"
2176 [(set (match_operand:V2SI 0 "register_operand" "=y")
2177 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
2178 UNSPEC_FIX_NOTRUNC))]
2180 "cvtpd2pi\t{%1, %0|%0, %1}"
2181 [(set_attr "type" "ssecvt")
2182 (set_attr "unit" "mmx")
2183 (set_attr "bdver1_decode" "double")
2184 (set_attr "prefix_data16" "1")
2185 (set_attr "mode" "DI")])
2187 (define_insn "sse2_cvttpd2pi"
2188 [(set (match_operand:V2SI 0 "register_operand" "=y")
2189 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
2191 "cvttpd2pi\t{%1, %0|%0, %1}"
2192 [(set_attr "type" "ssecvt")
2193 (set_attr "unit" "mmx")
2194 (set_attr "bdver1_decode" "double")
2195 (set_attr "prefix_data16" "1")
2196 (set_attr "mode" "TI")])
2198 (define_insn "sse2_cvtsi2sd"
2199 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
2202 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
2203 (match_operand:V2DF 1 "register_operand" "0,0,x")
2207 cvtsi2sd\t{%2, %0|%0, %2}
2208 cvtsi2sd\t{%2, %0|%0, %2}
2209 vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
2210 [(set_attr "isa" "noavx,noavx,avx")
2211 (set_attr "type" "sseicvt")
2212 (set_attr "athlon_decode" "double,direct,*")
2213 (set_attr "amdfam10_decode" "vector,double,*")
2214 (set_attr "bdver1_decode" "double,direct,*")
2215 (set_attr "prefix" "orig,orig,vex")
2216 (set_attr "mode" "DF")])
2218 (define_insn "sse2_cvtsi2sdq"
2219 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
2222 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
2223 (match_operand:V2DF 1 "register_operand" "0,0,x")
2225 "TARGET_SSE2 && TARGET_64BIT"
2227 cvtsi2sdq\t{%2, %0|%0, %2}
2228 cvtsi2sdq\t{%2, %0|%0, %2}
2229 vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
2230 [(set_attr "isa" "noavx,noavx,avx")
2231 (set_attr "type" "sseicvt")
2232 (set_attr "athlon_decode" "double,direct,*")
2233 (set_attr "amdfam10_decode" "vector,double,*")
2234 (set_attr "bdver1_decode" "double,direct,*")
2235 (set_attr "length_vex" "*,*,4")
2236 (set_attr "prefix_rex" "1,1,*")
2237 (set_attr "prefix" "orig,orig,vex")
2238 (set_attr "mode" "DF")])
2240 (define_insn "sse2_cvtsd2si"
2241 [(set (match_operand:SI 0 "register_operand" "=r,r")
2244 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2245 (parallel [(const_int 0)]))]
2246 UNSPEC_FIX_NOTRUNC))]
2248 "%vcvtsd2si\t{%1, %0|%0, %1}"
2249 [(set_attr "type" "sseicvt")
2250 (set_attr "athlon_decode" "double,vector")
2251 (set_attr "bdver1_decode" "double,double")
2252 (set_attr "prefix_rep" "1")
2253 (set_attr "prefix" "maybe_vex")
2254 (set_attr "mode" "SI")])
2256 (define_insn "sse2_cvtsd2si_2"
2257 [(set (match_operand:SI 0 "register_operand" "=r,r")
2258 (unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
2259 UNSPEC_FIX_NOTRUNC))]
2261 "%vcvtsd2si\t{%1, %0|%0, %1}"
2262 [(set_attr "type" "sseicvt")
2263 (set_attr "athlon_decode" "double,vector")
2264 (set_attr "amdfam10_decode" "double,double")
2265 (set_attr "bdver1_decode" "double,double")
2266 (set_attr "prefix_rep" "1")
2267 (set_attr "prefix" "maybe_vex")
2268 (set_attr "mode" "SI")])
2270 (define_insn "sse2_cvtsd2siq"
2271 [(set (match_operand:DI 0 "register_operand" "=r,r")
2274 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2275 (parallel [(const_int 0)]))]
2276 UNSPEC_FIX_NOTRUNC))]
2277 "TARGET_SSE2 && TARGET_64BIT"
2278 "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
2279 [(set_attr "type" "sseicvt")
2280 (set_attr "athlon_decode" "double,vector")
2281 (set_attr "bdver1_decode" "double,double")
2282 (set_attr "prefix_rep" "1")
2283 (set_attr "prefix" "maybe_vex")
2284 (set_attr "mode" "DI")])
2286 (define_insn "sse2_cvtsd2siq_2"
2287 [(set (match_operand:DI 0 "register_operand" "=r,r")
2288 (unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
2289 UNSPEC_FIX_NOTRUNC))]
2290 "TARGET_SSE2 && TARGET_64BIT"
2291 "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
2292 [(set_attr "type" "sseicvt")
2293 (set_attr "athlon_decode" "double,vector")
2294 (set_attr "amdfam10_decode" "double,double")
2295 (set_attr "bdver1_decode" "double,double")
2296 (set_attr "prefix_rep" "1")
2297 (set_attr "prefix" "maybe_vex")
2298 (set_attr "mode" "DI")])
2300 (define_insn "sse2_cvttsd2si"
2301 [(set (match_operand:SI 0 "register_operand" "=r,r")
2304 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2305 (parallel [(const_int 0)]))))]
2307 "%vcvttsd2si\t{%1, %0|%0, %1}"
2308 [(set_attr "type" "sseicvt")
2309 (set_attr "athlon_decode" "double,vector")
2310 (set_attr "amdfam10_decode" "double,double")
2311 (set_attr "bdver1_decode" "double,double")
2312 (set_attr "prefix_rep" "1")
2313 (set_attr "prefix" "maybe_vex")
2314 (set_attr "mode" "SI")])
2316 (define_insn "sse2_cvttsd2siq"
2317 [(set (match_operand:DI 0 "register_operand" "=r,r")
2320 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2321 (parallel [(const_int 0)]))))]
2322 "TARGET_SSE2 && TARGET_64BIT"
2323 "%vcvttsd2si{q}\t{%1, %0|%0, %1}"
2324 [(set_attr "type" "sseicvt")
2325 (set_attr "athlon_decode" "double,vector")
2326 (set_attr "amdfam10_decode" "double,double")
2327 (set_attr "bdver1_decode" "double,double")
2328 (set_attr "prefix_rep" "1")
2329 (set_attr "prefix" "maybe_vex")
2330 (set_attr "mode" "DI")])
2332 (define_insn "avx_cvtdq2pd256"
2333 [(set (match_operand:V4DF 0 "register_operand" "=x")
2334 (float:V4DF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
2336 "vcvtdq2pd\t{%1, %0|%0, %1}"
2337 [(set_attr "type" "ssecvt")
2338 (set_attr "prefix" "vex")
2339 (set_attr "mode" "V4DF")])
2341 (define_insn "*avx_cvtdq2pd256_2"
2342 [(set (match_operand:V4DF 0 "register_operand" "=x")
2345 (match_operand:V8SI 1 "nonimmediate_operand" "xm")
2346 (parallel [(const_int 0) (const_int 1)
2347 (const_int 2) (const_int 3)]))))]
2349 "vcvtdq2pd\t{%x1, %0|%0, %x1}"
2350 [(set_attr "type" "ssecvt")
2351 (set_attr "prefix" "vex")
2352 (set_attr "mode" "V4DF")])
2354 (define_insn "sse2_cvtdq2pd"
2355 [(set (match_operand:V2DF 0 "register_operand" "=x")
2358 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
2359 (parallel [(const_int 0) (const_int 1)]))))]
2361 "%vcvtdq2pd\t{%1, %0|%0, %1}"
2362 [(set_attr "type" "ssecvt")
2363 (set_attr "prefix" "maybe_vex")
2364 (set_attr "mode" "V2DF")])
2366 (define_insn "avx_cvtpd2dq256"
2367 [(set (match_operand:V4SI 0 "register_operand" "=x")
2368 (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
2369 UNSPEC_FIX_NOTRUNC))]
2371 "vcvtpd2dq{y}\t{%1, %0|%0, %1}"
2372 [(set_attr "type" "ssecvt")
2373 (set_attr "prefix" "vex")
2374 (set_attr "mode" "OI")])
2376 (define_expand "sse2_cvtpd2dq"
2377 [(set (match_operand:V4SI 0 "register_operand" "")
2379 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
2383 "operands[2] = CONST0_RTX (V2SImode);")
2385 (define_insn "*sse2_cvtpd2dq"
2386 [(set (match_operand:V4SI 0 "register_operand" "=x")
2388 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
2390 (match_operand:V2SI 2 "const0_operand" "")))]
2394 return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
2396 return "cvtpd2dq\t{%1, %0|%0, %1}";
2398 [(set_attr "type" "ssecvt")
2399 (set_attr "prefix_rep" "1")
2400 (set_attr "prefix_data16" "0")
2401 (set_attr "prefix" "maybe_vex")
2402 (set_attr "mode" "TI")
2403 (set_attr "amdfam10_decode" "double")
2404 (set_attr "athlon_decode" "vector")
2405 (set_attr "bdver1_decode" "double")])
2407 (define_insn "avx_cvttpd2dq256"
2408 [(set (match_operand:V4SI 0 "register_operand" "=x")
2409 (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
2411 "vcvttpd2dq{y}\t{%1, %0|%0, %1}"
2412 [(set_attr "type" "ssecvt")
2413 (set_attr "prefix" "vex")
2414 (set_attr "mode" "OI")])
2416 (define_expand "sse2_cvttpd2dq"
2417 [(set (match_operand:V4SI 0 "register_operand" "")
2419 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
2422 "operands[2] = CONST0_RTX (V2SImode);")
2424 (define_insn "*sse2_cvttpd2dq"
2425 [(set (match_operand:V4SI 0 "register_operand" "=x")
2427 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2428 (match_operand:V2SI 2 "const0_operand" "")))]
2432 return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
2434 return "cvttpd2dq\t{%1, %0|%0, %1}";
2436 [(set_attr "type" "ssecvt")
2437 (set_attr "amdfam10_decode" "double")
2438 (set_attr "athlon_decode" "vector")
2439 (set_attr "bdver1_decode" "double")
2440 (set_attr "prefix" "maybe_vex")
2441 (set_attr "mode" "TI")])
2443 (define_insn "sse2_cvtsd2ss"
2444 [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
2447 (float_truncate:V2SF
2448 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,xm")))
2449 (match_operand:V4SF 1 "register_operand" "0,0,x")
2453 cvtsd2ss\t{%2, %0|%0, %2}
2454 cvtsd2ss\t{%2, %0|%0, %2}
2455 vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
2456 [(set_attr "isa" "noavx,noavx,avx")
2457 (set_attr "type" "ssecvt")
2458 (set_attr "athlon_decode" "vector,double,*")
2459 (set_attr "amdfam10_decode" "vector,double,*")
2460 (set_attr "bdver1_decode" "direct,direct,*")
2461 (set_attr "prefix" "orig,orig,vex")
2462 (set_attr "mode" "SF")])
2464 (define_insn "sse2_cvtss2sd"
2465 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
2469 (match_operand:V4SF 2 "nonimmediate_operand" "x,m,xm")
2470 (parallel [(const_int 0) (const_int 1)])))
2471 (match_operand:V2DF 1 "register_operand" "0,0,x")
2475 cvtss2sd\t{%2, %0|%0, %2}
2476 cvtss2sd\t{%2, %0|%0, %2}
2477 vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
2478 [(set_attr "isa" "noavx,noavx,avx")
2479 (set_attr "type" "ssecvt")
2480 (set_attr "amdfam10_decode" "vector,double,*")
2481 (set_attr "athlon_decode" "direct,direct,*")
2482 (set_attr "bdver1_decode" "direct,direct,*")
2483 (set_attr "prefix" "orig,orig,vex")
2484 (set_attr "mode" "DF")])
2486 (define_insn "avx_cvtpd2ps256"
2487 [(set (match_operand:V4SF 0 "register_operand" "=x")
2488 (float_truncate:V4SF
2489 (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
2491 "vcvtpd2ps{y}\t{%1, %0|%0, %1}"
2492 [(set_attr "type" "ssecvt")
2493 (set_attr "prefix" "vex")
2494 (set_attr "mode" "V4SF")])
2496 (define_expand "sse2_cvtpd2ps"
2497 [(set (match_operand:V4SF 0 "register_operand" "")
2499 (float_truncate:V2SF
2500 (match_operand:V2DF 1 "nonimmediate_operand" ""))
2503 "operands[2] = CONST0_RTX (V2SFmode);")
2505 (define_insn "*sse2_cvtpd2ps"
2506 [(set (match_operand:V4SF 0 "register_operand" "=x")
2508 (float_truncate:V2SF
2509 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2510 (match_operand:V2SF 2 "const0_operand" "")))]
2514 return "vcvtpd2ps{x}\t{%1, %0|%0, %1}";
2516 return "cvtpd2ps\t{%1, %0|%0, %1}";
2518 [(set_attr "type" "ssecvt")
2519 (set_attr "amdfam10_decode" "double")
2520 (set_attr "athlon_decode" "vector")
2521 (set_attr "bdver1_decode" "double")
2522 (set_attr "prefix_data16" "1")
2523 (set_attr "prefix" "maybe_vex")
2524 (set_attr "mode" "V4SF")])
2526 (define_insn "avx_cvtps2pd256"
2527 [(set (match_operand:V4DF 0 "register_operand" "=x")
2529 (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
2531 "vcvtps2pd\t{%1, %0|%0, %1}"
2532 [(set_attr "type" "ssecvt")
2533 (set_attr "prefix" "vex")
2534 (set_attr "mode" "V4DF")])
2536 (define_insn "*avx_cvtps2pd256_2"
2537 [(set (match_operand:V4DF 0 "register_operand" "=x")
2540 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
2541 (parallel [(const_int 0) (const_int 1)
2542 (const_int 2) (const_int 3)]))))]
2544 "vcvtps2pd\t{%x1, %0|%0, %x1}"
2545 [(set_attr "type" "ssecvt")
2546 (set_attr "prefix" "vex")
2547 (set_attr "mode" "V4DF")])
2549 (define_insn "sse2_cvtps2pd"
2550 [(set (match_operand:V2DF 0 "register_operand" "=x")
2553 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2554 (parallel [(const_int 0) (const_int 1)]))))]
2556 "%vcvtps2pd\t{%1, %0|%0, %1}"
2557 [(set_attr "type" "ssecvt")
2558 (set_attr "amdfam10_decode" "direct")
2559 (set_attr "athlon_decode" "double")
2560 (set_attr "bdver1_decode" "double")
2561 (set_attr "prefix_data16" "0")
2562 (set_attr "prefix" "maybe_vex")
2563 (set_attr "mode" "V2DF")])
2565 (define_expand "vec_unpacks_hi_v4sf"
2570 (match_operand:V4SF 1 "nonimmediate_operand" ""))
2571 (parallel [(const_int 6) (const_int 7)
2572 (const_int 2) (const_int 3)])))
2573 (set (match_operand:V2DF 0 "register_operand" "")
2577 (parallel [(const_int 0) (const_int 1)]))))]
2579 "operands[2] = gen_reg_rtx (V4SFmode);")
2581 (define_expand "vec_unpacks_hi_v8sf"
2584 (match_operand:V8SF 1 "nonimmediate_operand" "")
2585 (parallel [(const_int 4) (const_int 5)
2586 (const_int 6) (const_int 7)])))
2587 (set (match_operand:V4DF 0 "register_operand" "")
2591 "operands[2] = gen_reg_rtx (V4SFmode);")
2593 (define_expand "vec_unpacks_lo_v4sf"
2594 [(set (match_operand:V2DF 0 "register_operand" "")
2597 (match_operand:V4SF 1 "nonimmediate_operand" "")
2598 (parallel [(const_int 0) (const_int 1)]))))]
2601 (define_expand "vec_unpacks_lo_v8sf"
2602 [(set (match_operand:V4DF 0 "register_operand" "")
2605 (match_operand:V8SF 1 "nonimmediate_operand" "")
2606 (parallel [(const_int 0) (const_int 1)
2607 (const_int 2) (const_int 3)]))))]
2610 (define_expand "vec_unpacks_float_hi_v8hi"
2611 [(match_operand:V4SF 0 "register_operand" "")
2612 (match_operand:V8HI 1 "register_operand" "")]
2615 rtx tmp = gen_reg_rtx (V4SImode);
2617 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
2618 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2622 (define_expand "vec_unpacks_float_lo_v8hi"
2623 [(match_operand:V4SF 0 "register_operand" "")
2624 (match_operand:V8HI 1 "register_operand" "")]
2627 rtx tmp = gen_reg_rtx (V4SImode);
2629 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
2630 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2634 (define_expand "vec_unpacku_float_hi_v8hi"
2635 [(match_operand:V4SF 0 "register_operand" "")
2636 (match_operand:V8HI 1 "register_operand" "")]
2639 rtx tmp = gen_reg_rtx (V4SImode);
2641 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
2642 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2646 (define_expand "vec_unpacku_float_lo_v8hi"
2647 [(match_operand:V4SF 0 "register_operand" "")
2648 (match_operand:V8HI 1 "register_operand" "")]
2651 rtx tmp = gen_reg_rtx (V4SImode);
2653 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
2654 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2658 (define_expand "vec_unpacks_float_hi_v4si"
2661 (match_operand:V4SI 1 "nonimmediate_operand" "")
2662 (parallel [(const_int 2) (const_int 3)
2663 (const_int 2) (const_int 3)])))
2664 (set (match_operand:V2DF 0 "register_operand" "")
2668 (parallel [(const_int 0) (const_int 1)]))))]
2670 "operands[2] = gen_reg_rtx (V4SImode);")
2672 (define_expand "vec_unpacks_float_lo_v4si"
2673 [(set (match_operand:V2DF 0 "register_operand" "")
2676 (match_operand:V4SI 1 "nonimmediate_operand" "")
2677 (parallel [(const_int 0) (const_int 1)]))))]
2680 (define_expand "vec_unpacks_float_hi_v8si"
2683 (match_operand:V8SI 1 "nonimmediate_operand" "")
2684 (parallel [(const_int 4) (const_int 5)
2685 (const_int 6) (const_int 7)])))
2686 (set (match_operand:V4DF 0 "register_operand" "")
2690 "operands[2] = gen_reg_rtx (V4SImode);")
2692 (define_expand "vec_unpacks_float_lo_v8si"
2693 [(set (match_operand:V4DF 0 "register_operand" "")
2696 (match_operand:V8SI 1 "nonimmediate_operand" "")
2697 (parallel [(const_int 0) (const_int 1)
2698 (const_int 2) (const_int 3)]))))]
2701 (define_expand "vec_unpacku_float_hi_v4si"
2704 (match_operand:V4SI 1 "nonimmediate_operand" "")
2705 (parallel [(const_int 2) (const_int 3)
2706 (const_int 2) (const_int 3)])))
2711 (parallel [(const_int 0) (const_int 1)]))))
2713 (lt:V2DF (match_dup 6) (match_dup 3)))
2715 (and:V2DF (match_dup 7) (match_dup 4)))
2716 (set (match_operand:V2DF 0 "register_operand" "")
2717 (plus:V2DF (match_dup 6) (match_dup 8)))]
2720 REAL_VALUE_TYPE TWO32r;
2724 real_ldexp (&TWO32r, &dconst1, 32);
2725 x = const_double_from_real_value (TWO32r, DFmode);
2727 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
2728 operands[4] = force_reg (V2DFmode,
2729 ix86_build_const_vector (V2DFmode, 1, x));
2731 operands[5] = gen_reg_rtx (V4SImode);
2733 for (i = 6; i < 9; i++)
2734 operands[i] = gen_reg_rtx (V2DFmode);
2737 (define_expand "vec_unpacku_float_lo_v4si"
2741 (match_operand:V4SI 1 "nonimmediate_operand" "")
2742 (parallel [(const_int 0) (const_int 1)]))))
2744 (lt:V2DF (match_dup 5) (match_dup 3)))
2746 (and:V2DF (match_dup 6) (match_dup 4)))
2747 (set (match_operand:V2DF 0 "register_operand" "")
2748 (plus:V2DF (match_dup 5) (match_dup 7)))]
2751 REAL_VALUE_TYPE TWO32r;
2755 real_ldexp (&TWO32r, &dconst1, 32);
2756 x = const_double_from_real_value (TWO32r, DFmode);
2758 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
2759 operands[4] = force_reg (V2DFmode,
2760 ix86_build_const_vector (V2DFmode, 1, x));
2762 for (i = 5; i < 8; i++)
2763 operands[i] = gen_reg_rtx (V2DFmode);
2766 (define_expand "vec_pack_trunc_v4df"
2768 (float_truncate:V4SF
2769 (match_operand:V4DF 1 "nonimmediate_operand" "")))
2771 (float_truncate:V4SF
2772 (match_operand:V4DF 2 "nonimmediate_operand" "")))
2773 (set (match_operand:V8SF 0 "register_operand" "")
2779 operands[3] = gen_reg_rtx (V4SFmode);
2780 operands[4] = gen_reg_rtx (V4SFmode);
2783 (define_expand "vec_pack_trunc_v2df"
2784 [(match_operand:V4SF 0 "register_operand" "")
2785 (match_operand:V2DF 1 "nonimmediate_operand" "")
2786 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2791 r1 = gen_reg_rtx (V4SFmode);
2792 r2 = gen_reg_rtx (V4SFmode);
2794 emit_insn (gen_sse2_cvtpd2ps (r1, operands[1]));
2795 emit_insn (gen_sse2_cvtpd2ps (r2, operands[2]));
2796 emit_insn (gen_sse_movlhps (operands[0], r1, r2));
2800 (define_expand "vec_pack_sfix_trunc_v2df"
2801 [(match_operand:V4SI 0 "register_operand" "")
2802 (match_operand:V2DF 1 "nonimmediate_operand" "")
2803 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2808 r1 = gen_reg_rtx (V4SImode);
2809 r2 = gen_reg_rtx (V4SImode);
2811 emit_insn (gen_sse2_cvttpd2dq (r1, operands[1]));
2812 emit_insn (gen_sse2_cvttpd2dq (r2, operands[2]));
2813 emit_insn (gen_vec_interleave_lowv2di (gen_lowpart (V2DImode, operands[0]),
2814 gen_lowpart (V2DImode, r1),
2815 gen_lowpart (V2DImode, r2)));
2819 (define_expand "vec_pack_sfix_v2df"
2820 [(match_operand:V4SI 0 "register_operand" "")
2821 (match_operand:V2DF 1 "nonimmediate_operand" "")
2822 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2827 r1 = gen_reg_rtx (V4SImode);
2828 r2 = gen_reg_rtx (V4SImode);
2830 emit_insn (gen_sse2_cvtpd2dq (r1, operands[1]));
2831 emit_insn (gen_sse2_cvtpd2dq (r2, operands[2]));
2832 emit_insn (gen_vec_interleave_lowv2di (gen_lowpart (V2DImode, operands[0]),
2833 gen_lowpart (V2DImode, r1),
2834 gen_lowpart (V2DImode, r2)));
2838 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2840 ;; Parallel single-precision floating point element swizzling
2842 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2844 (define_expand "sse_movhlps_exp"
2845 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2848 (match_operand:V4SF 1 "nonimmediate_operand" "")
2849 (match_operand:V4SF 2 "nonimmediate_operand" ""))
2850 (parallel [(const_int 6)
2856 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
2858 emit_insn (gen_sse_movhlps (dst, operands[1], operands[2]));
2860 /* Fix up the destination if needed. */
2861 if (dst != operands[0])
2862 emit_move_insn (operands[0], dst);
2867 (define_insn "*avx_movhlps"
2868 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
2871 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
2872 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
2873 (parallel [(const_int 6)
2877 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
2879 vmovhlps\t{%2, %1, %0|%0, %1, %2}
2880 vmovlps\t{%H2, %1, %0|%0, %1, %H2}
2881 vmovhps\t{%2, %0|%0, %2}"
2882 [(set_attr "type" "ssemov")
2883 (set_attr "prefix" "vex")
2884 (set_attr "mode" "V4SF,V2SF,V2SF")])
2886 (define_insn "sse_movhlps"
2887 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
2890 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
2891 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
2892 (parallel [(const_int 6)
2896 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
2898 movhlps\t{%2, %0|%0, %2}
2899 movlps\t{%H2, %0|%0, %H2}
2900 movhps\t{%2, %0|%0, %2}"
2901 [(set_attr "type" "ssemov")
2902 (set_attr "mode" "V4SF,V2SF,V2SF")])
2904 (define_expand "sse_movlhps_exp"
2905 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2908 (match_operand:V4SF 1 "nonimmediate_operand" "")
2909 (match_operand:V4SF 2 "nonimmediate_operand" ""))
2910 (parallel [(const_int 0)
2916 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
2918 emit_insn (gen_sse_movlhps (dst, operands[1], operands[2]));
2920 /* Fix up the destination if needed. */
2921 if (dst != operands[0])
2922 emit_move_insn (operands[0], dst);
2927 (define_insn "*avx_movlhps"
2928 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2931 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
2932 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
2933 (parallel [(const_int 0)
2937 "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
2939 vmovlhps\t{%2, %1, %0|%0, %1, %2}
2940 vmovhps\t{%2, %1, %0|%0, %1, %2}
2941 vmovlps\t{%2, %H0|%H0, %2}"
2942 [(set_attr "type" "ssemov")
2943 (set_attr "prefix" "vex")
2944 (set_attr "mode" "V4SF,V2SF,V2SF")])
2946 (define_insn "sse_movlhps"
2947 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2950 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
2951 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
2952 (parallel [(const_int 0)
2956 "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
2958 movlhps\t{%2, %0|%0, %2}
2959 movhps\t{%2, %0|%0, %2}
2960 movlps\t{%2, %H0|%H0, %2}"
2961 [(set_attr "type" "ssemov")
2962 (set_attr "mode" "V4SF,V2SF,V2SF")])
2964 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
2965 (define_insn "avx_unpckhps256"
2966 [(set (match_operand:V8SF 0 "register_operand" "=x")
2969 (match_operand:V8SF 1 "register_operand" "x")
2970 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
2971 (parallel [(const_int 2) (const_int 10)
2972 (const_int 3) (const_int 11)
2973 (const_int 6) (const_int 14)
2974 (const_int 7) (const_int 15)])))]
2976 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
2977 [(set_attr "type" "sselog")
2978 (set_attr "prefix" "vex")
2979 (set_attr "mode" "V8SF")])
2981 (define_insn "*avx_interleave_highv4sf"
2982 [(set (match_operand:V4SF 0 "register_operand" "=x")
2985 (match_operand:V4SF 1 "register_operand" "x")
2986 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
2987 (parallel [(const_int 2) (const_int 6)
2988 (const_int 3) (const_int 7)])))]
2990 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
2991 [(set_attr "type" "sselog")
2992 (set_attr "prefix" "vex")
2993 (set_attr "mode" "V4SF")])
2995 (define_expand "vec_interleave_highv8sf"
2999 (match_operand:V8SF 1 "register_operand" "x")
3000 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3001 (parallel [(const_int 0) (const_int 8)
3002 (const_int 1) (const_int 9)
3003 (const_int 4) (const_int 12)
3004 (const_int 5) (const_int 13)])))
3010 (parallel [(const_int 2) (const_int 10)
3011 (const_int 3) (const_int 11)
3012 (const_int 6) (const_int 14)
3013 (const_int 7) (const_int 15)])))
3014 (set (match_operand:V8SF 0 "register_operand" "")
3019 (parallel [(const_int 4) (const_int 5)
3020 (const_int 6) (const_int 7)
3021 (const_int 12) (const_int 13)
3022 (const_int 14) (const_int 15)])))]
3025 operands[3] = gen_reg_rtx (V8SFmode);
3026 operands[4] = gen_reg_rtx (V8SFmode);
3029 (define_insn "vec_interleave_highv4sf"
3030 [(set (match_operand:V4SF 0 "register_operand" "=x")
3033 (match_operand:V4SF 1 "register_operand" "0")
3034 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3035 (parallel [(const_int 2) (const_int 6)
3036 (const_int 3) (const_int 7)])))]
3038 "unpckhps\t{%2, %0|%0, %2}"
3039 [(set_attr "type" "sselog")
3040 (set_attr "mode" "V4SF")])
3042 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
3043 (define_insn "avx_unpcklps256"
3044 [(set (match_operand:V8SF 0 "register_operand" "=x")
3047 (match_operand:V8SF 1 "register_operand" "x")
3048 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3049 (parallel [(const_int 0) (const_int 8)
3050 (const_int 1) (const_int 9)
3051 (const_int 4) (const_int 12)
3052 (const_int 5) (const_int 13)])))]
3054 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
3055 [(set_attr "type" "sselog")
3056 (set_attr "prefix" "vex")
3057 (set_attr "mode" "V8SF")])
3059 (define_insn "*avx_interleave_lowv4sf"
3060 [(set (match_operand:V4SF 0 "register_operand" "=x")
3063 (match_operand:V4SF 1 "register_operand" "x")
3064 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3065 (parallel [(const_int 0) (const_int 4)
3066 (const_int 1) (const_int 5)])))]
3068 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
3069 [(set_attr "type" "sselog")
3070 (set_attr "prefix" "vex")
3071 (set_attr "mode" "V4SF")])
3073 (define_expand "vec_interleave_lowv8sf"
3077 (match_operand:V8SF 1 "register_operand" "x")
3078 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3079 (parallel [(const_int 0) (const_int 8)
3080 (const_int 1) (const_int 9)
3081 (const_int 4) (const_int 12)
3082 (const_int 5) (const_int 13)])))
3088 (parallel [(const_int 2) (const_int 10)
3089 (const_int 3) (const_int 11)
3090 (const_int 6) (const_int 14)
3091 (const_int 7) (const_int 15)])))
3092 (set (match_operand:V8SF 0 "register_operand" "")
3097 (parallel [(const_int 0) (const_int 1)
3098 (const_int 2) (const_int 3)
3099 (const_int 8) (const_int 9)
3100 (const_int 10) (const_int 11)])))]
3103 operands[3] = gen_reg_rtx (V8SFmode);
3104 operands[4] = gen_reg_rtx (V8SFmode);
3107 (define_insn "vec_interleave_lowv4sf"
3108 [(set (match_operand:V4SF 0 "register_operand" "=x")
3111 (match_operand:V4SF 1 "register_operand" "0")
3112 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3113 (parallel [(const_int 0) (const_int 4)
3114 (const_int 1) (const_int 5)])))]
3116 "unpcklps\t{%2, %0|%0, %2}"
3117 [(set_attr "type" "sselog")
3118 (set_attr "mode" "V4SF")])
3120 ;; These are modeled with the same vec_concat as the others so that we
3121 ;; capture users of shufps that can use the new instructions
3122 (define_insn "avx_movshdup256"
3123 [(set (match_operand:V8SF 0 "register_operand" "=x")
3126 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
3128 (parallel [(const_int 1) (const_int 1)
3129 (const_int 3) (const_int 3)
3130 (const_int 5) (const_int 5)
3131 (const_int 7) (const_int 7)])))]
3133 "vmovshdup\t{%1, %0|%0, %1}"
3134 [(set_attr "type" "sse")
3135 (set_attr "prefix" "vex")
3136 (set_attr "mode" "V8SF")])
3138 (define_insn "sse3_movshdup"
3139 [(set (match_operand:V4SF 0 "register_operand" "=x")
3142 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
3144 (parallel [(const_int 1)
3149 "%vmovshdup\t{%1, %0|%0, %1}"
3150 [(set_attr "type" "sse")
3151 (set_attr "prefix_rep" "1")
3152 (set_attr "prefix" "maybe_vex")
3153 (set_attr "mode" "V4SF")])
3155 (define_insn "avx_movsldup256"
3156 [(set (match_operand:V8SF 0 "register_operand" "=x")
3159 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
3161 (parallel [(const_int 0) (const_int 0)
3162 (const_int 2) (const_int 2)
3163 (const_int 4) (const_int 4)
3164 (const_int 6) (const_int 6)])))]
3166 "vmovsldup\t{%1, %0|%0, %1}"
3167 [(set_attr "type" "sse")
3168 (set_attr "prefix" "vex")
3169 (set_attr "mode" "V8SF")])
3171 (define_insn "sse3_movsldup"
3172 [(set (match_operand:V4SF 0 "register_operand" "=x")
3175 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
3177 (parallel [(const_int 0)
3182 "%vmovsldup\t{%1, %0|%0, %1}"
3183 [(set_attr "type" "sse")
3184 (set_attr "prefix_rep" "1")
3185 (set_attr "prefix" "maybe_vex")
3186 (set_attr "mode" "V4SF")])
3188 (define_expand "avx_shufps256"
3189 [(match_operand:V8SF 0 "register_operand" "")
3190 (match_operand:V8SF 1 "register_operand" "")
3191 (match_operand:V8SF 2 "nonimmediate_operand" "")
3192 (match_operand:SI 3 "const_int_operand" "")]
3195 int mask = INTVAL (operands[3]);
3196 emit_insn (gen_avx_shufps256_1 (operands[0], operands[1], operands[2],
3197 GEN_INT ((mask >> 0) & 3),
3198 GEN_INT ((mask >> 2) & 3),
3199 GEN_INT (((mask >> 4) & 3) + 8),
3200 GEN_INT (((mask >> 6) & 3) + 8),
3201 GEN_INT (((mask >> 0) & 3) + 4),
3202 GEN_INT (((mask >> 2) & 3) + 4),
3203 GEN_INT (((mask >> 4) & 3) + 12),
3204 GEN_INT (((mask >> 6) & 3) + 12)));
3208 ;; One bit in mask selects 2 elements.
3209 (define_insn "avx_shufps256_1"
3210 [(set (match_operand:V8SF 0 "register_operand" "=x")
3213 (match_operand:V8SF 1 "register_operand" "x")
3214 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3215 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3216 (match_operand 4 "const_0_to_3_operand" "")
3217 (match_operand 5 "const_8_to_11_operand" "")
3218 (match_operand 6 "const_8_to_11_operand" "")
3219 (match_operand 7 "const_4_to_7_operand" "")
3220 (match_operand 8 "const_4_to_7_operand" "")
3221 (match_operand 9 "const_12_to_15_operand" "")
3222 (match_operand 10 "const_12_to_15_operand" "")])))]
3224 && (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
3225 && INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
3226 && INTVAL (operands[5]) == (INTVAL (operands[9]) - 4)
3227 && INTVAL (operands[6]) == (INTVAL (operands[10]) - 4))"
3230 mask = INTVAL (operands[3]);
3231 mask |= INTVAL (operands[4]) << 2;
3232 mask |= (INTVAL (operands[5]) - 8) << 4;
3233 mask |= (INTVAL (operands[6]) - 8) << 6;
3234 operands[3] = GEN_INT (mask);
3236 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3238 [(set_attr "type" "sselog")
3239 (set_attr "length_immediate" "1")
3240 (set_attr "prefix" "vex")
3241 (set_attr "mode" "V8SF")])
3243 (define_expand "sse_shufps"
3244 [(match_operand:V4SF 0 "register_operand" "")
3245 (match_operand:V4SF 1 "register_operand" "")
3246 (match_operand:V4SF 2 "nonimmediate_operand" "")
3247 (match_operand:SI 3 "const_int_operand" "")]
3250 int mask = INTVAL (operands[3]);
3251 emit_insn (gen_sse_shufps_v4sf (operands[0], operands[1], operands[2],
3252 GEN_INT ((mask >> 0) & 3),
3253 GEN_INT ((mask >> 2) & 3),
3254 GEN_INT (((mask >> 4) & 3) + 4),
3255 GEN_INT (((mask >> 6) & 3) + 4)));
3259 (define_insn "*avx_shufps_<mode>"
3260 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
3261 (vec_select:SSEMODE4S
3262 (vec_concat:<ssedoublesizemode>
3263 (match_operand:SSEMODE4S 1 "register_operand" "x")
3264 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
3265 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3266 (match_operand 4 "const_0_to_3_operand" "")
3267 (match_operand 5 "const_4_to_7_operand" "")
3268 (match_operand 6 "const_4_to_7_operand" "")])))]
3272 mask |= INTVAL (operands[3]) << 0;
3273 mask |= INTVAL (operands[4]) << 2;
3274 mask |= (INTVAL (operands[5]) - 4) << 4;
3275 mask |= (INTVAL (operands[6]) - 4) << 6;
3276 operands[3] = GEN_INT (mask);
3278 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3280 [(set_attr "type" "sselog")
3281 (set_attr "length_immediate" "1")
3282 (set_attr "prefix" "vex")
3283 (set_attr "mode" "V4SF")])
3285 (define_insn "sse_shufps_<mode>"
3286 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
3287 (vec_select:SSEMODE4S
3288 (vec_concat:<ssedoublesizemode>
3289 (match_operand:SSEMODE4S 1 "register_operand" "0")
3290 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
3291 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3292 (match_operand 4 "const_0_to_3_operand" "")
3293 (match_operand 5 "const_4_to_7_operand" "")
3294 (match_operand 6 "const_4_to_7_operand" "")])))]
3298 mask |= INTVAL (operands[3]) << 0;
3299 mask |= INTVAL (operands[4]) << 2;
3300 mask |= (INTVAL (operands[5]) - 4) << 4;
3301 mask |= (INTVAL (operands[6]) - 4) << 6;
3302 operands[3] = GEN_INT (mask);
3304 return "shufps\t{%3, %2, %0|%0, %2, %3}";
3306 [(set_attr "type" "sselog")
3307 (set_attr "length_immediate" "1")
3308 (set_attr "mode" "V4SF")])
3310 (define_insn "sse_storehps"
3311 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3313 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
3314 (parallel [(const_int 2) (const_int 3)])))]
3317 %vmovhps\t{%1, %0|%0, %1}
3318 %vmovhlps\t{%1, %d0|%d0, %1}
3319 %vmovlps\t{%H1, %d0|%d0, %H1}"
3320 [(set_attr "type" "ssemov")
3321 (set_attr "prefix" "maybe_vex")
3322 (set_attr "mode" "V2SF,V4SF,V2SF")])
3324 (define_expand "sse_loadhps_exp"
3325 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3328 (match_operand:V4SF 1 "nonimmediate_operand" "")
3329 (parallel [(const_int 0) (const_int 1)]))
3330 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
3333 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
3335 emit_insn (gen_sse_loadhps (dst, operands[1], operands[2]));
3337 /* Fix up the destination if needed. */
3338 if (dst != operands[0])
3339 emit_move_insn (operands[0], dst);
3344 (define_insn "*avx_loadhps"
3345 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3348 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
3349 (parallel [(const_int 0) (const_int 1)]))
3350 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
3353 vmovhps\t{%2, %1, %0|%0, %1, %2}
3354 vmovlhps\t{%2, %1, %0|%0, %1, %2}
3355 vmovlps\t{%2, %H0|%H0, %2}"
3356 [(set_attr "type" "ssemov")
3357 (set_attr "prefix" "vex")
3358 (set_attr "mode" "V2SF,V4SF,V2SF")])
3360 (define_insn "sse_loadhps"
3361 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3364 (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
3365 (parallel [(const_int 0) (const_int 1)]))
3366 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
3369 movhps\t{%2, %0|%0, %2}
3370 movlhps\t{%2, %0|%0, %2}
3371 movlps\t{%2, %H0|%H0, %2}"
3372 [(set_attr "type" "ssemov")
3373 (set_attr "mode" "V2SF,V4SF,V2SF")])
3375 (define_insn "*avx_storelps"
3376 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3378 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
3379 (parallel [(const_int 0) (const_int 1)])))]
3382 vmovlps\t{%1, %0|%0, %1}
3383 vmovaps\t{%1, %0|%0, %1}
3384 vmovlps\t{%1, %0, %0|%0, %0, %1}"
3385 [(set_attr "type" "ssemov")
3386 (set_attr "prefix" "vex")
3387 (set_attr "mode" "V2SF,V2DF,V2SF")])
3389 (define_insn "sse_storelps"
3390 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3392 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
3393 (parallel [(const_int 0) (const_int 1)])))]
3396 movlps\t{%1, %0|%0, %1}
3397 movaps\t{%1, %0|%0, %1}
3398 movlps\t{%1, %0|%0, %1}"
3399 [(set_attr "type" "ssemov")
3400 (set_attr "mode" "V2SF,V4SF,V2SF")])
3402 (define_expand "sse_loadlps_exp"
3403 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3405 (match_operand:V2SF 2 "nonimmediate_operand" "")
3407 (match_operand:V4SF 1 "nonimmediate_operand" "")
3408 (parallel [(const_int 2) (const_int 3)]))))]
3411 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
3413 emit_insn (gen_sse_loadlps (dst, operands[1], operands[2]));
3415 /* Fix up the destination if needed. */
3416 if (dst != operands[0])
3417 emit_move_insn (operands[0], dst);
3422 (define_insn "*avx_loadlps"
3423 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3425 (match_operand:V2SF 2 "nonimmediate_operand" "x,m,x")
3427 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
3428 (parallel [(const_int 2) (const_int 3)]))))]
3431 shufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
3432 vmovlps\t{%2, %1, %0|%0, %1, %2}
3433 vmovlps\t{%2, %0|%0, %2}"
3434 [(set_attr "type" "sselog,ssemov,ssemov")
3435 (set_attr "length_immediate" "1,*,*")
3436 (set_attr "prefix" "vex")
3437 (set_attr "mode" "V4SF,V2SF,V2SF")])
3439 (define_insn "sse_loadlps"
3440 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3442 (match_operand:V2SF 2 "nonimmediate_operand" "0,m,x")
3444 (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
3445 (parallel [(const_int 2) (const_int 3)]))))]
3448 shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
3449 movlps\t{%2, %0|%0, %2}
3450 movlps\t{%2, %0|%0, %2}"
3451 [(set_attr "type" "sselog,ssemov,ssemov")
3452 (set_attr "length_immediate" "1,*,*")
3453 (set_attr "mode" "V4SF,V2SF,V2SF")])
3455 (define_insn "*avx_movss"
3456 [(set (match_operand:V4SF 0 "register_operand" "=x")
3458 (match_operand:V4SF 2 "register_operand" "x")
3459 (match_operand:V4SF 1 "register_operand" "x")
3462 "vmovss\t{%2, %1, %0|%0, %1, %2}"
3463 [(set_attr "type" "ssemov")
3464 (set_attr "prefix" "vex")
3465 (set_attr "mode" "SF")])
3467 (define_insn "sse_movss"
3468 [(set (match_operand:V4SF 0 "register_operand" "=x")
3470 (match_operand:V4SF 2 "register_operand" "x")
3471 (match_operand:V4SF 1 "register_operand" "0")
3474 "movss\t{%2, %0|%0, %2}"
3475 [(set_attr "type" "ssemov")
3476 (set_attr "mode" "SF")])
3478 (define_expand "vec_dupv4sf"
3479 [(set (match_operand:V4SF 0 "register_operand" "")
3481 (match_operand:SF 1 "nonimmediate_operand" "")))]
3485 operands[1] = force_reg (V4SFmode, operands[1]);
3488 (define_insn "*vec_dupv4sf_avx"
3489 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3491 (match_operand:SF 1 "nonimmediate_operand" "x,m")))]
3494 vshufps\t{$0, %1, %1, %0|%0, %1, %1, 0}
3495 vbroadcastss\t{%1, %0|%0, %1}"
3496 [(set_attr "type" "sselog1,ssemov")
3497 (set_attr "length_immediate" "1,0")
3498 (set_attr "prefix_extra" "0,1")
3499 (set_attr "prefix" "vex")
3500 (set_attr "mode" "V4SF")])
3502 (define_insn "*vec_dupv4sf"
3503 [(set (match_operand:V4SF 0 "register_operand" "=x")
3505 (match_operand:SF 1 "register_operand" "0")))]
3507 "shufps\t{$0, %0, %0|%0, %0, 0}"
3508 [(set_attr "type" "sselog1")
3509 (set_attr "length_immediate" "1")
3510 (set_attr "mode" "V4SF")])
3512 (define_insn "*vec_concatv2sf_avx"
3513 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
3515 (match_operand:SF 1 "nonimmediate_operand" " x,x,m, x , m")
3516 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
3519 vunpcklps\t{%2, %1, %0|%0, %1, %2}
3520 vinsertps\t{$0x10, %2, %1, %0|%0, %1, %2, 0x10}
3521 vmovss\t{%1, %0|%0, %1}
3522 punpckldq\t{%2, %0|%0, %2}
3523 movd\t{%1, %0|%0, %1}"
3524 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
3525 (set_attr "length_immediate" "*,1,*,*,*")
3526 (set_attr "prefix_extra" "*,1,*,*,*")
3527 (set (attr "prefix")
3528 (if_then_else (eq_attr "alternative" "3,4")
3529 (const_string "orig")
3530 (const_string "vex")))
3531 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
3533 ;; Although insertps takes register source, we prefer
3534 ;; unpcklps with register source since it is shorter.
3535 (define_insn "*vec_concatv2sf_sse4_1"
3536 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
3538 (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0 , m")
3539 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
3542 unpcklps\t{%2, %0|%0, %2}
3543 insertps\t{$0x10, %2, %0|%0, %2, 0x10}
3544 movss\t{%1, %0|%0, %1}
3545 punpckldq\t{%2, %0|%0, %2}
3546 movd\t{%1, %0|%0, %1}"
3547 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
3548 (set_attr "prefix_data16" "*,1,*,*,*")
3549 (set_attr "prefix_extra" "*,1,*,*,*")
3550 (set_attr "length_immediate" "*,1,*,*,*")
3551 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
3553 ;; ??? In theory we can match memory for the MMX alternative, but allowing
3554 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
3555 ;; alternatives pretty much forces the MMX alternative to be chosen.
3556 (define_insn "*vec_concatv2sf_sse"
3557 [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y")
3559 (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m")
3560 (match_operand:SF 2 "reg_or_0_operand" " x,C,*y, C")))]
3563 unpcklps\t{%2, %0|%0, %2}
3564 movss\t{%1, %0|%0, %1}
3565 punpckldq\t{%2, %0|%0, %2}
3566 movd\t{%1, %0|%0, %1}"
3567 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
3568 (set_attr "mode" "V4SF,SF,DI,DI")])
3570 (define_insn "*vec_concatv4sf_avx"
3571 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3573 (match_operand:V2SF 1 "register_operand" " x,x")
3574 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
3577 vmovlhps\t{%2, %1, %0|%0, %1, %2}
3578 vmovhps\t{%2, %1, %0|%0, %1, %2}"
3579 [(set_attr "type" "ssemov")
3580 (set_attr "prefix" "vex")
3581 (set_attr "mode" "V4SF,V2SF")])
3583 (define_insn "*vec_concatv4sf_sse"
3584 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3586 (match_operand:V2SF 1 "register_operand" " 0,0")
3587 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
3590 movlhps\t{%2, %0|%0, %2}
3591 movhps\t{%2, %0|%0, %2}"
3592 [(set_attr "type" "ssemov")
3593 (set_attr "mode" "V4SF,V2SF")])
3595 (define_expand "vec_init<mode>"
3596 [(match_operand:SSEMODE 0 "register_operand" "")
3597 (match_operand 1 "" "")]
3600 ix86_expand_vector_init (false, operands[0], operands[1]);
3604 (define_insn "*vec_set<mode>_0_avx"
3605 [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m")
3606 (vec_merge:SSEMODE4S
3607 (vec_duplicate:SSEMODE4S
3608 (match_operand:<ssescalarmode> 2
3609 "general_operand" " x,m,*r,x,*rm,x*rfF"))
3610 (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,x, x,0")
3614 vinsertps\t{$0xe, %2, %2, %0|%0, %2, %2, 0xe}
3615 vmov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
3616 vmovd\t{%2, %0|%0, %2}
3617 vmovss\t{%2, %1, %0|%0, %1, %2}
3618 vpinsrd\t{$0, %2, %1, %0|%0, %1, %2, 0}
3620 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*")
3621 (set_attr "prefix_extra" "*,*,*,*,1,*")
3622 (set_attr "length_immediate" "*,*,*,*,1,*")
3623 (set_attr "prefix" "vex")
3624 (set_attr "mode" "SF,<ssescalarmode>,SI,SF,TI,*")])
3626 (define_insn "*vec_set<mode>_0_sse4_1"
3627 [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m")
3628 (vec_merge:SSEMODE4S
3629 (vec_duplicate:SSEMODE4S
3630 (match_operand:<ssescalarmode> 2
3631 "general_operand" " x,m,*r,x,*rm,*rfF"))
3632 (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,0, 0,0")
3636 insertps\t{$0xe, %2, %0|%0, %2, 0xe}
3637 mov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
3638 movd\t{%2, %0|%0, %2}
3639 movss\t{%2, %0|%0, %2}
3640 pinsrd\t{$0, %2, %0|%0, %2, 0}
3642 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*")
3643 (set_attr "prefix_extra" "*,*,*,*,1,*")
3644 (set_attr "length_immediate" "*,*,*,*,1,*")
3645 (set_attr "mode" "SF,<ssescalarmode>,SI,SF,TI,*")])
3647 (define_insn "*vec_set<mode>_0_sse2"
3648 [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x, x,x,m")
3649 (vec_merge:SSEMODE4S
3650 (vec_duplicate:SSEMODE4S
3651 (match_operand:<ssescalarmode> 2
3652 "general_operand" " m,*r,x,x*rfF"))
3653 (match_operand:SSEMODE4S 1 "vector_move_operand" " C, C,0,0")
3657 mov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
3658 movd\t{%2, %0|%0, %2}
3659 movss\t{%2, %0|%0, %2}
3661 [(set_attr "type" "ssemov")
3662 (set_attr "mode" "<ssescalarmode>,SI,SF,*")])
3664 (define_insn "vec_set<mode>_0"
3665 [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x,m")
3666 (vec_merge:SSEMODE4S
3667 (vec_duplicate:SSEMODE4S
3668 (match_operand:<ssescalarmode> 2
3669 "general_operand" " m,x,x*rfF"))
3670 (match_operand:SSEMODE4S 1 "vector_move_operand" " C,0,0")
3674 movss\t{%2, %0|%0, %2}
3675 movss\t{%2, %0|%0, %2}
3677 [(set_attr "type" "ssemov")
3678 (set_attr "mode" "SF,SF,*")])
3680 ;; A subset is vec_setv4sf.
3681 (define_insn "*vec_setv4sf_avx"
3682 [(set (match_operand:V4SF 0 "register_operand" "=x")
3685 (match_operand:SF 2 "nonimmediate_operand" "xm"))
3686 (match_operand:V4SF 1 "register_operand" "x")
3687 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
3690 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
3691 return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3693 [(set_attr "type" "sselog")
3694 (set_attr "prefix_extra" "1")
3695 (set_attr "length_immediate" "1")
3696 (set_attr "prefix" "vex")
3697 (set_attr "mode" "V4SF")])
3699 (define_insn "*vec_setv4sf_sse4_1"
3700 [(set (match_operand:V4SF 0 "register_operand" "=x")
3703 (match_operand:SF 2 "nonimmediate_operand" "xm"))
3704 (match_operand:V4SF 1 "register_operand" "0")
3705 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
3708 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
3709 return "insertps\t{%3, %2, %0|%0, %2, %3}";
3711 [(set_attr "type" "sselog")
3712 (set_attr "prefix_data16" "1")
3713 (set_attr "prefix_extra" "1")
3714 (set_attr "length_immediate" "1")
3715 (set_attr "mode" "V4SF")])
3717 (define_insn "*avx_insertps"
3718 [(set (match_operand:V4SF 0 "register_operand" "=x")
3719 (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm")
3720 (match_operand:V4SF 1 "register_operand" "x")
3721 (match_operand:SI 3 "const_0_to_255_operand" "n")]
3724 "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3725 [(set_attr "type" "sselog")
3726 (set_attr "prefix" "vex")
3727 (set_attr "prefix_extra" "1")
3728 (set_attr "length_immediate" "1")
3729 (set_attr "mode" "V4SF")])
3731 (define_insn "sse4_1_insertps"
3732 [(set (match_operand:V4SF 0 "register_operand" "=x")
3733 (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
3734 (match_operand:V4SF 1 "register_operand" "0")
3735 (match_operand:SI 3 "const_0_to_255_operand" "n")]
3738 "insertps\t{%3, %2, %0|%0, %2, %3}";
3739 [(set_attr "type" "sselog")
3740 (set_attr "prefix_data16" "1")
3741 (set_attr "prefix_extra" "1")
3742 (set_attr "length_immediate" "1")
3743 (set_attr "mode" "V4SF")])
3746 [(set (match_operand:SSEMODE4S 0 "memory_operand" "")
3747 (vec_merge:SSEMODE4S
3748 (vec_duplicate:SSEMODE4S
3749 (match_operand:<ssescalarmode> 1 "nonmemory_operand" ""))
3752 "TARGET_SSE && reload_completed"
3755 emit_move_insn (adjust_address (operands[0], <ssescalarmode>mode, 0),
3760 (define_expand "vec_set<mode>"
3761 [(match_operand:SSEMODE 0 "register_operand" "")
3762 (match_operand:<ssescalarmode> 1 "register_operand" "")
3763 (match_operand 2 "const_int_operand" "")]
3766 ix86_expand_vector_set (false, operands[0], operands[1],
3767 INTVAL (operands[2]));
3771 (define_insn_and_split "*vec_extractv4sf_0"
3772 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,m,f,r")
3774 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x,m,m")
3775 (parallel [(const_int 0)])))]
3776 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3778 "&& reload_completed"
3781 rtx op1 = operands[1];
3783 op1 = gen_rtx_REG (SFmode, REGNO (op1));
3785 op1 = gen_lowpart (SFmode, op1);
3786 emit_move_insn (operands[0], op1);
3790 (define_expand "avx_vextractf128<mode>"
3791 [(match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "")
3792 (match_operand:AVX256MODE 1 "register_operand" "")
3793 (match_operand:SI 2 "const_0_to_1_operand" "")]
3796 rtx (*insn)(rtx, rtx);
3798 switch (INTVAL (operands[2]))
3801 insn = gen_vec_extract_lo_<mode>;
3804 insn = gen_vec_extract_hi_<mode>;
3810 emit_insn (insn (operands[0], operands[1]));
3814 (define_insn_and_split "vec_extract_lo_<mode>"
3815 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3816 (vec_select:<avxhalfvecmode>
3817 (match_operand:AVX256MODE4P 1 "nonimmediate_operand" "xm,x")
3818 (parallel [(const_int 0) (const_int 1)])))]
3821 "&& reload_completed"
3824 rtx op1 = operands[1];
3826 op1 = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (op1));
3828 op1 = gen_lowpart (<avxhalfvecmode>mode, op1);
3829 emit_move_insn (operands[0], op1);
3833 (define_insn "vec_extract_hi_<mode>"
3834 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3835 (vec_select:<avxhalfvecmode>
3836 (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
3837 (parallel [(const_int 2) (const_int 3)])))]
3839 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3840 [(set_attr "type" "sselog")
3841 (set_attr "prefix_extra" "1")
3842 (set_attr "length_immediate" "1")
3843 (set_attr "memory" "none,store")
3844 (set_attr "prefix" "vex")
3845 (set_attr "mode" "V8SF")])
3847 (define_insn_and_split "vec_extract_lo_<mode>"
3848 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3849 (vec_select:<avxhalfvecmode>
3850 (match_operand:AVX256MODE8P 1 "nonimmediate_operand" "xm,x")
3851 (parallel [(const_int 0) (const_int 1)
3852 (const_int 2) (const_int 3)])))]
3855 "&& reload_completed"
3858 rtx op1 = operands[1];
3860 op1 = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (op1));
3862 op1 = gen_lowpart (<avxhalfvecmode>mode, op1);
3863 emit_move_insn (operands[0], op1);
3867 (define_insn "vec_extract_hi_<mode>"
3868 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3869 (vec_select:<avxhalfvecmode>
3870 (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
3871 (parallel [(const_int 4) (const_int 5)
3872 (const_int 6) (const_int 7)])))]
3874 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3875 [(set_attr "type" "sselog")
3876 (set_attr "prefix_extra" "1")
3877 (set_attr "length_immediate" "1")
3878 (set_attr "memory" "none,store")
3879 (set_attr "prefix" "vex")
3880 (set_attr "mode" "V8SF")])
3882 (define_insn_and_split "vec_extract_lo_v16hi"
3883 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
3885 (match_operand:V16HI 1 "nonimmediate_operand" "xm,x")
3886 (parallel [(const_int 0) (const_int 1)
3887 (const_int 2) (const_int 3)
3888 (const_int 4) (const_int 5)
3889 (const_int 6) (const_int 7)])))]
3892 "&& reload_completed"
3895 rtx op1 = operands[1];
3897 op1 = gen_rtx_REG (V8HImode, REGNO (op1));
3899 op1 = gen_lowpart (V8HImode, op1);
3900 emit_move_insn (operands[0], op1);
3904 (define_insn "vec_extract_hi_v16hi"
3905 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
3907 (match_operand:V16HI 1 "register_operand" "x,x")
3908 (parallel [(const_int 8) (const_int 9)
3909 (const_int 10) (const_int 11)
3910 (const_int 12) (const_int 13)
3911 (const_int 14) (const_int 15)])))]
3913 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3914 [(set_attr "type" "sselog")
3915 (set_attr "prefix_extra" "1")
3916 (set_attr "length_immediate" "1")
3917 (set_attr "memory" "none,store")
3918 (set_attr "prefix" "vex")
3919 (set_attr "mode" "V8SF")])
3921 (define_insn_and_split "vec_extract_lo_v32qi"
3922 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
3924 (match_operand:V32QI 1 "nonimmediate_operand" "xm,x")
3925 (parallel [(const_int 0) (const_int 1)
3926 (const_int 2) (const_int 3)
3927 (const_int 4) (const_int 5)
3928 (const_int 6) (const_int 7)
3929 (const_int 8) (const_int 9)
3930 (const_int 10) (const_int 11)
3931 (const_int 12) (const_int 13)
3932 (const_int 14) (const_int 15)])))]
3935 "&& reload_completed"
3938 rtx op1 = operands[1];
3940 op1 = gen_rtx_REG (V16QImode, REGNO (op1));
3942 op1 = gen_lowpart (V16QImode, op1);
3943 emit_move_insn (operands[0], op1);
3947 (define_insn "vec_extract_hi_v32qi"
3948 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
3950 (match_operand:V32QI 1 "register_operand" "x,x")
3951 (parallel [(const_int 16) (const_int 17)
3952 (const_int 18) (const_int 19)
3953 (const_int 20) (const_int 21)
3954 (const_int 22) (const_int 23)
3955 (const_int 24) (const_int 25)
3956 (const_int 26) (const_int 27)
3957 (const_int 28) (const_int 29)
3958 (const_int 30) (const_int 31)])))]
3960 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3961 [(set_attr "type" "sselog")
3962 (set_attr "prefix_extra" "1")
3963 (set_attr "length_immediate" "1")
3964 (set_attr "memory" "none,store")
3965 (set_attr "prefix" "vex")
3966 (set_attr "mode" "V8SF")])
3968 (define_insn "*sse4_1_extractps"
3969 [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
3971 (match_operand:V4SF 1 "register_operand" "x")
3972 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
3974 "%vextractps\t{%2, %1, %0|%0, %1, %2}"
3975 [(set_attr "type" "sselog")
3976 (set_attr "prefix_data16" "1")
3977 (set_attr "prefix_extra" "1")
3978 (set_attr "length_immediate" "1")
3979 (set_attr "prefix" "maybe_vex")
3980 (set_attr "mode" "V4SF")])
3982 (define_insn_and_split "*vec_extract_v4sf_mem"
3983 [(set (match_operand:SF 0 "register_operand" "=x*rf")
3985 (match_operand:V4SF 1 "memory_operand" "o")
3986 (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
3992 int i = INTVAL (operands[2]);
3994 emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4));
3998 (define_expand "vec_extract<mode>"
3999 [(match_operand:<avxscalarmode> 0 "register_operand" "")
4000 (match_operand:VEC_EXTRACT_MODE 1 "register_operand" "")
4001 (match_operand 2 "const_int_operand" "")]
4004 ix86_expand_vector_extract (false, operands[0], operands[1],
4005 INTVAL (operands[2]));
4009 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4011 ;; Parallel double-precision floating point element swizzling
4013 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4015 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
4016 (define_insn "avx_unpckhpd256"
4017 [(set (match_operand:V4DF 0 "register_operand" "=x")
4020 (match_operand:V4DF 1 "register_operand" "x")
4021 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4022 (parallel [(const_int 1) (const_int 5)
4023 (const_int 3) (const_int 7)])))]
4025 "vunpckhpd\t{%2, %1, %0|%0, %1, %2}"
4026 [(set_attr "type" "sselog")
4027 (set_attr "prefix" "vex")
4028 (set_attr "mode" "V4DF")])
4030 (define_expand "vec_interleave_highv4df"
4034 (match_operand:V4DF 1 "register_operand" "x")
4035 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4036 (parallel [(const_int 0) (const_int 4)
4037 (const_int 2) (const_int 6)])))
4043 (parallel [(const_int 1) (const_int 5)
4044 (const_int 3) (const_int 7)])))
4045 (set (match_operand:V4DF 0 "register_operand" "")
4050 (parallel [(const_int 2) (const_int 3)
4051 (const_int 6) (const_int 7)])))]
4054 operands[3] = gen_reg_rtx (V4DFmode);
4055 operands[4] = gen_reg_rtx (V4DFmode);
4059 (define_expand "vec_interleave_highv2df"
4060 [(set (match_operand:V2DF 0 "register_operand" "")
4063 (match_operand:V2DF 1 "nonimmediate_operand" "")
4064 (match_operand:V2DF 2 "nonimmediate_operand" ""))
4065 (parallel [(const_int 1)
4069 if (!ix86_vec_interleave_v2df_operator_ok (operands, 1))
4070 operands[2] = force_reg (V2DFmode, operands[2]);
4073 (define_insn "*avx_interleave_highv2df"
4074 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,m")
4077 (match_operand:V2DF 1 "nonimmediate_operand" " x,o,o,x")
4078 (match_operand:V2DF 2 "nonimmediate_operand" " x,1,x,0"))
4079 (parallel [(const_int 1)
4081 "TARGET_AVX && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
4083 vunpckhpd\t{%2, %1, %0|%0, %1, %2}
4084 vmovddup\t{%H1, %0|%0, %H1}
4085 vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
4086 vmovhpd\t{%1, %0|%0, %1}"
4087 [(set_attr "type" "sselog,sselog,ssemov,ssemov")
4088 (set_attr "prefix" "vex")
4089 (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
4091 (define_insn "*sse3_interleave_highv2df"
4092 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,m")
4095 (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,o,x")
4096 (match_operand:V2DF 2 "nonimmediate_operand" " x,1,0,0"))
4097 (parallel [(const_int 1)
4099 "TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
4101 unpckhpd\t{%2, %0|%0, %2}
4102 movddup\t{%H1, %0|%0, %H1}
4103 movlpd\t{%H1, %0|%0, %H1}
4104 movhpd\t{%1, %0|%0, %1}"
4105 [(set_attr "type" "sselog,sselog,ssemov,ssemov")
4106 (set_attr "prefix_data16" "*,*,1,1")
4107 (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
4109 (define_insn "*sse2_interleave_highv2df"
4110 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
4113 (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
4114 (match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
4115 (parallel [(const_int 1)
4117 "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
4119 unpckhpd\t{%2, %0|%0, %2}
4120 movlpd\t{%H1, %0|%0, %H1}
4121 movhpd\t{%1, %0|%0, %1}"
4122 [(set_attr "type" "sselog,ssemov,ssemov")
4123 (set_attr "prefix_data16" "*,1,1")
4124 (set_attr "mode" "V2DF,V1DF,V1DF")])
4126 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
4127 (define_expand "avx_movddup256"
4128 [(set (match_operand:V4DF 0 "register_operand" "")
4131 (match_operand:V4DF 1 "nonimmediate_operand" "")
4133 (parallel [(const_int 0) (const_int 4)
4134 (const_int 2) (const_int 6)])))]
4137 (define_expand "avx_unpcklpd256"
4138 [(set (match_operand:V4DF 0 "register_operand" "")
4141 (match_operand:V4DF 1 "register_operand" "")
4142 (match_operand:V4DF 2 "nonimmediate_operand" ""))
4143 (parallel [(const_int 0) (const_int 4)
4144 (const_int 2) (const_int 6)])))]
4147 (define_insn "*avx_unpcklpd256"
4148 [(set (match_operand:V4DF 0 "register_operand" "=x,x")
4151 (match_operand:V4DF 1 "nonimmediate_operand" "xm,x")
4152 (match_operand:V4DF 2 "nonimmediate_operand" " 1,xm"))
4153 (parallel [(const_int 0) (const_int 4)
4154 (const_int 2) (const_int 6)])))]
4156 && (!MEM_P (operands[1]) || rtx_equal_p (operands[1], operands[2]))"
4158 vmovddup\t{%1, %0|%0, %1}
4159 vunpcklpd\t{%2, %1, %0|%0, %1, %2}"
4160 [(set_attr "type" "sselog")
4161 (set_attr "prefix" "vex")
4162 (set_attr "mode" "V4DF")])
4164 (define_expand "vec_interleave_lowv4df"
4168 (match_operand:V4DF 1 "register_operand" "x")
4169 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4170 (parallel [(const_int 0) (const_int 4)
4171 (const_int 2) (const_int 6)])))
4177 (parallel [(const_int 1) (const_int 5)
4178 (const_int 3) (const_int 7)])))
4179 (set (match_operand:V4DF 0 "register_operand" "")
4184 (parallel [(const_int 0) (const_int 1)
4185 (const_int 4) (const_int 5)])))]
4188 operands[3] = gen_reg_rtx (V4DFmode);
4189 operands[4] = gen_reg_rtx (V4DFmode);
4192 (define_expand "vec_interleave_lowv2df"
4193 [(set (match_operand:V2DF 0 "register_operand" "")
4196 (match_operand:V2DF 1 "nonimmediate_operand" "")
4197 (match_operand:V2DF 2 "nonimmediate_operand" ""))
4198 (parallel [(const_int 0)
4202 if (!ix86_vec_interleave_v2df_operator_ok (operands, 0))
4203 operands[1] = force_reg (V2DFmode, operands[1]);
4206 (define_insn "*avx_interleave_lowv2df"
4207 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o")
4210 (match_operand:V2DF 1 "nonimmediate_operand" " x,m,x,0")
4211 (match_operand:V2DF 2 "nonimmediate_operand" " x,1,m,x"))
4212 (parallel [(const_int 0)
4214 "TARGET_AVX && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
4216 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4217 vmovddup\t{%1, %0|%0, %1}
4218 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4219 vmovlpd\t{%2, %H0|%H0, %2}"
4220 [(set_attr "type" "sselog,sselog,ssemov,ssemov")
4221 (set_attr "prefix" "vex")
4222 (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
4224 (define_insn "*sse3_interleave_lowv2df"
4225 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o")
4228 (match_operand:V2DF 1 "nonimmediate_operand" " 0,m,0,0")
4229 (match_operand:V2DF 2 "nonimmediate_operand" " x,1,m,x"))
4230 (parallel [(const_int 0)
4232 "TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
4234 unpcklpd\t{%2, %0|%0, %2}
4235 movddup\t{%1, %0|%0, %1}
4236 movhpd\t{%2, %0|%0, %2}
4237 movlpd\t{%2, %H0|%H0, %2}"
4238 [(set_attr "type" "sselog,sselog,ssemov,ssemov")
4239 (set_attr "prefix_data16" "*,*,1,1")
4240 (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
4242 (define_insn "*sse2_interleave_lowv2df"
4243 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
4246 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
4247 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
4248 (parallel [(const_int 0)
4250 "TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
4252 unpcklpd\t{%2, %0|%0, %2}
4253 movhpd\t{%2, %0|%0, %2}
4254 movlpd\t{%2, %H0|%H0, %2}"
4255 [(set_attr "type" "sselog,ssemov,ssemov")
4256 (set_attr "prefix_data16" "*,1,1")
4257 (set_attr "mode" "V2DF,V1DF,V1DF")])
4260 [(set (match_operand:V2DF 0 "memory_operand" "")
4263 (match_operand:V2DF 1 "register_operand" "")
4265 (parallel [(const_int 0)
4267 "TARGET_SSE3 && reload_completed"
4270 rtx low = gen_rtx_REG (DFmode, REGNO (operands[1]));
4271 emit_move_insn (adjust_address (operands[0], DFmode, 0), low);
4272 emit_move_insn (adjust_address (operands[0], DFmode, 8), low);
4277 [(set (match_operand:V2DF 0 "register_operand" "")
4280 (match_operand:V2DF 1 "memory_operand" "")
4282 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "")
4283 (match_operand:SI 3 "const_int_operand" "")])))]
4284 "TARGET_SSE3 && INTVAL (operands[2]) + 2 == INTVAL (operands[3])"
4285 [(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))]
4287 operands[1] = adjust_address (operands[1], DFmode, INTVAL (operands[2]) * 8);
4290 (define_expand "avx_shufpd256"
4291 [(match_operand:V4DF 0 "register_operand" "")
4292 (match_operand:V4DF 1 "register_operand" "")
4293 (match_operand:V4DF 2 "nonimmediate_operand" "")
4294 (match_operand:SI 3 "const_int_operand" "")]
4297 int mask = INTVAL (operands[3]);
4298 emit_insn (gen_avx_shufpd256_1 (operands[0], operands[1], operands[2],
4300 GEN_INT (mask & 2 ? 5 : 4),
4301 GEN_INT (mask & 4 ? 3 : 2),
4302 GEN_INT (mask & 8 ? 7 : 6)));
4306 (define_insn "avx_shufpd256_1"
4307 [(set (match_operand:V4DF 0 "register_operand" "=x")
4310 (match_operand:V4DF 1 "register_operand" "x")
4311 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4312 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4313 (match_operand 4 "const_4_to_5_operand" "")
4314 (match_operand 5 "const_2_to_3_operand" "")
4315 (match_operand 6 "const_6_to_7_operand" "")])))]
4319 mask = INTVAL (operands[3]);
4320 mask |= (INTVAL (operands[4]) - 4) << 1;
4321 mask |= (INTVAL (operands[5]) - 2) << 2;
4322 mask |= (INTVAL (operands[6]) - 6) << 3;
4323 operands[3] = GEN_INT (mask);
4325 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4327 [(set_attr "type" "sselog")
4328 (set_attr "length_immediate" "1")
4329 (set_attr "prefix" "vex")
4330 (set_attr "mode" "V4DF")])
4332 (define_expand "sse2_shufpd"
4333 [(match_operand:V2DF 0 "register_operand" "")
4334 (match_operand:V2DF 1 "register_operand" "")
4335 (match_operand:V2DF 2 "nonimmediate_operand" "")
4336 (match_operand:SI 3 "const_int_operand" "")]
4339 int mask = INTVAL (operands[3]);
4340 emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
4342 GEN_INT (mask & 2 ? 3 : 2)));
4346 (define_expand "vec_extract_even<mode>"
4347 [(match_operand:SSEMODE_EO 0 "register_operand" "")
4348 (match_operand:SSEMODE_EO 1 "register_operand" "")
4349 (match_operand:SSEMODE_EO 2 "register_operand" "")]
4352 ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 0);
4356 (define_expand "vec_extract_odd<mode>"
4357 [(match_operand:SSEMODE_EO 0 "register_operand" "")
4358 (match_operand:SSEMODE_EO 1 "register_operand" "")
4359 (match_operand:SSEMODE_EO 2 "register_operand" "")]
4362 ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 1);
4366 ;; punpcklqdq and punpckhqdq are shorter than shufpd.
4367 (define_insn "*avx_interleave_highv2di"
4368 [(set (match_operand:V2DI 0 "register_operand" "=x")
4371 (match_operand:V2DI 1 "register_operand" "x")
4372 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4373 (parallel [(const_int 1)
4376 "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}"
4377 [(set_attr "type" "sselog")
4378 (set_attr "prefix" "vex")
4379 (set_attr "mode" "TI")])
4381 (define_insn "vec_interleave_highv2di"
4382 [(set (match_operand:V2DI 0 "register_operand" "=x")
4385 (match_operand:V2DI 1 "register_operand" "0")
4386 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4387 (parallel [(const_int 1)
4390 "punpckhqdq\t{%2, %0|%0, %2}"
4391 [(set_attr "type" "sselog")
4392 (set_attr "prefix_data16" "1")
4393 (set_attr "mode" "TI")])
4395 (define_insn "*avx_interleave_lowv2di"
4396 [(set (match_operand:V2DI 0 "register_operand" "=x")
4399 (match_operand:V2DI 1 "register_operand" "x")
4400 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4401 (parallel [(const_int 0)
4404 "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}"
4405 [(set_attr "type" "sselog")
4406 (set_attr "prefix" "vex")
4407 (set_attr "mode" "TI")])
4409 (define_insn "vec_interleave_lowv2di"
4410 [(set (match_operand:V2DI 0 "register_operand" "=x")
4413 (match_operand:V2DI 1 "register_operand" "0")
4414 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4415 (parallel [(const_int 0)
4418 "punpcklqdq\t{%2, %0|%0, %2}"
4419 [(set_attr "type" "sselog")
4420 (set_attr "prefix_data16" "1")
4421 (set_attr "mode" "TI")])
4423 (define_insn "*avx_shufpd_<mode>"
4424 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
4425 (vec_select:SSEMODE2D
4426 (vec_concat:<ssedoublesizemode>
4427 (match_operand:SSEMODE2D 1 "register_operand" "x")
4428 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
4429 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4430 (match_operand 4 "const_2_to_3_operand" "")])))]
4434 mask = INTVAL (operands[3]);
4435 mask |= (INTVAL (operands[4]) - 2) << 1;
4436 operands[3] = GEN_INT (mask);
4438 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4440 [(set_attr "type" "sselog")
4441 (set_attr "length_immediate" "1")
4442 (set_attr "prefix" "vex")
4443 (set_attr "mode" "V2DF")])
4445 (define_insn "sse2_shufpd_<mode>"
4446 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
4447 (vec_select:SSEMODE2D
4448 (vec_concat:<ssedoublesizemode>
4449 (match_operand:SSEMODE2D 1 "register_operand" "0")
4450 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
4451 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4452 (match_operand 4 "const_2_to_3_operand" "")])))]
4456 mask = INTVAL (operands[3]);
4457 mask |= (INTVAL (operands[4]) - 2) << 1;
4458 operands[3] = GEN_INT (mask);
4460 return "shufpd\t{%3, %2, %0|%0, %2, %3}";
4462 [(set_attr "type" "sselog")
4463 (set_attr "length_immediate" "1")
4464 (set_attr "mode" "V2DF")])
4466 ;; Avoid combining registers from different units in a single alternative,
4467 ;; see comment above inline_secondary_memory_needed function in i386.c
4468 (define_insn "*avx_storehpd"
4469 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4471 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,o,o,o")
4472 (parallel [(const_int 1)])))]
4473 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4475 vmovhpd\t{%1, %0|%0, %1}
4476 vunpckhpd\t{%1, %1, %0|%0, %1, %1}
4480 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
4481 (set_attr "prefix" "vex")
4482 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4484 (define_insn "sse2_storehpd"
4485 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4487 (match_operand:V2DF 1 "nonimmediate_operand" " x,0,o,o,o")
4488 (parallel [(const_int 1)])))]
4489 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4491 movhpd\t{%1, %0|%0, %1}
4496 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
4497 (set_attr "prefix_data16" "1,*,*,*,*")
4498 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4501 [(set (match_operand:DF 0 "register_operand" "")
4503 (match_operand:V2DF 1 "memory_operand" "")
4504 (parallel [(const_int 1)])))]
4505 "TARGET_SSE2 && reload_completed"
4506 [(set (match_dup 0) (match_dup 1))]
4507 "operands[1] = adjust_address (operands[1], DFmode, 8);")
4509 ;; Avoid combining registers from different units in a single alternative,
4510 ;; see comment above inline_secondary_memory_needed function in i386.c
4511 (define_insn "sse2_storelpd"
4512 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4514 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m")
4515 (parallel [(const_int 0)])))]
4516 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4518 %vmovlpd\t{%1, %0|%0, %1}
4523 [(set_attr "type" "ssemov,ssemov,ssemov,fmov,imov")
4524 (set_attr "prefix_data16" "1,*,*,*,*")
4525 (set_attr "prefix" "maybe_vex")
4526 (set_attr "mode" "V1DF,DF,DF,DF,DF")])
4529 [(set (match_operand:DF 0 "register_operand" "")
4531 (match_operand:V2DF 1 "nonimmediate_operand" "")
4532 (parallel [(const_int 0)])))]
4533 "TARGET_SSE2 && reload_completed"
4536 rtx op1 = operands[1];
4538 op1 = gen_rtx_REG (DFmode, REGNO (op1));
4540 op1 = gen_lowpart (DFmode, op1);
4541 emit_move_insn (operands[0], op1);
4545 (define_expand "sse2_loadhpd_exp"
4546 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4549 (match_operand:V2DF 1 "nonimmediate_operand" "")
4550 (parallel [(const_int 0)]))
4551 (match_operand:DF 2 "nonimmediate_operand" "")))]
4554 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
4556 emit_insn (gen_sse2_loadhpd (dst, operands[1], operands[2]));
4558 /* Fix up the destination if needed. */
4559 if (dst != operands[0])
4560 emit_move_insn (operands[0], dst);
4565 ;; Avoid combining registers from different units in a single alternative,
4566 ;; see comment above inline_secondary_memory_needed function in i386.c
4567 (define_insn "*avx_loadhpd"
4568 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o,o,o")
4571 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,0,0")
4572 (parallel [(const_int 0)]))
4573 (match_operand:DF 2 "nonimmediate_operand" " m,x,x,*f,r")))]
4574 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4576 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4577 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4581 [(set_attr "type" "ssemov,sselog,ssemov,fmov,imov")
4582 (set_attr "prefix" "vex")
4583 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4585 (define_insn "sse2_loadhpd"
4586 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o")
4589 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
4590 (parallel [(const_int 0)]))
4591 (match_operand:DF 2 "nonimmediate_operand" " m,x,0,x,*f,r")))]
4592 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4594 movhpd\t{%2, %0|%0, %2}
4595 unpcklpd\t{%2, %0|%0, %2}
4596 shufpd\t{$1, %1, %0|%0, %1, 1}
4600 [(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
4601 (set_attr "prefix_data16" "1,*,*,*,*,*")
4602 (set_attr "length_immediate" "*,*,1,*,*,*")
4603 (set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
4606 [(set (match_operand:V2DF 0 "memory_operand" "")
4608 (vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
4609 (match_operand:DF 1 "register_operand" "")))]
4610 "TARGET_SSE2 && reload_completed"
4611 [(set (match_dup 0) (match_dup 1))]
4612 "operands[0] = adjust_address (operands[0], DFmode, 8);")
4614 (define_expand "sse2_loadlpd_exp"
4615 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4617 (match_operand:DF 2 "nonimmediate_operand" "")
4619 (match_operand:V2DF 1 "nonimmediate_operand" "")
4620 (parallel [(const_int 1)]))))]
4623 rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
4625 emit_insn (gen_sse2_loadlpd (dst, operands[1], operands[2]));
4627 /* Fix up the destination if needed. */
4628 if (dst != operands[0])
4629 emit_move_insn (operands[0], dst);
4634 ;; Avoid combining registers from different units in a single alternative,
4635 ;; see comment above inline_secondary_memory_needed function in i386.c
4636 (define_insn "*avx_loadlpd"
4637 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,m,m")
4639 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,x,x,*f,r")
4641 (match_operand:V2DF 1 "vector_move_operand" " C,x,x,o,0,0,0")
4642 (parallel [(const_int 1)]))))]
4643 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4645 vmovsd\t{%2, %0|%0, %2}
4646 vmovlpd\t{%2, %1, %0|%0, %1, %2}
4647 vmovsd\t{%2, %1, %0|%0, %1, %2}
4648 vmovhpd\t{%H1, %2, %0|%0, %2, %H1}
4652 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov,fmov,imov")
4653 (set_attr "prefix" "vex")
4654 (set_attr "mode" "DF,V1DF,V1DF,V1DF,DF,DF,DF")])
4656 (define_insn "sse2_loadlpd"
4657 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m,m,m")
4659 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,0,0,x,*f,r")
4661 (match_operand:V2DF 1 "vector_move_operand" " C,0,0,x,o,0,0,0")
4662 (parallel [(const_int 1)]))))]
4663 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4665 movsd\t{%2, %0|%0, %2}
4666 movlpd\t{%2, %0|%0, %2}
4667 movsd\t{%2, %0|%0, %2}
4668 shufpd\t{$2, %1, %0|%0, %1, 2}
4669 movhpd\t{%H1, %0|%0, %H1}
4673 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
4674 (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
4675 (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
4676 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
4679 [(set (match_operand:V2DF 0 "memory_operand" "")
4681 (match_operand:DF 1 "register_operand" "")
4682 (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
4683 "TARGET_SSE2 && reload_completed"
4684 [(set (match_dup 0) (match_dup 1))]
4685 "operands[0] = adjust_address (operands[0], DFmode, 8);")
4687 ;; Not sure these two are ever used, but it doesn't hurt to have
4689 (define_insn "*vec_extractv2df_1_sse"
4690 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
4692 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,o")
4693 (parallel [(const_int 1)])))]
4694 "!TARGET_SSE2 && TARGET_SSE
4695 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4697 movhps\t{%1, %0|%0, %1}
4698 movhlps\t{%1, %0|%0, %1}
4699 movlps\t{%H1, %0|%0, %H1}"
4700 [(set_attr "type" "ssemov")
4701 (set_attr "mode" "V2SF,V4SF,V2SF")])
4703 (define_insn "*vec_extractv2df_0_sse"
4704 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
4706 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m")
4707 (parallel [(const_int 0)])))]
4708 "!TARGET_SSE2 && TARGET_SSE
4709 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4711 movlps\t{%1, %0|%0, %1}
4712 movaps\t{%1, %0|%0, %1}
4713 movlps\t{%1, %0|%0, %1}"
4714 [(set_attr "type" "ssemov")
4715 (set_attr "mode" "V2SF,V4SF,V2SF")])
4717 (define_insn "*avx_movsd"
4718 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,o")
4720 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,x,0")
4721 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,o,x")
4725 vmovsd\t{%2, %1, %0|%0, %1, %2}
4726 vmovlpd\t{%2, %1, %0|%0, %1, %2}
4727 vmovlpd\t{%2, %0|%0, %2}
4728 vmovhps\t{%H1, %2, %0|%0, %2, %H1}
4729 vmovhps\t{%1, %H0|%H0, %1}"
4730 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov")
4731 (set_attr "prefix" "vex")
4732 (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF")])
4734 (define_insn "sse2_movsd"
4735 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,x,o")
4737 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,0,0,0")
4738 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,x,o,x")
4742 movsd\t{%2, %0|%0, %2}
4743 movlpd\t{%2, %0|%0, %2}
4744 movlpd\t{%2, %0|%0, %2}
4745 shufpd\t{$2, %1, %0|%0, %1, 2}
4746 movhps\t{%H1, %0|%0, %H1}
4747 movhps\t{%1, %H0|%H0, %1}"
4748 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
4749 (set_attr "prefix_data16" "*,1,1,*,*,*")
4750 (set_attr "length_immediate" "*,*,*,1,*,*")
4751 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
4753 (define_insn "*vec_dupv2df_sse3"
4754 [(set (match_operand:V2DF 0 "register_operand" "=x")
4756 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
4758 "%vmovddup\t{%1, %0|%0, %1}"
4759 [(set_attr "type" "sselog1")
4760 (set_attr "prefix" "maybe_vex")
4761 (set_attr "mode" "DF")])
4763 (define_insn "vec_dupv2df"
4764 [(set (match_operand:V2DF 0 "register_operand" "=x")
4766 (match_operand:DF 1 "register_operand" "0")))]
4769 [(set_attr "type" "sselog1")
4770 (set_attr "mode" "V2DF")])
4772 (define_insn "*vec_concatv2df_sse3"
4773 [(set (match_operand:V2DF 0 "register_operand" "=x")
4775 (match_operand:DF 1 "nonimmediate_operand" "xm")
4778 "%vmovddup\t{%1, %0|%0, %1}"
4779 [(set_attr "type" "sselog1")
4780 (set_attr "prefix" "maybe_vex")
4781 (set_attr "mode" "DF")])
4783 (define_insn "*vec_concatv2df_avx"
4784 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
4786 (match_operand:DF 1 "nonimmediate_operand" " x,x,m")
4787 (match_operand:DF 2 "vector_move_operand" " x,m,C")))]
4790 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4791 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4792 vmovsd\t{%1, %0|%0, %1}"
4793 [(set_attr "type" "ssemov")
4794 (set_attr "prefix" "vex")
4795 (set_attr "mode" "DF,V1DF,DF")])
4797 (define_insn "*vec_concatv2df"
4798 [(set (match_operand:V2DF 0 "register_operand" "=Y2,Y2,Y2,x,x")
4800 (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0")
4801 (match_operand:DF 2 "vector_move_operand" " Y2,m ,C ,x,m")))]
4804 unpcklpd\t{%2, %0|%0, %2}
4805 movhpd\t{%2, %0|%0, %2}
4806 movsd\t{%1, %0|%0, %1}
4807 movlhps\t{%2, %0|%0, %2}
4808 movhps\t{%2, %0|%0, %2}"
4809 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
4810 (set_attr "prefix_data16" "*,1,*,*,*")
4811 (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
4813 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4815 ;; Parallel integral arithmetic
4817 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4819 (define_expand "neg<mode>2"
4820 [(set (match_operand:SSEMODEI 0 "register_operand" "")
4823 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
4825 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
4827 (define_expand "<plusminus_insn><mode>3"
4828 [(set (match_operand:SSEMODEI 0 "register_operand" "")
4830 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
4831 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
4833 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4835 (define_insn "*avx_<plusminus_insn><mode>3"
4836 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
4838 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>x")
4839 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
4840 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4841 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
4842 [(set_attr "type" "sseiadd")
4843 (set_attr "prefix" "vex")
4844 (set_attr "mode" "TI")])
4846 (define_insn "*<plusminus_insn><mode>3"
4847 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
4849 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
4850 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
4851 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4852 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
4853 [(set_attr "type" "sseiadd")
4854 (set_attr "prefix_data16" "1")
4855 (set_attr "mode" "TI")])
4857 (define_expand "sse2_<plusminus_insn><mode>3"
4858 [(set (match_operand:SSEMODE12 0 "register_operand" "")
4859 (sat_plusminus:SSEMODE12
4860 (match_operand:SSEMODE12 1 "nonimmediate_operand" "")
4861 (match_operand:SSEMODE12 2 "nonimmediate_operand" "")))]
4863 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4865 (define_insn "*avx_<plusminus_insn><mode>3"
4866 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
4867 (sat_plusminus:SSEMODE12
4868 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>x")
4869 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
4870 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4871 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
4872 [(set_attr "type" "sseiadd")
4873 (set_attr "prefix" "vex")
4874 (set_attr "mode" "TI")])
4876 (define_insn "*sse2_<plusminus_insn><mode>3"
4877 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
4878 (sat_plusminus:SSEMODE12
4879 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
4880 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
4881 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4882 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
4883 [(set_attr "type" "sseiadd")
4884 (set_attr "prefix_data16" "1")
4885 (set_attr "mode" "TI")])
4887 (define_insn_and_split "mulv16qi3"
4888 [(set (match_operand:V16QI 0 "register_operand" "")
4889 (mult:V16QI (match_operand:V16QI 1 "register_operand" "")
4890 (match_operand:V16QI 2 "register_operand" "")))]
4892 && can_create_pseudo_p ()"
4900 for (i = 0; i < 6; ++i)
4901 t[i] = gen_reg_rtx (V16QImode);
4903 /* Unpack data such that we've got a source byte in each low byte of
4904 each word. We don't care what goes into the high byte of each word.
4905 Rather than trying to get zero in there, most convenient is to let
4906 it be a copy of the low byte. */
4907 emit_insn (gen_vec_interleave_highv16qi (t[0], operands[1], operands[1]));
4908 emit_insn (gen_vec_interleave_highv16qi (t[1], operands[2], operands[2]));
4909 emit_insn (gen_vec_interleave_lowv16qi (t[2], operands[1], operands[1]));
4910 emit_insn (gen_vec_interleave_lowv16qi (t[3], operands[2], operands[2]));
4912 /* Multiply words. The end-of-line annotations here give a picture of what
4913 the output of that instruction looks like. Dot means don't care; the
4914 letters are the bytes of the result with A being the most significant. */
4915 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[4]), /* .A.B.C.D.E.F.G.H */
4916 gen_lowpart (V8HImode, t[0]),
4917 gen_lowpart (V8HImode, t[1])));
4918 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[5]), /* .I.J.K.L.M.N.O.P */
4919 gen_lowpart (V8HImode, t[2]),
4920 gen_lowpart (V8HImode, t[3])));
4922 /* Extract the even bytes and merge them back together. */
4923 ix86_expand_vec_extract_even_odd (operands[0], t[5], t[4], 0);
4927 (define_expand "mulv8hi3"
4928 [(set (match_operand:V8HI 0 "register_operand" "")
4929 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
4930 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
4932 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4934 (define_insn "*avx_mulv8hi3"
4935 [(set (match_operand:V8HI 0 "register_operand" "=x")
4936 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
4937 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
4938 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4939 "vpmullw\t{%2, %1, %0|%0, %1, %2}"
4940 [(set_attr "type" "sseimul")
4941 (set_attr "prefix" "vex")
4942 (set_attr "mode" "TI")])
4944 (define_insn "*mulv8hi3"
4945 [(set (match_operand:V8HI 0 "register_operand" "=x")
4946 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
4947 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
4948 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4949 "pmullw\t{%2, %0|%0, %2}"
4950 [(set_attr "type" "sseimul")
4951 (set_attr "prefix_data16" "1")
4952 (set_attr "mode" "TI")])
4954 (define_expand "<s>mulv8hi3_highpart"
4955 [(set (match_operand:V8HI 0 "register_operand" "")
4960 (match_operand:V8HI 1 "nonimmediate_operand" ""))
4962 (match_operand:V8HI 2 "nonimmediate_operand" "")))
4965 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4967 (define_insn "*avx_<s>mulv8hi3_highpart"
4968 [(set (match_operand:V8HI 0 "register_operand" "=x")
4973 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
4975 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4977 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4978 "vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
4979 [(set_attr "type" "sseimul")
4980 (set_attr "prefix" "vex")
4981 (set_attr "mode" "TI")])
4983 (define_insn "*<s>mulv8hi3_highpart"
4984 [(set (match_operand:V8HI 0 "register_operand" "=x")
4989 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
4991 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4993 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4994 "pmulh<u>w\t{%2, %0|%0, %2}"
4995 [(set_attr "type" "sseimul")
4996 (set_attr "prefix_data16" "1")
4997 (set_attr "mode" "TI")])
4999 (define_expand "sse2_umulv2siv2di3"
5000 [(set (match_operand:V2DI 0 "register_operand" "")
5004 (match_operand:V4SI 1 "nonimmediate_operand" "")
5005 (parallel [(const_int 0) (const_int 2)])))
5008 (match_operand:V4SI 2 "nonimmediate_operand" "")
5009 (parallel [(const_int 0) (const_int 2)])))))]
5011 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
5013 (define_insn "*avx_umulv2siv2di3"
5014 [(set (match_operand:V2DI 0 "register_operand" "=x")
5018 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5019 (parallel [(const_int 0) (const_int 2)])))
5022 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5023 (parallel [(const_int 0) (const_int 2)])))))]
5024 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5025 "vpmuludq\t{%2, %1, %0|%0, %1, %2}"
5026 [(set_attr "type" "sseimul")
5027 (set_attr "prefix" "vex")
5028 (set_attr "mode" "TI")])
5030 (define_insn "*sse2_umulv2siv2di3"
5031 [(set (match_operand:V2DI 0 "register_operand" "=x")
5035 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5036 (parallel [(const_int 0) (const_int 2)])))
5039 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5040 (parallel [(const_int 0) (const_int 2)])))))]
5041 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5042 "pmuludq\t{%2, %0|%0, %2}"
5043 [(set_attr "type" "sseimul")
5044 (set_attr "prefix_data16" "1")
5045 (set_attr "mode" "TI")])
5047 (define_expand "sse4_1_mulv2siv2di3"
5048 [(set (match_operand:V2DI 0 "register_operand" "")
5052 (match_operand:V4SI 1 "nonimmediate_operand" "")
5053 (parallel [(const_int 0) (const_int 2)])))
5056 (match_operand:V4SI 2 "nonimmediate_operand" "")
5057 (parallel [(const_int 0) (const_int 2)])))))]
5059 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
5061 (define_insn "*avx_mulv2siv2di3"
5062 [(set (match_operand:V2DI 0 "register_operand" "=x")
5066 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5067 (parallel [(const_int 0) (const_int 2)])))
5070 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5071 (parallel [(const_int 0) (const_int 2)])))))]
5072 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5073 "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
5074 [(set_attr "type" "sseimul")
5075 (set_attr "prefix_extra" "1")
5076 (set_attr "prefix" "vex")
5077 (set_attr "mode" "TI")])
5079 (define_insn "*sse4_1_mulv2siv2di3"
5080 [(set (match_operand:V2DI 0 "register_operand" "=x")
5084 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5085 (parallel [(const_int 0) (const_int 2)])))
5088 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5089 (parallel [(const_int 0) (const_int 2)])))))]
5090 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5091 "pmuldq\t{%2, %0|%0, %2}"
5092 [(set_attr "type" "sseimul")
5093 (set_attr "prefix_extra" "1")
5094 (set_attr "mode" "TI")])
5096 (define_expand "sse2_pmaddwd"
5097 [(set (match_operand:V4SI 0 "register_operand" "")
5102 (match_operand:V8HI 1 "nonimmediate_operand" "")
5103 (parallel [(const_int 0)
5109 (match_operand:V8HI 2 "nonimmediate_operand" "")
5110 (parallel [(const_int 0)
5116 (vec_select:V4HI (match_dup 1)
5117 (parallel [(const_int 1)
5122 (vec_select:V4HI (match_dup 2)
5123 (parallel [(const_int 1)
5126 (const_int 7)]))))))]
5128 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
5130 (define_insn "*avx_pmaddwd"
5131 [(set (match_operand:V4SI 0 "register_operand" "=x")
5136 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
5137 (parallel [(const_int 0)
5143 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
5144 (parallel [(const_int 0)
5150 (vec_select:V4HI (match_dup 1)
5151 (parallel [(const_int 1)
5156 (vec_select:V4HI (match_dup 2)
5157 (parallel [(const_int 1)
5160 (const_int 7)]))))))]
5161 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5162 "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
5163 [(set_attr "type" "sseiadd")
5164 (set_attr "prefix" "vex")
5165 (set_attr "mode" "TI")])
5167 (define_insn "*sse2_pmaddwd"
5168 [(set (match_operand:V4SI 0 "register_operand" "=x")
5173 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
5174 (parallel [(const_int 0)
5180 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
5181 (parallel [(const_int 0)
5187 (vec_select:V4HI (match_dup 1)
5188 (parallel [(const_int 1)
5193 (vec_select:V4HI (match_dup 2)
5194 (parallel [(const_int 1)
5197 (const_int 7)]))))))]
5198 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5199 "pmaddwd\t{%2, %0|%0, %2}"
5200 [(set_attr "type" "sseiadd")
5201 (set_attr "atom_unit" "simul")
5202 (set_attr "prefix_data16" "1")
5203 (set_attr "mode" "TI")])
5205 (define_expand "mulv4si3"
5206 [(set (match_operand:V4SI 0 "register_operand" "")
5207 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
5208 (match_operand:V4SI 2 "register_operand" "")))]
5211 if (TARGET_SSE4_1 || TARGET_AVX)
5212 ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
5215 (define_insn "*avx_mulv4si3"
5216 [(set (match_operand:V4SI 0 "register_operand" "=x")
5217 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5218 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
5219 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5220 "vpmulld\t{%2, %1, %0|%0, %1, %2}"
5221 [(set_attr "type" "sseimul")
5222 (set_attr "prefix_extra" "1")
5223 (set_attr "prefix" "vex")
5224 (set_attr "mode" "TI")])
5226 (define_insn "*sse4_1_mulv4si3"
5227 [(set (match_operand:V4SI 0 "register_operand" "=x")
5228 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5229 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
5230 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5231 "pmulld\t{%2, %0|%0, %2}"
5232 [(set_attr "type" "sseimul")
5233 (set_attr "prefix_extra" "1")
5234 (set_attr "mode" "TI")])
5236 (define_insn_and_split "*sse2_mulv4si3"
5237 [(set (match_operand:V4SI 0 "register_operand" "")
5238 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
5239 (match_operand:V4SI 2 "register_operand" "")))]
5240 "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX
5241 && can_create_pseudo_p ()"
5246 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
5252 t1 = gen_reg_rtx (V4SImode);
5253 t2 = gen_reg_rtx (V4SImode);
5254 t3 = gen_reg_rtx (V4SImode);
5255 t4 = gen_reg_rtx (V4SImode);
5256 t5 = gen_reg_rtx (V4SImode);
5257 t6 = gen_reg_rtx (V4SImode);
5258 thirtytwo = GEN_INT (32);
5260 /* Multiply elements 2 and 0. */
5261 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t1),
5264 /* Shift both input vectors down one element, so that elements 3
5265 and 1 are now in the slots for elements 2 and 0. For K8, at
5266 least, this is faster than using a shuffle. */
5267 emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2),
5268 gen_lowpart (V1TImode, op1),
5270 emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3),
5271 gen_lowpart (V1TImode, op2),
5273 /* Multiply elements 3 and 1. */
5274 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
5277 /* Move the results in element 2 down to element 1; we don't care
5278 what goes in elements 2 and 3. */
5279 emit_insn (gen_sse2_pshufd_1 (t5, t1, const0_rtx, const2_rtx,
5280 const0_rtx, const0_rtx));
5281 emit_insn (gen_sse2_pshufd_1 (t6, t4, const0_rtx, const2_rtx,
5282 const0_rtx, const0_rtx));
5284 /* Merge the parts back together. */
5285 emit_insn (gen_vec_interleave_lowv4si (op0, t5, t6));
5289 (define_insn_and_split "mulv2di3"
5290 [(set (match_operand:V2DI 0 "register_operand" "")
5291 (mult:V2DI (match_operand:V2DI 1 "register_operand" "")
5292 (match_operand:V2DI 2 "register_operand" "")))]
5294 && can_create_pseudo_p ()"
5299 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
5308 /* op1: A,B,C,D, op2: E,F,G,H */
5309 op1 = gen_lowpart (V4SImode, op1);
5310 op2 = gen_lowpart (V4SImode, op2);
5312 t1 = gen_reg_rtx (V4SImode);
5313 t2 = gen_reg_rtx (V4SImode);
5314 t3 = gen_reg_rtx (V2DImode);
5315 t4 = gen_reg_rtx (V2DImode);
5318 emit_insn (gen_sse2_pshufd_1 (t1, op1,
5324 /* t2: (B*E),(A*F),(D*G),(C*H) */
5325 emit_insn (gen_mulv4si3 (t2, t1, op2));
5327 /* t4: (B*E)+(A*F), (D*G)+(C*H) */
5328 emit_insn (gen_xop_phadddq (t3, t2));
5330 /* t5: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
5331 emit_insn (gen_ashlv2di3 (t4, t3, GEN_INT (32)));
5333 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
5334 emit_insn (gen_xop_pmacsdql (op0, op1, op2, t4));
5338 t1 = gen_reg_rtx (V2DImode);
5339 t2 = gen_reg_rtx (V2DImode);
5340 t3 = gen_reg_rtx (V2DImode);
5341 t4 = gen_reg_rtx (V2DImode);
5342 t5 = gen_reg_rtx (V2DImode);
5343 t6 = gen_reg_rtx (V2DImode);
5344 thirtytwo = GEN_INT (32);
5346 /* Multiply low parts. */
5347 emit_insn (gen_sse2_umulv2siv2di3 (t1, gen_lowpart (V4SImode, op1),
5348 gen_lowpart (V4SImode, op2)));
5350 /* Shift input vectors left 32 bits so we can multiply high parts. */
5351 emit_insn (gen_lshrv2di3 (t2, op1, thirtytwo));
5352 emit_insn (gen_lshrv2di3 (t3, op2, thirtytwo));
5354 /* Multiply high parts by low parts. */
5355 emit_insn (gen_sse2_umulv2siv2di3 (t4, gen_lowpart (V4SImode, op1),
5356 gen_lowpart (V4SImode, t3)));
5357 emit_insn (gen_sse2_umulv2siv2di3 (t5, gen_lowpart (V4SImode, op2),
5358 gen_lowpart (V4SImode, t2)));
5360 /* Shift them back. */
5361 emit_insn (gen_ashlv2di3 (t4, t4, thirtytwo));
5362 emit_insn (gen_ashlv2di3 (t5, t5, thirtytwo));
5364 /* Add the three parts together. */
5365 emit_insn (gen_addv2di3 (t6, t1, t4));
5366 emit_insn (gen_addv2di3 (op0, t6, t5));
5371 (define_expand "vec_widen_smult_hi_v8hi"
5372 [(match_operand:V4SI 0 "register_operand" "")
5373 (match_operand:V8HI 1 "register_operand" "")
5374 (match_operand:V8HI 2 "register_operand" "")]
5377 rtx op1, op2, t1, t2, dest;
5381 t1 = gen_reg_rtx (V8HImode);
5382 t2 = gen_reg_rtx (V8HImode);
5383 dest = gen_lowpart (V8HImode, operands[0]);
5385 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5386 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
5387 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
5391 (define_expand "vec_widen_smult_lo_v8hi"
5392 [(match_operand:V4SI 0 "register_operand" "")
5393 (match_operand:V8HI 1 "register_operand" "")
5394 (match_operand:V8HI 2 "register_operand" "")]
5397 rtx op1, op2, t1, t2, dest;
5401 t1 = gen_reg_rtx (V8HImode);
5402 t2 = gen_reg_rtx (V8HImode);
5403 dest = gen_lowpart (V8HImode, operands[0]);
5405 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5406 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
5407 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
5411 (define_expand "vec_widen_umult_hi_v8hi"
5412 [(match_operand:V4SI 0 "register_operand" "")
5413 (match_operand:V8HI 1 "register_operand" "")
5414 (match_operand:V8HI 2 "register_operand" "")]
5417 rtx op1, op2, t1, t2, dest;
5421 t1 = gen_reg_rtx (V8HImode);
5422 t2 = gen_reg_rtx (V8HImode);
5423 dest = gen_lowpart (V8HImode, operands[0]);
5425 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5426 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
5427 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
5431 (define_expand "vec_widen_umult_lo_v8hi"
5432 [(match_operand:V4SI 0 "register_operand" "")
5433 (match_operand:V8HI 1 "register_operand" "")
5434 (match_operand:V8HI 2 "register_operand" "")]
5437 rtx op1, op2, t1, t2, dest;
5441 t1 = gen_reg_rtx (V8HImode);
5442 t2 = gen_reg_rtx (V8HImode);
5443 dest = gen_lowpart (V8HImode, operands[0]);
5445 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5446 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
5447 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
5451 (define_expand "vec_widen_smult_hi_v4si"
5452 [(match_operand:V2DI 0 "register_operand" "")
5453 (match_operand:V4SI 1 "register_operand" "")
5454 (match_operand:V4SI 2 "register_operand" "")]
5459 t1 = gen_reg_rtx (V4SImode);
5460 t2 = gen_reg_rtx (V4SImode);
5462 emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
5467 emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
5472 emit_insn (gen_xop_mulv2div2di3_high (operands[0], t1, t2));
5476 (define_expand "vec_widen_smult_lo_v4si"
5477 [(match_operand:V2DI 0 "register_operand" "")
5478 (match_operand:V4SI 1 "register_operand" "")
5479 (match_operand:V4SI 2 "register_operand" "")]
5484 t1 = gen_reg_rtx (V4SImode);
5485 t2 = gen_reg_rtx (V4SImode);
5487 emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
5492 emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
5497 emit_insn (gen_xop_mulv2div2di3_low (operands[0], t1, t2));
5501 (define_expand "vec_widen_umult_hi_v4si"
5502 [(match_operand:V2DI 0 "register_operand" "")
5503 (match_operand:V4SI 1 "register_operand" "")
5504 (match_operand:V4SI 2 "register_operand" "")]
5507 rtx op1, op2, t1, t2;
5511 t1 = gen_reg_rtx (V4SImode);
5512 t2 = gen_reg_rtx (V4SImode);
5514 emit_insn (gen_vec_interleave_highv4si (t1, op1, op1));
5515 emit_insn (gen_vec_interleave_highv4si (t2, op2, op2));
5516 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
5520 (define_expand "vec_widen_umult_lo_v4si"
5521 [(match_operand:V2DI 0 "register_operand" "")
5522 (match_operand:V4SI 1 "register_operand" "")
5523 (match_operand:V4SI 2 "register_operand" "")]
5526 rtx op1, op2, t1, t2;
5530 t1 = gen_reg_rtx (V4SImode);
5531 t2 = gen_reg_rtx (V4SImode);
5533 emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1));
5534 emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2));
5535 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
5539 (define_expand "sdot_prodv8hi"
5540 [(match_operand:V4SI 0 "register_operand" "")
5541 (match_operand:V8HI 1 "register_operand" "")
5542 (match_operand:V8HI 2 "register_operand" "")
5543 (match_operand:V4SI 3 "register_operand" "")]
5546 rtx t = gen_reg_rtx (V4SImode);
5547 emit_insn (gen_sse2_pmaddwd (t, operands[1], operands[2]));
5548 emit_insn (gen_addv4si3 (operands[0], operands[3], t));
5552 (define_expand "udot_prodv4si"
5553 [(match_operand:V2DI 0 "register_operand" "")
5554 (match_operand:V4SI 1 "register_operand" "")
5555 (match_operand:V4SI 2 "register_operand" "")
5556 (match_operand:V2DI 3 "register_operand" "")]
5561 t1 = gen_reg_rtx (V2DImode);
5562 emit_insn (gen_sse2_umulv2siv2di3 (t1, operands[1], operands[2]));
5563 emit_insn (gen_addv2di3 (t1, t1, operands[3]));
5565 t2 = gen_reg_rtx (V4SImode);
5566 t3 = gen_reg_rtx (V4SImode);
5567 emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2),
5568 gen_lowpart (V1TImode, operands[1]),
5570 emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3),
5571 gen_lowpart (V1TImode, operands[2]),
5574 t4 = gen_reg_rtx (V2DImode);
5575 emit_insn (gen_sse2_umulv2siv2di3 (t4, t2, t3));
5577 emit_insn (gen_addv2di3 (operands[0], t1, t4));
5581 (define_insn "*avx_ashr<mode>3"
5582 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
5584 (match_operand:SSEMODE24 1 "register_operand" "x")
5585 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5587 "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5588 [(set_attr "type" "sseishft")
5589 (set_attr "prefix" "vex")
5590 (set (attr "length_immediate")
5591 (if_then_else (match_operand 2 "const_int_operand" "")
5593 (const_string "0")))
5594 (set_attr "mode" "TI")])
5596 (define_insn "ashr<mode>3"
5597 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
5599 (match_operand:SSEMODE24 1 "register_operand" "0")
5600 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5602 "psra<ssevecsize>\t{%2, %0|%0, %2}"
5603 [(set_attr "type" "sseishft")
5604 (set_attr "prefix_data16" "1")
5605 (set (attr "length_immediate")
5606 (if_then_else (match_operand 2 "const_int_operand" "")
5608 (const_string "0")))
5609 (set_attr "mode" "TI")])
5611 (define_insn "*avx_lshrv1ti3"
5612 [(set (match_operand:V1TI 0 "register_operand" "=x")
5614 (match_operand:V1TI 1 "register_operand" "x")
5615 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
5618 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
5619 return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
5621 [(set_attr "type" "sseishft")
5622 (set_attr "prefix" "vex")
5623 (set_attr "length_immediate" "1")
5624 (set_attr "mode" "TI")])
5626 (define_insn "*avx_lshr<mode>3"
5627 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5628 (lshiftrt:SSEMODE248
5629 (match_operand:SSEMODE248 1 "register_operand" "x")
5630 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5632 "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5633 [(set_attr "type" "sseishft")
5634 (set_attr "prefix" "vex")
5635 (set (attr "length_immediate")
5636 (if_then_else (match_operand 2 "const_int_operand" "")
5638 (const_string "0")))
5639 (set_attr "mode" "TI")])
5641 (define_insn "sse2_lshrv1ti3"
5642 [(set (match_operand:V1TI 0 "register_operand" "=x")
5644 (match_operand:V1TI 1 "register_operand" "0")
5645 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
5648 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
5649 return "psrldq\t{%2, %0|%0, %2}";
5651 [(set_attr "type" "sseishft")
5652 (set_attr "prefix_data16" "1")
5653 (set_attr "length_immediate" "1")
5654 (set_attr "atom_unit" "sishuf")
5655 (set_attr "mode" "TI")])
5657 (define_insn "lshr<mode>3"
5658 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5659 (lshiftrt:SSEMODE248
5660 (match_operand:SSEMODE248 1 "register_operand" "0")
5661 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5663 "psrl<ssevecsize>\t{%2, %0|%0, %2}"
5664 [(set_attr "type" "sseishft")
5665 (set_attr "prefix_data16" "1")
5666 (set (attr "length_immediate")
5667 (if_then_else (match_operand 2 "const_int_operand" "")
5669 (const_string "0")))
5670 (set_attr "mode" "TI")])
5672 (define_insn "*avx_ashlv1ti3"
5673 [(set (match_operand:V1TI 0 "register_operand" "=x")
5674 (ashift:V1TI (match_operand:V1TI 1 "register_operand" "x")
5675 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
5678 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
5679 return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
5681 [(set_attr "type" "sseishft")
5682 (set_attr "prefix" "vex")
5683 (set_attr "length_immediate" "1")
5684 (set_attr "mode" "TI")])
5686 (define_insn "*avx_ashl<mode>3"
5687 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5689 (match_operand:SSEMODE248 1 "register_operand" "x")
5690 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5692 "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5693 [(set_attr "type" "sseishft")
5694 (set_attr "prefix" "vex")
5695 (set (attr "length_immediate")
5696 (if_then_else (match_operand 2 "const_int_operand" "")
5698 (const_string "0")))
5699 (set_attr "mode" "TI")])
5701 (define_insn "sse2_ashlv1ti3"
5702 [(set (match_operand:V1TI 0 "register_operand" "=x")
5703 (ashift:V1TI (match_operand:V1TI 1 "register_operand" "0")
5704 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
5707 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
5708 return "pslldq\t{%2, %0|%0, %2}";
5710 [(set_attr "type" "sseishft")
5711 (set_attr "prefix_data16" "1")
5712 (set_attr "length_immediate" "1")
5713 (set_attr "mode" "TI")])
5715 (define_insn "ashl<mode>3"
5716 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5718 (match_operand:SSEMODE248 1 "register_operand" "0")
5719 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5721 "psll<ssevecsize>\t{%2, %0|%0, %2}"
5722 [(set_attr "type" "sseishft")
5723 (set_attr "prefix_data16" "1")
5724 (set (attr "length_immediate")
5725 (if_then_else (match_operand 2 "const_int_operand" "")
5727 (const_string "0")))
5728 (set_attr "mode" "TI")])
5730 (define_expand "vec_shl_<mode>"
5731 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5733 (match_operand:SSEMODEI 1 "register_operand" "")
5734 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
5737 operands[0] = gen_lowpart (V1TImode, operands[0]);
5738 operands[1] = gen_lowpart (V1TImode, operands[1]);
5741 (define_expand "vec_shr_<mode>"
5742 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5744 (match_operand:SSEMODEI 1 "register_operand" "")
5745 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
5748 operands[0] = gen_lowpart (V1TImode, operands[0]);
5749 operands[1] = gen_lowpart (V1TImode, operands[1]);
5752 (define_insn "*avx_<code><mode>3"
5753 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
5755 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
5756 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
5757 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5758 "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5759 [(set_attr "type" "sseiadd")
5760 (set (attr "prefix_extra")
5761 (if_then_else (match_operand:V16QI 0 "" "")
5763 (const_string "1")))
5764 (set_attr "prefix" "vex")
5765 (set_attr "mode" "TI")])
5767 (define_expand "<code>v16qi3"
5768 [(set (match_operand:V16QI 0 "register_operand" "")
5770 (match_operand:V16QI 1 "nonimmediate_operand" "")
5771 (match_operand:V16QI 2 "nonimmediate_operand" "")))]
5773 "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
5775 (define_insn "*<code>v16qi3"
5776 [(set (match_operand:V16QI 0 "register_operand" "=x")
5778 (match_operand:V16QI 1 "nonimmediate_operand" "%0")
5779 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
5780 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
5781 "p<maxmin_int>b\t{%2, %0|%0, %2}"
5782 [(set_attr "type" "sseiadd")
5783 (set_attr "prefix_data16" "1")
5784 (set_attr "mode" "TI")])
5786 (define_insn "*avx_<code><mode>3"
5787 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
5789 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
5790 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
5791 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5792 "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5793 [(set_attr "type" "sseiadd")
5794 (set (attr "prefix_extra")
5795 (if_then_else (match_operand:V8HI 0 "" "")
5797 (const_string "1")))
5798 (set_attr "prefix" "vex")
5799 (set_attr "mode" "TI")])
5801 (define_expand "<code>v8hi3"
5802 [(set (match_operand:V8HI 0 "register_operand" "")
5804 (match_operand:V8HI 1 "nonimmediate_operand" "")
5805 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
5807 "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
5809 (define_insn "*<code>v8hi3"
5810 [(set (match_operand:V8HI 0 "register_operand" "=x")
5812 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
5813 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
5814 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
5815 "p<maxmin_int>w\t{%2, %0|%0, %2}"
5816 [(set_attr "type" "sseiadd")
5817 (set_attr "prefix_data16" "1")
5818 (set_attr "mode" "TI")])
5820 (define_expand "umaxv8hi3"
5821 [(set (match_operand:V8HI 0 "register_operand" "")
5822 (umax:V8HI (match_operand:V8HI 1 "register_operand" "")
5823 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
5827 ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
5830 rtx op0 = operands[0], op2 = operands[2], op3 = op0;
5831 if (rtx_equal_p (op3, op2))
5832 op3 = gen_reg_rtx (V8HImode);
5833 emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
5834 emit_insn (gen_addv8hi3 (op0, op3, op2));
5839 (define_expand "smax<mode>3"
5840 [(set (match_operand:SSEMODE14 0 "register_operand" "")
5841 (smax:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
5842 (match_operand:SSEMODE14 2 "register_operand" "")))]
5846 ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
5852 xops[0] = operands[0];
5853 xops[1] = operands[1];
5854 xops[2] = operands[2];
5855 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5856 xops[4] = operands[1];
5857 xops[5] = operands[2];
5858 ok = ix86_expand_int_vcond (xops);
5864 (define_insn "*sse4_1_<code><mode>3"
5865 [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
5867 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
5868 (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
5869 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5870 "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
5871 [(set_attr "type" "sseiadd")
5872 (set_attr "prefix_extra" "1")
5873 (set_attr "mode" "TI")])
5875 (define_expand "smaxv2di3"
5876 [(set (match_operand:V2DI 0 "register_operand" "")
5877 (smax:V2DI (match_operand:V2DI 1 "register_operand" "")
5878 (match_operand:V2DI 2 "register_operand" "")))]
5884 xops[0] = operands[0];
5885 xops[1] = operands[1];
5886 xops[2] = operands[2];
5887 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5888 xops[4] = operands[1];
5889 xops[5] = operands[2];
5890 ok = ix86_expand_int_vcond (xops);
5895 (define_expand "umaxv4si3"
5896 [(set (match_operand:V4SI 0 "register_operand" "")
5897 (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
5898 (match_operand:V4SI 2 "register_operand" "")))]
5902 ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
5908 xops[0] = operands[0];
5909 xops[1] = operands[1];
5910 xops[2] = operands[2];
5911 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
5912 xops[4] = operands[1];
5913 xops[5] = operands[2];
5914 ok = ix86_expand_int_vcond (xops);
5920 (define_insn "*sse4_1_<code><mode>3"
5921 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
5923 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
5924 (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
5925 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5926 "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
5927 [(set_attr "type" "sseiadd")
5928 (set_attr "prefix_extra" "1")
5929 (set_attr "mode" "TI")])
5931 (define_expand "umaxv2di3"
5932 [(set (match_operand:V2DI 0 "register_operand" "")
5933 (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
5934 (match_operand:V2DI 2 "register_operand" "")))]
5940 xops[0] = operands[0];
5941 xops[1] = operands[1];
5942 xops[2] = operands[2];
5943 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
5944 xops[4] = operands[1];
5945 xops[5] = operands[2];
5946 ok = ix86_expand_int_vcond (xops);
5951 (define_expand "smin<mode>3"
5952 [(set (match_operand:SSEMODE14 0 "register_operand" "")
5953 (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
5954 (match_operand:SSEMODE14 2 "register_operand" "")))]
5958 ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
5964 xops[0] = operands[0];
5965 xops[1] = operands[2];
5966 xops[2] = operands[1];
5967 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5968 xops[4] = operands[1];
5969 xops[5] = operands[2];
5970 ok = ix86_expand_int_vcond (xops);
5976 (define_expand "sminv2di3"
5977 [(set (match_operand:V2DI 0 "register_operand" "")
5978 (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
5979 (match_operand:V2DI 2 "register_operand" "")))]
5985 xops[0] = operands[0];
5986 xops[1] = operands[2];
5987 xops[2] = operands[1];
5988 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5989 xops[4] = operands[1];
5990 xops[5] = operands[2];
5991 ok = ix86_expand_int_vcond (xops);
5996 (define_expand "umin<mode>3"
5997 [(set (match_operand:SSEMODE24 0 "register_operand" "")
5998 (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
5999 (match_operand:SSEMODE24 2 "register_operand" "")))]
6003 ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
6009 xops[0] = operands[0];
6010 xops[1] = operands[2];
6011 xops[2] = operands[1];
6012 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6013 xops[4] = operands[1];
6014 xops[5] = operands[2];
6015 ok = ix86_expand_int_vcond (xops);
6021 (define_expand "uminv2di3"
6022 [(set (match_operand:V2DI 0 "register_operand" "")
6023 (umin:V2DI (match_operand:V2DI 1 "register_operand" "")
6024 (match_operand:V2DI 2 "register_operand" "")))]
6030 xops[0] = operands[0];
6031 xops[1] = operands[2];
6032 xops[2] = operands[1];
6033 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6034 xops[4] = operands[1];
6035 xops[5] = operands[2];
6036 ok = ix86_expand_int_vcond (xops);
6041 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6043 ;; Parallel integral comparisons
6045 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6047 (define_expand "sse2_eq<mode>3"
6048 [(set (match_operand:SSEMODE124 0 "register_operand" "")
6050 (match_operand:SSEMODE124 1 "nonimmediate_operand" "")
6051 (match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
6052 "TARGET_SSE2 && !TARGET_XOP "
6053 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
6055 (define_insn "*avx_eq<mode>3"
6056 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
6058 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "%x")
6059 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
6060 "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
6061 "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6062 [(set_attr "type" "ssecmp")
6063 (set (attr "prefix_extra")
6064 (if_then_else (match_operand:V2DI 0 "" "")
6066 (const_string "*")))
6067 (set_attr "prefix" "vex")
6068 (set_attr "mode" "TI")])
6070 (define_insn "*sse2_eq<mode>3"
6071 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6073 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
6074 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6075 "TARGET_SSE2 && !TARGET_XOP
6076 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
6077 "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
6078 [(set_attr "type" "ssecmp")
6079 (set_attr "prefix_data16" "1")
6080 (set_attr "mode" "TI")])
6082 (define_expand "sse4_1_eqv2di3"
6083 [(set (match_operand:V2DI 0 "register_operand" "")
6085 (match_operand:V2DI 1 "nonimmediate_operand" "")
6086 (match_operand:V2DI 2 "nonimmediate_operand" "")))]
6088 "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
6090 (define_insn "*sse4_1_eqv2di3"
6091 [(set (match_operand:V2DI 0 "register_operand" "=x")
6093 (match_operand:V2DI 1 "nonimmediate_operand" "%0")
6094 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
6095 "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
6096 "pcmpeqq\t{%2, %0|%0, %2}"
6097 [(set_attr "type" "ssecmp")
6098 (set_attr "prefix_extra" "1")
6099 (set_attr "mode" "TI")])
6101 (define_insn "*avx_gt<mode>3"
6102 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
6104 (match_operand:SSEMODE1248 1 "register_operand" "x")
6105 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
6107 "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6108 [(set_attr "type" "ssecmp")
6109 (set (attr "prefix_extra")
6110 (if_then_else (match_operand:V2DI 0 "" "")
6112 (const_string "*")))
6113 (set_attr "prefix" "vex")
6114 (set_attr "mode" "TI")])
6116 (define_insn "sse2_gt<mode>3"
6117 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6119 (match_operand:SSEMODE124 1 "register_operand" "0")
6120 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6121 "TARGET_SSE2 && !TARGET_XOP"
6122 "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
6123 [(set_attr "type" "ssecmp")
6124 (set_attr "prefix_data16" "1")
6125 (set_attr "mode" "TI")])
6127 (define_insn "sse4_2_gtv2di3"
6128 [(set (match_operand:V2DI 0 "register_operand" "=x")
6130 (match_operand:V2DI 1 "register_operand" "0")
6131 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
6133 "pcmpgtq\t{%2, %0|%0, %2}"
6134 [(set_attr "type" "ssecmp")
6135 (set_attr "prefix_extra" "1")
6136 (set_attr "mode" "TI")])
6138 (define_expand "vcond<mode>"
6139 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
6140 (if_then_else:SSEMODE124C8
6141 (match_operator 3 ""
6142 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
6143 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
6144 (match_operand:SSEMODE124C8 1 "general_operand" "")
6145 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
6148 bool ok = ix86_expand_int_vcond (operands);
6153 (define_expand "vcondu<mode>"
6154 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
6155 (if_then_else:SSEMODE124C8
6156 (match_operator 3 ""
6157 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
6158 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
6159 (match_operand:SSEMODE124C8 1 "general_operand" "")
6160 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
6163 bool ok = ix86_expand_int_vcond (operands);
6168 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6170 ;; Parallel bitwise logical operations
6172 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6174 (define_expand "one_cmpl<mode>2"
6175 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6176 (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
6180 int i, n = GET_MODE_NUNITS (<MODE>mode);
6181 rtvec v = rtvec_alloc (n);
6183 for (i = 0; i < n; ++i)
6184 RTVEC_ELT (v, i) = constm1_rtx;
6186 operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
6189 (define_insn "*avx_andnot<mode>3"
6190 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
6192 (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x"))
6193 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
6195 "vandnps\t{%2, %1, %0|%0, %1, %2}"
6196 [(set_attr "type" "sselog")
6197 (set_attr "prefix" "vex")
6198 (set_attr "mode" "<avxvecpsmode>")])
6200 (define_insn "*sse_andnot<mode>3"
6201 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6203 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
6204 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6205 "(TARGET_SSE && !TARGET_SSE2)"
6206 "andnps\t{%2, %0|%0, %2}"
6207 [(set_attr "type" "sselog")
6208 (set_attr "mode" "V4SF")])
6210 (define_insn "*avx_andnot<mode>3"
6211 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6213 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x"))
6214 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6216 "vpandn\t{%2, %1, %0|%0, %1, %2}"
6217 [(set_attr "type" "sselog")
6218 (set_attr "prefix" "vex")
6219 (set_attr "mode" "TI")])
6221 (define_insn "sse2_andnot<mode>3"
6222 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6224 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
6225 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6227 "pandn\t{%2, %0|%0, %2}"
6228 [(set_attr "type" "sselog")
6229 (set_attr "prefix_data16" "1")
6230 (set_attr "mode" "TI")])
6232 (define_insn "*andnottf3"
6233 [(set (match_operand:TF 0 "register_operand" "=x")
6235 (not:TF (match_operand:TF 1 "register_operand" "0"))
6236 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
6238 "pandn\t{%2, %0|%0, %2}"
6239 [(set_attr "type" "sselog")
6240 (set_attr "prefix_data16" "1")
6241 (set_attr "mode" "TI")])
6243 (define_expand "<code><mode>3"
6244 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6246 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
6247 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
6249 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
6251 (define_insn "*avx_<code><mode>3"
6252 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
6253 (any_logic:AVX256MODEI
6254 (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
6255 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
6257 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6258 "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
6259 [(set_attr "type" "sselog")
6260 (set_attr "prefix" "vex")
6261 (set_attr "mode" "<avxvecpsmode>")])
6263 (define_insn "*sse_<code><mode>3"
6264 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6266 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6267 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6268 "(TARGET_SSE && !TARGET_SSE2)
6269 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6270 "<logic>ps\t{%2, %0|%0, %2}"
6271 [(set_attr "type" "sselog")
6272 (set_attr "mode" "V4SF")])
6274 (define_insn "*avx_<code><mode>3"
6275 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6277 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
6278 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6280 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6281 "vp<logic>\t{%2, %1, %0|%0, %1, %2}"
6282 [(set_attr "type" "sselog")
6283 (set_attr "prefix" "vex")
6284 (set_attr "mode" "TI")])
6286 (define_insn "*sse2_<code><mode>3"
6287 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6289 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6290 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6291 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6292 "p<logic>\t{%2, %0|%0, %2}"
6293 [(set_attr "type" "sselog")
6294 (set_attr "prefix_data16" "1")
6295 (set_attr "mode" "TI")])
6297 (define_expand "<code>tf3"
6298 [(set (match_operand:TF 0 "register_operand" "")
6300 (match_operand:TF 1 "nonimmediate_operand" "")
6301 (match_operand:TF 2 "nonimmediate_operand" "")))]
6303 "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
6305 (define_insn "*<code>tf3"
6306 [(set (match_operand:TF 0 "register_operand" "=x")
6308 (match_operand:TF 1 "nonimmediate_operand" "%0")
6309 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
6310 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
6311 "p<logic>\t{%2, %0|%0, %2}"
6312 [(set_attr "type" "sselog")
6313 (set_attr "prefix_data16" "1")
6314 (set_attr "mode" "TI")])
6316 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6318 ;; Parallel integral element swizzling
6320 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6322 (define_expand "vec_pack_trunc_v8hi"
6323 [(match_operand:V16QI 0 "register_operand" "")
6324 (match_operand:V8HI 1 "register_operand" "")
6325 (match_operand:V8HI 2 "register_operand" "")]
6328 rtx op1 = gen_lowpart (V16QImode, operands[1]);
6329 rtx op2 = gen_lowpart (V16QImode, operands[2]);
6330 ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
6334 (define_expand "vec_pack_trunc_v4si"
6335 [(match_operand:V8HI 0 "register_operand" "")
6336 (match_operand:V4SI 1 "register_operand" "")
6337 (match_operand:V4SI 2 "register_operand" "")]
6340 rtx op1 = gen_lowpart (V8HImode, operands[1]);
6341 rtx op2 = gen_lowpart (V8HImode, operands[2]);
6342 ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
6346 (define_expand "vec_pack_trunc_v2di"
6347 [(match_operand:V4SI 0 "register_operand" "")
6348 (match_operand:V2DI 1 "register_operand" "")
6349 (match_operand:V2DI 2 "register_operand" "")]
6352 rtx op1 = gen_lowpart (V4SImode, operands[1]);
6353 rtx op2 = gen_lowpart (V4SImode, operands[2]);
6354 ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
6358 (define_insn "*avx_packsswb"
6359 [(set (match_operand:V16QI 0 "register_operand" "=x")
6362 (match_operand:V8HI 1 "register_operand" "x"))
6364 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6366 "vpacksswb\t{%2, %1, %0|%0, %1, %2}"
6367 [(set_attr "type" "sselog")
6368 (set_attr "prefix" "vex")
6369 (set_attr "mode" "TI")])
6371 (define_insn "sse2_packsswb"
6372 [(set (match_operand:V16QI 0 "register_operand" "=x")
6375 (match_operand:V8HI 1 "register_operand" "0"))
6377 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6379 "packsswb\t{%2, %0|%0, %2}"
6380 [(set_attr "type" "sselog")
6381 (set_attr "prefix_data16" "1")
6382 (set_attr "mode" "TI")])
6384 (define_insn "*avx_packssdw"
6385 [(set (match_operand:V8HI 0 "register_operand" "=x")
6388 (match_operand:V4SI 1 "register_operand" "x"))
6390 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
6392 "vpackssdw\t{%2, %1, %0|%0, %1, %2}"
6393 [(set_attr "type" "sselog")
6394 (set_attr "prefix" "vex")
6395 (set_attr "mode" "TI")])
6397 (define_insn "sse2_packssdw"
6398 [(set (match_operand:V8HI 0 "register_operand" "=x")
6401 (match_operand:V4SI 1 "register_operand" "0"))
6403 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
6405 "packssdw\t{%2, %0|%0, %2}"
6406 [(set_attr "type" "sselog")
6407 (set_attr "prefix_data16" "1")
6408 (set_attr "mode" "TI")])
6410 (define_insn "*avx_packuswb"
6411 [(set (match_operand:V16QI 0 "register_operand" "=x")
6414 (match_operand:V8HI 1 "register_operand" "x"))
6416 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6418 "vpackuswb\t{%2, %1, %0|%0, %1, %2}"
6419 [(set_attr "type" "sselog")
6420 (set_attr "prefix" "vex")
6421 (set_attr "mode" "TI")])
6423 (define_insn "sse2_packuswb"
6424 [(set (match_operand:V16QI 0 "register_operand" "=x")
6427 (match_operand:V8HI 1 "register_operand" "0"))
6429 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6431 "packuswb\t{%2, %0|%0, %2}"
6432 [(set_attr "type" "sselog")
6433 (set_attr "prefix_data16" "1")
6434 (set_attr "mode" "TI")])
6436 (define_insn "*avx_interleave_highv16qi"
6437 [(set (match_operand:V16QI 0 "register_operand" "=x")
6440 (match_operand:V16QI 1 "register_operand" "x")
6441 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6442 (parallel [(const_int 8) (const_int 24)
6443 (const_int 9) (const_int 25)
6444 (const_int 10) (const_int 26)
6445 (const_int 11) (const_int 27)
6446 (const_int 12) (const_int 28)
6447 (const_int 13) (const_int 29)
6448 (const_int 14) (const_int 30)
6449 (const_int 15) (const_int 31)])))]
6451 "vpunpckhbw\t{%2, %1, %0|%0, %1, %2}"
6452 [(set_attr "type" "sselog")
6453 (set_attr "prefix" "vex")
6454 (set_attr "mode" "TI")])
6456 (define_insn "vec_interleave_highv16qi"
6457 [(set (match_operand:V16QI 0 "register_operand" "=x")
6460 (match_operand:V16QI 1 "register_operand" "0")
6461 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6462 (parallel [(const_int 8) (const_int 24)
6463 (const_int 9) (const_int 25)
6464 (const_int 10) (const_int 26)
6465 (const_int 11) (const_int 27)
6466 (const_int 12) (const_int 28)
6467 (const_int 13) (const_int 29)
6468 (const_int 14) (const_int 30)
6469 (const_int 15) (const_int 31)])))]
6471 "punpckhbw\t{%2, %0|%0, %2}"
6472 [(set_attr "type" "sselog")
6473 (set_attr "prefix_data16" "1")
6474 (set_attr "mode" "TI")])
6476 (define_insn "*avx_interleave_lowv16qi"
6477 [(set (match_operand:V16QI 0 "register_operand" "=x")
6480 (match_operand:V16QI 1 "register_operand" "x")
6481 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6482 (parallel [(const_int 0) (const_int 16)
6483 (const_int 1) (const_int 17)
6484 (const_int 2) (const_int 18)
6485 (const_int 3) (const_int 19)
6486 (const_int 4) (const_int 20)
6487 (const_int 5) (const_int 21)
6488 (const_int 6) (const_int 22)
6489 (const_int 7) (const_int 23)])))]
6491 "vpunpcklbw\t{%2, %1, %0|%0, %1, %2}"
6492 [(set_attr "type" "sselog")
6493 (set_attr "prefix" "vex")
6494 (set_attr "mode" "TI")])
6496 (define_insn "vec_interleave_lowv16qi"
6497 [(set (match_operand:V16QI 0 "register_operand" "=x")
6500 (match_operand:V16QI 1 "register_operand" "0")
6501 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6502 (parallel [(const_int 0) (const_int 16)
6503 (const_int 1) (const_int 17)
6504 (const_int 2) (const_int 18)
6505 (const_int 3) (const_int 19)
6506 (const_int 4) (const_int 20)
6507 (const_int 5) (const_int 21)
6508 (const_int 6) (const_int 22)
6509 (const_int 7) (const_int 23)])))]
6511 "punpcklbw\t{%2, %0|%0, %2}"
6512 [(set_attr "type" "sselog")
6513 (set_attr "prefix_data16" "1")
6514 (set_attr "mode" "TI")])
6516 (define_insn "*avx_interleave_highv8hi"
6517 [(set (match_operand:V8HI 0 "register_operand" "=x")
6520 (match_operand:V8HI 1 "register_operand" "x")
6521 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6522 (parallel [(const_int 4) (const_int 12)
6523 (const_int 5) (const_int 13)
6524 (const_int 6) (const_int 14)
6525 (const_int 7) (const_int 15)])))]
6527 "vpunpckhwd\t{%2, %1, %0|%0, %1, %2}"
6528 [(set_attr "type" "sselog")
6529 (set_attr "prefix" "vex")
6530 (set_attr "mode" "TI")])
6532 (define_insn "vec_interleave_highv8hi"
6533 [(set (match_operand:V8HI 0 "register_operand" "=x")
6536 (match_operand:V8HI 1 "register_operand" "0")
6537 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6538 (parallel [(const_int 4) (const_int 12)
6539 (const_int 5) (const_int 13)
6540 (const_int 6) (const_int 14)
6541 (const_int 7) (const_int 15)])))]
6543 "punpckhwd\t{%2, %0|%0, %2}"
6544 [(set_attr "type" "sselog")
6545 (set_attr "prefix_data16" "1")
6546 (set_attr "mode" "TI")])
6548 (define_insn "*avx_interleave_lowv8hi"
6549 [(set (match_operand:V8HI 0 "register_operand" "=x")
6552 (match_operand:V8HI 1 "register_operand" "x")
6553 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6554 (parallel [(const_int 0) (const_int 8)
6555 (const_int 1) (const_int 9)
6556 (const_int 2) (const_int 10)
6557 (const_int 3) (const_int 11)])))]
6559 "vpunpcklwd\t{%2, %1, %0|%0, %1, %2}"
6560 [(set_attr "type" "sselog")
6561 (set_attr "prefix" "vex")
6562 (set_attr "mode" "TI")])
6564 (define_insn "vec_interleave_lowv8hi"
6565 [(set (match_operand:V8HI 0 "register_operand" "=x")
6568 (match_operand:V8HI 1 "register_operand" "0")
6569 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6570 (parallel [(const_int 0) (const_int 8)
6571 (const_int 1) (const_int 9)
6572 (const_int 2) (const_int 10)
6573 (const_int 3) (const_int 11)])))]
6575 "punpcklwd\t{%2, %0|%0, %2}"
6576 [(set_attr "type" "sselog")
6577 (set_attr "prefix_data16" "1")
6578 (set_attr "mode" "TI")])
6580 (define_insn "*avx_interleave_highv4si"
6581 [(set (match_operand:V4SI 0 "register_operand" "=x")
6584 (match_operand:V4SI 1 "register_operand" "x")
6585 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6586 (parallel [(const_int 2) (const_int 6)
6587 (const_int 3) (const_int 7)])))]
6589 "vpunpckhdq\t{%2, %1, %0|%0, %1, %2}"
6590 [(set_attr "type" "sselog")
6591 (set_attr "prefix" "vex")
6592 (set_attr "mode" "TI")])
6594 (define_insn "vec_interleave_highv4si"
6595 [(set (match_operand:V4SI 0 "register_operand" "=x")
6598 (match_operand:V4SI 1 "register_operand" "0")
6599 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6600 (parallel [(const_int 2) (const_int 6)
6601 (const_int 3) (const_int 7)])))]
6603 "punpckhdq\t{%2, %0|%0, %2}"
6604 [(set_attr "type" "sselog")
6605 (set_attr "prefix_data16" "1")
6606 (set_attr "mode" "TI")])
6608 (define_insn "*avx_interleave_lowv4si"
6609 [(set (match_operand:V4SI 0 "register_operand" "=x")
6612 (match_operand:V4SI 1 "register_operand" "x")
6613 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6614 (parallel [(const_int 0) (const_int 4)
6615 (const_int 1) (const_int 5)])))]
6617 "vpunpckldq\t{%2, %1, %0|%0, %1, %2}"
6618 [(set_attr "type" "sselog")
6619 (set_attr "prefix" "vex")
6620 (set_attr "mode" "TI")])
6622 (define_insn "vec_interleave_lowv4si"
6623 [(set (match_operand:V4SI 0 "register_operand" "=x")
6626 (match_operand:V4SI 1 "register_operand" "0")
6627 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6628 (parallel [(const_int 0) (const_int 4)
6629 (const_int 1) (const_int 5)])))]
6631 "punpckldq\t{%2, %0|%0, %2}"
6632 [(set_attr "type" "sselog")
6633 (set_attr "prefix_data16" "1")
6634 (set_attr "mode" "TI")])
6636 (define_insn "*avx_pinsr<ssevecsize>"
6637 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6638 (vec_merge:SSEMODE124
6639 (vec_duplicate:SSEMODE124
6640 (match_operand:<avxscalarmode> 2 "nonimmediate_operand" "rm"))
6641 (match_operand:SSEMODE124 1 "register_operand" "x")
6642 (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))]
6645 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6646 if (MEM_P (operands[2]))
6647 return "vpinsr<ssevecsize>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6649 return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6651 [(set_attr "type" "sselog")
6652 (set (attr "prefix_extra")
6653 (if_then_else (match_operand:V8HI 0 "" "")
6655 (const_string "1")))
6656 (set_attr "length_immediate" "1")
6657 (set_attr "prefix" "vex")
6658 (set_attr "mode" "TI")])
6660 (define_insn "*sse4_1_pinsrb"
6661 [(set (match_operand:V16QI 0 "register_operand" "=x")
6663 (vec_duplicate:V16QI
6664 (match_operand:QI 2 "nonimmediate_operand" "rm"))
6665 (match_operand:V16QI 1 "register_operand" "0")
6666 (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))]
6669 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6670 if (MEM_P (operands[2]))
6671 return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
6673 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6675 [(set_attr "type" "sselog")
6676 (set_attr "prefix_extra" "1")
6677 (set_attr "length_immediate" "1")
6678 (set_attr "mode" "TI")])
6680 (define_insn "*sse2_pinsrw"
6681 [(set (match_operand:V8HI 0 "register_operand" "=x")
6684 (match_operand:HI 2 "nonimmediate_operand" "rm"))
6685 (match_operand:V8HI 1 "register_operand" "0")
6686 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
6689 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6690 if (MEM_P (operands[2]))
6691 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
6693 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6695 [(set_attr "type" "sselog")
6696 (set_attr "prefix_data16" "1")
6697 (set_attr "length_immediate" "1")
6698 (set_attr "mode" "TI")])
6700 ;; It must come before sse2_loadld since it is preferred.
6701 (define_insn "*sse4_1_pinsrd"
6702 [(set (match_operand:V4SI 0 "register_operand" "=x")
6705 (match_operand:SI 2 "nonimmediate_operand" "rm"))
6706 (match_operand:V4SI 1 "register_operand" "0")
6707 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
6710 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6711 return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
6713 [(set_attr "type" "sselog")
6714 (set_attr "prefix_extra" "1")
6715 (set_attr "length_immediate" "1")
6716 (set_attr "mode" "TI")])
6718 (define_insn "*avx_pinsrq"
6719 [(set (match_operand:V2DI 0 "register_operand" "=x")
6722 (match_operand:DI 2 "nonimmediate_operand" "rm"))
6723 (match_operand:V2DI 1 "register_operand" "x")
6724 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
6725 "TARGET_AVX && TARGET_64BIT"
6727 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6728 return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6730 [(set_attr "type" "sselog")
6731 (set_attr "prefix_extra" "1")
6732 (set_attr "length_immediate" "1")
6733 (set_attr "prefix" "vex")
6734 (set_attr "mode" "TI")])
6736 (define_insn "*sse4_1_pinsrq"
6737 [(set (match_operand:V2DI 0 "register_operand" "=x")
6740 (match_operand:DI 2 "nonimmediate_operand" "rm"))
6741 (match_operand:V2DI 1 "register_operand" "0")
6742 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
6743 "TARGET_SSE4_1 && TARGET_64BIT"
6745 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6746 return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
6748 [(set_attr "type" "sselog")
6749 (set_attr "prefix_rex" "1")
6750 (set_attr "prefix_extra" "1")
6751 (set_attr "length_immediate" "1")
6752 (set_attr "mode" "TI")])
6754 (define_insn "*sse4_1_pextrb_<mode>"
6755 [(set (match_operand:SWI48 0 "register_operand" "=r")
6758 (match_operand:V16QI 1 "register_operand" "x")
6759 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))]
6761 "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
6762 [(set_attr "type" "sselog")
6763 (set_attr "prefix_extra" "1")
6764 (set_attr "length_immediate" "1")
6765 (set_attr "prefix" "maybe_vex")
6766 (set_attr "mode" "TI")])
6768 (define_insn "*sse4_1_pextrb_memory"
6769 [(set (match_operand:QI 0 "memory_operand" "=m")
6771 (match_operand:V16QI 1 "register_operand" "x")
6772 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")])))]
6774 "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
6775 [(set_attr "type" "sselog")
6776 (set_attr "prefix_extra" "1")
6777 (set_attr "length_immediate" "1")
6778 (set_attr "prefix" "maybe_vex")
6779 (set_attr "mode" "TI")])
6781 (define_insn "*sse2_pextrw_<mode>"
6782 [(set (match_operand:SWI48 0 "register_operand" "=r")
6785 (match_operand:V8HI 1 "register_operand" "x")
6786 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
6788 "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
6789 [(set_attr "type" "sselog")
6790 (set_attr "prefix_data16" "1")
6791 (set_attr "length_immediate" "1")
6792 (set_attr "prefix" "maybe_vex")
6793 (set_attr "mode" "TI")])
6795 (define_insn "*sse4_1_pextrw_memory"
6796 [(set (match_operand:HI 0 "memory_operand" "=m")
6798 (match_operand:V8HI 1 "register_operand" "x")
6799 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")])))]
6801 "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
6802 [(set_attr "type" "sselog")
6803 (set_attr "prefix_extra" "1")
6804 (set_attr "length_immediate" "1")
6805 (set_attr "prefix" "maybe_vex")
6806 (set_attr "mode" "TI")])
6808 (define_insn "*sse4_1_pextrd"
6809 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6811 (match_operand:V4SI 1 "register_operand" "x")
6812 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
6814 "%vpextrd\t{%2, %1, %0|%0, %1, %2}"
6815 [(set_attr "type" "sselog")
6816 (set_attr "prefix_extra" "1")
6817 (set_attr "length_immediate" "1")
6818 (set_attr "prefix" "maybe_vex")
6819 (set_attr "mode" "TI")])
6821 (define_insn "*sse4_1_pextrd_zext"
6822 [(set (match_operand:DI 0 "register_operand" "=r")
6825 (match_operand:V4SI 1 "register_operand" "x")
6826 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
6827 "TARGET_64BIT && TARGET_SSE4_1"
6828 "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
6829 [(set_attr "type" "sselog")
6830 (set_attr "prefix_extra" "1")
6831 (set_attr "length_immediate" "1")
6832 (set_attr "prefix" "maybe_vex")
6833 (set_attr "mode" "TI")])
6835 ;; It must come before *vec_extractv2di_1_sse since it is preferred.
6836 (define_insn "*sse4_1_pextrq"
6837 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
6839 (match_operand:V2DI 1 "register_operand" "x")
6840 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")])))]
6841 "TARGET_SSE4_1 && TARGET_64BIT"
6842 "%vpextrq\t{%2, %1, %0|%0, %1, %2}"
6843 [(set_attr "type" "sselog")
6844 (set_attr "prefix_rex" "1")
6845 (set_attr "prefix_extra" "1")
6846 (set_attr "length_immediate" "1")
6847 (set_attr "prefix" "maybe_vex")
6848 (set_attr "mode" "TI")])
6850 (define_expand "sse2_pshufd"
6851 [(match_operand:V4SI 0 "register_operand" "")
6852 (match_operand:V4SI 1 "nonimmediate_operand" "")
6853 (match_operand:SI 2 "const_int_operand" "")]
6856 int mask = INTVAL (operands[2]);
6857 emit_insn (gen_sse2_pshufd_1 (operands[0], operands[1],
6858 GEN_INT ((mask >> 0) & 3),
6859 GEN_INT ((mask >> 2) & 3),
6860 GEN_INT ((mask >> 4) & 3),
6861 GEN_INT ((mask >> 6) & 3)));
6865 (define_insn "sse2_pshufd_1"
6866 [(set (match_operand:V4SI 0 "register_operand" "=x")
6868 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
6869 (parallel [(match_operand 2 "const_0_to_3_operand" "")
6870 (match_operand 3 "const_0_to_3_operand" "")
6871 (match_operand 4 "const_0_to_3_operand" "")
6872 (match_operand 5 "const_0_to_3_operand" "")])))]
6876 mask |= INTVAL (operands[2]) << 0;
6877 mask |= INTVAL (operands[3]) << 2;
6878 mask |= INTVAL (operands[4]) << 4;
6879 mask |= INTVAL (operands[5]) << 6;
6880 operands[2] = GEN_INT (mask);
6882 return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
6884 [(set_attr "type" "sselog1")
6885 (set_attr "prefix_data16" "1")
6886 (set_attr "prefix" "maybe_vex")
6887 (set_attr "length_immediate" "1")
6888 (set_attr "mode" "TI")])
6890 (define_expand "sse2_pshuflw"
6891 [(match_operand:V8HI 0 "register_operand" "")
6892 (match_operand:V8HI 1 "nonimmediate_operand" "")
6893 (match_operand:SI 2 "const_int_operand" "")]
6896 int mask = INTVAL (operands[2]);
6897 emit_insn (gen_sse2_pshuflw_1 (operands[0], operands[1],
6898 GEN_INT ((mask >> 0) & 3),
6899 GEN_INT ((mask >> 2) & 3),
6900 GEN_INT ((mask >> 4) & 3),
6901 GEN_INT ((mask >> 6) & 3)));
6905 (define_insn "sse2_pshuflw_1"
6906 [(set (match_operand:V8HI 0 "register_operand" "=x")
6908 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
6909 (parallel [(match_operand 2 "const_0_to_3_operand" "")
6910 (match_operand 3 "const_0_to_3_operand" "")
6911 (match_operand 4 "const_0_to_3_operand" "")
6912 (match_operand 5 "const_0_to_3_operand" "")
6920 mask |= INTVAL (operands[2]) << 0;
6921 mask |= INTVAL (operands[3]) << 2;
6922 mask |= INTVAL (operands[4]) << 4;
6923 mask |= INTVAL (operands[5]) << 6;
6924 operands[2] = GEN_INT (mask);
6926 return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
6928 [(set_attr "type" "sselog")
6929 (set_attr "prefix_data16" "0")
6930 (set_attr "prefix_rep" "1")
6931 (set_attr "prefix" "maybe_vex")
6932 (set_attr "length_immediate" "1")
6933 (set_attr "mode" "TI")])
6935 (define_expand "sse2_pshufhw"
6936 [(match_operand:V8HI 0 "register_operand" "")
6937 (match_operand:V8HI 1 "nonimmediate_operand" "")
6938 (match_operand:SI 2 "const_int_operand" "")]
6941 int mask = INTVAL (operands[2]);
6942 emit_insn (gen_sse2_pshufhw_1 (operands[0], operands[1],
6943 GEN_INT (((mask >> 0) & 3) + 4),
6944 GEN_INT (((mask >> 2) & 3) + 4),
6945 GEN_INT (((mask >> 4) & 3) + 4),
6946 GEN_INT (((mask >> 6) & 3) + 4)));
6950 (define_insn "sse2_pshufhw_1"
6951 [(set (match_operand:V8HI 0 "register_operand" "=x")
6953 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
6954 (parallel [(const_int 0)
6958 (match_operand 2 "const_4_to_7_operand" "")
6959 (match_operand 3 "const_4_to_7_operand" "")
6960 (match_operand 4 "const_4_to_7_operand" "")
6961 (match_operand 5 "const_4_to_7_operand" "")])))]
6965 mask |= (INTVAL (operands[2]) - 4) << 0;
6966 mask |= (INTVAL (operands[3]) - 4) << 2;
6967 mask |= (INTVAL (operands[4]) - 4) << 4;
6968 mask |= (INTVAL (operands[5]) - 4) << 6;
6969 operands[2] = GEN_INT (mask);
6971 return "%vpshufhw\t{%2, %1, %0|%0, %1, %2}";
6973 [(set_attr "type" "sselog")
6974 (set_attr "prefix_rep" "1")
6975 (set_attr "prefix_data16" "0")
6976 (set_attr "prefix" "maybe_vex")
6977 (set_attr "length_immediate" "1")
6978 (set_attr "mode" "TI")])
6980 (define_expand "sse2_loadd"
6981 [(set (match_operand:V4SI 0 "register_operand" "")
6984 (match_operand:SI 1 "nonimmediate_operand" ""))
6988 "operands[2] = CONST0_RTX (V4SImode);")
6990 (define_insn "*avx_loadld"
6991 [(set (match_operand:V4SI 0 "register_operand" "=x,Yi,x")
6994 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,x"))
6995 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,x")
6999 vmovd\t{%2, %0|%0, %2}
7000 vmovd\t{%2, %0|%0, %2}
7001 vmovss\t{%2, %1, %0|%0, %1, %2}"
7002 [(set_attr "type" "ssemov")
7003 (set_attr "prefix" "vex")
7004 (set_attr "mode" "TI,TI,V4SF")])
7006 (define_insn "sse2_loadld"
7007 [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x")
7010 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x"))
7011 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0")
7015 movd\t{%2, %0|%0, %2}
7016 movd\t{%2, %0|%0, %2}
7017 movss\t{%2, %0|%0, %2}
7018 movss\t{%2, %0|%0, %2}"
7019 [(set_attr "type" "ssemov")
7020 (set_attr "mode" "TI,TI,V4SF,SF")])
7022 (define_insn_and_split "sse2_stored"
7023 [(set (match_operand:SI 0 "nonimmediate_operand" "=mx,r")
7025 (match_operand:V4SI 1 "register_operand" "x,Yi")
7026 (parallel [(const_int 0)])))]
7029 "&& reload_completed
7030 && (TARGET_INTER_UNIT_MOVES
7031 || MEM_P (operands [0])
7032 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
7033 [(set (match_dup 0) (match_dup 1))]
7034 "operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));")
7036 (define_insn_and_split "*vec_ext_v4si_mem"
7037 [(set (match_operand:SI 0 "register_operand" "=r")
7039 (match_operand:V4SI 1 "memory_operand" "o")
7040 (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
7046 int i = INTVAL (operands[2]);
7048 emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
7052 (define_expand "sse_storeq"
7053 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7055 (match_operand:V2DI 1 "register_operand" "")
7056 (parallel [(const_int 0)])))]
7059 (define_insn "*sse2_storeq_rex64"
7060 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
7062 (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
7063 (parallel [(const_int 0)])))]
7064 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7068 %vmov{q}\t{%1, %0|%0, %1}"
7069 [(set_attr "type" "*,*,imov")
7070 (set_attr "prefix" "*,*,maybe_vex")
7071 (set_attr "mode" "*,*,DI")])
7073 (define_insn "*sse2_storeq"
7074 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
7076 (match_operand:V2DI 1 "register_operand" "x")
7077 (parallel [(const_int 0)])))]
7082 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7084 (match_operand:V2DI 1 "register_operand" "")
7085 (parallel [(const_int 0)])))]
7088 && (TARGET_INTER_UNIT_MOVES
7089 || MEM_P (operands [0])
7090 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
7091 [(set (match_dup 0) (match_dup 1))]
7092 "operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
7094 (define_insn "*vec_extractv2di_1_rex64_avx"
7095 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
7097 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o,o")
7098 (parallel [(const_int 1)])))]
7101 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7103 vmovhps\t{%1, %0|%0, %1}
7104 vpsrldq\t{$8, %1, %0|%0, %1, 8}
7105 vmovq\t{%H1, %0|%0, %H1}
7106 vmov{q}\t{%H1, %0|%0, %H1}"
7107 [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
7108 (set_attr "length_immediate" "*,1,*,*")
7109 (set_attr "memory" "*,none,*,*")
7110 (set_attr "prefix" "vex")
7111 (set_attr "mode" "V2SF,TI,TI,DI")])
7113 (define_insn "*vec_extractv2di_1_rex64"
7114 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
7116 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o")
7117 (parallel [(const_int 1)])))]
7118 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7120 movhps\t{%1, %0|%0, %1}
7121 psrldq\t{$8, %0|%0, 8}
7122 movq\t{%H1, %0|%0, %H1}
7123 mov{q}\t{%H1, %0|%0, %H1}"
7124 [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
7125 (set_attr "length_immediate" "*,1,*,*")
7126 (set_attr "memory" "*,none,*,*")
7127 (set_attr "mode" "V2SF,TI,TI,DI")])
7129 (define_insn "*vec_extractv2di_1_avx"
7130 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7132 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
7133 (parallel [(const_int 1)])))]
7136 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7138 vmovhps\t{%1, %0|%0, %1}
7139 vpsrldq\t{$8, %1, %0|%0, %1, 8}
7140 vmovq\t{%H1, %0|%0, %H1}"
7141 [(set_attr "type" "ssemov,sseishft1,ssemov")
7142 (set_attr "length_immediate" "*,1,*")
7143 (set_attr "memory" "*,none,*")
7144 (set_attr "prefix" "vex")
7145 (set_attr "mode" "V2SF,TI,TI")])
7147 (define_insn "*vec_extractv2di_1_sse2"
7148 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7150 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o")
7151 (parallel [(const_int 1)])))]
7153 && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7155 movhps\t{%1, %0|%0, %1}
7156 psrldq\t{$8, %0|%0, 8}
7157 movq\t{%H1, %0|%0, %H1}"
7158 [(set_attr "type" "ssemov,sseishft1,ssemov")
7159 (set_attr "length_immediate" "*,1,*")
7160 (set_attr "memory" "*,none,*")
7161 (set_attr "mode" "V2SF,TI,TI")])
7163 ;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
7164 (define_insn "*vec_extractv2di_1_sse"
7165 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7167 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
7168 (parallel [(const_int 1)])))]
7169 "!TARGET_SSE2 && TARGET_SSE
7170 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7172 movhps\t{%1, %0|%0, %1}
7173 movhlps\t{%1, %0|%0, %1}
7174 movlps\t{%H1, %0|%0, %H1}"
7175 [(set_attr "type" "ssemov")
7176 (set_attr "mode" "V2SF,V4SF,V2SF")])
7178 (define_insn "*vec_dupv4si_avx"
7179 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
7181 (match_operand:SI 1 "register_operand" "x,m")))]
7184 vpshufd\t{$0, %1, %0|%0, %1, 0}
7185 vbroadcastss\t{%1, %0|%0, %1}"
7186 [(set_attr "type" "sselog1,ssemov")
7187 (set_attr "length_immediate" "1,0")
7188 (set_attr "prefix_extra" "0,1")
7189 (set_attr "prefix" "vex")
7190 (set_attr "mode" "TI,V4SF")])
7192 (define_insn "*vec_dupv4si"
7193 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x")
7195 (match_operand:SI 1 "register_operand" " Y2,0")))]
7198 %vpshufd\t{$0, %1, %0|%0, %1, 0}
7199 shufps\t{$0, %0, %0|%0, %0, 0}"
7200 [(set_attr "type" "sselog1")
7201 (set_attr "length_immediate" "1")
7202 (set_attr "mode" "TI,V4SF")])
7204 (define_insn "*vec_dupv2di_avx"
7205 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
7207 (match_operand:DI 1 "nonimmediate_operand" " x,m")))]
7210 vpunpcklqdq\t{%1, %1, %0|%0, %1, %1}
7211 vmovddup\t{%1, %0|%0, %1}"
7212 [(set_attr "type" "sselog1")
7213 (set_attr "prefix" "vex")
7214 (set_attr "mode" "TI,DF")])
7216 (define_insn "*vec_dupv2di_sse3"
7217 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
7219 (match_operand:DI 1 "nonimmediate_operand" " 0,m")))]
7223 movddup\t{%1, %0|%0, %1}"
7224 [(set_attr "type" "sselog1")
7225 (set_attr "mode" "TI,DF")])
7227 (define_insn "*vec_dupv2di"
7228 [(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
7230 (match_operand:DI 1 "register_operand" " 0 ,0")))]
7235 [(set_attr "type" "sselog1,ssemov")
7236 (set_attr "mode" "TI,V4SF")])
7238 (define_insn "*vec_concatv2si_avx"
7239 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
7241 (match_operand:SI 1 "nonimmediate_operand" "x ,x,rm, 0 ,rm")
7242 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
7245 vpinsrd\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
7246 vpunpckldq\t{%2, %1, %0|%0, %1, %2}
7247 vmovd\t{%1, %0|%0, %1}
7248 punpckldq\t{%2, %0|%0, %2}
7249 movd\t{%1, %0|%0, %1}"
7250 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
7251 (set_attr "prefix_extra" "1,*,*,*,*")
7252 (set_attr "length_immediate" "1,*,*,*,*")
7253 (set (attr "prefix")
7254 (if_then_else (eq_attr "alternative" "3,4")
7255 (const_string "orig")
7256 (const_string "vex")))
7257 (set_attr "mode" "TI,TI,TI,DI,DI")])
7259 (define_insn "*vec_concatv2si_sse4_1"
7260 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
7262 (match_operand:SI 1 "nonimmediate_operand" "0 ,0,rm, 0 ,rm")
7263 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
7266 pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
7267 punpckldq\t{%2, %0|%0, %2}
7268 movd\t{%1, %0|%0, %1}
7269 punpckldq\t{%2, %0|%0, %2}
7270 movd\t{%1, %0|%0, %1}"
7271 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
7272 (set_attr "prefix_extra" "1,*,*,*,*")
7273 (set_attr "length_immediate" "1,*,*,*,*")
7274 (set_attr "mode" "TI,TI,TI,DI,DI")])
7276 ;; ??? In theory we can match memory for the MMX alternative, but allowing
7277 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
7278 ;; alternatives pretty much forces the MMX alternative to be chosen.
7279 (define_insn "*vec_concatv2si_sse2"
7280 [(set (match_operand:V2SI 0 "register_operand" "=x,x ,*y,*y")
7282 (match_operand:SI 1 "nonimmediate_operand" " 0,rm, 0,rm")
7283 (match_operand:SI 2 "reg_or_0_operand" " x,C ,*y, C")))]
7286 punpckldq\t{%2, %0|%0, %2}
7287 movd\t{%1, %0|%0, %1}
7288 punpckldq\t{%2, %0|%0, %2}
7289 movd\t{%1, %0|%0, %1}"
7290 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
7291 (set_attr "mode" "TI,TI,DI,DI")])
7293 (define_insn "*vec_concatv2si_sse"
7294 [(set (match_operand:V2SI 0 "register_operand" "=x,x,*y,*y")
7296 (match_operand:SI 1 "nonimmediate_operand" " 0,m, 0,*rm")
7297 (match_operand:SI 2 "reg_or_0_operand" " x,C,*y,C")))]
7300 unpcklps\t{%2, %0|%0, %2}
7301 movss\t{%1, %0|%0, %1}
7302 punpckldq\t{%2, %0|%0, %2}
7303 movd\t{%1, %0|%0, %1}"
7304 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
7305 (set_attr "mode" "V4SF,V4SF,DI,DI")])
7307 (define_insn "*vec_concatv4si_1_avx"
7308 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
7310 (match_operand:V2SI 1 "register_operand" " x,x")
7311 (match_operand:V2SI 2 "nonimmediate_operand" " x,m")))]
7314 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7315 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7316 [(set_attr "type" "sselog,ssemov")
7317 (set_attr "prefix" "vex")
7318 (set_attr "mode" "TI,V2SF")])
7320 (define_insn "*vec_concatv4si_1"
7321 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x")
7323 (match_operand:V2SI 1 "register_operand" " 0 ,0,0")
7324 (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))]
7327 punpcklqdq\t{%2, %0|%0, %2}
7328 movlhps\t{%2, %0|%0, %2}
7329 movhps\t{%2, %0|%0, %2}"
7330 [(set_attr "type" "sselog,ssemov,ssemov")
7331 (set_attr "mode" "TI,V4SF,V2SF")])
7333 (define_insn "*vec_concatv2di_avx"
7334 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,x,x")
7336 (match_operand:DI 1 "nonimmediate_operand" " m,*y,x,x")
7337 (match_operand:DI 2 "vector_move_operand" " C, C,x,m")))]
7338 "!TARGET_64BIT && TARGET_AVX"
7340 vmovq\t{%1, %0|%0, %1}
7341 movq2dq\t{%1, %0|%0, %1}
7342 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7343 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7344 [(set_attr "type" "ssemov,ssemov,sselog,ssemov")
7345 (set (attr "prefix")
7346 (if_then_else (eq_attr "alternative" "1")
7347 (const_string "orig")
7348 (const_string "vex")))
7349 (set_attr "mode" "TI,TI,TI,V2SF")])
7351 (define_insn "vec_concatv2di"
7352 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,?Y2,Y2,x,x")
7354 (match_operand:DI 1 "nonimmediate_operand" " mY2,*y ,0 ,0,0")
7355 (match_operand:DI 2 "vector_move_operand" " C , C,Y2,x,m")))]
7356 "!TARGET_64BIT && TARGET_SSE"
7358 movq\t{%1, %0|%0, %1}
7359 movq2dq\t{%1, %0|%0, %1}
7360 punpcklqdq\t{%2, %0|%0, %2}
7361 movlhps\t{%2, %0|%0, %2}
7362 movhps\t{%2, %0|%0, %2}"
7363 [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov")
7364 (set_attr "mode" "TI,TI,TI,V4SF,V2SF")])
7366 (define_insn "*vec_concatv2di_rex64_avx"
7367 [(set (match_operand:V2DI 0 "register_operand" "=x,x,Yi,!x,x,x")
7369 (match_operand:DI 1 "nonimmediate_operand" " x,m,r ,*y,x,x")
7370 (match_operand:DI 2 "vector_move_operand" "rm,C,C ,C ,x,m")))]
7371 "TARGET_64BIT && TARGET_AVX"
7373 vpinsrq\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
7374 vmovq\t{%1, %0|%0, %1}
7375 vmovq\t{%1, %0|%0, %1}
7376 movq2dq\t{%1, %0|%0, %1}
7377 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7378 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7379 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
7380 (set_attr "prefix_extra" "1,*,*,*,*,*")
7381 (set_attr "length_immediate" "1,*,*,*,*,*")
7382 (set (attr "prefix")
7383 (if_then_else (eq_attr "alternative" "3")
7384 (const_string "orig")
7385 (const_string "vex")))
7386 (set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
7388 (define_insn "*vec_concatv2di_rex64_sse4_1"
7389 [(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
7391 (match_operand:DI 1 "nonimmediate_operand" " 0 ,mx,r ,*y,0,0,0")
7392 (match_operand:DI 2 "vector_move_operand" " rm,C ,C ,C ,x,x,m")))]
7393 "TARGET_64BIT && TARGET_SSE4_1"
7395 pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
7396 movq\t{%1, %0|%0, %1}
7397 movd\t{%1, %0|%0, %1}
7398 movq2dq\t{%1, %0|%0, %1}
7399 punpcklqdq\t{%2, %0|%0, %2}
7400 movlhps\t{%2, %0|%0, %2}
7401 movhps\t{%2, %0|%0, %2}"
7402 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
7403 (set_attr "prefix_rex" "1,*,1,*,*,*,*")
7404 (set_attr "prefix_extra" "1,*,*,*,*,*,*")
7405 (set_attr "length_immediate" "1,*,*,*,*,*,*")
7406 (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
7408 (define_insn "*vec_concatv2di_rex64_sse"
7409 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
7411 (match_operand:DI 1 "nonimmediate_operand" " mY2,r ,*y ,0 ,0,0")
7412 (match_operand:DI 2 "vector_move_operand" " C ,C ,C ,Y2,x,m")))]
7413 "TARGET_64BIT && TARGET_SSE"
7415 movq\t{%1, %0|%0, %1}
7416 movd\t{%1, %0|%0, %1}
7417 movq2dq\t{%1, %0|%0, %1}
7418 punpcklqdq\t{%2, %0|%0, %2}
7419 movlhps\t{%2, %0|%0, %2}
7420 movhps\t{%2, %0|%0, %2}"
7421 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
7422 (set_attr "prefix_rex" "*,1,*,*,*,*")
7423 (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
7425 (define_expand "vec_unpacku_hi_v16qi"
7426 [(match_operand:V8HI 0 "register_operand" "")
7427 (match_operand:V16QI 1 "register_operand" "")]
7431 ix86_expand_sse4_unpack (operands, true, true);
7433 ix86_expand_sse_unpack (operands, true, true);
7437 (define_expand "vec_unpacks_hi_v16qi"
7438 [(match_operand:V8HI 0 "register_operand" "")
7439 (match_operand:V16QI 1 "register_operand" "")]
7443 ix86_expand_sse4_unpack (operands, false, true);
7445 ix86_expand_sse_unpack (operands, false, true);
7449 (define_expand "vec_unpacku_lo_v16qi"
7450 [(match_operand:V8HI 0 "register_operand" "")
7451 (match_operand:V16QI 1 "register_operand" "")]
7455 ix86_expand_sse4_unpack (operands, true, false);
7457 ix86_expand_sse_unpack (operands, true, false);
7461 (define_expand "vec_unpacks_lo_v16qi"
7462 [(match_operand:V8HI 0 "register_operand" "")
7463 (match_operand:V16QI 1 "register_operand" "")]
7467 ix86_expand_sse4_unpack (operands, false, false);
7469 ix86_expand_sse_unpack (operands, false, false);
7473 (define_expand "vec_unpacku_hi_v8hi"
7474 [(match_operand:V4SI 0 "register_operand" "")
7475 (match_operand:V8HI 1 "register_operand" "")]
7479 ix86_expand_sse4_unpack (operands, true, true);
7481 ix86_expand_sse_unpack (operands, true, true);
7485 (define_expand "vec_unpacks_hi_v8hi"
7486 [(match_operand:V4SI 0 "register_operand" "")
7487 (match_operand:V8HI 1 "register_operand" "")]
7491 ix86_expand_sse4_unpack (operands, false, true);
7493 ix86_expand_sse_unpack (operands, false, true);
7497 (define_expand "vec_unpacku_lo_v8hi"
7498 [(match_operand:V4SI 0 "register_operand" "")
7499 (match_operand:V8HI 1 "register_operand" "")]
7503 ix86_expand_sse4_unpack (operands, true, false);
7505 ix86_expand_sse_unpack (operands, true, false);
7509 (define_expand "vec_unpacks_lo_v8hi"
7510 [(match_operand:V4SI 0 "register_operand" "")
7511 (match_operand:V8HI 1 "register_operand" "")]
7515 ix86_expand_sse4_unpack (operands, false, false);
7517 ix86_expand_sse_unpack (operands, false, false);
7521 (define_expand "vec_unpacku_hi_v4si"
7522 [(match_operand:V2DI 0 "register_operand" "")
7523 (match_operand:V4SI 1 "register_operand" "")]
7527 ix86_expand_sse4_unpack (operands, true, true);
7529 ix86_expand_sse_unpack (operands, true, true);
7533 (define_expand "vec_unpacks_hi_v4si"
7534 [(match_operand:V2DI 0 "register_operand" "")
7535 (match_operand:V4SI 1 "register_operand" "")]
7539 ix86_expand_sse4_unpack (operands, false, true);
7541 ix86_expand_sse_unpack (operands, false, true);
7545 (define_expand "vec_unpacku_lo_v4si"
7546 [(match_operand:V2DI 0 "register_operand" "")
7547 (match_operand:V4SI 1 "register_operand" "")]
7551 ix86_expand_sse4_unpack (operands, true, false);
7553 ix86_expand_sse_unpack (operands, true, false);
7557 (define_expand "vec_unpacks_lo_v4si"
7558 [(match_operand:V2DI 0 "register_operand" "")
7559 (match_operand:V4SI 1 "register_operand" "")]
7563 ix86_expand_sse4_unpack (operands, false, false);
7565 ix86_expand_sse_unpack (operands, false, false);
7569 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7573 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7575 (define_expand "sse2_uavgv16qi3"
7576 [(set (match_operand:V16QI 0 "register_operand" "")
7582 (match_operand:V16QI 1 "nonimmediate_operand" ""))
7584 (match_operand:V16QI 2 "nonimmediate_operand" "")))
7585 (const_vector:V16QI [(const_int 1) (const_int 1)
7586 (const_int 1) (const_int 1)
7587 (const_int 1) (const_int 1)
7588 (const_int 1) (const_int 1)
7589 (const_int 1) (const_int 1)
7590 (const_int 1) (const_int 1)
7591 (const_int 1) (const_int 1)
7592 (const_int 1) (const_int 1)]))
7595 "ix86_fixup_binary_operands_no_copy (PLUS, V16QImode, operands);")
7597 (define_insn "*avx_uavgv16qi3"
7598 [(set (match_operand:V16QI 0 "register_operand" "=x")
7604 (match_operand:V16QI 1 "nonimmediate_operand" "%x"))
7606 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
7607 (const_vector:V16QI [(const_int 1) (const_int 1)
7608 (const_int 1) (const_int 1)
7609 (const_int 1) (const_int 1)
7610 (const_int 1) (const_int 1)
7611 (const_int 1) (const_int 1)
7612 (const_int 1) (const_int 1)
7613 (const_int 1) (const_int 1)
7614 (const_int 1) (const_int 1)]))
7616 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
7617 "vpavgb\t{%2, %1, %0|%0, %1, %2}"
7618 [(set_attr "type" "sseiadd")
7619 (set_attr "prefix" "vex")
7620 (set_attr "mode" "TI")])
7622 (define_insn "*sse2_uavgv16qi3"
7623 [(set (match_operand:V16QI 0 "register_operand" "=x")
7629 (match_operand:V16QI 1 "nonimmediate_operand" "%0"))
7631 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
7632 (const_vector:V16QI [(const_int 1) (const_int 1)
7633 (const_int 1) (const_int 1)
7634 (const_int 1) (const_int 1)
7635 (const_int 1) (const_int 1)
7636 (const_int 1) (const_int 1)
7637 (const_int 1) (const_int 1)
7638 (const_int 1) (const_int 1)
7639 (const_int 1) (const_int 1)]))
7641 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
7642 "pavgb\t{%2, %0|%0, %2}"
7643 [(set_attr "type" "sseiadd")
7644 (set_attr "prefix_data16" "1")
7645 (set_attr "mode" "TI")])
7647 (define_expand "sse2_uavgv8hi3"
7648 [(set (match_operand:V8HI 0 "register_operand" "")
7654 (match_operand:V8HI 1 "nonimmediate_operand" ""))
7656 (match_operand:V8HI 2 "nonimmediate_operand" "")))
7657 (const_vector:V8HI [(const_int 1) (const_int 1)
7658 (const_int 1) (const_int 1)
7659 (const_int 1) (const_int 1)
7660 (const_int 1) (const_int 1)]))
7663 "ix86_fixup_binary_operands_no_copy (PLUS, V8HImode, operands);")
7665 (define_insn "*avx_uavgv8hi3"
7666 [(set (match_operand:V8HI 0 "register_operand" "=x")
7672 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
7674 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
7675 (const_vector:V8HI [(const_int 1) (const_int 1)
7676 (const_int 1) (const_int 1)
7677 (const_int 1) (const_int 1)
7678 (const_int 1) (const_int 1)]))
7680 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
7681 "vpavgw\t{%2, %1, %0|%0, %1, %2}"
7682 [(set_attr "type" "sseiadd")
7683 (set_attr "prefix" "vex")
7684 (set_attr "mode" "TI")])
7686 (define_insn "*sse2_uavgv8hi3"
7687 [(set (match_operand:V8HI 0 "register_operand" "=x")
7693 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
7695 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
7696 (const_vector:V8HI [(const_int 1) (const_int 1)
7697 (const_int 1) (const_int 1)
7698 (const_int 1) (const_int 1)
7699 (const_int 1) (const_int 1)]))
7701 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
7702 "pavgw\t{%2, %0|%0, %2}"
7703 [(set_attr "type" "sseiadd")
7704 (set_attr "prefix_data16" "1")
7705 (set_attr "mode" "TI")])
7707 ;; The correct representation for this is absolutely enormous, and
7708 ;; surely not generally useful.
7709 (define_insn "*avx_psadbw"
7710 [(set (match_operand:V2DI 0 "register_operand" "=x")
7711 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "x")
7712 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
7715 "vpsadbw\t{%2, %1, %0|%0, %1, %2}"
7716 [(set_attr "type" "sseiadd")
7717 (set_attr "prefix" "vex")
7718 (set_attr "mode" "TI")])
7720 (define_insn "sse2_psadbw"
7721 [(set (match_operand:V2DI 0 "register_operand" "=x")
7722 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
7723 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
7726 "psadbw\t{%2, %0|%0, %2}"
7727 [(set_attr "type" "sseiadd")
7728 (set_attr "atom_unit" "simul")
7729 (set_attr "prefix_data16" "1")
7730 (set_attr "mode" "TI")])
7732 (define_insn "avx_movmsk<ssemodesuffix>256"
7733 [(set (match_operand:SI 0 "register_operand" "=r")
7735 [(match_operand:AVX256MODEF2P 1 "register_operand" "x")]
7737 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
7738 "vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
7739 [(set_attr "type" "ssecvt")
7740 (set_attr "prefix" "vex")
7741 (set_attr "mode" "<MODE>")])
7743 (define_insn "<sse>_movmsk<ssemodesuffix>"
7744 [(set (match_operand:SI 0 "register_operand" "=r")
7746 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
7748 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
7749 "%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
7750 [(set_attr "type" "ssemov")
7751 (set_attr "prefix" "maybe_vex")
7752 (set_attr "mode" "<MODE>")])
7754 (define_insn "sse2_pmovmskb"
7755 [(set (match_operand:SI 0 "register_operand" "=r")
7756 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
7759 "%vpmovmskb\t{%1, %0|%0, %1}"
7760 [(set_attr "type" "ssemov")
7761 (set_attr "prefix_data16" "1")
7762 (set_attr "prefix" "maybe_vex")
7763 (set_attr "mode" "SI")])
7765 (define_expand "sse2_maskmovdqu"
7766 [(set (match_operand:V16QI 0 "memory_operand" "")
7767 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
7768 (match_operand:V16QI 2 "register_operand" "")
7773 (define_insn "*sse2_maskmovdqu"
7774 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
7775 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
7776 (match_operand:V16QI 2 "register_operand" "x")
7777 (mem:V16QI (match_dup 0))]
7779 "TARGET_SSE2 && !TARGET_64BIT"
7780 ;; @@@ check ordering of operands in intel/nonintel syntax
7781 "%vmaskmovdqu\t{%2, %1|%1, %2}"
7782 [(set_attr "type" "ssemov")
7783 (set_attr "prefix_data16" "1")
7784 ;; The implicit %rdi operand confuses default length_vex computation.
7785 (set_attr "length_vex" "3")
7786 (set_attr "prefix" "maybe_vex")
7787 (set_attr "mode" "TI")])
7789 (define_insn "*sse2_maskmovdqu_rex64"
7790 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
7791 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
7792 (match_operand:V16QI 2 "register_operand" "x")
7793 (mem:V16QI (match_dup 0))]
7795 "TARGET_SSE2 && TARGET_64BIT"
7796 ;; @@@ check ordering of operands in intel/nonintel syntax
7797 "%vmaskmovdqu\t{%2, %1|%1, %2}"
7798 [(set_attr "type" "ssemov")
7799 (set_attr "prefix_data16" "1")
7800 ;; The implicit %rdi operand confuses default length_vex computation.
7801 (set (attr "length_vex")
7802 (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
7803 (set_attr "prefix" "maybe_vex")
7804 (set_attr "mode" "TI")])
7806 (define_insn "sse_ldmxcsr"
7807 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
7811 [(set_attr "type" "sse")
7812 (set_attr "atom_sse_attr" "mxcsr")
7813 (set_attr "prefix" "maybe_vex")
7814 (set_attr "memory" "load")])
7816 (define_insn "sse_stmxcsr"
7817 [(set (match_operand:SI 0 "memory_operand" "=m")
7818 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
7821 [(set_attr "type" "sse")
7822 (set_attr "atom_sse_attr" "mxcsr")
7823 (set_attr "prefix" "maybe_vex")
7824 (set_attr "memory" "store")])
7826 (define_expand "sse_sfence"
7828 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
7829 "TARGET_SSE || TARGET_3DNOW_A"
7831 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7832 MEM_VOLATILE_P (operands[0]) = 1;
7835 (define_insn "*sse_sfence"
7836 [(set (match_operand:BLK 0 "" "")
7837 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
7838 "TARGET_SSE || TARGET_3DNOW_A"
7840 [(set_attr "type" "sse")
7841 (set_attr "length_address" "0")
7842 (set_attr "atom_sse_attr" "fence")
7843 (set_attr "memory" "unknown")])
7845 (define_insn "sse2_clflush"
7846 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
7850 [(set_attr "type" "sse")
7851 (set_attr "atom_sse_attr" "fence")
7852 (set_attr "memory" "unknown")])
7854 (define_expand "sse2_mfence"
7856 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
7859 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7860 MEM_VOLATILE_P (operands[0]) = 1;
7863 (define_insn "*sse2_mfence"
7864 [(set (match_operand:BLK 0 "" "")
7865 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
7866 "TARGET_64BIT || TARGET_SSE2"
7868 [(set_attr "type" "sse")
7869 (set_attr "length_address" "0")
7870 (set_attr "atom_sse_attr" "fence")
7871 (set_attr "memory" "unknown")])
7873 (define_expand "sse2_lfence"
7875 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
7878 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7879 MEM_VOLATILE_P (operands[0]) = 1;
7882 (define_insn "*sse2_lfence"
7883 [(set (match_operand:BLK 0 "" "")
7884 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
7887 [(set_attr "type" "sse")
7888 (set_attr "length_address" "0")
7889 (set_attr "atom_sse_attr" "lfence")
7890 (set_attr "memory" "unknown")])
7892 (define_insn "sse3_mwait"
7893 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
7894 (match_operand:SI 1 "register_operand" "c")]
7897 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.
7898 ;; Since 32bit register operands are implicitly zero extended to 64bit,
7899 ;; we only need to set up 32bit registers.
7901 [(set_attr "length" "3")])
7903 (define_insn "sse3_monitor"
7904 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
7905 (match_operand:SI 1 "register_operand" "c")
7906 (match_operand:SI 2 "register_operand" "d")]
7908 "TARGET_SSE3 && !TARGET_64BIT"
7909 "monitor\t%0, %1, %2"
7910 [(set_attr "length" "3")])
7912 (define_insn "sse3_monitor64"
7913 [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
7914 (match_operand:SI 1 "register_operand" "c")
7915 (match_operand:SI 2 "register_operand" "d")]
7917 "TARGET_SSE3 && TARGET_64BIT"
7918 ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
7919 ;; RCX and RDX are used. Since 32bit register operands are implicitly
7920 ;; zero extended to 64bit, we only need to set up 32bit registers.
7922 [(set_attr "length" "3")])
7924 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7926 ;; SSSE3 instructions
7928 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7930 (define_insn "*avx_phaddwv8hi3"
7931 [(set (match_operand:V8HI 0 "register_operand" "=x")
7937 (match_operand:V8HI 1 "register_operand" "x")
7938 (parallel [(const_int 0)]))
7939 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7941 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7942 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7945 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7946 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7948 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7949 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7954 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7955 (parallel [(const_int 0)]))
7956 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7958 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7959 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7962 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7963 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7965 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7966 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7968 "vphaddw\t{%2, %1, %0|%0, %1, %2}"
7969 [(set_attr "type" "sseiadd")
7970 (set_attr "prefix_extra" "1")
7971 (set_attr "prefix" "vex")
7972 (set_attr "mode" "TI")])
7974 (define_insn "ssse3_phaddwv8hi3"
7975 [(set (match_operand:V8HI 0 "register_operand" "=x")
7981 (match_operand:V8HI 1 "register_operand" "0")
7982 (parallel [(const_int 0)]))
7983 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7985 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7986 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7989 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7990 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7992 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7993 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7998 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7999 (parallel [(const_int 0)]))
8000 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8002 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8003 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8006 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8007 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8009 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8010 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8012 "phaddw\t{%2, %0|%0, %2}"
8013 [(set_attr "type" "sseiadd")
8014 (set_attr "atom_unit" "complex")
8015 (set_attr "prefix_data16" "1")
8016 (set_attr "prefix_extra" "1")
8017 (set_attr "mode" "TI")])
8019 (define_insn "ssse3_phaddwv4hi3"
8020 [(set (match_operand:V4HI 0 "register_operand" "=y")
8025 (match_operand:V4HI 1 "register_operand" "0")
8026 (parallel [(const_int 0)]))
8027 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8029 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8030 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8034 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8035 (parallel [(const_int 0)]))
8036 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8038 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8039 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8041 "phaddw\t{%2, %0|%0, %2}"
8042 [(set_attr "type" "sseiadd")
8043 (set_attr "atom_unit" "complex")
8044 (set_attr "prefix_extra" "1")
8045 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8046 (set_attr "mode" "DI")])
8048 (define_insn "*avx_phadddv4si3"
8049 [(set (match_operand:V4SI 0 "register_operand" "=x")
8054 (match_operand:V4SI 1 "register_operand" "x")
8055 (parallel [(const_int 0)]))
8056 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8058 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8059 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8063 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8064 (parallel [(const_int 0)]))
8065 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8067 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8068 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8070 "vphaddd\t{%2, %1, %0|%0, %1, %2}"
8071 [(set_attr "type" "sseiadd")
8072 (set_attr "prefix_extra" "1")
8073 (set_attr "prefix" "vex")
8074 (set_attr "mode" "TI")])
8076 (define_insn "ssse3_phadddv4si3"
8077 [(set (match_operand:V4SI 0 "register_operand" "=x")
8082 (match_operand:V4SI 1 "register_operand" "0")
8083 (parallel [(const_int 0)]))
8084 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8086 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8087 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8091 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8092 (parallel [(const_int 0)]))
8093 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8095 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8096 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8098 "phaddd\t{%2, %0|%0, %2}"
8099 [(set_attr "type" "sseiadd")
8100 (set_attr "atom_unit" "complex")
8101 (set_attr "prefix_data16" "1")
8102 (set_attr "prefix_extra" "1")
8103 (set_attr "mode" "TI")])
8105 (define_insn "ssse3_phadddv2si3"
8106 [(set (match_operand:V2SI 0 "register_operand" "=y")
8110 (match_operand:V2SI 1 "register_operand" "0")
8111 (parallel [(const_int 0)]))
8112 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8115 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
8116 (parallel [(const_int 0)]))
8117 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
8119 "phaddd\t{%2, %0|%0, %2}"
8120 [(set_attr "type" "sseiadd")
8121 (set_attr "atom_unit" "complex")
8122 (set_attr "prefix_extra" "1")
8123 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8124 (set_attr "mode" "DI")])
8126 (define_insn "*avx_phaddswv8hi3"
8127 [(set (match_operand:V8HI 0 "register_operand" "=x")
8133 (match_operand:V8HI 1 "register_operand" "x")
8134 (parallel [(const_int 0)]))
8135 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8137 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8138 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8141 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8142 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8144 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8145 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8150 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8151 (parallel [(const_int 0)]))
8152 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8154 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8155 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8158 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8159 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8161 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8162 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8164 "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
8165 [(set_attr "type" "sseiadd")
8166 (set_attr "prefix_extra" "1")
8167 (set_attr "prefix" "vex")
8168 (set_attr "mode" "TI")])
8170 (define_insn "ssse3_phaddswv8hi3"
8171 [(set (match_operand:V8HI 0 "register_operand" "=x")
8177 (match_operand:V8HI 1 "register_operand" "0")
8178 (parallel [(const_int 0)]))
8179 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8181 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8182 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8185 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8186 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8188 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8189 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8194 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8195 (parallel [(const_int 0)]))
8196 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8198 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8199 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8202 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8203 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8205 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8206 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8208 "phaddsw\t{%2, %0|%0, %2}"
8209 [(set_attr "type" "sseiadd")
8210 (set_attr "atom_unit" "complex")
8211 (set_attr "prefix_data16" "1")
8212 (set_attr "prefix_extra" "1")
8213 (set_attr "mode" "TI")])
8215 (define_insn "ssse3_phaddswv4hi3"
8216 [(set (match_operand:V4HI 0 "register_operand" "=y")
8221 (match_operand:V4HI 1 "register_operand" "0")
8222 (parallel [(const_int 0)]))
8223 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8225 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8226 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8230 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8231 (parallel [(const_int 0)]))
8232 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8234 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8235 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8237 "phaddsw\t{%2, %0|%0, %2}"
8238 [(set_attr "type" "sseiadd")
8239 (set_attr "atom_unit" "complex")
8240 (set_attr "prefix_extra" "1")
8241 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8242 (set_attr "mode" "DI")])
8244 (define_insn "*avx_phsubwv8hi3"
8245 [(set (match_operand:V8HI 0 "register_operand" "=x")
8251 (match_operand:V8HI 1 "register_operand" "x")
8252 (parallel [(const_int 0)]))
8253 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8255 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8256 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8259 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8260 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8262 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8263 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8268 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8269 (parallel [(const_int 0)]))
8270 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8272 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8273 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8276 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8277 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8279 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8280 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8282 "vphsubw\t{%2, %1, %0|%0, %1, %2}"
8283 [(set_attr "type" "sseiadd")
8284 (set_attr "prefix_extra" "1")
8285 (set_attr "prefix" "vex")
8286 (set_attr "mode" "TI")])
8288 (define_insn "ssse3_phsubwv8hi3"
8289 [(set (match_operand:V8HI 0 "register_operand" "=x")
8295 (match_operand:V8HI 1 "register_operand" "0")
8296 (parallel [(const_int 0)]))
8297 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8299 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8300 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8303 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8304 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8306 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8307 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8312 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8313 (parallel [(const_int 0)]))
8314 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8316 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8317 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8320 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8321 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8323 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8324 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8326 "phsubw\t{%2, %0|%0, %2}"
8327 [(set_attr "type" "sseiadd")
8328 (set_attr "atom_unit" "complex")
8329 (set_attr "prefix_data16" "1")
8330 (set_attr "prefix_extra" "1")
8331 (set_attr "mode" "TI")])
8333 (define_insn "ssse3_phsubwv4hi3"
8334 [(set (match_operand:V4HI 0 "register_operand" "=y")
8339 (match_operand:V4HI 1 "register_operand" "0")
8340 (parallel [(const_int 0)]))
8341 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8343 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8344 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8348 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8349 (parallel [(const_int 0)]))
8350 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8352 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8353 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8355 "phsubw\t{%2, %0|%0, %2}"
8356 [(set_attr "type" "sseiadd")
8357 (set_attr "atom_unit" "complex")
8358 (set_attr "prefix_extra" "1")
8359 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8360 (set_attr "mode" "DI")])
8362 (define_insn "*avx_phsubdv4si3"
8363 [(set (match_operand:V4SI 0 "register_operand" "=x")
8368 (match_operand:V4SI 1 "register_operand" "x")
8369 (parallel [(const_int 0)]))
8370 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8372 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8373 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8377 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8378 (parallel [(const_int 0)]))
8379 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8381 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8382 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8384 "vphsubd\t{%2, %1, %0|%0, %1, %2}"
8385 [(set_attr "type" "sseiadd")
8386 (set_attr "prefix_extra" "1")
8387 (set_attr "prefix" "vex")
8388 (set_attr "mode" "TI")])
8390 (define_insn "ssse3_phsubdv4si3"
8391 [(set (match_operand:V4SI 0 "register_operand" "=x")
8396 (match_operand:V4SI 1 "register_operand" "0")
8397 (parallel [(const_int 0)]))
8398 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8400 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8401 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8405 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8406 (parallel [(const_int 0)]))
8407 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8409 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8410 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8412 "phsubd\t{%2, %0|%0, %2}"
8413 [(set_attr "type" "sseiadd")
8414 (set_attr "atom_unit" "complex")
8415 (set_attr "prefix_data16" "1")
8416 (set_attr "prefix_extra" "1")
8417 (set_attr "mode" "TI")])
8419 (define_insn "ssse3_phsubdv2si3"
8420 [(set (match_operand:V2SI 0 "register_operand" "=y")
8424 (match_operand:V2SI 1 "register_operand" "0")
8425 (parallel [(const_int 0)]))
8426 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8429 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
8430 (parallel [(const_int 0)]))
8431 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
8433 "phsubd\t{%2, %0|%0, %2}"
8434 [(set_attr "type" "sseiadd")
8435 (set_attr "atom_unit" "complex")
8436 (set_attr "prefix_extra" "1")
8437 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8438 (set_attr "mode" "DI")])
8440 (define_insn "*avx_phsubswv8hi3"
8441 [(set (match_operand:V8HI 0 "register_operand" "=x")
8447 (match_operand:V8HI 1 "register_operand" "x")
8448 (parallel [(const_int 0)]))
8449 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8451 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8452 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8455 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8456 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8458 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8459 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8464 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8465 (parallel [(const_int 0)]))
8466 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8468 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8469 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8472 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8473 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8475 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8476 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8478 "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
8479 [(set_attr "type" "sseiadd")
8480 (set_attr "prefix_extra" "1")
8481 (set_attr "prefix" "vex")
8482 (set_attr "mode" "TI")])
8484 (define_insn "ssse3_phsubswv8hi3"
8485 [(set (match_operand:V8HI 0 "register_operand" "=x")
8491 (match_operand:V8HI 1 "register_operand" "0")
8492 (parallel [(const_int 0)]))
8493 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8495 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8496 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8499 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8500 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8502 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8503 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8508 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8509 (parallel [(const_int 0)]))
8510 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8512 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8513 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8516 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8517 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8519 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8520 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8522 "phsubsw\t{%2, %0|%0, %2}"
8523 [(set_attr "type" "sseiadd")
8524 (set_attr "atom_unit" "complex")
8525 (set_attr "prefix_data16" "1")
8526 (set_attr "prefix_extra" "1")
8527 (set_attr "mode" "TI")])
8529 (define_insn "ssse3_phsubswv4hi3"
8530 [(set (match_operand:V4HI 0 "register_operand" "=y")
8535 (match_operand:V4HI 1 "register_operand" "0")
8536 (parallel [(const_int 0)]))
8537 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8539 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8540 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8544 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8545 (parallel [(const_int 0)]))
8546 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8548 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8549 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8551 "phsubsw\t{%2, %0|%0, %2}"
8552 [(set_attr "type" "sseiadd")
8553 (set_attr "atom_unit" "complex")
8554 (set_attr "prefix_extra" "1")
8555 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8556 (set_attr "mode" "DI")])
8558 (define_insn "*avx_pmaddubsw128"
8559 [(set (match_operand:V8HI 0 "register_operand" "=x")
8564 (match_operand:V16QI 1 "register_operand" "x")
8565 (parallel [(const_int 0)
8575 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8576 (parallel [(const_int 0)
8586 (vec_select:V8QI (match_dup 1)
8587 (parallel [(const_int 1)
8596 (vec_select:V8QI (match_dup 2)
8597 (parallel [(const_int 1)
8604 (const_int 15)]))))))]
8606 "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
8607 [(set_attr "type" "sseiadd")
8608 (set_attr "prefix_extra" "1")
8609 (set_attr "prefix" "vex")
8610 (set_attr "mode" "TI")])
8612 (define_insn "ssse3_pmaddubsw128"
8613 [(set (match_operand:V8HI 0 "register_operand" "=x")
8618 (match_operand:V16QI 1 "register_operand" "0")
8619 (parallel [(const_int 0)
8629 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8630 (parallel [(const_int 0)
8640 (vec_select:V8QI (match_dup 1)
8641 (parallel [(const_int 1)
8650 (vec_select:V8QI (match_dup 2)
8651 (parallel [(const_int 1)
8658 (const_int 15)]))))))]
8660 "pmaddubsw\t{%2, %0|%0, %2}"
8661 [(set_attr "type" "sseiadd")
8662 (set_attr "atom_unit" "simul")
8663 (set_attr "prefix_data16" "1")
8664 (set_attr "prefix_extra" "1")
8665 (set_attr "mode" "TI")])
8667 (define_insn "ssse3_pmaddubsw"
8668 [(set (match_operand:V4HI 0 "register_operand" "=y")
8673 (match_operand:V8QI 1 "register_operand" "0")
8674 (parallel [(const_int 0)
8680 (match_operand:V8QI 2 "nonimmediate_operand" "ym")
8681 (parallel [(const_int 0)
8687 (vec_select:V4QI (match_dup 1)
8688 (parallel [(const_int 1)
8693 (vec_select:V4QI (match_dup 2)
8694 (parallel [(const_int 1)
8697 (const_int 7)]))))))]
8699 "pmaddubsw\t{%2, %0|%0, %2}"
8700 [(set_attr "type" "sseiadd")
8701 (set_attr "atom_unit" "simul")
8702 (set_attr "prefix_extra" "1")
8703 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8704 (set_attr "mode" "DI")])
8706 (define_expand "ssse3_pmulhrswv8hi3"
8707 [(set (match_operand:V8HI 0 "register_operand" "")
8714 (match_operand:V8HI 1 "nonimmediate_operand" ""))
8716 (match_operand:V8HI 2 "nonimmediate_operand" "")))
8718 (const_vector:V8HI [(const_int 1) (const_int 1)
8719 (const_int 1) (const_int 1)
8720 (const_int 1) (const_int 1)
8721 (const_int 1) (const_int 1)]))
8724 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
8726 (define_insn "*avx_pmulhrswv8hi3"
8727 [(set (match_operand:V8HI 0 "register_operand" "=x")
8734 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
8736 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8738 (const_vector:V8HI [(const_int 1) (const_int 1)
8739 (const_int 1) (const_int 1)
8740 (const_int 1) (const_int 1)
8741 (const_int 1) (const_int 1)]))
8743 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
8744 "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
8745 [(set_attr "type" "sseimul")
8746 (set_attr "prefix_extra" "1")
8747 (set_attr "prefix" "vex")
8748 (set_attr "mode" "TI")])
8750 (define_insn "*ssse3_pmulhrswv8hi3"
8751 [(set (match_operand:V8HI 0 "register_operand" "=x")
8758 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
8760 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8762 (const_vector:V8HI [(const_int 1) (const_int 1)
8763 (const_int 1) (const_int 1)
8764 (const_int 1) (const_int 1)
8765 (const_int 1) (const_int 1)]))
8767 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
8768 "pmulhrsw\t{%2, %0|%0, %2}"
8769 [(set_attr "type" "sseimul")
8770 (set_attr "prefix_data16" "1")
8771 (set_attr "prefix_extra" "1")
8772 (set_attr "mode" "TI")])
8774 (define_expand "ssse3_pmulhrswv4hi3"
8775 [(set (match_operand:V4HI 0 "register_operand" "")
8782 (match_operand:V4HI 1 "nonimmediate_operand" ""))
8784 (match_operand:V4HI 2 "nonimmediate_operand" "")))
8786 (const_vector:V4HI [(const_int 1) (const_int 1)
8787 (const_int 1) (const_int 1)]))
8790 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
8792 (define_insn "*ssse3_pmulhrswv4hi3"
8793 [(set (match_operand:V4HI 0 "register_operand" "=y")
8800 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
8802 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
8804 (const_vector:V4HI [(const_int 1) (const_int 1)
8805 (const_int 1) (const_int 1)]))
8807 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
8808 "pmulhrsw\t{%2, %0|%0, %2}"
8809 [(set_attr "type" "sseimul")
8810 (set_attr "prefix_extra" "1")
8811 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8812 (set_attr "mode" "DI")])
8814 (define_insn "*avx_pshufbv16qi3"
8815 [(set (match_operand:V16QI 0 "register_operand" "=x")
8816 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8817 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8820 "vpshufb\t{%2, %1, %0|%0, %1, %2}";
8821 [(set_attr "type" "sselog1")
8822 (set_attr "prefix_extra" "1")
8823 (set_attr "prefix" "vex")
8824 (set_attr "mode" "TI")])
8826 (define_insn "ssse3_pshufbv16qi3"
8827 [(set (match_operand:V16QI 0 "register_operand" "=x")
8828 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
8829 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8832 "pshufb\t{%2, %0|%0, %2}";
8833 [(set_attr "type" "sselog1")
8834 (set_attr "prefix_data16" "1")
8835 (set_attr "prefix_extra" "1")
8836 (set_attr "mode" "TI")])
8838 (define_insn "ssse3_pshufbv8qi3"
8839 [(set (match_operand:V8QI 0 "register_operand" "=y")
8840 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
8841 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
8844 "pshufb\t{%2, %0|%0, %2}";
8845 [(set_attr "type" "sselog1")
8846 (set_attr "prefix_extra" "1")
8847 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8848 (set_attr "mode" "DI")])
8850 (define_insn "*avx_psign<mode>3"
8851 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8853 [(match_operand:SSEMODE124 1 "register_operand" "x")
8854 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
8857 "vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
8858 [(set_attr "type" "sselog1")
8859 (set_attr "prefix_extra" "1")
8860 (set_attr "prefix" "vex")
8861 (set_attr "mode" "TI")])
8863 (define_insn "ssse3_psign<mode>3"
8864 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8866 [(match_operand:SSEMODE124 1 "register_operand" "0")
8867 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
8870 "psign<ssevecsize>\t{%2, %0|%0, %2}";
8871 [(set_attr "type" "sselog1")
8872 (set_attr "prefix_data16" "1")
8873 (set_attr "prefix_extra" "1")
8874 (set_attr "mode" "TI")])
8876 (define_insn "ssse3_psign<mode>3"
8877 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
8879 [(match_operand:MMXMODEI 1 "register_operand" "0")
8880 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
8883 "psign<mmxvecsize>\t{%2, %0|%0, %2}";
8884 [(set_attr "type" "sselog1")
8885 (set_attr "prefix_extra" "1")
8886 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8887 (set_attr "mode" "DI")])
8889 (define_insn "*avx_palignrti"
8890 [(set (match_operand:TI 0 "register_operand" "=x")
8891 (unspec:TI [(match_operand:TI 1 "register_operand" "x")
8892 (match_operand:TI 2 "nonimmediate_operand" "xm")
8893 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8897 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8898 return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
8900 [(set_attr "type" "sseishft")
8901 (set_attr "prefix_extra" "1")
8902 (set_attr "length_immediate" "1")
8903 (set_attr "prefix" "vex")
8904 (set_attr "mode" "TI")])
8906 (define_insn "ssse3_palignrti"
8907 [(set (match_operand:TI 0 "register_operand" "=x")
8908 (unspec:TI [(match_operand:TI 1 "register_operand" "0")
8909 (match_operand:TI 2 "nonimmediate_operand" "xm")
8910 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8914 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8915 return "palignr\t{%3, %2, %0|%0, %2, %3}";
8917 [(set_attr "type" "sseishft")
8918 (set_attr "atom_unit" "sishuf")
8919 (set_attr "prefix_data16" "1")
8920 (set_attr "prefix_extra" "1")
8921 (set_attr "length_immediate" "1")
8922 (set_attr "mode" "TI")])
8924 (define_insn "ssse3_palignrdi"
8925 [(set (match_operand:DI 0 "register_operand" "=y")
8926 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
8927 (match_operand:DI 2 "nonimmediate_operand" "ym")
8928 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8932 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8933 return "palignr\t{%3, %2, %0|%0, %2, %3}";
8935 [(set_attr "type" "sseishft")
8936 (set_attr "atom_unit" "sishuf")
8937 (set_attr "prefix_extra" "1")
8938 (set_attr "length_immediate" "1")
8939 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8940 (set_attr "mode" "DI")])
8942 (define_insn "abs<mode>2"
8943 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8944 (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
8946 "%vpabs<ssevecsize>\t{%1, %0|%0, %1}"
8947 [(set_attr "type" "sselog1")
8948 (set_attr "prefix_data16" "1")
8949 (set_attr "prefix_extra" "1")
8950 (set_attr "prefix" "maybe_vex")
8951 (set_attr "mode" "TI")])
8953 (define_insn "abs<mode>2"
8954 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
8955 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
8957 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
8958 [(set_attr "type" "sselog1")
8959 (set_attr "prefix_rep" "0")
8960 (set_attr "prefix_extra" "1")
8961 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8962 (set_attr "mode" "DI")])
8964 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8966 ;; AMD SSE4A instructions
8968 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8970 (define_insn "sse4a_movnt<mode>"
8971 [(set (match_operand:MODEF 0 "memory_operand" "=m")
8973 [(match_operand:MODEF 1 "register_operand" "x")]
8976 "movnts<ssemodefsuffix>\t{%1, %0|%0, %1}"
8977 [(set_attr "type" "ssemov")
8978 (set_attr "mode" "<MODE>")])
8980 (define_insn "sse4a_vmmovnt<mode>"
8981 [(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
8982 (unspec:<ssescalarmode>
8983 [(vec_select:<ssescalarmode>
8984 (match_operand:SSEMODEF2P 1 "register_operand" "x")
8985 (parallel [(const_int 0)]))]
8988 "movnt<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
8989 [(set_attr "type" "ssemov")
8990 (set_attr "mode" "<ssescalarmode>")])
8992 (define_insn "sse4a_extrqi"
8993 [(set (match_operand:V2DI 0 "register_operand" "=x")
8994 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
8995 (match_operand 2 "const_int_operand" "")
8996 (match_operand 3 "const_int_operand" "")]
8999 "extrq\t{%3, %2, %0|%0, %2, %3}"
9000 [(set_attr "type" "sse")
9001 (set_attr "prefix_data16" "1")
9002 (set_attr "length_immediate" "2")
9003 (set_attr "mode" "TI")])
9005 (define_insn "sse4a_extrq"
9006 [(set (match_operand:V2DI 0 "register_operand" "=x")
9007 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9008 (match_operand:V16QI 2 "register_operand" "x")]
9011 "extrq\t{%2, %0|%0, %2}"
9012 [(set_attr "type" "sse")
9013 (set_attr "prefix_data16" "1")
9014 (set_attr "mode" "TI")])
9016 (define_insn "sse4a_insertqi"
9017 [(set (match_operand:V2DI 0 "register_operand" "=x")
9018 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9019 (match_operand:V2DI 2 "register_operand" "x")
9020 (match_operand 3 "const_int_operand" "")
9021 (match_operand 4 "const_int_operand" "")]
9024 "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
9025 [(set_attr "type" "sseins")
9026 (set_attr "prefix_data16" "0")
9027 (set_attr "prefix_rep" "1")
9028 (set_attr "length_immediate" "2")
9029 (set_attr "mode" "TI")])
9031 (define_insn "sse4a_insertq"
9032 [(set (match_operand:V2DI 0 "register_operand" "=x")
9033 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9034 (match_operand:V2DI 2 "register_operand" "x")]
9037 "insertq\t{%2, %0|%0, %2}"
9038 [(set_attr "type" "sseins")
9039 (set_attr "prefix_data16" "0")
9040 (set_attr "prefix_rep" "1")
9041 (set_attr "mode" "TI")])
9043 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9045 ;; Intel SSE4.1 instructions
9047 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9049 (define_insn "avx_blend<ssemodesuffix><avxmodesuffix>"
9050 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9051 (vec_merge:AVXMODEF2P
9052 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9053 (match_operand:AVXMODEF2P 1 "register_operand" "x")
9054 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
9056 "vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9057 [(set_attr "type" "ssemov")
9058 (set_attr "prefix_extra" "1")
9059 (set_attr "length_immediate" "1")
9060 (set_attr "prefix" "vex")
9061 (set_attr "mode" "<avxvecmode>")])
9063 (define_insn "avx_blendv<ssemodesuffix><avxmodesuffix>"
9064 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9066 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
9067 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9068 (match_operand:AVXMODEF2P 3 "register_operand" "x")]
9071 "vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9072 [(set_attr "type" "ssemov")
9073 (set_attr "prefix_extra" "1")
9074 (set_attr "length_immediate" "1")
9075 (set_attr "prefix" "vex")
9076 (set_attr "mode" "<avxvecmode>")])
9078 (define_insn "sse4_1_blend<ssemodesuffix>"
9079 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9080 (vec_merge:SSEMODEF2P
9081 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
9082 (match_operand:SSEMODEF2P 1 "register_operand" "0")
9083 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
9085 "blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
9086 [(set_attr "type" "ssemov")
9087 (set_attr "prefix_data16" "1")
9088 (set_attr "prefix_extra" "1")
9089 (set_attr "length_immediate" "1")
9090 (set_attr "mode" "<MODE>")])
9092 (define_insn "sse4_1_blendv<ssemodesuffix>"
9093 [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
9095 [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
9096 (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
9097 (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
9100 "blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
9101 [(set_attr "type" "ssemov")
9102 (set_attr "prefix_data16" "1")
9103 (set_attr "prefix_extra" "1")
9104 (set_attr "mode" "<MODE>")])
9106 (define_insn "avx_dp<ssemodesuffix><avxmodesuffix>"
9107 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9109 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
9110 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9111 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9114 "vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9115 [(set_attr "type" "ssemul")
9116 (set_attr "prefix" "vex")
9117 (set_attr "prefix_extra" "1")
9118 (set_attr "length_immediate" "1")
9119 (set_attr "mode" "<avxvecmode>")])
9121 (define_insn "sse4_1_dp<ssemodesuffix>"
9122 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9124 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
9125 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
9126 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9129 "dp<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
9130 [(set_attr "type" "ssemul")
9131 (set_attr "prefix_data16" "1")
9132 (set_attr "prefix_extra" "1")
9133 (set_attr "length_immediate" "1")
9134 (set_attr "mode" "<MODE>")])
9136 (define_insn "sse4_1_movntdqa"
9137 [(set (match_operand:V2DI 0 "register_operand" "=x")
9138 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "m")]
9141 "%vmovntdqa\t{%1, %0|%0, %1}"
9142 [(set_attr "type" "ssemov")
9143 (set_attr "prefix_extra" "1")
9144 (set_attr "prefix" "maybe_vex")
9145 (set_attr "mode" "TI")])
9147 (define_insn "*avx_mpsadbw"
9148 [(set (match_operand:V16QI 0 "register_operand" "=x")
9149 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
9150 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9151 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9154 "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9155 [(set_attr "type" "sselog1")
9156 (set_attr "prefix" "vex")
9157 (set_attr "prefix_extra" "1")
9158 (set_attr "length_immediate" "1")
9159 (set_attr "mode" "TI")])
9161 (define_insn "sse4_1_mpsadbw"
9162 [(set (match_operand:V16QI 0 "register_operand" "=x")
9163 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
9164 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9165 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9168 "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
9169 [(set_attr "type" "sselog1")
9170 (set_attr "prefix_extra" "1")
9171 (set_attr "length_immediate" "1")
9172 (set_attr "mode" "TI")])
9174 (define_insn "*avx_packusdw"
9175 [(set (match_operand:V8HI 0 "register_operand" "=x")
9178 (match_operand:V4SI 1 "register_operand" "x"))
9180 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
9182 "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
9183 [(set_attr "type" "sselog")
9184 (set_attr "prefix_extra" "1")
9185 (set_attr "prefix" "vex")
9186 (set_attr "mode" "TI")])
9188 (define_insn "sse4_1_packusdw"
9189 [(set (match_operand:V8HI 0 "register_operand" "=x")
9192 (match_operand:V4SI 1 "register_operand" "0"))
9194 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
9196 "packusdw\t{%2, %0|%0, %2}"
9197 [(set_attr "type" "sselog")
9198 (set_attr "prefix_extra" "1")
9199 (set_attr "mode" "TI")])
9201 (define_insn "*avx_pblendvb"
9202 [(set (match_operand:V16QI 0 "register_operand" "=x")
9203 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
9204 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9205 (match_operand:V16QI 3 "register_operand" "x")]
9208 "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9209 [(set_attr "type" "ssemov")
9210 (set_attr "prefix_extra" "1")
9211 (set_attr "length_immediate" "1")
9212 (set_attr "prefix" "vex")
9213 (set_attr "mode" "TI")])
9215 (define_insn "sse4_1_pblendvb"
9216 [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
9217 (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0")
9218 (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
9219 (match_operand:V16QI 3 "register_operand" "Yz")]
9222 "pblendvb\t{%3, %2, %0|%0, %2, %3}"
9223 [(set_attr "type" "ssemov")
9224 (set_attr "prefix_extra" "1")
9225 (set_attr "mode" "TI")])
9227 (define_insn "*avx_pblendw"
9228 [(set (match_operand:V8HI 0 "register_operand" "=x")
9230 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9231 (match_operand:V8HI 1 "register_operand" "x")
9232 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
9234 "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9235 [(set_attr "type" "ssemov")
9236 (set_attr "prefix" "vex")
9237 (set_attr "prefix_extra" "1")
9238 (set_attr "length_immediate" "1")
9239 (set_attr "mode" "TI")])
9241 (define_insn "sse4_1_pblendw"
9242 [(set (match_operand:V8HI 0 "register_operand" "=x")
9244 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9245 (match_operand:V8HI 1 "register_operand" "0")
9246 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
9248 "pblendw\t{%3, %2, %0|%0, %2, %3}"
9249 [(set_attr "type" "ssemov")
9250 (set_attr "prefix_extra" "1")
9251 (set_attr "length_immediate" "1")
9252 (set_attr "mode" "TI")])
9254 (define_insn "sse4_1_phminposuw"
9255 [(set (match_operand:V8HI 0 "register_operand" "=x")
9256 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
9257 UNSPEC_PHMINPOSUW))]
9259 "%vphminposuw\t{%1, %0|%0, %1}"
9260 [(set_attr "type" "sselog1")
9261 (set_attr "prefix_extra" "1")
9262 (set_attr "prefix" "maybe_vex")
9263 (set_attr "mode" "TI")])
9265 (define_insn "sse4_1_<code>v8qiv8hi2"
9266 [(set (match_operand:V8HI 0 "register_operand" "=x")
9269 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
9270 (parallel [(const_int 0)
9279 "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
9280 [(set_attr "type" "ssemov")
9281 (set_attr "prefix_extra" "1")
9282 (set_attr "prefix" "maybe_vex")
9283 (set_attr "mode" "TI")])
9285 (define_insn "sse4_1_<code>v4qiv4si2"
9286 [(set (match_operand:V4SI 0 "register_operand" "=x")
9289 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
9290 (parallel [(const_int 0)
9295 "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
9296 [(set_attr "type" "ssemov")
9297 (set_attr "prefix_extra" "1")
9298 (set_attr "prefix" "maybe_vex")
9299 (set_attr "mode" "TI")])
9301 (define_insn "sse4_1_<code>v4hiv4si2"
9302 [(set (match_operand:V4SI 0 "register_operand" "=x")
9305 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
9306 (parallel [(const_int 0)
9311 "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
9312 [(set_attr "type" "ssemov")
9313 (set_attr "prefix_extra" "1")
9314 (set_attr "prefix" "maybe_vex")
9315 (set_attr "mode" "TI")])
9317 (define_insn "sse4_1_<code>v2qiv2di2"
9318 [(set (match_operand:V2DI 0 "register_operand" "=x")
9321 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
9322 (parallel [(const_int 0)
9325 "%vpmov<extsuffix>bq\t{%1, %0|%0, %1}"
9326 [(set_attr "type" "ssemov")
9327 (set_attr "prefix_extra" "1")
9328 (set_attr "prefix" "maybe_vex")
9329 (set_attr "mode" "TI")])
9331 (define_insn "sse4_1_<code>v2hiv2di2"
9332 [(set (match_operand:V2DI 0 "register_operand" "=x")
9335 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
9336 (parallel [(const_int 0)
9339 "%vpmov<extsuffix>wq\t{%1, %0|%0, %1}"
9340 [(set_attr "type" "ssemov")
9341 (set_attr "prefix_extra" "1")
9342 (set_attr "prefix" "maybe_vex")
9343 (set_attr "mode" "TI")])
9345 (define_insn "sse4_1_<code>v2siv2di2"
9346 [(set (match_operand:V2DI 0 "register_operand" "=x")
9349 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
9350 (parallel [(const_int 0)
9353 "%vpmov<extsuffix>dq\t{%1, %0|%0, %1}"
9354 [(set_attr "type" "ssemov")
9355 (set_attr "prefix_extra" "1")
9356 (set_attr "prefix" "maybe_vex")
9357 (set_attr "mode" "TI")])
9359 ;; ptestps/ptestpd are very similar to comiss and ucomiss when
9360 ;; setting FLAGS_REG. But it is not a really compare instruction.
9361 (define_insn "avx_vtest<ssemodesuffix><avxmodesuffix>"
9362 [(set (reg:CC FLAGS_REG)
9363 (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x")
9364 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")]
9367 "vtest<ssemodesuffix>\t{%1, %0|%0, %1}"
9368 [(set_attr "type" "ssecomi")
9369 (set_attr "prefix_extra" "1")
9370 (set_attr "prefix" "vex")
9371 (set_attr "mode" "<MODE>")])
9373 ;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
9374 ;; But it is not a really compare instruction.
9375 (define_insn "avx_ptest256"
9376 [(set (reg:CC FLAGS_REG)
9377 (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
9378 (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
9381 "vptest\t{%1, %0|%0, %1}"
9382 [(set_attr "type" "ssecomi")
9383 (set_attr "prefix_extra" "1")
9384 (set_attr "prefix" "vex")
9385 (set_attr "mode" "OI")])
9387 (define_insn "sse4_1_ptest"
9388 [(set (reg:CC FLAGS_REG)
9389 (unspec:CC [(match_operand:V2DI 0 "register_operand" "x")
9390 (match_operand:V2DI 1 "nonimmediate_operand" "xm")]
9393 "%vptest\t{%1, %0|%0, %1}"
9394 [(set_attr "type" "ssecomi")
9395 (set_attr "prefix_extra" "1")
9396 (set_attr "prefix" "maybe_vex")
9397 (set_attr "mode" "TI")])
9399 (define_insn "avx_round<ssemodesuffix>256"
9400 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
9401 (unspec:AVX256MODEF2P
9402 [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm")
9403 (match_operand:SI 2 "const_0_to_15_operand" "n")]
9406 "vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
9407 [(set_attr "type" "ssecvt")
9408 (set_attr "prefix_extra" "1")
9409 (set_attr "length_immediate" "1")
9410 (set_attr "prefix" "vex")
9411 (set_attr "mode" "<MODE>")])
9413 (define_insn "sse4_1_round<ssemodesuffix>"
9414 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9416 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
9417 (match_operand:SI 2 "const_0_to_15_operand" "n")]
9420 "%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
9421 [(set_attr "type" "ssecvt")
9422 (set_attr "prefix_data16" "1")
9423 (set_attr "prefix_extra" "1")
9424 (set_attr "length_immediate" "1")
9425 (set_attr "prefix" "maybe_vex")
9426 (set_attr "mode" "<MODE>")])
9428 (define_insn "*avx_round<ssescalarmodesuffix>"
9429 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9430 (vec_merge:SSEMODEF2P
9432 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
9433 (match_operand:SI 3 "const_0_to_15_operand" "n")]
9435 (match_operand:SSEMODEF2P 1 "register_operand" "x")
9438 "vround<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9439 [(set_attr "type" "ssecvt")
9440 (set_attr "prefix_extra" "1")
9441 (set_attr "length_immediate" "1")
9442 (set_attr "prefix" "vex")
9443 (set_attr "mode" "<MODE>")])
9445 (define_insn "sse4_1_round<ssescalarmodesuffix>"
9446 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9447 (vec_merge:SSEMODEF2P
9449 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
9450 (match_operand:SI 3 "const_0_to_15_operand" "n")]
9452 (match_operand:SSEMODEF2P 1 "register_operand" "0")
9455 "round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3}"
9456 [(set_attr "type" "ssecvt")
9457 (set_attr "prefix_data16" "1")
9458 (set_attr "prefix_extra" "1")
9459 (set_attr "length_immediate" "1")
9460 (set_attr "mode" "<MODE>")])
9462 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9464 ;; Intel SSE4.2 string/text processing instructions
9466 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9468 (define_insn_and_split "sse4_2_pcmpestr"
9469 [(set (match_operand:SI 0 "register_operand" "=c,c")
9471 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
9472 (match_operand:SI 3 "register_operand" "a,a")
9473 (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m")
9474 (match_operand:SI 5 "register_operand" "d,d")
9475 (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
9477 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
9485 (set (reg:CC FLAGS_REG)
9494 && can_create_pseudo_p ()"
9499 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
9500 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
9501 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
9504 emit_insn (gen_sse4_2_pcmpestri (operands[0], operands[2],
9505 operands[3], operands[4],
9506 operands[5], operands[6]));
9508 emit_insn (gen_sse4_2_pcmpestrm (operands[1], operands[2],
9509 operands[3], operands[4],
9510 operands[5], operands[6]));
9511 if (flags && !(ecx || xmm0))
9512 emit_insn (gen_sse4_2_pcmpestr_cconly (NULL, NULL,
9513 operands[2], operands[3],
9514 operands[4], operands[5],
9518 [(set_attr "type" "sselog")
9519 (set_attr "prefix_data16" "1")
9520 (set_attr "prefix_extra" "1")
9521 (set_attr "length_immediate" "1")
9522 (set_attr "memory" "none,load")
9523 (set_attr "mode" "TI")])
9525 (define_insn "sse4_2_pcmpestri"
9526 [(set (match_operand:SI 0 "register_operand" "=c,c")
9528 [(match_operand:V16QI 1 "register_operand" "x,x")
9529 (match_operand:SI 2 "register_operand" "a,a")
9530 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
9531 (match_operand:SI 4 "register_operand" "d,d")
9532 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
9534 (set (reg:CC FLAGS_REG)
9543 "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
9544 [(set_attr "type" "sselog")
9545 (set_attr "prefix_data16" "1")
9546 (set_attr "prefix_extra" "1")
9547 (set_attr "prefix" "maybe_vex")
9548 (set_attr "length_immediate" "1")
9549 (set_attr "memory" "none,load")
9550 (set_attr "mode" "TI")])
9552 (define_insn "sse4_2_pcmpestrm"
9553 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
9555 [(match_operand:V16QI 1 "register_operand" "x,x")
9556 (match_operand:SI 2 "register_operand" "a,a")
9557 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
9558 (match_operand:SI 4 "register_operand" "d,d")
9559 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
9561 (set (reg:CC FLAGS_REG)
9570 "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
9571 [(set_attr "type" "sselog")
9572 (set_attr "prefix_data16" "1")
9573 (set_attr "prefix_extra" "1")
9574 (set_attr "length_immediate" "1")
9575 (set_attr "prefix" "maybe_vex")
9576 (set_attr "memory" "none,load")
9577 (set_attr "mode" "TI")])
9579 (define_insn "sse4_2_pcmpestr_cconly"
9580 [(set (reg:CC FLAGS_REG)
9582 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
9583 (match_operand:SI 3 "register_operand" "a,a,a,a")
9584 (match_operand:V16QI 4 "nonimmediate_operand" "x,m,x,m")
9585 (match_operand:SI 5 "register_operand" "d,d,d,d")
9586 (match_operand:SI 6 "const_0_to_255_operand" "n,n,n,n")]
9588 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
9589 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
9592 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
9593 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
9594 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
9595 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
9596 [(set_attr "type" "sselog")
9597 (set_attr "prefix_data16" "1")
9598 (set_attr "prefix_extra" "1")
9599 (set_attr "length_immediate" "1")
9600 (set_attr "memory" "none,load,none,load")
9601 (set_attr "prefix" "maybe_vex")
9602 (set_attr "mode" "TI")])
9604 (define_insn_and_split "sse4_2_pcmpistr"
9605 [(set (match_operand:SI 0 "register_operand" "=c,c")
9607 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
9608 (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m")
9609 (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
9611 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
9617 (set (reg:CC FLAGS_REG)
9624 && can_create_pseudo_p ()"
9629 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
9630 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
9631 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
9634 emit_insn (gen_sse4_2_pcmpistri (operands[0], operands[2],
9635 operands[3], operands[4]));
9637 emit_insn (gen_sse4_2_pcmpistrm (operands[1], operands[2],
9638 operands[3], operands[4]));
9639 if (flags && !(ecx || xmm0))
9640 emit_insn (gen_sse4_2_pcmpistr_cconly (NULL, NULL,
9641 operands[2], operands[3],
9645 [(set_attr "type" "sselog")
9646 (set_attr "prefix_data16" "1")
9647 (set_attr "prefix_extra" "1")
9648 (set_attr "length_immediate" "1")
9649 (set_attr "memory" "none,load")
9650 (set_attr "mode" "TI")])
9652 (define_insn "sse4_2_pcmpistri"
9653 [(set (match_operand:SI 0 "register_operand" "=c,c")
9655 [(match_operand:V16QI 1 "register_operand" "x,x")
9656 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
9657 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
9659 (set (reg:CC FLAGS_REG)
9666 "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
9667 [(set_attr "type" "sselog")
9668 (set_attr "prefix_data16" "1")
9669 (set_attr "prefix_extra" "1")
9670 (set_attr "length_immediate" "1")
9671 (set_attr "prefix" "maybe_vex")
9672 (set_attr "memory" "none,load")
9673 (set_attr "mode" "TI")])
9675 (define_insn "sse4_2_pcmpistrm"
9676 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
9678 [(match_operand:V16QI 1 "register_operand" "x,x")
9679 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
9680 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
9682 (set (reg:CC FLAGS_REG)
9689 "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
9690 [(set_attr "type" "sselog")
9691 (set_attr "prefix_data16" "1")
9692 (set_attr "prefix_extra" "1")
9693 (set_attr "length_immediate" "1")
9694 (set_attr "prefix" "maybe_vex")
9695 (set_attr "memory" "none,load")
9696 (set_attr "mode" "TI")])
9698 (define_insn "sse4_2_pcmpistr_cconly"
9699 [(set (reg:CC FLAGS_REG)
9701 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
9702 (match_operand:V16QI 3 "nonimmediate_operand" "x,m,x,m")
9703 (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
9705 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
9706 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
9709 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
9710 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
9711 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
9712 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
9713 [(set_attr "type" "sselog")
9714 (set_attr "prefix_data16" "1")
9715 (set_attr "prefix_extra" "1")
9716 (set_attr "length_immediate" "1")
9717 (set_attr "memory" "none,load,none,load")
9718 (set_attr "prefix" "maybe_vex")
9719 (set_attr "mode" "TI")])
9721 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9725 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9727 ;; XOP parallel integer multiply/add instructions.
9728 ;; Note the XOP multiply/add instructions
9729 ;; a[i] = b[i] * c[i] + d[i];
9730 ;; do not allow the value being added to be a memory operation.
9731 (define_insn "xop_pmacsww"
9732 [(set (match_operand:V8HI 0 "register_operand" "=x")
9735 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
9736 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
9737 (match_operand:V8HI 3 "nonimmediate_operand" "x")))]
9739 "vpmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9740 [(set_attr "type" "ssemuladd")
9741 (set_attr "mode" "TI")])
9743 (define_insn "xop_pmacssww"
9744 [(set (match_operand:V8HI 0 "register_operand" "=x")
9746 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
9747 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
9748 (match_operand:V8HI 3 "nonimmediate_operand" "x")))]
9750 "vpmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9751 [(set_attr "type" "ssemuladd")
9752 (set_attr "mode" "TI")])
9754 (define_insn "xop_pmacsdd"
9755 [(set (match_operand:V4SI 0 "register_operand" "=x")
9758 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9759 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
9760 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
9762 "vpmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9763 [(set_attr "type" "ssemuladd")
9764 (set_attr "mode" "TI")])
9766 (define_insn "xop_pmacssdd"
9767 [(set (match_operand:V4SI 0 "register_operand" "=x")
9769 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9770 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
9771 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
9773 "vpmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9774 [(set_attr "type" "ssemuladd")
9775 (set_attr "mode" "TI")])
9777 (define_insn "xop_pmacssdql"
9778 [(set (match_operand:V2DI 0 "register_operand" "=x")
9783 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9784 (parallel [(const_int 1)
9787 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9788 (parallel [(const_int 1)
9790 (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
9792 "vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9793 [(set_attr "type" "ssemuladd")
9794 (set_attr "mode" "TI")])
9796 (define_insn "xop_pmacssdqh"
9797 [(set (match_operand:V2DI 0 "register_operand" "=x")
9802 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9803 (parallel [(const_int 0)
9807 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9808 (parallel [(const_int 0)
9810 (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
9812 "vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9813 [(set_attr "type" "ssemuladd")
9814 (set_attr "mode" "TI")])
9816 (define_insn "xop_pmacsdql"
9817 [(set (match_operand:V2DI 0 "register_operand" "=x")
9822 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9823 (parallel [(const_int 1)
9827 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9828 (parallel [(const_int 1)
9830 (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
9832 "vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9833 [(set_attr "type" "ssemuladd")
9834 (set_attr "mode" "TI")])
9836 ;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
9837 ;; fake it with a multiply/add. In general, we expect the define_split to
9838 ;; occur before register allocation, so we have to handle the corner case where
9839 ;; the target is the same as operands 1/2
9840 (define_insn_and_split "xop_mulv2div2di3_low"
9841 [(set (match_operand:V2DI 0 "register_operand" "=&x")
9845 (match_operand:V4SI 1 "register_operand" "%x")
9846 (parallel [(const_int 1)
9850 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9851 (parallel [(const_int 1)
9852 (const_int 3)])))))]
9855 "&& reload_completed"
9864 (parallel [(const_int 1)
9869 (parallel [(const_int 1)
9873 operands[3] = CONST0_RTX (V2DImode);
9875 [(set_attr "type" "ssemul")
9876 (set_attr "mode" "TI")])
9878 (define_insn "xop_pmacsdqh"
9879 [(set (match_operand:V2DI 0 "register_operand" "=x")
9884 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
9885 (parallel [(const_int 0)
9889 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9890 (parallel [(const_int 0)
9892 (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
9894 "vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9895 [(set_attr "type" "ssemuladd")
9896 (set_attr "mode" "TI")])
9898 ;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
9899 ;; fake it with a multiply/add. In general, we expect the define_split to
9900 ;; occur before register allocation, so we have to handle the corner case where
9901 ;; the target is the same as either operands[1] or operands[2]
9902 (define_insn_and_split "xop_mulv2div2di3_high"
9903 [(set (match_operand:V2DI 0 "register_operand" "=&x")
9907 (match_operand:V4SI 1 "register_operand" "%x")
9908 (parallel [(const_int 0)
9912 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
9913 (parallel [(const_int 0)
9914 (const_int 2)])))))]
9917 "&& reload_completed"
9926 (parallel [(const_int 0)
9931 (parallel [(const_int 0)
9935 operands[3] = CONST0_RTX (V2DImode);
9937 [(set_attr "type" "ssemul")
9938 (set_attr "mode" "TI")])
9940 ;; XOP parallel integer multiply/add instructions for the intrinisics
9941 (define_insn "xop_pmacsswd"
9942 [(set (match_operand:V4SI 0 "register_operand" "=x")
9947 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
9948 (parallel [(const_int 1)
9954 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9955 (parallel [(const_int 1)
9959 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
9961 "vpmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9962 [(set_attr "type" "ssemuladd")
9963 (set_attr "mode" "TI")])
9965 (define_insn "xop_pmacswd"
9966 [(set (match_operand:V4SI 0 "register_operand" "=x")
9971 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
9972 (parallel [(const_int 1)
9978 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9979 (parallel [(const_int 1)
9983 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
9985 "vpmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9986 [(set_attr "type" "ssemuladd")
9987 (set_attr "mode" "TI")])
9989 (define_insn "xop_pmadcsswd"
9990 [(set (match_operand:V4SI 0 "register_operand" "=x")
9996 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
9997 (parallel [(const_int 0)
10003 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
10004 (parallel [(const_int 0)
10012 (parallel [(const_int 1)
10019 (parallel [(const_int 1)
10022 (const_int 7)])))))
10023 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
10025 "vpmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10026 [(set_attr "type" "ssemuladd")
10027 (set_attr "mode" "TI")])
10029 (define_insn "xop_pmadcswd"
10030 [(set (match_operand:V4SI 0 "register_operand" "=x")
10036 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
10037 (parallel [(const_int 0)
10043 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
10044 (parallel [(const_int 0)
10052 (parallel [(const_int 1)
10059 (parallel [(const_int 1)
10062 (const_int 7)])))))
10063 (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
10065 "vpmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10066 [(set_attr "type" "ssemuladd")
10067 (set_attr "mode" "TI")])
10069 ;; XOP parallel XMM conditional moves
10070 (define_insn "xop_pcmov_<mode>"
10071 [(set (match_operand:SSEMODE 0 "register_operand" "=x,x")
10072 (if_then_else:SSEMODE
10073 (match_operand:SSEMODE 3 "nonimmediate_operand" "x,m")
10074 (match_operand:SSEMODE 1 "vector_move_operand" "x,x")
10075 (match_operand:SSEMODE 2 "vector_move_operand" "xm,x")))]
10077 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10078 [(set_attr "type" "sse4arg")])
10080 (define_insn "xop_pcmov_<mode>256"
10081 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
10082 (if_then_else:AVX256MODE
10083 (match_operand:AVX256MODE 3 "nonimmediate_operand" "x,m")
10084 (match_operand:AVX256MODE 1 "vector_move_operand" "x,x")
10085 (match_operand:AVX256MODE 2 "vector_move_operand" "xm,x")))]
10087 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10088 [(set_attr "type" "sse4arg")])
10090 ;; XOP horizontal add/subtract instructions
10091 (define_insn "xop_phaddbw"
10092 [(set (match_operand:V8HI 0 "register_operand" "=x")
10096 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10097 (parallel [(const_int 0)
10108 (parallel [(const_int 1)
10115 (const_int 15)])))))]
10117 "vphaddbw\t{%1, %0|%0, %1}"
10118 [(set_attr "type" "sseiadd1")])
10120 (define_insn "xop_phaddbd"
10121 [(set (match_operand:V4SI 0 "register_operand" "=x")
10126 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10127 (parallel [(const_int 0)
10134 (parallel [(const_int 1)
10137 (const_int 13)]))))
10142 (parallel [(const_int 2)
10149 (parallel [(const_int 3)
10152 (const_int 15)]))))))]
10154 "vphaddbd\t{%1, %0|%0, %1}"
10155 [(set_attr "type" "sseiadd1")])
10157 (define_insn "xop_phaddbq"
10158 [(set (match_operand:V2DI 0 "register_operand" "=x")
10164 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10165 (parallel [(const_int 0)
10170 (parallel [(const_int 1)
10176 (parallel [(const_int 2)
10181 (parallel [(const_int 3)
10182 (const_int 7)])))))
10188 (parallel [(const_int 8)
10193 (parallel [(const_int 9)
10194 (const_int 13)]))))
10199 (parallel [(const_int 10)
10204 (parallel [(const_int 11)
10205 (const_int 15)])))))))]
10207 "vphaddbq\t{%1, %0|%0, %1}"
10208 [(set_attr "type" "sseiadd1")])
10210 (define_insn "xop_phaddwd"
10211 [(set (match_operand:V4SI 0 "register_operand" "=x")
10215 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
10216 (parallel [(const_int 0)
10223 (parallel [(const_int 1)
10226 (const_int 7)])))))]
10228 "vphaddwd\t{%1, %0|%0, %1}"
10229 [(set_attr "type" "sseiadd1")])
10231 (define_insn "xop_phaddwq"
10232 [(set (match_operand:V2DI 0 "register_operand" "=x")
10237 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
10238 (parallel [(const_int 0)
10243 (parallel [(const_int 1)
10249 (parallel [(const_int 2)
10254 (parallel [(const_int 3)
10255 (const_int 7)]))))))]
10257 "vphaddwq\t{%1, %0|%0, %1}"
10258 [(set_attr "type" "sseiadd1")])
10260 (define_insn "xop_phadddq"
10261 [(set (match_operand:V2DI 0 "register_operand" "=x")
10265 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
10266 (parallel [(const_int 0)
10271 (parallel [(const_int 1)
10272 (const_int 3)])))))]
10274 "vphadddq\t{%1, %0|%0, %1}"
10275 [(set_attr "type" "sseiadd1")])
10277 (define_insn "xop_phaddubw"
10278 [(set (match_operand:V8HI 0 "register_operand" "=x")
10282 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10283 (parallel [(const_int 0)
10294 (parallel [(const_int 1)
10301 (const_int 15)])))))]
10303 "vphaddubw\t{%1, %0|%0, %1}"
10304 [(set_attr "type" "sseiadd1")])
10306 (define_insn "xop_phaddubd"
10307 [(set (match_operand:V4SI 0 "register_operand" "=x")
10312 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10313 (parallel [(const_int 0)
10320 (parallel [(const_int 1)
10323 (const_int 13)]))))
10328 (parallel [(const_int 2)
10335 (parallel [(const_int 3)
10338 (const_int 15)]))))))]
10340 "vphaddubd\t{%1, %0|%0, %1}"
10341 [(set_attr "type" "sseiadd1")])
10343 (define_insn "xop_phaddubq"
10344 [(set (match_operand:V2DI 0 "register_operand" "=x")
10350 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10351 (parallel [(const_int 0)
10356 (parallel [(const_int 1)
10362 (parallel [(const_int 2)
10367 (parallel [(const_int 3)
10368 (const_int 7)])))))
10374 (parallel [(const_int 8)
10379 (parallel [(const_int 9)
10380 (const_int 13)]))))
10385 (parallel [(const_int 10)
10390 (parallel [(const_int 11)
10391 (const_int 15)])))))))]
10393 "vphaddubq\t{%1, %0|%0, %1}"
10394 [(set_attr "type" "sseiadd1")])
10396 (define_insn "xop_phadduwd"
10397 [(set (match_operand:V4SI 0 "register_operand" "=x")
10401 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
10402 (parallel [(const_int 0)
10409 (parallel [(const_int 1)
10412 (const_int 7)])))))]
10414 "vphadduwd\t{%1, %0|%0, %1}"
10415 [(set_attr "type" "sseiadd1")])
10417 (define_insn "xop_phadduwq"
10418 [(set (match_operand:V2DI 0 "register_operand" "=x")
10423 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
10424 (parallel [(const_int 0)
10429 (parallel [(const_int 1)
10435 (parallel [(const_int 2)
10440 (parallel [(const_int 3)
10441 (const_int 7)]))))))]
10443 "vphadduwq\t{%1, %0|%0, %1}"
10444 [(set_attr "type" "sseiadd1")])
10446 (define_insn "xop_phaddudq"
10447 [(set (match_operand:V2DI 0 "register_operand" "=x")
10451 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
10452 (parallel [(const_int 0)
10457 (parallel [(const_int 1)
10458 (const_int 3)])))))]
10460 "vphaddudq\t{%1, %0|%0, %1}"
10461 [(set_attr "type" "sseiadd1")])
10463 (define_insn "xop_phsubbw"
10464 [(set (match_operand:V8HI 0 "register_operand" "=x")
10468 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10469 (parallel [(const_int 0)
10480 (parallel [(const_int 1)
10487 (const_int 15)])))))]
10489 "vphsubbw\t{%1, %0|%0, %1}"
10490 [(set_attr "type" "sseiadd1")])
10492 (define_insn "xop_phsubwd"
10493 [(set (match_operand:V4SI 0 "register_operand" "=x")
10497 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
10498 (parallel [(const_int 0)
10505 (parallel [(const_int 1)
10508 (const_int 7)])))))]
10510 "vphsubwd\t{%1, %0|%0, %1}"
10511 [(set_attr "type" "sseiadd1")])
10513 (define_insn "xop_phsubdq"
10514 [(set (match_operand:V2DI 0 "register_operand" "=x")
10518 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
10519 (parallel [(const_int 0)
10524 (parallel [(const_int 1)
10525 (const_int 3)])))))]
10527 "vphsubdq\t{%1, %0|%0, %1}"
10528 [(set_attr "type" "sseiadd1")])
10530 ;; XOP permute instructions
10531 (define_insn "xop_pperm"
10532 [(set (match_operand:V16QI 0 "register_operand" "=x,x")
10534 [(match_operand:V16QI 1 "register_operand" "x,x")
10535 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
10536 (match_operand:V16QI 3 "nonimmediate_operand" "xm,x")]
10537 UNSPEC_XOP_PERMUTE))]
10538 "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
10539 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10540 [(set_attr "type" "sse4arg")
10541 (set_attr "mode" "TI")])
10543 ;; XOP pack instructions that combine two vectors into a smaller vector
10544 (define_insn "xop_pperm_pack_v2di_v4si"
10545 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10548 (match_operand:V2DI 1 "register_operand" "x,x"))
10550 (match_operand:V2DI 2 "nonimmediate_operand" "x,m"))))
10551 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
10552 "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
10553 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10554 [(set_attr "type" "sse4arg")
10555 (set_attr "mode" "TI")])
10557 (define_insn "xop_pperm_pack_v4si_v8hi"
10558 [(set (match_operand:V8HI 0 "register_operand" "=x,x")
10561 (match_operand:V4SI 1 "register_operand" "x,x"))
10563 (match_operand:V4SI 2 "nonimmediate_operand" "x,m"))))
10564 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
10565 "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
10566 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10567 [(set_attr "type" "sse4arg")
10568 (set_attr "mode" "TI")])
10570 (define_insn "xop_pperm_pack_v8hi_v16qi"
10571 [(set (match_operand:V16QI 0 "register_operand" "=x,x")
10574 (match_operand:V8HI 1 "register_operand" "x,x"))
10576 (match_operand:V8HI 2 "nonimmediate_operand" "x,m"))))
10577 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
10578 "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
10579 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10580 [(set_attr "type" "sse4arg")
10581 (set_attr "mode" "TI")])
10583 ;; XOP packed rotate instructions
10584 (define_expand "rotl<mode>3"
10585 [(set (match_operand:SSEMODE1248 0 "register_operand" "")
10586 (rotate:SSEMODE1248
10587 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
10588 (match_operand:SI 2 "general_operand")))]
10591 /* If we were given a scalar, convert it to parallel */
10592 if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
10594 rtvec vs = rtvec_alloc (<ssescalarnum>);
10595 rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
10596 rtx reg = gen_reg_rtx (<MODE>mode);
10597 rtx op2 = operands[2];
10600 if (GET_MODE (op2) != <ssescalarmode>mode)
10602 op2 = gen_reg_rtx (<ssescalarmode>mode);
10603 convert_move (op2, operands[2], false);
10606 for (i = 0; i < <ssescalarnum>; i++)
10607 RTVEC_ELT (vs, i) = op2;
10609 emit_insn (gen_vec_init<mode> (reg, par));
10610 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], reg));
10615 (define_expand "rotr<mode>3"
10616 [(set (match_operand:SSEMODE1248 0 "register_operand" "")
10617 (rotatert:SSEMODE1248
10618 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
10619 (match_operand:SI 2 "general_operand")))]
10622 /* If we were given a scalar, convert it to parallel */
10623 if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
10625 rtvec vs = rtvec_alloc (<ssescalarnum>);
10626 rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
10627 rtx neg = gen_reg_rtx (<MODE>mode);
10628 rtx reg = gen_reg_rtx (<MODE>mode);
10629 rtx op2 = operands[2];
10632 if (GET_MODE (op2) != <ssescalarmode>mode)
10634 op2 = gen_reg_rtx (<ssescalarmode>mode);
10635 convert_move (op2, operands[2], false);
10638 for (i = 0; i < <ssescalarnum>; i++)
10639 RTVEC_ELT (vs, i) = op2;
10641 emit_insn (gen_vec_init<mode> (reg, par));
10642 emit_insn (gen_neg<mode>2 (neg, reg));
10643 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], neg));
10648 (define_insn "xop_rotl<mode>3"
10649 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10650 (rotate:SSEMODE1248
10651 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
10652 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
10654 "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
10655 [(set_attr "type" "sseishft")
10656 (set_attr "length_immediate" "1")
10657 (set_attr "mode" "TI")])
10659 (define_insn "xop_rotr<mode>3"
10660 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10661 (rotatert:SSEMODE1248
10662 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
10663 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
10666 operands[3] = GEN_INT ((<ssescalarnum> * 8) - INTVAL (operands[2]));
10667 return \"vprot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
10669 [(set_attr "type" "sseishft")
10670 (set_attr "length_immediate" "1")
10671 (set_attr "mode" "TI")])
10673 (define_expand "vrotr<mode>3"
10674 [(match_operand:SSEMODE1248 0 "register_operand" "")
10675 (match_operand:SSEMODE1248 1 "register_operand" "")
10676 (match_operand:SSEMODE1248 2 "register_operand" "")]
10679 rtx reg = gen_reg_rtx (<MODE>mode);
10680 emit_insn (gen_neg<mode>2 (reg, operands[2]));
10681 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], reg));
10685 (define_expand "vrotl<mode>3"
10686 [(match_operand:SSEMODE1248 0 "register_operand" "")
10687 (match_operand:SSEMODE1248 1 "register_operand" "")
10688 (match_operand:SSEMODE1248 2 "register_operand" "")]
10691 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
10695 (define_insn "xop_vrotl<mode>3"
10696 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
10697 (if_then_else:SSEMODE1248
10699 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
10701 (rotate:SSEMODE1248
10702 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
10704 (rotatert:SSEMODE1248
10706 (neg:SSEMODE1248 (match_dup 2)))))]
10707 "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10708 "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
10709 [(set_attr "type" "sseishft")
10710 (set_attr "prefix_data16" "0")
10711 (set_attr "prefix_extra" "2")
10712 (set_attr "mode" "TI")])
10714 ;; XOP packed shift instructions.
10715 ;; FIXME: add V2DI back in
10716 (define_expand "vlshr<mode>3"
10717 [(match_operand:SSEMODE124 0 "register_operand" "")
10718 (match_operand:SSEMODE124 1 "register_operand" "")
10719 (match_operand:SSEMODE124 2 "register_operand" "")]
10722 rtx neg = gen_reg_rtx (<MODE>mode);
10723 emit_insn (gen_neg<mode>2 (neg, operands[2]));
10724 emit_insn (gen_xop_lshl<mode>3 (operands[0], operands[1], neg));
10728 (define_expand "vashr<mode>3"
10729 [(match_operand:SSEMODE124 0 "register_operand" "")
10730 (match_operand:SSEMODE124 1 "register_operand" "")
10731 (match_operand:SSEMODE124 2 "register_operand" "")]
10734 rtx neg = gen_reg_rtx (<MODE>mode);
10735 emit_insn (gen_neg<mode>2 (neg, operands[2]));
10736 emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], neg));
10740 (define_expand "vashl<mode>3"
10741 [(match_operand:SSEMODE124 0 "register_operand" "")
10742 (match_operand:SSEMODE124 1 "register_operand" "")
10743 (match_operand:SSEMODE124 2 "register_operand" "")]
10746 emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
10750 (define_insn "xop_ashl<mode>3"
10751 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
10752 (if_then_else:SSEMODE1248
10754 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
10756 (ashift:SSEMODE1248
10757 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
10759 (ashiftrt:SSEMODE1248
10761 (neg:SSEMODE1248 (match_dup 2)))))]
10762 "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10763 "vpsha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
10764 [(set_attr "type" "sseishft")
10765 (set_attr "prefix_data16" "0")
10766 (set_attr "prefix_extra" "2")
10767 (set_attr "mode" "TI")])
10769 (define_insn "xop_lshl<mode>3"
10770 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
10771 (if_then_else:SSEMODE1248
10773 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
10775 (ashift:SSEMODE1248
10776 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
10778 (lshiftrt:SSEMODE1248
10780 (neg:SSEMODE1248 (match_dup 2)))))]
10781 "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10782 "vpshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
10783 [(set_attr "type" "sseishft")
10784 (set_attr "prefix_data16" "0")
10785 (set_attr "prefix_extra" "2")
10786 (set_attr "mode" "TI")])
10788 ;; SSE2 doesn't have some shift varients, so define versions for XOP
10789 (define_expand "ashlv16qi3"
10790 [(match_operand:V16QI 0 "register_operand" "")
10791 (match_operand:V16QI 1 "register_operand" "")
10792 (match_operand:SI 2 "nonmemory_operand" "")]
10795 rtvec vs = rtvec_alloc (16);
10796 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
10797 rtx reg = gen_reg_rtx (V16QImode);
10799 for (i = 0; i < 16; i++)
10800 RTVEC_ELT (vs, i) = operands[2];
10802 emit_insn (gen_vec_initv16qi (reg, par));
10803 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
10807 (define_expand "lshlv16qi3"
10808 [(match_operand:V16QI 0 "register_operand" "")
10809 (match_operand:V16QI 1 "register_operand" "")
10810 (match_operand:SI 2 "nonmemory_operand" "")]
10813 rtvec vs = rtvec_alloc (16);
10814 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
10815 rtx reg = gen_reg_rtx (V16QImode);
10817 for (i = 0; i < 16; i++)
10818 RTVEC_ELT (vs, i) = operands[2];
10820 emit_insn (gen_vec_initv16qi (reg, par));
10821 emit_insn (gen_xop_lshlv16qi3 (operands[0], operands[1], reg));
10825 (define_expand "ashrv16qi3"
10826 [(match_operand:V16QI 0 "register_operand" "")
10827 (match_operand:V16QI 1 "register_operand" "")
10828 (match_operand:SI 2 "nonmemory_operand" "")]
10831 rtvec vs = rtvec_alloc (16);
10832 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
10833 rtx reg = gen_reg_rtx (V16QImode);
10835 rtx ele = ((CONST_INT_P (operands[2]))
10836 ? GEN_INT (- INTVAL (operands[2]))
10839 for (i = 0; i < 16; i++)
10840 RTVEC_ELT (vs, i) = ele;
10842 emit_insn (gen_vec_initv16qi (reg, par));
10844 if (!CONST_INT_P (operands[2]))
10846 rtx neg = gen_reg_rtx (V16QImode);
10847 emit_insn (gen_negv16qi2 (neg, reg));
10848 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], neg));
10851 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
10856 (define_expand "ashrv2di3"
10857 [(match_operand:V2DI 0 "register_operand" "")
10858 (match_operand:V2DI 1 "register_operand" "")
10859 (match_operand:DI 2 "nonmemory_operand" "")]
10862 rtvec vs = rtvec_alloc (2);
10863 rtx par = gen_rtx_PARALLEL (V2DImode, vs);
10864 rtx reg = gen_reg_rtx (V2DImode);
10867 if (CONST_INT_P (operands[2]))
10868 ele = GEN_INT (- INTVAL (operands[2]));
10869 else if (GET_MODE (operands[2]) != DImode)
10871 rtx move = gen_reg_rtx (DImode);
10872 ele = gen_reg_rtx (DImode);
10873 convert_move (move, operands[2], false);
10874 emit_insn (gen_negdi2 (ele, move));
10878 ele = gen_reg_rtx (DImode);
10879 emit_insn (gen_negdi2 (ele, operands[2]));
10882 RTVEC_ELT (vs, 0) = ele;
10883 RTVEC_ELT (vs, 1) = ele;
10884 emit_insn (gen_vec_initv2di (reg, par));
10885 emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg));
10889 ;; XOP FRCZ support
10890 (define_insn "xop_frcz<mode>2"
10891 [(set (match_operand:FMAMODE 0 "register_operand" "=x")
10893 [(match_operand:FMAMODE 1 "nonimmediate_operand" "xm")]
10896 "vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
10897 [(set_attr "type" "ssecvt1")
10898 (set_attr "mode" "<MODE>")])
10901 (define_expand "xop_vmfrcz<mode>2"
10902 [(set (match_operand:SSEMODEF2P 0 "register_operand")
10903 (vec_merge:SSEMODEF2P
10905 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand")]
10911 operands[3] = CONST0_RTX (<MODE>mode);
10914 (define_insn "*xop_vmfrcz_<mode>"
10915 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
10916 (vec_merge:SSEMODEF2P
10918 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")]
10920 (match_operand:SSEMODEF2P 2 "const0_operand")
10923 "vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
10924 [(set_attr "type" "ssecvt1")
10925 (set_attr "mode" "<MODE>")])
10927 (define_insn "xop_maskcmp<mode>3"
10928 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10929 (match_operator:SSEMODE1248 1 "ix86_comparison_int_operator"
10930 [(match_operand:SSEMODE1248 2 "register_operand" "x")
10931 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
10933 "vpcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
10934 [(set_attr "type" "sse4arg")
10935 (set_attr "prefix_data16" "0")
10936 (set_attr "prefix_rep" "0")
10937 (set_attr "prefix_extra" "2")
10938 (set_attr "length_immediate" "1")
10939 (set_attr "mode" "TI")])
10941 (define_insn "xop_maskcmp_uns<mode>3"
10942 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10943 (match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
10944 [(match_operand:SSEMODE1248 2 "register_operand" "x")
10945 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
10947 "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
10948 [(set_attr "type" "ssecmp")
10949 (set_attr "prefix_data16" "0")
10950 (set_attr "prefix_rep" "0")
10951 (set_attr "prefix_extra" "2")
10952 (set_attr "length_immediate" "1")
10953 (set_attr "mode" "TI")])
10955 ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
10956 ;; and pcomneu* not to be converted to the signed ones in case somebody needs
10957 ;; the exact instruction generated for the intrinsic.
10958 (define_insn "xop_maskcmp_uns2<mode>3"
10959 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10960 (unspec:SSEMODE1248
10961 [(match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
10962 [(match_operand:SSEMODE1248 2 "register_operand" "x")
10963 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")])]
10964 UNSPEC_XOP_UNSIGNED_CMP))]
10966 "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
10967 [(set_attr "type" "ssecmp")
10968 (set_attr "prefix_data16" "0")
10969 (set_attr "prefix_extra" "2")
10970 (set_attr "length_immediate" "1")
10971 (set_attr "mode" "TI")])
10973 ;; Pcomtrue and pcomfalse support. These are useless instructions, but are
10974 ;; being added here to be complete.
10975 (define_insn "xop_pcom_tf<mode>3"
10976 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
10977 (unspec:SSEMODE1248
10978 [(match_operand:SSEMODE1248 1 "register_operand" "x")
10979 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")
10980 (match_operand:SI 3 "const_int_operand" "n")]
10981 UNSPEC_XOP_TRUEFALSE))]
10984 return ((INTVAL (operands[3]) != 0)
10985 ? "vpcomtrue<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
10986 : "vpcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
10988 [(set_attr "type" "ssecmp")
10989 (set_attr "prefix_data16" "0")
10990 (set_attr "prefix_extra" "2")
10991 (set_attr "length_immediate" "1")
10992 (set_attr "mode" "TI")])
10994 (define_insn "xop_vpermil2<mode>3"
10995 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
10997 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
10998 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x")
10999 (match_operand:<avxpermvecmode> 3 "nonimmediate_operand" "xm")
11000 (match_operand:SI 4 "const_0_to_3_operand" "n")]
11003 "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
11004 [(set_attr "type" "sse4arg")
11005 (set_attr "length_immediate" "1")
11006 (set_attr "mode" "<MODE>")])
11008 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11009 (define_insn "*avx_aesenc"
11010 [(set (match_operand:V2DI 0 "register_operand" "=x")
11011 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11012 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11014 "TARGET_AES && TARGET_AVX"
11015 "vaesenc\t{%2, %1, %0|%0, %1, %2}"
11016 [(set_attr "type" "sselog1")
11017 (set_attr "prefix_extra" "1")
11018 (set_attr "prefix" "vex")
11019 (set_attr "mode" "TI")])
11021 (define_insn "aesenc"
11022 [(set (match_operand:V2DI 0 "register_operand" "=x")
11023 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11024 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11027 "aesenc\t{%2, %0|%0, %2}"
11028 [(set_attr "type" "sselog1")
11029 (set_attr "prefix_extra" "1")
11030 (set_attr "mode" "TI")])
11032 (define_insn "*avx_aesenclast"
11033 [(set (match_operand:V2DI 0 "register_operand" "=x")
11034 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11035 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11036 UNSPEC_AESENCLAST))]
11037 "TARGET_AES && TARGET_AVX"
11038 "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
11039 [(set_attr "type" "sselog1")
11040 (set_attr "prefix_extra" "1")
11041 (set_attr "prefix" "vex")
11042 (set_attr "mode" "TI")])
11044 (define_insn "aesenclast"
11045 [(set (match_operand:V2DI 0 "register_operand" "=x")
11046 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11047 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11048 UNSPEC_AESENCLAST))]
11050 "aesenclast\t{%2, %0|%0, %2}"
11051 [(set_attr "type" "sselog1")
11052 (set_attr "prefix_extra" "1")
11053 (set_attr "mode" "TI")])
11055 (define_insn "*avx_aesdec"
11056 [(set (match_operand:V2DI 0 "register_operand" "=x")
11057 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11058 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11060 "TARGET_AES && TARGET_AVX"
11061 "vaesdec\t{%2, %1, %0|%0, %1, %2}"
11062 [(set_attr "type" "sselog1")
11063 (set_attr "prefix_extra" "1")
11064 (set_attr "prefix" "vex")
11065 (set_attr "mode" "TI")])
11067 (define_insn "aesdec"
11068 [(set (match_operand:V2DI 0 "register_operand" "=x")
11069 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11070 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11073 "aesdec\t{%2, %0|%0, %2}"
11074 [(set_attr "type" "sselog1")
11075 (set_attr "prefix_extra" "1")
11076 (set_attr "mode" "TI")])
11078 (define_insn "*avx_aesdeclast"
11079 [(set (match_operand:V2DI 0 "register_operand" "=x")
11080 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11081 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11082 UNSPEC_AESDECLAST))]
11083 "TARGET_AES && TARGET_AVX"
11084 "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
11085 [(set_attr "type" "sselog1")
11086 (set_attr "prefix_extra" "1")
11087 (set_attr "prefix" "vex")
11088 (set_attr "mode" "TI")])
11090 (define_insn "aesdeclast"
11091 [(set (match_operand:V2DI 0 "register_operand" "=x")
11092 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11093 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11094 UNSPEC_AESDECLAST))]
11096 "aesdeclast\t{%2, %0|%0, %2}"
11097 [(set_attr "type" "sselog1")
11098 (set_attr "prefix_extra" "1")
11099 (set_attr "mode" "TI")])
11101 (define_insn "aesimc"
11102 [(set (match_operand:V2DI 0 "register_operand" "=x")
11103 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")]
11106 "%vaesimc\t{%1, %0|%0, %1}"
11107 [(set_attr "type" "sselog1")
11108 (set_attr "prefix_extra" "1")
11109 (set_attr "prefix" "maybe_vex")
11110 (set_attr "mode" "TI")])
11112 (define_insn "aeskeygenassist"
11113 [(set (match_operand:V2DI 0 "register_operand" "=x")
11114 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")
11115 (match_operand:SI 2 "const_0_to_255_operand" "n")]
11116 UNSPEC_AESKEYGENASSIST))]
11118 "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
11119 [(set_attr "type" "sselog1")
11120 (set_attr "prefix_extra" "1")
11121 (set_attr "length_immediate" "1")
11122 (set_attr "prefix" "maybe_vex")
11123 (set_attr "mode" "TI")])
11125 (define_insn "*vpclmulqdq"
11126 [(set (match_operand:V2DI 0 "register_operand" "=x")
11127 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11128 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
11129 (match_operand:SI 3 "const_0_to_255_operand" "n")]
11131 "TARGET_PCLMUL && TARGET_AVX"
11132 "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11133 [(set_attr "type" "sselog1")
11134 (set_attr "prefix_extra" "1")
11135 (set_attr "length_immediate" "1")
11136 (set_attr "prefix" "vex")
11137 (set_attr "mode" "TI")])
11139 (define_insn "pclmulqdq"
11140 [(set (match_operand:V2DI 0 "register_operand" "=x")
11141 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11142 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
11143 (match_operand:SI 3 "const_0_to_255_operand" "n")]
11146 "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
11147 [(set_attr "type" "sselog1")
11148 (set_attr "prefix_extra" "1")
11149 (set_attr "length_immediate" "1")
11150 (set_attr "mode" "TI")])
11152 (define_expand "avx_vzeroall"
11153 [(match_par_dup 0 [(const_int 0)])]
11156 int nregs = TARGET_64BIT ? 16 : 8;
11159 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs + 1));
11161 XVECEXP (operands[0], 0, 0)
11162 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
11165 for (regno = 0; regno < nregs; regno++)
11166 XVECEXP (operands[0], 0, regno + 1)
11167 = gen_rtx_SET (VOIDmode,
11168 gen_rtx_REG (V8SImode, SSE_REGNO (regno)),
11169 CONST0_RTX (V8SImode));
11172 (define_insn "*avx_vzeroall"
11173 [(match_parallel 0 "vzeroall_operation"
11174 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROALL)])]
11177 [(set_attr "type" "sse")
11178 (set_attr "modrm" "0")
11179 (set_attr "memory" "none")
11180 (set_attr "prefix" "vex")
11181 (set_attr "mode" "OI")])
11183 ;; Clear the upper 128bits of AVX registers, equivalent to a NOP
11184 ;; if the upper 128bits are unused.
11185 (define_insn "avx_vzeroupper"
11186 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
11187 UNSPECV_VZEROUPPER)]
11190 [(set_attr "type" "sse")
11191 (set_attr "modrm" "0")
11192 (set_attr "memory" "none")
11193 (set_attr "prefix" "vex")
11194 (set_attr "mode" "OI")])
11196 (define_insn_and_split "vec_dup<mode>"
11197 [(set (match_operand:AVX256MODE24P 0 "register_operand" "=x,x")
11198 (vec_duplicate:AVX256MODE24P
11199 (match_operand:<avxscalarmode> 1 "nonimmediate_operand" "m,?x")))]
11202 vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1}
11204 "&& reload_completed && REG_P (operands[1])"
11205 [(set (match_dup 2) (vec_duplicate:<avxhalfvecmode> (match_dup 1)))
11206 (set (match_dup 0) (vec_concat:AVX256MODE24P (match_dup 2) (match_dup 2)))]
11207 "operands[2] = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (operands[0]));"
11208 [(set_attr "type" "ssemov")
11209 (set_attr "prefix_extra" "1")
11210 (set_attr "prefix" "vex")
11211 (set_attr "mode" "V8SF")])
11213 (define_insn "avx_vbroadcastf128_<mode>"
11214 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x,x")
11215 (vec_concat:AVX256MODE
11216 (match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "m,0,?x")
11220 vbroadcastf128\t{%1, %0|%0, %1}
11221 vinsertf128\t{$1, %1, %0, %0|%0, %0, %1, 1}
11222 vperm2f128\t{$0, %t1, %t1, %0|%0, %t1, %t1, 0}"
11223 [(set_attr "type" "ssemov,sselog1,sselog1")
11224 (set_attr "prefix_extra" "1")
11225 (set_attr "length_immediate" "0,1,1")
11226 (set_attr "prefix" "vex")
11227 (set_attr "mode" "V4SF,V8SF,V8SF")])
11229 ;; Recognize broadcast as a vec_select as produced by builtin_vec_perm.
11230 ;; If it so happens that the input is in memory, use vbroadcast.
11231 ;; Otherwise use vpermilp (and in the case of 256-bit modes, vperm2f128).
11232 (define_insn "*avx_vperm_broadcast_v4sf"
11233 [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
11235 (match_operand:V4SF 1 "nonimmediate_operand" "m,o,x")
11236 (match_parallel 2 "avx_vbroadcast_operand"
11237 [(match_operand 3 "const_int_operand" "C,n,n")])))]
11240 int elt = INTVAL (operands[3]);
11241 switch (which_alternative)
11245 operands[1] = adjust_address_nv (operands[1], SFmode, elt * 4);
11246 return "vbroadcastss\t{%1, %0|%0, %1}";
11248 operands[2] = GEN_INT (elt * 0x55);
11249 return "vpermilps\t{%2, %1, %0|%0, %1, %2}";
11251 gcc_unreachable ();
11254 [(set_attr "type" "ssemov,ssemov,sselog1")
11255 (set_attr "prefix_extra" "1")
11256 (set_attr "length_immediate" "0,0,1")
11257 (set_attr "prefix" "vex")
11258 (set_attr "mode" "SF,SF,V4SF")])
11260 (define_insn_and_split "*avx_vperm_broadcast_<mode>"
11261 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x,x,x")
11262 (vec_select:AVX256MODEF2P
11263 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "m,o,?x")
11264 (match_parallel 2 "avx_vbroadcast_operand"
11265 [(match_operand 3 "const_int_operand" "C,n,n")])))]
11268 "&& reload_completed"
11269 [(set (match_dup 0) (vec_duplicate:AVX256MODEF2P (match_dup 1)))]
11271 rtx op0 = operands[0], op1 = operands[1];
11272 int elt = INTVAL (operands[3]);
11278 /* Shuffle element we care about into all elements of the 128-bit lane.
11279 The other lane gets shuffled too, but we don't care. */
11280 if (<MODE>mode == V4DFmode)
11281 mask = (elt & 1 ? 15 : 0);
11283 mask = (elt & 3) * 0x55;
11284 emit_insn (gen_avx_vpermil<mode> (op0, op1, GEN_INT (mask)));
11286 /* Shuffle the lane we care about into both lanes of the dest. */
11287 mask = (elt / (<ssescalarnum> / 2)) * 0x11;
11288 emit_insn (gen_avx_vperm2f128<mode>3 (op0, op0, op0, GEN_INT (mask)));
11292 operands[1] = adjust_address_nv (op1, <avxscalarmode>mode,
11293 elt * GET_MODE_SIZE (<avxscalarmode>mode));
11296 (define_expand "avx_vpermil<mode>"
11297 [(set (match_operand:AVXMODEFDP 0 "register_operand" "")
11298 (vec_select:AVXMODEFDP
11299 (match_operand:AVXMODEFDP 1 "nonimmediate_operand" "")
11300 (match_operand:SI 2 "const_0_to_255_operand" "")))]
11303 int mask = INTVAL (operands[2]);
11304 rtx perm[<ssescalarnum>];
11306 perm[0] = GEN_INT (mask & 1);
11307 perm[1] = GEN_INT ((mask >> 1) & 1);
11308 if (<MODE>mode == V4DFmode)
11310 perm[2] = GEN_INT (((mask >> 2) & 1) + 2);
11311 perm[3] = GEN_INT (((mask >> 3) & 1) + 2);
11315 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (<ssescalarnum>, perm));
11318 (define_expand "avx_vpermil<mode>"
11319 [(set (match_operand:AVXMODEFSP 0 "register_operand" "")
11320 (vec_select:AVXMODEFSP
11321 (match_operand:AVXMODEFSP 1 "nonimmediate_operand" "")
11322 (match_operand:SI 2 "const_0_to_255_operand" "")))]
11325 int mask = INTVAL (operands[2]);
11326 rtx perm[<ssescalarnum>];
11328 perm[0] = GEN_INT (mask & 3);
11329 perm[1] = GEN_INT ((mask >> 2) & 3);
11330 perm[2] = GEN_INT ((mask >> 4) & 3);
11331 perm[3] = GEN_INT ((mask >> 6) & 3);
11332 if (<MODE>mode == V8SFmode)
11334 perm[4] = GEN_INT ((mask & 3) + 4);
11335 perm[5] = GEN_INT (((mask >> 2) & 3) + 4);
11336 perm[6] = GEN_INT (((mask >> 4) & 3) + 4);
11337 perm[7] = GEN_INT (((mask >> 6) & 3) + 4);
11341 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (<ssescalarnum>, perm));
11344 (define_insn "*avx_vpermilp<mode>"
11345 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
11346 (vec_select:AVXMODEF2P
11347 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")
11348 (match_parallel 2 "avx_vpermilp_<mode>_operand"
11349 [(match_operand 3 "const_int_operand" "")])))]
11352 int mask = avx_vpermilp_parallel (operands[2], <MODE>mode) - 1;
11353 operands[2] = GEN_INT (mask);
11354 return "vpermil<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}";
11356 [(set_attr "type" "sselog")
11357 (set_attr "prefix_extra" "1")
11358 (set_attr "length_immediate" "1")
11359 (set_attr "prefix" "vex")
11360 (set_attr "mode" "<MODE>")])
11362 (define_insn "avx_vpermilvar<mode>3"
11363 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
11365 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
11366 (match_operand:<avxpermvecmode> 2 "nonimmediate_operand" "xm")]
11369 "vpermil<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
11370 [(set_attr "type" "sselog")
11371 (set_attr "prefix_extra" "1")
11372 (set_attr "prefix" "vex")
11373 (set_attr "mode" "<MODE>")])
11375 (define_expand "avx_vperm2f128<mode>3"
11376 [(set (match_operand:AVX256MODE2P 0 "register_operand" "")
11377 (unspec:AVX256MODE2P
11378 [(match_operand:AVX256MODE2P 1 "register_operand" "")
11379 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "")
11380 (match_operand:SI 3 "const_0_to_255_operand" "")]
11381 UNSPEC_VPERMIL2F128))]
11384 int mask = INTVAL (operands[3]);
11385 if ((mask & 0x88) == 0)
11387 rtx perm[<ssescalarnum>], t1, t2;
11388 int i, base, nelt = <ssescalarnum>, nelt2 = nelt / 2;
11390 base = (mask & 3) * nelt2;
11391 for (i = 0; i < nelt2; ++i)
11392 perm[i] = GEN_INT (base + i);
11394 base = ((mask >> 4) & 3) * nelt2;
11395 for (i = 0; i < nelt2; ++i)
11396 perm[i + nelt2] = GEN_INT (base + i);
11398 t2 = gen_rtx_VEC_CONCAT (<ssedoublesizemode>mode,
11399 operands[1], operands[2]);
11400 t1 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, perm));
11401 t2 = gen_rtx_VEC_SELECT (<MODE>mode, t2, t1);
11402 t2 = gen_rtx_SET (VOIDmode, operands[0], t2);
11408 ;; Note that bits 7 and 3 of the imm8 allow lanes to be zeroed, which
11409 ;; means that in order to represent this properly in rtl we'd have to
11410 ;; nest *another* vec_concat with a zero operand and do the select from
11411 ;; a 4x wide vector. That doesn't seem very nice.
11412 (define_insn "*avx_vperm2f128<mode>_full"
11413 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x")
11414 (unspec:AVX256MODE2P
11415 [(match_operand:AVX256MODE2P 1 "register_operand" "x")
11416 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm")
11417 (match_operand:SI 3 "const_0_to_255_operand" "n")]
11418 UNSPEC_VPERMIL2F128))]
11420 "vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11421 [(set_attr "type" "sselog")
11422 (set_attr "prefix_extra" "1")
11423 (set_attr "length_immediate" "1")
11424 (set_attr "prefix" "vex")
11425 (set_attr "mode" "V8SF")])
11427 (define_insn "*avx_vperm2f128<mode>_nozero"
11428 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x")
11429 (vec_select:AVX256MODE2P
11430 (vec_concat:<ssedoublesizemode>
11431 (match_operand:AVX256MODE2P 1 "register_operand" "x")
11432 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm"))
11433 (match_parallel 3 "avx_vperm2f128_<mode>_operand"
11434 [(match_operand 4 "const_int_operand" "")])))]
11437 int mask = avx_vperm2f128_parallel (operands[3], <MODE>mode) - 1;
11438 operands[3] = GEN_INT (mask);
11439 return "vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}";
11441 [(set_attr "type" "sselog")
11442 (set_attr "prefix_extra" "1")
11443 (set_attr "length_immediate" "1")
11444 (set_attr "prefix" "vex")
11445 (set_attr "mode" "V8SF")])
11447 (define_expand "avx_vinsertf128<mode>"
11448 [(match_operand:AVX256MODE 0 "register_operand" "")
11449 (match_operand:AVX256MODE 1 "register_operand" "")
11450 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "")
11451 (match_operand:SI 3 "const_0_to_1_operand" "")]
11454 rtx (*insn)(rtx, rtx, rtx);
11456 switch (INTVAL (operands[3]))
11459 insn = gen_vec_set_lo_<mode>;
11462 insn = gen_vec_set_hi_<mode>;
11465 gcc_unreachable ();
11468 emit_insn (insn (operands[0], operands[1], operands[2]));
11472 (define_insn "vec_set_lo_<mode>"
11473 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
11474 (vec_concat:AVX256MODE4P
11475 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
11476 (vec_select:<avxhalfvecmode>
11477 (match_operand:AVX256MODE4P 1 "register_operand" "x")
11478 (parallel [(const_int 2) (const_int 3)]))))]
11480 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
11481 [(set_attr "type" "sselog")
11482 (set_attr "prefix_extra" "1")
11483 (set_attr "length_immediate" "1")
11484 (set_attr "prefix" "vex")
11485 (set_attr "mode" "V8SF")])
11487 (define_insn "vec_set_hi_<mode>"
11488 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
11489 (vec_concat:AVX256MODE4P
11490 (vec_select:<avxhalfvecmode>
11491 (match_operand:AVX256MODE4P 1 "register_operand" "x")
11492 (parallel [(const_int 0) (const_int 1)]))
11493 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
11495 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
11496 [(set_attr "type" "sselog")
11497 (set_attr "prefix_extra" "1")
11498 (set_attr "length_immediate" "1")
11499 (set_attr "prefix" "vex")
11500 (set_attr "mode" "V8SF")])
11502 (define_insn "vec_set_lo_<mode>"
11503 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
11504 (vec_concat:AVX256MODE8P
11505 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
11506 (vec_select:<avxhalfvecmode>
11507 (match_operand:AVX256MODE8P 1 "register_operand" "x")
11508 (parallel [(const_int 4) (const_int 5)
11509 (const_int 6) (const_int 7)]))))]
11511 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
11512 [(set_attr "type" "sselog")
11513 (set_attr "prefix_extra" "1")
11514 (set_attr "length_immediate" "1")
11515 (set_attr "prefix" "vex")
11516 (set_attr "mode" "V8SF")])
11518 (define_insn "vec_set_hi_<mode>"
11519 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
11520 (vec_concat:AVX256MODE8P
11521 (vec_select:<avxhalfvecmode>
11522 (match_operand:AVX256MODE8P 1 "register_operand" "x")
11523 (parallel [(const_int 0) (const_int 1)
11524 (const_int 2) (const_int 3)]))
11525 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
11527 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
11528 [(set_attr "type" "sselog")
11529 (set_attr "prefix_extra" "1")
11530 (set_attr "length_immediate" "1")
11531 (set_attr "prefix" "vex")
11532 (set_attr "mode" "V8SF")])
11534 (define_insn "vec_set_lo_v16hi"
11535 [(set (match_operand:V16HI 0 "register_operand" "=x")
11537 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
11539 (match_operand:V16HI 1 "register_operand" "x")
11540 (parallel [(const_int 8) (const_int 9)
11541 (const_int 10) (const_int 11)
11542 (const_int 12) (const_int 13)
11543 (const_int 14) (const_int 15)]))))]
11545 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
11546 [(set_attr "type" "sselog")
11547 (set_attr "prefix_extra" "1")
11548 (set_attr "length_immediate" "1")
11549 (set_attr "prefix" "vex")
11550 (set_attr "mode" "V8SF")])
11552 (define_insn "vec_set_hi_v16hi"
11553 [(set (match_operand:V16HI 0 "register_operand" "=x")
11556 (match_operand:V16HI 1 "register_operand" "x")
11557 (parallel [(const_int 0) (const_int 1)
11558 (const_int 2) (const_int 3)
11559 (const_int 4) (const_int 5)
11560 (const_int 6) (const_int 7)]))
11561 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
11563 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
11564 [(set_attr "type" "sselog")
11565 (set_attr "prefix_extra" "1")
11566 (set_attr "length_immediate" "1")
11567 (set_attr "prefix" "vex")
11568 (set_attr "mode" "V8SF")])
11570 (define_insn "vec_set_lo_v32qi"
11571 [(set (match_operand:V32QI 0 "register_operand" "=x")
11573 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
11575 (match_operand:V32QI 1 "register_operand" "x")
11576 (parallel [(const_int 16) (const_int 17)
11577 (const_int 18) (const_int 19)
11578 (const_int 20) (const_int 21)
11579 (const_int 22) (const_int 23)
11580 (const_int 24) (const_int 25)
11581 (const_int 26) (const_int 27)
11582 (const_int 28) (const_int 29)
11583 (const_int 30) (const_int 31)]))))]
11585 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
11586 [(set_attr "type" "sselog")
11587 (set_attr "prefix_extra" "1")
11588 (set_attr "length_immediate" "1")
11589 (set_attr "prefix" "vex")
11590 (set_attr "mode" "V8SF")])
11592 (define_insn "vec_set_hi_v32qi"
11593 [(set (match_operand:V32QI 0 "register_operand" "=x")
11596 (match_operand:V32QI 1 "register_operand" "x")
11597 (parallel [(const_int 0) (const_int 1)
11598 (const_int 2) (const_int 3)
11599 (const_int 4) (const_int 5)
11600 (const_int 6) (const_int 7)
11601 (const_int 8) (const_int 9)
11602 (const_int 10) (const_int 11)
11603 (const_int 12) (const_int 13)
11604 (const_int 14) (const_int 15)]))
11605 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
11607 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
11608 [(set_attr "type" "sselog")
11609 (set_attr "prefix_extra" "1")
11610 (set_attr "length_immediate" "1")
11611 (set_attr "prefix" "vex")
11612 (set_attr "mode" "V8SF")])
11614 (define_insn "avx_maskload<ssemodesuffix><avxmodesuffix>"
11615 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
11617 [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
11618 (match_operand:<avxpermvecmode> 2 "register_operand" "x")
11622 "vmaskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"
11623 [(set_attr "type" "sselog1")
11624 (set_attr "prefix_extra" "1")
11625 (set_attr "prefix" "vex")
11626 (set_attr "mode" "<MODE>")])
11628 (define_insn "avx_maskstore<ssemodesuffix><avxmodesuffix>"
11629 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
11631 [(match_operand:<avxpermvecmode> 1 "register_operand" "x")
11632 (match_operand:AVXMODEF2P 2 "register_operand" "x")
11634 UNSPEC_MASKSTORE))]
11636 "vmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
11637 [(set_attr "type" "sselog1")
11638 (set_attr "prefix_extra" "1")
11639 (set_attr "prefix" "vex")
11640 (set_attr "mode" "<MODE>")])
11642 (define_insn_and_split "avx_<avxmodesuffixp><avxmodesuffix>_<avxmodesuffixp>"
11643 [(set (match_operand:AVX256MODE2P 0 "nonimmediate_operand" "=x,m")
11644 (unspec:AVX256MODE2P
11645 [(match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "xm,x")]
11649 "&& reload_completed"
11652 rtx op1 = operands[1];
11654 op1 = gen_rtx_REG (<MODE>mode, REGNO (op1));
11656 op1 = gen_lowpart (<MODE>mode, op1);
11657 emit_move_insn (operands[0], op1);
11661 (define_expand "vec_init<mode>"
11662 [(match_operand:AVX256MODE 0 "register_operand" "")
11663 (match_operand 1 "" "")]
11666 ix86_expand_vector_init (false, operands[0], operands[1]);
11670 (define_insn "*vec_concat<mode>_avx"
11671 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
11672 (vec_concat:AVX256MODE
11673 (match_operand:<avxhalfvecmode> 1 "register_operand" "x,x")
11674 (match_operand:<avxhalfvecmode> 2 "vector_move_operand" "xm,C")))]
11677 switch (which_alternative)
11680 return "vinsertf128\t{$0x1, %2, %t1, %0|%0, %t1, %2, 0x1}";
11682 switch (get_attr_mode (insn))
11685 return "vmovaps\t{%1, %x0|%x0, %1}";
11687 return "vmovapd\t{%1, %x0|%x0, %1}";
11689 return "vmovdqa\t{%1, %x0|%x0, %1}";
11692 gcc_unreachable ();
11695 [(set_attr "type" "sselog,ssemov")
11696 (set_attr "prefix_extra" "1,*")
11697 (set_attr "length_immediate" "1,*")
11698 (set_attr "prefix" "vex")
11699 (set_attr "mode" "<avxvecmode>")])
11701 (define_insn "vcvtph2ps"
11702 [(set (match_operand:V4SF 0 "register_operand" "=x")
11704 (unspec:V8SF [(match_operand:V8HI 1 "register_operand" "x")]
11706 (parallel [(const_int 0) (const_int 1)
11707 (const_int 1) (const_int 2)])))]
11709 "vcvtph2ps\t{%1, %0|%0, %1}"
11710 [(set_attr "type" "ssecvt")
11711 (set_attr "prefix" "vex")
11712 (set_attr "mode" "V4SF")])
11714 (define_insn "*vcvtph2ps_load"
11715 [(set (match_operand:V4SF 0 "register_operand" "=x")
11716 (unspec:V4SF [(match_operand:V4HI 1 "memory_operand" "m")]
11717 UNSPEC_VCVTPH2PS))]
11719 "vcvtph2ps\t{%1, %0|%0, %1}"
11720 [(set_attr "type" "ssecvt")
11721 (set_attr "prefix" "vex")
11722 (set_attr "mode" "V8SF")])
11724 (define_insn "vcvtph2ps256"
11725 [(set (match_operand:V8SF 0 "register_operand" "=x")
11726 (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
11727 UNSPEC_VCVTPH2PS))]
11729 "vcvtph2ps\t{%1, %0|%0, %1}"
11730 [(set_attr "type" "ssecvt")
11731 (set_attr "prefix" "vex")
11732 (set_attr "mode" "V8SF")])
11734 (define_expand "vcvtps2ph"
11735 [(set (match_operand:V8HI 0 "register_operand" "")
11737 (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "")
11738 (match_operand:SI 2 "immediate_operand" "")]
11742 "operands[3] = CONST0_RTX (V4HImode);")
11744 (define_insn "*vcvtps2ph"
11745 [(set (match_operand:V8HI 0 "register_operand" "=x")
11747 (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
11748 (match_operand:SI 2 "immediate_operand" "N")]
11750 (match_operand:V4HI 3 "const0_operand" "")))]
11752 "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
11753 [(set_attr "type" "ssecvt")
11754 (set_attr "prefix" "vex")
11755 (set_attr "mode" "V4SF")])
11757 (define_insn "*vcvtps2ph_store"
11758 [(set (match_operand:V4HI 0 "memory_operand" "=m")
11759 (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
11760 (match_operand:SI 2 "immediate_operand" "N")]
11761 UNSPEC_VCVTPS2PH))]
11763 "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
11764 [(set_attr "type" "ssecvt")
11765 (set_attr "prefix" "vex")
11766 (set_attr "mode" "V4SF")])
11768 (define_insn "vcvtps2ph256"
11769 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm")
11770 (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "x")
11771 (match_operand:SI 2 "immediate_operand" "N")]
11772 UNSPEC_VCVTPS2PH))]
11774 "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
11775 [(set_attr "type" "ssecvt")
11776 (set_attr "prefix" "vex")
11777 (set_attr "mode" "V8SF")])