| blob | ac5f3b862b5a66227cfa20c36c9f780c743ed853 |
1 ;; ARM VFP instruction patterns
2 ;; Copyright (C) 2003-2016 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; SImode moves
22 ;; ??? For now do not allow loading constants into vfp regs. This causes
23 ;; problems because small constants get converted into adds.
24 (define_insn "*arm_movsi_vfp"
25 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
26 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
27 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
28 && ( s_register_operand (operands[0], SImode)
29 || s_register_operand (operands[1], SImode))"
30 "*
31 switch (which_alternative)
32 {
33 case 0: case 1:
34 return \"mov%?\\t%0, %1\";
35 case 2:
36 return \"mvn%?\\t%0, #%B1\";
37 case 3:
38 return \"movw%?\\t%0, %1\";
39 case 4:
40 return \"ldr%?\\t%0, %1\";
41 case 5:
42 return \"str%?\\t%1, %0\";
43 case 6:
44 return \"vmov%?\\t%0, %1\\t%@ int\";
45 case 7:
46 return \"vmov%?\\t%0, %1\\t%@ int\";
47 case 8:
48 return \"vmov%?.f32\\t%0, %1\\t%@ int\";
49 case 9: case 10:
50 return output_move_vfp (operands);
51 default:
52 gcc_unreachable ();
53 }
54 "
55 [(set_attr "predicable" "yes")
56 (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
57 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
58 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
59 )
61 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
62 ;; high/low register alternatives for loads and stores here.
63 ;; The l/Py alternative should come after r/I to ensure that the short variant
64 ;; is chosen with length 2 when the instruction is predicated for
65 ;; arm_restrict_it.
66 (define_insn "*thumb2_movsi_vfp"
67 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv")
68 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
69 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
70 && ( s_register_operand (operands[0], SImode)
71 || s_register_operand (operands[1], SImode))"
72 "*
73 switch (which_alternative)
74 {
75 case 0:
76 case 1:
77 case 2:
78 return \"mov%?\\t%0, %1\";
79 case 3:
80 return \"mvn%?\\t%0, #%B1\";
81 case 4:
82 return \"movw%?\\t%0, %1\";
83 case 5:
84 case 6:
85 return \"ldr%?\\t%0, %1\";
86 case 7:
87 case 8:
88 return \"str%?\\t%1, %0\";
89 case 9:
90 return \"vmov%?\\t%0, %1\\t%@ int\";
91 case 10:
92 return \"vmov%?\\t%0, %1\\t%@ int\";
93 case 11:
94 return \"vmov%?.f32\\t%0, %1\\t%@ int\";
95 case 12: case 13:
96 return output_move_vfp (operands);
97 default:
98 gcc_unreachable ();
99 }
100 "
101 [(set_attr "predicable" "yes")
102 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
103 (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
104 (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
105 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
106 (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
107 )
110 ;; DImode moves
112 (define_insn "*movdi_vfp"
113 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
114 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
115 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
116 && ( register_operand (operands[0], DImode)
117 || register_operand (operands[1], DImode))
118 && !(TARGET_NEON && CONST_INT_P (operands[1])
119 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
120 "*
121 switch (which_alternative)
122 {
123 case 0:
124 case 1:
125 case 2:
126 case 3:
127 return \"#\";
128 case 4:
129 case 5:
130 case 6:
131 return output_move_double (operands, true, NULL);
132 case 7:
133 return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
134 case 8:
135 return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
136 case 9:
137 if (TARGET_VFP_SINGLE)
138 return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\";
139 else
140 return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
141 case 10: case 11:
142 return output_move_vfp (operands);
143 default:
144 gcc_unreachable ();
145 }
146 "
147 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
148 (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
149 (eq_attr "alternative" "2") (const_int 12)
150 (eq_attr "alternative" "3") (const_int 16)
151 (eq_attr "alternative" "9")
152 (if_then_else
153 (match_test "TARGET_VFP_SINGLE")
154 (const_int 8)
155 (const_int 4))]
156 (const_int 4)))
157 (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*")
158 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
159 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
160 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
161 )
163 (define_insn "*movdi_vfp_cortexa8"
164 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
165 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
166 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
167 && ( register_operand (operands[0], DImode)
168 || register_operand (operands[1], DImode))
169 && !(TARGET_NEON && CONST_INT_P (operands[1])
170 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
171 "*
172 switch (which_alternative)
173 {
174 case 0:
175 case 1:
176 case 2:
177 case 3:
178 return \"#\";
179 case 4:
180 case 5:
181 case 6:
182 return output_move_double (operands, true, NULL);
183 case 7:
184 return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
185 case 8:
186 return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
187 case 9:
188 return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
189 case 10: case 11:
190 return output_move_vfp (operands);
191 default:
192 gcc_unreachable ();
193 }
194 "
195 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
196 (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
197 (eq_attr "alternative" "2") (const_int 12)
198 (eq_attr "alternative" "3") (const_int 16)
199 (eq_attr "alternative" "4,5,6")
200 (symbol_ref
201 "arm_count_output_move_double_insns (operands) \
202 * 4")]
203 (const_int 4)))
204 (set_attr "predicable" "yes")
205 (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
206 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
207 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
208 (set (attr "ce_count")
209 (symbol_ref "get_attr_length (insn) / 4"))
210 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
211 )
213 ;; HFmode moves
214 (define_insn "*movhf_vfp_neon"
215 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
216 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
217 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
218 && ( s_register_operand (operands[0], HFmode)
219 || s_register_operand (operands[1], HFmode))"
220 "*
221 switch (which_alternative)
222 {
223 case 0: /* S register from memory */
224 return \"vld1.16\\t{%z0}, %A1\";
225 case 1: /* memory from S register */
226 return \"vst1.16\\t{%z1}, %A0\";
227 case 2: /* ARM register from memory */
228 return \"ldrh\\t%0, %1\\t%@ __fp16\";
229 case 3: /* memory from ARM register */
230 return \"strh\\t%1, %0\\t%@ __fp16\";
231 case 4: /* S register from S register */
232 return \"vmov.f32\\t%0, %1\";
233 case 5: /* ARM register from ARM register */
234 return \"mov\\t%0, %1\\t%@ __fp16\";
235 case 6: /* S register from ARM register */
236 return \"vmov\\t%0, %1\";
237 case 7: /* ARM register from S register */
238 return \"vmov\\t%0, %1\";
239 case 8: /* ARM register from constant */
240 {
241 long bits;
242 rtx ops[4];
244 bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
245 HFmode);
246 ops[0] = operands[0];
247 ops[1] = GEN_INT (bits);
248 ops[2] = GEN_INT (bits & 0xff00);
249 ops[3] = GEN_INT (bits & 0x00ff);
251 if (arm_arch_thumb2)
252 output_asm_insn (\"movw\\t%0, %1\", ops);
253 else
254 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
255 return \"\";
256 }
257 default:
258 gcc_unreachable ();
259 }
260 "
261 [(set_attr "conds" "unconditional")
262 (set_attr "type" "neon_load1_1reg,neon_store1_1reg,\
263 load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
264 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
265 )
267 ;; FP16 without element load/store instructions.
268 (define_insn "*movhf_vfp"
269 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
270 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
271 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
272 && ( s_register_operand (operands[0], HFmode)
273 || s_register_operand (operands[1], HFmode))"
274 "*
275 switch (which_alternative)
276 {
277 case 0: /* ARM register from memory */
278 return \"ldrh\\t%0, %1\\t%@ __fp16\";
279 case 1: /* memory from ARM register */
280 return \"strh\\t%1, %0\\t%@ __fp16\";
281 case 2: /* S register from S register */
282 return \"vmov.f32\\t%0, %1\";
283 case 3: /* ARM register from ARM register */
284 return \"mov\\t%0, %1\\t%@ __fp16\";
285 case 4: /* S register from ARM register */
286 return \"vmov\\t%0, %1\";
287 case 5: /* ARM register from S register */
288 return \"vmov\\t%0, %1\";
289 case 6: /* ARM register from constant */
290 {
291 long bits;
292 rtx ops[4];
294 bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
295 HFmode);
296 ops[0] = operands[0];
297 ops[1] = GEN_INT (bits);
298 ops[2] = GEN_INT (bits & 0xff00);
299 ops[3] = GEN_INT (bits & 0x00ff);
301 if (arm_arch_thumb2)
302 output_asm_insn (\"movw\\t%0, %1\", ops);
303 else
304 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
305 return \"\";
306 }
307 default:
308 gcc_unreachable ();
309 }
310 "
311 [(set_attr "conds" "unconditional")
312 (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
313 (set_attr "length" "4,4,4,4,4,4,8")]
314 )
317 ;; SFmode moves
318 ;; Disparage the w<->r cases because reloading an invalid address is
319 ;; preferable to loading the value via integer registers.
321 (define_insn "*movsf_vfp"
322 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
323 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
324 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
325 && ( s_register_operand (operands[0], SFmode)
326 || s_register_operand (operands[1], SFmode))"
327 "*
328 switch (which_alternative)
329 {
330 case 0:
331 return \"vmov%?\\t%0, %1\";
332 case 1:
333 return \"vmov%?\\t%0, %1\";
334 case 2:
335 return \"vmov%?.f32\\t%0, %1\";
336 case 3: case 4:
337 return output_move_vfp (operands);
338 case 5:
339 return \"ldr%?\\t%0, %1\\t%@ float\";
340 case 6:
341 return \"str%?\\t%1, %0\\t%@ float\";
342 case 7:
343 return \"vmov%?.f32\\t%0, %1\";
344 case 8:
345 return \"mov%?\\t%0, %1\\t%@ float\";
346 default:
347 gcc_unreachable ();
348 }
349 "
350 [(set_attr "predicable" "yes")
351 (set_attr "type"
352 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
353 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
354 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
355 )
357 (define_insn "*thumb2_movsf_vfp"
358 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
359 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
360 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
361 && ( s_register_operand (operands[0], SFmode)
362 || s_register_operand (operands[1], SFmode))"
363 "*
364 switch (which_alternative)
365 {
366 case 0:
367 return \"vmov%?\\t%0, %1\";
368 case 1:
369 return \"vmov%?\\t%0, %1\";
370 case 2:
371 return \"vmov%?.f32\\t%0, %1\";
372 case 3: case 4:
373 return output_move_vfp (operands);
374 case 5:
375 return \"ldr%?\\t%0, %1\\t%@ float\";
376 case 6:
377 return \"str%?\\t%1, %0\\t%@ float\";
378 case 7:
379 return \"vmov%?.f32\\t%0, %1\";
380 case 8:
381 return \"mov%?\\t%0, %1\\t%@ float\";
382 default:
383 gcc_unreachable ();
384 }
385 "
386 [(set_attr "predicable" "yes")
387 (set_attr "predicable_short_it" "no")
388 (set_attr "type"
389 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
390 (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
391 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
392 )
394 ;; DFmode moves
396 (define_insn "*movdf_vfp"
397 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
398 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
399 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
400 && ( register_operand (operands[0], DFmode)
401 || register_operand (operands[1], DFmode))"
402 "*
403 {
404 switch (which_alternative)
405 {
406 case 0:
407 return \"vmov%?\\t%P0, %Q1, %R1\";
408 case 1:
409 return \"vmov%?\\t%Q0, %R0, %P1\";
410 case 2:
411 gcc_assert (TARGET_VFP_DOUBLE);
412 return \"vmov%?.f64\\t%P0, %1\";
413 case 3: case 4:
414 return output_move_vfp (operands);
415 case 5: case 6:
416 return output_move_double (operands, true, NULL);
417 case 7:
418 if (TARGET_VFP_SINGLE)
419 return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
420 else
421 return \"vmov%?.f64\\t%P0, %P1\";
422 case 8:
423 return \"#\";
424 default:
425 gcc_unreachable ();
426 }
427 }
428 "
429 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
430 load2,store2,ffarithd,multiple")
431 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
432 (eq_attr "alternative" "7")
433 (if_then_else
434 (match_test "TARGET_VFP_SINGLE")
435 (const_int 8)
436 (const_int 4))]
437 (const_int 4)))
438 (set_attr "predicable" "yes")
439 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
440 (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
441 )
443 (define_insn "*thumb2_movdf_vfp"
444 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
445 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
446 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
447 && ( register_operand (operands[0], DFmode)
448 || register_operand (operands[1], DFmode))"
449 "*
450 {
451 switch (which_alternative)
452 {
453 case 0:
454 return \"vmov%?\\t%P0, %Q1, %R1\";
455 case 1:
456 return \"vmov%?\\t%Q0, %R0, %P1\";
457 case 2:
458 gcc_assert (TARGET_VFP_DOUBLE);
459 return \"vmov%?.f64\\t%P0, %1\";
460 case 3: case 4:
461 return output_move_vfp (operands);
462 case 5: case 6: case 8:
463 return output_move_double (operands, true, NULL);
464 case 7:
465 if (TARGET_VFP_SINGLE)
466 return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
467 else
468 return \"vmov%?.f64\\t%P0, %P1\";
469 default:
470 abort ();
471 }
472 }
473 "
474 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
475 f_stored,load2,store2,ffarithd,multiple")
476 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
477 (eq_attr "alternative" "7")
478 (if_then_else
479 (match_test "TARGET_VFP_SINGLE")
480 (const_int 8)
481 (const_int 4))]
482 (const_int 4)))
483 (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
484 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
485 )
488 ;; Conditional move patterns
490 (define_insn "*movsfcc_vfp"
491 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
492 (if_then_else:SF
493 (match_operator 3 "arm_comparison_operator"
494 [(match_operand 4 "cc_register" "") (const_int 0)])
495 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
496 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
497 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
498 "@
499 vmov%D3.f32\\t%0, %2
500 vmov%d3.f32\\t%0, %1
501 vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
502 vmov%D3\\t%0, %2
503 vmov%d3\\t%0, %1
504 vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
505 vmov%D3\\t%0, %2
506 vmov%d3\\t%0, %1
507 vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
508 [(set_attr "conds" "use")
509 (set_attr "length" "4,4,8,4,4,8,4,4,8")
510 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
511 )
513 (define_insn "*thumb2_movsfcc_vfp"
514 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
515 (if_then_else:SF
516 (match_operator 3 "arm_comparison_operator"
517 [(match_operand 4 "cc_register" "") (const_int 0)])
518 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
519 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
520 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
521 "@
522 it\\t%D3\;vmov%D3.f32\\t%0, %2
523 it\\t%d3\;vmov%d3.f32\\t%0, %1
524 ite\\t%D3\;vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
525 it\\t%D3\;vmov%D3\\t%0, %2
526 it\\t%d3\;vmov%d3\\t%0, %1
527 ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
528 it\\t%D3\;vmov%D3\\t%0, %2
529 it\\t%d3\;vmov%d3\\t%0, %1
530 ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
531 [(set_attr "conds" "use")
532 (set_attr "length" "6,6,10,6,6,10,6,6,10")
533 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
534 )
536 (define_insn "*movdfcc_vfp"
537 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
538 (if_then_else:DF
539 (match_operator 3 "arm_comparison_operator"
540 [(match_operand 4 "cc_register" "") (const_int 0)])
541 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
542 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
543 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
544 "@
545 vmov%D3.f64\\t%P0, %P2
546 vmov%d3.f64\\t%P0, %P1
547 vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
548 vmov%D3\\t%P0, %Q2, %R2
549 vmov%d3\\t%P0, %Q1, %R1
550 vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
551 vmov%D3\\t%Q0, %R0, %P2
552 vmov%d3\\t%Q0, %R0, %P1
553 vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
554 [(set_attr "conds" "use")
555 (set_attr "length" "4,4,8,4,4,8,4,4,8")
556 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
557 )
559 (define_insn "*thumb2_movdfcc_vfp"
560 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
561 (if_then_else:DF
562 (match_operator 3 "arm_comparison_operator"
563 [(match_operand 4 "cc_register" "") (const_int 0)])
564 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
565 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
566 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
567 "@
568 it\\t%D3\;vmov%D3.f64\\t%P0, %P2
569 it\\t%d3\;vmov%d3.f64\\t%P0, %P1
570 ite\\t%D3\;vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
571 it\t%D3\;vmov%D3\\t%P0, %Q2, %R2
572 it\t%d3\;vmov%d3\\t%P0, %Q1, %R1
573 ite\\t%D3\;vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
574 it\t%D3\;vmov%D3\\t%Q0, %R0, %P2
575 it\t%d3\;vmov%d3\\t%Q0, %R0, %P1
576 ite\\t%D3\;vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
577 [(set_attr "conds" "use")
578 (set_attr "length" "6,6,10,6,6,10,6,6,10")
579 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
580 )
583 ;; Sign manipulation functions
585 (define_insn "*abssf2_vfp"
586 [(set (match_operand:SF 0 "s_register_operand" "=t")
587 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
588 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
589 "vabs%?.f32\\t%0, %1"
590 [(set_attr "predicable" "yes")
591 (set_attr "predicable_short_it" "no")
592 (set_attr "type" "ffariths")]
593 )
595 (define_insn "*absdf2_vfp"
596 [(set (match_operand:DF 0 "s_register_operand" "=w")
597 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
598 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
599 "vabs%?.f64\\t%P0, %P1"
600 [(set_attr "predicable" "yes")
601 (set_attr "predicable_short_it" "no")
602 (set_attr "type" "ffarithd")]
603 )
605 (define_insn "*negsf2_vfp"
606 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
607 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
608 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
609 "@
610 vneg%?.f32\\t%0, %1
611 eor%?\\t%0, %1, #-2147483648"
612 [(set_attr "predicable" "yes")
613 (set_attr "predicable_short_it" "no")
614 (set_attr "type" "ffariths")]
615 )
617 (define_insn_and_split "*negdf2_vfp"
618 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
619 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
620 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
621 "@
622 vneg%?.f64\\t%P0, %P1
623 #
624 #"
625 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
626 && arm_general_register_operand (operands[0], DFmode)"
627 [(set (match_dup 0) (match_dup 1))]
628 "
629 if (REGNO (operands[0]) == REGNO (operands[1]))
630 {
631 operands[0] = gen_highpart (SImode, operands[0]);
632 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
633 }
634 else
635 {
636 rtx in_hi, in_lo, out_hi, out_lo;
638 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
639 GEN_INT (0x80000000));
640 in_lo = gen_lowpart (SImode, operands[1]);
641 out_hi = gen_highpart (SImode, operands[0]);
642 out_lo = gen_lowpart (SImode, operands[0]);
644 if (REGNO (in_lo) == REGNO (out_hi))
645 {
646 emit_insn (gen_rtx_SET (out_lo, in_lo));
647 operands[0] = out_hi;
648 operands[1] = in_hi;
649 }
650 else
651 {
652 emit_insn (gen_rtx_SET (out_hi, in_hi));
653 operands[0] = out_lo;
654 operands[1] = in_lo;
655 }
656 }
657 "
658 [(set_attr "predicable" "yes")
659 (set_attr "predicable_short_it" "no")
660 (set_attr "length" "4,4,8")
661 (set_attr "type" "ffarithd")]
662 )
665 ;; Arithmetic insns
667 (define_insn "*addsf3_vfp"
668 [(set (match_operand:SF 0 "s_register_operand" "=t")
669 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
670 (match_operand:SF 2 "s_register_operand" "t")))]
671 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
672 "vadd%?.f32\\t%0, %1, %2"
673 [(set_attr "predicable" "yes")
674 (set_attr "predicable_short_it" "no")
675 (set_attr "type" "fadds")]
676 )
678 (define_insn "*adddf3_vfp"
679 [(set (match_operand:DF 0 "s_register_operand" "=w")
680 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
681 (match_operand:DF 2 "s_register_operand" "w")))]
682 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
683 "vadd%?.f64\\t%P0, %P1, %P2"
684 [(set_attr "predicable" "yes")
685 (set_attr "predicable_short_it" "no")
686 (set_attr "type" "faddd")]
687 )
690 (define_insn "*subsf3_vfp"
691 [(set (match_operand:SF 0 "s_register_operand" "=t")
692 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
693 (match_operand:SF 2 "s_register_operand" "t")))]
694 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
695 "vsub%?.f32\\t%0, %1, %2"
696 [(set_attr "predicable" "yes")
697 (set_attr "predicable_short_it" "no")
698 (set_attr "type" "fadds")]
699 )
701 (define_insn "*subdf3_vfp"
702 [(set (match_operand:DF 0 "s_register_operand" "=w")
703 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
704 (match_operand:DF 2 "s_register_operand" "w")))]
705 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
706 "vsub%?.f64\\t%P0, %P1, %P2"
707 [(set_attr "predicable" "yes")
708 (set_attr "predicable_short_it" "no")
709 (set_attr "type" "faddd")]
710 )
713 ;; Division insns
715 ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
716 ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
717 ; earlier.
718 (define_insn "*divsf3_vfp"
719 [(set (match_operand:SF 0 "s_register_operand" "=&t,t")
720 (div:SF (match_operand:SF 1 "s_register_operand" "t,t")
721 (match_operand:SF 2 "s_register_operand" "t,t")))]
722 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
723 "vdiv%?.f32\\t%0, %1, %2"
724 [(set_attr "predicable" "yes")
725 (set_attr "predicable_short_it" "no")
726 (set_attr "arch" "*,armv6_or_vfpv3")
727 (set_attr "type" "fdivs")]
728 )
730 (define_insn "*divdf3_vfp"
731 [(set (match_operand:DF 0 "s_register_operand" "=&w,w")
732 (div:DF (match_operand:DF 1 "s_register_operand" "w,w")
733 (match_operand:DF 2 "s_register_operand" "w,w")))]
734 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
735 "vdiv%?.f64\\t%P0, %P1, %P2"
736 [(set_attr "predicable" "yes")
737 (set_attr "predicable_short_it" "no")
738 (set_attr "arch" "*,armv6_or_vfpv3")
739 (set_attr "type" "fdivd")]
740 )
743 ;; Multiplication insns
745 (define_insn "*mulsf3_vfp"
746 [(set (match_operand:SF 0 "s_register_operand" "=t")
747 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
748 (match_operand:SF 2 "s_register_operand" "t")))]
749 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
750 "vmul%?.f32\\t%0, %1, %2"
751 [(set_attr "predicable" "yes")
752 (set_attr "predicable_short_it" "no")
753 (set_attr "type" "fmuls")]
754 )
756 (define_insn "*muldf3_vfp"
757 [(set (match_operand:DF 0 "s_register_operand" "=w")
758 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
759 (match_operand:DF 2 "s_register_operand" "w")))]
760 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
761 "vmul%?.f64\\t%P0, %P1, %P2"
762 [(set_attr "predicable" "yes")
763 (set_attr "predicable_short_it" "no")
764 (set_attr "type" "fmuld")]
765 )
767 (define_insn "*mulsf3negsf_vfp"
768 [(set (match_operand:SF 0 "s_register_operand" "=t")
769 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
770 (match_operand:SF 2 "s_register_operand" "t")))]
771 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math"
772 "vnmul%?.f32\\t%0, %1, %2"
773 [(set_attr "predicable" "yes")
774 (set_attr "predicable_short_it" "no")
775 (set_attr "type" "fmuls")]
776 )
778 (define_insn "*negmulsf3_vfp"
779 [(set (match_operand:SF 0 "s_register_operand" "=t")
780 (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
781 (match_operand:SF 2 "s_register_operand" "t"))))]
782 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
783 "vnmul%?.f32\\t%0, %1, %2"
784 [(set_attr "predicable" "yes")
785 (set_attr "predicable_short_it" "no")
786 (set_attr "type" "fmuls")]
787 )
789 (define_insn "*muldf3negdf_vfp"
790 [(set (match_operand:DF 0 "s_register_operand" "=w")
791 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
792 (match_operand:DF 2 "s_register_operand" "w")))]
793 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
794 && !flag_rounding_math"
795 "vnmul%?.f64\\t%P0, %P1, %P2"
796 [(set_attr "predicable" "yes")
797 (set_attr "predicable_short_it" "no")
798 (set_attr "type" "fmuld")]
799 )
801 (define_insn "*negmuldf3_vfp"
802 [(set (match_operand:DF 0 "s_register_operand" "=w")
803 (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w")
804 (match_operand:DF 2 "s_register_operand" "w"))))]
805 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
806 "vnmul%?.f64\\t%P0, %P1, %P2"
807 [(set_attr "predicable" "yes")
808 (set_attr "predicable_short_it" "no")
809 (set_attr "type" "fmuld")]
810 )
813 ;; Multiply-accumulate insns
815 ;; 0 = 1 * 2 + 0
816 (define_insn "*mulsf3addsf_vfp"
817 [(set (match_operand:SF 0 "s_register_operand" "=t")
818 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
819 (match_operand:SF 3 "s_register_operand" "t"))
820 (match_operand:SF 1 "s_register_operand" "0")))]
821 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
822 "vmla%?.f32\\t%0, %2, %3"
823 [(set_attr "predicable" "yes")
824 (set_attr "predicable_short_it" "no")
825 (set_attr "type" "fmacs")]
826 )
828 (define_insn "*muldf3adddf_vfp"
829 [(set (match_operand:DF 0 "s_register_operand" "=w")
830 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
831 (match_operand:DF 3 "s_register_operand" "w"))
832 (match_operand:DF 1 "s_register_operand" "0")))]
833 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
834 "vmla%?.f64\\t%P0, %P2, %P3"
835 [(set_attr "predicable" "yes")
836 (set_attr "predicable_short_it" "no")
837 (set_attr "type" "fmacd")]
838 )
840 ;; 0 = 1 * 2 - 0
841 (define_insn "*mulsf3subsf_vfp"
842 [(set (match_operand:SF 0 "s_register_operand" "=t")
843 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
844 (match_operand:SF 3 "s_register_operand" "t"))
845 (match_operand:SF 1 "s_register_operand" "0")))]
846 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
847 "vnmls%?.f32\\t%0, %2, %3"
848 [(set_attr "predicable" "yes")
849 (set_attr "predicable_short_it" "no")
850 (set_attr "type" "fmacs")]
851 )
853 (define_insn "*muldf3subdf_vfp"
854 [(set (match_operand:DF 0 "s_register_operand" "=w")
855 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
856 (match_operand:DF 3 "s_register_operand" "w"))
857 (match_operand:DF 1 "s_register_operand" "0")))]
858 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
859 "vnmls%?.f64\\t%P0, %P2, %P3"
860 [(set_attr "predicable" "yes")
861 (set_attr "predicable_short_it" "no")
862 (set_attr "type" "fmacd")]
863 )
865 ;; 0 = -(1 * 2) + 0
866 (define_insn "*mulsf3negsfaddsf_vfp"
867 [(set (match_operand:SF 0 "s_register_operand" "=t")
868 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
869 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
870 (match_operand:SF 3 "s_register_operand" "t"))))]
871 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
872 "vmls%?.f32\\t%0, %2, %3"
873 [(set_attr "predicable" "yes")
874 (set_attr "predicable_short_it" "no")
875 (set_attr "type" "fmacs")]
876 )
878 (define_insn "*fmuldf3negdfadddf_vfp"
879 [(set (match_operand:DF 0 "s_register_operand" "=w")
880 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
881 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
882 (match_operand:DF 3 "s_register_operand" "w"))))]
883 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
884 "vmls%?.f64\\t%P0, %P2, %P3"
885 [(set_attr "predicable" "yes")
886 (set_attr "predicable_short_it" "no")
887 (set_attr "type" "fmacd")]
888 )
891 ;; 0 = -(1 * 2) - 0
892 (define_insn "*mulsf3negsfsubsf_vfp"
893 [(set (match_operand:SF 0 "s_register_operand" "=t")
894 (minus:SF (mult:SF
895 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
896 (match_operand:SF 3 "s_register_operand" "t"))
897 (match_operand:SF 1 "s_register_operand" "0")))]
898 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
899 "vnmla%?.f32\\t%0, %2, %3"
900 [(set_attr "predicable" "yes")
901 (set_attr "predicable_short_it" "no")
902 (set_attr "type" "fmacs")]
903 )
905 (define_insn "*muldf3negdfsubdf_vfp"
906 [(set (match_operand:DF 0 "s_register_operand" "=w")
907 (minus:DF (mult:DF
908 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
909 (match_operand:DF 3 "s_register_operand" "w"))
910 (match_operand:DF 1 "s_register_operand" "0")))]
911 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
912 "vnmla%?.f64\\t%P0, %P2, %P3"
913 [(set_attr "predicable" "yes")
914 (set_attr "predicable_short_it" "no")
915 (set_attr "type" "fmacd")]
916 )
918 ;; Fused-multiply-accumulate
920 (define_insn "fma<SDF:mode>4"
921 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
922 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
923 (match_operand:SDF 2 "register_operand" "<F_constraint>")
924 (match_operand:SDF 3 "register_operand" "0")))]
925 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
926 "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
927 [(set_attr "predicable" "yes")
928 (set_attr "predicable_short_it" "no")
929 (set_attr "type" "ffma<vfp_type>")]
930 )
932 (define_insn "*fmsub<SDF:mode>4"
933 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
934 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
935 "<F_constraint>"))
936 (match_operand:SDF 2 "register_operand" "<F_constraint>")
937 (match_operand:SDF 3 "register_operand" "0")))]
938 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
939 "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
940 [(set_attr "predicable" "yes")
941 (set_attr "predicable_short_it" "no")
942 (set_attr "type" "ffma<vfp_type>")]
943 )
945 (define_insn "*fnmsub<SDF:mode>4"
946 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
947 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
948 (match_operand:SDF 2 "register_operand" "<F_constraint>")
949 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
950 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
951 "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
952 [(set_attr "predicable" "yes")
953 (set_attr "predicable_short_it" "no")
954 (set_attr "type" "ffma<vfp_type>")]
955 )
957 (define_insn "*fnmadd<SDF:mode>4"
958 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
959 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
960 "<F_constraint>"))
961 (match_operand:SDF 2 "register_operand" "<F_constraint>")
962 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
963 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
964 "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
965 [(set_attr "predicable" "yes")
966 (set_attr "predicable_short_it" "no")
967 (set_attr "type" "ffma<vfp_type>")]
968 )
971 ;; Conversion routines
973 (define_insn "*extendsfdf2_vfp"
974 [(set (match_operand:DF 0 "s_register_operand" "=w")
975 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
976 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
977 "vcvt%?.f64.f32\\t%P0, %1"
978 [(set_attr "predicable" "yes")
979 (set_attr "predicable_short_it" "no")
980 (set_attr "type" "f_cvt")]
981 )
983 (define_insn "*truncdfsf2_vfp"
984 [(set (match_operand:SF 0 "s_register_operand" "=t")
985 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
986 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
987 "vcvt%?.f32.f64\\t%0, %P1"
988 [(set_attr "predicable" "yes")
989 (set_attr "predicable_short_it" "no")
990 (set_attr "type" "f_cvt")]
991 )
993 (define_insn "extendhfsf2"
994 [(set (match_operand:SF 0 "s_register_operand" "=t")
995 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
996 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
997 "vcvtb%?.f32.f16\\t%0, %1"
998 [(set_attr "predicable" "yes")
999 (set_attr "predicable_short_it" "no")
1000 (set_attr "type" "f_cvt")]
1001 )
1003 (define_insn "truncsfhf2"
1004 [(set (match_operand:HF 0 "s_register_operand" "=t")
1005 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
1006 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
1007 "vcvtb%?.f16.f32\\t%0, %1"
1008 [(set_attr "predicable" "yes")
1009 (set_attr "predicable_short_it" "no")
1010 (set_attr "type" "f_cvt")]
1011 )
1013 (define_insn "*truncsisf2_vfp"
1014 [(set (match_operand:SI 0 "s_register_operand" "=t")
1015 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1016 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1017 "vcvt%?.s32.f32\\t%0, %1"
1018 [(set_attr "predicable" "yes")
1019 (set_attr "predicable_short_it" "no")
1020 (set_attr "type" "f_cvtf2i")]
1021 )
1023 (define_insn "*truncsidf2_vfp"
1024 [(set (match_operand:SI 0 "s_register_operand" "=t")
1025 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
1026 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1027 "vcvt%?.s32.f64\\t%0, %P1"
1028 [(set_attr "predicable" "yes")
1029 (set_attr "predicable_short_it" "no")
1030 (set_attr "type" "f_cvtf2i")]
1031 )
1034 (define_insn "fixuns_truncsfsi2"
1035 [(set (match_operand:SI 0 "s_register_operand" "=t")
1036 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1037 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1038 "vcvt%?.u32.f32\\t%0, %1"
1039 [(set_attr "predicable" "yes")
1040 (set_attr "predicable_short_it" "no")
1041 (set_attr "type" "f_cvtf2i")]
1042 )
1044 (define_insn "fixuns_truncdfsi2"
1045 [(set (match_operand:SI 0 "s_register_operand" "=t")
1046 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1047 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1048 "vcvt%?.u32.f64\\t%0, %P1"
1049 [(set_attr "predicable" "yes")
1050 (set_attr "predicable_short_it" "no")
1051 (set_attr "type" "f_cvtf2i")]
1052 )
1055 (define_insn "*floatsisf2_vfp"
1056 [(set (match_operand:SF 0 "s_register_operand" "=t")
1057 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1058 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1059 "vcvt%?.f32.s32\\t%0, %1"
1060 [(set_attr "predicable" "yes")
1061 (set_attr "predicable_short_it" "no")
1062 (set_attr "type" "f_cvti2f")]
1063 )
1065 (define_insn "*floatsidf2_vfp"
1066 [(set (match_operand:DF 0 "s_register_operand" "=w")
1067 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1068 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1069 "vcvt%?.f64.s32\\t%P0, %1"
1070 [(set_attr "predicable" "yes")
1071 (set_attr "predicable_short_it" "no")
1072 (set_attr "type" "f_cvti2f")]
1073 )
1076 (define_insn "floatunssisf2"
1077 [(set (match_operand:SF 0 "s_register_operand" "=t")
1078 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1079 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1080 "vcvt%?.f32.u32\\t%0, %1"
1081 [(set_attr "predicable" "yes")
1082 (set_attr "predicable_short_it" "no")
1083 (set_attr "type" "f_cvti2f")]
1084 )
1086 (define_insn "floatunssidf2"
1087 [(set (match_operand:DF 0 "s_register_operand" "=w")
1088 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1089 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1090 "vcvt%?.f64.u32\\t%P0, %1"
1091 [(set_attr "predicable" "yes")
1092 (set_attr "predicable_short_it" "no")
1093 (set_attr "type" "f_cvti2f")]
1094 )
1097 ;; Sqrt insns.
1099 ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
1100 ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
1101 ; earlier.
1102 (define_insn "*sqrtsf2_vfp"
1103 [(set (match_operand:SF 0 "s_register_operand" "=&t,t")
1104 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
1105 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1106 "vsqrt%?.f32\\t%0, %1"
1107 [(set_attr "predicable" "yes")
1108 (set_attr "predicable_short_it" "no")
1109 (set_attr "arch" "*,armv6_or_vfpv3")
1110 (set_attr "type" "fsqrts")]
1111 )
1113 (define_insn "*sqrtdf2_vfp"
1114 [(set (match_operand:DF 0 "s_register_operand" "=&w,w")
1115 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))]
1116 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1117 "vsqrt%?.f64\\t%P0, %P1"
1118 [(set_attr "predicable" "yes")
1119 (set_attr "predicable_short_it" "no")
1120 (set_attr "arch" "*,armv6_or_vfpv3")
1121 (set_attr "type" "fsqrtd")]
1122 )
1125 ;; Patterns to split/copy vfp condition flags.
1127 (define_insn "*movcc_vfp"
1128 [(set (reg CC_REGNUM)
1129 (reg VFPCC_REGNUM))]
1130 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1131 "vmrs%?\\tAPSR_nzcv, FPSCR"
1132 [(set_attr "conds" "set")
1133 (set_attr "type" "f_flag")]
1134 )
1136 (define_insn_and_split "*cmpsf_split_vfp"
1137 [(set (reg:CCFP CC_REGNUM)
1138 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
1139 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1140 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1141 "#"
1142 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1143 [(set (reg:CCFP VFPCC_REGNUM)
1144 (compare:CCFP (match_dup 0)
1145 (match_dup 1)))
1146 (set (reg:CCFP CC_REGNUM)
1147 (reg:CCFP VFPCC_REGNUM))]
1148 ""
1149 )
1151 (define_insn_and_split "*cmpsf_trap_split_vfp"
1152 [(set (reg:CCFPE CC_REGNUM)
1153 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
1154 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1155 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1156 "#"
1157 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1158 [(set (reg:CCFPE VFPCC_REGNUM)
1159 (compare:CCFPE (match_dup 0)
1160 (match_dup 1)))
1161 (set (reg:CCFPE CC_REGNUM)
1162 (reg:CCFPE VFPCC_REGNUM))]
1163 ""
1164 )
1166 (define_insn_and_split "*cmpdf_split_vfp"
1167 [(set (reg:CCFP CC_REGNUM)
1168 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
1169 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1170 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1171 "#"
1172 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1173 [(set (reg:CCFP VFPCC_REGNUM)
1174 (compare:CCFP (match_dup 0)
1175 (match_dup 1)))
1176 (set (reg:CCFP CC_REGNUM)
1177 (reg:CCFP VFPCC_REGNUM))]
1178 ""
1179 )
1181 (define_insn_and_split "*cmpdf_trap_split_vfp"
1182 [(set (reg:CCFPE CC_REGNUM)
1183 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
1184 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1185 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1186 "#"
1187 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1188 [(set (reg:CCFPE VFPCC_REGNUM)
1189 (compare:CCFPE (match_dup 0)
1190 (match_dup 1)))
1191 (set (reg:CCFPE CC_REGNUM)
1192 (reg:CCFPE VFPCC_REGNUM))]
1193 ""
1194 )
1197 ;; Comparison patterns
1199 ;; In the compare with FP zero case the ARM Architecture Reference Manual
1200 ;; specifies the immediate to be #0.0. However, some buggy assemblers only
1201 ;; accept #0. We don't want to autodetect broken assemblers, so output #0.
1202 (define_insn "*cmpsf_vfp"
1203 [(set (reg:CCFP VFPCC_REGNUM)
1204 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
1205 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1206 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1207 "@
1208 vcmp%?.f32\\t%0, %1
1209 vcmp%?.f32\\t%0, #0"
1210 [(set_attr "predicable" "yes")
1211 (set_attr "predicable_short_it" "no")
1212 (set_attr "type" "fcmps")]
1213 )
1215 (define_insn "*cmpsf_trap_vfp"
1216 [(set (reg:CCFPE VFPCC_REGNUM)
1217 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
1218 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1219 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1220 "@
1221 vcmpe%?.f32\\t%0, %1
1222 vcmpe%?.f32\\t%0, #0"
1223 [(set_attr "predicable" "yes")
1224 (set_attr "predicable_short_it" "no")
1225 (set_attr "type" "fcmps")]
1226 )
1228 (define_insn "*cmpdf_vfp"
1229 [(set (reg:CCFP VFPCC_REGNUM)
1230 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
1231 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1232 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1233 "@
1234 vcmp%?.f64\\t%P0, %P1
1235 vcmp%?.f64\\t%P0, #0"
1236 [(set_attr "predicable" "yes")
1237 (set_attr "predicable_short_it" "no")
1238 (set_attr "type" "fcmpd")]
1239 )
1241 (define_insn "*cmpdf_trap_vfp"
1242 [(set (reg:CCFPE VFPCC_REGNUM)
1243 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
1244 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1245 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1246 "@
1247 vcmpe%?.f64\\t%P0, %P1
1248 vcmpe%?.f64\\t%P0, #0"
1249 [(set_attr "predicable" "yes")
1250 (set_attr "predicable_short_it" "no")
1251 (set_attr "type" "fcmpd")]
1252 )
1254 ;; Fixed point to floating point conversions.
1255 (define_code_iterator FCVT [unsigned_float float])
1256 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1258 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1259 [(set (match_operand:SF 0 "s_register_operand" "=t")
1260 (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1261 (match_operand 2
1262 "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1263 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1264 "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
1265 [(set_attr "predicable" "yes")
1266 (set_attr "predicable_short_it" "no")
1267 (set_attr "type" "f_cvti2f")]
1268 )
1270 ;; Not the ideal way of implementing this. Ideally we would be able to split
1271 ;; this into a move to a DP register and then a vcvt.f64.i32
1272 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1273 [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1274 (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1275 (match_operand 2
1276 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1277 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1278 && !TARGET_VFP_SINGLE"
1279 "@
1280 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1281 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1282 vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1283 [(set_attr "predicable" "yes")
1284 (set_attr "ce_count" "2")
1285 (set_attr "predicable_short_it" "no")
1286 (set_attr "type" "f_cvti2f")
1287 (set_attr "length" "8")]
1288 )
1290 (define_insn "*combine_vcvtf2i"
1291 [(set (match_operand:SI 0 "s_register_operand" "=t")
1292 (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0")
1293 (match_operand 2
1294 "const_double_vcvt_power_of_two" "Dp")))))]
1295 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1296 "vcvt%?.s32.f32\\t%0, %1, %v2"
1297 [(set_attr "predicable" "yes")
1298 (set_attr "predicable_short_it" "no")
1299 (set_attr "type" "f_cvtf2i")]
1300 )
1302 ;; Store multiple insn used in function prologue.
1303 (define_insn "*push_multi_vfp"
1304 [(match_parallel 2 "multi_register_push"
1305 [(set (match_operand:BLK 0 "memory_operand" "=m")
1306 (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1307 UNSPEC_PUSH_MULT))])]
1308 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1309 "* return vfp_output_vstmd (operands);"
1310 [(set_attr "type" "f_stored")]
1311 )
1313 ;; VRINT round to integral instructions.
1314 ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
1315 ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
1316 ;; rintsf2, rintdf2.
1317 (define_insn "<vrint_pattern><SDF:mode>2"
1318 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1319 (unspec:SDF [(match_operand:SDF 1
1320 "register_operand" "<F_constraint>")]
1321 VRINT))]
1322 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
1323 "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1324 [(set_attr "predicable" "<vrint_predicable>")
1325 (set_attr "predicable_short_it" "no")
1326 (set_attr "type" "f_rint<vfp_type>")
1327 (set_attr "conds" "<vrint_conds>")]
1328 )
1330 ;; Implements the lround, lfloor and lceil optabs.
1331 (define_insn "l<vrint_pattern><su_optab><mode>si2"
1332 [(set (match_operand:SI 0 "register_operand" "=t")
1333 (FIXUORS:SI (unspec:SDF
1334 [(match_operand:SDF 1
1335 "register_operand" "<F_constraint>")] VCVT)))]
1336 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1337 "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
1338 [(set_attr "predicable" "no")
1339 (set_attr "conds" "unconditional")
1340 (set_attr "type" "f_cvtf2i")]
1341 )
1343 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
1344 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
1345 ;; operand will be returned when both operands are zero (i.e. they may not
1346 ;; honour signed zeroes), or when either operand is NaN. Therefore GCC
1347 ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
1348 ;; NaNs.
1350 (define_insn "smax<mode>3"
1351 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1352 (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1353 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1354 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
1355 "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1356 [(set_attr "type" "f_minmax<vfp_type>")
1357 (set_attr "conds" "unconditional")]
1358 )
1360 (define_insn "smin<mode>3"
1361 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1362 (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1363 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1364 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
1365 "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1366 [(set_attr "type" "f_minmax<vfp_type>")
1367 (set_attr "conds" "unconditional")]
1368 )
1370 ;; Scalar forms for the IEEE-754 fmax()/fmin() functions
1371 (define_insn "<fmaxmin><mode>3"
1372 [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
1373 (unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>")
1374 (match_operand:SDF 2 "s_register_operand" "<F_constraint>")]
1375 VMAXMINFNM))]
1376 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
1377 "<fmaxmin_op>.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1378 [(set_attr "type" "f_minmax<vfp_type>")
1379 (set_attr "conds" "unconditional")]
1380 )
1382 ;; Write Floating-point Status and Control Register.
1383 (define_insn "set_fpscr"
1384 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
1385 "TARGET_VFP && TARGET_HARD_FLOAT"
1386 "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
1387 [(set_attr "type" "mrs")])
1389 ;; Read Floating-point Status and Control Register.
1390 (define_insn "get_fpscr"
1391 [(set (match_operand:SI 0 "register_operand" "=r")
1392 (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
1393 "TARGET_VFP && TARGET_HARD_FLOAT"
1394 "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
1395 [(set_attr "type" "mrs")])
1398 ;; Unimplemented insns:
1399 ;; fldm*
1400 ;; fstm*
1401 ;; fmdhr et al (VFPv1)
1402 ;; Support for xD (single precision only) variants.
1403 ;; fmrrs, fmsrr