| blob | 096967808ace1398f699678051387606fad548e6 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This is the loop optimization pass of the compiler.
24 It finds invariant computations within loops and moves them
25 to the beginning of the loop. Then it identifies basic and
26 general induction variables. Strength reduction is applied to the general
27 induction variables, and induction variable elimination is applied to
28 the basic induction variables.
30 It also finds cases where
31 a register is set within the loop by zero-extending a narrower value
32 and changes these to zero the entire register once before the loop
33 and merely copy the low part within the loop.
35 Most of the complexity is in heuristics to decide when it is worth
36 while to do these things. */
58 /* Vector mapping INSN_UIDs to luids.
59 The luids are like uids but increase monotonically always.
60 We use them to see whether a jump comes from outside a given loop. */
64 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
65 number the insn is contained in. */
69 /* 1 + largest uid of any insn. */
73 /* 1 + luid of last insn. */
77 /* Number of loops detected in current function. Used as index to the
78 next few tables. */
82 /* Indexed by register number, contains the number of times the reg
83 is set during the loop being scanned.
84 During code motion, a negative value indicates a reg that has been
85 made a candidate; in particular -2 means that it is an candidate that
86 we know is equal to a constant and -1 means that it is an candidate
87 not known equal to a constant.
88 After code motion, regs moved have 0 (which is accurate now)
89 while the failed candidates have the original number of times set.
91 Therefore, at all times, == 0 indicates an invariant register;
92 < 0 a conditionally invariant one. */
96 /* Original value of set_in_loop; same except that this value
97 is not set negative for a reg whose sets have been made candidates
98 and not set to 0 for a reg that is moved. */
102 /* Index by register number, 1 indicates that the register
103 cannot be moved or strength reduced. */
107 /* Contains the insn in which a register was used if it was used
108 exactly once; contains const0_rtx if it was used more than once. */
112 /* Nonzero means reg N has already been moved out of one loop.
113 This reduces the desire to move it out of another. */
117 /* List of MEMs that are stored in this loop. */
121 /* The insn where the first of these was found. */
130 /* Array of MEMs that are used (read or written) in this loop, but
131 cannot be aliased by anything in this loop, except perhaps
132 themselves. In other words, if loop_mems[i] is altered during the
133 loop, it is altered by an expression that is rtx_equal_p to it. */
137 /* The index of the next available slot in LOOP_MEMS. */
141 /* The number of elements allocated in LOOP_MEMs. */
145 /* Nonzero if we don't know what MEMs were changed in the current
146 loop. This happens if the loop contains a call (in which case
147 `loop_info->has_call' will also be set) or if we store into more
148 than NUM_STORES MEMs. */
152 /* The above doesn't count any readonly memory locations that are stored.
153 This does. */
157 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
160 /* Count of memory write instructions discovered in the loop. */
163 /* Bound on pseudo register number before loop optimization.
164 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
167 /* The value to pass to the next call of reg_scan_update. */
170 /* This obstack is used in product_cheap_p to allocate its rtl. It
171 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
172 If we used the same obstack that it did, we would be deallocating
173 that array. */
177 /* This is where the pointer to the obstack being used for RTL is stored. */
181 #define obstack_chunk_alloc xmalloc
182 #define obstack_chunk_free free
183 \f
184 /* During the analysis of a loop, a chain of `struct movable's
185 is made to record all the movable insns found.
186 Then the entire chain can be scanned to decide which to move. */
188 struct movable
189 {
194 of any registers used within the LIBCALL. */
196 that must be moved with this one. */
199 may be adjusted when matching movables
200 that load the same value are found. */
202 including other movables that force this
203 or match this one. */
207 /* If PARTIAL is 1, GLOBAL means something different:
208 that the reg is live outside the range from where it is set
209 to the following label. */
213 In particular, moving it does not make it
214 invariant. */
216 load SRC, rather than copying INSN. */
218 first insn of a consecutive sets group. */
221 that we should avoid changing when clearing
222 the rest of the reg. */
226 };
232 /* Forward declarations. */
250 #if 0
252 #endif
315 rtx r;
320 rtx r1;
321 rtx r2;
324 /* Nonzero iff INSN is between START and END, inclusive. */
325 #define INSN_IN_RANGE_P(INSN, START, END) \
326 (INSN_UID (INSN) < max_uid_for_loop \
327 && INSN_LUID (INSN) >= INSN_LUID (START) \
328 && INSN_LUID (INSN) <= INSN_LUID (END))
330 #ifdef HAVE_decrement_and_branch_on_count
331 /* Test whether BCT applicable and safe. */
334 /* Auxiliary function that inserts the BCT pattern into the loop. */
338 /* Indirect_jump_in_function is computed once per function. */
346 \f
347 /* Relative gain of eliminating various kinds of operations. */
349 #if 0
352 #endif
354 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
355 copy the value of the strength reduced giv to its original register. */
358 /* Cost of using a register, to normalize the benefits of a giv. */
362 void
364 {
372 /* We multiply by 2 to reconcile the difference in scale between
373 these two ways of computing costs. Otherwise the cost of a copy
374 will be far less than the cost of an add. */
378 /* Free the objects we just allocated. */
381 /* Initialize the obstack used for rtl in product_cheap_p. */
383 }
384 \f
385 /* Compute the mapping from uids to luids.
386 LUIDs are numbers assigned to insns, like uids,
387 except that luids increase monotonically through the code.
388 Start at insn START and stop just before END. Assign LUIDs
389 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
390 static int
394 {
396 rtx insn;
399 {
402 /* Don't assign luids to line-number NOTEs, so that the distance in
403 luids between two insns is not affected by -g. */
407 else
408 /* Give a line number note the same luid as preceding insn. */
410 }
412 }
413 \f
414 /* Entry point of this file. Perform loop optimization
415 on the current function. F is the first insn of the function
416 and DUMPFILE is a stream for output of a trace of actions taken
417 (or 0 if none should be output). */
419 void
421 /* f is the first instruction of a chain of insns for one function */
422 rtx f;
425 {
441 /* Count the number of loops. */
445 {
448 max_loop_num++;
449 }
451 /* Don't waste time if no loops. */
459 /* Get size to use for tables indexed by uids.
460 Leave some space for labels allocated by find_and_verify_loops. */
467 /* Allocate storage for array of loops. */
471 /* Find and process each loop.
472 First, find them, and record them in order of their beginnings. */
475 /* Allocate and initialize auxiliary loop information. */
480 /* Now find all register lifetimes. This must be done after
481 find_and_verify_loops, because it might reorder the insns in the
482 function. */
485 /* This must occur after reg_scan so that registers created by gcse
486 will have entries in the register tables.
488 We could have added a call to reg_scan after gcse_main in toplev.c,
489 but moving this call to init_alias_analysis is more efficient. */
492 /* See if we went too far. Note that get_max_uid already returns
493 one more that the maximum uid of all insn. */
496 /* Now reset it to the actual size we need. See above. */
499 /* find_and_verify_loops has already called compute_luids, but it
500 might have rearranged code afterwards, so we need to recompute
501 the luids now. */
504 /* Don't leave gaps in uid_luid for insns that have been
505 deleted. It is possible that the first or last insn
506 using some register has been deleted by cross-jumping.
507 Make sure that uid_luid for that former insn's uid
508 points to the general area where that insn used to be. */
510 {
514 }
519 /* Determine if the function has indirect jump. On some systems
520 this prevents low overhead loop instructions from being used. */
523 /* Now scan the loops, last ones first, since this means inner ones are done
524 before outer ones. */
526 {
531 }
533 /* If there were lexical blocks inside the loop, they have been
534 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
535 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
536 the BLOCKs as well. */
542 /* Clean up. */
548 }
549 \f
550 /* Returns the next insn, in execution order, after INSN. START and
551 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
552 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
553 insn-stream; it is used with loops that are entered near the
554 bottom. */
556 static rtx
559 rtx insn;
560 {
564 {
566 /* Go to the top of the loop, and continue there. */
568 else
569 /* We're done. */
571 }
574 /* We're done. */
578 }
580 /* Optimize one loop described by LOOP. */
582 /* ??? Could also move memory writes out of loops if the destination address
583 is invariant, the source is invariant, the memory write is not volatile,
584 and if we can prove that no read inside the loop can read this address
585 before the write occurs. If there is a read of this address after the
586 write, then we can also mark the memory read as invariant. */
588 static void
592 {
596 /* Additional information about the current loop being processed
597 that is used to compute the number of loop iterations for loop
598 unrolling and doloop optimization. */
600 rtx p;
601 /* 1 if we are scanning insns that could be executed zero times. */
603 /* 1 if we are scanning insns that might never be executed
604 due to a subroutine call which might exit before they are reached. */
606 /* Jump insn that enters the loop, or 0 if control drops in. */
608 /* Number of insns in the loop. */
613 /* The SET from an insn, if it is the only SET in the insn. */
615 /* Chain describing insns movable in current loop. */
617 /* Last element in `movables' -- so we can add elements at the end. */
619 /* Ratio of extra register life span we can justify
620 for saving an instruction. More if loop doesn't call subroutines
621 since in that case saving an insn makes more difference
622 and more registers are available. */
624 /* Nonzero if we are scanning instructions in a sub-loop. */
630 /* Determine whether this loop starts with a jump down to a test at
631 the end. This will occur for a small number of loops with a test
632 that is too complex to duplicate in front of the loop.
634 We search for the first insn or label in the loop, skipping NOTEs.
635 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
636 (because we might have a loop executed only once that contains a
637 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
638 (in case we have a degenerate loop).
640 Note that if we mistakenly think that a loop is entered at the top
641 when, in fact, it is entered at the exit test, the only effect will be
642 slightly poorer optimization. Making the opposite error can generate
643 incorrect code. Since very few loops now start with a jump to the
644 exit test, the code here to detect that case is very conservative. */
647 p != loop_end
653 ;
657 /* Set up variables describing this loop. */
661 /* If loop has a jump before the first label,
662 the true entry is the target of that jump.
663 Start scan from there.
664 But record in LOOP->TOP the place where the end-test jumps
665 back to so we can scan that after the end of the loop. */
667 {
670 /* Loop entry must be unconditional jump (and not a RETURN) */
673 /* Check to see whether the jump actually
674 jumps out of the loop (meaning it's no loop).
675 This case can happen for things like
676 do {..} while (0). If this label was generated previously
677 by loop, we can't tell anything about it and have to reject
678 the loop. */
680 {
683 }
684 }
686 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
687 as required by loop_reg_used_before_p. So skip such loops. (This
688 test may never be true, but it's best to play it safe.)
690 Also, skip loops where we do not start scanning at a label. This
691 test also rejects loops starting with a JUMP_INSN that failed the
692 test above. */
696 {
701 }
703 /* Count number of times each reg is set during this loop.
704 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
705 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
707 /* Allocate extra space for REGS that might be created by
708 load_mems. We allocate a little extra slop as well, in the hopes
709 that even after the moving of movables creates some new registers
710 we won't have to reallocate these arrays. However, we do grow
711 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
722 {
725 }
727 #ifdef AVOID_CCMODE_COPIES
728 /* Don't try to move insns which set CC registers if we should not
729 create CCmode register copies. */
733 #endif
739 {
745 }
747 /* Scan through the loop finding insns that are safe to move.
748 Set set_in_loop negative for the reg being set, so that
749 this reg will be considered invariant for subsequent insns.
750 We consider whether subsequent insns use the reg
751 in deciding whether it is worth actually moving.
753 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
754 and therefore it is possible that the insns we are scanning
755 would never be executed. At such times, we must make sure
756 that it is safe to execute the insn once instead of zero times.
757 When MAYBE_NEVER is 0, all insns will be executed at least once
758 so that is not a problem. */
763 {
775 {
782 /* Figure out what to use as a source of this insn. If a REG_EQUIV
783 note is given or if a REG_EQUAL note with a constant operand is
784 specified, use it as the source and mark that we should move
785 this insn by calling emit_move_insn rather that duplicating the
786 insn.
788 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
789 is present. */
793 else
794 {
799 {
801 /* A libcall block can use regs that don't appear in
802 the equivalent expression. To move the libcall,
803 we must move those regs too. */
805 }
806 }
808 /* Don't try to optimize a register that was made
809 by loop-optimization for an inner loop.
810 We don't know its life-span, so we can't compute the benefit. */
812 ;
814 than the one where it is set (meaning that
815 something after this point in the loop might
816 depend on its value before the set). */
818 /* And the set is not guaranteed to be executed one
819 the loop starts, or the value before the set is
820 needed before the set occurs...
822 ??? Note we have quadratic behaviour here, mitigated
823 by the fact that the previous test will often fail for
824 large loops. Rather than re-scanning the entire loop
825 each time for register usage, we should build tables
826 of the register usage and use them here instead. */
827 && (maybe_never
829 /* It is unsafe to move the set.
831 This code used to consider it OK to move a set of a variable
832 which was not created by the user and not used in an exit test.
833 That behavior is incorrect and was removed. */
834 ;
840 || (tem1
841 = consec_sets_invariant_p
844 p)))
845 /* If the insn can cause a trap (such as divide by zero),
846 can't move it unless it's guaranteed to be executed
847 once loop is entered. Even a function call might
848 prevent the trap insn from being reached
849 (since it might exit!) */
852 {
856 /* A potential lossage is where we have a case where two insns
857 can be combined as long as they are both in the loop, but
858 we move one of them outside the loop. For large loops,
859 this can lose. The most common case of this is the address
860 of a function being called.
862 Therefore, if this register is marked as being used exactly
863 once if we are in a loop with calls (a "large loop"), see if
864 we can replace the usage of this register with the source
865 of this SET. If we can, delete this insn.
867 Don't do this if P has a REG_RETVAL note or if we have
868 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
879 && (! SMALL_REGISTER_CLASSES
882 /* This test is not redundant; SET_SRC (set) might be
883 a call-clobbered register and the life of REGNO
884 might span a call. */
886 VARRAY_RTX
890 VARRAY_RTX
892 {
893 /* Replace any usage in a REG_EQUAL note. Must copy the
894 new source, so that we don't get rtx sharing between the
895 SET_SOURCE and REG_NOTES of insn p. */
906 }
925 /* Set M->cond if either loop_invariant_p
926 or consec_sets_invariant_p returned 2
927 (only conditionally invariant). */
939 /* Add M to the end of the chain MOVABLES. */
942 else
947 {
948 /* It is possible for the first instruction to have a
949 REG_EQUAL note but a non-invariant SET_SRC, so we must
950 remember the status of the first instruction in case
951 the last instruction doesn't have a REG_EQUAL note. */
954 /* Skip this insn, not checking REG_LIBCALL notes. */
956 /* Skip the consecutive insns, if there are any. */
958 /* Back up to the last insn of the consecutive group. */
961 /* We must now reset m->move_insn, m->is_equiv, and possibly
962 m->set_src to correspond to the effects of all the
963 insns. */
967 else
968 {
972 else
975 }
977 }
978 }
979 /* If this register is always set within a STRICT_LOW_PART
980 or set to zero, then its high bytes are constant.
981 So clear them outside the loop and within the loop
982 just load the low bytes.
983 We must check that the machine has an instruction to do so.
984 Also, if the value loaded into the register
985 depends on the same register, this cannot be done. */
995 {
998 {
1012 /* If the insn may not be executed on some cycles,
1013 we can't clear the whole reg; clear just high part.
1014 Not even if the reg is used only within this loop.
1015 Consider this:
1016 while (1)
1017 while (s != t) {
1018 if (foo ()) x = *s;
1019 use (x);
1020 }
1021 Clearing x before the inner loop could clobber a value
1022 being saved from the last time around the outer loop.
1023 However, if the reg is not used outside this loop
1024 and all uses of the register are in the same
1025 basic block as the store, there is no problem.
1027 If this insn was made by loop, we don't know its
1028 INSN_LUID and hence must make a conservative
1029 assumption. */
1035 || (labels_in_range_p
1039 else
1048 /* Add M to the end of the chain MOVABLES. */
1051 else
1054 }
1055 }
1056 }
1057 /* Past a call insn, we get to insns which might not be executed
1058 because the call might exit. This matters for insns that trap.
1059 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1060 so they don't count. */
1063 /* Past a label or a jump, we get to insns for which we
1064 can't count on whether or how many times they will be
1065 executed during each iteration. Therefore, we can
1066 only move out sets of trivial variables
1067 (those not used after the loop). */
1068 /* Similar code appears twice in strength_reduce. */
1070 /* If we enter the loop in the middle, and scan around to the
1071 beginning, don't set maybe_never for that. This must be an
1072 unconditional jump, otherwise the code at the top of the
1073 loop might never be executed. Unconditional jumps are
1074 followed a by barrier then loop end. */
1080 {
1081 /* At the virtual top of a converted loop, insns are again known to
1082 be executed: logically, the loop begins here even though the exit
1083 code has been duplicated. */
1087 loop_depth++;
1089 loop_depth--;
1090 }
1091 }
1093 /* If one movable subsumes another, ignore that other. */
1097 /* For each movable insn, see if the reg that it loads
1098 leads when it dies right into another conditionally movable insn.
1099 If so, record that the second insn "forces" the first one,
1100 since the second can be moved only if the first is. */
1104 /* See if there are multiple movable insns that load the same value.
1105 If there are, make all but the first point at the first one
1106 through the `match' field, and add the priorities of them
1107 all together as the priority of the first. */
1111 /* Now consider each movable insn to decide whether it is worth moving.
1112 Store 0 in set_in_loop for each reg that is moved.
1114 Generally this increases code size, so do not move moveables when
1115 optimizing for code size. */
1120 /* Now candidates that still are negative are those not moved.
1121 Change set_in_loop to indicate that those are not actually invariant. */
1126 /* Now that we've moved some things out of the loop, we might be able to
1127 hoist even more memory references. */
1134 ;
1141 {
1147 }
1153 }
1154 \f
1155 /* Add elements to *OUTPUT to record all the pseudo-regs
1156 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1158 void
1162 {
1170 {
1188 }
1192 {
1196 {
1205 }
1206 }
1207 }
1208 \f
1209 /* Check what regs are referred to in the libcall block ending with INSN,
1210 aside from those mentioned in the equivalent value.
1211 If there are none, return 0.
1212 If there are one or more, return an EXPR_LIST containing all of them. */
1214 rtx
1217 {
1222 /* First, find all the regs used in the libcall block
1223 that are not mentioned as inputs to the result. */
1226 {
1231 }
1234 }
1235 \f
1236 /* Return 1 if all uses of REG
1237 are between INSN and the end of the basic block. */
1239 static int
1242 {
1244 rtx p;
1249 /* Search this basic block for the already recorded last use of the reg. */
1251 {
1253 {
1259 /* Ordinary insn: if this is the last use, we win. */
1265 /* Jump insn: if this is the last use, we win. */
1268 /* Otherwise, it's the end of the basic block, so we lose. */
1273 /* It's the end of the basic block, so we lose. */
1278 }
1279 }
1281 /* The "last use" that was recorded can't be found after the first
1282 use. This can happen when the last use was deleted while
1283 processing an inner loop, this inner loop was then completely
1284 unrolled, and the outer loop is always exited after the inner loop,
1285 so that everything after the first use becomes a single basic block. */
1287 }
1288 \f
1289 /* Compute the benefit of eliminating the insns in the block whose
1290 last insn is LAST. This may be a group of insns used to compute a
1291 value directly or can contain a library call. */
1293 static int
1295 rtx last;
1296 {
1297 rtx insn;
1302 {
1305 routine. */
1309 benefit++;
1310 }
1313 }
1314 \f
1315 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1317 static rtx
1319 rtx insn;
1321 {
1323 {
1324 rtx temp;
1326 /* If first insn of libcall sequence, skip to end. */
1327 /* Do this at start of loop, since INSN is guaranteed to
1328 be an insn here. */
1335 }
1338 }
1340 /* Ignore any movable whose insn falls within a libcall
1341 which is part of another movable.
1342 We make use of the fact that the movable for the libcall value
1343 was made later and so appears later on the chain. */
1345 static void
1348 {
1352 {
1353 /* Is this a movable for the value of a libcall? */
1356 {
1357 rtx insn;
1358 /* Check for earlier movables inside that range,
1359 and mark them invalid. We cannot use LUIDs here because
1360 insns created by loop.c for prior loops don't have LUIDs.
1361 Rather than reject all such insns from movables, we just
1362 explicitly check each insn in the libcall (since invariant
1363 libcalls aren't that common). */
1368 }
1369 }
1370 }
1372 /* For each movable insn, see if the reg that it loads
1373 leads when it dies right into another conditionally movable insn.
1374 If so, record that the second insn "forces" the first one,
1375 since the second can be moved only if the first is. */
1377 static void
1380 {
1383 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1385 {
1388 /* ??? Could this be a bug? What if CSE caused the
1389 register of M1 to be used after this insn?
1390 Since CSE does not update regno_last_uid,
1391 this insn M->insn might not be where it dies.
1392 But very likely this doesn't matter; what matters is
1393 that M's reg is computed from M1's reg. */
1398 /* If m->consec, m->set_src isn't valid. */
1402 /* Increase the priority of the moving the first insn
1403 since it permits the second to be moved as well. */
1405 {
1409 }
1410 }
1411 }
1412 \f
1413 /* Find invariant expressions that are equal and can be combined into
1414 one register. */
1416 static void
1420 {
1425 /* Regs that are set more than once are not allowed to match
1426 or be matched. I'm no longer sure why not. */
1427 /* Perhaps testing m->consec_sets would be more appropriate here? */
1431 {
1438 /* We want later insns to match the first one. Don't make the first
1439 one match any later ones. So start this loop at m->next. */
1442 /* A reg used outside the loop mustn't be eliminated. */
1444 /* A reg used for zero-extending mustn't be eliminated. */
1447 ||
1448 (
1449 /* Can combine regs with different modes loaded from the
1450 same constant only if the modes are the same or
1451 if both are integer modes with M wider or the same
1452 width as M1. The check for integer is redundant, but
1453 safe, since the only case of differing destination
1454 modes with equal sources is when both sources are
1455 VOIDmode, i.e., CONST_INT. */
1461 /* See if the source of M1 says it matches M. */
1465 movables))))
1468 {
1474 }
1475 }
1477 /* Now combine the regs used for zero-extension.
1478 This can be done for those not marked `global'
1479 provided their lives don't overlap. */
1483 {
1486 /* Combine all the registers for extension from mode MODE.
1487 Don't combine any that are used outside this loop. */
1491 {
1497 {
1498 /* First one: don't check for overlap, just record it. */
1501 }
1503 /* Make sure they extend to the same mode.
1504 (Almost always true.) */
1508 /* We already have one: check for overlap with those
1509 already combined together. */
1516 /* No overlap: we can combine this with the others. */
1522 overlap: ;
1523 }
1524 }
1526 /* Clean up. */
1528 }
1529 \f
1530 /* Return 1 if regs X and Y will become the same if moved. */
1532 static int
1536 {
1553 }
1555 /* Return 1 if X and Y are identical-looking rtx's.
1556 This is the Lisp function EQUAL for rtx arguments.
1558 If two registers are matching movables or a movable register and an
1559 equivalent constant, consider them equal. */
1561 static int
1565 {
1579 /* If we have a register and a constant, they may sometimes be
1580 equal. */
1583 {
1588 }
1591 {
1596 }
1598 /* Otherwise, rtx's of different codes cannot be equal. */
1602 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1603 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1608 /* These three types of rtx's can be compared nonrecursively. */
1617 /* Compare the elements. If any pair of corresponding elements
1618 fail to match, return 0 for the whole things. */
1622 {
1624 {
1636 /* Two vectors must have the same length. */
1640 /* And the corresponding elements must match. */
1657 /* These are just backpointers, so they don't matter. */
1663 /* It is believed that rtx's at this level will never
1664 contain anything but integers and other rtx's,
1665 except for within LABEL_REFs and SYMBOL_REFs. */
1668 }
1669 }
1671 }
1672 \f
1673 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1674 insns in INSNS which use the reference. */
1676 static void
1678 rtx x;
1679 rtx insns;
1680 {
1684 rtx insn;
1687 {
1688 /* This code used to ignore labels that referred to dispatch tables to
1689 avoid flow generating (slighly) worse code.
1691 We no longer ignore such label references (see LABEL_REF handling in
1692 mark_jump_label for additional information). */
1697 }
1701 {
1707 }
1708 }
1709 \f
1710 /* Scan MOVABLES, and move the insns that deserve to be moved.
1711 If two matching movables are combined, replace one reg with the
1712 other throughout. */
1714 static void
1721 {
1727 /* Map of pseudo-register replacements to handle combining
1728 when we move several insns that load the same value
1729 into different pseudo-registers. */
1736 {
1737 /* Describe this movable insn. */
1740 {
1761 }
1763 /* Count movables. Value used in heuristics in strength_reduce. */
1764 num_movables++;
1766 /* Ignore the insn if it's already done (it matched something else).
1767 Otherwise, see if it is now safe to move. */
1779 {
1784 /* We have an insn that is safe to move.
1785 Compute its desirability. */
1796 /* An insn MUST be moved if we already moved something else
1797 which is safe only if this one is moved too: that is,
1798 if already_moved[REGNO] is nonzero. */
1800 /* An insn is desirable to move if the new lifetime of the
1801 register is no more than THRESHOLD times the old lifetime.
1802 If it's not desirable, it means the loop is so big
1803 that moving won't speed things up much,
1804 and it is liable to make register usage worse. */
1806 /* It is also desirable to move if it can be moved at no
1807 extra cost because something else was already moved. */
1810 || flag_move_all_movables
1815 {
1820 /* Now move the insns that set the reg. */
1823 {
1826 /* Find the end of this chain of matching regs.
1827 Thus, we load each reg in the chain from that one reg.
1828 And that reg is loaded with 0 directly,
1829 since it has ->match == 0. */
1835 /* Mark the moved, invariant reg as being allowed to
1836 share a hard reg with the other matching invariant. */
1840 regs_may_share
1843 regs_may_share));
1851 }
1852 /* If we are to re-generate the item being moved with a
1853 new move insn, first delete what we have and then emit
1854 the move insn before the loop. */
1856 {
1860 {
1861 /* If this is the first insn of a library call sequence,
1862 skip to the end. */
1867 /* If this is the last insn of a libcall sequence, then
1868 delete every insn in the sequence except the last.
1869 The last insn is handled in the normal manner. */
1872 {
1876 }
1881 /* simplify_giv_expr expects that it can walk the insns
1882 at m->insn forwards and see this old sequence we are
1883 tossing here. delete_insn does preserve the next
1884 pointers, but when we skip over a NOTE we must fix
1885 it up. Otherwise that code walks into the non-deleted
1886 insn stream. */
1889 }
1907 /* The more regs we move, the less we like moving them. */
1909 }
1910 else
1911 {
1913 {
1916 /* If first insn of libcall sequence, skip to end. */
1917 /* Do this at start of loop, since p is guaranteed to
1918 be an insn here. */
1923 /* If last insn of libcall sequence, move all
1924 insns except the last before the loop. The last
1925 insn is handled in the normal manner. */
1928 {
1936 {
1937 rtx body;
1938 rtx n;
1939 rtx next;
1946 /* Find the next insn after TEMP,
1947 not counting USE or NOTE insns. */
1955 /* If that is the call, this may be the insn
1956 that loads the function address.
1958 Extract the function address from the insn
1959 that loads it into a register.
1960 If this insn was cse'd, we get incorrect code.
1962 So emit a new move insn that copies the
1963 function address into the register that the
1964 call insn will use. flow.c will delete any
1965 redundant stores that we have created. */
1970 NULL_RTX)))
1971 {
1977 }
1978 /* We have the call insn.
1979 If it uses the register we suspect it might,
1980 load it with the correct address directly. */
1985 fn_address),
1986 fn_address_insn);
1989 {
1991 /* Because the USAGE information potentially
1992 contains objects other than hard registers
1993 we need to copy it. */
1997 }
1998 else
2006 }
2009 }
2011 {
2012 /* P sets REG to zero; but we should clear only
2013 the bits that are not covered by the mode
2014 m->savemode. */
2016 rtx sequence;
2017 rtx tem;
2020 tem = expand_binop
2033 }
2035 {
2037 /* Because the USAGE information potentially
2038 contains objects other than hard registers
2039 we need to copy it. */
2043 }
2045 {
2046 /* The SET_SRC might not be invariant, so we must
2047 use the REG_EQUAL note. */
2061 }
2062 else
2066 {
2069 /* If there is a REG_EQUAL note present whose value
2070 is not loop invariant, then delete it, since it
2071 may cause problems with later optimization passes.
2072 It is possible for cse to create such notes
2073 like this as a result of record_jump_cond. */
2078 }
2087 /* If library call, now fix the REG_NOTES that contain
2088 insn pointers, namely REG_LIBCALL on FIRST
2089 and REG_RETVAL on I1. */
2091 {
2095 }
2101 /* simplify_giv_expr expects that it can walk the insns
2102 at m->insn forwards and see this old sequence we are
2103 tossing here. delete_insn does preserve the next
2104 pointers, but when we skip over a NOTE we must fix
2105 it up. Otherwise that code walks into the non-deleted
2106 insn stream. */
2109 }
2111 /* The more regs we move, the less we like moving them. */
2113 }
2115 /* Any other movable that loads the same register
2116 MUST be moved. */
2119 /* This reg has been moved out of one loop. */
2122 /* The reg set here is now invariant. */
2128 /* Change the length-of-life info for the register
2129 to say it lives at least the full length of this loop.
2130 This will help guide optimizations in outer loops. */
2133 /* This is the old insn before all the moved insns.
2134 We can't use the moved insn because it is out of range
2135 in uid_luid. Only the old insns have luids. */
2140 /* Combine with this moved insn any other matching movables. */
2145 {
2146 rtx temp;
2148 /* Schedule the reg loaded by M1
2149 for replacement so that shares the reg of M.
2150 If the modes differ (only possible in restricted
2151 circumstances, make a SUBREG.
2153 Note this assumes that the target dependent files
2154 treat REG and SUBREG equally, including within
2155 GO_IF_LEGITIMATE_ADDRESS and in all the
2156 predicates since we never verify that replacing the
2157 original register with a SUBREG results in a
2158 recognizable insn. */
2161 else
2166 /* Get rid of the matching insn
2167 and prevent further processing of it. */
2170 /* if library call, delete all insn except last, which
2171 is deleted below */
2173 NULL_RTX)))
2174 {
2178 }
2181 /* Any other movable that loads the same register
2182 MUST be moved. */
2185 /* The reg merged here is now invariant,
2186 if the reg it matches is invariant. */
2189 }
2190 }
2193 }
2199 }
2204 /* Go through all the instructions in the loop, making
2205 all the register substitutions scheduled in REG_MAP. */
2209 {
2213 }
2215 /* Clean up. */
2218 }
2219 \f
2220 #if 0
2221 /* Scan X and replace the address of any MEM in it with ADDR.
2222 REG is the address that MEM should have before the replacement. */
2224 static void
2227 {
2236 {
2248 /* Short cut for very common case. */
2253 /* Short cut for very common case. */
2258 /* If this MEM uses a reg other than the one we expected,
2259 something is wrong. */
2267 }
2271 {
2275 {
2279 }
2280 }
2281 }
2282 #endif
2283 \f
2284 /* Return the number of memory refs to addresses that vary
2285 in the rtx X. */
2287 static int
2290 rtx x;
2291 {
2302 {
2319 }
2324 {
2328 {
2332 }
2333 }
2335 }
2337 \f
2338 #if 0
2339 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2340 Replace it with an instruction to load just the low bytes
2341 if the machine supports such an instruction,
2342 and insert above LOOP_START an instruction to clear the register. */
2344 static void
2347 {
2351 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2352 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2354 new
2355 = gen_rtx_SET
2357 gen_rtx_STRICT_LOW_PART
2366 {
2369 /* Clear destination register before the loop. */
2372 loop_start);
2374 /* Inside the loop, just load the low part. */
2376 }
2377 }
2378 #endif
2379 \f
2380 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2381 `has_call', `has_volatile', and `has_tablejump' within LOOP.
2382 Set the global variables `unknown_address_altered',
2383 `unknown_constant_address_altered', and `num_mem_sets'. Also, fill
2384 in the array `loop_mems' and the list `loop_store_mems'. */
2386 static void
2389 {
2391 rtx insn;
2395 /* The label after END. Jumping here is just like falling off the
2396 end of the loop. We use next_nonnote_insn instead of next_label
2397 as a hedge against the (pathological) case where some actual insn
2398 might end up between the two. */
2419 {
2421 {
2423 {
2425 /* Count number of loops contained in this one. */
2427 }
2429 {
2432 {
2435 }
2436 }
2438 {
2441 }
2443 {
2444 /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for
2445 or while style loop, with a loop exit test at the
2446 start. Thus, we can assume that the loop condition
2447 was true when the loop was entered. */
2450 }
2451 }
2453 {
2457 }
2459 {
2479 {
2481 {
2484 }
2485 else
2486 {
2488 }
2492 {
2494 {
2495 /* Something tricky. */
2498 }
2501 {
2502 /* A jump outside the current loop. */
2505 }
2506 }
2511 }
2512 }
2515 }
2517 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2519 ! unknown_address_altered
2520 /* An exception thrown by a called function might land us
2521 anywhere. */
2523 /* We don't want loads for MEMs moved to a location before the
2524 one at which their stack memory becomes allocated. (Note
2525 that this is not a problem for malloc, etc., since those
2526 require actual function calls. */
2527 && ! current_function_calls_alloca
2528 /* There are ways to leave the loop other than falling off the
2529 end. */
2534 }
2535 \f
2536 /* LOOP->CONT_DOMINATOR is now the last label between the loop start
2537 and the continue note that is a the destination of a (cond)jump after
2538 the continue note. If there is any (cond)jump between the loop start
2539 and what we have so far as LOOP->CONT_DOMINATOR that has a
2540 target between LOOP->DOMINATOR and the continue note, move
2541 LOOP->CONT_DOMINATOR forward to that label; if a jump's
2542 destination cannot be determined, clear LOOP->CONT_DOMINATOR. */
2544 static void
2547 {
2548 rtx insn;
2551 /* This can happen for an empty loop, e.g. in
2552 gcc.c-torture/compile/920410-2.c */
2555 {
2558 }
2561 {
2564 {
2568 /* If it is not a jump we can easily understand or for
2569 which we do not have jump target information in the JUMP_LABEL
2570 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2571 LOOP->CONT_DOMINATOR. */
2575 {
2578 }
2582 && (label_luid
2585 }
2586 }
2587 }
2589 /* Scan the function looking for loops. Record the start and end of each loop.
2590 Also mark as invalid loops any loops that contain a setjmp or are branched
2591 to from outside the loop. */
2593 static void
2595 rtx f;
2597 {
2598 rtx insn;
2599 rtx label;
2609 /* If there are jumps to undefined labels,
2610 treat them as jumps out of any/all loops.
2611 This also avoids writing past end of tables when there are no loops. */
2614 /* Find boundaries of loops, mark which loops are contained within
2615 loops, and invalidate loops that have setjmp. */
2620 {
2623 {
2627 num_loops++;
2634 /* In this case, we must invalidate our current loop and any
2635 enclosing loop. */
2637 {
2643 }
2660 }
2661 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2662 and NOTE_INSN_LOOP_END notes, update loop->dominator. */
2666 {
2673 do
2674 {
2675 /* First see if we care about this loop. */
2677 {
2678 /* If the jump destination is not known, invalidate
2679 loop->const_dominator. */
2682 else
2683 /* Check if the destination is between loop start and
2684 cont. */
2689 /* And if there is no later destination already
2690 recorded. */
2695 }
2697 }
2699 }
2701 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2702 enclosing loop, but this doesn't matter. */
2704 }
2706 /* Any loop containing a label used in an initializer must be invalidated,
2707 because it can be jumped into from anywhere. */
2710 {
2714 }
2716 /* Any loop containing a label used for an exception handler must be
2717 invalidated, because it can be jumped into from anywhere. */
2720 {
2724 }
2726 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2727 loop that it is not contained within, that loop is marked invalid.
2728 If any INSN or CALL_INSN uses a label's address, then the loop containing
2729 that label is marked invalid, because it could be jumped into from
2730 anywhere.
2732 Also look for blocks of code ending in an unconditional branch that
2733 exits the loop. If such a block is surrounded by a conditional
2734 branch around the block, move the block elsewhere (see below) and
2735 invert the jump to point to the code block. This may eliminate a
2736 label in our loop and will simplify processing by both us and a
2737 possible second cse pass. */
2741 {
2745 {
2748 {
2752 }
2753 }
2760 /* See if this is an unconditional branch outside the loop. */
2767 {
2768 rtx p;
2774 /* Go backwards until we reach the start of the loop, a label,
2775 or a JUMP_INSN. */
2782 ;
2784 /* Check for the case where we have a jump to an inner nested
2785 loop, and do not perform the optimization in that case. */
2788 {
2791 {
2796 }
2797 }
2799 /* Make sure that the target of P is within the current loop. */
2805 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2806 we have a block of code to try to move.
2808 We look backward and then forward from the target of INSN
2809 to find a BARRIER at the same loop depth as the target.
2810 If we find such a BARRIER, we make a new label for the start
2811 of the block, invert the jump in P and point it to that label,
2812 and move the block of code to the spot we found. */
2817 /* Just ignore jumps to labels that were never emitted.
2818 These always indicate compilation errors. */
2823 /* If it's not safe to move the sequence, then we
2824 mustn't try. */
2827 {
2828 rtx target
2835 /* Don't move things inside a tablejump. */
2848 /* Don't move things inside a tablejump. */
2859 {
2863 /* Ensure our label doesn't go away. */
2866 /* Verify that uid_loop is large enough and that
2867 we can invert P. */
2869 {
2872 /* If no suitable BARRIER was found, create a suitable
2873 one before TARGET. Since TARGET is a fall through
2874 path, we'll need to insert an jump around our block
2875 and a add a BARRIER before TARGET.
2877 This creates an extra unconditional jump outside
2878 the loop. However, the benefits of removing rarely
2879 executed instructions from inside the loop usually
2880 outweighs the cost of the extra unconditional jump
2881 outside the loop. */
2883 {
2884 rtx temp;
2891 }
2893 /* Include the BARRIER after INSN and copy the
2894 block after LOC. */
2896 last_insn_to_move);
2899 /* All those insns are now in TARGET_LOOP. */
2905 /* The label jumped to by INSN is no longer a loop exit.
2906 Unless INSN does not have a label (e.g., it is a
2907 RETURN insn), search loop->exit_labels to find
2908 its label_ref, and remove it. Also turn off
2909 LABEL_OUTSIDE_LOOP_P bit. */
2911 {
2916 {
2920 else
2923 }
2929 /* If we didn't find it, then something is
2930 wrong. */
2933 }
2935 /* P is now a jump outside the loop, so it must be put
2936 in loop->exit_labels, and marked as such.
2937 The easiest way to do this is to just call
2938 mark_loop_jump again for P. */
2941 /* If INSN now jumps to the insn after it,
2942 delete INSN. */
2947 }
2949 /* Continue the loop after where the conditional
2950 branch used to jump, since the only branch insn
2951 in the block (if it still remains) is an inter-loop
2952 branch and hence needs no processing. */
2958 /* This loop will be continued with NEXT_INSN (insn). */
2960 }
2961 }
2962 }
2963 }
2964 }
2966 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2967 loops it is contained in, mark the target loop invalid.
2969 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2971 static void
2973 rtx x;
2975 {
2981 {
2993 /* There could be a label reference in here. */
3005 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3017 /* Link together all labels that branch outside the loop. This
3018 is used by final_[bg]iv_value and the loop unrolling code. Also
3019 mark this LABEL_REF so we know that this branch should predict
3020 false. */
3022 /* A check to make sure the label is not in an inner nested loop,
3023 since this does not count as a loop exit. */
3025 {
3030 }
3031 else
3035 {
3044 }
3046 /* If this is inside a loop, but not in the current loop or one enclosed
3047 by it, it invalidates at least one loop. */
3052 /* We must invalidate every nested loop containing the target of this
3053 label, except those that also contain the jump insn. */
3056 {
3057 /* Stop when we reach a loop that also contains the jump insn. */
3062 /* If we get here, we know we need to invalidate a loop. */
3069 }
3073 /* If this is not setting pc, ignore. */
3095 /* Strictly speaking this is not a jump into the loop, only a possible
3096 jump out of the loop. However, we have no way to link the destination
3097 of this jump onto the list of exit labels. To be safe we mark this
3098 loop and any containing loops as invalid. */
3100 {
3102 {
3108 }
3109 }
3111 }
3112 }
3113 \f
3114 /* Return nonzero if there is a label in the range from
3115 insn INSN to and including the insn whose luid is END
3116 INSN must have an assigned luid (i.e., it must not have
3117 been previously created by loop.c). */
3119 static int
3121 rtx insn;
3123 {
3125 {
3129 }
3132 }
3134 /* Record that a memory reference X is being set. */
3136 static void
3138 rtx x;
3139 rtx y ATTRIBUTE_UNUSED;
3141 {
3145 /* Count number of memory writes.
3146 This affects heuristics in strength_reduce. */
3147 num_mem_sets++;
3149 /* BLKmode MEM means all memory is clobbered. */
3151 {
3154 else
3158 }
3161 }
3163 /* X is a value modified by an INSN that references a biv inside a loop
3164 exit test (ie, X is somehow related to the value of the biv). If X
3165 is a pseudo that is used more than once, then the biv is (effectively)
3166 used more than once. DATA is really an `int *', and is set if the
3167 biv is used more than once. */
3169 static void
3171 rtx x;
3172 rtx y ATTRIBUTE_UNUSED;
3174 {
3187 /* If we do not have usage information, or if we know the register
3188 is used more than once, note that fact for check_dbra_loop. */
3193 }
3194 \f
3195 /* Return nonzero if the rtx X is invariant over the current loop.
3197 The value is 2 if we refer to something only conditionally invariant.
3199 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3200 Otherwise, a memory ref is invariant if it does not conflict with
3201 anything stored in `loop_store_mems'. */
3203 int
3207 {
3212 rtx mem_list_entry;
3218 {
3226 /* A LABEL_REF is normally invariant, however, if we are unrolling
3227 loops, and this label is inside the loop, then it isn't invariant.
3228 This is because each unrolled copy of the loop body will have
3229 a copy of this label. If this was invariant, then an insn loading
3230 the address of this label into a register might get moved outside
3231 the loop, and then each loop body would end up using the same label.
3233 We don't know the loop bounds here though, so just fail for all
3234 labels. */
3237 else
3246 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3247 since the reg might be set by initialization within the loop. */
3264 /* Volatile memory references must be rejected. Do this before
3265 checking for read-only items, so that volatile read-only items
3266 will be rejected also. */
3270 /* If we had a subroutine call, any location in memory could
3271 have been clobbered. We used to test here for volatile and
3272 readonly, but true_dependence knows how to do that better
3273 than we do. */
3278 /* See if there is any dependence between a store and this load. */
3281 {
3287 }
3289 /* It's not invalidated by a store in memory
3290 but we must still verify the address is invariant. */
3294 /* Don't mess with insns declared volatile. */
3301 }
3305 {
3307 {
3313 }
3315 {
3318 {
3324 }
3326 }
3327 }
3330 }
3332 \f
3333 /* Return nonzero if all the insns in the loop that set REG
3334 are INSN and the immediately following insns,
3335 and if each of those insns sets REG in an invariant way
3336 (not counting uses of REG in them).
3338 The value is 2 if some of these insns are only conditionally invariant.
3340 We assume that INSN itself is the first set of REG
3341 and that its source is invariant. */
3343 static int
3348 {
3351 rtx temp;
3352 /* Number of sets we have to insist on finding after INSN. */
3358 /* If N_SETS hit the limit, we can't rely on its value. */
3365 {
3367 rtx set;
3372 /* If library call, skip to end of it. */
3381 {
3386 {
3387 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3388 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3389 notes are OK. */
3395 }
3396 }
3398 count--;
3400 {
3403 }
3404 }
3407 /* If loop_invariant_p ever returned 2, we return 2. */
3409 }
3411 #if 0
3412 /* I don't think this condition is sufficient to allow INSN
3413 to be moved, so we no longer test it. */
3415 /* Return 1 if all insns in the basic block of INSN and following INSN
3416 that set REG are invariant according to TABLE. */
3418 static int
3422 {
3427 {
3436 {
3439 }
3440 }
3441 }
3443 \f
3444 /* Look at all uses (not sets) of registers in X. For each, if it is
3445 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3446 a different insn, set USAGE[REGNO] to const0_rtx. */
3448 static void
3450 rtx insn;
3451 rtx x;
3452 varray_type usage;
3453 {
3465 {
3466 /* Don't count SET_DEST if it is a REG; otherwise count things
3467 in SET_DEST because if a register is partially modified, it won't
3468 show up as a potential movable so we don't care how USAGE is set
3469 for it. */
3473 }
3474 else
3476 {
3482 }
3483 }
3484 \f
3485 /* Count and record any set in X which is contained in INSN. Update
3486 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3488 static void
3491 varray_type may_not_move;
3493 {
3495 /* Don't move a reg that has an explicit clobber.
3496 It's not worth the pain to try to do it correctly. */
3500 {
3508 {
3510 /* If this is the first setting of this reg
3511 in current basic block, and it was set before,
3512 it must be set in two basic blocks, so it cannot
3513 be moved out of the loop. */
3517 /* If this is not first setting in current basic block,
3518 see if reg was used in between previous one and this.
3519 If so, neither one can be moved. */
3526 }
3527 }
3528 }
3530 /* Increment SET_IN_LOOP at the index of each register
3531 that is modified by an insn between FROM and TO.
3532 If the value of an element of SET_IN_LOOP becomes 127 or more,
3533 stop incrementing it, to avoid overflow.
3535 Store in SINGLE_USAGE[I] the single insn in which register I is
3536 used, if it is only used once. Otherwise, it is set to 0 (for no
3537 uses) or const0_rtx for more than one use. This parameter may be zero,
3538 in which case this processing is not done.
3540 Store in *COUNT_PTR the number of actual instruction
3541 in the loop. We use this to decide what is worth moving out. */
3543 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3544 In that case, it is the insn that last set reg n. */
3546 static void
3549 varray_type may_not_move;
3550 varray_type single_usage;
3553 {
3559 {
3561 {
3564 /* Record registers that have exactly one use. */
3567 /* Include uses in REG_EQUAL notes. */
3575 {
3580 }
3581 }
3585 }
3588 /* Clean up. */
3590 }
3591 \f
3592 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3593 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3594 contained in insn INSN is used by any insn that precedes INSN in
3595 cyclic order starting from the loop entry point.
3597 We don't want to use INSN_LUID here because if we restrict INSN to those
3598 that have a valid INSN_LUID, it means we cannot move an invariant out
3599 from an inner loop past two loops. */
3601 static int
3605 {
3607 rtx p;
3609 /* Scan forward checking for register usage. If we hit INSN, we
3610 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3612 {
3619 }
3622 }
3623 \f
3624 /* A "basic induction variable" or biv is a pseudo reg that is set
3625 (within this loop) only by incrementing or decrementing it. */
3626 /* A "general induction variable" or giv is a pseudo reg whose
3627 value is a linear function of a biv. */
3629 /* Bivs are recognized by `basic_induction_var';
3630 Givs by `general_induction_var'. */
3632 /* Indexed by register number, indicates whether or not register is an
3633 induction variable, and if so what type. */
3635 varray_type reg_iv_type;
3637 /* Indexed by register number, contains pointer to `struct induction'
3638 if register is an induction variable. This holds general info for
3639 all induction variables. */
3641 varray_type reg_iv_info;
3643 /* Indexed by register number, contains pointer to `struct iv_class'
3644 if register is a basic induction variable. This holds info describing
3645 the class (a related group) of induction variables that the biv belongs
3646 to. */
3650 /* The head of a list which links together (via the next field)
3651 every iv class for the current loop. */
3655 /* Givs made from biv increments are always splittable for loop unrolling.
3656 Since there is no regscan info for them, we have to keep track of them
3657 separately. */
3660 /* Communication with routines called via `note_stores'. */
3664 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3668 /* ??? Unfinished optimizations, and possible future optimizations,
3669 for the strength reduction code. */
3671 /* ??? The interaction of biv elimination, and recognition of 'constant'
3672 bivs, may cause problems. */
3674 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3675 performance problems.
3677 Perhaps don't eliminate things that can be combined with an addressing
3678 mode. Find all givs that have the same biv, mult_val, and add_val;
3679 then for each giv, check to see if its only use dies in a following
3680 memory address. If so, generate a new memory address and check to see
3681 if it is valid. If it is valid, then store the modified memory address,
3682 otherwise, mark the giv as not done so that it will get its own iv. */
3684 /* ??? Could try to optimize branches when it is known that a biv is always
3685 positive. */
3687 /* ??? When replace a biv in a compare insn, we should replace with closest
3688 giv so that an optimized branch can still be recognized by the combiner,
3689 e.g. the VAX acb insn. */
3691 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3692 was rerun in loop_optimize whenever a register was added or moved.
3693 Also, some of the optimizations could be a little less conservative. */
3694 \f
3695 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3696 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3697 callback.
3699 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3700 loop iteration except for the last one.
3702 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3703 loop iteration.
3704 */
3705 void
3708 loop_insn_callback fncall;
3709 {
3710 /* This is 1 if current insn is not executed at least once for every loop
3711 iteration. */
3716 rtx p;
3718 /* If loop_scan_start points to the loop exit test, we have to be wary of
3719 subversive use of gotos inside expression statements. */
3723 /* Scan through loop to find all possible bivs. */
3728 {
3731 /* Past CODE_LABEL, we get to insns that may be executed multiple
3732 times. The only way we can be sure that they can't is if every
3733 jump insn between here and the end of the loop either
3734 returns, exits the loop, is a jump to a location that is still
3735 behind the label, or is a jump to the loop start. */
3738 {
3744 {
3749 {
3752 else
3756 }
3764 {
3767 }
3768 }
3769 }
3771 /* Past a jump, we get to insns for which we can't count
3772 on whether they will be executed during each iteration. */
3773 /* This code appears twice in strength_reduce. There is also similar
3774 code in scan_loop. */
3776 /* If we enter the loop in the middle, and scan around to the
3777 beginning, don't set not_every_iteration for that.
3778 This can be any kind of jump, since we want to know if insns
3779 will be executed if the loop is executed. */
3783 {
3786 /* If this is a jump outside the loop, then it also doesn't
3787 matter. Check to see if the target of this branch is on the
3788 loop->exits_labels list. */
3796 }
3799 {
3800 /* At the virtual top of a converted loop, insns are again known to
3801 be executed each iteration: logically, the loop begins here
3802 even though the exit code has been duplicated.
3804 Insns are also again known to be executed each iteration at
3805 the LOOP_CONT note. */
3811 loop_depth++;
3813 loop_depth--;
3814 }
3816 /* Note if we pass a loop latch. If we do, then we can not clear
3817 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3818 a loop since a jump before the last CODE_LABEL may have started
3819 a new loop iteration.
3821 Note that LOOP_TOP is only set for rotated loops and we need
3822 this check for all loops, so compare against the CODE_LABEL
3823 which immediately follows LOOP_START. */
3828 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3829 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3830 or not an insn is known to be executed each iteration of the
3831 loop, whether or not any iterations are known to occur.
3833 Therefore, if we have just passed a label and have no more labels
3834 between here and the test insn of the loop, and we have not passed
3835 a jump to the top of the loop, then we know these insns will be
3836 executed each iteration. */
3839 && !past_loop_latch
3844 }
3845 }
3846 \f
3847 /* Perform strength reduction and induction variable elimination.
3849 Pseudo registers created during this function will be beyond the last
3850 valid index in several tables including n_times_set and regno_last_uid.
3851 This does not cause a problem here, because the added registers cannot be
3852 givs outside of their loop, and hence will never be reconsidered.
3853 But scan_loop must check regnos to make sure they are in bounds. */
3855 static void
3860 {
3861 rtx p;
3862 /* Temporary list pointers for traversing loop_iv_list. */
3865 /* Ratio of extra register life span we can justify
3866 for saving an instruction. More if loop doesn't call subroutines
3867 since in that case saving an insn makes more difference
3868 and more registers are available. */
3869 /* ??? could set this to last value of threshold in move_movables */
3871 /* Map of pseudo-register replacements. */
3875 rtx test;
3876 rtx end_insert_before;
3891 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3892 must be put before this insn, so that they will appear in the right
3893 order (i.e. loop order).
3895 If loop_end is the end of the current function, then emit a
3896 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3897 dummy note insn. */
3900 else
3905 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3906 Make a sanity check against n_times_set. */
3908 {
3912 /* Above happens if register modified by subreg, etc. */
3913 /* Make sure it is not recognized as a basic induction var: */
3915 /* If never incremented, it is invariant that we decided not to
3916 move. So leave it alone. */
3920 {
3921 /* ??? If we have multiple increments for this BIV, and any of
3922 them take multiple insns to perform the increment, drop the
3923 BIV, since the bit below that converts the extra increments
3924 into GIVs can't handle the multiple insn increment. */
3930 }
3933 {
3944 }
3945 else
3946 {
3951 }
3952 }
3954 /* Exit if there are no bivs. */
3956 {
3957 /* Can still unroll the loop anyways, but indicate that there is no
3958 strength reduction info available. */
3963 }
3965 /* Find initial value for each biv by searching backwards from loop_start,
3966 halting at first label. Also record any test condition. */
3970 {
3979 /* Record any test of a biv that branches around the loop if no store
3980 between it and the start of loop. We only care about tests with
3981 constants and registers and only certain of those. */
3991 {
3992 /* If an NE test, we have an initial value! */
3994 {
3998 }
3999 else
4001 }
4002 }
4004 /* Look at the each biv and see if we can say anything better about its
4005 initial value from any initializing insns set up above. (This is done
4006 in two passes to avoid missing SETs in a PARALLEL.) */
4008 {
4009 rtx src;
4010 rtx note;
4015 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4016 is a constant, use the value of that. */
4022 else
4033 {
4037 {
4039 {
4042 }
4043 else
4044 {
4047 }
4048 }
4049 }
4050 else
4051 {
4055 /* Biv initial value is not a simple move. If it is the sum of
4056 another biv and a constant, check if both bivs are incremented
4057 in lockstep. Then we are actually looking at a giv.
4058 For simplicity, we only handle the case where there is but a
4059 single increment, and the register is not used elsewhere. */
4067 {
4073 }
4075 /* Now, can we transform this biv into a giv? */
4079 /* init_insn is only set to insns that are before loop_start
4080 without any intervening labels. */
4083 /* The register from BL2 must be set before the register from
4084 BL is set, or we must be able to move the latter set after
4085 the former set. Currently there can't be any labels
4086 in-between when biv_total_increment returns nonzero both times
4087 but we test it here in case some day some real cfg analysis
4088 gets used to set always_computable. */
4097 {
4105 /* Let this giv be discovered by the generic code. */
4108 /* We can get better optimization if we can move the giv setting
4109 before the first giv use. */
4113 dominator)
4116 {
4117 rtx p;
4118 rtx next;
4121 {
4127 #ifdef HAVE_cc0
4130 #endif
4132 }
4136 /* Avoid problems with luids by actually moving the insn
4137 and adjusting all luids in the range. */
4142 /* If the only purpose of the init insn is to initialize
4143 this giv, delete it. */
4147 }
4149 {
4156 }
4157 /* Remove this biv from the chain. */
4159 }
4161 /* If we can't make it a giv,
4162 let biv keep initial value of "itself". */
4165 }
4166 }
4168 /* If a biv is unconditionally incremented several times in a row, convert
4169 all but the last increment into a giv. */
4171 /* Get an upper bound for the number of registers
4172 we might have after all bivs have been processed. */
4177 /* If the loop contains volatile memory references do not allow any
4178 replacements to take place, since this could loose the volatile
4179 markers. */
4181 {
4184 /* Reallocate reg_iv_type and reg_iv_info. */
4189 {
4193 /* The biv increments lists are in reverse order. Fix this
4194 first. */
4196 {
4200 }
4202 /* We must guard against the case that an early exit between v->insn
4203 and next->insn leaves the biv live after the loop, since that
4204 would mean that we'd be missing an increment for the final
4205 value. The following test to set biv_dead_after_loop is like
4206 the first part of the test to set bl->eliminable.
4207 We don't check here if we can calculate the final value, since
4208 this can't succeed if we already know that there is a jump
4209 between v->insn and next->insn, yet next->always_executed is
4210 set and next->maybe_multiple is cleared. Such a combination
4211 implies that the jump destination is outside the loop.
4212 If we want to make this check more sophisticated, we should
4213 check each branch between v->insn and next->insn individually
4214 to see if the biv is dead at its destination. */
4221 #ifdef HAVE_decrement_and_branch_until_zero
4223 #endif
4228 {
4229 HOST_WIDE_INT offset;
4241 || ! (biv_dead_after_loop
4243 {
4246 }
4253 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4254 have been allocated with some slop space, so we may not
4255 actually need to reallocate them. If we do, the following
4256 if statement will be executed just once in this loop. */
4258 {
4259 /* Grow all the remaining arrays. */
4264 }
4267 {
4270 }
4272 /* Here we can try to eliminate the increment by combining
4273 it into the uses. */
4275 /* Set last_use_insn so that we can check against it. */
4280 {
4284 {
4286 }
4287 }
4289 /* If we can't get the LUIDs for the insns, we can't
4290 calculate the lifetime. This is likely from unrolling
4291 of an inner loop, so there is little point in making this
4292 a DEST_REG giv anyways. */
4296 {
4297 /* Change the increment at NEXT back to what it was. */
4303 }
4337 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4338 it must be replaced. */
4343 /* Remove the increment from the list of biv increments,
4344 and record it as a giv. */
4353 /* Now replace the biv with DEST_REG in all insns between
4354 the replaced increment and the next increment, and
4355 remember the last insn that needed a replacement. */
4359 {
4360 rtx note;
4365 {
4369 }
4371 {
4375 }
4376 }
4380 /* If the lifetime is zero, it means that this register is really
4381 a dead store. So mark this as a giv that can be ignored.
4382 This will not prevent the biv from being eliminated. */
4390 }
4391 }
4392 }
4395 /* Search the loop for general induction variables. */
4399 /* Try to calculate and save the number of loop iterations. This is
4400 set to zero if the actual number can not be calculated. This must
4401 be called after all giv's have been identified, since otherwise it may
4402 fail if the iteration variable is a giv. */
4406 /* Now for each giv for which we still don't know whether or not it is
4407 replaceable, check to see if it is replaceable because its final value
4408 can be calculated. This must be done after loop_iterations is called,
4409 so that final_giv_value will work correctly. */
4412 {
4418 }
4420 /* Try to prove that the loop counter variable (if any) is always
4421 nonnegative; if so, record that fact with a REG_NONNEG note
4422 so that "decrement and branch until zero" insn can be used. */
4425 /* Create reg_map to hold substitutions for replaceable giv regs.
4426 Some givs might have been made from biv increments, so look at
4427 reg_iv_type for a suitable size. */
4431 /* Examine each iv class for feasibility of strength reduction/induction
4432 variable elimination. */
4435 {
4442 /* Test whether it will be possible to eliminate this biv
4443 provided all givs are reduced. This is possible if either
4444 the reg is not used outside the loop, or we can compute
4445 what its final value will be.
4447 For architectures with a decrement_and_branch_until_zero insn,
4448 don't do this if we put a REG_NONNEG note on the endtest for
4449 this biv. */
4451 /* Compare against bl->init_insn rather than loop_start.
4452 We aren't concerned with any uses of the biv between
4453 init_insn and loop_start since these won't be affected
4454 by the value of the biv elsewhere in the function, so
4455 long as init_insn doesn't use the biv itself.
4456 March 14, 1989 -- self@bayes.arc.nasa.gov */
4462 #ifdef HAVE_decrement_and_branch_until_zero
4464 #endif
4467 #ifdef HAVE_decrement_and_branch_until_zero
4469 #endif
4470 ))
4472 insn_count);
4473 else
4474 {
4476 {
4484 }
4485 }
4487 /* Combine all giv's for this iv_class. */
4490 /* This will be true at the end, if all givs which depend on this
4491 biv have been strength reduced.
4492 We can't (currently) eliminate the biv unless this is so. */
4495 /* Check each giv in this class to see if we will benefit by reducing
4496 it. Skip giv's combined with others. */
4498 {
4506 /* Reduce benefit if not replaceable, since we will insert
4507 a move-insn to replace the insn that calculates this giv.
4508 Don't do this unless the giv is a user variable, since it
4509 will often be marked non-replaceable because of the duplication
4510 of the exit code outside the loop. In such a case, the copies
4511 we insert are dead and will be deleted. So they don't have
4512 a cost. Similar situations exist. */
4513 /* ??? The new final_[bg]iv_value code does a much better job
4514 of finding replaceable giv's, and hence this code may no longer
4515 be necessary. */
4520 /* Decrease the benefit to count the add-insns that we will
4521 insert to increment the reduced reg for the giv. */
4524 /* Decide whether to strength-reduce this giv or to leave the code
4525 unchanged (recompute it from the biv each time it is used).
4526 This decision can be made independently for each giv. */
4528 #ifdef AUTO_INC_DEC
4529 /* Attempt to guess whether autoincrement will handle some of the
4530 new add insns; if so, increase BENEFIT (undo the subtraction of
4531 add_cost that was done above). */
4534 {
4547 }
4548 #endif
4550 /* If an insn is not to be strength reduced, then set its ignore
4551 flag, and clear all_reduced. */
4553 /* A giv that depends on a reversed biv must be reduced if it is
4554 used after the loop exit, otherwise, it would have the wrong
4555 value after the loop exit. To make it simple, just reduce all
4556 of such giv's whether or not we know they are used after the loop
4557 exit. */
4561 {
4569 }
4570 else
4571 {
4572 /* Check that we can increment the reduced giv without a
4573 multiply insn. If not, reject it. */
4578 {
4586 }
4587 }
4588 }
4590 /* Check for givs whose first use is their definition and whose
4591 last use is the definition of another giv. If so, it is likely
4592 dead and should not be used to derive another giv nor to
4593 eliminate a biv. */
4595 {
4601 {
4607 }
4610 {
4616 }
4617 }
4619 /* Now that we know which givs will be reduced, try to rearrange the
4620 combinations to reduce register pressure.
4621 recombine_givs calls find_life_end, which needs reg_iv_type and
4622 reg_iv_info to be valid for all pseudos. We do the necessary
4623 reallocation here since it allows to check if there are still
4624 more bivs to process. */
4627 {
4628 /* If there are still more bivs to process, allocate some slack
4629 space so that we're not constantly reallocating these arrays. */
4632 /* Reallocate reg_iv_type and reg_iv_info. */
4635 }
4638 /* Reduce each giv that we decided to reduce. */
4641 {
4644 {
4647 /* If the code for derived givs immediately below has already
4648 allocated a new_reg, we must keep it. */
4653 {
4656 /* In case d->dest_reg is not replaceable, we have
4657 to replace it in v->insn now. */
4664 /* For each place where the biv is incremented, add an
4665 insn to set the new, reduced reg for the giv.
4666 We used to do this only for biv_count != 1, but
4667 this fails when there is a giv after a single biv
4668 increment, e.g. when the last giv was expressed as
4669 pre-decrement. */
4671 {
4672 /* We always emit reduced giv increments before the
4673 biv increment when bl->biv_count != 1. So by
4674 emitting the add insns for derived givs after the
4675 biv increment, they pick up the updated value of
4676 the reduced giv.
4677 If the reduced giv is processed with
4678 auto_inc_opt == 1, then it is incremented earlier
4679 than the biv, hence we'll still pick up the right
4680 value.
4681 If it's processed with auto_inc_opt == -1,
4682 that implies that the biv increment is before the
4683 first reduced giv's use. The derived giv's lifetime
4684 is after the reduced giv's lifetime, hence in this
4685 case, the biv increment doesn't matter. */
4687 }
4689 }
4691 #ifdef AUTO_INC_DEC
4692 /* If the target has auto-increment addressing modes, and
4693 this is an address giv, then try to put the increment
4694 immediately after its use, so that flow can create an
4695 auto-increment addressing mode. */
4698 /* We don't handle reversed biv's because bl->biv->insn
4699 does not have a valid INSN_LUID. */
4703 {
4704 /* If other giv's have been combined with this one, then
4705 this will work only if all uses of the other giv's occur
4706 before this giv's insn. This is difficult to check.
4708 We simplify this by looking for the common case where
4709 there is one DEST_REG giv, and this giv's insn is the
4710 last use of the dest_reg of that DEST_REG giv. If the
4711 increment occurs after the address giv, then we can
4712 perform the optimization. (Otherwise, the increment
4713 would have to go before other_giv, and we would not be
4714 able to combine it with the address giv to get an
4715 auto-inc address.) */
4717 {
4722 {
4725 else
4727 }
4734 }
4735 /* Check for case where increment is before the address
4736 giv. Do this test in "loop order". */
4745 else
4748 #ifdef HAVE_cc0
4749 {
4750 rtx prev;
4752 /* We can't put an insn immediately after one setting
4753 cc0, or immediately before one using cc0. */
4760 }
4761 #endif
4765 }
4766 #endif
4768 /* For each place where the biv is incremented, add an insn
4769 to increment the new, reduced reg for the giv. */
4771 {
4772 rtx insert_before;
4778 else
4785 /* A multiply is acceptable here
4786 since this is presumed to be seldom executed. */
4789 }
4791 /* Add code at loop start to initialize giv's reduced reg. */
4795 }
4796 }
4798 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4799 as not reduced.
4801 For each giv register that can be reduced now: if replaceable,
4802 substitute reduced reg wherever the old giv occurs;
4803 else add new move insn "giv_reg = reduced_reg". */
4806 {
4813 /* Update expression if this was combined, in case other giv was
4814 replaced. */
4820 /* Store reduced reg as the address in the memref where we found
4821 this giv. */
4824 {
4827 #if 0
4828 /* I can no longer duplicate the original problem. Perhaps
4829 this is unnecessary now? */
4831 /* Replaceable; it isn't strictly necessary to delete the old
4832 insn and emit a new one, because v->dest_reg is now dead.
4834 However, especially when unrolling loops, the special
4835 handling for (set REG0 REG1) in the second cse pass may
4836 make v->dest_reg live again. To avoid this problem, emit
4837 an insn to set the original giv reg from the reduced giv.
4838 We can not delete the original insn, since it may be part
4839 of a LIBCALL, and the code in flow that eliminates dead
4840 libcalls will fail if it is deleted. */
4843 #endif
4844 }
4845 else
4846 {
4847 /* Not replaceable; emit an insn to set the original giv reg from
4848 the reduced giv, same as above. */
4851 }
4853 /* When a loop is reversed, givs which depend on the reversed
4854 biv, and which are live outside the loop, must be set to their
4855 correct final value. This insn is only needed if the giv is
4856 not replaceable. The correct final value is the same as the
4857 value that the giv starts the reversed loop with. */
4862 {
4863 rtx insert_before;
4865 /* If the loop has multiple exits, emit the insn before the
4866 loop to ensure that it will always be executed no matter
4867 how the loop exits. Otherwise, emit the insn after the loop,
4868 since this is slightly more efficient. */
4871 else
4874 insert_before);
4876 #if 0
4877 /* If the insn to set the final value of the giv was emitted
4878 before the loop, then we must delete the insn inside the loop
4879 that sets it. If this is a LIBCALL, then we must delete
4880 every insn in the libcall. Note, however, that
4881 final_giv_value will only succeed when there are multiple
4882 exits if the giv is dead at each exit, hence it does not
4883 matter that the original insn remains because it is dead
4884 anyways. */
4885 /* Delete the insn inside the loop that sets the giv since
4886 the giv is now set before (or after) the loop. */
4888 #endif
4889 }
4892 {
4897 }
4898 }
4900 /* All the givs based on the biv bl have been reduced if they
4901 merit it. */
4903 /* For each giv not marked as maybe dead that has been combined with a
4904 second giv, clear any "maybe dead" mark on that second giv.
4905 v->new_reg will either be or refer to the register of the giv it
4906 combined with.
4908 Doing this clearing avoids problems in biv elimination where a
4909 giv's new_reg is a complex value that can't be put in the insn but
4910 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4911 Since the register will be used in either case, we'd prefer it be
4912 used from the simpler giv. */
4918 /* Try to eliminate the biv, if it is a candidate.
4919 This won't work if ! all_reduced,
4920 since the givs we planned to use might not have been reduced.
4922 We have to be careful that we didn't initially think we could eliminate
4923 this biv because of a giv that we now think may be dead and shouldn't
4924 be used as a biv replacement.
4926 Also, there is the possibility that we may have a giv that looks
4927 like it can be used to eliminate a biv, but the resulting insn
4928 isn't valid. This can happen, for example, on the 88k, where a
4929 JUMP_INSN can compare a register only with zero. Attempts to
4930 replace it with a compare with a constant will fail.
4932 Note that in cases where this call fails, we may have replaced some
4933 of the occurrences of the biv with a giv, but no harm was done in
4934 doing so in the rare cases where it can occur. */
4938 {
4939 /* ?? If we created a new test to bypass the loop entirely,
4940 or otherwise drop straight in, based on this test, then
4941 we might want to rewrite it also. This way some later
4942 pass has more hope of removing the initialization of this
4943 biv entirely. */
4945 /* If final_value != 0, then the biv may be used after loop end
4946 and we must emit an insn to set it just in case.
4948 Reversed bivs already have an insn after the loop setting their
4949 value, so we don't need another one. We can't calculate the
4950 proper final value for such a biv here anyways. */
4952 {
4953 rtx insert_before;
4955 /* If the loop has multiple exits, emit the insn before the
4956 loop to ensure that it will always be executed no matter
4957 how the loop exits. Otherwise, emit the insn after the
4958 loop, since this is slightly more efficient. */
4961 else
4965 end_insert_before);
4966 }
4968 #if 0
4969 /* Delete all of the instructions inside the loop which set
4970 the biv, as they are all dead. If is safe to delete them,
4971 because an insn setting a biv will never be part of a libcall. */
4972 /* However, deleting them will invalidate the regno_last_uid info,
4973 so keeping them around is more convenient. Final_biv_value
4974 will only succeed when there are multiple exits if the biv
4975 is dead at each exit, hence it does not matter that the original
4976 insn remains, because it is dead anyways. */
4979 #endif
4984 }
4985 }
4987 /* Go through all the instructions in the loop, making all the
4988 register substitutions scheduled in REG_MAP. */
4993 {
4997 }
5000 {
5001 /* When we completely unroll a loop we will likely not need the increment
5002 of the loop BIV and we will not need the conditional branch at the
5003 end of the loop. */
5006 #ifdef HAVE_cc0
5007 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5008 need the comparison before the conditional branch at the end of the
5009 loop. */
5011 #endif
5013 /* We'll need one copy for each loop iteration. */
5016 /* A little slop to account for the ability to remove initialization
5017 code, better CSE, and other secondary benefits of completely
5018 unrolling some loops. */
5021 /* Clamp the value. */
5024 }
5026 /* Unroll loops from within strength reduction so that we can use the
5027 induction variable information that strength_reduce has already
5028 collected. Always unroll loops that would be as small or smaller
5029 unrolled than when rolled. */
5035 #ifdef HAVE_decrement_and_branch_on_count
5036 /* Instrument the loop with BCT insn. */
5045 egress:
5051 }
5052 \f
5053 /*Record all basic induction variables calculated in the insn. */
5054 static rtx
5057 rtx p;
5060 {
5061 rtx set;
5062 rtx dest_reg;
5063 rtx inc_val;
5064 rtx mult_val;
5070 {
5075 {
5082 {
5083 /* It is a possible basic induction variable.
5084 Create and initialize an induction structure for it. */
5091 multi_insn_incr);
5093 }
5096 }
5097 }
5099 }
5100 \f
5101 /* Record all givs calculated in the insn.
5102 A register is a giv if: it is only set once, it is a function of a
5103 biv and a constant (or invariant), and it is not a biv. */
5104 static rtx
5107 rtx p;
5110 {
5111 rtx set;
5112 /* Look for a general induction variable in a register. */
5117 {
5118 rtx src_reg;
5119 rtx dest_reg;
5120 rtx add_val;
5121 rtx mult_val;
5124 rtx last_consec_insn;
5133 /* Equivalent expression is a giv. */
5138 /* Don't try to handle any regs made by loop optimization.
5139 We have nothing on them in regno_first_uid, etc. */
5141 /* Don't recognize a BASIC_INDUCT_VAR here. */
5143 /* This must be the only place where the register is set. */
5145 /* or all sets must be consecutive and make a giv. */
5150 {
5154 /* If this is a library call, increase benefit. */
5158 /* Skip the consecutive insns, if there are any. */
5166 }
5167 }
5169 #ifndef DONT_REDUCE_ADDR
5170 /* Look for givs which are memory addresses. */
5171 /* This resulted in worse code on a VAX 8600. I wonder if it
5172 still does. */
5175 maybe_multiple);
5176 #endif
5178 /* Update the status of whether giv can derive other givs. This can
5179 change when we pass a label or an insn that updates a biv. */
5184 }
5185 \f
5186 /* Return 1 if X is a valid source for an initial value (or as value being
5187 compared against in an initial test).
5189 X must be either a register or constant and must not be clobbered between
5190 the current insn and the start of the loop.
5192 INSN is the insn containing X. */
5194 static int
5196 rtx x;
5197 rtx insn;
5199 rtx loop_start;
5200 {
5204 /* Only consider pseudos we know about initialized in insns whose luids
5205 we know. */
5210 /* Don't use call-clobbered registers across a call which clobbers it. On
5211 some machines, don't use any hard registers at all. */
5213 && (SMALL_REGISTER_CLASSES
5217 /* Don't use registers that have been clobbered before the start of the
5218 loop. */
5223 }
5224 \f
5225 /* Scan X for memory refs and check each memory address
5226 as a possible giv. INSN is the insn whose pattern X comes from.
5227 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5228 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5229 more thanonce in each loop iteration. */
5231 static void
5234 rtx x;
5235 rtx insn;
5237 {
5247 {
5263 {
5264 rtx src_reg;
5265 rtx add_val;
5266 rtx mult_val;
5269 /* This code used to disable creating GIVs with mult_val == 1 and
5270 add_val == 0. However, this leads to lost optimizations when
5271 it comes time to combine a set of related DEST_ADDR GIVs, since
5272 this one would not be seen. */
5276 {
5277 /* Found one; record it. */
5286 }
5287 }
5292 }
5294 /* Recursively scan the subexpressions for other mem refs. */
5300 maybe_multiple);
5304 maybe_multiple);
5305 }
5306 \f
5307 /* Fill in the data about one biv update.
5308 V is the `struct induction' in which we record the biv. (It is
5309 allocated by the caller, with alloca.)
5310 INSN is the insn that sets it.
5311 DEST_REG is the biv's reg.
5313 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5314 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5315 being set to INC_VAL.
5317 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5318 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5319 can be executed more than once per iteration. If MAYBE_MULTIPLE
5320 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5321 executed exactly once per iteration. */
5323 static void
5327 rtx insn;
5328 rtx dest_reg;
5329 rtx inc_val;
5330 rtx mult_val;
5335 {
5350 /* Add this to the reg's iv_class, creating a class
5351 if this is the first incrementation of the reg. */
5355 {
5356 /* Create and initialize new iv_class. */
5366 /* Set initial value to the reg itself. */
5368 /* We haven't seen the initializing insn yet */
5378 /* Add this class to loop_iv_list. */
5382 /* Put it in the array of biv register classes. */
5384 }
5386 /* Update IV_CLASS entry for this biv. */
5394 {
5399 {
5403 }
5404 else
5405 {
5409 }
5410 }
5411 }
5412 \f
5413 /* Fill in the data about one giv.
5414 V is the `struct induction' in which we record the giv. (It is
5415 allocated by the caller, with alloca.)
5416 INSN is the insn that sets it.
5417 BENEFIT estimates the savings from deleting this insn.
5418 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5419 into a register or is used as a memory address.
5421 SRC_REG is the biv reg which the giv is computed from.
5422 DEST_REG is the giv's reg (if the giv is stored in a reg).
5423 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5424 LOCATION points to the place where this giv's value appears in INSN. */
5426 static void
5431 rtx insn;
5432 rtx src_reg;
5433 rtx dest_reg;
5439 {
5443 rtx temp;
5445 /* Attempt to prove constantness of the values. */
5475 /* The v->always_computable field is used in update_giv_derive, to
5476 determine whether a giv can be used to derive another giv. For a
5477 DEST_REG giv, INSN computes a new value for the giv, so its value
5478 isn't computable if INSN insn't executed every iteration.
5479 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5480 it does not compute a new value. Hence the value is always computable
5481 regardless of whether INSN is executed each iteration. */
5485 else
5491 {
5494 }
5496 {
5502 /* If the lifetime is zero, it means that this register is
5503 really a dead store. So mark this as a giv that can be
5504 ignored. This will not prevent the biv from being eliminated. */
5510 }
5512 /* Add the giv to the class of givs computed from one biv. */
5516 {
5519 /* Don't count DEST_ADDR. This is supposed to count the number of
5520 insns that calculate givs. */
5524 }
5525 else
5526 /* Fatal error, biv missing for this giv? */
5531 else
5532 {
5533 /* The giv can be replaced outright by the reduced register only if all
5534 of the following conditions are true:
5535 - the insn that sets the giv is always executed on any iteration
5536 on which the giv is used at all
5537 (there are two ways to deduce this:
5538 either the insn is executed on every iteration,
5539 or all uses follow that insn in the same basic block),
5540 - the giv is not used outside the loop
5541 - no assignments to the biv occur during the giv's lifetime. */
5544 /* Previous line always fails if INSN was moved by loop opt. */
5547 && (! not_every_iteration
5549 {
5550 /* Now check that there are no assignments to the biv within the
5551 giv's lifetime. This requires two separate checks. */
5553 /* Check each biv update, and fail if any are between the first
5554 and last use of the giv.
5556 If this loop contains an inner loop that was unrolled, then
5557 the insn modifying the biv may have been emitted by the loop
5558 unrolling code, and hence does not have a valid luid. Just
5559 mark the biv as not replaceable in this case. It is not very
5560 useful as a biv, because it is used in two different loops.
5561 It is very unlikely that we would be able to optimize the giv
5562 using this biv anyways. */
5566 {
5572 {
5576 }
5577 }
5579 /* If there are any backwards branches that go from after the
5580 biv update to before it, then this giv is not replaceable. */
5584 {
5588 }
5589 }
5590 else
5591 {
5592 /* May still be replaceable, we don't have enough info here to
5593 decide. */
5596 }
5597 }
5599 /* Record whether the add_val contains a const_int, for later use by
5600 combine_givs. */
5601 {
5606 ;
5610 {
5612 {
5617 else
5619 }
5622 }
5623 }
5626 {
5630 else
5646 {
5649 }
5650 else
5651 {
5654 }
5657 {
5660 }
5661 else
5662 {
5665 }
5666 }
5671 }
5674 /* All this does is determine whether a giv can be made replaceable because
5675 its final value can be calculated. This code can not be part of record_giv
5676 above, because final_giv_value requires that the number of loop iterations
5677 be known, and that can not be accurately calculated until after all givs
5678 have been identified. */
5680 static void
5684 {
5690 /* DEST_ADDR givs will never reach here, because they are always marked
5691 replaceable above in record_giv. */
5693 /* The giv can be replaced outright by the reduced register only if all
5694 of the following conditions are true:
5695 - the insn that sets the giv is always executed on any iteration
5696 on which the giv is used at all
5697 (there are two ways to deduce this:
5698 either the insn is executed on every iteration,
5699 or all uses follow that insn in the same basic block),
5700 - its final value can be calculated (this condition is different
5701 than the one above in record_giv)
5702 - no assignments to the biv occur during the giv's lifetime. */
5704 #if 0
5705 /* This is only called now when replaceable is known to be false. */
5706 /* Clear replaceable, so that it won't confuse final_giv_value. */
5708 #endif
5712 {
5715 rtx last_giv_use;
5719 /* When trying to determine whether or not a biv increment occurs
5720 during the lifetime of the giv, we can ignore uses of the variable
5721 outside the loop because final_value is true. Hence we can not
5722 use regno_last_uid and regno_first_uid as above in record_giv. */
5724 /* Search the loop to determine whether any assignments to the
5725 biv occur during the giv's lifetime. Start with the insn
5726 that sets the giv, and search around the loop until we come
5727 back to that insn again.
5729 Also fail if there is a jump within the giv's lifetime that jumps
5730 to somewhere outside the lifetime but still within the loop. This
5731 catches spaghetti code where the execution order is not linear, and
5732 hence the above test fails. Here we assume that the giv lifetime
5733 does not extend from one iteration of the loop to the next, so as
5734 to make the test easier. Since the lifetime isn't known yet,
5735 this requires two loops. See also record_giv above. */
5740 {
5749 {
5751 {
5753 {
5757 }
5758 }
5763 }
5764 }
5766 /* Now that the lifetime of the giv is known, check for branches
5767 from within the lifetime to outside the lifetime if it is still
5768 replaceable. */
5771 {
5774 {
5787 {
5796 }
5797 }
5798 }
5800 /* If it is replaceable, then save the final value. */
5803 }
5808 }
5809 \f
5810 /* Update the status of whether a giv can derive other givs.
5812 We need to do something special if there is or may be an update to the biv
5813 between the time the giv is defined and the time it is used to derive
5814 another giv.
5816 In addition, a giv that is only conditionally set is not allowed to
5817 derive another giv once a label has been passed.
5819 The cases we look at are when a label or an update to a biv is passed. */
5821 static void
5824 rtx p;
5825 {
5828 rtx tem;
5831 /* Search all IV classes, then all bivs, and finally all givs.
5833 There are three cases we are concerned with. First we have the situation
5834 of a giv that is only updated conditionally. In that case, it may not
5835 derive any givs after a label is passed.
5837 The second case is when a biv update occurs, or may occur, after the
5838 definition of a giv. For certain biv updates (see below) that are
5839 known to occur between the giv definition and use, we can adjust the
5840 giv definition. For others, or when the biv update is conditional,
5841 we must prevent the giv from deriving any other givs. There are two
5842 sub-cases within this case.
5844 If this is a label, we are concerned with any biv update that is done
5845 conditionally, since it may be done after the giv is defined followed by
5846 a branch here (actually, we need to pass both a jump and a label, but
5847 this extra tracking doesn't seem worth it).
5849 If this is a jump, we are concerned about any biv update that may be
5850 executed multiple times. We are actually only concerned about
5851 backward jumps, but it is probably not worth performing the test
5852 on the jump again here.
5854 If this is a biv update, we must adjust the giv status to show that a
5855 subsequent biv update was performed. If this adjustment cannot be done,
5856 the giv cannot derive further givs. */
5862 {
5864 {
5865 /* If cant_derive is already true, there is no point in
5866 checking all of these conditions again. */
5870 /* If this giv is conditionally set and we have passed a label,
5871 it cannot derive anything. */
5875 /* Skip givs that have mult_val == 0, since
5876 they are really invariants. Also skip those that are
5877 replaceable, since we know their lifetime doesn't contain
5878 any biv update. */
5882 /* The only way we can allow this giv to derive another
5883 is if this is a biv increment and we can form the product
5884 of biv->add_val and giv->mult_val. In this case, we will
5885 be able to compute a compensation. */
5887 {
5898 tem = simplify_giv_expr
5905 else
5907 }
5911 }
5912 }
5913 }
5914 \f
5915 /* Check whether an insn is an increment legitimate for a basic induction var.
5916 X is the source of insn P, or a part of it.
5917 MODE is the mode in which X should be interpreted.
5919 DEST_REG is the putative biv, also the destination of the insn.
5920 We accept patterns of these forms:
5921 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5922 REG = INVARIANT + REG
5924 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5925 store the additive term into *INC_VAL, and store the place where
5926 we found the additive term into *LOCATION.
5928 If X is an assignment of an invariant into DEST_REG, we set
5929 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5931 We also want to detect a BIV when it corresponds to a variable
5932 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5933 of the variable may be a PLUS that adds a SUBREG of that variable to
5934 an invariant and then sign- or zero-extends the result of the PLUS
5935 into the variable.
5937 Most GIVs in such cases will be in the promoted mode, since that is the
5938 probably the natural computation mode (and almost certainly the mode
5939 used for addresses) on the machine. So we view the pseudo-reg containing
5940 the variable as the BIV, as if it were simply incremented.
5942 Note that treating the entire pseudo as a BIV will result in making
5943 simple increments to any GIVs based on it. However, if the variable
5944 overflows in its declared mode but not its promoted mode, the result will
5945 be incorrect. This is acceptable if the variable is signed, since
5946 overflows in such cases are undefined, but not if it is unsigned, since
5947 those overflows are defined. So we only check for SIGN_EXTEND and
5948 not ZERO_EXTEND.
5950 If we cannot find a biv, we return 0. */
5952 static int
5958 rtx dest_reg;
5959 rtx p;
5964 {
5972 {
5978 {
5980 }
5985 {
5987 }
5988 else
6001 /* If this is a SUBREG for a promoted variable, check the inner
6002 value. */
6007 multi_insn_incr);
6011 /* If this register is assigned in a previous insn, look at its
6012 source, but don't go outside the loop or past a label. */
6016 {
6041 multi_insn_incr))
6042 {
6045 }
6046 }
6047 /* ... fall through ... */
6049 /* Can accept constant setting of biv only when inside inner most loop.
6050 Otherwise, a biv of an inner loop may be incorrectly recognized
6051 as a biv of the outer loop,
6052 causing code to be moved INTO the inner loop. */
6059 /* convert_modes aborts if we try to convert to or from CCmode, so just
6060 exclude that case. It is very unlikely that a condition code value
6061 would be a useful iterator anyways. */
6065 {
6066 /* Possible bug here? Perhaps we don't know the mode of X. */
6070 }
6071 else
6077 multi_insn_incr);
6080 /* Similar, since this can be a sign extension. */
6085 ;
6099 {
6102 }
6107 }
6108 }
6109 \f
6110 /* A general induction variable (giv) is any quantity that is a linear
6111 function of a basic induction variable,
6112 i.e. giv = biv * mult_val + add_val.
6113 The coefficients can be any loop invariant quantity.
6114 A giv need not be computed directly from the biv;
6115 it can be computed by way of other givs. */
6117 /* Determine whether X computes a giv.
6118 If it does, return a nonzero value
6119 which is the benefit from eliminating the computation of X;
6120 set *SRC_REG to the register of the biv that it is computed from;
6121 set *ADD_VAL and *MULT_VAL to the coefficients,
6122 such that the value of X is biv * mult + add; */
6124 static int
6128 rtx x;
6135 {
6139 /* If this is an invariant, forget it, it isn't a giv. */
6143 /* See if the expression could be a giv and get its form.
6144 Mark our place on the obstack in case we don't find a giv. */
6149 {
6152 }
6155 {
6158 /* Since this is now an invariant and wasn't before, it must be a giv
6159 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6160 with. */
6167 /* This is equivalent to a BIV. */
6174 /* Either (plus (biv) (invar)) or
6175 (plus (mult (biv) (invar_1)) (invar_2)). */
6177 {
6180 }
6181 else
6182 {
6185 }
6190 /* ADD_VAL is zero. */
6198 }
6200 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6201 unless they are CONST_INT). */
6209 else
6212 /* Always return true if this is a giv so it will be detected as such,
6213 even if the benefit is zero or negative. This allows elimination
6214 of bivs that might otherwise not be eliminated. */
6216 }
6217 \f
6218 /* Given an expression, X, try to form it as a linear function of a biv.
6219 We will canonicalize it to be of the form
6220 (plus (mult (BIV) (invar_1))
6221 (invar_2))
6222 with possible degeneracies.
6224 The invariant expressions must each be of a form that can be used as a
6225 machine operand. We surround then with a USE rtx (a hack, but localized
6226 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6227 routine; it is the caller's responsibility to strip them.
6229 If no such canonicalization is possible (i.e., two biv's are used or an
6230 expression that is neither invariant nor a biv or giv), this routine
6231 returns 0.
6233 For a non-zero return, the result will have a code of CONST_INT, USE,
6234 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6236 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6243 static rtx
6246 rtx x;
6248 {
6251 rtx tem;
6253 /* If this is not an integer mode, or if we cannot do arithmetic in this
6254 mode, this can't be a giv. */
6261 {
6268 /* Put constant last, CONST_INT last if both constant. */
6276 /* Handle addition of zero, then addition of an invariant. */
6281 {
6284 /* Adding two invariants must result in an invariant, so enclose
6285 addition operation inside a USE and return it. */
6295 else
6304 /* biv + invar or mult + invar. Return sum. */
6308 /* (a + invar_1) + invar_2. Associate. */
6309 return
6315 arg1)),
6316 benefit);
6320 }
6322 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6323 MULT to reduce cases. */
6329 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6330 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6331 Recurse to associate the second PLUS. */
6336 return
6342 benefit);
6344 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6357 benefit);
6360 /* Handle "a - b" as "a + b * (-1)". */
6366 constm1_rtx)),
6367 benefit);
6375 /* Put constant last, CONST_INT last if both constant. */
6380 /* If second argument is not now constant, not giv. */
6384 /* Handle multiply by 0 or 1. */
6392 {
6394 /* biv * invar. Done. */
6398 /* Product of two constants. */
6402 /* invar * invar is a giv, but attempt to simplify it somehow. */
6408 {
6409 /* (invar_0 * invar_1) * invar_2. Associate. */
6416 arg1)),
6417 benefit);
6418 }
6419 /* Porpagate the MULT expressions to the intermost nodes. */
6421 {
6422 /* (invar_0 + invar_1) * invar_2. Distribute. */
6428 arg1),
6432 arg1)),
6433 benefit);
6434 }
6438 /* (a * invar_1) * invar_2. Associate. */
6444 arg1)),
6445 benefit);
6448 /* (a + invar_1) * invar_2. Distribute. */
6453 arg1),
6456 arg1)),
6457 benefit);
6461 }
6464 /* Shift by constant is multiply by power of two. */
6468 return
6474 benefit);
6477 /* "-a" is "a * (-1)" */
6480 benefit);
6483 /* "~a" is "-a - 1". Silly, but easy. */
6487 const1_rtx),
6488 benefit);
6491 /* Already in proper form for invariant. */
6495 /* If this is a new register, we can't deal with it. */
6499 /* Check for biv or giv. */
6501 {
6505 {
6508 /* Form expression from giv and add benefit. Ensure this giv
6509 can derive another and subtract any needed adjustment if so. */
6521 }
6524 /* If it isn't an induction variable, and it is invariant, we
6525 may be able to simplify things further by looking through
6526 the bits we just moved outside the loop. */
6528 {
6533 {
6534 /* Ok, we found a match. Substitute and simplify. */
6536 /* If we match another movable, we must use that, as
6537 this one is going away. */
6540 benefit);
6542 /* If consec is non-zero, this is a member of a group of
6543 instructions that were moved together. We handle this
6544 case only to the point of seeking to the last insn and
6545 looking for a REG_EQUAL. Fail if we don't find one. */
6547 {
6555 }
6556 else
6557 {
6561 }
6564 {
6565 /* What we are most interested in is pointer
6566 arithmetic on invariants -- only take
6567 patterns we may be able to do something with. */
6573 {
6577 }
6582 {
6584 benefit);
6587 }
6588 }
6590 }
6591 }
6593 }
6595 /* Fall through to general case. */
6597 /* If invariant, return as USE (unless CONST_INT).
6598 Otherwise, not giv. */
6603 {
6612 }
6613 else
6615 }
6616 }
6618 /* This routine folds invariants such that there is only ever one
6619 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6621 static rtx
6624 {
6630 {
6633 }
6636 {
6639 }
6640 else
6641 {
6644 }
6645 }
6647 static rtx
6651 {
6653 {
6657 else
6660 }
6663 else
6666 }
6667 \f
6668 /* Help detect a giv that is calculated by several consecutive insns;
6669 for example,
6670 giv = biv * M
6671 giv = giv + A
6672 The caller has already identified the first insn P as having a giv as dest;
6673 we check that all other insns that set the same register follow
6674 immediately after P, that they alter nothing else,
6675 and that the result of the last is still a giv.
6677 The value is 0 if the reg set in P is not really a giv.
6678 Otherwise, the value is the amount gained by eliminating
6679 all the consecutive insns that compute the value.
6681 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6682 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6684 The coefficients of the ultimate giv value are stored in
6685 *MULT_VAL and *ADD_VAL. */
6687 static int
6692 rtx p;
6693 rtx src_reg;
6694 rtx dest_reg;
6698 {
6702 rtx temp;
6703 rtx set;
6705 /* Indicate that this is a giv so that we can update the value produced in
6706 each insn of the multi-insn sequence.
6708 This induction structure will be used only by the call to
6709 general_induction_var below, so we can allocate it on our stack.
6710 If this is a giv, our caller will replace the induct var entry with
6711 a new induction structure. */
6727 {
6731 /* If libcall, skip to end of call sequence. */
6741 /* Giv created by equivalent expression. */
6745 VOIDmode)))
6747 {
6751 count--;
6755 }
6757 {
6758 /* Allow insns that set something other than this giv to a
6759 constant. Such insns are needed on machines which cannot
6760 include long constants and should not disqualify a giv. */
6769 }
6770 }
6774 }
6775 \f
6776 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6777 represented by G1. If no such expression can be found, or it is clear that
6778 it cannot possibly be a valid address, 0 is returned.
6780 To perform the computation, we note that
6781 G1 = x * v + a and
6782 G2 = y * v + b
6783 where `v' is the biv.
6785 So G2 = (y/b) * G1 + (b - a*y/x).
6787 Note that MULT = y/x.
6789 Update: A and B are now allowed to be additive expressions such that
6790 B contains all variables in A. That is, computing B-A will not require
6791 subtracting variables. */
6793 static rtx
6796 {
6797 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6802 /* If MULT is not 1, we cannot handle A with non-constants, since we
6803 would then be required to subtract multiples of the registers in A.
6804 This is theoretically possible, and may even apply to some Fortran
6805 constructs, but it is a lot of work and we do not attempt it here. */
6810 /* In general these structures are sorted top to bottom (down the PLUS
6811 chain), but not left to right across the PLUS. If B is a higher
6812 order giv than A, we can strip one level and recurse. If A is higher
6813 order, we'll eventually bail out, but won't know that until the end.
6814 If they are the same, we'll strip one level around this loop. */
6817 {
6829 /* We matched: remove one reg completely. */
6832 /* An alternate match. */
6835 /* An alternate match. */
6837 else
6838 {
6839 /* Indicates an extra register in B. Strip one level from B and
6840 recurse, hoping B was the higher order expression. */
6845 }
6846 }
6848 /* Here we are at the last level of A, go through the cases hoping to
6849 get rid of everything but a constant. */
6852 {
6865 }
6867 {
6869 }
6871 {
6873 }
6875 {
6880 else
6882 }
6887 }
6889 rtx
6892 {
6895 /* The value that G1 will be multiplied by must be a constant integer. Also,
6896 the only chance we have of getting a valid address is if b*c/a (see above
6897 for notation) is also an integer. */
6900 {
6905 }
6908 else
6909 {
6910 /* ??? Find out if the one is a multiple of the other? */
6912 }
6916 {
6917 /* Failed. If we've got a multiplication factor between G1 and G2,
6918 scale G1's addend and try again. */
6920 {
6924 {
6925 HOST_WIDE_INT m;
6929 }
6930 else
6931 {
6933 mult);
6934 }
6937 }
6938 }
6942 /* Form simplified final result. */
6947 else
6952 else
6953 {
6956 {
6960 }
6963 }
6965 }
6966 \f
6967 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6968 represented by G1. This indicates that G2 should be combined with G1 and
6969 that G2 can use (either directly or via an address expression) a register
6970 used to represent G1. */
6972 static rtx
6975 {
6978 /* If these givs are identical, they can be combined. We use the results
6979 of express_from because the addends are not in a canonical form, so
6980 rtx_equal_p is a weaker test. */
6981 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6982 combination to be the other way round. */
6985 {
6987 }
6989 /* If G2 can be expressed as a function of G1 and that function is valid
6990 as an address and no more expensive than using a register for G2,
6991 the expression of G2 in terms of G1 can be used. */
6995 /* ??? Looses, especially with -fforce-addr, where *g2->location
6996 will always be a register, and so anything more complicated
6997 gets discarded. */
6998 #if 0
6999 #ifdef ADDRESS_COST
7001 #else
7003 #endif
7004 #endif
7005 )
7006 {
7008 }
7011 }
7012 \f
7013 struct combine_givs_stats
7014 {
7017 };
7019 static int
7023 {
7030 /* Stabilize the sort. */
7034 }
7036 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7037 any other. If so, point SAME to the giv combined with and set NEW_REG to
7038 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7039 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7041 static void
7044 {
7045 /* Additional benefit to add for being combined multiple times. */
7053 /* Count givs, because bl->giv_count is incorrect here. */
7057 giv_count++;
7059 giv_array
7070 {
7072 rtx single_use;
7077 /* If a DEST_REG GIV is used only once, do not allow it to combine
7078 with anything, for in doing so we will gain nothing that cannot
7079 be had by simply letting the GIV with which we would have combined
7080 to be reduced on its own. The losage shows up in particular with
7081 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7082 be seen elsewhere as well. */
7089 /* Add an additional weight for zero addends. */
7094 {
7095 rtx this_combine;
7100 {
7103 }
7104 }
7106 }
7108 /* Iterate, combining until we can't. */
7109 restart:
7113 {
7116 {
7122 }
7124 }
7127 {
7133 /* If it has already been combined, skip. */
7138 {
7141 /* If it has already been combined, skip. */
7143 {
7153 /* ??? The new final_[bg]iv_value code does a much better job
7154 of finding replaceable giv's, and hence this code may no
7155 longer be necessary. */
7159 /* To help optimize the next set of combinations, remove
7160 this giv from the benefits of other potential mates. */
7162 {
7166 }
7172 }
7173 }
7175 /* To help optimize the next set of combinations, remove
7176 this giv from the benefits of other potential mates. */
7178 {
7180 {
7184 }
7188 /* We've finished with this giv, and everything it touched.
7189 Restart the combination so that proper weights for the
7190 rest of the givs are properly taken into account. */
7191 /* ??? Ideally we would compact the arrays at this point, so
7192 as to not cover old ground. But sanely compacting
7193 can_combine is tricky. */
7195 }
7196 }
7198 /* Clean up. */
7201 }
7202 \f
7203 struct recombine_givs_stats
7204 {
7207 };
7209 /* Used below as comparison function for qsort. We want a ascending luid
7210 when scanning the array starting at the end, thus the arguments are
7211 used in reverse. */
7212 static int
7216 {
7223 /* Stabilize the sort. */
7227 }
7229 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7230 look for the start of life of a giv where the start has not been seen
7231 yet to unlock the search for the end of its life.
7232 Only consider givs that belong to BIV.
7233 Return the total number of lifetime ends that have been found. */
7234 static int
7238 {
7246 {
7248 {
7251 {
7259 {
7260 /* If we see a 0 here for end_luid, it means that we have
7261 scanned the entire loop without finding any use at all.
7262 We must not predicate this code on a start_luid match
7263 since that would make the test fail for givs that have
7264 been hoisted out of inner loops. */
7266 {
7269 }
7272 }
7274 }
7276 }
7278 {
7286 {
7291 }
7293 }
7301 }
7305 {
7312 }
7314 }
7316 /* For each giv that has been combined with another, look if
7317 we can combine it with the most recently used one instead.
7318 This tends to shorten giv lifetimes, and helps the next step:
7319 try to derive givs from other givs. */
7320 static void
7325 {
7333 {
7335 giv_count++;
7336 }
7337 giv_array
7341 /* Initialize stats and set up the ix field for each giv in stats to name
7342 the corresponding index into stats. */
7344 {
7345 rtx p;
7351 /* If this giv has been hoisted out of an inner loop, use the luid of
7352 the previous insn. */
7356 i++;
7357 }
7361 /* Set up the ix field for each giv in stats to name
7362 the corresponding index into stats, and
7363 do the actual most-recently-used recombination. */
7365 {
7369 {
7371 rtx new_combine;
7373 /* combine_givs_p actually says if we can make this transformation.
7374 The other tests are here only to avoid keeping a giv alive
7375 that could otherwise be eliminated. */
7381 {
7386 /* No need to update lifetimes / benefits here since we have
7387 already decided what to reduce. */
7390 {
7396 }
7398 }
7400 }
7408 }
7411 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7412 lifetime ends from regscan info. */
7414 {
7419 {
7420 /* Loop unrolling of an inner loop can even create new DEST_REG
7421 givs. */
7422 rtx p;
7428 }
7430 {
7432 {
7435 }
7437 {
7438 rtx p;
7439 /* This insn has been created by loop optimization on an inner
7440 loop. We don't have a proper start_luid that will match
7441 when we see the first set. But we do know that there will
7442 be no use before the set, so we can set end_luid to 0 so that
7443 we'll start looking for the last use right away. */
7448 ends_need_computing++;
7449 }
7450 else
7451 {
7456 /* Find the first insn that sets the giv, so that we can verify
7457 if this giv's lifetime wraps around the loop. We also need
7458 the luid of the first setting insn in order to detect the
7459 last use properly. */
7461 {
7464 count--;
7465 }
7469 {
7471 ends_need_computing++;
7472 }
7473 else
7474 {
7477 {
7479 ends_need_computing++;
7480 }
7481 }
7482 }
7483 }
7484 }
7486 /* If the regscan information was unconclusive for one or more DEST_REG
7487 givs, scan the all insn in the loop to find out lifetime ends. */
7489 {
7493 do
7494 {
7501 }
7503 }
7505 /* Set start_luid back to the last insn that sets the giv. This allows
7506 more combinations. */
7508 {
7514 }
7516 /* Now adjust lifetime ends by taking combined givs into account. */
7518 {
7526 {
7529 /* Use unsigned arithmetic to model loop wrap-around. */
7533 }
7534 }
7538 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7539 same mult_val and non-overlapping lifetime. This reduces register
7540 pressure.
7541 Once we find a DEST_REG giv that is suitable to derive others from,
7542 we set last_giv to this giv, and try to derive as many other DEST_REG
7543 givs from it without joining overlapping lifetimes. If we then
7544 encounter a DEST_REG giv that we can't derive, we set rescan to the
7545 index for this giv (unless rescan is already set).
7546 When we are finished with the current LAST_GIV (i.e. the inner loop
7547 terminates), we start again with rescan, which then becomes the new
7548 LAST_GIV. */
7550 {
7554 {
7555 rtx sum;
7561 {
7562 /* Don't use a giv that's likely to be dead to derive
7563 others - that would be likely to keep that giv alive. */
7565 {
7569 }
7571 }
7572 /* Use unsigned arithmetic to model loop wrap around. */
7577 /* Check that the giv insn we're about to use for deriving
7578 precedes all uses of that giv. Note that initializing the
7579 derived giv would defeat the purpose of reducing register
7580 pressure.
7581 ??? We could arrange to move the insn. */
7585 /* ??? Could handle libcalls, but would need more logic. */
7587 /* We would really like to know if for any giv that v
7588 is combined with, v->insn or any intervening biv increment
7589 dominates that combined giv. However, we
7590 don't have this detailed control flow information.
7591 N.B. since last_giv will be reduced, it is valid
7592 anywhere in the loop, so we don't need to check the
7593 validity of last_giv.
7594 We rely here on the fact that v->always_executed implies that
7595 there is no jump to someplace else in the loop before the
7596 giv insn, and hence any insn that is executed before the
7597 giv insn in the loop will have a lower luid. */
7600 /* Make sure we don't make the add more expensive. ADD_COST
7601 doesn't take different costs of registers and constants into
7602 account, so compare the cost of the actual SET_SRCs. */
7605 /* ??? unroll can't understand anything but reg + const_int
7606 sums. It would be cleaner to fix unroll. */
7613 {
7618 {
7624 }
7625 }
7628 }
7629 }
7631 /* Clean up. */
7634 }
7635 \f
7636 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7638 void
7644 rtx insert_before;
7645 {
7646 rtx seq;
7647 rtx result;
7649 /* Prevent unexpected sharing of these rtx. */
7653 /* Increase the lifetime of any invariants moved further in code. */
7667 /* It is entirely possible that the expansion created lots of new
7668 registers. Iterate over the sequence we just created and
7669 record them all. */
7672 {
7675 {
7679 }
7680 }
7684 }
7685 \f
7686 /* Test whether A * B can be computed without
7687 an actual multiply insn. Value is 1 if so. */
7689 static int
7691 rtx a;
7692 rtx b;
7693 {
7695 rtx tmp;
7700 /* If only one is constant, make it B. */
7704 /* If first constant, both constant, so don't need multiply. */
7708 /* If second not constant, neither is constant, so would need multiply. */
7712 /* One operand is constant, so might not need multiply insn. Generate the
7713 code for the multiply and see if a call or multiply, or long sequence
7714 of insns is generated. */
7723 {
7728 else
7730 {
7739 {
7742 }
7743 }
7744 }
7753 /* Free any storage we obtained in generating this multiply and restore rtl
7754 allocation to its normal obstack. */
7759 }
7760 \f
7761 /* Check to see if loop can be terminated by a "decrement and branch until
7762 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7763 Also try reversing an increment loop to a decrement loop
7764 to see if the optimization can be performed.
7765 Value is nonzero if optimization was performed. */
7767 /* This is useful even if the architecture doesn't have such an insn,
7768 because it might change a loops which increments from 0 to n to a loop
7769 which decrements from n to 0. A loop that decrements to zero is usually
7770 faster than one that increments from zero. */
7772 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7773 such as approx_final_value, biv_total_increment, loop_iterations, and
7774 final_[bg]iv_value. */
7776 static int
7780 {
7782 rtx reg;
7783 rtx jump_label;
7784 rtx final_value;
7785 rtx start_value;
7786 rtx new_add_val;
7787 rtx comparison;
7788 rtx before_comparison;
7789 rtx p;
7790 rtx jump;
7791 rtx first_compare;
7797 /* If last insn is a conditional branch, and the insn before tests a
7798 register value, try to optimize it. Otherwise, we can't do anything. */
7805 /* Try to compute whether the compare/branch at the loop end is one or
7806 two instructions. */
7812 else
7815 /* Check all of the bivs to see if the compare uses one of them.
7816 Skip biv's set more than once because we can't guarantee that
7817 it will be zero on the last iteration. Also skip if the biv is
7818 used between its update and the test insn. */
7821 {
7826 first_compare))
7828 }
7833 /* Look for the case where the basic induction variable is always
7834 nonnegative, and equals zero on the last iteration.
7835 In this case, add a reg_note REG_NONNEG, which allows the
7836 m68k DBRA instruction to be used. */
7844 {
7845 /* Initial value must be greater than 0,
7846 init_val % -dec_value == 0 to ensure that it equals zero on
7847 the last iteration */
7853 {
7854 /* register always nonnegative, add REG_NOTE to branch */
7861 }
7863 /* If the decrement is 1 and the value was tested as >= 0 before
7864 the loop, then we can safely optimize. */
7866 {
7879 {
7886 }
7887 }
7888 }
7891 {
7892 /* Try to change inc to dec, so can apply above optimization. */
7893 /* Can do this if:
7894 all registers modified are induction variables or invariant,
7895 all memory references have non-overlapping addresses
7896 (obviously true if only one write)
7897 allow 2 insns for the compare/jump at the end of the loop. */
7898 /* Also, we must avoid any instructions which use both the reversed
7899 biv and another biv. Such instructions will fail if the loop is
7900 reversed. We meet this condition by requiring that either
7901 no_use_except_counting is true, or else that there is only
7902 one biv. */
7904 /* 1 if the iteration var is used only to count iterations. */
7906 /* 1 if the loop has no memory store, or it has a single memory store
7907 which is reversible. */
7911 {
7914 /* If there are no givs for this biv, and the only exit is the
7915 fall through at the end of the loop, then
7916 see if perhaps there are no uses except to count. */
7920 {
7925 /* An insn that sets the biv is okay. */
7926 ;
7930 {
7931 /* If either of these insns uses the biv and sets a pseudo
7932 that has more than one usage, then the biv has uses
7933 other than counting since it's used to derive a value
7934 that is used more than one time. */
7939 {
7942 }
7943 }
7945 {
7948 }
7949 }
7950 }
7955 {
7960 /* If the loop has a single store, and the destination address is
7961 invariant, then we can't reverse the loop, because this address
7962 might then have the wrong value at loop exit.
7963 This would work if the source was invariant also, however, in that
7964 case, the insn should have been moved out of the loop. */
7967 {
7970 reversible_mem_store
7971 = (! unknown_address_altered
7972 && ! unknown_constant_address_altered
7977 /* If the store depends on a register that is set after the
7978 store, it depends on the initial value, and is thus not
7979 reversible. */
7981 {
7987 }
7988 }
7989 }
7990 else
7993 /* This code only acts for innermost loops. Also it simplifies
7994 the memory address check by only reversing loops with
7995 zero or one memory access.
7996 Two memory accesses could involve parts of the same array,
7997 and that can't be reversed.
7998 If the biv is used only for counting, than we don't need to worry
7999 about all these things. */
8004 && reversible_mem_store
8009 {
8010 rtx tem;
8012 /* Loop can be reversed. */
8016 /* Now check other conditions:
8018 The increment must be a constant, as must the initial value,
8019 and the comparison code must be LT.
8021 This test can probably be improved since +/- 1 in the constant
8022 can be obtained by changing LT to LE and vice versa; this is
8023 confusing. */
8026 /* for constants, LE gets turned into LT */
8030 {
8041 comparison_const_width
8043 else
8044 comparison_const_width
8048 comparison_sign_mask
8051 /* If the comparison value is not a loop invariant, then we
8052 can not reverse this loop.
8054 ??? If the insns which initialize the comparison value as
8055 a whole compute an invariant result, then we could move
8056 them out of the loop and proceed with loop reversal. */
8064 /* Normalize the initial value if it is an integer and
8065 has no other use except as a counter. This will allow
8066 a few more loops to be reversed. */
8070 {
8072 /* The code below requires comparison_val to be a multiple
8073 of add_val in order to do the loop reversal, so
8074 round up comparison_val to a multiple of add_val.
8075 Since comparison_value is constant, we know that the
8076 current comparison code is LT. */
8078 comparison_val
8080 /* We postpone overflow checks for COMPARISON_VAL here;
8081 even if there is an overflow, we might still be able to
8082 reverse the loop, if converting the loop exit test to
8083 NE is possible. */
8085 }
8087 /* First check if we can do a vanilla loop reversal. */
8089 /* If we have a decrement_and_branch_on_count,
8090 prefer the NE test, since this will allow that
8091 instruction to be generated. Note that we must
8092 use a vanilla loop reversal if the biv is used to
8093 calculate a giv or has a non-counting use. */
8094 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8095 && defined (HAVE_decrement_and_branch_on_count)
8099 #endif
8101 /* Now do postponed overflow checks on COMPARISON_VAL. */
8104 {
8105 /* Register will always be nonnegative, with value
8106 0 on last iteration */
8110 }
8114 {
8117 }
8118 else
8124 /* If the initial value is not zero, or if the comparison
8125 value is not an exact multiple of the increment, then we
8126 can not reverse this loop. */
8129 {
8132 }
8133 else
8134 {
8137 }
8141 /* Reset these in case we normalized the initial value
8142 and comparison value above. */
8145 {
8147 final_value
8149 }
8152 /* Save some info needed to produce the new insns. */
8159 /* Set start_value; if this is not a CONST_INT, we need
8160 to generate a SUB.
8161 Initialize biv to start_value before loop start.
8162 The old initializing insn will be deleted as a
8163 dead store by flow.c. */
8166 {
8169 loop_start);
8170 }
8172 {
8175 enum insn_code icode
8184 start_value
8188 loop_start);
8192 }
8194 {
8196 enum insn_code icode
8204 start_value
8208 loop_start);
8209 }
8210 else
8211 /* We could handle the other cases too, but it'll be
8212 better to have a testcase first. */
8215 /* We may not have a single insn which can increment a reg, so
8216 create a sequence to hold all the insns from expand_inc. */
8225 /* Update biv info to reflect its new status. */
8230 /* Update loop info. */
8239 /* Inc LABEL_NUSES so that delete_insn will
8240 not delete the label. */
8243 /* Emit an insn after the end of the loop to set the biv's
8244 proper exit value if it is used anywhere outside the loop. */
8249 loop_end);
8251 /* Delete compare/branch at end of loop. */
8256 /* Add new compare/branch insn at end of loop. */
8268 ;
8274 {
8276 {
8277 /* Increment of LABEL_NUSES done above. */
8278 /* Register is now always nonnegative,
8279 so add REG_NONNEG note to the branch. */
8282 }
8284 }
8286 /* No insn may reference both the reversed and another biv or it
8287 will fail (see comment near the top of the loop reversal
8288 code).
8289 Earlier on, we have verified that the biv has no use except
8290 counting, or it is the only biv in this function.
8291 However, the code that computes no_use_except_counting does
8292 not verify reg notes. It's possible to have an insn that
8293 references another biv, and has a REG_EQUAL note with an
8294 expression based on the reversed biv. To avoid this case,
8295 remove all REG_EQUAL notes based on the reversed biv
8296 here. */
8299 {
8302 /* If this is a set of a GIV based on the reversed biv, any
8303 REG_EQUAL notes should still be correct. */
8310 {
8315 else
8317 }
8318 }
8320 /* Mark that this biv has been reversed. Each giv which depends
8321 on this biv, and which is also live past the end of the loop
8322 will have to be fixed up. */
8327 {
8331 else
8333 }
8336 }
8337 }
8338 }
8341 }
8342 \f
8343 /* Verify whether the biv BL appears to be eliminable,
8344 based on the insns in the loop that refer to it.
8346 If ELIMINATE_P is non-zero, actually do the elimination.
8348 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8349 determine whether invariant insns should be placed inside or at the
8350 start of the loop. */
8352 static int
8358 {
8362 rtx p;
8364 /* Scan all insns in the loop, stopping if we find one that uses the
8365 biv in a way that we cannot eliminate. */
8368 {
8372 /* If this is a libcall that sets a giv, skip ahead to its end. */
8374 {
8378 {
8383 {
8390 }
8391 }
8392 }
8397 {
8403 }
8404 }
8407 {
8412 }
8415 }
8416 \f
8417 /* INSN and REFERENCE are instructions in the same insn chain.
8418 Return non-zero if INSN is first. */
8420 int
8423 {
8427 {
8428 /* Start with test for not first so that INSN == REFERENCE yields not
8429 first. */
8435 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8436 previous insn, hence the <= comparison below does not work if
8437 P is a note. */
8448 }
8449 }
8451 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8452 the offset that we have to take into account due to auto-increment /
8453 div derivation is zero. */
8454 static int
8457 rtx insn;
8458 {
8459 /* If the giv V had the auto-inc address optimization applied
8460 to it, and INSN occurs between the giv insn and the biv
8461 insn, then we'd have to adjust the value used here.
8462 This is rare, so we don't bother to make this possible. */
8470 /* If the giv V was derived from another giv, and INSN does
8471 not occur between the giv insn and the biv insn, then we'd
8472 have to adjust the value used here. This is rare, so we don't
8473 bother to make this possible. */
8487 }
8489 /* If BL appears in X (part of the pattern of INSN), see if we can
8490 eliminate its use. If so, return 1. If not, return 0.
8492 If BIV does not appear in X, return 1.
8494 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8495 where extra insns should be added. Depending on how many items have been
8496 moved out of the loop, it will either be before INSN or at the start of
8497 the loop. */
8499 static int
8505 rtx where;
8506 {
8512 #ifdef HAVE_cc0
8514 #endif
8520 {
8522 /* If we haven't already been able to do something with this BIV,
8523 we can't eliminate it. */
8529 /* If this sets the BIV, it is not a problem. */
8533 /* If this is an insn that defines a giv, it is also ok because
8534 it will go away when the giv is reduced. */
8539 #ifdef HAVE_cc0
8541 {
8542 /* Can replace with any giv that was reduced and
8543 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8544 Require a constant for MULT_VAL, so we know it's nonzero.
8545 ??? We disable this optimization to avoid potential
8546 overflows. */
8554 {
8561 /* If the giv has the opposite direction of change,
8562 then reverse the comparison. */
8566 else
8569 /* We can probably test that giv's reduced reg. */
8572 }
8574 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8575 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8576 Require a constant for MULT_VAL, so we know it's nonzero.
8577 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8578 overflow problem. */
8589 {
8596 /* If the giv has the opposite direction of change,
8597 then reverse the comparison. */
8601 else
8605 /* Replace biv with the giv's reduced register. */
8610 /* Insn doesn't support that constant or invariant. Copy it
8611 into a register (it will be a loop invariant.) */
8615 where);
8617 /* Substitute the new register for its invariant value in
8618 the compare expression. */
8622 }
8623 }
8624 #endif
8631 /* See if either argument is the biv. */
8636 else
8640 {
8641 /* First try to replace with any giv that has constant positive
8642 mult_val and constant add_val. We might be able to support
8643 negative mult_val, but it seems complex to do it in general. */
8654 {
8661 /* Replace biv with the giv's reduced reg. */
8664 /* If all constants are actually constant integers and
8665 the derived constant can be directly placed in the COMPARE,
8666 do so. */
8670 {
8675 }
8676 else
8677 {
8678 /* Otherwise, load it into a register. */
8682 }
8685 }
8687 /* Look for giv with positive constant mult_val and nonconst add_val.
8688 Insert insns to calculate new compare value.
8689 ??? Turn this off due to possible overflow. */
8696 {
8697 rtx tem;
8707 /* Replace biv with giv's reduced register. */
8711 /* Compute value to compare against. */
8713 /* Use it in this insn. */
8717 }
8718 }
8720 {
8722 {
8723 /* Look for giv with constant positive mult_val and nonconst
8724 add_val. Insert insns to compute new compare value.
8725 ??? Turn this off due to possible overflow. */
8732 {
8733 rtx tem;
8743 /* Replace biv with giv's reduced register. */
8747 /* Compute value to compare against. */
8753 }
8754 }
8756 /* This code has problems. Basically, you can't know when
8757 seeing if we will eliminate BL, whether a particular giv
8758 of ARG will be reduced. If it isn't going to be reduced,
8759 we can't eliminate BL. We can try forcing it to be reduced,
8760 but that can generate poor code.
8762 The problem is that the benefit of reducing TV, below should
8763 be increased if BL can actually be eliminated, but this means
8764 we might have to do a topological sort of the order in which
8765 we try to process biv. It doesn't seem worthwhile to do
8766 this sort of thing now. */
8768 #if 0
8769 /* Otherwise the reg compared with had better be a biv. */
8774 /* Look for a pair of givs, one for each biv,
8775 with identical coefficients. */
8777 {
8788 {
8795 /* Replace biv with its giv's reduced reg. */
8797 /* Replace other operand with the other giv's
8798 reduced reg. */
8801 }
8802 }
8803 #endif
8804 }
8806 /* If we get here, the biv can't be eliminated. */
8810 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8811 biv is used in it, since it will be replaced. */
8819 }
8821 /* See if any subexpression fails elimination. */
8824 {
8826 {
8839 }
8840 }
8843 }
8844 \f
8845 /* Return nonzero if the last use of REG
8846 is in an insn following INSN in the same basic block. */
8848 static int
8850 rtx reg;
8851 rtx insn;
8852 {
8853 rtx n;
8857 {
8860 }
8862 }
8863 \f
8864 /* Called via `note_stores' to record the initial value of a biv. Here we
8865 just record the location of the set and process it later. */
8867 static void
8869 rtx dest;
8870 rtx set;
8872 {
8882 /* If this is the first set found, record it. */
8884 {
8887 }
8888 }
8889 \f
8890 /* If any of the registers in X are "old" and currently have a last use earlier
8891 than INSN, update them to have a last use of INSN. Their actual last use
8892 will be the previous insn but it will not have a valid uid_luid so we can't
8893 use it. */
8895 static void
8897 rtx x;
8898 rtx insn;
8899 {
8900 /* Check for the case where INSN does not have a valid luid. In this case,
8901 there is no need to modify the regno_last_uid, as this can only happen
8902 when code is inserted after the loop_end to set a pseudo's final value,
8903 and hence this insn will never be the last use of x. */
8908 else
8909 {
8913 {
8919 }
8920 }
8921 }
8922 \f
8923 /* Given an insn INSN and condition COND, return the condition in a
8924 canonical form to simplify testing by callers. Specifically:
8926 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8927 (2) Both operands will be machine operands; (cc0) will have been replaced.
8928 (3) If an operand is a constant, it will be the second operand.
8929 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8930 for GE, GEU, and LEU.
8932 If the condition cannot be understood, or is an inequality floating-point
8933 comparison which needs to be reversed, 0 will be returned.
8935 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8937 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8938 insn used in locating the condition was found. If a replacement test
8939 of the condition is desired, it should be placed in front of that
8940 insn and we will be sure that the inputs are still valid.
8942 If WANT_REG is non-zero, we wish the condition to be relative to that
8943 register, if possible. Therefore, do not canonicalize the condition
8944 further. */
8946 rtx
8948 rtx insn;
8949 rtx cond;
8952 rtx want_reg;
8953 {
8956 rtx set;
8957 rtx tem;
8969 {
8972 }
8977 /* If we are comparing a register with zero, see if the register is set
8978 in the previous insn to a COMPARE or a comparison operation. Perform
8979 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8980 in cse.c */
8985 {
8986 /* Set non-zero when we find something of interest. */
8989 #ifdef HAVE_cc0
8990 /* If comparison with cc0, import actual comparison from compare
8991 insn. */
8993 {
9004 }
9005 #endif
9007 /* If this is a COMPARE, pick up the two things being compared. */
9009 {
9013 }
9017 /* Go back to the previous insn. Stop if it is not an INSN. We also
9018 stop if it isn't a single set or if it has a REG_INC note because
9019 we don't want to bother dealing with it. */
9027 /* If this is setting OP0, get what it sets it to if it looks
9028 relevant. */
9030 {
9033 /* ??? We may not combine comparisons done in a CCmode with
9034 comparisons not done in a CCmode. This is to aid targets
9035 like Alpha that have an IEEE compliant EQ instruction, and
9036 a non-IEEE compliant BEQ instruction. The use of CCmode is
9037 actually artificial, simply to prevent the combination, but
9038 should not affect other platforms.
9040 However, we must allow VOIDmode comparisons to match either
9041 CCmode or non-CCmode comparison, because some ports have
9042 modeless comparisons inside branch patterns.
9044 ??? This mode check should perhaps look more like the mode check
9045 in simplify_comparison in combine. */
9053 && (STORE_FLAG_VALUE
9056 #ifdef FLOAT_STORE_FLAG_VALUE
9059 && (REAL_VALUE_NEGATIVE
9061 #endif
9062 ))
9073 && (STORE_FLAG_VALUE
9076 #ifdef FLOAT_STORE_FLAG_VALUE
9079 && (REAL_VALUE_NEGATIVE
9081 #endif
9082 ))
9088 {
9089 /* We might have reversed a LT to get a GE here. But this wasn't
9090 actually the comparison of data, so we don't flag that we
9091 have had to reverse the condition. */
9095 }
9096 else
9098 }
9101 /* If this sets OP0, but not directly, we have to give up. */
9105 {
9109 {
9115 }
9120 }
9121 }
9123 /* If constant is first, put it last. */
9127 /* If OP0 is the result of a comparison, we weren't able to find what
9128 was really being compared, so fail. */
9132 /* Canonicalize any ordered comparison with integers involving equality
9133 if we can do computations in the relevant mode and we do not
9134 overflow. */
9139 {
9142 unsigned HOST_WIDE_INT max_val
9146 {
9152 /* When cross-compiling, const_val might be sign-extended from
9153 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9173 }
9174 }
9176 /* If this was floating-point and we reversed anything other than an
9177 EQ or NE or (UN)ORDERED, return zero. */
9179 && did_reverse_condition
9181 && ! flag_fast_math
9185 #ifdef HAVE_cc0
9186 /* Never return CC0; return zero instead. */
9189 #endif
9192 }
9194 /* Given a jump insn JUMP, return the condition that will cause it to branch
9195 to its JUMP_LABEL. If the condition cannot be understood, or is an
9196 inequality floating-point comparison which needs to be reversed, 0 will
9197 be returned.
9199 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9200 insn used in locating the condition was found. If a replacement test
9201 of the condition is desired, it should be placed in front of that
9202 insn and we will be sure that the inputs are still valid. */
9204 rtx
9206 rtx jump;
9208 {
9209 rtx cond;
9212 /* If this is not a standard conditional jump, we can't parse it. */
9219 /* If this branches to JUMP_LABEL when the condition is false, reverse
9220 the condition. */
9221 reverse
9226 }
9228 /* Similar to above routine, except that we also put an invariant last
9229 unless both operands are invariants. */
9231 rtx
9234 rtx x;
9235 {
9245 }
9247 #ifdef HAVE_decrement_and_branch_on_count
9248 /* Instrument loop for insertion of bct instruction. We distinguish between
9249 loops with compile-time bounds and those with run-time bounds.
9250 Information from loop_iterations() is used to compute compile-time bounds.
9251 Run-time bounds should use loop preconditioning, but currently ignored.
9252 */
9254 static void
9257 {
9264 #if 0
9266 /* If the loop condition is <= or >=, the number of iteration
9267 is 1 more than the range of the bounds of the loop. */
9270 #endif
9272 /* It's impossible to instrument a competely unrolled loop. */
9276 /* Make sure that the count register is not in use. */
9278 {
9282 loop_num);
9284 }
9286 /* Make sure that the function has no indirect jumps. */
9288 {
9292 loop_num);
9294 }
9296 /* Make sure that the last loop insn is a conditional jump. */
9300 {
9304 loop_num);
9306 }
9308 /* Make sure that the loop does not contain a function call
9309 (the count register might be altered by the called function). */
9311 {
9315 loop_num);
9317 }
9319 /* Make sure that the loop does not jump via a table.
9320 (the count register might be used to perform the branch on table). */
9322 {
9326 loop_num);
9328 }
9330 /* Account for loop unrolling in instrumented iteration count. */
9333 else
9337 {
9338 /* Allow an enclosing outer loop to benefit if possible. */
9342 loop_num);
9344 }
9346 /* Try to instrument the loop. */
9348 /* Handle the simpler case, where the bounds are known at compile time. */
9350 {
9354 /* Mark all enclosing loops that they cannot use count register. */
9356 {
9359 }
9362 }
9364 /* Handle the more complex case, that the bounds are NOT known
9365 at compile time. In this case we generate run_time calculation
9366 of the number of iterations. */
9369 {
9373 loop_num);
9375 }
9379 {
9383 loop_num);
9385 }
9387 /* With runtime bounds, if the compare is of the form '!=' we give up */
9389 {
9393 loop_num);
9395 }
9396 /* Use common loop preconditioning code instead. */
9397 #if 0
9398 else
9399 {
9400 /* We rely on the existence of run-time guard to ensure that the
9401 loop executes at least once. */
9402 rtx sequence;
9403 rtx iterations_num_reg;
9405 unsigned HOST_WIDE_INT increment_value_abs
9408 /* make sure that the increment is a power of two, otherwise (an
9409 expensive) divide is needed. */
9411 {
9416 }
9418 /* compute the number of iterations */
9420 {
9421 rtx temp_reg;
9423 /* Again, the number of iterations is calculated by:
9424 ;
9425 ; compare-val - initial-val + (increment -1) + additional-iteration
9426 ; num_iterations = -----------------------------------------------------------------
9427 ; increment
9428 */
9429 /* ??? Do we have to call copy_rtx here before passing rtx to
9430 expand_binop? */
9432 {
9433 /* <, <= :the loop variable is increasing */
9437 }
9438 else
9439 {
9443 }
9453 temp_reg,
9456 else
9458 }
9463 }
9467 }
9469 /* Instrument loop by inserting a bct in it as follows:
9470 1. A new counter register is created.
9471 2. In the head of the loop the new variable is initialized to the value
9472 passed in the loop_num_iterations parameter.
9473 3. At the end of the loop, comparison of the register with 0 is generated.
9474 The created comparison follows the pattern defined for the
9475 decrement_and_branch_on_count insn, so this insn will be generated.
9476 4. The branch on the old variable are deleted. The compare must remain
9477 because it might be used elsewhere. If the loop-variable or condition
9478 register are used elsewhere, they will be eliminated by flow. */
9480 static void
9483 rtx loop_num_iterations;
9484 {
9485 rtx counter_reg;
9486 rtx start_label;
9487 rtx sequence;
9490 {
9492 {
9497 else
9500 }
9502 /* Discard original jump to continue loop. Original compare result
9503 may still be live, so it cannot be discarded explicitly. */
9506 /* Insert the label which will delimit the start of the loop. */
9510 /* Insert initialization of the count register into the loop header. */
9518 /* Insert new comparison on the count register instead of the
9519 old one, generating the needed BCT pattern (that will be
9520 later recognized by assembly generation phase). */
9522 start_label),
9523 loop_end);
9525 }
9527 }
9530 /* Scan the function and determine whether it has indirect (computed) jumps.
9532 This is taken mostly from flow.c; similar code exists elsewhere
9533 in the compiler. It may be useful to put this into rtlanal.c. */
9534 static int
9536 rtx start;
9537 {
9538 rtx insn;
9545 }
9547 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9548 documentation for LOOP_MEMS for the definition of `appropriate'.
9549 This function is called from prescan_loop via for_each_rtx. */
9551 static int
9555 {
9563 {
9568 /* We're not interested in MEMs that are only clobbered. */
9572 /* We're not interested in the MEM associated with a
9573 CONST_DOUBLE, so there's no need to traverse into this. */
9577 /* We're not interested in any MEMs that only appear in notes. */
9581 /* This is not a MEM. */
9583 }
9585 /* See if we've already seen this MEM. */
9588 {
9590 /* The modes of the two memory accesses are different. If
9591 this happens, something tricky is going on, and we just
9592 don't optimize accesses to this MEM. */
9596 }
9598 /* Resize the array, if necessary. */
9600 {
9603 else
9609 }
9611 /* Actually insert the MEM. */
9613 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9614 because we can't put it in a register. We still store it in the
9615 table, though, so that if we see the same address later, but in a
9616 non-BLK mode, we'll not think we can optimize it at that point. */
9622 }
9624 /* Like load_mems, but also ensures that SET_IN_LOOP,
9625 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9626 values after load_mems. */
9628 static void
9632 {
9637 /* Recalculate set_in_loop and friends since load_mems may have
9638 created new registers. */
9640 {
9648 {
9649 /* Grow all the arrays. */
9654 }
9655 /* Clear the arrays */
9665 {
9668 }
9670 #ifdef AVOID_CCMODE_COPIES
9671 /* Don't try to move insns which set CC registers if we should not
9672 create CCmode register copies. */
9676 #endif
9678 /* Set n_times_set for the new registers. */
9682 }
9683 }
9685 /* Move MEMs into registers for the duration of the loop. */
9687 static void
9690 {
9693 rtx p;
9696 /* Nonzero if the next instruction may never be executed. */
9703 /* Find start of the extended basic block that enters the loop. */
9707 ;
9711 /* Build table of mems that get set to constant values before the
9712 loop. */
9716 /* Check to see if it's possible that some instructions in the
9717 loop are never executed. */
9721 {
9725 /* If we enter the loop in the middle, and scan
9726 around to the beginning, don't set maybe_never
9727 for that. This must be an unconditional jump,
9728 otherwise the code at the top of the loop might
9729 never be executed. Unconditional jumps are
9730 followed a by barrier then loop end. */
9735 {
9737 /* Something complicated. */
9739 else
9740 /* If there are any more instructions in the loop, they
9741 might not be reached. */
9743 }
9746 }
9748 /* Actually move the MEMs. */
9750 {
9751 regset_head copies;
9753 rtx reg;
9755 rtx mem_list_entry;
9759 /* There's no telling whether or not MEM is modified. */
9762 /* Go through the MEMs written to in the loop to see if this
9763 one is aliased by one of them. */
9766 {
9771 {
9772 /* MEM is indeed aliased by this store. */
9775 }
9777 }
9783 /* If this MEM is written to, we must be sure that there
9784 are no reads from another MEM that aliases this one. */
9786 {
9790 {
9794 VOIDmode,
9796 rtx_varies_p))
9797 {
9798 /* It's not safe to hoist loop_mems[i] out of
9799 the loop because writes to it might not be
9800 seen by reads from loop_mems[j]. */
9803 }
9804 }
9805 }
9808 /* We can't access the MEM outside the loop; it might
9809 cause a trap that wouldn't have happened otherwise. */
9813 /* We thought we were going to lift this MEM out of the
9814 loop, but later discovered that we could not. */
9819 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9820 order to keep scan_loop from moving stores to this MEM
9821 out of the loop just because this REG is neither a
9822 user-variable nor used in the loop test. */
9827 /* Now, replace all references to the MEM with the
9828 corresponding pesudos. */
9833 {
9834 rtx_and_int ri;
9835 rtx set;
9838 {
9839 /* See if this copies the mem into a register that isn't
9840 modified afterwards. We'll try to do copy propagation
9841 a little further on. */
9844 /* @@@ This test is _way_ too conservative. */
9845 && ! maybe_never
9855 }
9860 }
9863 /* We couldn't replace all occurrences of the MEM. */
9865 else
9866 {
9867 /* Load the memory immediately before LOOP->START, which is
9868 the NOTE_LOOP_BEG. */
9870 rtx set;
9876 {
9880 {
9884 /* Extending hard register lifetimes cuases crash
9885 on SRC targets. Doing so on non-SRC is
9886 probably also not good idea, since we most
9887 probably have pseudoregister equivalence as
9888 well. */
9891 }
9892 /* Use the constant equivalence if that is cheap enough. */
9898 {
9901 }
9903 /* If best_equiv is nonzero, we know that MEM is set to a
9904 constant or register before the loop. We will use this
9905 knowledge to initialize the shadow register with that
9906 constant or reg rather than by loading from MEM. */
9909 }
9918 {
9920 {
9921 /* We must compute the former
9922 right-after-the-end label before we insert
9923 the new one. */
9927 }
9929 /* Store the memory immediately after END, which is
9930 the NOTE_LOOP_END. */
9933 }
9936 {
9941 }
9943 /* Attempt a bit of copy propagation. This helps untangle the
9944 data flow, and enables {basic,general}_induction_var to find
9945 more bivs/givs. */
9946 EXECUTE_IF_SET_IN_REG_SET
9948 {
9950 });
9952 }
9953 }
9956 {
9957 /* Now, we need to replace all references to the previous exit
9958 label with the new one. */
9959 rtx_pair rr;
9964 {
9967 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9968 field. This is not handled by for_each_rtx because it doesn't
9969 handle unprinted ('0') fields. We need to update JUMP_LABEL
9970 because the immediately following unroll pass will use it.
9971 replace_label would not work anyways, because that only handles
9972 LABEL_REFs. */
9975 }
9976 }
9979 }
9981 /* For communication between note_reg_stored and its caller. */
9982 struct note_reg_stored_arg
9983 {
9985 rtx reg;
9986 };
9988 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9989 is equal to ARG. */
9990 static void
9994 {
9998 }
10000 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10001 There must be exactly one insn that sets this pseudo; it will be
10002 deleted if all replacements succeed and we can prove that the register
10003 is not used after the loop. */
10005 static void
10008 rtx replacement;
10010 {
10011 /* This is the reg that we are copying from. */
10014 rtx insn;
10015 /* These help keep track of whether we replaced all uses of the reg. */
10022 {
10023 rtx set;
10025 /* Only substitute within one extended basic block from the initializing
10026 insn. */
10033 /* Is this the initializing insn? */
10038 {
10045 }
10047 /* Only substitute after seeing the initializing insn. */
10049 {
10060 /* Stop replacing when REPLACEMENT is modified. */
10066 }
10067 }
10071 {
10075 {
10081 }
10084 }
10085 }
10087 /* Replace MEM with its associated pseudo register. This function is
10088 called from load_mems via for_each_rtx. DATA is actually an
10089 rtx_and_int * describing the instruction currently being scanned
10090 and the MEM we are currently replacing. */
10092 static int
10096 {
10098 rtx insn;
10106 {
10111 /* We're not interested in the MEM associated with a
10112 CONST_DOUBLE, so there's no need to traverse into one. */
10116 /* This is not a MEM. */
10118 }
10124 /* This is not the MEM we are currently replacing. */
10129 /* Actually replace the MEM. */
10133 }
10135 /* Replace one register with another. Called through for_each_rtx; PX points
10136 to the rtx being scanned. DATA is actually an array of three rtx's; the
10137 first one is the one to be replaced, and the second one the replacement.
10138 The third one is the current insn. */
10140 static int
10144 {
10155 }
10157 /* Replace occurrences of the old exit label for the loop with the new
10158 one. DATA is an rtx_pair containing the old and new labels,
10159 respectively. */
10161 static int
10165 {
10184 }