1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
39 /* Forward declarations */
40 static void set_of_1 (rtx
, const_rtx
, void *);
41 static bool covers_regno_p (const_rtx
, unsigned int);
42 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
43 static int computed_jump_p_1 (const_rtx
);
44 static void parms_set (rtx
, const_rtx
, void *);
46 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
47 const_rtx
, machine_mode
,
48 unsigned HOST_WIDE_INT
);
49 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
50 const_rtx
, machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
53 const_rtx
, machine_mode
,
55 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
56 const_rtx
, machine_mode
,
59 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
60 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
62 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
63 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
64 SIGN_EXTEND then while narrowing we also have to enforce the
65 representation and sign-extend the value to mode DESTINATION_REP.
67 If the value is already sign-extended to DESTINATION_REP mode we
68 can just switch to DESTINATION mode on it. For each pair of
69 integral modes SOURCE and DESTINATION, when truncating from SOURCE
70 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
71 contains the number of high-order bits in SOURCE that have to be
72 copies of the sign-bit so that we can do this mode-switch to
76 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
78 /* Store X into index I of ARRAY. ARRAY is known to have at least I
79 elements. Return the new base of ARRAY. */
82 typename
T::value_type
*
83 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
85 size_t i
, value_type x
)
87 if (base
== array
.stack
)
94 gcc_checking_assert (i
== LOCAL_ELEMS
);
95 /* A previous iteration might also have moved from the stack to the
96 heap, in which case the heap array will already be big enough. */
97 if (vec_safe_length (array
.heap
) <= i
)
98 vec_safe_grow (array
.heap
, i
+ 1);
99 base
= array
.heap
->address ();
100 memcpy (base
, array
.stack
, sizeof (array
.stack
));
101 base
[LOCAL_ELEMS
] = x
;
104 unsigned int length
= array
.heap
->length ();
107 gcc_checking_assert (base
== array
.heap
->address ());
113 gcc_checking_assert (i
== length
);
114 vec_safe_push (array
.heap
, x
);
115 return array
.heap
->address ();
119 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
120 number of elements added to the worklist. */
122 template <typename T
>
124 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
126 size_t end
, rtx_type x
)
128 enum rtx_code code
= GET_CODE (x
);
129 const char *format
= GET_RTX_FORMAT (code
);
130 size_t orig_end
= end
;
131 if (__builtin_expect (INSN_P (x
), false))
133 /* Put the pattern at the top of the queue, since that's what
134 we're likely to want most. It also allows for the SEQUENCE
136 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
137 if (format
[i
] == 'e')
139 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
140 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
143 base
= add_single_to_queue (array
, base
, end
++, subx
);
147 for (int i
= 0; format
[i
]; ++i
)
148 if (format
[i
] == 'e')
150 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
151 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
154 base
= add_single_to_queue (array
, base
, end
++, subx
);
156 else if (format
[i
] == 'E')
158 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
159 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
160 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
161 for (unsigned int j
= 0; j
< length
; j
++)
162 base
[end
++] = T::get_value (vec
[j
]);
164 for (unsigned int j
= 0; j
< length
; j
++)
165 base
= add_single_to_queue (array
, base
, end
++,
166 T::get_value (vec
[j
]));
167 if (code
== SEQUENCE
&& end
== length
)
168 /* If the subrtxes of the sequence fill the entire array then
169 we know that no other parts of a containing insn are queued.
170 The caller is therefore iterating over the sequence as a
171 PATTERN (...), so we also want the patterns of the
173 for (unsigned int j
= 0; j
< length
; j
++)
175 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
177 base
[j
] = T::get_value (PATTERN (x
));
180 return end
- orig_end
;
183 template <typename T
>
185 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
187 vec_free (array
.heap
);
190 template <typename T
>
191 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
193 template class generic_subrtx_iterator
<const_rtx_accessor
>;
194 template class generic_subrtx_iterator
<rtx_var_accessor
>;
195 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
197 /* Return 1 if the value of X is unstable
198 (would be different at a different point in the program).
199 The frame pointer, arg pointer, etc. are considered stable
200 (within one function) and so is anything marked `unchanging'. */
203 rtx_unstable_p (const_rtx x
)
205 const RTX_CODE code
= GET_CODE (x
);
212 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
221 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
222 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
223 /* The arg pointer varies if it is not a fixed register. */
224 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
226 /* ??? When call-clobbered, the value is stable modulo the restore
227 that must happen after a call. This currently screws up local-alloc
228 into believing that the restore is not needed. */
229 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
234 if (MEM_VOLATILE_P (x
))
243 fmt
= GET_RTX_FORMAT (code
);
244 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
247 if (rtx_unstable_p (XEXP (x
, i
)))
250 else if (fmt
[i
] == 'E')
253 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
254 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
261 /* Return 1 if X has a value that can vary even between two
262 executions of the program. 0 means X can be compared reliably
263 against certain constants or near-constants.
264 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
265 zero, we are slightly more conservative.
266 The frame pointer and the arg pointer are considered constant. */
269 rtx_varies_p (const_rtx x
, bool for_alias
)
282 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
291 /* Note that we have to test for the actual rtx used for the frame
292 and arg pointers and not just the register number in case we have
293 eliminated the frame and/or arg pointer and are using it
295 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
296 /* The arg pointer varies if it is not a fixed register. */
297 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
299 if (x
== pic_offset_table_rtx
300 /* ??? When call-clobbered, the value is stable modulo the restore
301 that must happen after a call. This currently screws up
302 local-alloc into believing that the restore is not needed, so we
303 must return 0 only if we are called from alias analysis. */
304 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
309 /* The operand 0 of a LO_SUM is considered constant
310 (in fact it is related specifically to operand 1)
311 during alias analysis. */
312 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
313 || rtx_varies_p (XEXP (x
, 1), for_alias
);
316 if (MEM_VOLATILE_P (x
))
325 fmt
= GET_RTX_FORMAT (code
);
326 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
329 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
332 else if (fmt
[i
] == 'E')
335 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
336 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
343 /* Compute an approximation for the offset between the register
344 FROM and TO for the current function, as it was at the start
348 get_initial_register_offset (int from
, int to
)
350 static const struct elim_table_t
354 } table
[] = ELIMINABLE_REGS
;
355 poly_int64 offset1
, offset2
;
361 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
362 before the reload pass. We need to give at least
363 an estimation for the resulting frame size. */
364 if (! reload_completed
)
366 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
367 #if !STACK_GROWS_DOWNWARD
370 if (to
== STACK_POINTER_REGNUM
)
372 else if (from
== STACK_POINTER_REGNUM
)
378 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
379 if (table
[i
].from
== from
)
381 if (table
[i
].to
== to
)
383 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
387 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
389 if (table
[j
].to
== to
390 && table
[j
].from
== table
[i
].to
)
392 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
394 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
396 return offset1
+ offset2
;
398 if (table
[j
].from
== to
399 && table
[j
].to
== table
[i
].to
)
401 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
403 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
405 return offset1
- offset2
;
409 else if (table
[i
].to
== from
)
411 if (table
[i
].from
== to
)
413 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
417 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
419 if (table
[j
].to
== to
420 && table
[j
].from
== table
[i
].from
)
422 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
424 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
426 return - offset1
+ offset2
;
428 if (table
[j
].from
== to
429 && table
[j
].to
== table
[i
].from
)
431 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
433 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
435 return - offset1
- offset2
;
440 /* If the requested register combination was not found,
441 try a different more simple combination. */
442 if (from
== ARG_POINTER_REGNUM
)
443 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
444 else if (to
== ARG_POINTER_REGNUM
)
445 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
446 else if (from
== HARD_FRAME_POINTER_REGNUM
)
447 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
448 else if (to
== HARD_FRAME_POINTER_REGNUM
)
449 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
454 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
455 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
456 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
457 references on strict alignment machines. */
460 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
461 machine_mode mode
, bool unaligned_mems
)
463 enum rtx_code code
= GET_CODE (x
);
464 gcc_checking_assert (mode
== BLKmode
|| known_size_p (size
));
466 /* The offset must be a multiple of the mode size if we are considering
467 unaligned memory references on strict alignment machines. */
468 if (STRICT_ALIGNMENT
&& unaligned_mems
&& mode
!= BLKmode
)
470 poly_int64 actual_offset
= offset
;
472 #ifdef SPARC_STACK_BOUNDARY_HACK
473 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
474 the real alignment of %sp. However, when it does this, the
475 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
476 if (SPARC_STACK_BOUNDARY_HACK
477 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
478 actual_offset
-= STACK_POINTER_OFFSET
;
481 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
488 if (SYMBOL_REF_WEAK (x
))
490 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
493 poly_int64 decl_size
;
495 if (maybe_lt (offset
, 0))
497 if (!known_size_p (size
))
498 return maybe_ne (offset
, 0);
500 /* If the size of the access or of the symbol is unknown,
502 decl
= SYMBOL_REF_DECL (x
);
504 /* Else check that the access is in bounds. TODO: restructure
505 expr_size/tree_expr_size/int_expr_size and just use the latter. */
508 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
510 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
513 else if (TREE_CODE (decl
) == STRING_CST
)
514 decl_size
= TREE_STRING_LENGTH (decl
);
515 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
516 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
520 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
521 ? maybe_ne (offset
, 0)
522 : maybe_gt (offset
+ size
, decl_size
));
531 /* Stack references are assumed not to trap, but we need to deal with
532 nonsensical offsets. */
533 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
534 || x
== stack_pointer_rtx
535 /* The arg pointer varies if it is not a fixed register. */
536 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
539 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
541 poly_int64 red_zone_size
= 0;
543 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
544 poly_int64 low_bound
, high_bound
;
546 if (!known_size_p (size
))
549 if (x
== frame_pointer_rtx
)
551 if (FRAME_GROWS_DOWNWARD
)
553 high_bound
= targetm
.starting_frame_offset ();
554 low_bound
= high_bound
- get_frame_size ();
558 low_bound
= targetm
.starting_frame_offset ();
559 high_bound
= low_bound
+ get_frame_size ();
562 else if (x
== hard_frame_pointer_rtx
)
565 = get_initial_register_offset (STACK_POINTER_REGNUM
,
566 HARD_FRAME_POINTER_REGNUM
);
568 = get_initial_register_offset (ARG_POINTER_REGNUM
,
569 HARD_FRAME_POINTER_REGNUM
);
571 #if STACK_GROWS_DOWNWARD
572 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
573 high_bound
= ap_offset
574 + FIRST_PARM_OFFSET (current_function_decl
)
575 #if !ARGS_GROW_DOWNWARD
580 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
581 low_bound
= ap_offset
582 + FIRST_PARM_OFFSET (current_function_decl
)
583 #if ARGS_GROW_DOWNWARD
589 else if (x
== stack_pointer_rtx
)
592 = get_initial_register_offset (ARG_POINTER_REGNUM
,
593 STACK_POINTER_REGNUM
);
595 #if STACK_GROWS_DOWNWARD
596 low_bound
= - red_zone_size
- stack_boundary
;
597 high_bound
= ap_offset
598 + FIRST_PARM_OFFSET (current_function_decl
)
599 #if !ARGS_GROW_DOWNWARD
604 high_bound
= red_zone_size
+ stack_boundary
;
605 low_bound
= ap_offset
606 + FIRST_PARM_OFFSET (current_function_decl
)
607 #if ARGS_GROW_DOWNWARD
615 /* We assume that accesses are safe to at least the
617 Examples are varargs and __builtin_return_address. */
618 #if ARGS_GROW_DOWNWARD
619 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
621 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
622 - crtl
->args
.size
- stack_boundary
;
624 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
626 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
627 + crtl
->args
.size
+ stack_boundary
;
631 if (known_ge (offset
, low_bound
)
632 && known_le (offset
, high_bound
- size
))
636 /* All of the virtual frame registers are stack references. */
637 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
638 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
643 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
644 mode
, unaligned_mems
);
647 /* An address is assumed not to trap if:
648 - it is the pic register plus a const unspec without offset. */
649 if (XEXP (x
, 0) == pic_offset_table_rtx
650 && GET_CODE (XEXP (x
, 1)) == CONST
651 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
652 && known_eq (offset
, 0))
655 /* - or it is an address that can't trap plus a constant integer. */
656 if (CONST_INT_P (XEXP (x
, 1))
657 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
658 size
, mode
, unaligned_mems
))
665 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
666 mode
, unaligned_mems
);
673 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
674 mode
, unaligned_mems
);
680 /* If it isn't one of the case above, it can cause a trap. */
684 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
687 rtx_addr_can_trap_p (const_rtx x
)
689 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
692 /* Return true if X contains a MEM subrtx. */
695 contains_mem_rtx_p (rtx x
)
697 subrtx_iterator::array_type array
;
698 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
705 /* Return true if X is an address that is known to not be zero. */
708 nonzero_address_p (const_rtx x
)
710 const enum rtx_code code
= GET_CODE (x
);
715 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
721 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
722 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
723 || x
== stack_pointer_rtx
724 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
726 /* All of the virtual frame registers are stack references. */
727 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
728 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
733 return nonzero_address_p (XEXP (x
, 0));
736 /* Handle PIC references. */
737 if (XEXP (x
, 0) == pic_offset_table_rtx
738 && CONSTANT_P (XEXP (x
, 1)))
743 /* Similar to the above; allow positive offsets. Further, since
744 auto-inc is only allowed in memories, the register must be a
746 if (CONST_INT_P (XEXP (x
, 1))
747 && INTVAL (XEXP (x
, 1)) > 0)
749 return nonzero_address_p (XEXP (x
, 0));
752 /* Similarly. Further, the offset is always positive. */
759 return nonzero_address_p (XEXP (x
, 0));
762 return nonzero_address_p (XEXP (x
, 1));
768 /* If it isn't one of the case above, might be zero. */
772 /* Return 1 if X refers to a memory location whose address
773 cannot be compared reliably with constant addresses,
774 or if X refers to a BLKmode memory object.
775 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
776 zero, we are slightly more conservative. */
779 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
790 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
792 fmt
= GET_RTX_FORMAT (code
);
793 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
796 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
799 else if (fmt
[i
] == 'E')
802 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
803 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
809 /* Return the CALL in X if there is one. */
812 get_call_rtx_from (rtx x
)
816 if (GET_CODE (x
) == PARALLEL
)
817 x
= XVECEXP (x
, 0, 0);
818 if (GET_CODE (x
) == SET
)
820 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
825 /* Return the value of the integer term in X, if one is apparent;
827 Only obvious integer terms are detected.
828 This is used in cse.c with the `related_value' field. */
831 get_integer_term (const_rtx x
)
833 if (GET_CODE (x
) == CONST
)
836 if (GET_CODE (x
) == MINUS
837 && CONST_INT_P (XEXP (x
, 1)))
838 return - INTVAL (XEXP (x
, 1));
839 if (GET_CODE (x
) == PLUS
840 && CONST_INT_P (XEXP (x
, 1)))
841 return INTVAL (XEXP (x
, 1));
845 /* If X is a constant, return the value sans apparent integer term;
847 Only obvious integer terms are detected. */
850 get_related_value (const_rtx x
)
852 if (GET_CODE (x
) != CONST
)
855 if (GET_CODE (x
) == PLUS
856 && CONST_INT_P (XEXP (x
, 1)))
858 else if (GET_CODE (x
) == MINUS
859 && CONST_INT_P (XEXP (x
, 1)))
864 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
865 to somewhere in the same object or object_block as SYMBOL. */
868 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
872 if (GET_CODE (symbol
) != SYMBOL_REF
)
880 if (CONSTANT_POOL_ADDRESS_P (symbol
)
881 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
884 decl
= SYMBOL_REF_DECL (symbol
);
885 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
889 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
890 && SYMBOL_REF_BLOCK (symbol
)
891 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
892 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
893 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
899 /* Split X into a base and a constant offset, storing them in *BASE_OUT
900 and *OFFSET_OUT respectively. */
903 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
905 if (GET_CODE (x
) == CONST
)
908 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
910 *base_out
= XEXP (x
, 0);
911 *offset_out
= XEXP (x
, 1);
916 *offset_out
= const0_rtx
;
919 /* Express integer value X as some value Y plus a polynomial offset,
920 where Y is either const0_rtx, X or something within X (as opposed
921 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
924 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
926 rtx base
= const0_rtx
;
928 if (GET_CODE (test
) == CONST
)
929 test
= XEXP (test
, 0);
930 if (GET_CODE (test
) == PLUS
)
932 base
= XEXP (test
, 0);
933 test
= XEXP (test
, 1);
935 if (poly_int_rtx_p (test
, offset_out
))
941 /* Return the number of places FIND appears within X. If COUNT_DEST is
942 zero, we do not count occurrences inside the destination of a SET. */
945 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
949 const char *format_ptr
;
968 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
970 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
974 if (MEM_P (find
) && rtx_equal_p (x
, find
))
979 if (SET_DEST (x
) == find
&& ! count_dest
)
980 return count_occurrences (SET_SRC (x
), find
, count_dest
);
987 format_ptr
= GET_RTX_FORMAT (code
);
990 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
992 switch (*format_ptr
++)
995 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
999 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1000 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1008 /* Return TRUE if OP is a register or subreg of a register that
1009 holds an unsigned quantity. Otherwise, return FALSE. */
1012 unsigned_reg_p (rtx op
)
1016 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1019 if (GET_CODE (op
) == SUBREG
1020 && SUBREG_PROMOTED_SIGN (op
))
1027 /* Nonzero if register REG appears somewhere within IN.
1028 Also works if REG is not a register; in this case it checks
1029 for a subexpression of IN that is Lisp "equal" to REG. */
1032 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1044 if (GET_CODE (in
) == LABEL_REF
)
1045 return reg
== label_ref_label (in
);
1047 code
= GET_CODE (in
);
1051 /* Compare registers by number. */
1053 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1055 /* These codes have no constituent expressions
1063 /* These are kept unique for a given value. */
1070 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1073 fmt
= GET_RTX_FORMAT (code
);
1075 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1080 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1081 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1084 else if (fmt
[i
] == 'e'
1085 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1091 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1092 no CODE_LABEL insn. */
1095 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1100 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1106 /* Nonzero if register REG is used in an insn between
1107 FROM_INSN and TO_INSN (exclusive of those two). */
1110 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1111 const rtx_insn
*to_insn
)
1115 if (from_insn
== to_insn
)
1118 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1119 if (NONDEBUG_INSN_P (insn
)
1120 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1121 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1126 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1127 is entirely replaced by a new value and the only use is as a SET_DEST,
1128 we do not consider it a reference. */
1131 reg_referenced_p (const_rtx x
, const_rtx body
)
1135 switch (GET_CODE (body
))
1138 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1141 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1142 of a REG that occupies all of the REG, the insn references X if
1143 it is mentioned in the destination. */
1144 if (GET_CODE (SET_DEST (body
)) != CC0
1145 && GET_CODE (SET_DEST (body
)) != PC
1146 && !REG_P (SET_DEST (body
))
1147 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1148 && REG_P (SUBREG_REG (SET_DEST (body
)))
1149 && !read_modify_subreg_p (SET_DEST (body
)))
1150 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1155 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1156 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1163 return reg_overlap_mentioned_p (x
, body
);
1166 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1169 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1172 case UNSPEC_VOLATILE
:
1173 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1174 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1179 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1180 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1185 if (MEM_P (XEXP (body
, 0)))
1186 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1191 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1193 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1200 /* Nonzero if register REG is set or clobbered in an insn between
1201 FROM_INSN and TO_INSN (exclusive of those two). */
1204 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1205 const rtx_insn
*to_insn
)
1207 const rtx_insn
*insn
;
1209 if (from_insn
== to_insn
)
1212 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1213 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1218 /* Return true if REG is set or clobbered inside INSN. */
1221 reg_set_p (const_rtx reg
, const_rtx insn
)
1223 /* After delay slot handling, call and branch insns might be in a
1224 sequence. Check all the elements there. */
1225 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1227 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1228 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1234 /* We can be passed an insn or part of one. If we are passed an insn,
1235 check if a side-effect of the insn clobbers REG. */
1237 && (FIND_REG_INC_NOTE (insn
, reg
)
1240 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1241 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1242 GET_MODE (reg
), REGNO (reg
)))
1244 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1247 /* There are no REG_INC notes for SP autoinc. */
1248 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1250 subrtx_var_iterator::array_type array
;
1251 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1256 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1258 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1260 iter
.skip_subrtxes ();
1265 return set_of (reg
, insn
) != NULL_RTX
;
1268 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1269 only if none of them are modified between START and END. Return 1 if
1270 X contains a MEM; this routine does use memory aliasing. */
1273 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1275 const enum rtx_code code
= GET_CODE (x
);
1296 if (modified_between_p (XEXP (x
, 0), start
, end
))
1298 if (MEM_READONLY_P (x
))
1300 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1301 if (memory_modified_in_insn_p (x
, insn
))
1306 return reg_set_between_p (x
, start
, end
);
1312 fmt
= GET_RTX_FORMAT (code
);
1313 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1315 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1318 else if (fmt
[i
] == 'E')
1319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1320 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1327 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1328 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1329 does use memory aliasing. */
1332 modified_in_p (const_rtx x
, const_rtx insn
)
1334 const enum rtx_code code
= GET_CODE (x
);
1351 if (modified_in_p (XEXP (x
, 0), insn
))
1353 if (MEM_READONLY_P (x
))
1355 if (memory_modified_in_insn_p (x
, insn
))
1360 return reg_set_p (x
, insn
);
1366 fmt
= GET_RTX_FORMAT (code
);
1367 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1369 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1372 else if (fmt
[i
] == 'E')
1373 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1374 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1381 /* Return true if X is a SUBREG and if storing a value to X would
1382 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1383 target, using a SUBREG to store to one half of a DImode REG would
1384 preserve the other half. */
1387 read_modify_subreg_p (const_rtx x
)
1389 unsigned int isize
, osize
;
1390 if (GET_CODE (x
) != SUBREG
)
1392 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1393 osize
= GET_MODE_SIZE (GET_MODE (x
));
1394 return isize
> osize
1395 && isize
> REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1398 /* Helper function for set_of. */
1406 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1408 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1409 if (rtx_equal_p (x
, data
->pat
)
1410 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1414 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1415 (either directly or via STRICT_LOW_PART and similar modifiers). */
1417 set_of (const_rtx pat
, const_rtx insn
)
1419 struct set_of_data data
;
1420 data
.found
= NULL_RTX
;
1422 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1426 /* Add all hard register in X to *PSET. */
1428 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1430 subrtx_iterator::array_type array
;
1431 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1433 const_rtx x
= *iter
;
1434 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1435 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1439 /* This function, called through note_stores, collects sets and
1440 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1443 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1445 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1446 if (REG_P (x
) && HARD_REGISTER_P (x
))
1447 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1450 /* Examine INSN, and compute the set of hard registers written by it.
1451 Store it in *PSET. Should only be called after reload. */
1453 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1457 CLEAR_HARD_REG_SET (*pset
);
1458 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1462 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1464 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1465 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1467 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1468 if (REG_NOTE_KIND (link
) == REG_INC
)
1469 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1472 /* Like record_hard_reg_sets, but called through note_uses. */
1474 record_hard_reg_uses (rtx
*px
, void *data
)
1476 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1479 /* Given an INSN, return a SET expression if this insn has only a single SET.
1480 It may also have CLOBBERs, USEs, or SET whose output
1481 will not be used, which we ignore. */
1484 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1487 int set_verified
= 1;
1490 if (GET_CODE (pat
) == PARALLEL
)
1492 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1494 rtx sub
= XVECEXP (pat
, 0, i
);
1495 switch (GET_CODE (sub
))
1502 /* We can consider insns having multiple sets, where all
1503 but one are dead as single set insns. In common case
1504 only single set is present in the pattern so we want
1505 to avoid checking for REG_UNUSED notes unless necessary.
1507 When we reach set first time, we just expect this is
1508 the single set we are looking for and only when more
1509 sets are found in the insn, we check them. */
1512 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1513 && !side_effects_p (set
))
1519 set
= sub
, set_verified
= 0;
1520 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1521 || side_effects_p (sub
))
1533 /* Given an INSN, return nonzero if it has more than one SET, else return
1537 multiple_sets (const_rtx insn
)
1542 /* INSN must be an insn. */
1543 if (! INSN_P (insn
))
1546 /* Only a PARALLEL can have multiple SETs. */
1547 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1549 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1550 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1552 /* If we have already found a SET, then return now. */
1560 /* Either zero or one SET. */
1564 /* Return nonzero if the destination of SET equals the source
1565 and there are no side effects. */
1568 set_noop_p (const_rtx set
)
1570 rtx src
= SET_SRC (set
);
1571 rtx dst
= SET_DEST (set
);
1573 if (dst
== pc_rtx
&& src
== pc_rtx
)
1576 if (MEM_P (dst
) && MEM_P (src
))
1577 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1579 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1580 return rtx_equal_p (XEXP (dst
, 0), src
)
1581 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1582 && !side_effects_p (src
);
1584 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1585 dst
= XEXP (dst
, 0);
1587 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1589 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1591 src
= SUBREG_REG (src
);
1592 dst
= SUBREG_REG (dst
);
1595 /* It is a NOOP if destination overlaps with selected src vector
1597 if (GET_CODE (src
) == VEC_SELECT
1598 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1599 && HARD_REGISTER_P (XEXP (src
, 0))
1600 && HARD_REGISTER_P (dst
))
1603 rtx par
= XEXP (src
, 1);
1604 rtx src0
= XEXP (src
, 0);
1605 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1606 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1608 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1609 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1612 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1613 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1616 return (REG_P (src
) && REG_P (dst
)
1617 && REGNO (src
) == REGNO (dst
));
1620 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1624 noop_move_p (const rtx_insn
*insn
)
1626 rtx pat
= PATTERN (insn
);
1628 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1631 /* Insns carrying these notes are useful later on. */
1632 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1635 /* Check the code to be executed for COND_EXEC. */
1636 if (GET_CODE (pat
) == COND_EXEC
)
1637 pat
= COND_EXEC_CODE (pat
);
1639 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1642 if (GET_CODE (pat
) == PARALLEL
)
1645 /* If nothing but SETs of registers to themselves,
1646 this insn can also be deleted. */
1647 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1649 rtx tem
= XVECEXP (pat
, 0, i
);
1651 if (GET_CODE (tem
) == USE
1652 || GET_CODE (tem
) == CLOBBER
)
1655 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1665 /* Return nonzero if register in range [REGNO, ENDREGNO)
1666 appears either explicitly or implicitly in X
1667 other than being stored into.
1669 References contained within the substructure at LOC do not count.
1670 LOC may be zero, meaning don't ignore anything. */
1673 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1677 unsigned int x_regno
;
1682 /* The contents of a REG_NONNEG note is always zero, so we must come here
1683 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1687 code
= GET_CODE (x
);
1692 x_regno
= REGNO (x
);
1694 /* If we modifying the stack, frame, or argument pointer, it will
1695 clobber a virtual register. In fact, we could be more precise,
1696 but it isn't worth it. */
1697 if ((x_regno
== STACK_POINTER_REGNUM
1698 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1699 && x_regno
== ARG_POINTER_REGNUM
)
1700 || x_regno
== FRAME_POINTER_REGNUM
)
1701 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1704 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1707 /* If this is a SUBREG of a hard reg, we can see exactly which
1708 registers are being modified. Otherwise, handle normally. */
1709 if (REG_P (SUBREG_REG (x
))
1710 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1712 unsigned int inner_regno
= subreg_regno (x
);
1713 unsigned int inner_endregno
1714 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1715 ? subreg_nregs (x
) : 1);
1717 return endregno
> inner_regno
&& regno
< inner_endregno
;
1723 if (&SET_DEST (x
) != loc
1724 /* Note setting a SUBREG counts as referring to the REG it is in for
1725 a pseudo but not for hard registers since we can
1726 treat each word individually. */
1727 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1728 && loc
!= &SUBREG_REG (SET_DEST (x
))
1729 && REG_P (SUBREG_REG (SET_DEST (x
)))
1730 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1731 && refers_to_regno_p (regno
, endregno
,
1732 SUBREG_REG (SET_DEST (x
)), loc
))
1733 || (!REG_P (SET_DEST (x
))
1734 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1737 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1746 /* X does not match, so try its subexpressions. */
1748 fmt
= GET_RTX_FORMAT (code
);
1749 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1751 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1759 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1762 else if (fmt
[i
] == 'E')
1765 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1766 if (loc
!= &XVECEXP (x
, i
, j
)
1767 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1774 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1775 we check if any register number in X conflicts with the relevant register
1776 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1777 contains a MEM (we don't bother checking for memory addresses that can't
1778 conflict because we expect this to be a rare case. */
1781 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1783 unsigned int regno
, endregno
;
1785 /* If either argument is a constant, then modifying X can not
1786 affect IN. Here we look at IN, we can profitably combine
1787 CONSTANT_P (x) with the switch statement below. */
1788 if (CONSTANT_P (in
))
1792 switch (GET_CODE (x
))
1794 case STRICT_LOW_PART
:
1797 /* Overly conservative. */
1802 regno
= REGNO (SUBREG_REG (x
));
1803 if (regno
< FIRST_PSEUDO_REGISTER
)
1804 regno
= subreg_regno (x
);
1805 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1806 ? subreg_nregs (x
) : 1);
1811 endregno
= END_REGNO (x
);
1813 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1823 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1824 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1827 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1830 else if (fmt
[i
] == 'E')
1833 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1834 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1844 return reg_mentioned_p (x
, in
);
1850 /* If any register in here refers to it we return true. */
1851 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1852 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1853 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1859 gcc_assert (CONSTANT_P (x
));
1864 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1865 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1866 ignored by note_stores, but passed to FUN.
1868 FUN receives three arguments:
1869 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1870 2. the SET or CLOBBER rtx that does the store,
1871 3. the pointer DATA provided to note_stores.
1873 If the item being stored in or clobbered is a SUBREG of a hard register,
1874 the SUBREG will be passed. */
1877 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1881 if (GET_CODE (x
) == COND_EXEC
)
1882 x
= COND_EXEC_CODE (x
);
1884 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1886 rtx dest
= SET_DEST (x
);
1888 while ((GET_CODE (dest
) == SUBREG
1889 && (!REG_P (SUBREG_REG (dest
))
1890 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1891 || GET_CODE (dest
) == ZERO_EXTRACT
1892 || GET_CODE (dest
) == STRICT_LOW_PART
)
1893 dest
= XEXP (dest
, 0);
1895 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1896 each of whose first operand is a register. */
1897 if (GET_CODE (dest
) == PARALLEL
)
1899 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1900 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1901 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1904 (*fun
) (dest
, x
, data
);
1907 else if (GET_CODE (x
) == PARALLEL
)
1908 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1909 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1912 /* Like notes_stores, but call FUN for each expression that is being
1913 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1914 FUN for each expression, not any interior subexpressions. FUN receives a
1915 pointer to the expression and the DATA passed to this function.
1917 Note that this is not quite the same test as that done in reg_referenced_p
1918 since that considers something as being referenced if it is being
1919 partially set, while we do not. */
1922 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1927 switch (GET_CODE (body
))
1930 (*fun
) (&COND_EXEC_TEST (body
), data
);
1931 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1935 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1936 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1940 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1941 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1945 (*fun
) (&XEXP (body
, 0), data
);
1949 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1950 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1954 (*fun
) (&TRAP_CONDITION (body
), data
);
1958 (*fun
) (&XEXP (body
, 0), data
);
1962 case UNSPEC_VOLATILE
:
1963 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1964 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1968 if (MEM_P (XEXP (body
, 0)))
1969 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1974 rtx dest
= SET_DEST (body
);
1976 /* For sets we replace everything in source plus registers in memory
1977 expression in store and operands of a ZERO_EXTRACT. */
1978 (*fun
) (&SET_SRC (body
), data
);
1980 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1982 (*fun
) (&XEXP (dest
, 1), data
);
1983 (*fun
) (&XEXP (dest
, 2), data
);
1986 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1987 dest
= XEXP (dest
, 0);
1990 (*fun
) (&XEXP (dest
, 0), data
);
1995 /* All the other possibilities never store. */
1996 (*fun
) (pbody
, data
);
2001 /* Return nonzero if X's old contents don't survive after INSN.
2002 This will be true if X is (cc0) or if X is a register and
2003 X dies in INSN or because INSN entirely sets X.
2005 "Entirely set" means set directly and not through a SUBREG, or
2006 ZERO_EXTRACT, so no trace of the old contents remains.
2007 Likewise, REG_INC does not count.
2009 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2010 but for this use that makes no difference, since regs don't overlap
2011 during their lifetimes. Therefore, this function may be used
2012 at any time after deaths have been computed.
2014 If REG is a hard reg that occupies multiple machine registers, this
2015 function will only return 1 if each of those registers will be replaced
2019 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2021 unsigned int regno
, end_regno
;
2024 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2025 if (GET_CODE (x
) == CC0
)
2028 gcc_assert (REG_P (x
));
2031 end_regno
= END_REGNO (x
);
2032 for (i
= regno
; i
< end_regno
; i
++)
2033 if (! dead_or_set_regno_p (insn
, i
))
2039 /* Return TRUE iff DEST is a register or subreg of a register, is a
2040 complete rather than read-modify-write destination, and contains
2041 register TEST_REGNO. */
2044 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2046 unsigned int regno
, endregno
;
2048 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2049 dest
= SUBREG_REG (dest
);
2054 regno
= REGNO (dest
);
2055 endregno
= END_REGNO (dest
);
2056 return (test_regno
>= regno
&& test_regno
< endregno
);
2059 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2060 any member matches the covers_regno_no_parallel_p criteria. */
2063 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2065 if (GET_CODE (dest
) == PARALLEL
)
2067 /* Some targets place small structures in registers for return
2068 values of functions, and those registers are wrapped in
2069 PARALLELs that we may see as the destination of a SET. */
2072 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2074 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2075 if (inner
!= NULL_RTX
2076 && covers_regno_no_parallel_p (inner
, test_regno
))
2083 return covers_regno_no_parallel_p (dest
, test_regno
);
2086 /* Utility function for dead_or_set_p to check an individual register. */
2089 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2093 /* See if there is a death note for something that includes TEST_REGNO. */
2094 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2098 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2101 pattern
= PATTERN (insn
);
2103 /* If a COND_EXEC is not executed, the value survives. */
2104 if (GET_CODE (pattern
) == COND_EXEC
)
2107 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2108 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2109 else if (GET_CODE (pattern
) == PARALLEL
)
2113 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2115 rtx body
= XVECEXP (pattern
, 0, i
);
2117 if (GET_CODE (body
) == COND_EXEC
)
2118 body
= COND_EXEC_CODE (body
);
2120 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2121 && covers_regno_p (SET_DEST (body
), test_regno
))
2129 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2130 If DATUM is nonzero, look for one whose datum is DATUM. */
2133 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2137 gcc_checking_assert (insn
);
2139 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2140 if (! INSN_P (insn
))
2144 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2145 if (REG_NOTE_KIND (link
) == kind
)
2150 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2151 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2156 /* Return the reg-note of kind KIND in insn INSN which applies to register
2157 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2158 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2159 it might be the case that the note overlaps REGNO. */
2162 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2166 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2167 if (! INSN_P (insn
))
2170 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2171 if (REG_NOTE_KIND (link
) == kind
2172 /* Verify that it is a register, so that scratch and MEM won't cause a
2174 && REG_P (XEXP (link
, 0))
2175 && REGNO (XEXP (link
, 0)) <= regno
2176 && END_REGNO (XEXP (link
, 0)) > regno
)
2181 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2185 find_reg_equal_equiv_note (const_rtx insn
)
2192 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2193 if (REG_NOTE_KIND (link
) == REG_EQUAL
2194 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2196 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2197 insns that have multiple sets. Checking single_set to
2198 make sure of this is not the proper check, as explained
2199 in the comment in set_unique_reg_note.
2201 This should be changed into an assert. */
2202 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2209 /* Check whether INSN is a single_set whose source is known to be
2210 equivalent to a constant. Return that constant if so, otherwise
2214 find_constant_src (const rtx_insn
*insn
)
2218 set
= single_set (insn
);
2221 x
= avoid_constant_pool_reference (SET_SRC (set
));
2226 note
= find_reg_equal_equiv_note (insn
);
2227 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2228 return XEXP (note
, 0);
2233 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2234 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2237 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2239 /* If it's not a CALL_INSN, it can't possibly have a
2240 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2250 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2252 link
= XEXP (link
, 1))
2253 if (GET_CODE (XEXP (link
, 0)) == code
2254 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2259 unsigned int regno
= REGNO (datum
);
2261 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2262 to pseudo registers, so don't bother checking. */
2264 if (regno
< FIRST_PSEUDO_REGISTER
)
2266 unsigned int end_regno
= END_REGNO (datum
);
2269 for (i
= regno
; i
< end_regno
; i
++)
2270 if (find_regno_fusage (insn
, code
, i
))
2278 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2279 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2282 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2286 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2287 to pseudo registers, so don't bother checking. */
2289 if (regno
>= FIRST_PSEUDO_REGISTER
2293 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2297 if (GET_CODE (op
= XEXP (link
, 0)) == code
2298 && REG_P (reg
= XEXP (op
, 0))
2299 && REGNO (reg
) <= regno
2300 && END_REGNO (reg
) > regno
)
2308 /* Return true if KIND is an integer REG_NOTE. */
2311 int_reg_note_p (enum reg_note kind
)
2313 return kind
== REG_BR_PROB
;
2316 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2317 stored as the pointer to the next register note. */
2320 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2324 gcc_checking_assert (!int_reg_note_p (kind
));
2329 case REG_LABEL_TARGET
:
2330 case REG_LABEL_OPERAND
:
2332 /* These types of register notes use an INSN_LIST rather than an
2333 EXPR_LIST, so that copying is done right and dumps look
2335 note
= alloc_INSN_LIST (datum
, list
);
2336 PUT_REG_NOTE_KIND (note
, kind
);
2340 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2347 /* Add register note with kind KIND and datum DATUM to INSN. */
2350 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2352 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2355 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2358 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2360 gcc_checking_assert (int_reg_note_p (kind
));
2361 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2362 datum
, REG_NOTES (insn
));
2365 /* Add a register note like NOTE to INSN. */
2368 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2370 if (GET_CODE (note
) == INT_LIST
)
2371 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2373 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2376 /* Duplicate NOTE and return the copy. */
2378 duplicate_reg_note (rtx note
)
2380 reg_note kind
= REG_NOTE_KIND (note
);
2382 if (GET_CODE (note
) == INT_LIST
)
2383 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2384 else if (GET_CODE (note
) == EXPR_LIST
)
2385 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2387 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2390 /* Remove register note NOTE from the REG_NOTES of INSN. */
2393 remove_note (rtx_insn
*insn
, const_rtx note
)
2397 if (note
== NULL_RTX
)
2400 if (REG_NOTES (insn
) == note
)
2401 REG_NOTES (insn
) = XEXP (note
, 1);
2403 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2404 if (XEXP (link
, 1) == note
)
2406 XEXP (link
, 1) = XEXP (note
, 1);
2410 switch (REG_NOTE_KIND (note
))
2414 df_notes_rescan (insn
);
2421 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2422 Return true if any note has been removed. */
2425 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2430 loc
= ®_NOTES (insn
);
2433 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2434 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2436 *loc
= XEXP (*loc
, 1);
2440 loc
= &XEXP (*loc
, 1);
2445 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2448 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2455 /* This loop is a little tricky. We cannot just go down the chain because
2456 it is being modified by some actions in the loop. So we just iterate
2457 over the head. We plan to drain the list anyway. */
2458 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2460 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2461 rtx note
= find_reg_equal_equiv_note (insn
);
2463 /* This assert is generally triggered when someone deletes a REG_EQUAL
2464 or REG_EQUIV note by hacking the list manually rather than calling
2468 remove_note (insn
, note
);
2472 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2473 return 1 if it is found. A simple equality test is used to determine if
2477 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2481 for (x
= listp
; x
; x
= XEXP (x
, 1))
2482 if (node
== XEXP (x
, 0))
2488 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2489 remove that entry from the list if it is found.
2491 A simple equality test is used to determine if NODE matches. */
2494 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2496 rtx_expr_list
*temp
= *listp
;
2497 rtx_expr_list
*prev
= NULL
;
2501 if (node
== temp
->element ())
2503 /* Splice the node out of the list. */
2505 XEXP (prev
, 1) = temp
->next ();
2507 *listp
= temp
->next ();
2513 temp
= temp
->next ();
2517 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2518 remove that entry from the list if it is found.
2520 A simple equality test is used to determine if NODE matches. */
2523 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2525 rtx_insn_list
*temp
= *listp
;
2526 rtx_insn_list
*prev
= NULL
;
2530 if (node
== temp
->insn ())
2532 /* Splice the node out of the list. */
2534 XEXP (prev
, 1) = temp
->next ();
2536 *listp
= temp
->next ();
2542 temp
= temp
->next ();
2546 /* Nonzero if X contains any volatile instructions. These are instructions
2547 which may cause unpredictable machine state instructions, and thus no
2548 instructions or register uses should be moved or combined across them.
2549 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2552 volatile_insn_p (const_rtx x
)
2554 const RTX_CODE code
= GET_CODE (x
);
2572 case UNSPEC_VOLATILE
:
2577 if (MEM_VOLATILE_P (x
))
2584 /* Recursively scan the operands of this expression. */
2587 const char *const fmt
= GET_RTX_FORMAT (code
);
2590 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2594 if (volatile_insn_p (XEXP (x
, i
)))
2597 else if (fmt
[i
] == 'E')
2600 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2601 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2609 /* Nonzero if X contains any volatile memory references
2610 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2613 volatile_refs_p (const_rtx x
)
2615 const RTX_CODE code
= GET_CODE (x
);
2631 case UNSPEC_VOLATILE
:
2637 if (MEM_VOLATILE_P (x
))
2644 /* Recursively scan the operands of this expression. */
2647 const char *const fmt
= GET_RTX_FORMAT (code
);
2650 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2654 if (volatile_refs_p (XEXP (x
, i
)))
2657 else if (fmt
[i
] == 'E')
2660 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2661 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2669 /* Similar to above, except that it also rejects register pre- and post-
2673 side_effects_p (const_rtx x
)
2675 const RTX_CODE code
= GET_CODE (x
);
2692 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2693 when some combination can't be done. If we see one, don't think
2694 that we can simplify the expression. */
2695 return (GET_MODE (x
) != VOIDmode
);
2704 case UNSPEC_VOLATILE
:
2710 if (MEM_VOLATILE_P (x
))
2717 /* Recursively scan the operands of this expression. */
2720 const char *fmt
= GET_RTX_FORMAT (code
);
2723 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2727 if (side_effects_p (XEXP (x
, i
)))
2730 else if (fmt
[i
] == 'E')
2733 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2734 if (side_effects_p (XVECEXP (x
, i
, j
)))
2742 /* Return nonzero if evaluating rtx X might cause a trap.
2743 FLAGS controls how to consider MEMs. A nonzero means the context
2744 of the access may have changed from the original, such that the
2745 address may have become invalid. */
2748 may_trap_p_1 (const_rtx x
, unsigned flags
)
2754 /* We make no distinction currently, but this function is part of
2755 the internal target-hooks ABI so we keep the parameter as
2756 "unsigned flags". */
2757 bool code_changed
= flags
!= 0;
2761 code
= GET_CODE (x
);
2764 /* Handle these cases quickly. */
2776 return targetm
.unspec_may_trap_p (x
, flags
);
2778 case UNSPEC_VOLATILE
:
2784 return MEM_VOLATILE_P (x
);
2786 /* Memory ref can trap unless it's a static var or a stack slot. */
2788 /* Recognize specific pattern of stack checking probes. */
2789 if (flag_stack_check
2790 && MEM_VOLATILE_P (x
)
2791 && XEXP (x
, 0) == stack_pointer_rtx
)
2793 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2794 reference; moving it out of context such as when moving code
2795 when optimizing, might cause its address to become invalid. */
2797 || !MEM_NOTRAP_P (x
))
2799 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
2800 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2801 GET_MODE (x
), code_changed
);
2806 /* Division by a non-constant might trap. */
2811 if (HONOR_SNANS (x
))
2813 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2814 return flag_trapping_math
;
2815 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2820 /* An EXPR_LIST is used to represent a function call. This
2821 certainly may trap. */
2830 /* Some floating point comparisons may trap. */
2831 if (!flag_trapping_math
)
2833 /* ??? There is no machine independent way to check for tests that trap
2834 when COMPARE is used, though many targets do make this distinction.
2835 For instance, sparc uses CCFPE for compares which generate exceptions
2836 and CCFP for compares which do not generate exceptions. */
2839 /* But often the compare has some CC mode, so check operand
2841 if (HONOR_NANS (XEXP (x
, 0))
2842 || HONOR_NANS (XEXP (x
, 1)))
2848 if (HONOR_SNANS (x
))
2850 /* Often comparison is CC mode, so check operand modes. */
2851 if (HONOR_SNANS (XEXP (x
, 0))
2852 || HONOR_SNANS (XEXP (x
, 1)))
2857 /* Conversion of floating point might trap. */
2858 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2865 /* These operations don't trap even with floating point. */
2869 /* Any floating arithmetic may trap. */
2870 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2874 fmt
= GET_RTX_FORMAT (code
);
2875 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2879 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2882 else if (fmt
[i
] == 'E')
2885 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2886 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2893 /* Return nonzero if evaluating rtx X might cause a trap. */
2896 may_trap_p (const_rtx x
)
2898 return may_trap_p_1 (x
, 0);
2901 /* Same as above, but additionally return nonzero if evaluating rtx X might
2902 cause a fault. We define a fault for the purpose of this function as a
2903 erroneous execution condition that cannot be encountered during the normal
2904 execution of a valid program; the typical example is an unaligned memory
2905 access on a strict alignment machine. The compiler guarantees that it
2906 doesn't generate code that will fault from a valid program, but this
2907 guarantee doesn't mean anything for individual instructions. Consider
2908 the following example:
2910 struct S { int d; union { char *cp; int *ip; }; };
2912 int foo(struct S *s)
2920 on a strict alignment machine. In a valid program, foo will never be
2921 invoked on a structure for which d is equal to 1 and the underlying
2922 unique field of the union not aligned on a 4-byte boundary, but the
2923 expression *s->ip might cause a fault if considered individually.
2925 At the RTL level, potentially problematic expressions will almost always
2926 verify may_trap_p; for example, the above dereference can be emitted as
2927 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2928 However, suppose that foo is inlined in a caller that causes s->cp to
2929 point to a local character variable and guarantees that s->d is not set
2930 to 1; foo may have been effectively translated into pseudo-RTL as:
2933 (set (reg:SI) (mem:SI (%fp - 7)))
2935 (set (reg:QI) (mem:QI (%fp - 7)))
2937 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2938 memory reference to a stack slot, but it will certainly cause a fault
2939 on a strict alignment machine. */
2942 may_trap_or_fault_p (const_rtx x
)
2944 return may_trap_p_1 (x
, 1);
2947 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2948 i.e., an inequality. */
2951 inequality_comparisons_p (const_rtx x
)
2955 const enum rtx_code code
= GET_CODE (x
);
2983 len
= GET_RTX_LENGTH (code
);
2984 fmt
= GET_RTX_FORMAT (code
);
2986 for (i
= 0; i
< len
; i
++)
2990 if (inequality_comparisons_p (XEXP (x
, i
)))
2993 else if (fmt
[i
] == 'E')
2996 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2997 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
3005 /* Replace any occurrence of FROM in X with TO. The function does
3006 not enter into CONST_DOUBLE for the replace.
3008 Note that copying is not done so X must not be shared unless all copies
3011 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3012 those pointer-equal ones. */
3015 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3023 /* Allow this function to make replacements in EXPR_LISTs. */
3030 && REGNO (x
) == REGNO (from
))
3032 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3035 else if (GET_CODE (x
) == SUBREG
)
3037 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3039 if (CONST_INT_P (new_rtx
))
3041 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3042 GET_MODE (SUBREG_REG (x
)),
3047 SUBREG_REG (x
) = new_rtx
;
3051 else if (GET_CODE (x
) == ZERO_EXTEND
)
3053 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3055 if (CONST_INT_P (new_rtx
))
3057 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3058 new_rtx
, GET_MODE (XEXP (x
, 0)));
3062 XEXP (x
, 0) = new_rtx
;
3067 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3068 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3071 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3072 else if (fmt
[i
] == 'E')
3073 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3074 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3075 from
, to
, all_regs
);
3081 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3082 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3085 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3087 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3089 if (JUMP_TABLE_DATA_P (x
))
3092 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3093 int len
= GET_NUM_ELEM (vec
);
3094 for (int i
= 0; i
< len
; ++i
)
3096 rtx ref
= RTVEC_ELT (vec
, i
);
3097 if (XEXP (ref
, 0) == old_label
)
3099 XEXP (ref
, 0) = new_label
;
3100 if (update_label_nuses
)
3102 ++LABEL_NUSES (new_label
);
3103 --LABEL_NUSES (old_label
);
3110 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3111 field. This is not handled by the iterator because it doesn't
3112 handle unprinted ('0') fields. */
3113 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3114 JUMP_LABEL (x
) = new_label
;
3116 subrtx_ptr_iterator::array_type array
;
3117 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3122 if (GET_CODE (x
) == SYMBOL_REF
3123 && CONSTANT_POOL_ADDRESS_P (x
))
3125 rtx c
= get_pool_constant (x
);
3126 if (rtx_referenced_p (old_label
, c
))
3128 /* Create a copy of constant C; replace the label inside
3129 but do not update LABEL_NUSES because uses in constant pool
3131 rtx new_c
= copy_rtx (c
);
3132 replace_label (&new_c
, old_label
, new_label
, false);
3134 /* Add the new constant NEW_C to constant pool and replace
3135 the old reference to constant by new reference. */
3136 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3137 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3141 if ((GET_CODE (x
) == LABEL_REF
3142 || GET_CODE (x
) == INSN_LIST
)
3143 && XEXP (x
, 0) == old_label
)
3145 XEXP (x
, 0) = new_label
;
3146 if (update_label_nuses
)
3148 ++LABEL_NUSES (new_label
);
3149 --LABEL_NUSES (old_label
);
3157 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3158 rtx_insn
*new_label
, bool update_label_nuses
)
3160 rtx insn_as_rtx
= insn
;
3161 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3162 gcc_checking_assert (insn_as_rtx
== insn
);
3165 /* Return true if X is referenced in BODY. */
3168 rtx_referenced_p (const_rtx x
, const_rtx body
)
3170 subrtx_iterator::array_type array
;
3171 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3172 if (const_rtx y
= *iter
)
3174 /* Check if a label_ref Y refers to label X. */
3175 if (GET_CODE (y
) == LABEL_REF
3177 && label_ref_label (y
) == x
)
3180 if (rtx_equal_p (x
, y
))
3183 /* If Y is a reference to pool constant traverse the constant. */
3184 if (GET_CODE (y
) == SYMBOL_REF
3185 && CONSTANT_POOL_ADDRESS_P (y
))
3186 iter
.substitute (get_pool_constant (y
));
3191 /* If INSN is a tablejump return true and store the label (before jump table) to
3192 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3195 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3196 rtx_jump_table_data
**tablep
)
3201 rtx target
= JUMP_LABEL (insn
);
3202 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3205 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3206 rtx_insn
*table
= next_insn (label
);
3207 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3213 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3217 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3218 constant that is not in the constant pool and not in the condition
3219 of an IF_THEN_ELSE. */
3222 computed_jump_p_1 (const_rtx x
)
3224 const enum rtx_code code
= GET_CODE (x
);
3241 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3242 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3245 return (computed_jump_p_1 (XEXP (x
, 1))
3246 || computed_jump_p_1 (XEXP (x
, 2)));
3252 fmt
= GET_RTX_FORMAT (code
);
3253 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3256 && computed_jump_p_1 (XEXP (x
, i
)))
3259 else if (fmt
[i
] == 'E')
3260 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3261 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3268 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3270 Tablejumps and casesi insns are not considered indirect jumps;
3271 we can recognize them by a (use (label_ref)). */
3274 computed_jump_p (const rtx_insn
*insn
)
3279 rtx pat
= PATTERN (insn
);
3281 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3282 if (JUMP_LABEL (insn
) != NULL
)
3285 if (GET_CODE (pat
) == PARALLEL
)
3287 int len
= XVECLEN (pat
, 0);
3288 int has_use_labelref
= 0;
3290 for (i
= len
- 1; i
>= 0; i
--)
3291 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3292 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3295 has_use_labelref
= 1;
3299 if (! has_use_labelref
)
3300 for (i
= len
- 1; i
>= 0; i
--)
3301 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3302 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3303 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3306 else if (GET_CODE (pat
) == SET
3307 && SET_DEST (pat
) == pc_rtx
3308 && computed_jump_p_1 (SET_SRC (pat
)))
3316 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3317 the equivalent add insn and pass the result to FN, using DATA as the
3321 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3323 rtx x
= XEXP (mem
, 0);
3324 switch (GET_CODE (x
))
3329 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3330 rtx r1
= XEXP (x
, 0);
3331 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3332 return fn (mem
, x
, r1
, r1
, c
, data
);
3338 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3339 rtx r1
= XEXP (x
, 0);
3340 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3341 return fn (mem
, x
, r1
, r1
, c
, data
);
3347 rtx r1
= XEXP (x
, 0);
3348 rtx add
= XEXP (x
, 1);
3349 return fn (mem
, x
, r1
, add
, NULL
, data
);
3357 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3358 For each such autoinc operation found, call FN, passing it
3359 the innermost enclosing MEM, the operation itself, the RTX modified
3360 by the operation, two RTXs (the second may be NULL) that, once
3361 added, represent the value to be held by the modified RTX
3362 afterwards, and DATA. FN is to return 0 to continue the
3363 traversal or any other value to have it returned to the caller of
3364 for_each_inc_dec. */
3367 for_each_inc_dec (rtx x
,
3368 for_each_inc_dec_fn fn
,
3371 subrtx_var_iterator::array_type array
;
3372 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3377 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3379 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3382 iter
.skip_subrtxes ();
3389 /* Searches X for any reference to REGNO, returning the rtx of the
3390 reference found if any. Otherwise, returns NULL_RTX. */
3393 regno_use_in (unsigned int regno
, rtx x
)
3399 if (REG_P (x
) && REGNO (x
) == regno
)
3402 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3403 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3407 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3410 else if (fmt
[i
] == 'E')
3411 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3412 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3419 /* Return a value indicating whether OP, an operand of a commutative
3420 operation, is preferred as the first or second operand. The more
3421 positive the value, the stronger the preference for being the first
3425 commutative_operand_precedence (rtx op
)
3427 enum rtx_code code
= GET_CODE (op
);
3429 /* Constants always become the second operand. Prefer "nice" constants. */
3430 if (code
== CONST_INT
)
3432 if (code
== CONST_WIDE_INT
)
3434 if (code
== CONST_POLY_INT
)
3436 if (code
== CONST_DOUBLE
)
3438 if (code
== CONST_FIXED
)
3440 op
= avoid_constant_pool_reference (op
);
3441 code
= GET_CODE (op
);
3443 switch (GET_RTX_CLASS (code
))
3446 if (code
== CONST_INT
)
3448 if (code
== CONST_WIDE_INT
)
3450 if (code
== CONST_POLY_INT
)
3452 if (code
== CONST_DOUBLE
)
3454 if (code
== CONST_FIXED
)
3459 /* SUBREGs of objects should come second. */
3460 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3465 /* Complex expressions should be the first, so decrease priority
3466 of objects. Prefer pointer objects over non pointer objects. */
3467 if ((REG_P (op
) && REG_POINTER (op
))
3468 || (MEM_P (op
) && MEM_POINTER (op
)))
3472 case RTX_COMM_ARITH
:
3473 /* Prefer operands that are themselves commutative to be first.
3474 This helps to make things linear. In particular,
3475 (and (and (reg) (reg)) (not (reg))) is canonical. */
3479 /* If only one operand is a binary expression, it will be the first
3480 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3481 is canonical, although it will usually be further simplified. */
3485 /* Then prefer NEG and NOT. */
3486 if (code
== NEG
|| code
== NOT
)
3495 /* Return 1 iff it is necessary to swap operands of commutative operation
3496 in order to canonicalize expression. */
3499 swap_commutative_operands_p (rtx x
, rtx y
)
3501 return (commutative_operand_precedence (x
)
3502 < commutative_operand_precedence (y
));
3505 /* Return 1 if X is an autoincrement side effect and the register is
3506 not the stack pointer. */
3508 auto_inc_p (const_rtx x
)
3510 switch (GET_CODE (x
))
3518 /* There are no REG_INC notes for SP. */
3519 if (XEXP (x
, 0) != stack_pointer_rtx
)
3527 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3529 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3538 code
= GET_CODE (in
);
3539 fmt
= GET_RTX_FORMAT (code
);
3540 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3544 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3547 else if (fmt
[i
] == 'E')
3548 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3549 if (loc
== &XVECEXP (in
, i
, j
)
3550 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3556 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3557 and SUBREG_BYTE, return the bit offset where the subreg begins
3558 (counting from the least significant bit of the operand). */
3561 subreg_lsb_1 (machine_mode outer_mode
,
3562 machine_mode inner_mode
,
3563 poly_uint64 subreg_byte
)
3565 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3567 /* A paradoxical subreg begins at bit position 0. */
3568 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
3571 subreg_end
= subreg_byte
+ GET_MODE_SIZE (outer_mode
);
3572 trailing_bytes
= GET_MODE_SIZE (inner_mode
) - subreg_end
;
3573 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3574 byte_pos
= trailing_bytes
;
3575 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3576 byte_pos
= subreg_byte
;
3579 /* When bytes and words have opposite endianness, we must be able
3580 to split offsets into words and bytes at compile time. */
3581 poly_uint64 leading_word_part
3582 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3583 poly_uint64 trailing_word_part
3584 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3585 /* If the subreg crosses a word boundary ensure that
3586 it also begins and ends on a word boundary. */
3587 gcc_assert (known_le (subreg_end
- leading_word_part
,
3588 (unsigned int) UNITS_PER_WORD
)
3589 || (known_eq (leading_word_part
, subreg_byte
)
3590 && known_eq (trailing_word_part
, trailing_bytes
)));
3591 if (WORDS_BIG_ENDIAN
)
3592 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3594 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3597 return byte_pos
* BITS_PER_UNIT
;
3600 /* Given a subreg X, return the bit offset where the subreg begins
3601 (counting from the least significant bit of the reg). */
3604 subreg_lsb (const_rtx x
)
3606 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3610 /* Return the subreg byte offset for a subreg whose outer value has
3611 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3612 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3613 lsb of the inner value. This is the inverse of the calculation
3614 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3617 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3618 poly_uint64 lsb_shift
)
3620 /* A paradoxical subreg begins at bit position 0. */
3621 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3622 if (maybe_gt (outer_bytes
, inner_bytes
))
3624 gcc_checking_assert (known_eq (lsb_shift
, 0U));
3628 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
3629 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3630 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3632 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3636 /* When bytes and words have opposite endianness, we must be able
3637 to split offsets into words and bytes at compile time. */
3638 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
3640 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
3642 if (WORDS_BIG_ENDIAN
)
3643 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3645 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3649 /* Fill in information about a subreg of a hard register.
3650 xregno - A regno of an inner hard subreg_reg (or what will become one).
3651 xmode - The mode of xregno.
3652 offset - The byte offset.
3653 ymode - The mode of a top level SUBREG (or what may become one).
3654 info - Pointer to structure to fill in.
3656 Rather than considering one particular inner register (and thus one
3657 particular "outer" register) in isolation, this function really uses
3658 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3659 function does not check whether adding INFO->offset to XREGNO gives
3660 a valid hard register; even if INFO->offset + XREGNO is out of range,
3661 there might be another register of the same type that is in range.
3662 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
3663 the new register, since that can depend on things like whether the final
3664 register number is even or odd. Callers that want to check whether
3665 this particular subreg can be replaced by a simple (reg ...) should
3666 use simplify_subreg_regno. */
3669 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3670 poly_uint64 offset
, machine_mode ymode
,
3671 struct subreg_info
*info
)
3673 unsigned int nregs_xmode
, nregs_ymode
;
3675 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3677 unsigned int xsize
= GET_MODE_SIZE (xmode
);
3678 unsigned int ysize
= GET_MODE_SIZE (ymode
);
3679 bool rknown
= false;
3681 /* If the register representation of a non-scalar mode has holes in it,
3682 we expect the scalar units to be concatenated together, with the holes
3683 distributed evenly among the scalar units. Each scalar unit must occupy
3684 at least one register. */
3685 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3687 /* As a consequence, we must be dealing with a constant number of
3688 scalars, and thus a constant offset. */
3689 HOST_WIDE_INT coffset
= offset
.to_constant ();
3690 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3691 unsigned int nunits
= GET_MODE_NUNITS (xmode
);
3692 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
3693 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3694 gcc_assert (nregs_xmode
3696 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3697 gcc_assert (hard_regno_nregs (xregno
, xmode
)
3698 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
3700 /* You can only ask for a SUBREG of a value with holes in the middle
3701 if you don't cross the holes. (Such a SUBREG should be done by
3702 picking a different register class, or doing it in memory if
3703 necessary.) An example of a value with holes is XCmode on 32-bit
3704 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3705 3 for each part, but in memory it's two 128-bit parts.
3706 Padding is assumed to be at the end (not necessarily the 'high part')
3708 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3709 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
3710 != ((coffset
+ ysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3712 info
->representable_p
= false;
3717 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
3719 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
3721 /* Paradoxical subregs are otherwise valid. */
3722 if (!rknown
&& known_eq (offset
, 0U) && ysize
> xsize
)
3724 info
->representable_p
= true;
3725 /* If this is a big endian paradoxical subreg, which uses more
3726 actual hard registers than the original register, we must
3727 return a negative offset so that we find the proper highpart
3730 We assume that the ordering of registers within a multi-register
3731 value has a consistent endianness: if bytes and register words
3732 have different endianness, the hard registers that make up a
3733 multi-register value must be at least word-sized. */
3734 if (REG_WORDS_BIG_ENDIAN
)
3735 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3738 info
->nregs
= nregs_ymode
;
3742 /* If registers store different numbers of bits in the different
3743 modes, we cannot generally form this subreg. */
3744 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3745 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3746 && (xsize
% nregs_xmode
) == 0
3747 && (ysize
% nregs_ymode
) == 0)
3749 int regsize_xmode
= xsize
/ nregs_xmode
;
3750 int regsize_ymode
= ysize
/ nregs_ymode
;
3752 && ((nregs_ymode
> 1 && regsize_xmode
> regsize_ymode
)
3753 || (nregs_xmode
> 1 && regsize_ymode
> regsize_xmode
)))
3755 info
->representable_p
= false;
3756 info
->nregs
= CEIL (ysize
, regsize_xmode
);
3757 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3758 /* Checked by validate_subreg. We must know at compile time
3759 which inner registers are being accessed. */
3763 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3764 would go outside of XMODE. */
3765 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
3767 info
->representable_p
= false;
3768 info
->nregs
= nregs_ymode
;
3769 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3770 /* Checked by validate_subreg. We must know at compile time
3771 which inner registers are being accessed. */
3775 /* Quick exit for the simple and common case of extracting whole
3776 subregisters from a multiregister value. */
3777 /* ??? It would be better to integrate this into the code below,
3778 if we can generalize the concept enough and figure out how
3779 odd-sized modes can coexist with the other weird cases we support. */
3780 HOST_WIDE_INT count
;
3782 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3783 && regsize_xmode
== regsize_ymode
3784 && constant_multiple_p (offset
, regsize_ymode
, &count
))
3786 info
->representable_p
= true;
3787 info
->nregs
= nregs_ymode
;
3788 info
->offset
= count
;
3789 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3794 /* Lowpart subregs are otherwise valid. */
3795 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
3797 info
->representable_p
= true;
3800 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
3803 info
->nregs
= nregs_ymode
;
3808 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3809 values there are in (reg:XMODE XREGNO). We can view the register
3810 as consisting of this number of independent "blocks", where each
3811 block occupies NREGS_YMODE registers and contains exactly one
3812 representable YMODE value. */
3813 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3814 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3816 /* Calculate the number of bytes in each block. This must always
3817 be exact, otherwise we don't know how to verify the constraint.
3818 These conditions may be relaxed but subreg_regno_offset would
3819 need to be redesigned. */
3820 gcc_assert ((xsize
% num_blocks
) == 0);
3821 poly_uint64 bytes_per_block
= xsize
/ num_blocks
;
3823 /* Get the number of the first block that contains the subreg and the byte
3824 offset of the subreg from the start of that block. */
3825 unsigned int block_number
;
3826 poly_uint64 subblock_offset
;
3827 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
3829 /* Checked by validate_subreg. We must know at compile time which
3830 inner registers are being accessed. */
3835 /* Only the lowpart of each block is representable. */
3836 info
->representable_p
3837 = known_eq (subblock_offset
,
3838 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3842 /* We assume that the ordering of registers within a multi-register
3843 value has a consistent endianness: if bytes and register words
3844 have different endianness, the hard registers that make up a
3845 multi-register value must be at least word-sized. */
3846 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3847 /* The block number we calculated above followed memory endianness.
3848 Convert it to register endianness by counting back from the end.
3849 (Note that, because of the assumption above, each block must be
3850 at least word-sized.) */
3851 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3853 info
->offset
= block_number
* nregs_ymode
;
3854 info
->nregs
= nregs_ymode
;
3857 /* This function returns the regno offset of a subreg expression.
3858 xregno - A regno of an inner hard subreg_reg (or what will become one).
3859 xmode - The mode of xregno.
3860 offset - The byte offset.
3861 ymode - The mode of a top level SUBREG (or what may become one).
3862 RETURN - The regno offset which would be used. */
3864 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3865 poly_uint64 offset
, machine_mode ymode
)
3867 struct subreg_info info
;
3868 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3872 /* This function returns true when the offset is representable via
3873 subreg_offset in the given regno.
3874 xregno - A regno of an inner hard subreg_reg (or what will become one).
3875 xmode - The mode of xregno.
3876 offset - The byte offset.
3877 ymode - The mode of a top level SUBREG (or what may become one).
3878 RETURN - Whether the offset is representable. */
3880 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3881 poly_uint64 offset
, machine_mode ymode
)
3883 struct subreg_info info
;
3884 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3885 return info
.representable_p
;
3888 /* Return the number of a YMODE register to which
3890 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3892 can be simplified. Return -1 if the subreg can't be simplified.
3894 XREGNO is a hard register number. */
3897 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3898 poly_uint64 offset
, machine_mode ymode
)
3900 struct subreg_info info
;
3901 unsigned int yregno
;
3903 /* Give the backend a chance to disallow the mode change. */
3904 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3905 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3906 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3907 /* We can use mode change in LRA for some transformations. */
3908 && ! lra_in_progress
)
3911 /* We shouldn't simplify stack-related registers. */
3912 if ((!reload_completed
|| frame_pointer_needed
)
3913 && xregno
== FRAME_POINTER_REGNUM
)
3916 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3917 && xregno
== ARG_POINTER_REGNUM
)
3920 if (xregno
== STACK_POINTER_REGNUM
3921 /* We should convert hard stack register in LRA if it is
3923 && ! lra_in_progress
)
3926 /* Try to get the register offset. */
3927 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3928 if (!info
.representable_p
)
3931 /* Make sure that the offsetted register value is in range. */
3932 yregno
= xregno
+ info
.offset
;
3933 if (!HARD_REGISTER_NUM_P (yregno
))
3936 /* See whether (reg:YMODE YREGNO) is valid.
3938 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3939 This is a kludge to work around how complex FP arguments are passed
3940 on IA-64 and should be fixed. See PR target/49226. */
3941 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
3942 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
3945 return (int) yregno
;
3948 /* Return the final regno that a subreg expression refers to. */
3950 subreg_regno (const_rtx x
)
3953 rtx subreg
= SUBREG_REG (x
);
3954 int regno
= REGNO (subreg
);
3956 ret
= regno
+ subreg_regno_offset (regno
,
3964 /* Return the number of registers that a subreg expression refers
3967 subreg_nregs (const_rtx x
)
3969 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3972 /* Return the number of registers that a subreg REG with REGNO
3973 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3974 changed so that the regno can be passed in. */
3977 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3979 struct subreg_info info
;
3980 rtx subreg
= SUBREG_REG (x
);
3982 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3987 struct parms_set_data
3993 /* Helper function for noticing stores to parameter registers. */
3995 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3997 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3998 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3999 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4001 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4006 /* Look backward for first parameter to be loaded.
4007 Note that loads of all parameters will not necessarily be
4008 found if CSE has eliminated some of them (e.g., an argument
4009 to the outer function is passed down as a parameter).
4010 Do not skip BOUNDARY. */
4012 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4014 struct parms_set_data parm
;
4016 rtx_insn
*before
, *first_set
;
4018 /* Since different machines initialize their parameter registers
4019 in different orders, assume nothing. Collect the set of all
4020 parameter registers. */
4021 CLEAR_HARD_REG_SET (parm
.regs
);
4023 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4024 if (GET_CODE (XEXP (p
, 0)) == USE
4025 && REG_P (XEXP (XEXP (p
, 0), 0))
4026 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4028 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4030 /* We only care about registers which can hold function
4032 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4035 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4039 first_set
= call_insn
;
4041 /* Search backward for the first set of a register in this set. */
4042 while (parm
.nregs
&& before
!= boundary
)
4044 before
= PREV_INSN (before
);
4046 /* It is possible that some loads got CSEed from one call to
4047 another. Stop in that case. */
4048 if (CALL_P (before
))
4051 /* Our caller needs either ensure that we will find all sets
4052 (in case code has not been optimized yet), or take care
4053 for possible labels in a way by setting boundary to preceding
4055 if (LABEL_P (before
))
4057 gcc_assert (before
== boundary
);
4061 if (INSN_P (before
))
4063 int nregs_old
= parm
.nregs
;
4064 note_stores (PATTERN (before
), parms_set
, &parm
);
4065 /* If we found something that did not set a parameter reg,
4066 we're done. Do not keep going, as that might result
4067 in hoisting an insn before the setting of a pseudo
4068 that is used by the hoisted insn. */
4069 if (nregs_old
!= parm
.nregs
)
4078 /* Return true if we should avoid inserting code between INSN and preceding
4079 call instruction. */
4082 keep_with_call_p (const rtx_insn
*insn
)
4086 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4088 if (REG_P (SET_DEST (set
))
4089 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4090 && fixed_regs
[REGNO (SET_DEST (set
))]
4091 && general_operand (SET_SRC (set
), VOIDmode
))
4093 if (REG_P (SET_SRC (set
))
4094 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4095 && REG_P (SET_DEST (set
))
4096 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4098 /* There may be a stack pop just after the call and before the store
4099 of the return register. Search for the actual store when deciding
4100 if we can break or not. */
4101 if (SET_DEST (set
) == stack_pointer_rtx
)
4103 /* This CONST_CAST is okay because next_nonnote_insn just
4104 returns its argument and we assign it to a const_rtx
4107 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4108 if (i2
&& keep_with_call_p (i2
))
4115 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4116 to non-complex jumps. That is, direct unconditional, conditional,
4117 and tablejumps, but not computed jumps or returns. It also does
4118 not apply to the fallthru case of a conditional jump. */
4121 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4123 rtx tmp
= JUMP_LABEL (jump_insn
);
4124 rtx_jump_table_data
*table
;
4129 if (tablejump_p (jump_insn
, NULL
, &table
))
4131 rtvec vec
= table
->get_labels ();
4132 int i
, veclen
= GET_NUM_ELEM (vec
);
4134 for (i
= 0; i
< veclen
; ++i
)
4135 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4139 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4146 /* Return an estimate of the cost of computing rtx X.
4147 One use is in cse, to decide which expression to keep in the hash table.
4148 Another is in rtl generation, to pick the cheapest way to multiply.
4149 Other uses like the latter are expected in the future.
4151 X appears as operand OPNO in an expression with code OUTER_CODE.
4152 SPEED specifies whether costs optimized for speed or size should
4156 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4157 int opno
, bool speed
)
4168 if (GET_MODE (x
) != VOIDmode
)
4169 mode
= GET_MODE (x
);
4171 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4172 many insns, taking N times as long. */
4173 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4177 /* Compute the default costs of certain things.
4178 Note that targetm.rtx_costs can override the defaults. */
4180 code
= GET_CODE (x
);
4184 /* Multiplication has time-complexity O(N*N), where N is the
4185 number of units (translated from digits) when using
4186 schoolbook long multiplication. */
4187 total
= factor
* factor
* COSTS_N_INSNS (5);
4193 /* Similarly, complexity for schoolbook long division. */
4194 total
= factor
* factor
* COSTS_N_INSNS (7);
4197 /* Used in combine.c as a marker. */
4201 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4202 the mode for the factor. */
4203 mode
= GET_MODE (SET_DEST (x
));
4204 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4209 total
= factor
* COSTS_N_INSNS (1);
4219 /* If we can't tie these modes, make this expensive. The larger
4220 the mode, the more expensive it is. */
4221 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4222 return COSTS_N_INSNS (2 + factor
);
4226 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4233 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4238 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4239 which is already in total. */
4241 fmt
= GET_RTX_FORMAT (code
);
4242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4244 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4245 else if (fmt
[i
] == 'E')
4246 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4247 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4252 /* Fill in the structure C with information about both speed and size rtx
4253 costs for X, which is operand OPNO in an expression with code OUTER. */
4256 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4257 struct full_rtx_costs
*c
)
4259 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4260 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4264 /* Return cost of address expression X.
4265 Expect that X is properly formed address reference.
4267 SPEED parameter specify whether costs optimized for speed or size should
4271 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4273 /* We may be asked for cost of various unusual addresses, such as operands
4274 of push instruction. It is not worthwhile to complicate writing
4275 of the target hook by such cases. */
4277 if (!memory_address_addr_space_p (mode
, x
, as
))
4280 return targetm
.address_cost (x
, mode
, as
, speed
);
4283 /* If the target doesn't override, compute the cost as with arithmetic. */
4286 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4288 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4292 unsigned HOST_WIDE_INT
4293 nonzero_bits (const_rtx x
, machine_mode mode
)
4295 if (mode
== VOIDmode
)
4296 mode
= GET_MODE (x
);
4297 scalar_int_mode int_mode
;
4298 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4299 return GET_MODE_MASK (mode
);
4300 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4304 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4306 if (mode
== VOIDmode
)
4307 mode
= GET_MODE (x
);
4308 scalar_int_mode int_mode
;
4309 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4311 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4314 /* Return true if nonzero_bits1 might recurse into both operands
4318 nonzero_bits_binary_arith_p (const_rtx x
)
4320 if (!ARITHMETIC_P (x
))
4322 switch (GET_CODE (x
))
4344 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4345 It avoids exponential behavior in nonzero_bits1 when X has
4346 identical subexpressions on the first or the second level. */
4348 static unsigned HOST_WIDE_INT
4349 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4350 machine_mode known_mode
,
4351 unsigned HOST_WIDE_INT known_ret
)
4353 if (x
== known_x
&& mode
== known_mode
)
4356 /* Try to find identical subexpressions. If found call
4357 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4358 precomputed value for the subexpression as KNOWN_RET. */
4360 if (nonzero_bits_binary_arith_p (x
))
4362 rtx x0
= XEXP (x
, 0);
4363 rtx x1
= XEXP (x
, 1);
4365 /* Check the first level. */
4367 return nonzero_bits1 (x
, mode
, x0
, mode
,
4368 cached_nonzero_bits (x0
, mode
, known_x
,
4369 known_mode
, known_ret
));
4371 /* Check the second level. */
4372 if (nonzero_bits_binary_arith_p (x0
)
4373 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4374 return nonzero_bits1 (x
, mode
, x1
, mode
,
4375 cached_nonzero_bits (x1
, mode
, known_x
,
4376 known_mode
, known_ret
));
4378 if (nonzero_bits_binary_arith_p (x1
)
4379 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4380 return nonzero_bits1 (x
, mode
, x0
, mode
,
4381 cached_nonzero_bits (x0
, mode
, known_x
,
4382 known_mode
, known_ret
));
4385 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4388 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4389 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4390 is less useful. We can't allow both, because that results in exponential
4391 run time recursion. There is a nullstone testcase that triggered
4392 this. This macro avoids accidental uses of num_sign_bit_copies. */
4393 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4395 /* Given an expression, X, compute which bits in X can be nonzero.
4396 We don't care about bits outside of those defined in MODE.
4398 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4399 an arithmetic operation, we can do better. */
4401 static unsigned HOST_WIDE_INT
4402 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4403 machine_mode known_mode
,
4404 unsigned HOST_WIDE_INT known_ret
)
4406 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4407 unsigned HOST_WIDE_INT inner_nz
;
4409 machine_mode inner_mode
;
4410 scalar_int_mode xmode
;
4412 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4414 if (CONST_INT_P (x
))
4416 if (SHORT_IMMEDIATES_SIGN_EXTEND
4418 && mode_width
< BITS_PER_WORD
4419 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4420 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4425 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4427 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4429 /* If X is wider than MODE, use its mode instead. */
4430 if (xmode_width
> mode_width
)
4433 nonzero
= GET_MODE_MASK (mode
);
4434 mode_width
= xmode_width
;
4437 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4438 /* Our only callers in this case look for single bit values. So
4439 just return the mode mask. Those tests will then be false. */
4442 /* If MODE is wider than X, but both are a single word for both the host
4443 and target machines, we can compute this from which bits of the
4444 object might be nonzero in its own mode, taking into account the fact
4445 that on many CISC machines, accessing an object in a wider mode
4446 causes the high-order bits to become undefined. So they are
4447 not known to be zero. */
4449 if (!WORD_REGISTER_OPERATIONS
4450 && mode_width
> xmode_width
4451 && xmode_width
<= BITS_PER_WORD
4452 && xmode_width
<= HOST_BITS_PER_WIDE_INT
)
4454 nonzero
&= cached_nonzero_bits (x
, xmode
,
4455 known_x
, known_mode
, known_ret
);
4456 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4460 /* Please keep nonzero_bits_binary_arith_p above in sync with
4461 the code in the switch below. */
4462 code
= GET_CODE (x
);
4466 #if defined(POINTERS_EXTEND_UNSIGNED)
4467 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4468 all the bits above ptr_mode are known to be zero. */
4469 /* As we do not know which address space the pointer is referring to,
4470 we can do this only if the target does not support different pointer
4471 or address modes depending on the address space. */
4472 if (target_default_pointer_address_modes_p ()
4473 && POINTERS_EXTEND_UNSIGNED
4476 && !targetm
.have_ptr_extend ())
4477 nonzero
&= GET_MODE_MASK (ptr_mode
);
4480 /* Include declared information about alignment of pointers. */
4481 /* ??? We don't properly preserve REG_POINTER changes across
4482 pointer-to-integer casts, so we can't trust it except for
4483 things that we know must be pointers. See execute/960116-1.c. */
4484 if ((x
== stack_pointer_rtx
4485 || x
== frame_pointer_rtx
4486 || x
== arg_pointer_rtx
)
4487 && REGNO_POINTER_ALIGN (REGNO (x
)))
4489 unsigned HOST_WIDE_INT alignment
4490 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4492 #ifdef PUSH_ROUNDING
4493 /* If PUSH_ROUNDING is defined, it is possible for the
4494 stack to be momentarily aligned only to that amount,
4495 so we pick the least alignment. */
4496 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4497 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4501 nonzero
&= ~(alignment
- 1);
4505 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4506 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4510 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4511 known_mode
, known_ret
);
4513 return nonzero_for_hook
;
4517 /* In many, if not most, RISC machines, reading a byte from memory
4518 zeros the rest of the register. Noticing that fact saves a lot
4519 of extra zero-extends. */
4520 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4521 nonzero
&= GET_MODE_MASK (xmode
);
4525 case UNEQ
: case LTGT
:
4526 case GT
: case GTU
: case UNGT
:
4527 case LT
: case LTU
: case UNLT
:
4528 case GE
: case GEU
: case UNGE
:
4529 case LE
: case LEU
: case UNLE
:
4530 case UNORDERED
: case ORDERED
:
4531 /* If this produces an integer result, we know which bits are set.
4532 Code here used to clear bits outside the mode of X, but that is
4534 /* Mind that MODE is the mode the caller wants to look at this
4535 operation in, and not the actual operation mode. We can wind
4536 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4537 that describes the results of a vector compare. */
4538 if (GET_MODE_CLASS (xmode
) == MODE_INT
4539 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4540 nonzero
= STORE_FLAG_VALUE
;
4545 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4546 and num_sign_bit_copies. */
4547 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4551 if (xmode_width
< mode_width
)
4552 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4557 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4558 and num_sign_bit_copies. */
4559 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4565 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4566 known_x
, known_mode
, known_ret
)
4567 & GET_MODE_MASK (mode
));
4571 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4572 known_x
, known_mode
, known_ret
);
4573 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4574 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4578 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4579 Otherwise, show all the bits in the outer mode but not the inner
4581 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4582 known_x
, known_mode
, known_ret
);
4583 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4585 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4586 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4587 inner_nz
|= (GET_MODE_MASK (mode
)
4588 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4591 nonzero
&= inner_nz
;
4595 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4596 known_x
, known_mode
, known_ret
)
4597 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4598 known_x
, known_mode
, known_ret
);
4602 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4604 unsigned HOST_WIDE_INT nonzero0
4605 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4606 known_x
, known_mode
, known_ret
);
4608 /* Don't call nonzero_bits for the second time if it cannot change
4610 if ((nonzero
& nonzero0
) != nonzero
)
4612 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4613 known_x
, known_mode
, known_ret
);
4617 case PLUS
: case MINUS
:
4619 case DIV
: case UDIV
:
4620 case MOD
: case UMOD
:
4621 /* We can apply the rules of arithmetic to compute the number of
4622 high- and low-order zero bits of these operations. We start by
4623 computing the width (position of the highest-order nonzero bit)
4624 and the number of low-order zero bits for each value. */
4626 unsigned HOST_WIDE_INT nz0
4627 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4628 known_x
, known_mode
, known_ret
);
4629 unsigned HOST_WIDE_INT nz1
4630 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4631 known_x
, known_mode
, known_ret
);
4632 int sign_index
= xmode_width
- 1;
4633 int width0
= floor_log2 (nz0
) + 1;
4634 int width1
= floor_log2 (nz1
) + 1;
4635 int low0
= ctz_or_zero (nz0
);
4636 int low1
= ctz_or_zero (nz1
);
4637 unsigned HOST_WIDE_INT op0_maybe_minusp
4638 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4639 unsigned HOST_WIDE_INT op1_maybe_minusp
4640 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4641 unsigned int result_width
= mode_width
;
4647 result_width
= MAX (width0
, width1
) + 1;
4648 result_low
= MIN (low0
, low1
);
4651 result_low
= MIN (low0
, low1
);
4654 result_width
= width0
+ width1
;
4655 result_low
= low0
+ low1
;
4660 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4661 result_width
= width0
;
4666 result_width
= width0
;
4671 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4672 result_width
= MIN (width0
, width1
);
4673 result_low
= MIN (low0
, low1
);
4678 result_width
= MIN (width0
, width1
);
4679 result_low
= MIN (low0
, low1
);
4685 if (result_width
< mode_width
)
4686 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4689 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4694 if (CONST_INT_P (XEXP (x
, 1))
4695 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4696 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4700 /* If this is a SUBREG formed for a promoted variable that has
4701 been zero-extended, we know that at least the high-order bits
4702 are zero, though others might be too. */
4703 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4704 nonzero
= GET_MODE_MASK (xmode
)
4705 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
4706 known_x
, known_mode
, known_ret
);
4708 /* If the inner mode is a single word for both the host and target
4709 machines, we can compute this from which bits of the inner
4710 object might be nonzero. */
4711 inner_mode
= GET_MODE (SUBREG_REG (x
));
4712 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4713 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
)
4715 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4716 known_x
, known_mode
, known_ret
);
4718 /* On many CISC machines, accessing an object in a wider mode
4719 causes the high-order bits to become undefined. So they are
4720 not known to be zero. */
4722 if ((!WORD_REGISTER_OPERATIONS
4723 /* If this is a typical RISC machine, we only have to worry
4724 about the way loads are extended. */
4725 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4726 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4727 : extend_op
!= ZERO_EXTEND
)
4728 || (!MEM_P (SUBREG_REG (x
)) && !REG_P (SUBREG_REG (x
))))
4729 && xmode_width
> GET_MODE_PRECISION (inner_mode
))
4730 nonzero
|= (GET_MODE_MASK (xmode
) & ~GET_MODE_MASK (inner_mode
));
4738 /* The nonzero bits are in two classes: any bits within MODE
4739 that aren't in xmode are always significant. The rest of the
4740 nonzero bits are those that are significant in the operand of
4741 the shift when shifted the appropriate number of bits. This
4742 shows that high-order bits are cleared by the right shift and
4743 low-order bits by left shifts. */
4744 if (CONST_INT_P (XEXP (x
, 1))
4745 && INTVAL (XEXP (x
, 1)) >= 0
4746 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4747 && INTVAL (XEXP (x
, 1)) < xmode_width
)
4749 int count
= INTVAL (XEXP (x
, 1));
4750 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
4751 unsigned HOST_WIDE_INT op_nonzero
4752 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4753 known_x
, known_mode
, known_ret
);
4754 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4755 unsigned HOST_WIDE_INT outer
= 0;
4757 if (mode_width
> xmode_width
)
4758 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4760 if (code
== LSHIFTRT
)
4762 else if (code
== ASHIFTRT
)
4766 /* If the sign bit may have been nonzero before the shift, we
4767 need to mark all the places it could have been copied to
4768 by the shift as possibly nonzero. */
4769 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
4770 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
4771 << (xmode_width
- count
));
4773 else if (code
== ASHIFT
)
4776 inner
= ((inner
<< (count
% xmode_width
)
4777 | (inner
>> (xmode_width
- (count
% xmode_width
))))
4780 nonzero
&= (outer
| inner
);
4786 /* This is at most the number of bits in the mode. */
4787 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4791 /* If CLZ has a known value at zero, then the nonzero bits are
4792 that value, plus the number of bits in the mode minus one. */
4793 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4795 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4801 /* If CTZ has a known value at zero, then the nonzero bits are
4802 that value, plus the number of bits in the mode minus one. */
4803 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4805 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4811 /* This is at most the number of bits in the mode minus 1. */
4812 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4821 unsigned HOST_WIDE_INT nonzero_true
4822 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4823 known_x
, known_mode
, known_ret
);
4825 /* Don't call nonzero_bits for the second time if it cannot change
4827 if ((nonzero
& nonzero_true
) != nonzero
)
4828 nonzero
&= nonzero_true
4829 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4830 known_x
, known_mode
, known_ret
);
4841 /* See the macro definition above. */
4842 #undef cached_num_sign_bit_copies
4845 /* Return true if num_sign_bit_copies1 might recurse into both operands
4849 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4851 if (!ARITHMETIC_P (x
))
4853 switch (GET_CODE (x
))
4871 /* The function cached_num_sign_bit_copies is a wrapper around
4872 num_sign_bit_copies1. It avoids exponential behavior in
4873 num_sign_bit_copies1 when X has identical subexpressions on the
4874 first or the second level. */
4877 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
4878 const_rtx known_x
, machine_mode known_mode
,
4879 unsigned int known_ret
)
4881 if (x
== known_x
&& mode
== known_mode
)
4884 /* Try to find identical subexpressions. If found call
4885 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4886 the precomputed value for the subexpression as KNOWN_RET. */
4888 if (num_sign_bit_copies_binary_arith_p (x
))
4890 rtx x0
= XEXP (x
, 0);
4891 rtx x1
= XEXP (x
, 1);
4893 /* Check the first level. */
4896 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4897 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4901 /* Check the second level. */
4902 if (num_sign_bit_copies_binary_arith_p (x0
)
4903 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4905 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4906 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4910 if (num_sign_bit_copies_binary_arith_p (x1
)
4911 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4913 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4914 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4919 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4922 /* Return the number of bits at the high-order end of X that are known to
4923 be equal to the sign bit. X will be used in mode MODE. The returned
4924 value will always be between 1 and the number of bits in MODE. */
4927 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4928 machine_mode known_mode
,
4929 unsigned int known_ret
)
4931 enum rtx_code code
= GET_CODE (x
);
4932 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4933 int num0
, num1
, result
;
4934 unsigned HOST_WIDE_INT nonzero
;
4936 if (CONST_INT_P (x
))
4938 /* If the constant is negative, take its 1's complement and remask.
4939 Then see how many zero bits we have. */
4940 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4941 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4942 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
4943 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4945 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4948 scalar_int_mode xmode
, inner_mode
;
4949 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4952 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4954 /* For a smaller mode, just ignore the high bits. */
4955 if (bitwidth
< xmode_width
)
4957 num0
= cached_num_sign_bit_copies (x
, xmode
,
4958 known_x
, known_mode
, known_ret
);
4959 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
4962 if (bitwidth
> xmode_width
)
4964 /* If this machine does not do all register operations on the entire
4965 register and MODE is wider than the mode of X, we can say nothing
4966 at all about the high-order bits. */
4967 if (!WORD_REGISTER_OPERATIONS
)
4970 /* Likewise on machines that do, if the mode of the object is smaller
4971 than a word and loads of that size don't sign extend, we can say
4972 nothing about the high order bits. */
4973 if (xmode_width
< BITS_PER_WORD
4974 && load_extend_op (xmode
) != SIGN_EXTEND
)
4978 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4979 the code in the switch below. */
4984 #if defined(POINTERS_EXTEND_UNSIGNED)
4985 /* If pointers extend signed and this is a pointer in Pmode, say that
4986 all the bits above ptr_mode are known to be sign bit copies. */
4987 /* As we do not know which address space the pointer is referring to,
4988 we can do this only if the target does not support different pointer
4989 or address modes depending on the address space. */
4990 if (target_default_pointer_address_modes_p ()
4991 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
4992 && mode
== Pmode
&& REG_POINTER (x
)
4993 && !targetm
.have_ptr_extend ())
4994 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4998 unsigned int copies_for_hook
= 1, copies
= 1;
4999 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5003 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5004 known_mode
, known_ret
);
5006 if (copies
> 1 || copies_for_hook
> 1)
5007 return MAX (copies
, copies_for_hook
);
5009 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5014 /* Some RISC machines sign-extend all loads of smaller than a word. */
5015 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5016 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5020 /* If this is a SUBREG for a promoted object that is sign-extended
5021 and we are looking at it in a wider mode, we know that at least the
5022 high-order bits are known to be sign bit copies. */
5024 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5026 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5027 known_x
, known_mode
, known_ret
);
5028 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5031 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5033 /* For a smaller object, just ignore the high bits. */
5034 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5036 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5037 known_x
, known_mode
,
5039 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5043 /* For paradoxical SUBREGs on machines where all register operations
5044 affect the entire register, just look inside. Note that we are
5045 passing MODE to the recursive call, so the number of sign bit
5046 copies will remain relative to that mode, not the inner mode. */
5048 /* This works only if loads sign extend. Otherwise, if we get a
5049 reload for the inner part, it may be loaded from the stack, and
5050 then we lose all sign bit copies that existed before the store
5053 if (WORD_REGISTER_OPERATIONS
5054 && load_extend_op (inner_mode
) == SIGN_EXTEND
5055 && paradoxical_subreg_p (x
)
5056 && (MEM_P (SUBREG_REG (x
)) || REG_P (SUBREG_REG (x
))))
5057 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5058 known_x
, known_mode
, known_ret
);
5063 if (CONST_INT_P (XEXP (x
, 1)))
5064 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5068 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5069 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5070 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5071 known_x
, known_mode
, known_ret
));
5075 /* For a smaller object, just ignore the high bits. */
5076 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5077 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5078 known_x
, known_mode
, known_ret
);
5079 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5083 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5084 known_x
, known_mode
, known_ret
);
5086 case ROTATE
: case ROTATERT
:
5087 /* If we are rotating left by a number of bits less than the number
5088 of sign bit copies, we can just subtract that amount from the
5090 if (CONST_INT_P (XEXP (x
, 1))
5091 && INTVAL (XEXP (x
, 1)) >= 0
5092 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5094 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5095 known_x
, known_mode
, known_ret
);
5096 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5097 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5102 /* In general, this subtracts one sign bit copy. But if the value
5103 is known to be positive, the number of sign bit copies is the
5104 same as that of the input. Finally, if the input has just one bit
5105 that might be nonzero, all the bits are copies of the sign bit. */
5106 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5107 known_x
, known_mode
, known_ret
);
5108 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5109 return num0
> 1 ? num0
- 1 : 1;
5111 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5116 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5121 case IOR
: case AND
: case XOR
:
5122 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5123 /* Logical operations will preserve the number of sign-bit copies.
5124 MIN and MAX operations always return one of the operands. */
5125 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5126 known_x
, known_mode
, known_ret
);
5127 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5128 known_x
, known_mode
, known_ret
);
5130 /* If num1 is clearing some of the top bits then regardless of
5131 the other term, we are guaranteed to have at least that many
5132 high-order zero bits. */
5135 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5136 && CONST_INT_P (XEXP (x
, 1))
5137 && (UINTVAL (XEXP (x
, 1))
5138 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5141 /* Similarly for IOR when setting high-order bits. */
5144 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5145 && CONST_INT_P (XEXP (x
, 1))
5146 && (UINTVAL (XEXP (x
, 1))
5147 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5150 return MIN (num0
, num1
);
5152 case PLUS
: case MINUS
:
5153 /* For addition and subtraction, we can have a 1-bit carry. However,
5154 if we are subtracting 1 from a positive number, there will not
5155 be such a carry. Furthermore, if the positive number is known to
5156 be 0 or 1, we know the result is either -1 or 0. */
5158 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5159 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5161 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5162 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5163 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5164 : bitwidth
- floor_log2 (nonzero
) - 1);
5167 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5168 known_x
, known_mode
, known_ret
);
5169 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5170 known_x
, known_mode
, known_ret
);
5171 result
= MAX (1, MIN (num0
, num1
) - 1);
5176 /* The number of bits of the product is the sum of the number of
5177 bits of both terms. However, unless one of the terms if known
5178 to be positive, we must allow for an additional bit since negating
5179 a negative number can remove one sign bit copy. */
5181 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5182 known_x
, known_mode
, known_ret
);
5183 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5184 known_x
, known_mode
, known_ret
);
5186 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5188 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5189 || (((nonzero_bits (XEXP (x
, 0), mode
)
5190 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5191 && ((nonzero_bits (XEXP (x
, 1), mode
)
5192 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5196 return MAX (1, result
);
5199 /* The result must be <= the first operand. If the first operand
5200 has the high bit set, we know nothing about the number of sign
5202 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5204 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5205 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5208 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5209 known_x
, known_mode
, known_ret
);
5212 /* The result must be <= the second operand. If the second operand
5213 has (or just might have) the high bit set, we know nothing about
5214 the number of sign bit copies. */
5215 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5217 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5218 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5221 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5222 known_x
, known_mode
, known_ret
);
5225 /* Similar to unsigned division, except that we have to worry about
5226 the case where the divisor is negative, in which case we have
5228 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5229 known_x
, known_mode
, known_ret
);
5231 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5232 || (nonzero_bits (XEXP (x
, 1), mode
)
5233 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5239 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5240 known_x
, known_mode
, known_ret
);
5242 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5243 || (nonzero_bits (XEXP (x
, 1), mode
)
5244 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5250 /* Shifts by a constant add to the number of bits equal to the
5252 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5253 known_x
, known_mode
, known_ret
);
5254 if (CONST_INT_P (XEXP (x
, 1))
5255 && INTVAL (XEXP (x
, 1)) > 0
5256 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5257 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5262 /* Left shifts destroy copies. */
5263 if (!CONST_INT_P (XEXP (x
, 1))
5264 || INTVAL (XEXP (x
, 1)) < 0
5265 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5266 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5269 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5270 known_x
, known_mode
, known_ret
);
5271 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5274 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5275 known_x
, known_mode
, known_ret
);
5276 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5277 known_x
, known_mode
, known_ret
);
5278 return MIN (num0
, num1
);
5280 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5281 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5282 case GEU
: case GTU
: case LEU
: case LTU
:
5283 case UNORDERED
: case ORDERED
:
5284 /* If the constant is negative, take its 1's complement and remask.
5285 Then see how many zero bits we have. */
5286 nonzero
= STORE_FLAG_VALUE
;
5287 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5288 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5289 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5291 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5297 /* If we haven't been able to figure it out by one of the above rules,
5298 see if some of the high-order bits are known to be zero. If so,
5299 count those bits and return one less than that amount. If we can't
5300 safely compute the mask for this mode, always return BITWIDTH. */
5302 bitwidth
= GET_MODE_PRECISION (mode
);
5303 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5306 nonzero
= nonzero_bits (x
, mode
);
5307 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5308 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5311 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5312 zero indicates an instruction pattern without a known cost. */
5315 pattern_cost (rtx pat
, bool speed
)
5320 /* Extract the single set rtx from the instruction pattern. We
5321 can't use single_set since we only have the pattern. We also
5322 consider PARALLELs of a normal set and a single comparison. In
5323 that case we use the cost of the non-comparison SET operation,
5324 which is most-likely to be the real cost of this operation. */
5325 if (GET_CODE (pat
) == SET
)
5327 else if (GET_CODE (pat
) == PARALLEL
)
5330 rtx comparison
= NULL_RTX
;
5332 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5334 rtx x
= XVECEXP (pat
, 0, i
);
5335 if (GET_CODE (x
) == SET
)
5337 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5352 if (!set
&& comparison
)
5361 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5362 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5365 /* Calculate the cost of a single instruction. A return value of zero
5366 indicates an instruction pattern without a known cost. */
5369 insn_cost (rtx_insn
*insn
, bool speed
)
5371 if (targetm
.insn_cost
)
5372 return targetm
.insn_cost (insn
, speed
);
5374 return pattern_cost (PATTERN (insn
), speed
);
5377 /* Returns estimate on cost of computing SEQ. */
5380 seq_cost (const rtx_insn
*seq
, bool speed
)
5385 for (; seq
; seq
= NEXT_INSN (seq
))
5387 set
= single_set (seq
);
5389 cost
+= set_rtx_cost (set
, speed
);
5390 else if (NONDEBUG_INSN_P (seq
))
5392 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5403 /* Given an insn INSN and condition COND, return the condition in a
5404 canonical form to simplify testing by callers. Specifically:
5406 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5407 (2) Both operands will be machine operands; (cc0) will have been replaced.
5408 (3) If an operand is a constant, it will be the second operand.
5409 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5410 for GE, GEU, and LEU.
5412 If the condition cannot be understood, or is an inequality floating-point
5413 comparison which needs to be reversed, 0 will be returned.
5415 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5417 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5418 insn used in locating the condition was found. If a replacement test
5419 of the condition is desired, it should be placed in front of that
5420 insn and we will be sure that the inputs are still valid.
5422 If WANT_REG is nonzero, we wish the condition to be relative to that
5423 register, if possible. Therefore, do not canonicalize the condition
5424 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5425 to be a compare to a CC mode register.
5427 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5431 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5432 rtx_insn
**earliest
,
5433 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5436 rtx_insn
*prev
= insn
;
5440 int reverse_code
= 0;
5442 basic_block bb
= BLOCK_FOR_INSN (insn
);
5444 code
= GET_CODE (cond
);
5445 mode
= GET_MODE (cond
);
5446 op0
= XEXP (cond
, 0);
5447 op1
= XEXP (cond
, 1);
5450 code
= reversed_comparison_code (cond
, insn
);
5451 if (code
== UNKNOWN
)
5457 /* If we are comparing a register with zero, see if the register is set
5458 in the previous insn to a COMPARE or a comparison operation. Perform
5459 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5462 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5463 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5464 && op1
== CONST0_RTX (GET_MODE (op0
))
5467 /* Set nonzero when we find something of interest. */
5470 /* If comparison with cc0, import actual comparison from compare
5474 if ((prev
= prev_nonnote_insn (prev
)) == 0
5475 || !NONJUMP_INSN_P (prev
)
5476 || (set
= single_set (prev
)) == 0
5477 || SET_DEST (set
) != cc0_rtx
)
5480 op0
= SET_SRC (set
);
5481 op1
= CONST0_RTX (GET_MODE (op0
));
5486 /* If this is a COMPARE, pick up the two things being compared. */
5487 if (GET_CODE (op0
) == COMPARE
)
5489 op1
= XEXP (op0
, 1);
5490 op0
= XEXP (op0
, 0);
5493 else if (!REG_P (op0
))
5496 /* Go back to the previous insn. Stop if it is not an INSN. We also
5497 stop if it isn't a single set or if it has a REG_INC note because
5498 we don't want to bother dealing with it. */
5500 prev
= prev_nonnote_nondebug_insn (prev
);
5503 || !NONJUMP_INSN_P (prev
)
5504 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5505 /* In cfglayout mode, there do not have to be labels at the
5506 beginning of a block, or jumps at the end, so the previous
5507 conditions would not stop us when we reach bb boundary. */
5508 || BLOCK_FOR_INSN (prev
) != bb
)
5511 set
= set_of (op0
, prev
);
5514 && (GET_CODE (set
) != SET
5515 || !rtx_equal_p (SET_DEST (set
), op0
)))
5518 /* If this is setting OP0, get what it sets it to if it looks
5522 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5523 #ifdef FLOAT_STORE_FLAG_VALUE
5524 REAL_VALUE_TYPE fsfv
;
5527 /* ??? We may not combine comparisons done in a CCmode with
5528 comparisons not done in a CCmode. This is to aid targets
5529 like Alpha that have an IEEE compliant EQ instruction, and
5530 a non-IEEE compliant BEQ instruction. The use of CCmode is
5531 actually artificial, simply to prevent the combination, but
5532 should not affect other platforms.
5534 However, we must allow VOIDmode comparisons to match either
5535 CCmode or non-CCmode comparison, because some ports have
5536 modeless comparisons inside branch patterns.
5538 ??? This mode check should perhaps look more like the mode check
5539 in simplify_comparison in combine. */
5540 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5541 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5543 && inner_mode
!= VOIDmode
)
5545 if (GET_CODE (SET_SRC (set
)) == COMPARE
5548 && val_signbit_known_set_p (inner_mode
,
5550 #ifdef FLOAT_STORE_FLAG_VALUE
5552 && SCALAR_FLOAT_MODE_P (inner_mode
)
5553 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5554 REAL_VALUE_NEGATIVE (fsfv
)))
5557 && COMPARISON_P (SET_SRC (set
))))
5559 else if (((code
== EQ
5561 && val_signbit_known_set_p (inner_mode
,
5563 #ifdef FLOAT_STORE_FLAG_VALUE
5565 && SCALAR_FLOAT_MODE_P (inner_mode
)
5566 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5567 REAL_VALUE_NEGATIVE (fsfv
)))
5570 && COMPARISON_P (SET_SRC (set
)))
5575 else if ((code
== EQ
|| code
== NE
)
5576 && GET_CODE (SET_SRC (set
)) == XOR
)
5577 /* Handle sequences like:
5580 ...(eq|ne op0 (const_int 0))...
5584 (eq op0 (const_int 0)) reduces to (eq X Y)
5585 (ne op0 (const_int 0)) reduces to (ne X Y)
5587 This is the form used by MIPS16, for example. */
5593 else if (reg_set_p (op0
, prev
))
5594 /* If this sets OP0, but not directly, we have to give up. */
5599 /* If the caller is expecting the condition to be valid at INSN,
5600 make sure X doesn't change before INSN. */
5601 if (valid_at_insn_p
)
5602 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5604 if (COMPARISON_P (x
))
5605 code
= GET_CODE (x
);
5608 code
= reversed_comparison_code (x
, prev
);
5609 if (code
== UNKNOWN
)
5614 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5620 /* If constant is first, put it last. */
5621 if (CONSTANT_P (op0
))
5622 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5624 /* If OP0 is the result of a comparison, we weren't able to find what
5625 was really being compared, so fail. */
5627 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5630 /* Canonicalize any ordered comparison with integers involving equality
5631 if we can do computations in the relevant mode and we do not
5634 scalar_int_mode op0_mode
;
5635 if (CONST_INT_P (op1
)
5636 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
5637 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
5639 HOST_WIDE_INT const_val
= INTVAL (op1
);
5640 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5641 unsigned HOST_WIDE_INT max_val
5642 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
5647 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5648 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
5651 /* When cross-compiling, const_val might be sign-extended from
5652 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5654 if ((const_val
& max_val
)
5655 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
5656 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
5660 if (uconst_val
< max_val
)
5661 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
5665 if (uconst_val
!= 0)
5666 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
5674 /* Never return CC0; return zero instead. */
5678 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5681 /* Given a jump insn JUMP, return the condition that will cause it to branch
5682 to its JUMP_LABEL. If the condition cannot be understood, or is an
5683 inequality floating-point comparison which needs to be reversed, 0 will
5686 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5687 insn used in locating the condition was found. If a replacement test
5688 of the condition is desired, it should be placed in front of that
5689 insn and we will be sure that the inputs are still valid. If EARLIEST
5690 is null, the returned condition will be valid at INSN.
5692 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5693 compare CC mode register.
5695 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5698 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5699 int valid_at_insn_p
)
5705 /* If this is not a standard conditional jump, we can't parse it. */
5707 || ! any_condjump_p (jump
))
5709 set
= pc_set (jump
);
5711 cond
= XEXP (SET_SRC (set
), 0);
5713 /* If this branches to JUMP_LABEL when the condition is false, reverse
5716 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5717 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5719 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5720 allow_cc_mode
, valid_at_insn_p
);
5723 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5724 TARGET_MODE_REP_EXTENDED.
5726 Note that we assume that the property of
5727 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5728 narrower than mode B. I.e., if A is a mode narrower than B then in
5729 order to be able to operate on it in mode B, mode A needs to
5730 satisfy the requirements set by the representation of mode B. */
5733 init_num_sign_bit_copies_in_rep (void)
5735 opt_scalar_int_mode in_mode_iter
;
5736 scalar_int_mode mode
;
5738 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
5739 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
5741 scalar_int_mode in_mode
= in_mode_iter
.require ();
5744 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5745 extends to the next widest mode. */
5746 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5747 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
5749 /* We are in in_mode. Count how many bits outside of mode
5750 have to be copies of the sign-bit. */
5751 FOR_EACH_MODE (i
, mode
, in_mode
)
5753 /* This must always exist (for the last iteration it will be
5755 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
5757 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5758 /* We can only check sign-bit copies starting from the
5759 top-bit. In order to be able to check the bits we
5760 have already seen we pretend that subsequent bits
5761 have to be sign-bit copies too. */
5762 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5763 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5764 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5769 /* Suppose that truncation from the machine mode of X to MODE is not a
5770 no-op. See if there is anything special about X so that we can
5771 assume it already contains a truncated value of MODE. */
5774 truncated_to_mode (machine_mode mode
, const_rtx x
)
5776 /* This register has already been used in MODE without explicit
5778 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5781 /* See if we already satisfy the requirements of MODE. If yes we
5782 can just switch to MODE. */
5783 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5784 && (num_sign_bit_copies (x
, GET_MODE (x
))
5785 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5791 /* Return true if RTX code CODE has a single sequence of zero or more
5792 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5793 entry in that case. */
5796 setup_reg_subrtx_bounds (unsigned int code
)
5798 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5800 for (; format
[i
] != 'e'; ++i
)
5803 /* No subrtxes. Leave start and count as 0. */
5805 if (format
[i
] == 'E' || format
[i
] == 'V')
5809 /* Record the sequence of 'e's. */
5810 rtx_all_subrtx_bounds
[code
].start
= i
;
5813 while (format
[i
] == 'e');
5814 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5815 /* rtl-iter.h relies on this. */
5816 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5818 for (; format
[i
]; ++i
)
5819 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5825 /* Initialize rtx_all_subrtx_bounds. */
5830 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5832 if (!setup_reg_subrtx_bounds (i
))
5833 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5834 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5835 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5838 init_num_sign_bit_copies_in_rep ();
5841 /* Check whether this is a constant pool constant. */
5843 constant_pool_constant_p (rtx x
)
5845 x
= avoid_constant_pool_reference (x
);
5846 return CONST_DOUBLE_P (x
);
5849 /* If M is a bitmask that selects a field of low-order bits within an item but
5850 not the entire word, return the length of the field. Return -1 otherwise.
5851 M is used in machine mode MODE. */
5854 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5856 if (mode
!= VOIDmode
)
5858 if (!HWI_COMPUTABLE_MODE_P (mode
))
5860 m
&= GET_MODE_MASK (mode
);
5863 return exact_log2 (m
+ 1);
5866 /* Return the mode of MEM's address. */
5869 get_address_mode (rtx mem
)
5873 gcc_assert (MEM_P (mem
));
5874 mode
= GET_MODE (XEXP (mem
, 0));
5875 if (mode
!= VOIDmode
)
5876 return as_a
<scalar_int_mode
> (mode
);
5877 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5880 /* Split up a CONST_DOUBLE or integer constant rtx
5881 into two rtx's for single words,
5882 storing in *FIRST the word that comes first in memory in the target
5883 and in *SECOND the other.
5885 TODO: This function needs to be rewritten to work on any size
5889 split_double (rtx value
, rtx
*first
, rtx
*second
)
5891 if (CONST_INT_P (value
))
5893 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5895 /* In this case the CONST_INT holds both target words.
5896 Extract the bits from it into two word-sized pieces.
5897 Sign extend each half to HOST_WIDE_INT. */
5898 unsigned HOST_WIDE_INT low
, high
;
5899 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5900 unsigned bits_per_word
= BITS_PER_WORD
;
5902 /* Set sign_bit to the most significant bit of a word. */
5904 sign_bit
<<= bits_per_word
- 1;
5906 /* Set mask so that all bits of the word are set. We could
5907 have used 1 << BITS_PER_WORD instead of basing the
5908 calculation on sign_bit. However, on machines where
5909 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5910 compiler warning, even though the code would never be
5912 mask
= sign_bit
<< 1;
5915 /* Set sign_extend as any remaining bits. */
5916 sign_extend
= ~mask
;
5918 /* Pick the lower word and sign-extend it. */
5919 low
= INTVAL (value
);
5924 /* Pick the higher word, shifted to the least significant
5925 bits, and sign-extend it. */
5926 high
= INTVAL (value
);
5927 high
>>= bits_per_word
- 1;
5930 if (high
& sign_bit
)
5931 high
|= sign_extend
;
5933 /* Store the words in the target machine order. */
5934 if (WORDS_BIG_ENDIAN
)
5936 *first
= GEN_INT (high
);
5937 *second
= GEN_INT (low
);
5941 *first
= GEN_INT (low
);
5942 *second
= GEN_INT (high
);
5947 /* The rule for using CONST_INT for a wider mode
5948 is that we regard the value as signed.
5949 So sign-extend it. */
5950 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5951 if (WORDS_BIG_ENDIAN
)
5963 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5965 /* All of this is scary code and needs to be converted to
5966 properly work with any size integer. */
5967 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5968 if (WORDS_BIG_ENDIAN
)
5970 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5971 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5975 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5976 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5979 else if (!CONST_DOUBLE_P (value
))
5981 if (WORDS_BIG_ENDIAN
)
5983 *first
= const0_rtx
;
5989 *second
= const0_rtx
;
5992 else if (GET_MODE (value
) == VOIDmode
5993 /* This is the old way we did CONST_DOUBLE integers. */
5994 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5996 /* In an integer, the words are defined as most and least significant.
5997 So order them by the target's convention. */
5998 if (WORDS_BIG_ENDIAN
)
6000 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6001 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6005 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6006 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6013 /* Note, this converts the REAL_VALUE_TYPE to the target's
6014 format, splits up the floating point double and outputs
6015 exactly 32 bits of it into each of l[0] and l[1] --
6016 not necessarily BITS_PER_WORD bits. */
6017 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6019 /* If 32 bits is an entire word for the target, but not for the host,
6020 then sign-extend on the host so that the number will look the same
6021 way on the host that it would on the target. See for instance
6022 simplify_unary_operation. The #if is needed to avoid compiler
6025 #if HOST_BITS_PER_LONG > 32
6026 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6028 if (l
[0] & ((long) 1 << 31))
6029 l
[0] |= ((unsigned long) (-1) << 32);
6030 if (l
[1] & ((long) 1 << 31))
6031 l
[1] |= ((unsigned long) (-1) << 32);
6035 *first
= GEN_INT (l
[0]);
6036 *second
= GEN_INT (l
[1]);
6040 /* Return true if X is a sign_extract or zero_extract from the least
6044 lsb_bitfield_op_p (rtx x
)
6046 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6048 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6049 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6050 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6052 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
6057 /* Strip outer address "mutations" from LOC and return a pointer to the
6058 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6059 stripped expression there.
6061 "Mutations" either convert between modes or apply some kind of
6062 extension, truncation or alignment. */
6065 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6069 enum rtx_code code
= GET_CODE (*loc
);
6070 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6071 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6072 used to convert between pointer sizes. */
6073 loc
= &XEXP (*loc
, 0);
6074 else if (lsb_bitfield_op_p (*loc
))
6075 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6076 acts as a combined truncation and extension. */
6077 loc
= &XEXP (*loc
, 0);
6078 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6079 /* (and ... (const_int -X)) is used to align to X bytes. */
6080 loc
= &XEXP (*loc
, 0);
6081 else if (code
== SUBREG
6082 && !OBJECT_P (SUBREG_REG (*loc
))
6083 && subreg_lowpart_p (*loc
))
6084 /* (subreg (operator ...) ...) inside and is used for mode
6086 loc
= &SUBREG_REG (*loc
);
6094 /* Return true if CODE applies some kind of scale. The scaled value is
6095 is the first operand and the scale is the second. */
6098 binary_scale_code_p (enum rtx_code code
)
6100 return (code
== MULT
6102 /* Needed by ARM targets. */
6106 || code
== ROTATERT
);
6109 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6110 (see address_info). Return null otherwise. */
6113 get_base_term (rtx
*inner
)
6115 if (GET_CODE (*inner
) == LO_SUM
)
6116 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6119 || GET_CODE (*inner
) == SUBREG
6120 || GET_CODE (*inner
) == SCRATCH
)
6125 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6126 (see address_info). Return null otherwise. */
6129 get_index_term (rtx
*inner
)
6131 /* At present, only constant scales are allowed. */
6132 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6133 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6136 || GET_CODE (*inner
) == SUBREG
6137 || GET_CODE (*inner
) == SCRATCH
)
6142 /* Set the segment part of address INFO to LOC, given that INNER is the
6146 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6148 gcc_assert (!info
->segment
);
6149 info
->segment
= loc
;
6150 info
->segment_term
= inner
;
6153 /* Set the base part of address INFO to LOC, given that INNER is the
6157 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6159 gcc_assert (!info
->base
);
6161 info
->base_term
= inner
;
6164 /* Set the index part of address INFO to LOC, given that INNER is the
6168 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6170 gcc_assert (!info
->index
);
6172 info
->index_term
= inner
;
6175 /* Set the displacement part of address INFO to LOC, given that INNER
6176 is the constant term. */
6179 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6181 gcc_assert (!info
->disp
);
6183 info
->disp_term
= inner
;
6186 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6187 rest of INFO accordingly. */
6190 decompose_incdec_address (struct address_info
*info
)
6192 info
->autoinc_p
= true;
6194 rtx
*base
= &XEXP (*info
->inner
, 0);
6195 set_address_base (info
, base
, base
);
6196 gcc_checking_assert (info
->base
== info
->base_term
);
6198 /* These addresses are only valid when the size of the addressed
6200 gcc_checking_assert (info
->mode
!= VOIDmode
);
6203 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6204 of INFO accordingly. */
6207 decompose_automod_address (struct address_info
*info
)
6209 info
->autoinc_p
= true;
6211 rtx
*base
= &XEXP (*info
->inner
, 0);
6212 set_address_base (info
, base
, base
);
6213 gcc_checking_assert (info
->base
== info
->base_term
);
6215 rtx plus
= XEXP (*info
->inner
, 1);
6216 gcc_assert (GET_CODE (plus
) == PLUS
);
6218 info
->base_term2
= &XEXP (plus
, 0);
6219 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6221 rtx
*step
= &XEXP (plus
, 1);
6222 rtx
*inner_step
= strip_address_mutations (step
);
6223 if (CONSTANT_P (*inner_step
))
6224 set_address_disp (info
, step
, inner_step
);
6226 set_address_index (info
, step
, inner_step
);
6229 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6230 values in [PTR, END). Return a pointer to the end of the used array. */
6233 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6236 if (GET_CODE (x
) == PLUS
)
6238 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6239 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6243 gcc_assert (ptr
!= end
);
6249 /* Evaluate the likelihood of X being a base or index value, returning
6250 positive if it is likely to be a base, negative if it is likely to be
6251 an index, and 0 if we can't tell. Make the magnitude of the return
6252 value reflect the amount of confidence we have in the answer.
6254 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6257 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6258 enum rtx_code outer_code
, enum rtx_code index_code
)
6260 /* Believe *_POINTER unless the address shape requires otherwise. */
6261 if (REG_P (x
) && REG_POINTER (x
))
6263 if (MEM_P (x
) && MEM_POINTER (x
))
6266 if (REG_P (x
) && HARD_REGISTER_P (x
))
6268 /* X is a hard register. If it only fits one of the base
6269 or index classes, choose that interpretation. */
6270 int regno
= REGNO (x
);
6271 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6272 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6273 if (base_p
!= index_p
)
6274 return base_p
? 1 : -1;
6279 /* INFO->INNER describes a normal, non-automodified address.
6280 Fill in the rest of INFO accordingly. */
6283 decompose_normal_address (struct address_info
*info
)
6285 /* Treat the address as the sum of up to four values. */
6287 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6288 ops
+ ARRAY_SIZE (ops
)) - ops
;
6290 /* If there is more than one component, any base component is in a PLUS. */
6292 info
->base_outer_code
= PLUS
;
6294 /* Try to classify each sum operand now. Leave those that could be
6295 either a base or an index in OPS. */
6298 for (size_t in
= 0; in
< n_ops
; ++in
)
6301 rtx
*inner
= strip_address_mutations (loc
);
6302 if (CONSTANT_P (*inner
))
6303 set_address_disp (info
, loc
, inner
);
6304 else if (GET_CODE (*inner
) == UNSPEC
)
6305 set_address_segment (info
, loc
, inner
);
6308 /* The only other possibilities are a base or an index. */
6309 rtx
*base_term
= get_base_term (inner
);
6310 rtx
*index_term
= get_index_term (inner
);
6311 gcc_assert (base_term
|| index_term
);
6313 set_address_index (info
, loc
, index_term
);
6314 else if (!index_term
)
6315 set_address_base (info
, loc
, base_term
);
6318 gcc_assert (base_term
== index_term
);
6320 inner_ops
[out
] = base_term
;
6326 /* Classify the remaining OPS members as bases and indexes. */
6329 /* If we haven't seen a base or an index yet, assume that this is
6330 the base. If we were confident that another term was the base
6331 or index, treat the remaining operand as the other kind. */
6333 set_address_base (info
, ops
[0], inner_ops
[0]);
6335 set_address_index (info
, ops
[0], inner_ops
[0]);
6339 /* In the event of a tie, assume the base comes first. */
6340 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6342 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6343 GET_CODE (*ops
[0])))
6345 set_address_base (info
, ops
[0], inner_ops
[0]);
6346 set_address_index (info
, ops
[1], inner_ops
[1]);
6350 set_address_base (info
, ops
[1], inner_ops
[1]);
6351 set_address_index (info
, ops
[0], inner_ops
[0]);
6355 gcc_assert (out
== 0);
6358 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6359 or VOIDmode if not known. AS is the address space associated with LOC.
6360 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6363 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6364 addr_space_t as
, enum rtx_code outer_code
)
6366 memset (info
, 0, sizeof (*info
));
6369 info
->addr_outer_code
= outer_code
;
6371 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6372 info
->base_outer_code
= outer_code
;
6373 switch (GET_CODE (*info
->inner
))
6379 decompose_incdec_address (info
);
6384 decompose_automod_address (info
);
6388 decompose_normal_address (info
);
6393 /* Describe address operand LOC in INFO. */
6396 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6398 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6401 /* Describe the address of MEM X in INFO. */
6404 decompose_mem_address (struct address_info
*info
, rtx x
)
6406 gcc_assert (MEM_P (x
));
6407 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6408 MEM_ADDR_SPACE (x
), MEM
);
6411 /* Update INFO after a change to the address it describes. */
6414 update_address (struct address_info
*info
)
6416 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6417 info
->addr_outer_code
);
6420 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6421 more complicated than that. */
6424 get_index_scale (const struct address_info
*info
)
6426 rtx index
= *info
->index
;
6427 if (GET_CODE (index
) == MULT
6428 && CONST_INT_P (XEXP (index
, 1))
6429 && info
->index_term
== &XEXP (index
, 0))
6430 return INTVAL (XEXP (index
, 1));
6432 if (GET_CODE (index
) == ASHIFT
6433 && CONST_INT_P (XEXP (index
, 1))
6434 && info
->index_term
== &XEXP (index
, 0))
6435 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6437 if (info
->index
== info
->index_term
)
6443 /* Return the "index code" of INFO, in the form required by
6447 get_index_code (const struct address_info
*info
)
6450 return GET_CODE (*info
->index
);
6453 return GET_CODE (*info
->disp
);
6458 /* Return true if RTL X contains a SYMBOL_REF. */
6461 contains_symbol_ref_p (const_rtx x
)
6463 subrtx_iterator::array_type array
;
6464 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6465 if (SYMBOL_REF_P (*iter
))
6471 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6474 contains_symbolic_reference_p (const_rtx x
)
6476 subrtx_iterator::array_type array
;
6477 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6478 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6484 /* Return true if X contains a thread-local symbol. */
6487 tls_referenced_p (const_rtx x
)
6489 if (!targetm
.have_tls
)
6492 subrtx_iterator::array_type array
;
6493 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6494 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)