1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
77 (UNSPEC_ADDRESS_FIRST 100)
80 (GOT_VERSION_REGNUM 79)
82 ;; For MIPS Paired-Singled Floating Point Instructions.
84 (UNSPEC_MOVE_TF_PS 200)
87 ;; MIPS64/MIPS32R2 alnv.ps
90 ;; MIPS-3D instructions
94 (UNSPEC_CVT_PW_PS 205)
95 (UNSPEC_CVT_PS_PW 206)
103 (UNSPEC_SINGLE_CC 213)
106 ;; MIPS DSP ASE Revision 0.98 3/24/2005
114 (UNSPEC_RADDU_W_QB 307)
116 (UNSPEC_PRECRQ_QB_PH 309)
117 (UNSPEC_PRECRQ_PH_W 310)
118 (UNSPEC_PRECRQ_RS_PH_W 311)
119 (UNSPEC_PRECRQU_S_QB_PH 312)
120 (UNSPEC_PRECEQ_W_PHL 313)
121 (UNSPEC_PRECEQ_W_PHR 314)
122 (UNSPEC_PRECEQU_PH_QBL 315)
123 (UNSPEC_PRECEQU_PH_QBR 316)
124 (UNSPEC_PRECEQU_PH_QBLA 317)
125 (UNSPEC_PRECEQU_PH_QBRA 318)
126 (UNSPEC_PRECEU_PH_QBL 319)
127 (UNSPEC_PRECEU_PH_QBR 320)
128 (UNSPEC_PRECEU_PH_QBLA 321)
129 (UNSPEC_PRECEU_PH_QBRA 322)
135 (UNSPEC_MULEU_S_PH_QBL 328)
136 (UNSPEC_MULEU_S_PH_QBR 329)
137 (UNSPEC_MULQ_RS_PH 330)
138 (UNSPEC_MULEQ_S_W_PHL 331)
139 (UNSPEC_MULEQ_S_W_PHR 332)
140 (UNSPEC_DPAU_H_QBL 333)
141 (UNSPEC_DPAU_H_QBR 334)
142 (UNSPEC_DPSU_H_QBL 335)
143 (UNSPEC_DPSU_H_QBR 336)
144 (UNSPEC_DPAQ_S_W_PH 337)
145 (UNSPEC_DPSQ_S_W_PH 338)
146 (UNSPEC_MULSAQ_S_W_PH 339)
147 (UNSPEC_DPAQ_SA_L_W 340)
148 (UNSPEC_DPSQ_SA_L_W 341)
149 (UNSPEC_MAQ_S_W_PHL 342)
150 (UNSPEC_MAQ_S_W_PHR 343)
151 (UNSPEC_MAQ_SA_W_PHL 344)
152 (UNSPEC_MAQ_SA_W_PHR 345)
160 (UNSPEC_CMPGU_EQ_QB 353)
161 (UNSPEC_CMPGU_LT_QB 354)
162 (UNSPEC_CMPGU_LE_QB 355)
164 (UNSPEC_PACKRL_PH 357)
166 (UNSPEC_EXTR_R_W 359)
167 (UNSPEC_EXTR_RS_W 360)
168 (UNSPEC_EXTR_S_H 361)
176 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
177 (UNSPEC_ABSQ_S_QB 400)
179 (UNSPEC_ADDU_S_PH 402)
180 (UNSPEC_ADDUH_QB 403)
181 (UNSPEC_ADDUH_R_QB 404)
184 (UNSPEC_CMPGDU_EQ_QB 407)
185 (UNSPEC_CMPGDU_LT_QB 408)
186 (UNSPEC_CMPGDU_LE_QB 409)
187 (UNSPEC_DPA_W_PH 410)
188 (UNSPEC_DPS_W_PH 411)
194 (UNSPEC_MUL_S_PH 417)
195 (UNSPEC_MULQ_RS_W 418)
196 (UNSPEC_MULQ_S_PH 419)
197 (UNSPEC_MULQ_S_W 420)
198 (UNSPEC_MULSA_W_PH 421)
201 (UNSPEC_PRECR_QB_PH 424)
202 (UNSPEC_PRECR_SRA_PH_W 425)
203 (UNSPEC_PRECR_SRA_R_PH_W 426)
206 (UNSPEC_SHRA_R_QB 429)
209 (UNSPEC_SUBU_S_PH 432)
210 (UNSPEC_SUBUH_QB 433)
211 (UNSPEC_SUBUH_R_QB 434)
212 (UNSPEC_ADDQH_PH 435)
213 (UNSPEC_ADDQH_R_PH 436)
215 (UNSPEC_ADDQH_R_W 438)
216 (UNSPEC_SUBQH_PH 439)
217 (UNSPEC_SUBQH_R_PH 440)
219 (UNSPEC_SUBQH_R_W 442)
220 (UNSPEC_DPAX_W_PH 443)
221 (UNSPEC_DPSX_W_PH 444)
222 (UNSPEC_DPAQX_S_W_PH 445)
223 (UNSPEC_DPAQX_SA_W_PH 446)
224 (UNSPEC_DPSQX_S_W_PH 447)
225 (UNSPEC_DPSQX_SA_W_PH 448)
227 ;; ST Microelectronics Loongson-2E/2F.
228 (UNSPEC_LOONGSON_PAVG 500)
229 (UNSPEC_LOONGSON_PCMPEQ 501)
230 (UNSPEC_LOONGSON_PCMPGT 502)
231 (UNSPEC_LOONGSON_PEXTR 503)
232 (UNSPEC_LOONGSON_PINSR_0 504)
233 (UNSPEC_LOONGSON_PINSR_1 505)
234 (UNSPEC_LOONGSON_PINSR_2 506)
235 (UNSPEC_LOONGSON_PINSR_3 507)
236 (UNSPEC_LOONGSON_PMADD 508)
237 (UNSPEC_LOONGSON_PMOVMSK 509)
238 (UNSPEC_LOONGSON_PMULHU 510)
239 (UNSPEC_LOONGSON_PMULH 511)
240 (UNSPEC_LOONGSON_PMULL 512)
241 (UNSPEC_LOONGSON_PMULU 513)
242 (UNSPEC_LOONGSON_PASUBUB 514)
243 (UNSPEC_LOONGSON_BIADD 515)
244 (UNSPEC_LOONGSON_PSADBH 516)
245 (UNSPEC_LOONGSON_PSHUFH 517)
246 (UNSPEC_LOONGSON_PUNPCKH 518)
247 (UNSPEC_LOONGSON_PUNPCKL 519)
248 (UNSPEC_LOONGSON_PADDD 520)
249 (UNSPEC_LOONGSON_PSUBD 521)
251 ;; Used in loongson2ef.md
252 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
253 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
254 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
255 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
257 (UNSPEC_MIPS_CACHE 600)
258 (UNSPEC_R10K_CACHE_BARRIER 601)
262 (include "predicates.md")
263 (include "constraints.md")
265 ;; ....................
269 ;; ....................
271 (define_attr "got" "unset,xgot_high,load"
272 (const_string "unset"))
274 ;; For jal instructions, this attribute is DIRECT when the target address
275 ;; is symbolic and INDIRECT when it is a register.
276 (define_attr "jal" "unset,direct,indirect"
277 (const_string "unset"))
279 ;; This attribute is YES if the instruction is a jal macro (not a
280 ;; real jal instruction).
282 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
283 ;; an instruction to restore $gp. Direct jals are also macros for
284 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
285 ;; the target address into a register.
286 (define_attr "jal_macro" "no,yes"
287 (cond [(eq_attr "jal" "direct")
288 (symbol_ref "((TARGET_CALL_CLOBBERED_GP
289 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS))
290 ? JAL_MACRO_YES : JAL_MACRO_NO)")
291 (eq_attr "jal" "indirect")
292 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
293 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
294 (const_string "no")))
296 ;; Classification of moves, extensions and truncations. Most values
297 ;; are as for "type" (see below) but there are also the following
298 ;; move-specific values:
300 ;; constN move an N-constraint integer into a MIPS16 register
301 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
302 ;; to produce a sign-extended DEST, even if SRC is not
303 ;; properly sign-extended
304 ;; ext_ins EXT, DEXT, INS or DINS instruction
305 ;; andi a single ANDI instruction
306 ;; loadpool move a constant into a MIPS16 register by loading it
308 ;; shift_shift a shift left followed by a shift right
309 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
311 ;; This attribute is used to determine the instruction's length and
312 ;; scheduling type. For doubleword moves, the attribute always describes
313 ;; the split instructions; in some cases, it is more appropriate for the
314 ;; scheduling type to be "multi" instead.
315 (define_attr "move_type"
316 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
317 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
318 shift_shift,lui_movf"
319 (const_string "unknown"))
321 ;; Main data type used by the insn
322 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
323 (const_string "unknown"))
325 ;; True if the main data type is twice the size of a word.
326 (define_attr "dword_mode" "no,yes"
327 (cond [(and (eq_attr "mode" "DI,DF")
328 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
331 (and (eq_attr "mode" "TI,TF")
332 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
333 (const_string "yes")]
334 (const_string "no")))
336 ;; Classification of each insn.
337 ;; branch conditional branch
338 ;; jump unconditional jump
339 ;; call unconditional call
340 ;; load load instruction(s)
341 ;; fpload floating point load
342 ;; fpidxload floating point indexed load
343 ;; store store instruction(s)
344 ;; fpstore floating point store
345 ;; fpidxstore floating point indexed store
346 ;; prefetch memory prefetch (register + offset)
347 ;; prefetchx memory indexed prefetch (register + register)
348 ;; condmove conditional moves
349 ;; mtc transfer to coprocessor
350 ;; mfc transfer from coprocessor
351 ;; mthilo transfer to hi/lo registers
352 ;; mfhilo transfer from hi/lo registers
353 ;; const load constant
354 ;; arith integer arithmetic instructions
355 ;; logical integer logical instructions
356 ;; shift integer shift instructions
357 ;; slt set less than instructions
358 ;; signext sign extend instructions
359 ;; clz the clz and clo instructions
360 ;; pop the pop instruction
361 ;; trap trap if instructions
362 ;; imul integer multiply 2 operands
363 ;; imul3 integer multiply 3 operands
364 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
365 ;; imadd integer multiply-add
366 ;; idiv integer divide 2 operands
367 ;; idiv3 integer divide 3 operands
368 ;; move integer register move ({,D}ADD{,U} with rt = 0)
369 ;; fmove floating point register move
370 ;; fadd floating point add/subtract
371 ;; fmul floating point multiply
372 ;; fmadd floating point multiply-add
373 ;; fdiv floating point divide
374 ;; frdiv floating point reciprocal divide
375 ;; frdiv1 floating point reciprocal divide step 1
376 ;; frdiv2 floating point reciprocal divide step 2
377 ;; fabs floating point absolute value
378 ;; fneg floating point negation
379 ;; fcmp floating point compare
380 ;; fcvt floating point convert
381 ;; fsqrt floating point square root
382 ;; frsqrt floating point reciprocal square root
383 ;; frsqrt1 floating point reciprocal square root step1
384 ;; frsqrt2 floating point reciprocal square root step2
385 ;; multi multiword sequence (or user asm statements)
387 ;; ghost an instruction that produces no real code
389 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
390 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
391 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
392 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
393 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
394 (cond [(eq_attr "jal" "!unset") (const_string "call")
395 (eq_attr "got" "load") (const_string "load")
397 ;; If a doubleword move uses these expensive instructions,
398 ;; it is usually better to schedule them in the same way
399 ;; as the singleword form, rather than as "multi".
400 (eq_attr "move_type" "load") (const_string "load")
401 (eq_attr "move_type" "fpload") (const_string "fpload")
402 (eq_attr "move_type" "store") (const_string "store")
403 (eq_attr "move_type" "fpstore") (const_string "fpstore")
404 (eq_attr "move_type" "mtc") (const_string "mtc")
405 (eq_attr "move_type" "mfc") (const_string "mfc")
406 (eq_attr "move_type" "mthilo") (const_string "mthilo")
407 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
409 ;; These types of move are always single insns.
410 (eq_attr "move_type" "fmove") (const_string "fmove")
411 (eq_attr "move_type" "loadpool") (const_string "load")
412 (eq_attr "move_type" "signext") (const_string "signext")
413 (eq_attr "move_type" "ext_ins") (const_string "arith")
414 (eq_attr "move_type" "arith") (const_string "arith")
415 (eq_attr "move_type" "logical") (const_string "logical")
416 (eq_attr "move_type" "sll0") (const_string "shift")
417 (eq_attr "move_type" "andi") (const_string "logical")
419 ;; These types of move are always split.
420 (eq_attr "move_type" "constN,shift_shift")
421 (const_string "multi")
423 ;; These types of move are split for doubleword modes only.
424 (and (eq_attr "move_type" "move,const")
425 (eq_attr "dword_mode" "yes"))
426 (const_string "multi")
427 (eq_attr "move_type" "move") (const_string "move")
428 (eq_attr "move_type" "const") (const_string "const")]
429 ;; We classify "lui_movf" as "unknown" rather than "multi"
430 ;; because we don't split it. FIXME: we should split instead.
431 (const_string "unknown")))
433 ;; Mode for conversion types (fcvt)
434 ;; I2S integer to float single (SI/DI to SF)
435 ;; I2D integer to float double (SI/DI to DF)
436 ;; S2I float to integer (SF to SI/DI)
437 ;; D2I float to integer (DF to SI/DI)
438 ;; D2S double to float single
439 ;; S2D float single to double
441 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
442 (const_string "unknown"))
444 ;; Is this an extended instruction in mips16 mode?
445 (define_attr "extended_mips16" "no,yes"
446 (if_then_else (ior (eq_attr "move_type" "sll0")
447 (eq_attr "type" "branch")
448 (eq_attr "jal" "direct"))
450 (const_string "no")))
452 ;; Length of instruction in bytes.
453 (define_attr "length" ""
454 (cond [(and (eq_attr "extended_mips16" "yes")
455 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
458 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
459 ;; If a branch is outside this range, we have a choice of two
460 ;; sequences. For PIC, an out-of-range branch like:
465 ;; becomes the equivalent of:
474 ;; where the load address can be up to three instructions long
477 ;; The non-PIC case is similar except that we use a direct
478 ;; jump instead of an la/jr pair. Since the target of this
479 ;; jump is an absolute 28-bit bit address (the other bits
480 ;; coming from the address of the delay slot) this form cannot
481 ;; cross a 256MB boundary. We could provide the option of
482 ;; using la/jr in this case too, but we do not do so at
485 ;; Note that this value does not account for the delay slot
486 ;; instruction, whose length is added separately. If the RTL
487 ;; pattern has no explicit delay slot, mips_adjust_insn_length
488 ;; will add the length of the implicit nop. The values for
489 ;; forward and backward branches will be different as well.
490 (eq_attr "type" "branch")
491 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
492 (le (minus (pc) (match_dup 1)) (const_int 131068)))
494 (ne (symbol_ref "flag_pic") (const_int 0))
498 ;; "Ghost" instructions occupy no space.
499 (eq_attr "type" "ghost")
502 (eq_attr "got" "load")
503 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
506 (eq_attr "got" "xgot_high")
509 ;; In general, constant-pool loads are extended instructions.
510 (eq_attr "move_type" "loadpool")
513 ;; LUI_MOVFs are decomposed into two separate instructions.
514 (eq_attr "move_type" "lui_movf")
517 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
518 ;; They are extended instructions on MIPS16 targets.
519 (eq_attr "move_type" "shift_shift")
520 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
524 ;; Check for doubleword moves that are decomposed into two
526 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
527 (eq_attr "dword_mode" "yes"))
530 ;; Doubleword CONST{,N} moves are split into two word
532 (and (eq_attr "move_type" "const,constN")
533 (eq_attr "dword_mode" "yes"))
534 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
536 ;; Otherwise, constants, loads and stores are handled by external
538 (eq_attr "move_type" "const,constN")
539 (symbol_ref "mips_const_insns (operands[1]) * 4")
540 (eq_attr "move_type" "load,fpload")
541 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
542 (eq_attr "move_type" "store,fpstore")
543 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
545 ;; In the worst case, a call macro will take 8 instructions:
547 ;; lui $25,%call_hi(FOO)
549 ;; lw $25,%call_lo(FOO)($25)
555 (eq_attr "jal_macro" "yes")
558 ;; Various VR4120 errata require a nop to be inserted after a macc
559 ;; instruction. The assembler does this for us, so account for
560 ;; the worst-case length here.
561 (and (eq_attr "type" "imadd")
562 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
565 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
566 ;; the result of the second one is missed. The assembler should work
567 ;; around this by inserting a nop after the first dmult.
568 (and (eq_attr "type" "imul,imul3")
569 (and (eq_attr "mode" "DI")
570 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
573 (eq_attr "type" "idiv,idiv3")
574 (symbol_ref "mips_idiv_insns () * 4")
577 ;; Attribute describing the processor. This attribute must match exactly
578 ;; with the processor_type enumeration in mips.h.
580 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
581 (const (symbol_ref "mips_tune_attr")))
583 ;; The type of hardware hazard associated with this instruction.
584 ;; DELAY means that the next instruction cannot read the result
585 ;; of this one. HILO means that the next two instructions cannot
586 ;; write to HI or LO.
587 (define_attr "hazard" "none,delay,hilo"
588 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
589 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
590 (const_string "delay")
592 (and (eq_attr "type" "mfc,mtc")
593 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
594 (const_string "delay")
596 (and (eq_attr "type" "fcmp")
597 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
598 (const_string "delay")
600 ;; The r4000 multiplication patterns include an mflo instruction.
601 (and (eq_attr "type" "imul")
602 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
603 (const_string "hilo")
605 (and (eq_attr "type" "mfhilo")
606 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
607 (const_string "hilo")]
608 (const_string "none")))
610 ;; Is it a single instruction?
611 (define_attr "single_insn" "no,yes"
612 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
613 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
615 ;; Can the instruction be put into a delay slot?
616 (define_attr "can_delay" "no,yes"
617 (if_then_else (and (eq_attr "type" "!branch,call,jump")
618 (and (eq_attr "hazard" "none")
619 (eq_attr "single_insn" "yes")))
621 (const_string "no")))
623 ;; Attribute defining whether or not we can use the branch-likely
625 (define_attr "branch_likely" "no,yes"
626 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
628 (const_string "no")))
630 ;; True if an instruction might assign to hi or lo when reloaded.
631 ;; This is used by the TUNE_MACC_CHAINS code.
632 (define_attr "may_clobber_hilo" "no,yes"
633 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
635 (const_string "no")))
637 ;; Describe a user's asm statement.
638 (define_asm_attributes
639 [(set_attr "type" "multi")
640 (set_attr "can_delay" "no")])
642 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
643 ;; from the same template.
644 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
646 ;; A copy of GPR that can be used when a pattern has two independent
648 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
650 ;; This mode iterator allows :HILO to be used as the mode of the
651 ;; concatenated HI and LO registers.
652 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
654 ;; This mode iterator allows :P to be used for patterns that operate on
655 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
656 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
658 ;; This mode iterator allows :MOVECC to be used anywhere that a
659 ;; conditional-move-type condition is needed.
660 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
661 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
663 ;; 32-bit integer moves for which we provide move patterns.
664 (define_mode_iterator IMOVE32
673 (V4UQQ "TARGET_DSP")])
675 ;; 64-bit modes for which we provide move patterns.
676 (define_mode_iterator MOVE64
678 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
679 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
680 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
681 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
683 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
684 (define_mode_iterator MOVE128 [TI TF])
686 ;; This mode iterator allows the QI and HI extension patterns to be
687 ;; defined from the same template.
688 (define_mode_iterator SHORT [QI HI])
690 ;; Likewise the 64-bit truncate-and-shift patterns.
691 (define_mode_iterator SUBDI [QI HI SI])
693 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
694 ;; floating-point mode is allowed.
695 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
696 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
697 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
699 ;; Like ANYF, but only applies to scalar modes.
700 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
701 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
703 ;; A floating-point mode for which moves involving FPRs may need to be split.
704 (define_mode_iterator SPLITF
705 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
706 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
707 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
708 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
709 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
710 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
711 (TF "TARGET_64BIT && TARGET_FLOAT64")])
713 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
714 ;; 32-bit version and "dsubu" in the 64-bit version.
715 (define_mode_attr d [(SI "") (DI "d")
716 (QQ "") (HQ "") (SQ "") (DQ "d")
717 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
718 (HA "") (SA "") (DA "d")
719 (UHA "") (USA "") (UDA "d")])
721 ;; Same as d but upper-case.
722 (define_mode_attr D [(SI "") (DI "D")
723 (QQ "") (HQ "") (SQ "") (DQ "D")
724 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
725 (HA "") (SA "") (DA "D")
726 (UHA "") (USA "") (UDA "D")])
728 ;; This attribute gives the length suffix for a sign- or zero-extension
730 (define_mode_attr size [(QI "b") (HI "h")])
732 ;; This attributes gives the mode mask of a SHORT.
733 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
735 ;; Mode attributes for GPR loads.
736 (define_mode_attr load [(SI "lw") (DI "ld")])
737 ;; Instruction names for stores.
738 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
740 ;; Similarly for MIPS IV indexed FPR loads and stores.
741 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
742 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
744 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
745 ;; are different. Some forms of unextended addiu have an 8-bit immediate
746 ;; field but the equivalent daddiu has only a 5-bit field.
747 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
749 ;; This attribute gives the best constraint to use for registers of
751 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
753 ;; This attribute gives the format suffix for floating-point operations.
754 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
756 ;; This attribute gives the upper-case mode name for one unit of a
757 ;; floating-point mode.
758 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
760 ;; This attribute gives the integer mode that has the same size as a
762 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
763 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
764 (HA "HI") (SA "SI") (DA "DI")
765 (UHA "HI") (USA "SI") (UDA "DI")
766 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
767 (V2HQ "SI") (V2HA "SI")])
769 ;; This attribute gives the integer mode that has half the size of
770 ;; the controlling mode.
771 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
772 (V2SI "SI") (V4HI "SI") (V8QI "SI")
775 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
777 ;; In certain cases, div.s and div.ps may have a rounding error
778 ;; and/or wrong inexact flag.
780 ;; Therefore, we only allow div.s if not working around SB-1 rev2
781 ;; errata or if a slight loss of precision is OK.
782 (define_mode_attr divide_condition
783 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
784 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
786 ;; This attribute gives the conditions under which SQRT.fmt instructions
788 (define_mode_attr sqrt_condition
789 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
791 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
792 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
793 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
794 ;; so for safety's sake, we apply this restriction to all targets.
795 (define_mode_attr recip_condition
797 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
798 (V2SF "TARGET_SB1")])
800 ;; This code iterator allows signed and unsigned widening multiplications
801 ;; to use the same template.
802 (define_code_iterator any_extend [sign_extend zero_extend])
804 ;; This code iterator allows the two right shift instructions to be
805 ;; generated from the same template.
806 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
808 ;; This code iterator allows the three shift instructions to be generated
809 ;; from the same template.
810 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
812 ;; This code iterator allows unsigned and signed division to be generated
813 ;; from the same template.
814 (define_code_iterator any_div [div udiv])
816 ;; This code iterator allows unsigned and signed modulus to be generated
817 ;; from the same template.
818 (define_code_iterator any_mod [mod umod])
820 ;; This code iterator allows all native floating-point comparisons to be
821 ;; generated from the same template.
822 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
824 ;; This code iterator is used for comparisons that can be implemented
825 ;; by swapping the operands.
826 (define_code_iterator swapped_fcond [ge gt unge ungt])
828 ;; Equality operators.
829 (define_code_iterator equality_op [eq ne])
831 ;; These code iterators allow the signed and unsigned scc operations to use
832 ;; the same template.
833 (define_code_iterator any_gt [gt gtu])
834 (define_code_iterator any_ge [ge geu])
835 (define_code_iterator any_lt [lt ltu])
836 (define_code_iterator any_le [le leu])
838 ;; <u> expands to an empty string when doing a signed operation and
839 ;; "u" when doing an unsigned operation.
840 (define_code_attr u [(sign_extend "") (zero_extend "u")
848 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
849 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
851 ;; <optab> expands to the name of the optab for a particular code.
852 (define_code_attr optab [(ashift "ashl")
861 ;; <insn> expands to the name of the insn that implements a particular code.
862 (define_code_attr insn [(ashift "sll")
871 ;; <immediate_insn> expands to the name of the insn that implements
872 ;; a particular code to operate on immediate values.
873 (define_code_attr immediate_insn [(ior "ori")
877 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
878 (define_code_attr fcond [(unordered "un")
886 ;; Similar, but for swapped conditions.
887 (define_code_attr swapped_fcond [(ge "le")
892 ;; The value of the bit when the branch is taken for branch_bit patterns.
893 ;; Comparison is always against zero so this depends on the operator.
894 (define_code_attr bbv [(eq "0") (ne "1")])
896 ;; This is the inverse value of bbv.
897 (define_code_attr bbinv [(eq "1") (ne "0")])
899 ;; .........................
901 ;; Branch, call and jump delay slots
903 ;; .........................
905 (define_delay (and (eq_attr "type" "branch")
906 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
907 (eq_attr "branch_likely" "yes"))
908 [(eq_attr "can_delay" "yes")
910 (eq_attr "can_delay" "yes")])
912 ;; Branches that don't have likely variants do not annul on false.
913 (define_delay (and (eq_attr "type" "branch")
914 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
915 (eq_attr "branch_likely" "no"))
916 [(eq_attr "can_delay" "yes")
920 (define_delay (eq_attr "type" "jump")
921 [(eq_attr "can_delay" "yes")
925 (define_delay (and (eq_attr "type" "call")
926 (eq_attr "jal_macro" "no"))
927 [(eq_attr "can_delay" "yes")
931 ;; Pipeline descriptions.
933 ;; generic.md provides a fallback for processors without a specific
934 ;; pipeline description. It is derived from the old define_function_unit
935 ;; version and uses the "alu" and "imuldiv" units declared below.
937 ;; Some of the processor-specific files are also derived from old
938 ;; define_function_unit descriptions and simply override the parts of
939 ;; generic.md that don't apply. The other processor-specific files
940 ;; are self-contained.
941 (define_automaton "alu,imuldiv")
943 (define_cpu_unit "alu" "alu")
944 (define_cpu_unit "imuldiv" "imuldiv")
946 ;; Ghost instructions produce no real code and introduce no hazards.
947 ;; They exist purely to express an effect on dataflow.
948 (define_insn_reservation "ghost" 0
949 (eq_attr "type" "ghost")
970 (include "loongson2ef.md")
971 (include "octeon.md")
975 (include "generic.md")
978 ;; ....................
982 ;; ....................
986 [(trap_if (const_int 1) (const_int 0))]
989 if (ISA_HAS_COND_TRAP)
991 else if (TARGET_MIPS16)
996 [(set_attr "type" "trap")])
998 (define_expand "ctrap<mode>4"
999 [(trap_if (match_operator 0 "comparison_operator"
1000 [(match_operand:GPR 1 "reg_or_0_operand")
1001 (match_operand:GPR 2 "arith_operand")])
1002 (match_operand 3 "const_0_operand"))]
1005 mips_expand_conditional_trap (operands[0]);
1009 (define_insn "*conditional_trap<mode>"
1010 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1011 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1012 (match_operand:GPR 2 "arith_operand" "dI")])
1016 [(set_attr "type" "trap")])
1019 ;; ....................
1023 ;; ....................
1026 (define_insn "add<mode>3"
1027 [(set (match_operand:ANYF 0 "register_operand" "=f")
1028 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1029 (match_operand:ANYF 2 "register_operand" "f")))]
1031 "add.<fmt>\t%0,%1,%2"
1032 [(set_attr "type" "fadd")
1033 (set_attr "mode" "<UNITMODE>")])
1035 (define_expand "add<mode>3"
1036 [(set (match_operand:GPR 0 "register_operand")
1037 (plus:GPR (match_operand:GPR 1 "register_operand")
1038 (match_operand:GPR 2 "arith_operand")))]
1041 (define_insn "*add<mode>3"
1042 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1043 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1044 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1049 [(set_attr "type" "arith")
1050 (set_attr "mode" "<MODE>")])
1052 (define_insn "*add<mode>3_mips16"
1053 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1054 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1055 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1063 [(set_attr "type" "arith")
1064 (set_attr "mode" "<MODE>")
1065 (set_attr_alternative "length"
1066 [(if_then_else (match_operand 2 "m16_simm8_8")
1069 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1072 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1075 (if_then_else (match_operand 2 "m16_simm4_1")
1080 ;; On the mips16, we can sometimes split an add of a constant which is
1081 ;; a 4 byte instruction into two adds which are both 2 byte
1082 ;; instructions. There are two cases: one where we are adding a
1083 ;; constant plus a register to another register, and one where we are
1084 ;; simply adding a constant to a register.
1087 [(set (match_operand:SI 0 "d_operand")
1088 (plus:SI (match_dup 0)
1089 (match_operand:SI 1 "const_int_operand")))]
1090 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1091 && ((INTVAL (operands[1]) > 0x7f
1092 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1093 || (INTVAL (operands[1]) < - 0x80
1094 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1095 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1096 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1098 HOST_WIDE_INT val = INTVAL (operands[1]);
1102 operands[1] = GEN_INT (0x7f);
1103 operands[2] = GEN_INT (val - 0x7f);
1107 operands[1] = GEN_INT (- 0x80);
1108 operands[2] = GEN_INT (val + 0x80);
1113 [(set (match_operand:SI 0 "d_operand")
1114 (plus:SI (match_operand:SI 1 "d_operand")
1115 (match_operand:SI 2 "const_int_operand")))]
1116 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1117 && REGNO (operands[0]) != REGNO (operands[1])
1118 && ((INTVAL (operands[2]) > 0x7
1119 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1120 || (INTVAL (operands[2]) < - 0x8
1121 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1122 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1123 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1125 HOST_WIDE_INT val = INTVAL (operands[2]);
1129 operands[2] = GEN_INT (0x7);
1130 operands[3] = GEN_INT (val - 0x7);
1134 operands[2] = GEN_INT (- 0x8);
1135 operands[3] = GEN_INT (val + 0x8);
1140 [(set (match_operand:DI 0 "d_operand")
1141 (plus:DI (match_dup 0)
1142 (match_operand:DI 1 "const_int_operand")))]
1143 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1144 && ((INTVAL (operands[1]) > 0xf
1145 && INTVAL (operands[1]) <= 0xf + 0xf)
1146 || (INTVAL (operands[1]) < - 0x10
1147 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1148 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1149 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1151 HOST_WIDE_INT val = INTVAL (operands[1]);
1155 operands[1] = GEN_INT (0xf);
1156 operands[2] = GEN_INT (val - 0xf);
1160 operands[1] = GEN_INT (- 0x10);
1161 operands[2] = GEN_INT (val + 0x10);
1166 [(set (match_operand:DI 0 "d_operand")
1167 (plus:DI (match_operand:DI 1 "d_operand")
1168 (match_operand:DI 2 "const_int_operand")))]
1169 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1170 && REGNO (operands[0]) != REGNO (operands[1])
1171 && ((INTVAL (operands[2]) > 0x7
1172 && INTVAL (operands[2]) <= 0x7 + 0xf)
1173 || (INTVAL (operands[2]) < - 0x8
1174 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1175 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1176 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1178 HOST_WIDE_INT val = INTVAL (operands[2]);
1182 operands[2] = GEN_INT (0x7);
1183 operands[3] = GEN_INT (val - 0x7);
1187 operands[2] = GEN_INT (- 0x8);
1188 operands[3] = GEN_INT (val + 0x8);
1192 (define_insn "*addsi3_extended"
1193 [(set (match_operand:DI 0 "register_operand" "=d,d")
1195 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1196 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1197 "TARGET_64BIT && !TARGET_MIPS16"
1201 [(set_attr "type" "arith")
1202 (set_attr "mode" "SI")])
1204 ;; Split this insn so that the addiu splitters can have a crack at it.
1205 ;; Use a conservative length estimate until the split.
1206 (define_insn_and_split "*addsi3_extended_mips16"
1207 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1209 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1210 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1211 "TARGET_64BIT && TARGET_MIPS16"
1213 "&& reload_completed"
1214 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1215 { operands[3] = gen_lowpart (SImode, operands[0]); }
1216 [(set_attr "type" "arith")
1217 (set_attr "mode" "SI")
1218 (set_attr "extended_mips16" "yes")])
1220 ;; Combiner patterns for unsigned byte-add.
1222 (define_insn "*baddu_si_eb"
1223 [(set (match_operand:SI 0 "register_operand" "=d")
1226 (plus:SI (match_operand:SI 1 "register_operand" "d")
1227 (match_operand:SI 2 "register_operand" "d")) 3)))]
1228 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1230 [(set_attr "type" "arith")])
1232 (define_insn "*baddu_si_el"
1233 [(set (match_operand:SI 0 "register_operand" "=d")
1236 (plus:SI (match_operand:SI 1 "register_operand" "d")
1237 (match_operand:SI 2 "register_operand" "d")) 0)))]
1238 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1240 [(set_attr "type" "arith")])
1242 (define_insn "*baddu_di<mode>"
1243 [(set (match_operand:GPR 0 "register_operand" "=d")
1246 (plus:DI (match_operand:DI 1 "register_operand" "d")
1247 (match_operand:DI 2 "register_operand" "d")))))]
1248 "ISA_HAS_BADDU && TARGET_64BIT"
1250 [(set_attr "type" "arith")])
1253 ;; ....................
1257 ;; ....................
1260 (define_insn "sub<mode>3"
1261 [(set (match_operand:ANYF 0 "register_operand" "=f")
1262 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1263 (match_operand:ANYF 2 "register_operand" "f")))]
1265 "sub.<fmt>\t%0,%1,%2"
1266 [(set_attr "type" "fadd")
1267 (set_attr "mode" "<UNITMODE>")])
1269 (define_insn "sub<mode>3"
1270 [(set (match_operand:GPR 0 "register_operand" "=d")
1271 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1272 (match_operand:GPR 2 "register_operand" "d")))]
1275 [(set_attr "type" "arith")
1276 (set_attr "mode" "<MODE>")])
1278 (define_insn "*subsi3_extended"
1279 [(set (match_operand:DI 0 "register_operand" "=d")
1281 (minus:SI (match_operand:SI 1 "register_operand" "d")
1282 (match_operand:SI 2 "register_operand" "d"))))]
1285 [(set_attr "type" "arith")
1286 (set_attr "mode" "DI")])
1289 ;; ....................
1293 ;; ....................
1296 (define_expand "mul<mode>3"
1297 [(set (match_operand:SCALARF 0 "register_operand")
1298 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1299 (match_operand:SCALARF 2 "register_operand")))]
1303 (define_insn "*mul<mode>3"
1304 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1305 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1306 (match_operand:SCALARF 2 "register_operand" "f")))]
1307 "!TARGET_4300_MUL_FIX"
1308 "mul.<fmt>\t%0,%1,%2"
1309 [(set_attr "type" "fmul")
1310 (set_attr "mode" "<MODE>")])
1312 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1313 ;; operands may corrupt immediately following multiplies. This is a
1314 ;; simple fix to insert NOPs.
1316 (define_insn "*mul<mode>3_r4300"
1317 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1318 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1319 (match_operand:SCALARF 2 "register_operand" "f")))]
1320 "TARGET_4300_MUL_FIX"
1321 "mul.<fmt>\t%0,%1,%2\;nop"
1322 [(set_attr "type" "fmul")
1323 (set_attr "mode" "<MODE>")
1324 (set_attr "length" "8")])
1326 (define_insn "mulv2sf3"
1327 [(set (match_operand:V2SF 0 "register_operand" "=f")
1328 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1329 (match_operand:V2SF 2 "register_operand" "f")))]
1330 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1332 [(set_attr "type" "fmul")
1333 (set_attr "mode" "SF")])
1335 ;; The original R4000 has a cpu bug. If a double-word or a variable
1336 ;; shift executes while an integer multiplication is in progress, the
1337 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1338 ;; with the mult on the R4000.
1340 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1341 ;; (also valid for MIPS R4000MC processors):
1343 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1344 ;; this errata description.
1345 ;; The following code sequence causes the R4000 to incorrectly
1346 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1347 ;; instruction. If the dsra32 instruction is executed during an
1348 ;; integer multiply, the dsra32 will only shift by the amount in
1349 ;; specified in the instruction rather than the amount plus 32
1351 ;; instruction 1: mult rs,rt integer multiply
1352 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1353 ;; right arithmetic + 32
1354 ;; Workaround: A dsra32 instruction placed after an integer
1355 ;; multiply should not be one of the 11 instructions after the
1356 ;; multiply instruction."
1360 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1361 ;; the following description.
1362 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1363 ;; 64-bit versions) may produce incorrect results under the
1364 ;; following conditions:
1365 ;; 1) An integer multiply is currently executing
1366 ;; 2) These types of shift instructions are executed immediately
1367 ;; following an integer divide instruction.
1369 ;; 1) Make sure no integer multiply is running wihen these
1370 ;; instruction are executed. If this cannot be predicted at
1371 ;; compile time, then insert a "mfhi" to R0 instruction
1372 ;; immediately after the integer multiply instruction. This
1373 ;; will cause the integer multiply to complete before the shift
1375 ;; 2) Separate integer divide and these two classes of shift
1376 ;; instructions by another instruction or a noop."
1378 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1381 (define_expand "mul<mode>3"
1382 [(set (match_operand:GPR 0 "register_operand")
1383 (mult:GPR (match_operand:GPR 1 "register_operand")
1384 (match_operand:GPR 2 "register_operand")))]
1387 if (TARGET_LOONGSON_2EF)
1388 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1390 else if (ISA_HAS_<D>MUL3)
1391 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1392 else if (TARGET_FIX_R4000)
1393 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1396 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1400 (define_insn "mul<mode>3_mul3_ls2ef"
1401 [(set (match_operand:GPR 0 "register_operand" "=d")
1402 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1403 (match_operand:GPR 2 "register_operand" "d")))]
1404 "TARGET_LOONGSON_2EF"
1405 "<d>multu.g\t%0,%1,%2"
1406 [(set_attr "type" "imul3nc")
1407 (set_attr "mode" "<MODE>")])
1409 (define_insn "mul<mode>3_mul3"
1410 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1411 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1412 (match_operand:GPR 2 "register_operand" "d,d")))
1413 (clobber (match_scratch:GPR 3 "=l,X"))]
1416 if (which_alternative == 1)
1417 return "<d>mult\t%1,%2";
1418 if (<MODE>mode == SImode && TARGET_MIPS3900)
1419 return "mult\t%0,%1,%2";
1420 return "<d>mul\t%0,%1,%2";
1422 [(set_attr "type" "imul3,imul")
1423 (set_attr "mode" "<MODE>")])
1425 ;; If a register gets allocated to LO, and we spill to memory, the reload
1426 ;; will include a move from LO to a GPR. Merge it into the multiplication
1427 ;; if it can set the GPR directly.
1430 ;; Operand 1: GPR (1st multiplication operand)
1431 ;; Operand 2: GPR (2nd multiplication operand)
1432 ;; Operand 3: GPR (destination)
1435 [(set (match_operand:SI 0 "lo_operand")
1436 (mult:SI (match_operand:SI 1 "d_operand")
1437 (match_operand:SI 2 "d_operand")))
1438 (clobber (scratch:SI))])
1439 (set (match_operand:SI 3 "d_operand")
1441 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1444 (mult:SI (match_dup 1)
1446 (clobber (match_dup 0))])])
1448 (define_insn "mul<mode>3_internal"
1449 [(set (match_operand:GPR 0 "register_operand" "=l")
1450 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1451 (match_operand:GPR 2 "register_operand" "d")))]
1454 [(set_attr "type" "imul")
1455 (set_attr "mode" "<MODE>")])
1457 (define_insn "mul<mode>3_r4000"
1458 [(set (match_operand:GPR 0 "register_operand" "=d")
1459 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1460 (match_operand:GPR 2 "register_operand" "d")))
1461 (clobber (match_scratch:GPR 3 "=l"))]
1463 "<d>mult\t%1,%2\;mflo\t%0"
1464 [(set_attr "type" "imul")
1465 (set_attr "mode" "<MODE>")
1466 (set_attr "length" "8")])
1468 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1469 ;; of "mult; mflo". They have the same latency, but the first form gives
1470 ;; us an extra cycle to compute the operands.
1473 ;; Operand 1: GPR (1st multiplication operand)
1474 ;; Operand 2: GPR (2nd multiplication operand)
1475 ;; Operand 3: GPR (destination)
1477 [(set (match_operand:SI 0 "lo_operand")
1478 (mult:SI (match_operand:SI 1 "d_operand")
1479 (match_operand:SI 2 "d_operand")))
1480 (set (match_operand:SI 3 "d_operand")
1482 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1487 (plus:SI (mult:SI (match_dup 1)
1491 (plus:SI (mult:SI (match_dup 1)
1495 ;; Multiply-accumulate patterns
1497 ;; This pattern is first matched by combine, which tries to use the
1498 ;; pattern wherever it can. We don't know until later whether it
1499 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1500 ;; so we need to keep both options open.
1502 ;; The second alternative has a "?" marker because it is generally
1503 ;; one instruction more costly than the first alternative. This "?"
1504 ;; marker is enough to convey the relative costs to the register
1507 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1508 ;; reloads of the other operands, even though operands 4 and 5 need no
1509 ;; copy instructions. Reload therefore thinks that the second alternative
1510 ;; is two reloads more costly than the first. We add "*?*?" to the first
1511 ;; alternative as a counterweight.
1512 (define_insn "*mul_acc_si"
1513 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1514 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1515 (match_operand:SI 2 "register_operand" "d,d"))
1516 (match_operand:SI 3 "register_operand" "0,d")))
1517 (clobber (match_scratch:SI 4 "=X,l"))
1518 (clobber (match_scratch:SI 5 "=X,&d"))]
1519 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1523 [(set_attr "type" "imadd")
1524 (set_attr "mode" "SI")
1525 (set_attr "length" "4,8")])
1527 ;; The same idea applies here. The middle alternative needs one less
1528 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1529 (define_insn "*mul_acc_si_r3900"
1530 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1531 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1532 (match_operand:SI 2 "register_operand" "d,d,d"))
1533 (match_operand:SI 3 "register_operand" "0,l,d")))
1534 (clobber (match_scratch:SI 4 "=X,3,l"))
1535 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1536 "TARGET_MIPS3900 && !TARGET_MIPS16"
1541 [(set_attr "type" "imadd")
1542 (set_attr "mode" "SI")
1543 (set_attr "length" "4,4,8")])
1545 ;; Split *mul_acc_si if both the source and destination accumulator
1548 [(set (match_operand:SI 0 "d_operand")
1549 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1550 (match_operand:SI 2 "d_operand"))
1551 (match_operand:SI 3 "d_operand")))
1552 (clobber (match_operand:SI 4 "lo_operand"))
1553 (clobber (match_operand:SI 5 "d_operand"))]
1555 [(parallel [(set (match_dup 5)
1556 (mult:SI (match_dup 1) (match_dup 2)))
1557 (clobber (match_dup 4))])
1558 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1561 (define_insn "*macc"
1562 [(set (match_operand:SI 0 "register_operand" "=l,d")
1563 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1564 (match_operand:SI 2 "register_operand" "d,d"))
1565 (match_operand:SI 3 "register_operand" "0,l")))
1566 (clobber (match_scratch:SI 4 "=X,3"))]
1569 if (which_alternative == 1)
1570 return "macc\t%0,%1,%2";
1571 else if (TARGET_MIPS5500)
1572 return "madd\t%1,%2";
1574 /* The VR4130 assumes that there is a two-cycle latency between a macc
1575 that "writes" to $0 and an instruction that reads from it. We avoid
1576 this by assigning to $1 instead. */
1577 return "%[macc\t%@,%1,%2%]";
1579 [(set_attr "type" "imadd")
1580 (set_attr "mode" "SI")])
1582 (define_insn "*msac"
1583 [(set (match_operand:SI 0 "register_operand" "=l,d")
1584 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1585 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1586 (match_operand:SI 3 "register_operand" "d,d"))))
1587 (clobber (match_scratch:SI 4 "=X,1"))]
1590 if (which_alternative == 1)
1591 return "msac\t%0,%2,%3";
1592 else if (TARGET_MIPS5500)
1593 return "msub\t%2,%3";
1595 return "msac\t$0,%2,%3";
1597 [(set_attr "type" "imadd")
1598 (set_attr "mode" "SI")])
1600 ;; An msac-like instruction implemented using negation and a macc.
1601 (define_insn_and_split "*msac_using_macc"
1602 [(set (match_operand:SI 0 "register_operand" "=l,d")
1603 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1604 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1605 (match_operand:SI 3 "register_operand" "d,d"))))
1606 (clobber (match_scratch:SI 4 "=X,1"))
1607 (clobber (match_scratch:SI 5 "=d,d"))]
1608 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1610 "&& reload_completed"
1612 (neg:SI (match_dup 3)))
1615 (plus:SI (mult:SI (match_dup 2)
1618 (clobber (match_dup 4))])]
1620 [(set_attr "type" "imadd")
1621 (set_attr "length" "8")])
1623 ;; Patterns generated by the define_peephole2 below.
1625 (define_insn "*macc2"
1626 [(set (match_operand:SI 0 "register_operand" "=l")
1627 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1628 (match_operand:SI 2 "register_operand" "d"))
1630 (set (match_operand:SI 3 "register_operand" "=d")
1631 (plus:SI (mult:SI (match_dup 1)
1634 "ISA_HAS_MACC && reload_completed"
1636 [(set_attr "type" "imadd")
1637 (set_attr "mode" "SI")])
1639 (define_insn "*msac2"
1640 [(set (match_operand:SI 0 "register_operand" "=l")
1641 (minus:SI (match_dup 0)
1642 (mult:SI (match_operand:SI 1 "register_operand" "d")
1643 (match_operand:SI 2 "register_operand" "d"))))
1644 (set (match_operand:SI 3 "register_operand" "=d")
1645 (minus:SI (match_dup 0)
1646 (mult:SI (match_dup 1)
1648 "ISA_HAS_MSAC && reload_completed"
1650 [(set_attr "type" "imadd")
1651 (set_attr "mode" "SI")])
1653 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1657 ;; Operand 1: macc/msac
1658 ;; Operand 2: GPR (destination)
1661 [(set (match_operand:SI 0 "lo_operand")
1662 (match_operand:SI 1 "macc_msac_operand"))
1663 (clobber (scratch:SI))])
1664 (set (match_operand:SI 2 "d_operand")
1667 [(parallel [(set (match_dup 0)
1672 ;; When we have a three-address multiplication instruction, it should
1673 ;; be faster to do a separate multiply and add, rather than moving
1674 ;; something into LO in order to use a macc instruction.
1676 ;; This peephole needs a scratch register to cater for the case when one
1677 ;; of the multiplication operands is the same as the destination.
1679 ;; Operand 0: GPR (scratch)
1681 ;; Operand 2: GPR (addend)
1682 ;; Operand 3: GPR (destination)
1683 ;; Operand 4: macc/msac
1684 ;; Operand 5: new multiplication
1685 ;; Operand 6: new addition/subtraction
1687 [(match_scratch:SI 0 "d")
1688 (set (match_operand:SI 1 "lo_operand")
1689 (match_operand:SI 2 "d_operand"))
1692 [(set (match_operand:SI 3 "d_operand")
1693 (match_operand:SI 4 "macc_msac_operand"))
1694 (clobber (match_dup 1))])]
1695 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1696 [(parallel [(set (match_dup 0)
1698 (clobber (match_dup 1))])
1702 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1703 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1704 operands[2], operands[0]);
1707 ;; Same as above, except LO is the initial target of the macc.
1709 ;; Operand 0: GPR (scratch)
1711 ;; Operand 2: GPR (addend)
1712 ;; Operand 3: macc/msac
1713 ;; Operand 4: GPR (destination)
1714 ;; Operand 5: new multiplication
1715 ;; Operand 6: new addition/subtraction
1717 [(match_scratch:SI 0 "d")
1718 (set (match_operand:SI 1 "lo_operand")
1719 (match_operand:SI 2 "d_operand"))
1723 (match_operand:SI 3 "macc_msac_operand"))
1724 (clobber (scratch:SI))])
1726 (set (match_operand:SI 4 "d_operand")
1728 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1729 [(parallel [(set (match_dup 0)
1731 (clobber (match_dup 1))])
1735 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1736 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1737 operands[2], operands[0]);
1740 ;; See the comment above *mul_add_si for details.
1741 (define_insn "*mul_sub_si"
1742 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1743 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1744 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1745 (match_operand:SI 3 "register_operand" "d,d"))))
1746 (clobber (match_scratch:SI 4 "=X,l"))
1747 (clobber (match_scratch:SI 5 "=X,&d"))]
1748 "GENERATE_MADD_MSUB"
1752 [(set_attr "type" "imadd")
1753 (set_attr "mode" "SI")
1754 (set_attr "length" "4,8")])
1756 ;; Split *mul_sub_si if both the source and destination accumulator
1759 [(set (match_operand:SI 0 "d_operand")
1760 (minus:SI (match_operand:SI 1 "d_operand")
1761 (mult:SI (match_operand:SI 2 "d_operand")
1762 (match_operand:SI 3 "d_operand"))))
1763 (clobber (match_operand:SI 4 "lo_operand"))
1764 (clobber (match_operand:SI 5 "d_operand"))]
1766 [(parallel [(set (match_dup 5)
1767 (mult:SI (match_dup 2) (match_dup 3)))
1768 (clobber (match_dup 4))])
1769 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1772 (define_insn "*muls"
1773 [(set (match_operand:SI 0 "register_operand" "=l,d")
1774 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1775 (match_operand:SI 2 "register_operand" "d,d"))))
1776 (clobber (match_scratch:SI 3 "=X,l"))]
1781 [(set_attr "type" "imul,imul3")
1782 (set_attr "mode" "SI")])
1784 (define_expand "<u>mulsidi3"
1785 [(set (match_operand:DI 0 "register_operand")
1786 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1787 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1788 "!TARGET_64BIT || !TARGET_FIX_R4000"
1791 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1792 else if (TARGET_FIX_R4000)
1793 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1796 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1800 (define_insn "<u>mulsidi3_32bit"
1801 [(set (match_operand:DI 0 "register_operand" "=x")
1802 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1803 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1804 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1806 [(set_attr "type" "imul")
1807 (set_attr "mode" "SI")])
1809 (define_insn "<u>mulsidi3_32bit_r4000"
1810 [(set (match_operand:DI 0 "register_operand" "=d")
1811 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1812 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1813 (clobber (match_scratch:DI 3 "=x"))]
1814 "!TARGET_64BIT && TARGET_FIX_R4000"
1815 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1816 [(set_attr "type" "imul")
1817 (set_attr "mode" "SI")
1818 (set_attr "length" "12")])
1820 (define_insn_and_split "<u>mulsidi3_64bit"
1821 [(set (match_operand:DI 0 "register_operand" "=d")
1822 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1823 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1824 (clobber (match_scratch:TI 3 "=x"))
1825 (clobber (match_scratch:DI 4 "=d"))]
1826 "TARGET_64BIT && !TARGET_FIX_R4000"
1828 "&& reload_completed"
1830 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1831 (any_extend:DI (match_dup 2)))]
1834 ;; OP4 <- LO, OP0 <- HI
1835 (set (match_dup 4) (match_dup 5))
1836 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1840 (ashift:DI (match_dup 4)
1843 (lshiftrt:DI (match_dup 4)
1846 ;; Shift OP0 into place.
1848 (ashift:DI (match_dup 0)
1851 ;; OR the two halves together
1853 (ior:DI (match_dup 0)
1855 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1856 [(set_attr "type" "imul")
1857 (set_attr "mode" "SI")
1858 (set_attr "length" "24")])
1860 (define_insn "<u>mulsidi3_64bit_hilo"
1861 [(set (match_operand:TI 0 "register_operand" "=x")
1864 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1865 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1867 "TARGET_64BIT && !TARGET_FIX_R4000"
1869 [(set_attr "type" "imul")
1870 (set_attr "mode" "SI")])
1872 ;; Widening multiply with negation.
1873 (define_insn "*muls<u>_di"
1874 [(set (match_operand:DI 0 "register_operand" "=x")
1877 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1878 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1879 "!TARGET_64BIT && ISA_HAS_MULS"
1881 [(set_attr "type" "imul")
1882 (set_attr "mode" "SI")])
1884 (define_insn "<u>msubsidi4"
1885 [(set (match_operand:DI 0 "register_operand" "=ka")
1887 (match_operand:DI 3 "register_operand" "0")
1889 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1890 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1891 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1894 return "msub<u>\t%q0,%1,%2";
1895 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1896 return "msub<u>\t%1,%2";
1898 return "msac<u>\t$0,%1,%2";
1900 [(set_attr "type" "imadd")
1901 (set_attr "mode" "SI")])
1903 ;; _highpart patterns
1905 (define_expand "<su>mulsi3_highpart"
1906 [(set (match_operand:SI 0 "register_operand")
1909 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1910 (any_extend:DI (match_operand:SI 2 "register_operand")))
1915 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1919 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1924 (define_insn_and_split "<su>mulsi3_highpart_internal"
1925 [(set (match_operand:SI 0 "register_operand" "=d")
1928 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1929 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1931 (clobber (match_scratch:SI 3 "=l"))]
1933 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1934 "&& reload_completed && !TARGET_FIX_R4000"
1941 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1942 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1943 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1947 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1948 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1949 emit_insn (gen_mfhisi_di (operands[0], hilo));
1953 [(set_attr "type" "imul")
1954 (set_attr "mode" "SI")
1955 (set_attr "length" "8")])
1957 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1958 [(set (match_operand:SI 0 "register_operand" "=d")
1962 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1963 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1965 (clobber (match_scratch:SI 3 "=l"))]
1967 "mulhi<u>\t%0,%1,%2"
1968 [(set_attr "type" "imul3")
1969 (set_attr "mode" "SI")])
1971 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1972 [(set (match_operand:SI 0 "register_operand" "=d")
1977 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1978 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1980 (clobber (match_scratch:SI 3 "=l"))]
1982 "mulshi<u>\t%0,%1,%2"
1983 [(set_attr "type" "imul3")
1984 (set_attr "mode" "SI")])
1986 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1987 ;; errata MD(0), which says that dmultu does not always produce the
1989 (define_insn_and_split "<su>muldi3_highpart"
1990 [(set (match_operand:DI 0 "register_operand" "=d")
1993 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1994 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1996 (clobber (match_scratch:DI 3 "=l"))]
1997 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1998 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1999 "&& reload_completed && !TARGET_FIX_R4000"
2004 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2005 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2006 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2009 [(set_attr "type" "imul")
2010 (set_attr "mode" "DI")
2011 (set_attr "length" "8")])
2013 (define_expand "<u>mulditi3"
2014 [(set (match_operand:TI 0 "register_operand")
2015 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2016 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2017 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2019 if (TARGET_FIX_R4000)
2020 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2022 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2027 (define_insn "<u>mulditi3_internal"
2028 [(set (match_operand:TI 0 "register_operand" "=x")
2029 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2030 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2032 && !TARGET_FIX_R4000
2033 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2035 [(set_attr "type" "imul")
2036 (set_attr "mode" "DI")])
2038 (define_insn "<u>mulditi3_r4000"
2039 [(set (match_operand:TI 0 "register_operand" "=d")
2040 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2041 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2042 (clobber (match_scratch:TI 3 "=x"))]
2045 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2046 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2047 [(set_attr "type" "imul")
2048 (set_attr "mode" "DI")
2049 (set_attr "length" "12")])
2051 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2052 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2054 (define_insn "madsi"
2055 [(set (match_operand:SI 0 "register_operand" "+l")
2056 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2057 (match_operand:SI 2 "register_operand" "d"))
2061 [(set_attr "type" "imadd")
2062 (set_attr "mode" "SI")])
2064 (define_insn "<u>maddsidi4"
2065 [(set (match_operand:DI 0 "register_operand" "=ka")
2067 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2068 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2069 (match_operand:DI 3 "register_operand" "0")))]
2070 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2074 return "mad<u>\t%1,%2";
2075 else if (ISA_HAS_DSPR2)
2076 return "madd<u>\t%q0,%1,%2";
2077 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2078 return "madd<u>\t%1,%2";
2080 /* See comment in *macc. */
2081 return "%[macc<u>\t%@,%1,%2%]";
2083 [(set_attr "type" "imadd")
2084 (set_attr "mode" "SI")])
2086 ;; Floating point multiply accumulate instructions.
2088 (define_insn "*madd4<mode>"
2089 [(set (match_operand:ANYF 0 "register_operand" "=f")
2090 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2091 (match_operand:ANYF 2 "register_operand" "f"))
2092 (match_operand:ANYF 3 "register_operand" "f")))]
2093 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2094 "madd.<fmt>\t%0,%3,%1,%2"
2095 [(set_attr "type" "fmadd")
2096 (set_attr "mode" "<UNITMODE>")])
2098 (define_insn "*madd3<mode>"
2099 [(set (match_operand:ANYF 0 "register_operand" "=f")
2100 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2101 (match_operand:ANYF 2 "register_operand" "f"))
2102 (match_operand:ANYF 3 "register_operand" "0")))]
2103 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2104 "madd.<fmt>\t%0,%1,%2"
2105 [(set_attr "type" "fmadd")
2106 (set_attr "mode" "<UNITMODE>")])
2108 (define_insn "*msub4<mode>"
2109 [(set (match_operand:ANYF 0 "register_operand" "=f")
2110 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2111 (match_operand:ANYF 2 "register_operand" "f"))
2112 (match_operand:ANYF 3 "register_operand" "f")))]
2113 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2114 "msub.<fmt>\t%0,%3,%1,%2"
2115 [(set_attr "type" "fmadd")
2116 (set_attr "mode" "<UNITMODE>")])
2118 (define_insn "*msub3<mode>"
2119 [(set (match_operand:ANYF 0 "register_operand" "=f")
2120 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2121 (match_operand:ANYF 2 "register_operand" "f"))
2122 (match_operand:ANYF 3 "register_operand" "0")))]
2123 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2124 "msub.<fmt>\t%0,%1,%2"
2125 [(set_attr "type" "fmadd")
2126 (set_attr "mode" "<UNITMODE>")])
2128 (define_insn "*nmadd4<mode>"
2129 [(set (match_operand:ANYF 0 "register_operand" "=f")
2130 (neg:ANYF (plus:ANYF
2131 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2132 (match_operand:ANYF 2 "register_operand" "f"))
2133 (match_operand:ANYF 3 "register_operand" "f"))))]
2134 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2135 && TARGET_FUSED_MADD
2136 && HONOR_SIGNED_ZEROS (<MODE>mode)
2137 && !HONOR_NANS (<MODE>mode)"
2138 "nmadd.<fmt>\t%0,%3,%1,%2"
2139 [(set_attr "type" "fmadd")
2140 (set_attr "mode" "<UNITMODE>")])
2142 (define_insn "*nmadd3<mode>"
2143 [(set (match_operand:ANYF 0 "register_operand" "=f")
2144 (neg:ANYF (plus:ANYF
2145 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2146 (match_operand:ANYF 2 "register_operand" "f"))
2147 (match_operand:ANYF 3 "register_operand" "0"))))]
2148 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2149 && TARGET_FUSED_MADD
2150 && HONOR_SIGNED_ZEROS (<MODE>mode)
2151 && !HONOR_NANS (<MODE>mode)"
2152 "nmadd.<fmt>\t%0,%1,%2"
2153 [(set_attr "type" "fmadd")
2154 (set_attr "mode" "<UNITMODE>")])
2156 (define_insn "*nmadd4<mode>_fastmath"
2157 [(set (match_operand:ANYF 0 "register_operand" "=f")
2159 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2160 (match_operand:ANYF 2 "register_operand" "f"))
2161 (match_operand:ANYF 3 "register_operand" "f")))]
2162 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2163 && TARGET_FUSED_MADD
2164 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2165 && !HONOR_NANS (<MODE>mode)"
2166 "nmadd.<fmt>\t%0,%3,%1,%2"
2167 [(set_attr "type" "fmadd")
2168 (set_attr "mode" "<UNITMODE>")])
2170 (define_insn "*nmadd3<mode>_fastmath"
2171 [(set (match_operand:ANYF 0 "register_operand" "=f")
2173 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2174 (match_operand:ANYF 2 "register_operand" "f"))
2175 (match_operand:ANYF 3 "register_operand" "0")))]
2176 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2177 && TARGET_FUSED_MADD
2178 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2179 && !HONOR_NANS (<MODE>mode)"
2180 "nmadd.<fmt>\t%0,%1,%2"
2181 [(set_attr "type" "fmadd")
2182 (set_attr "mode" "<UNITMODE>")])
2184 (define_insn "*nmsub4<mode>"
2185 [(set (match_operand:ANYF 0 "register_operand" "=f")
2186 (neg:ANYF (minus:ANYF
2187 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2188 (match_operand:ANYF 3 "register_operand" "f"))
2189 (match_operand:ANYF 1 "register_operand" "f"))))]
2190 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2191 && TARGET_FUSED_MADD
2192 && HONOR_SIGNED_ZEROS (<MODE>mode)
2193 && !HONOR_NANS (<MODE>mode)"
2194 "nmsub.<fmt>\t%0,%1,%2,%3"
2195 [(set_attr "type" "fmadd")
2196 (set_attr "mode" "<UNITMODE>")])
2198 (define_insn "*nmsub3<mode>"
2199 [(set (match_operand:ANYF 0 "register_operand" "=f")
2200 (neg:ANYF (minus:ANYF
2201 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2202 (match_operand:ANYF 3 "register_operand" "f"))
2203 (match_operand:ANYF 1 "register_operand" "0"))))]
2204 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2205 && TARGET_FUSED_MADD
2206 && HONOR_SIGNED_ZEROS (<MODE>mode)
2207 && !HONOR_NANS (<MODE>mode)"
2208 "nmsub.<fmt>\t%0,%1,%2"
2209 [(set_attr "type" "fmadd")
2210 (set_attr "mode" "<UNITMODE>")])
2212 (define_insn "*nmsub4<mode>_fastmath"
2213 [(set (match_operand:ANYF 0 "register_operand" "=f")
2215 (match_operand:ANYF 1 "register_operand" "f")
2216 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2217 (match_operand:ANYF 3 "register_operand" "f"))))]
2218 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2219 && TARGET_FUSED_MADD
2220 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2221 && !HONOR_NANS (<MODE>mode)"
2222 "nmsub.<fmt>\t%0,%1,%2,%3"
2223 [(set_attr "type" "fmadd")
2224 (set_attr "mode" "<UNITMODE>")])
2226 (define_insn "*nmsub3<mode>_fastmath"
2227 [(set (match_operand:ANYF 0 "register_operand" "=f")
2229 (match_operand:ANYF 1 "register_operand" "f")
2230 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2231 (match_operand:ANYF 3 "register_operand" "0"))))]
2232 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2233 && TARGET_FUSED_MADD
2234 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2235 && !HONOR_NANS (<MODE>mode)"
2236 "nmsub.<fmt>\t%0,%1,%2"
2237 [(set_attr "type" "fmadd")
2238 (set_attr "mode" "<UNITMODE>")])
2241 ;; ....................
2243 ;; DIVISION and REMAINDER
2245 ;; ....................
2248 (define_expand "div<mode>3"
2249 [(set (match_operand:ANYF 0 "register_operand")
2250 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2251 (match_operand:ANYF 2 "register_operand")))]
2252 "<divide_condition>"
2254 if (const_1_operand (operands[1], <MODE>mode))
2255 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2256 operands[1] = force_reg (<MODE>mode, operands[1]);
2259 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2261 ;; If an mfc1 or dmfc1 happens to access the floating point register
2262 ;; file at the same time a long latency operation (div, sqrt, recip,
2263 ;; sqrt) iterates an intermediate result back through the floating
2264 ;; point register file bypass, then instead returning the correct
2265 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2266 ;; result of the long latency operation.
2268 ;; The workaround is to insert an unconditional 'mov' from/to the
2269 ;; long latency op destination register.
2271 (define_insn "*div<mode>3"
2272 [(set (match_operand:ANYF 0 "register_operand" "=f")
2273 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2274 (match_operand:ANYF 2 "register_operand" "f")))]
2275 "<divide_condition>"
2278 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2280 return "div.<fmt>\t%0,%1,%2";
2282 [(set_attr "type" "fdiv")
2283 (set_attr "mode" "<UNITMODE>")
2284 (set (attr "length")
2285 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2289 (define_insn "*recip<mode>3"
2290 [(set (match_operand:ANYF 0 "register_operand" "=f")
2291 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2292 (match_operand:ANYF 2 "register_operand" "f")))]
2293 "<recip_condition> && flag_unsafe_math_optimizations"
2296 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2298 return "recip.<fmt>\t%0,%2";
2300 [(set_attr "type" "frdiv")
2301 (set_attr "mode" "<UNITMODE>")
2302 (set (attr "length")
2303 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2307 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2308 ;; with negative operands. We use special libgcc functions instead.
2309 (define_insn_and_split "divmod<mode>4"
2310 [(set (match_operand:GPR 0 "register_operand" "=l")
2311 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2312 (match_operand:GPR 2 "register_operand" "d")))
2313 (set (match_operand:GPR 3 "register_operand" "=d")
2314 (mod:GPR (match_dup 1)
2316 "!TARGET_FIX_VR4120"
2318 "&& reload_completed"
2325 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2326 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2327 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2331 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2332 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2333 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2337 [(set_attr "type" "idiv")
2338 (set_attr "mode" "<MODE>")
2339 (set_attr "length" "8")])
2341 (define_insn_and_split "udivmod<mode>4"
2342 [(set (match_operand:GPR 0 "register_operand" "=l")
2343 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2344 (match_operand:GPR 2 "register_operand" "d")))
2345 (set (match_operand:GPR 3 "register_operand" "=d")
2346 (umod:GPR (match_dup 1)
2357 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2358 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2359 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2363 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2364 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2365 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2369 [(set_attr "type" "idiv")
2370 (set_attr "mode" "<MODE>")
2371 (set_attr "length" "8")])
2373 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2374 [(set (match_operand:HILO 0 "register_operand" "=x")
2376 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2377 (match_operand:GPR 2 "register_operand" "d"))]
2380 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2381 [(set_attr "type" "idiv")
2382 (set_attr "mode" "<GPR:MODE>")])
2385 ;; ....................
2389 ;; ....................
2391 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2392 ;; "*div[sd]f3" comment for details).
2394 (define_insn "sqrt<mode>2"
2395 [(set (match_operand:ANYF 0 "register_operand" "=f")
2396 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2400 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2402 return "sqrt.<fmt>\t%0,%1";
2404 [(set_attr "type" "fsqrt")
2405 (set_attr "mode" "<UNITMODE>")
2406 (set (attr "length")
2407 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2411 (define_insn "*rsqrt<mode>a"
2412 [(set (match_operand:ANYF 0 "register_operand" "=f")
2413 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2414 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2415 "<recip_condition> && flag_unsafe_math_optimizations"
2418 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2420 return "rsqrt.<fmt>\t%0,%2";
2422 [(set_attr "type" "frsqrt")
2423 (set_attr "mode" "<UNITMODE>")
2424 (set (attr "length")
2425 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2429 (define_insn "*rsqrt<mode>b"
2430 [(set (match_operand:ANYF 0 "register_operand" "=f")
2431 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2432 (match_operand:ANYF 2 "register_operand" "f"))))]
2433 "<recip_condition> && flag_unsafe_math_optimizations"
2436 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2438 return "rsqrt.<fmt>\t%0,%2";
2440 [(set_attr "type" "frsqrt")
2441 (set_attr "mode" "<UNITMODE>")
2442 (set (attr "length")
2443 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2448 ;; ....................
2452 ;; ....................
2454 ;; Do not use the integer abs macro instruction, since that signals an
2455 ;; exception on -2147483648 (sigh).
2457 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2458 ;; invalid; it does not clear their sign bits. We therefore can't use
2459 ;; abs.fmt if the signs of NaNs matter.
2461 (define_insn "abs<mode>2"
2462 [(set (match_operand:ANYF 0 "register_operand" "=f")
2463 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2464 "!HONOR_NANS (<MODE>mode)"
2466 [(set_attr "type" "fabs")
2467 (set_attr "mode" "<UNITMODE>")])
2470 ;; ...................
2472 ;; Count leading zeroes.
2474 ;; ...................
2477 (define_insn "clz<mode>2"
2478 [(set (match_operand:GPR 0 "register_operand" "=d")
2479 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2482 [(set_attr "type" "clz")
2483 (set_attr "mode" "<MODE>")])
2486 ;; ...................
2488 ;; Count number of set bits.
2490 ;; ...................
2493 (define_insn "popcount<mode>2"
2494 [(set (match_operand:GPR 0 "register_operand" "=d")
2495 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2498 [(set_attr "type" "pop")
2499 (set_attr "mode" "<MODE>")])
2502 ;; ....................
2504 ;; NEGATION and ONE'S COMPLEMENT
2506 ;; ....................
2508 (define_insn "negsi2"
2509 [(set (match_operand:SI 0 "register_operand" "=d")
2510 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2514 return "neg\t%0,%1";
2516 return "subu\t%0,%.,%1";
2518 [(set_attr "type" "arith")
2519 (set_attr "mode" "SI")])
2521 (define_insn "negdi2"
2522 [(set (match_operand:DI 0 "register_operand" "=d")
2523 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2524 "TARGET_64BIT && !TARGET_MIPS16"
2526 [(set_attr "type" "arith")
2527 (set_attr "mode" "DI")])
2529 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2530 ;; invalid; it does not flip their sign bit. We therefore can't use
2531 ;; neg.fmt if the signs of NaNs matter.
2533 (define_insn "neg<mode>2"
2534 [(set (match_operand:ANYF 0 "register_operand" "=f")
2535 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2536 "!HONOR_NANS (<MODE>mode)"
2538 [(set_attr "type" "fneg")
2539 (set_attr "mode" "<UNITMODE>")])
2541 (define_insn "one_cmpl<mode>2"
2542 [(set (match_operand:GPR 0 "register_operand" "=d")
2543 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2547 return "not\t%0,%1";
2549 return "nor\t%0,%.,%1";
2551 [(set_attr "type" "logical")
2552 (set_attr "mode" "<MODE>")])
2555 ;; ....................
2559 ;; ....................
2562 ;; Many of these instructions use trivial define_expands, because we
2563 ;; want to use a different set of constraints when TARGET_MIPS16.
2565 (define_expand "and<mode>3"
2566 [(set (match_operand:GPR 0 "register_operand")
2567 (and:GPR (match_operand:GPR 1 "register_operand")
2568 (match_operand:GPR 2 "and_reg_operand")))])
2570 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2571 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2572 ;; Note that this variant does not trigger for SI mode because we require
2573 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2574 ;; sign-extended SImode value.
2576 ;; These are possible combinations for operand 1 and 2. The table
2577 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2578 ;; 16=MIPS16, x=match, S=split):
2580 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2586 ;; 0xffff_ffff x S x S x
2591 (define_insn "*and<mode>3"
2592 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2593 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2594 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2595 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2599 switch (which_alternative)
2602 operands[1] = gen_lowpart (QImode, operands[1]);
2603 return "lbu\t%0,%1";
2605 operands[1] = gen_lowpart (HImode, operands[1]);
2606 return "lhu\t%0,%1";
2608 operands[1] = gen_lowpart (SImode, operands[1]);
2609 return "lwu\t%0,%1";
2611 return "andi\t%0,%1,%x2";
2613 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2614 operands[2] = GEN_INT (len);
2615 return "<d>ext\t%0,%1,0,%2";
2619 return "and\t%0,%1,%2";
2624 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2625 (set_attr "mode" "<MODE>")])
2627 (define_insn "*and<mode>3_mips16"
2628 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2629 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2630 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2631 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2633 switch (which_alternative)
2636 operands[1] = gen_lowpart (QImode, operands[1]);
2637 return "lbu\t%0,%1";
2639 operands[1] = gen_lowpart (HImode, operands[1]);
2640 return "lhu\t%0,%1";
2642 operands[1] = gen_lowpart (SImode, operands[1]);
2643 return "lwu\t%0,%1";
2647 return "and\t%0,%2";
2652 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2653 (set_attr "mode" "<MODE>")])
2655 (define_expand "ior<mode>3"
2656 [(set (match_operand:GPR 0 "register_operand")
2657 (ior:GPR (match_operand:GPR 1 "register_operand")
2658 (match_operand:GPR 2 "uns_arith_operand")))]
2662 operands[2] = force_reg (<MODE>mode, operands[2]);
2665 (define_insn "*ior<mode>3"
2666 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2667 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2668 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2673 [(set_attr "type" "logical")
2674 (set_attr "mode" "<MODE>")])
2676 (define_insn "*ior<mode>3_mips16"
2677 [(set (match_operand:GPR 0 "register_operand" "=d")
2678 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2679 (match_operand:GPR 2 "register_operand" "d")))]
2682 [(set_attr "type" "logical")
2683 (set_attr "mode" "<MODE>")])
2685 (define_expand "xor<mode>3"
2686 [(set (match_operand:GPR 0 "register_operand")
2687 (xor:GPR (match_operand:GPR 1 "register_operand")
2688 (match_operand:GPR 2 "uns_arith_operand")))]
2693 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2694 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2695 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2700 [(set_attr "type" "logical")
2701 (set_attr "mode" "<MODE>")])
2704 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2705 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2706 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2712 [(set_attr "type" "logical,arith,arith")
2713 (set_attr "mode" "<MODE>")
2714 (set_attr_alternative "length"
2716 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2721 (define_insn "*nor<mode>3"
2722 [(set (match_operand:GPR 0 "register_operand" "=d")
2723 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2724 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2727 [(set_attr "type" "logical")
2728 (set_attr "mode" "<MODE>")])
2731 ;; ....................
2735 ;; ....................
2739 (define_insn "truncdfsf2"
2740 [(set (match_operand:SF 0 "register_operand" "=f")
2741 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2742 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2744 [(set_attr "type" "fcvt")
2745 (set_attr "cnv_mode" "D2S")
2746 (set_attr "mode" "SF")])
2748 ;; Integer truncation patterns. Truncating SImode values to smaller
2749 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2750 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2751 ;; need to make sure that the lower 32 bits are properly sign-extended
2752 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2753 ;; smaller than SImode is equivalent to two separate truncations:
2756 ;; DI ---> HI == DI ---> SI ---> HI
2757 ;; DI ---> QI == DI ---> SI ---> QI
2759 ;; Step A needs a real instruction but step B does not.
2761 (define_insn "truncdi<mode>2"
2762 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
2763 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
2768 [(set_attr "move_type" "sll0,store")
2769 (set_attr "mode" "SI")])
2771 ;; Combiner patterns to optimize shift/truncate combinations.
2773 (define_insn "*ashr_trunc<mode>"
2774 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2776 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2777 (match_operand:DI 2 "const_arith_operand" ""))))]
2778 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2780 [(set_attr "type" "shift")
2781 (set_attr "mode" "<MODE>")])
2783 (define_insn "*lshr32_trunc<mode>"
2784 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2786 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2788 "TARGET_64BIT && !TARGET_MIPS16"
2790 [(set_attr "type" "shift")
2791 (set_attr "mode" "<MODE>")])
2793 ;; Logical shift by 32 or more results in proper SI values so
2794 ;; truncation is removed by the middle end.
2795 (define_insn "*<optab>_trunc<mode>_exts"
2796 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2798 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2799 (match_operand:DI 2 "const_arith_operand" ""))))]
2800 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2802 [(set_attr "type" "arith")
2803 (set_attr "mode" "<MODE>")])
2806 ;; ....................
2810 ;; ....................
2814 (define_expand "zero_extendsidi2"
2815 [(set (match_operand:DI 0 "register_operand")
2816 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
2819 (define_insn_and_split "*zero_extendsidi2"
2820 [(set (match_operand:DI 0 "register_operand" "=d,d")
2821 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2822 "TARGET_64BIT && !ISA_HAS_EXT_INS"
2826 "&& reload_completed && REG_P (operands[1])"
2828 (ashift:DI (match_dup 1) (const_int 32)))
2830 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2831 { operands[1] = gen_lowpart (DImode, operands[1]); }
2832 [(set_attr "move_type" "shift_shift,load")
2833 (set_attr "mode" "DI")])
2835 (define_insn "*zero_extendsidi2_dext"
2836 [(set (match_operand:DI 0 "register_operand" "=d,d")
2837 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2838 "TARGET_64BIT && ISA_HAS_EXT_INS"
2842 [(set_attr "move_type" "arith,load")
2843 (set_attr "mode" "DI")])
2845 ;; See the comment before the *and<mode>3 pattern why this is generated by
2849 [(set (match_operand:DI 0 "register_operand")
2850 (and:DI (match_operand:DI 1 "register_operand")
2851 (const_int 4294967295)))]
2852 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
2854 (ashift:DI (match_dup 1) (const_int 32)))
2856 (lshiftrt:DI (match_dup 0) (const_int 32)))])
2858 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2859 [(set (match_operand:GPR 0 "register_operand")
2860 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2863 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2864 && !memory_operand (operands[1], <SHORT:MODE>mode))
2866 emit_insn (gen_and<GPR:mode>3 (operands[0],
2867 gen_lowpart (<GPR:MODE>mode, operands[1]),
2868 force_reg (<GPR:MODE>mode,
2869 GEN_INT (<SHORT:mask>))));
2874 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2875 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2877 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2880 andi\t%0,%1,<SHORT:mask>
2881 l<SHORT:size>u\t%0,%1"
2882 [(set_attr "move_type" "andi,load")
2883 (set_attr "mode" "<GPR:MODE>")])
2885 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2886 [(set (match_operand:GPR 0 "register_operand" "=d")
2887 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2889 "ze<SHORT:size>\t%0"
2890 ;; This instruction is effectively a special encoding of ANDI.
2891 [(set_attr "move_type" "andi")
2892 (set_attr "mode" "<GPR:MODE>")])
2894 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2895 [(set (match_operand:GPR 0 "register_operand" "=d")
2896 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2898 "l<SHORT:size>u\t%0,%1"
2899 [(set_attr "move_type" "load")
2900 (set_attr "mode" "<GPR:MODE>")])
2902 (define_expand "zero_extendqihi2"
2903 [(set (match_operand:HI 0 "register_operand")
2904 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2907 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2909 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2915 (define_insn "*zero_extendqihi2"
2916 [(set (match_operand:HI 0 "register_operand" "=d,d")
2917 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2922 [(set_attr "move_type" "andi,load")
2923 (set_attr "mode" "HI")])
2925 (define_insn "*zero_extendqihi2_mips16"
2926 [(set (match_operand:HI 0 "register_operand" "=d")
2927 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2930 [(set_attr "move_type" "load")
2931 (set_attr "mode" "HI")])
2933 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2935 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
2936 [(set (match_operand:GPR 0 "register_operand" "=d")
2938 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2939 "TARGET_64BIT && !TARGET_MIPS16"
2941 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
2942 return "andi\t%0,%1,%x2";
2944 [(set_attr "type" "logical")
2945 (set_attr "mode" "<GPR:MODE>")])
2947 (define_insn "*zero_extendhi_truncqi"
2948 [(set (match_operand:HI 0 "register_operand" "=d")
2950 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2951 "TARGET_64BIT && !TARGET_MIPS16"
2953 [(set_attr "type" "logical")
2954 (set_attr "mode" "HI")])
2957 ;; ....................
2961 ;; ....................
2964 ;; Those for integer source operand are ordered widest source type first.
2966 ;; When TARGET_64BIT, all SImode integer registers should already be in
2967 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2968 ;; therefore get rid of register->register instructions if we constrain
2969 ;; the source to be in the same register as the destination.
2971 ;; The register alternative has type "arith" so that the pre-reload
2972 ;; scheduler will treat it as a move. This reflects what happens if
2973 ;; the register alternative needs a reload.
2974 (define_insn_and_split "extendsidi2"
2975 [(set (match_operand:DI 0 "register_operand" "=d,d")
2976 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2981 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2984 emit_note (NOTE_INSN_DELETED);
2987 [(set_attr "move_type" "move,load")
2988 (set_attr "mode" "DI")])
2990 (define_expand "extend<SHORT:mode><GPR:mode>2"
2991 [(set (match_operand:GPR 0 "register_operand")
2992 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2995 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2996 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2997 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3001 l<SHORT:size>\t%0,%1"
3002 [(set_attr "move_type" "signext,load")
3003 (set_attr "mode" "<GPR:MODE>")])
3005 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3006 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3008 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3009 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3012 l<SHORT:size>\t%0,%1"
3013 "&& reload_completed && REG_P (operands[1])"
3014 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3015 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3017 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3018 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3019 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3021 [(set_attr "move_type" "shift_shift,load")
3022 (set_attr "mode" "<GPR:MODE>")])
3024 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3025 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3027 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3030 se<SHORT:size>\t%0,%1
3031 l<SHORT:size>\t%0,%1"
3032 [(set_attr "move_type" "signext,load")
3033 (set_attr "mode" "<GPR:MODE>")])
3035 (define_expand "extendqihi2"
3036 [(set (match_operand:HI 0 "register_operand")
3037 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3040 (define_insn "*extendqihi2_mips16e"
3041 [(set (match_operand:HI 0 "register_operand" "=d,d")
3042 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3047 [(set_attr "move_type" "signext,load")
3048 (set_attr "mode" "SI")])
3050 (define_insn_and_split "*extendqihi2"
3051 [(set (match_operand:HI 0 "register_operand" "=d,d")
3053 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3054 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3058 "&& reload_completed && REG_P (operands[1])"
3059 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3060 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3062 operands[0] = gen_lowpart (SImode, operands[0]);
3063 operands[1] = gen_lowpart (SImode, operands[1]);
3064 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3065 - GET_MODE_BITSIZE (QImode));
3067 [(set_attr "move_type" "shift_shift,load")
3068 (set_attr "mode" "SI")])
3070 (define_insn "*extendqihi2_seb"
3071 [(set (match_operand:HI 0 "register_operand" "=d,d")
3073 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3078 [(set_attr "move_type" "signext,load")
3079 (set_attr "mode" "SI")])
3081 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3082 ;; use the shift/truncate patterns.
3084 (define_insn_and_split "*extenddi_truncate<mode>"
3085 [(set (match_operand:DI 0 "register_operand" "=d")
3087 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3088 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3090 "&& reload_completed"
3092 (ashift:DI (match_dup 1)
3095 (ashiftrt:DI (match_dup 2)
3098 operands[2] = gen_lowpart (DImode, operands[0]);
3099 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3101 [(set_attr "move_type" "shift_shift")
3102 (set_attr "mode" "DI")])
3104 (define_insn_and_split "*extendsi_truncate<mode>"
3105 [(set (match_operand:SI 0 "register_operand" "=d")
3107 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3108 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3110 "&& reload_completed"
3112 (ashift:DI (match_dup 1)
3115 (truncate:SI (ashiftrt:DI (match_dup 2)
3118 operands[2] = gen_lowpart (DImode, operands[0]);
3119 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3121 [(set_attr "move_type" "shift_shift")
3122 (set_attr "mode" "SI")])
3124 (define_insn_and_split "*extendhi_truncateqi"
3125 [(set (match_operand:HI 0 "register_operand" "=d")
3127 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3128 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3130 "&& reload_completed"
3132 (ashift:DI (match_dup 1)
3135 (truncate:HI (ashiftrt:DI (match_dup 2)
3138 operands[2] = gen_lowpart (DImode, operands[0]);
3140 [(set_attr "move_type" "shift_shift")
3141 (set_attr "mode" "SI")])
3143 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3144 [(set (match_operand:GPR 0 "register_operand" "=d")
3146 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3147 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3149 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3150 return "exts\t%0,%1,0,%m2";
3152 [(set_attr "type" "arith")
3153 (set_attr "mode" "<GPR:MODE>")])
3155 (define_insn "*extendhi_truncateqi_exts"
3156 [(set (match_operand:HI 0 "register_operand" "=d")
3158 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3159 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3161 [(set_attr "type" "arith")
3162 (set_attr "mode" "SI")])
3164 (define_insn "extendsfdf2"
3165 [(set (match_operand:DF 0 "register_operand" "=f")
3166 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3167 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3169 [(set_attr "type" "fcvt")
3170 (set_attr "cnv_mode" "S2D")
3171 (set_attr "mode" "DF")])
3174 ;; ....................
3178 ;; ....................
3180 (define_expand "fix_truncdfsi2"
3181 [(set (match_operand:SI 0 "register_operand")
3182 (fix:SI (match_operand:DF 1 "register_operand")))]
3183 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3185 if (!ISA_HAS_TRUNC_W)
3187 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3192 (define_insn "fix_truncdfsi2_insn"
3193 [(set (match_operand:SI 0 "register_operand" "=f")
3194 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3195 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3197 [(set_attr "type" "fcvt")
3198 (set_attr "mode" "DF")
3199 (set_attr "cnv_mode" "D2I")])
3201 (define_insn "fix_truncdfsi2_macro"
3202 [(set (match_operand:SI 0 "register_operand" "=f")
3203 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3204 (clobber (match_scratch:DF 2 "=d"))]
3205 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3207 if (mips_nomacro.nesting_level > 0)
3208 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3210 return "trunc.w.d %0,%1,%2";
3212 [(set_attr "type" "fcvt")
3213 (set_attr "mode" "DF")
3214 (set_attr "cnv_mode" "D2I")
3215 (set_attr "length" "36")])
3217 (define_expand "fix_truncsfsi2"
3218 [(set (match_operand:SI 0 "register_operand")
3219 (fix:SI (match_operand:SF 1 "register_operand")))]
3222 if (!ISA_HAS_TRUNC_W)
3224 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3229 (define_insn "fix_truncsfsi2_insn"
3230 [(set (match_operand:SI 0 "register_operand" "=f")
3231 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3232 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3234 [(set_attr "type" "fcvt")
3235 (set_attr "mode" "SF")
3236 (set_attr "cnv_mode" "S2I")])
3238 (define_insn "fix_truncsfsi2_macro"
3239 [(set (match_operand:SI 0 "register_operand" "=f")
3240 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3241 (clobber (match_scratch:SF 2 "=d"))]
3242 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3244 if (mips_nomacro.nesting_level > 0)
3245 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3247 return "trunc.w.s %0,%1,%2";
3249 [(set_attr "type" "fcvt")
3250 (set_attr "mode" "SF")
3251 (set_attr "cnv_mode" "S2I")
3252 (set_attr "length" "36")])
3255 (define_insn "fix_truncdfdi2"
3256 [(set (match_operand:DI 0 "register_operand" "=f")
3257 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3258 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3260 [(set_attr "type" "fcvt")
3261 (set_attr "mode" "DF")
3262 (set_attr "cnv_mode" "D2I")])
3265 (define_insn "fix_truncsfdi2"
3266 [(set (match_operand:DI 0 "register_operand" "=f")
3267 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3268 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3270 [(set_attr "type" "fcvt")
3271 (set_attr "mode" "SF")
3272 (set_attr "cnv_mode" "S2I")])
3275 (define_insn "floatsidf2"
3276 [(set (match_operand:DF 0 "register_operand" "=f")
3277 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3278 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3280 [(set_attr "type" "fcvt")
3281 (set_attr "mode" "DF")
3282 (set_attr "cnv_mode" "I2D")])
3285 (define_insn "floatdidf2"
3286 [(set (match_operand:DF 0 "register_operand" "=f")
3287 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3288 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3290 [(set_attr "type" "fcvt")
3291 (set_attr "mode" "DF")
3292 (set_attr "cnv_mode" "I2D")])
3295 (define_insn "floatsisf2"
3296 [(set (match_operand:SF 0 "register_operand" "=f")
3297 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3300 [(set_attr "type" "fcvt")
3301 (set_attr "mode" "SF")
3302 (set_attr "cnv_mode" "I2S")])
3305 (define_insn "floatdisf2"
3306 [(set (match_operand:SF 0 "register_operand" "=f")
3307 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3308 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3310 [(set_attr "type" "fcvt")
3311 (set_attr "mode" "SF")
3312 (set_attr "cnv_mode" "I2S")])
3315 (define_expand "fixuns_truncdfsi2"
3316 [(set (match_operand:SI 0 "register_operand")
3317 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3318 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3320 rtx reg1 = gen_reg_rtx (DFmode);
3321 rtx reg2 = gen_reg_rtx (DFmode);
3322 rtx reg3 = gen_reg_rtx (SImode);
3323 rtx label1 = gen_label_rtx ();
3324 rtx label2 = gen_label_rtx ();
3326 REAL_VALUE_TYPE offset;
3328 real_2expN (&offset, 31, DFmode);
3330 if (reg1) /* Turn off complaints about unreached code. */
3332 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3333 do_pending_stack_adjust ();
3335 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3336 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3338 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3339 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3340 gen_rtx_LABEL_REF (VOIDmode, label2)));
3343 emit_label (label1);
3344 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3345 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3346 (BITMASK_HIGH, SImode)));
3348 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3349 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3351 emit_label (label2);
3353 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3354 fields, and can't be used for REG_NOTES anyway). */
3355 emit_use (stack_pointer_rtx);
3361 (define_expand "fixuns_truncdfdi2"
3362 [(set (match_operand:DI 0 "register_operand")
3363 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3364 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3366 rtx reg1 = gen_reg_rtx (DFmode);
3367 rtx reg2 = gen_reg_rtx (DFmode);
3368 rtx reg3 = gen_reg_rtx (DImode);
3369 rtx label1 = gen_label_rtx ();
3370 rtx label2 = gen_label_rtx ();
3372 REAL_VALUE_TYPE offset;
3374 real_2expN (&offset, 63, DFmode);
3376 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3377 do_pending_stack_adjust ();
3379 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3380 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3382 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3383 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3384 gen_rtx_LABEL_REF (VOIDmode, label2)));
3387 emit_label (label1);
3388 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3389 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3390 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3392 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3393 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3395 emit_label (label2);
3397 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3398 fields, and can't be used for REG_NOTES anyway). */
3399 emit_use (stack_pointer_rtx);
3404 (define_expand "fixuns_truncsfsi2"
3405 [(set (match_operand:SI 0 "register_operand")
3406 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3409 rtx reg1 = gen_reg_rtx (SFmode);
3410 rtx reg2 = gen_reg_rtx (SFmode);
3411 rtx reg3 = gen_reg_rtx (SImode);
3412 rtx label1 = gen_label_rtx ();
3413 rtx label2 = gen_label_rtx ();
3415 REAL_VALUE_TYPE offset;
3417 real_2expN (&offset, 31, SFmode);
3419 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3420 do_pending_stack_adjust ();
3422 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3423 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3425 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3426 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3427 gen_rtx_LABEL_REF (VOIDmode, label2)));
3430 emit_label (label1);
3431 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3432 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3433 (BITMASK_HIGH, SImode)));
3435 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3436 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3438 emit_label (label2);
3440 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3441 fields, and can't be used for REG_NOTES anyway). */
3442 emit_use (stack_pointer_rtx);
3447 (define_expand "fixuns_truncsfdi2"
3448 [(set (match_operand:DI 0 "register_operand")
3449 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3450 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3452 rtx reg1 = gen_reg_rtx (SFmode);
3453 rtx reg2 = gen_reg_rtx (SFmode);
3454 rtx reg3 = gen_reg_rtx (DImode);
3455 rtx label1 = gen_label_rtx ();
3456 rtx label2 = gen_label_rtx ();
3458 REAL_VALUE_TYPE offset;
3460 real_2expN (&offset, 63, SFmode);
3462 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3463 do_pending_stack_adjust ();
3465 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3466 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3468 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3469 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3470 gen_rtx_LABEL_REF (VOIDmode, label2)));
3473 emit_label (label1);
3474 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3475 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3476 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3478 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3479 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3481 emit_label (label2);
3483 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3484 fields, and can't be used for REG_NOTES anyway). */
3485 emit_use (stack_pointer_rtx);
3490 ;; ....................
3494 ;; ....................
3496 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3498 (define_expand "extv"
3499 [(set (match_operand 0 "register_operand")
3500 (sign_extract (match_operand 1 "nonimmediate_operand")
3501 (match_operand 2 "const_int_operand")
3502 (match_operand 3 "const_int_operand")))]
3505 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3506 INTVAL (operands[2]),
3507 INTVAL (operands[3])))
3509 else if (register_operand (operands[1], GET_MODE (operands[0]))
3510 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3512 if (GET_MODE (operands[0]) == DImode)
3513 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3516 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3524 (define_insn "extv<mode>"
3525 [(set (match_operand:GPR 0 "register_operand" "=d")
3526 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3527 (match_operand 2 "const_int_operand" "")
3528 (match_operand 3 "const_int_operand" "")))]
3529 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3530 "exts\t%0,%1,%3,%m2"
3531 [(set_attr "type" "arith")
3532 (set_attr "mode" "<MODE>")])
3535 (define_expand "extzv"
3536 [(set (match_operand 0 "register_operand")
3537 (zero_extract (match_operand 1 "nonimmediate_operand")
3538 (match_operand 2 "const_int_operand")
3539 (match_operand 3 "const_int_operand")))]
3542 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3543 INTVAL (operands[2]),
3544 INTVAL (operands[3])))
3546 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3547 INTVAL (operands[3])))
3549 if (GET_MODE (operands[0]) == DImode)
3550 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3553 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3561 (define_insn "extzv<mode>"
3562 [(set (match_operand:GPR 0 "register_operand" "=d")
3563 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3564 (match_operand 2 "const_int_operand" "")
3565 (match_operand 3 "const_int_operand" "")))]
3566 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3567 INTVAL (operands[3]))"
3568 "<d>ext\t%0,%1,%3,%2"
3569 [(set_attr "type" "arith")
3570 (set_attr "mode" "<MODE>")])
3572 (define_insn "*extzv_truncsi_exts"
3573 [(set (match_operand:SI 0 "register_operand" "=d")
3575 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3576 (match_operand 2 "const_int_operand" "")
3577 (match_operand 3 "const_int_operand" ""))))]
3578 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3580 [(set_attr "type" "arith")
3581 (set_attr "mode" "SI")])
3584 (define_expand "insv"
3585 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3586 (match_operand 1 "immediate_operand")
3587 (match_operand 2 "immediate_operand"))
3588 (match_operand 3 "reg_or_0_operand"))]
3591 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3592 INTVAL (operands[1]),
3593 INTVAL (operands[2])))
3595 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3596 INTVAL (operands[2])))
3598 if (GET_MODE (operands[0]) == DImode)
3599 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3602 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3610 (define_insn "insv<mode>"
3611 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3612 (match_operand:SI 1 "immediate_operand" "I")
3613 (match_operand:SI 2 "immediate_operand" "I"))
3614 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3615 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3616 INTVAL (operands[2]))"
3617 "<d>ins\t%0,%z3,%2,%1"
3618 [(set_attr "type" "arith")
3619 (set_attr "mode" "<MODE>")])
3621 ;; Combiner pattern for cins (clear and insert bit field). We can
3622 ;; implement mask-and-shift-left operation with this. Note that if
3623 ;; the upper bit of the mask is set in an SImode operation, the mask
3624 ;; itself will be sign-extended. mask_low_and_shift_len will
3625 ;; therefore be greater than our threshold of 32.
3627 (define_insn "*cins<mode>"
3628 [(set (match_operand:GPR 0 "register_operand" "=d")
3630 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3631 (match_operand:GPR 2 "const_int_operand" ""))
3632 (match_operand:GPR 3 "const_int_operand" "")))]
3634 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3637 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3638 return "cins\t%0,%1,%2,%m3";
3640 [(set_attr "type" "shift")
3641 (set_attr "mode" "<MODE>")])
3643 ;; Unaligned word moves generated by the bit field patterns.
3645 ;; As far as the rtl is concerned, both the left-part and right-part
3646 ;; instructions can access the whole field. However, the real operand
3647 ;; refers to just the first or the last byte (depending on endianness).
3648 ;; We therefore use two memory operands to each instruction, one to
3649 ;; describe the rtl effect and one to use in the assembly output.
3651 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3652 ;; This allows us to use the standard length calculations for the "load"
3653 ;; and "store" type attributes.
3655 (define_insn "mov_<load>l"
3656 [(set (match_operand:GPR 0 "register_operand" "=d")
3657 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3658 (match_operand:QI 2 "memory_operand" "m")]
3660 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3662 [(set_attr "move_type" "load")
3663 (set_attr "mode" "<MODE>")])
3665 (define_insn "mov_<load>r"
3666 [(set (match_operand:GPR 0 "register_operand" "=d")
3667 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3668 (match_operand:QI 2 "memory_operand" "m")
3669 (match_operand:GPR 3 "register_operand" "0")]
3670 UNSPEC_LOAD_RIGHT))]
3671 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3673 [(set_attr "move_type" "load")
3674 (set_attr "mode" "<MODE>")])
3676 (define_insn "mov_<store>l"
3677 [(set (match_operand:BLK 0 "memory_operand" "=m")
3678 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3679 (match_operand:QI 2 "memory_operand" "m")]
3680 UNSPEC_STORE_LEFT))]
3681 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3683 [(set_attr "move_type" "store")
3684 (set_attr "mode" "<MODE>")])
3686 (define_insn "mov_<store>r"
3687 [(set (match_operand:BLK 0 "memory_operand" "+m")
3688 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3689 (match_operand:QI 2 "memory_operand" "m")
3691 UNSPEC_STORE_RIGHT))]
3692 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3694 [(set_attr "move_type" "store")
3695 (set_attr "mode" "<MODE>")])
3697 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3698 ;; The required value is:
3700 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3702 ;; which translates to:
3704 ;; lui op0,%highest(op1)
3705 ;; daddiu op0,op0,%higher(op1)
3707 ;; daddiu op0,op0,%hi(op1)
3710 ;; The split is deferred until after flow2 to allow the peephole2 below
3712 (define_insn_and_split "*lea_high64"
3713 [(set (match_operand:DI 0 "register_operand" "=d")
3714 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3715 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3717 "&& epilogue_completed"
3718 [(set (match_dup 0) (high:DI (match_dup 2)))
3719 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3720 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3721 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3722 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3724 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3725 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3727 [(set_attr "length" "20")])
3729 ;; Use a scratch register to reduce the latency of the above pattern
3730 ;; on superscalar machines. The optimized sequence is:
3732 ;; lui op1,%highest(op2)
3734 ;; daddiu op1,op1,%higher(op2)
3736 ;; daddu op1,op1,op0
3738 [(set (match_operand:DI 1 "d_operand")
3739 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3740 (match_scratch:DI 0 "d")]
3741 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3742 [(set (match_dup 1) (high:DI (match_dup 3)))
3743 (set (match_dup 0) (high:DI (match_dup 4)))
3744 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3745 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3746 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3748 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3749 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3752 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3753 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3754 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3755 ;; used once. We can then use the sequence:
3757 ;; lui op0,%highest(op1)
3759 ;; daddiu op0,op0,%higher(op1)
3760 ;; daddiu op2,op2,%lo(op1)
3762 ;; daddu op0,op0,op2
3764 ;; which takes 4 cycles on most superscalar targets.
3765 (define_insn_and_split "*lea64"
3766 [(set (match_operand:DI 0 "register_operand" "=d")
3767 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3768 (clobber (match_scratch:DI 2 "=&d"))]
3769 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3771 "&& reload_completed"
3772 [(set (match_dup 0) (high:DI (match_dup 3)))
3773 (set (match_dup 2) (high:DI (match_dup 4)))
3774 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3775 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3776 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3777 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3779 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3780 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3782 [(set_attr "length" "24")])
3784 ;; Split HIGHs into:
3789 ;; on MIPS16 targets.
3791 [(set (match_operand:SI 0 "d_operand")
3792 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3793 "TARGET_MIPS16 && reload_completed"
3794 [(set (match_dup 0) (match_dup 2))
3795 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3797 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3800 ;; Insns to fetch a symbol from a big GOT.
3802 (define_insn_and_split "*xgot_hi<mode>"
3803 [(set (match_operand:P 0 "register_operand" "=d")
3804 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3805 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3807 "&& reload_completed"
3808 [(set (match_dup 0) (high:P (match_dup 2)))
3809 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3811 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3812 operands[3] = pic_offset_table_rtx;
3814 [(set_attr "got" "xgot_high")
3815 (set_attr "mode" "<MODE>")])
3817 (define_insn_and_split "*xgot_lo<mode>"
3818 [(set (match_operand:P 0 "register_operand" "=d")
3819 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3820 (match_operand:P 2 "got_disp_operand" "")))]
3821 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3823 "&& reload_completed"
3825 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3826 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3827 [(set_attr "got" "load")
3828 (set_attr "mode" "<MODE>")])
3830 ;; Insns to fetch a symbol from a normal GOT.
3832 (define_insn_and_split "*got_disp<mode>"
3833 [(set (match_operand:P 0 "register_operand" "=d")
3834 (match_operand:P 1 "got_disp_operand" ""))]
3835 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3837 "&& reload_completed"
3838 [(set (match_dup 0) (match_dup 2))]
3839 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3840 [(set_attr "got" "load")
3841 (set_attr "mode" "<MODE>")])
3843 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3845 (define_insn_and_split "*got_page<mode>"
3846 [(set (match_operand:P 0 "register_operand" "=d")
3847 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3848 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3850 "&& reload_completed"
3851 [(set (match_dup 0) (match_dup 2))]
3852 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3853 [(set_attr "got" "load")
3854 (set_attr "mode" "<MODE>")])
3856 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3857 (define_expand "unspec_got<mode>"
3858 [(unspec:P [(match_operand:P 0)
3859 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3861 ;; Lower-level instructions for loading an address from the GOT.
3862 ;; We could use MEMs, but an unspec gives more optimization
3865 (define_insn "load_got<mode>"
3866 [(set (match_operand:P 0 "register_operand" "=d")
3867 (unspec:P [(match_operand:P 1 "register_operand" "d")
3868 (match_operand:P 2 "immediate_operand" "")]
3871 "<load>\t%0,%R2(%1)"
3872 [(set_attr "got" "load")
3873 (set_attr "mode" "<MODE>")])
3875 ;; Instructions for adding the low 16 bits of an address to a register.
3876 ;; Operand 2 is the address: mips_print_operand works out which relocation
3877 ;; should be applied.
3879 (define_insn "*low<mode>"
3880 [(set (match_operand:P 0 "register_operand" "=d")
3881 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3882 (match_operand:P 2 "immediate_operand" "")))]
3884 "<d>addiu\t%0,%1,%R2"
3885 [(set_attr "type" "arith")
3886 (set_attr "mode" "<MODE>")])
3888 (define_insn "*low<mode>_mips16"
3889 [(set (match_operand:P 0 "register_operand" "=d")
3890 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3891 (match_operand:P 2 "immediate_operand" "")))]
3894 [(set_attr "type" "arith")
3895 (set_attr "mode" "<MODE>")
3896 (set_attr "extended_mips16" "yes")])
3898 ;; Expose MIPS16 uses of the global pointer after reload if the function
3899 ;; is responsible for setting up the register itself.
3901 [(set (match_operand:GPR 0 "d_operand")
3902 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3903 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3904 [(set (match_dup 0) (match_dup 1))]
3905 { operands[1] = pic_offset_table_rtx; })
3907 ;; Allow combine to split complex const_int load sequences, using operand 2
3908 ;; to store the intermediate results. See move_operand for details.
3910 [(set (match_operand:GPR 0 "register_operand")
3911 (match_operand:GPR 1 "splittable_const_int_operand"))
3912 (clobber (match_operand:GPR 2 "register_operand"))]
3916 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3920 ;; Likewise, for symbolic operands.
3922 [(set (match_operand:P 0 "register_operand")
3923 (match_operand:P 1))
3924 (clobber (match_operand:P 2 "register_operand"))]
3925 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3926 [(set (match_dup 0) (match_dup 3))]
3928 mips_split_symbol (operands[2], operands[1],
3929 MAX_MACHINE_MODE, &operands[3]);
3932 ;; 64-bit integer moves
3934 ;; Unlike most other insns, the move insns can't be split with
3935 ;; different predicates, because register spilling and other parts of
3936 ;; the compiler, have memoized the insn number already.
3938 (define_expand "movdi"
3939 [(set (match_operand:DI 0 "")
3940 (match_operand:DI 1 ""))]
3943 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3947 ;; For mips16, we need a special case to handle storing $31 into
3948 ;; memory, since we don't have a constraint to match $31. This
3949 ;; instruction can be generated by save_restore_insns.
3951 (define_insn "*mov<mode>_ra"
3952 [(set (match_operand:GPR 0 "stack_operand" "=m")
3956 [(set_attr "move_type" "store")
3957 (set_attr "mode" "<MODE>")])
3959 (define_insn "*movdi_32bit"
3960 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3961 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3962 "!TARGET_64BIT && !TARGET_MIPS16
3963 && (register_operand (operands[0], DImode)
3964 || reg_or_0_operand (operands[1], DImode))"
3965 { return mips_output_move (operands[0], operands[1]); }
3966 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3967 (set_attr "mode" "DI")])
3969 (define_insn "*movdi_32bit_mips16"
3970 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3971 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3972 "!TARGET_64BIT && TARGET_MIPS16
3973 && (register_operand (operands[0], DImode)
3974 || register_operand (operands[1], DImode))"
3975 { return mips_output_move (operands[0], operands[1]); }
3976 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3977 (set_attr "mode" "DI")])
3979 (define_insn "*movdi_64bit"
3980 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3981 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3982 "TARGET_64BIT && !TARGET_MIPS16
3983 && (register_operand (operands[0], DImode)
3984 || reg_or_0_operand (operands[1], DImode))"
3985 { return mips_output_move (operands[0], operands[1]); }
3986 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3987 (set_attr "mode" "DI")])
3989 (define_insn "*movdi_64bit_mips16"
3990 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3991 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3992 "TARGET_64BIT && TARGET_MIPS16
3993 && (register_operand (operands[0], DImode)
3994 || register_operand (operands[1], DImode))"
3995 { return mips_output_move (operands[0], operands[1]); }
3996 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3997 (set_attr "mode" "DI")])
3999 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4000 ;; when the original load is a 4 byte instruction but the add and the
4001 ;; load are 2 2 byte instructions.
4004 [(set (match_operand:DI 0 "d_operand")
4005 (mem:DI (plus:DI (match_dup 0)
4006 (match_operand:DI 1 "const_int_operand"))))]
4007 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4008 && !TARGET_DEBUG_D_MODE
4009 && ((INTVAL (operands[1]) < 0
4010 && INTVAL (operands[1]) >= -0x10)
4011 || (INTVAL (operands[1]) >= 32 * 8
4012 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4013 || (INTVAL (operands[1]) >= 0
4014 && INTVAL (operands[1]) < 32 * 8
4015 && (INTVAL (operands[1]) & 7) != 0))"
4016 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4017 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4019 HOST_WIDE_INT val = INTVAL (operands[1]);
4022 operands[2] = const0_rtx;
4023 else if (val >= 32 * 8)
4027 operands[1] = GEN_INT (0x8 + off);
4028 operands[2] = GEN_INT (val - off - 0x8);
4034 operands[1] = GEN_INT (off);
4035 operands[2] = GEN_INT (val - off);
4039 ;; 32-bit Integer moves
4041 ;; Unlike most other insns, the move insns can't be split with
4042 ;; different predicates, because register spilling and other parts of
4043 ;; the compiler, have memoized the insn number already.
4045 (define_expand "mov<mode>"
4046 [(set (match_operand:IMOVE32 0 "")
4047 (match_operand:IMOVE32 1 ""))]
4050 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4054 ;; The difference between these two is whether or not ints are allowed
4055 ;; in FP registers (off by default, use -mdebugh to enable).
4057 (define_insn "*mov<mode>_internal"
4058 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4059 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4061 && (register_operand (operands[0], <MODE>mode)
4062 || reg_or_0_operand (operands[1], <MODE>mode))"
4063 { return mips_output_move (operands[0], operands[1]); }
4064 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
4065 (set_attr "mode" "SI")])
4067 (define_insn "*mov<mode>_mips16"
4068 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4069 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4071 && (register_operand (operands[0], <MODE>mode)
4072 || register_operand (operands[1], <MODE>mode))"
4073 { return mips_output_move (operands[0], operands[1]); }
4074 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
4075 (set_attr "mode" "SI")])
4077 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4078 ;; when the original load is a 4 byte instruction but the add and the
4079 ;; load are 2 2 byte instructions.
4082 [(set (match_operand:SI 0 "d_operand")
4083 (mem:SI (plus:SI (match_dup 0)
4084 (match_operand:SI 1 "const_int_operand"))))]
4085 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4086 && ((INTVAL (operands[1]) < 0
4087 && INTVAL (operands[1]) >= -0x80)
4088 || (INTVAL (operands[1]) >= 32 * 4
4089 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4090 || (INTVAL (operands[1]) >= 0
4091 && INTVAL (operands[1]) < 32 * 4
4092 && (INTVAL (operands[1]) & 3) != 0))"
4093 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4094 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4096 HOST_WIDE_INT val = INTVAL (operands[1]);
4099 operands[2] = const0_rtx;
4100 else if (val >= 32 * 4)
4104 operands[1] = GEN_INT (0x7c + off);
4105 operands[2] = GEN_INT (val - off - 0x7c);
4111 operands[1] = GEN_INT (off);
4112 operands[2] = GEN_INT (val - off);
4116 ;; On the mips16, we can split a load of certain constants into a load
4117 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4121 [(set (match_operand:SI 0 "d_operand")
4122 (match_operand:SI 1 "const_int_operand"))]
4123 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4124 && INTVAL (operands[1]) >= 0x100
4125 && INTVAL (operands[1]) <= 0xff + 0x7f"
4126 [(set (match_dup 0) (match_dup 1))
4127 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4129 int val = INTVAL (operands[1]);
4131 operands[1] = GEN_INT (0xff);
4132 operands[2] = GEN_INT (val - 0xff);
4135 ;; This insn handles moving CCmode values. It's really just a
4136 ;; slightly simplified copy of movsi_internal2, with additional cases
4137 ;; to move a condition register to a general register and to move
4138 ;; between the general registers and the floating point registers.
4140 (define_insn "movcc"
4141 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4142 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4143 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4144 { return mips_output_move (operands[0], operands[1]); }
4145 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4146 (set_attr "mode" "SI")])
4148 ;; Reload condition code registers. reload_incc and reload_outcc
4149 ;; both handle moves from arbitrary operands into condition code
4150 ;; registers. reload_incc handles the more common case in which
4151 ;; a source operand is constrained to be in a condition-code
4152 ;; register, but has not been allocated to one.
4154 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4155 ;; constraints do not include 'z'. reload_outcc handles the case
4156 ;; when such an operand is allocated to a condition-code register.
4158 ;; Note that reloads from a condition code register to some
4159 ;; other location can be done using ordinary moves. Moving
4160 ;; into a GPR takes a single movcc, moving elsewhere takes
4161 ;; two. We can leave these cases to the generic reload code.
4162 (define_expand "reload_incc"
4163 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4164 (match_operand:CC 1 "general_operand" ""))
4165 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4166 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4168 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4172 (define_expand "reload_outcc"
4173 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4174 (match_operand:CC 1 "register_operand" ""))
4175 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4176 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4178 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4182 ;; MIPS4 supports loading and storing a floating point register from
4183 ;; the sum of two general registers. We use two versions for each of
4184 ;; these four instructions: one where the two general registers are
4185 ;; SImode, and one where they are DImode. This is because general
4186 ;; registers will be in SImode when they hold 32-bit values, but,
4187 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4188 ;; instructions will still work correctly.
4190 ;; ??? Perhaps it would be better to support these instructions by
4191 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4192 ;; these instructions can only be used to load and store floating
4193 ;; point registers, that would probably cause trouble in reload.
4195 (define_insn "*<ANYF:loadx>_<P:mode>"
4196 [(set (match_operand:ANYF 0 "register_operand" "=f")
4197 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4198 (match_operand:P 2 "register_operand" "d"))))]
4200 "<ANYF:loadx>\t%0,%1(%2)"
4201 [(set_attr "type" "fpidxload")
4202 (set_attr "mode" "<ANYF:UNITMODE>")])
4204 (define_insn "*<ANYF:storex>_<P:mode>"
4205 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4206 (match_operand:P 2 "register_operand" "d")))
4207 (match_operand:ANYF 0 "register_operand" "f"))]
4209 "<ANYF:storex>\t%0,%1(%2)"
4210 [(set_attr "type" "fpidxstore")
4211 (set_attr "mode" "<ANYF:UNITMODE>")])
4213 ;; Scaled indexed address load.
4214 ;; Per md.texi, we only need to look for a pattern with multiply in the
4215 ;; address expression, not shift.
4217 (define_insn "*lwxs"
4218 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4220 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4222 (match_operand:P 2 "register_operand" "d"))))]
4225 [(set_attr "type" "load")
4226 (set_attr "mode" "SI")])
4228 ;; 16-bit Integer moves
4230 ;; Unlike most other insns, the move insns can't be split with
4231 ;; different predicates, because register spilling and other parts of
4232 ;; the compiler, have memoized the insn number already.
4233 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4235 (define_expand "movhi"
4236 [(set (match_operand:HI 0 "")
4237 (match_operand:HI 1 ""))]
4240 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4244 (define_insn "*movhi_internal"
4245 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4246 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4248 && (register_operand (operands[0], HImode)
4249 || reg_or_0_operand (operands[1], HImode))"
4250 { return mips_output_move (operands[0], operands[1]); }
4251 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4252 (set_attr "mode" "HI")])
4254 (define_insn "*movhi_mips16"
4255 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4256 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4258 && (register_operand (operands[0], HImode)
4259 || register_operand (operands[1], HImode))"
4260 { return mips_output_move (operands[0], operands[1]); }
4261 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4262 (set_attr "mode" "HI")])
4264 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4265 ;; when the original load is a 4 byte instruction but the add and the
4266 ;; load are 2 2 byte instructions.
4269 [(set (match_operand:HI 0 "d_operand")
4270 (mem:HI (plus:SI (match_dup 0)
4271 (match_operand:SI 1 "const_int_operand"))))]
4272 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4273 && ((INTVAL (operands[1]) < 0
4274 && INTVAL (operands[1]) >= -0x80)
4275 || (INTVAL (operands[1]) >= 32 * 2
4276 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4277 || (INTVAL (operands[1]) >= 0
4278 && INTVAL (operands[1]) < 32 * 2
4279 && (INTVAL (operands[1]) & 1) != 0))"
4280 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4281 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4283 HOST_WIDE_INT val = INTVAL (operands[1]);
4286 operands[2] = const0_rtx;
4287 else if (val >= 32 * 2)
4291 operands[1] = GEN_INT (0x7e + off);
4292 operands[2] = GEN_INT (val - off - 0x7e);
4298 operands[1] = GEN_INT (off);
4299 operands[2] = GEN_INT (val - off);
4303 ;; 8-bit Integer moves
4305 ;; Unlike most other insns, the move insns can't be split with
4306 ;; different predicates, because register spilling and other parts of
4307 ;; the compiler, have memoized the insn number already.
4308 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4310 (define_expand "movqi"
4311 [(set (match_operand:QI 0 "")
4312 (match_operand:QI 1 ""))]
4315 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4319 (define_insn "*movqi_internal"
4320 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4321 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4323 && (register_operand (operands[0], QImode)
4324 || reg_or_0_operand (operands[1], QImode))"
4325 { return mips_output_move (operands[0], operands[1]); }
4326 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4327 (set_attr "mode" "QI")])
4329 (define_insn "*movqi_mips16"
4330 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4331 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4333 && (register_operand (operands[0], QImode)
4334 || register_operand (operands[1], QImode))"
4335 { return mips_output_move (operands[0], operands[1]); }
4336 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4337 (set_attr "mode" "QI")])
4339 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4340 ;; when the original load is a 4 byte instruction but the add and the
4341 ;; load are 2 2 byte instructions.
4344 [(set (match_operand:QI 0 "d_operand")
4345 (mem:QI (plus:SI (match_dup 0)
4346 (match_operand:SI 1 "const_int_operand"))))]
4347 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4348 && ((INTVAL (operands[1]) < 0
4349 && INTVAL (operands[1]) >= -0x80)
4350 || (INTVAL (operands[1]) >= 32
4351 && INTVAL (operands[1]) <= 31 + 0x7f))"
4352 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4353 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4355 HOST_WIDE_INT val = INTVAL (operands[1]);
4358 operands[2] = const0_rtx;
4361 operands[1] = GEN_INT (0x7f);
4362 operands[2] = GEN_INT (val - 0x7f);
4366 ;; 32-bit floating point moves
4368 (define_expand "movsf"
4369 [(set (match_operand:SF 0 "")
4370 (match_operand:SF 1 ""))]
4373 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4377 (define_insn "*movsf_hardfloat"
4378 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4379 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4381 && (register_operand (operands[0], SFmode)
4382 || reg_or_0_operand (operands[1], SFmode))"
4383 { return mips_output_move (operands[0], operands[1]); }
4384 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4385 (set_attr "mode" "SF")])
4387 (define_insn "*movsf_softfloat"
4388 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4389 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4390 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4391 && (register_operand (operands[0], SFmode)
4392 || reg_or_0_operand (operands[1], SFmode))"
4393 { return mips_output_move (operands[0], operands[1]); }
4394 [(set_attr "move_type" "move,load,store")
4395 (set_attr "mode" "SF")])
4397 (define_insn "*movsf_mips16"
4398 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4399 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4401 && (register_operand (operands[0], SFmode)
4402 || register_operand (operands[1], SFmode))"
4403 { return mips_output_move (operands[0], operands[1]); }
4404 [(set_attr "move_type" "move,move,move,load,store")
4405 (set_attr "mode" "SF")])
4407 ;; 64-bit floating point moves
4409 (define_expand "movdf"
4410 [(set (match_operand:DF 0 "")
4411 (match_operand:DF 1 ""))]
4414 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4418 (define_insn "*movdf_hardfloat"
4419 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4420 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4421 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4422 && (register_operand (operands[0], DFmode)
4423 || reg_or_0_operand (operands[1], DFmode))"
4424 { return mips_output_move (operands[0], operands[1]); }
4425 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4426 (set_attr "mode" "DF")])
4428 (define_insn "*movdf_softfloat"
4429 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4430 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4431 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4432 && (register_operand (operands[0], DFmode)
4433 || reg_or_0_operand (operands[1], DFmode))"
4434 { return mips_output_move (operands[0], operands[1]); }
4435 [(set_attr "move_type" "move,load,store")
4436 (set_attr "mode" "DF")])
4438 (define_insn "*movdf_mips16"
4439 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4440 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4442 && (register_operand (operands[0], DFmode)
4443 || register_operand (operands[1], DFmode))"
4444 { return mips_output_move (operands[0], operands[1]); }
4445 [(set_attr "move_type" "move,move,move,load,store")
4446 (set_attr "mode" "DF")])
4448 ;; 128-bit integer moves
4450 (define_expand "movti"
4451 [(set (match_operand:TI 0)
4452 (match_operand:TI 1))]
4455 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4459 (define_insn "*movti"
4460 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4461 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4464 && (register_operand (operands[0], TImode)
4465 || reg_or_0_operand (operands[1], TImode))"
4467 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4468 (set_attr "mode" "TI")])
4470 (define_insn "*movti_mips16"
4471 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4472 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4475 && (register_operand (operands[0], TImode)
4476 || register_operand (operands[1], TImode))"
4478 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4479 (set_attr "mode" "TI")])
4481 ;; 128-bit floating point moves
4483 (define_expand "movtf"
4484 [(set (match_operand:TF 0)
4485 (match_operand:TF 1))]
4488 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4492 ;; This pattern handles both hard- and soft-float cases.
4493 (define_insn "*movtf"
4494 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4495 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4498 && (register_operand (operands[0], TFmode)
4499 || reg_or_0_operand (operands[1], TFmode))"
4501 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4502 (set_attr "mode" "TF")])
4504 (define_insn "*movtf_mips16"
4505 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4506 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4509 && (register_operand (operands[0], TFmode)
4510 || register_operand (operands[1], TFmode))"
4512 [(set_attr "move_type" "move,move,move,load,store")
4513 (set_attr "mode" "TF")])
4516 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4517 (match_operand:MOVE64 1 "move_operand"))]
4518 "reload_completed && !TARGET_64BIT
4519 && mips_split_64bit_move_p (operands[0], operands[1])"
4522 mips_split_doubleword_move (operands[0], operands[1]);
4527 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4528 (match_operand:MOVE128 1 "move_operand"))]
4529 "TARGET_64BIT && reload_completed"
4532 mips_split_doubleword_move (operands[0], operands[1]);
4536 ;; When generating mips16 code, split moves of negative constants into
4537 ;; a positive "li" followed by a negation.
4539 [(set (match_operand 0 "d_operand")
4540 (match_operand 1 "const_int_operand"))]
4541 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4545 (neg:SI (match_dup 2)))]
4547 operands[2] = gen_lowpart (SImode, operands[0]);
4548 operands[3] = GEN_INT (-INTVAL (operands[1]));
4551 ;; 64-bit paired-single floating point moves
4553 (define_expand "movv2sf"
4554 [(set (match_operand:V2SF 0)
4555 (match_operand:V2SF 1))]
4556 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4558 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4562 (define_insn "*movv2sf"
4563 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4564 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4566 && TARGET_PAIRED_SINGLE_FLOAT
4567 && (register_operand (operands[0], V2SFmode)
4568 || reg_or_0_operand (operands[1], V2SFmode))"
4569 { return mips_output_move (operands[0], operands[1]); }
4570 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4571 (set_attr "mode" "DF")])
4573 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4574 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4576 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4577 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4578 ;; and the errata related to -mfix-vr4130.
4579 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4580 [(set (match_operand:GPR 0 "register_operand" "=d")
4581 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4584 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4585 [(set_attr "move_type" "mfhilo")
4586 (set_attr "mode" "<GPR:MODE>")])
4588 ;; Set the high part of a HI/LO value, given that the low part has
4589 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4590 ;; why we can't just use (reg:GPR HI_REGNUM).
4591 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4592 [(set (match_operand:HILO 0 "register_operand" "=x")
4593 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4594 (match_operand:GPR 2 "register_operand" "l")]
4598 [(set_attr "move_type" "mthilo")
4599 (set_attr "mode" "SI")])
4601 ;; Emit a doubleword move in which exactly one of the operands is
4602 ;; a floating-point register. We can't just emit two normal moves
4603 ;; because of the constraints imposed by the FPU register model;
4604 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4605 ;; the FPR whole and use special patterns to refer to each word of
4606 ;; the other operand.
4608 (define_expand "move_doubleword_fpr<mode>"
4609 [(set (match_operand:SPLITF 0)
4610 (match_operand:SPLITF 1))]
4613 if (FP_REG_RTX_P (operands[0]))
4615 rtx low = mips_subword (operands[1], 0);
4616 rtx high = mips_subword (operands[1], 1);
4617 emit_insn (gen_load_low<mode> (operands[0], low));
4618 if (TARGET_FLOAT64 && !TARGET_64BIT)
4619 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4621 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4625 rtx low = mips_subword (operands[0], 0);
4626 rtx high = mips_subword (operands[0], 1);
4627 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4628 if (TARGET_FLOAT64 && !TARGET_64BIT)
4629 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4631 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4636 ;; Load the low word of operand 0 with operand 1.
4637 (define_insn "load_low<mode>"
4638 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4639 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4643 operands[0] = mips_subword (operands[0], 0);
4644 return mips_output_move (operands[0], operands[1]);
4646 [(set_attr "move_type" "mtc,fpload")
4647 (set_attr "mode" "<HALFMODE>")])
4649 ;; Load the high word of operand 0 from operand 1, preserving the value
4651 (define_insn "load_high<mode>"
4652 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4653 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4654 (match_operand:SPLITF 2 "register_operand" "0,0")]
4658 operands[0] = mips_subword (operands[0], 1);
4659 return mips_output_move (operands[0], operands[1]);
4661 [(set_attr "move_type" "mtc,fpload")
4662 (set_attr "mode" "<HALFMODE>")])
4664 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4665 ;; high word and 0 to store the low word.
4666 (define_insn "store_word<mode>"
4667 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4668 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4669 (match_operand 2 "const_int_operand")]
4670 UNSPEC_STORE_WORD))]
4673 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4674 return mips_output_move (operands[0], operands[1]);
4676 [(set_attr "move_type" "mfc,fpstore")
4677 (set_attr "mode" "<HALFMODE>")])
4679 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4680 ;; value in the low word.
4681 (define_insn "mthc1<mode>"
4682 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4683 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4684 (match_operand:SPLITF 2 "register_operand" "0")]
4686 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4688 [(set_attr "move_type" "mtc")
4689 (set_attr "mode" "<HALFMODE>")])
4691 ;; Move high word of operand 1 to operand 0 using mfhc1.
4692 (define_insn "mfhc1<mode>"
4693 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4694 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4696 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4698 [(set_attr "move_type" "mfc")
4699 (set_attr "mode" "<HALFMODE>")])
4701 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4702 (define_expand "load_const_gp_<mode>"
4703 [(set (match_operand:P 0 "register_operand" "=d")
4704 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4706 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4707 ;; of _gp from the start of this function. Operand 1 is the incoming
4708 ;; function address.
4709 (define_insn_and_split "loadgp_newabi_<mode>"
4710 [(set (match_operand:P 0 "register_operand" "=d")
4711 (unspec_volatile:P [(match_operand:P 1)
4712 (match_operand:P 2 "register_operand" "d")]
4714 "mips_current_loadgp_style () == LOADGP_NEWABI"
4717 [(set (match_dup 0) (match_dup 3))
4718 (set (match_dup 0) (match_dup 4))
4719 (set (match_dup 0) (match_dup 5))]
4721 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4722 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4723 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4725 [(set_attr "length" "12")])
4727 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4728 (define_insn_and_split "loadgp_absolute_<mode>"
4729 [(set (match_operand:P 0 "register_operand" "=d")
4730 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4731 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4736 mips_emit_move (operands[0], operands[1]);
4739 [(set_attr "length" "8")])
4741 ;; This blockage instruction prevents the gp load from being
4742 ;; scheduled after an implicit use of gp. It also prevents
4743 ;; the load from being deleted as dead.
4744 (define_insn "loadgp_blockage"
4745 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4748 [(set_attr "type" "ghost")
4749 (set_attr "mode" "none")])
4751 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4752 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4753 (define_insn_and_split "loadgp_rtp_<mode>"
4754 [(set (match_operand:P 0 "register_operand" "=d")
4755 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4756 (match_operand:P 2 "symbol_ref_operand")]
4758 "mips_current_loadgp_style () == LOADGP_RTP"
4761 [(set (match_dup 0) (high:P (match_dup 3)))
4762 (set (match_dup 0) (unspec:P [(match_dup 0)
4763 (match_dup 3)] UNSPEC_LOAD_GOT))
4764 (set (match_dup 0) (unspec:P [(match_dup 0)
4765 (match_dup 4)] UNSPEC_LOAD_GOT))]
4767 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4768 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4770 [(set_attr "length" "12")])
4772 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4773 ;; global pointer and operand 1 is the MIPS16 register that holds
4774 ;; the required value.
4775 (define_insn_and_split "copygp_mips16"
4776 [(set (match_operand:SI 0 "register_operand" "=y")
4777 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4781 "&& reload_completed"
4782 [(set (match_dup 0) (match_dup 1))])
4784 ;; Emit a .cprestore directive, which normally expands to a single store
4785 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4786 ;; code so that jals inside inline asms will work correctly.
4787 (define_insn "cprestore"
4788 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4793 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
4794 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4796 return ".cprestore\t%0";
4798 [(set_attr "type" "store")
4799 (set_attr "length" "4,12")])
4801 ;; Expand in-line code to clear the instruction cache between operand[0] and
4803 (define_expand "clear_cache"
4804 [(match_operand 0 "pmode_register_operand")
4805 (match_operand 1 "pmode_register_operand")]
4811 mips_expand_synci_loop (operands[0], operands[1]);
4812 emit_insn (gen_sync ());
4813 emit_insn (Pmode == SImode
4814 ? gen_clear_hazard_si ()
4815 : gen_clear_hazard_di ());
4817 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4819 rtx len = gen_reg_rtx (Pmode);
4820 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4821 MIPS_ICACHE_SYNC (operands[0], len);
4827 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4831 (define_insn "synci"
4832 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4837 (define_insn "rdhwr_synci_step_<mode>"
4838 [(set (match_operand:P 0 "register_operand" "=d")
4839 (unspec_volatile [(const_int 1)]
4844 (define_insn "clear_hazard_<mode>"
4845 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4846 (clobber (reg:P 31))]
4849 return "%(%<bal\t1f\n"
4851 "1:\t<d>addiu\t$31,$31,12\n"
4855 [(set_attr "length" "20")])
4857 ;; Cache operations for R4000-style caches.
4858 (define_insn "mips_cache"
4859 [(set (mem:BLK (scratch))
4860 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4861 (match_operand:QI 1 "address_operand" "p")]
4862 UNSPEC_MIPS_CACHE))]
4866 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4867 ;; operation. We keep the pattern distinct so that we can identify
4868 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4869 ;; the operation is never inserted into a delay slot.
4870 (define_insn "r10k_cache_barrier"
4871 [(set (mem:BLK (scratch))
4872 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4875 [(set_attr "can_delay" "no")])
4877 ;; Block moves, see mips.c for more details.
4878 ;; Argument 0 is the destination
4879 ;; Argument 1 is the source
4880 ;; Argument 2 is the length
4881 ;; Argument 3 is the alignment
4883 (define_expand "movmemsi"
4884 [(parallel [(set (match_operand:BLK 0 "general_operand")
4885 (match_operand:BLK 1 "general_operand"))
4886 (use (match_operand:SI 2 ""))
4887 (use (match_operand:SI 3 "const_int_operand"))])]
4888 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4890 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4897 ;; ....................
4901 ;; ....................
4903 (define_expand "<optab><mode>3"
4904 [(set (match_operand:GPR 0 "register_operand")
4905 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4906 (match_operand:SI 2 "arith_operand")))]
4909 /* On the mips16, a shift of more than 8 is a four byte instruction,
4910 so, for a shift between 8 and 16, it is just as fast to do two
4911 shifts of 8 or less. If there is a lot of shifting going on, we
4912 may win in CSE. Otherwise combine will put the shifts back
4913 together again. This can be called by mips_function_arg, so we must
4914 be careful not to allocate a new register if we've reached the
4918 && CONST_INT_P (operands[2])
4919 && INTVAL (operands[2]) > 8
4920 && INTVAL (operands[2]) <= 16
4921 && !reload_in_progress
4922 && !reload_completed)
4924 rtx temp = gen_reg_rtx (<MODE>mode);
4926 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4927 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4928 GEN_INT (INTVAL (operands[2]) - 8)));
4933 (define_insn "*<optab><mode>3"
4934 [(set (match_operand:GPR 0 "register_operand" "=d")
4935 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4936 (match_operand:SI 2 "arith_operand" "dI")))]
4939 if (CONST_INT_P (operands[2]))
4940 operands[2] = GEN_INT (INTVAL (operands[2])
4941 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4943 return "<d><insn>\t%0,%1,%2";
4945 [(set_attr "type" "shift")
4946 (set_attr "mode" "<MODE>")])
4948 (define_insn "*<optab>si3_extend"
4949 [(set (match_operand:DI 0 "register_operand" "=d")
4951 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4952 (match_operand:SI 2 "arith_operand" "dI"))))]
4953 "TARGET_64BIT && !TARGET_MIPS16"
4955 if (CONST_INT_P (operands[2]))
4956 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4958 return "<insn>\t%0,%1,%2";
4960 [(set_attr "type" "shift")
4961 (set_attr "mode" "SI")])
4963 (define_insn "*<optab>si3_mips16"
4964 [(set (match_operand:SI 0 "register_operand" "=d,d")
4965 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4966 (match_operand:SI 2 "arith_operand" "d,I")))]
4969 if (which_alternative == 0)
4970 return "<insn>\t%0,%2";
4972 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4973 return "<insn>\t%0,%1,%2";
4975 [(set_attr "type" "shift")
4976 (set_attr "mode" "SI")
4977 (set_attr_alternative "length"
4979 (if_then_else (match_operand 2 "m16_uimm3_b")
4983 ;; We need separate DImode MIPS16 patterns because of the irregularity
4985 (define_insn "*ashldi3_mips16"
4986 [(set (match_operand:DI 0 "register_operand" "=d,d")
4987 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4988 (match_operand:SI 2 "arith_operand" "d,I")))]
4989 "TARGET_64BIT && TARGET_MIPS16"
4991 if (which_alternative == 0)
4992 return "dsll\t%0,%2";
4994 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4995 return "dsll\t%0,%1,%2";
4997 [(set_attr "type" "shift")
4998 (set_attr "mode" "DI")
4999 (set_attr_alternative "length"
5001 (if_then_else (match_operand 2 "m16_uimm3_b")
5005 (define_insn "*ashrdi3_mips16"
5006 [(set (match_operand:DI 0 "register_operand" "=d,d")
5007 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5008 (match_operand:SI 2 "arith_operand" "d,I")))]
5009 "TARGET_64BIT && TARGET_MIPS16"
5011 if (CONST_INT_P (operands[2]))
5012 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5014 return "dsra\t%0,%2";
5016 [(set_attr "type" "shift")
5017 (set_attr "mode" "DI")
5018 (set_attr_alternative "length"
5020 (if_then_else (match_operand 2 "m16_uimm3_b")
5024 (define_insn "*lshrdi3_mips16"
5025 [(set (match_operand:DI 0 "register_operand" "=d,d")
5026 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5027 (match_operand:SI 2 "arith_operand" "d,I")))]
5028 "TARGET_64BIT && TARGET_MIPS16"
5030 if (CONST_INT_P (operands[2]))
5031 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5033 return "dsrl\t%0,%2";
5035 [(set_attr "type" "shift")
5036 (set_attr "mode" "DI")
5037 (set_attr_alternative "length"
5039 (if_then_else (match_operand 2 "m16_uimm3_b")
5043 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5046 [(set (match_operand:GPR 0 "d_operand")
5047 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5048 (match_operand:GPR 2 "const_int_operand")))]
5049 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5050 && INTVAL (operands[2]) > 8
5051 && INTVAL (operands[2]) <= 16"
5052 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5053 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5054 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5056 ;; If we load a byte on the mips16 as a bitfield, the resulting
5057 ;; sequence of instructions is too complicated for combine, because it
5058 ;; involves four instructions: a load, a shift, a constant load into a
5059 ;; register, and an and (the key problem here is that the mips16 does
5060 ;; not have and immediate). We recognize a shift of a load in order
5061 ;; to make it simple enough for combine to understand.
5063 ;; The length here is the worst case: the length of the split version
5064 ;; will be more accurate.
5065 (define_insn_and_split ""
5066 [(set (match_operand:SI 0 "register_operand" "=d")
5067 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5068 (match_operand:SI 2 "immediate_operand" "I")))]
5072 [(set (match_dup 0) (match_dup 1))
5073 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5075 [(set_attr "type" "load")
5076 (set_attr "mode" "SI")
5077 (set_attr "length" "16")])
5079 (define_insn "rotr<mode>3"
5080 [(set (match_operand:GPR 0 "register_operand" "=d")
5081 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5082 (match_operand:SI 2 "arith_operand" "dI")))]
5085 if (CONST_INT_P (operands[2]))
5086 gcc_assert (INTVAL (operands[2]) >= 0
5087 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5089 return "<d>ror\t%0,%1,%2";
5091 [(set_attr "type" "shift")
5092 (set_attr "mode" "<MODE>")])
5095 ;; ....................
5097 ;; CONDITIONAL BRANCHES
5099 ;; ....................
5101 ;; Conditional branches on floating-point equality tests.
5103 (define_insn "*branch_fp"
5106 (match_operator 0 "equality_operator"
5107 [(match_operand:CC 2 "register_operand" "z")
5109 (label_ref (match_operand 1 "" ""))
5113 return mips_output_conditional_branch (insn, operands,
5114 MIPS_BRANCH ("b%F0", "%Z2%1"),
5115 MIPS_BRANCH ("b%W0", "%Z2%1"));
5117 [(set_attr "type" "branch")
5118 (set_attr "mode" "none")])
5120 (define_insn "*branch_fp_inverted"
5123 (match_operator 0 "equality_operator"
5124 [(match_operand:CC 2 "register_operand" "z")
5127 (label_ref (match_operand 1 "" ""))))]
5130 return mips_output_conditional_branch (insn, operands,
5131 MIPS_BRANCH ("b%W0", "%Z2%1"),
5132 MIPS_BRANCH ("b%F0", "%Z2%1"));
5134 [(set_attr "type" "branch")
5135 (set_attr "mode" "none")])
5137 ;; Conditional branches on ordered comparisons with zero.
5139 (define_insn "*branch_order<mode>"
5142 (match_operator 0 "order_operator"
5143 [(match_operand:GPR 2 "register_operand" "d")
5145 (label_ref (match_operand 1 "" ""))
5148 { return mips_output_order_conditional_branch (insn, operands, false); }
5149 [(set_attr "type" "branch")
5150 (set_attr "mode" "none")])
5152 (define_insn "*branch_order<mode>_inverted"
5155 (match_operator 0 "order_operator"
5156 [(match_operand:GPR 2 "register_operand" "d")
5159 (label_ref (match_operand 1 "" ""))))]
5161 { return mips_output_order_conditional_branch (insn, operands, true); }
5162 [(set_attr "type" "branch")
5163 (set_attr "mode" "none")])
5165 ;; Conditional branch on equality comparison.
5167 (define_insn "*branch_equality<mode>"
5170 (match_operator 0 "equality_operator"
5171 [(match_operand:GPR 2 "register_operand" "d")
5172 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5173 (label_ref (match_operand 1 "" ""))
5177 return mips_output_conditional_branch (insn, operands,
5178 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5179 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5181 [(set_attr "type" "branch")
5182 (set_attr "mode" "none")])
5184 (define_insn "*branch_equality<mode>_inverted"
5187 (match_operator 0 "equality_operator"
5188 [(match_operand:GPR 2 "register_operand" "d")
5189 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5191 (label_ref (match_operand 1 "" ""))))]
5194 return mips_output_conditional_branch (insn, operands,
5195 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5196 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5198 [(set_attr "type" "branch")
5199 (set_attr "mode" "none")])
5203 (define_insn "*branch_equality<mode>_mips16"
5206 (match_operator 0 "equality_operator"
5207 [(match_operand:GPR 1 "register_operand" "d,t")
5209 (match_operand 2 "pc_or_label_operand" "")
5210 (match_operand 3 "pc_or_label_operand" "")))]
5213 if (operands[2] != pc_rtx)
5215 if (which_alternative == 0)
5216 return "b%C0z\t%1,%2";
5218 return "bt%C0z\t%2";
5222 if (which_alternative == 0)
5223 return "b%N0z\t%1,%3";
5225 return "bt%N0z\t%3";
5228 [(set_attr "type" "branch")
5229 (set_attr "mode" "none")])
5231 (define_expand "cbranch<mode>4"
5233 (if_then_else (match_operator 0 "comparison_operator"
5234 [(match_operand:GPR 1 "register_operand")
5235 (match_operand:GPR 2 "nonmemory_operand")])
5236 (label_ref (match_operand 3 ""))
5240 mips_expand_conditional_branch (operands);
5244 (define_expand "cbranch<mode>4"
5246 (if_then_else (match_operator 0 "comparison_operator"
5247 [(match_operand:SCALARF 1 "register_operand")
5248 (match_operand:SCALARF 2 "register_operand")])
5249 (label_ref (match_operand 3 ""))
5253 mips_expand_conditional_branch (operands);
5257 ;; Used to implement built-in functions.
5258 (define_expand "condjump"
5260 (if_then_else (match_operand 0)
5261 (label_ref (match_operand 1))
5264 ;; Branch if bit is set/clear.
5266 (define_insn "*branch_bit<bbv><mode>"
5269 (equality_op (zero_extract:GPR
5270 (match_operand:GPR 0 "register_operand" "d")
5272 (match_operand 2 "const_int_operand" ""))
5274 (label_ref (match_operand 1 ""))
5276 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5279 mips_output_conditional_branch (insn, operands,
5280 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
5281 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
5283 [(set_attr "type" "branch")
5284 (set_attr "mode" "none")
5285 (set_attr "branch_likely" "no")])
5287 (define_insn "*branch_bit<bbv><mode>_inverted"
5290 (equality_op (zero_extract:GPR
5291 (match_operand:GPR 0 "register_operand" "d")
5293 (match_operand 2 "const_int_operand" ""))
5296 (label_ref (match_operand 1 ""))))]
5297 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5300 mips_output_conditional_branch (insn, operands,
5301 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
5302 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
5304 [(set_attr "type" "branch")
5305 (set_attr "mode" "none")
5306 (set_attr "branch_likely" "no")])
5309 ;; ....................
5311 ;; SETTING A REGISTER FROM A COMPARISON
5313 ;; ....................
5315 ;; Destination is always set in SI mode.
5317 (define_expand "cstore<mode>4"
5318 [(set (match_operand:SI 0 "register_operand")
5319 (match_operator:SI 1 "mips_cstore_operator"
5320 [(match_operand:GPR 2 "register_operand")
5321 (match_operand:GPR 3 "nonmemory_operand")]))]
5324 mips_expand_scc (operands);
5328 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5329 [(set (match_operand:GPR2 0 "register_operand" "=d")
5330 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5332 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5334 [(set_attr "type" "slt")
5335 (set_attr "mode" "<GPR:MODE>")])
5337 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5338 [(set (match_operand:GPR2 0 "register_operand" "=t")
5339 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5341 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5343 [(set_attr "type" "slt")
5344 (set_attr "mode" "<GPR:MODE>")])
5346 ;; Generate sltiu unless using seq results in better code.
5347 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5348 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5349 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5350 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5356 [(set_attr "type" "slt")
5357 (set_attr "mode" "<GPR:MODE>")])
5359 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5360 [(set (match_operand:GPR2 0 "register_operand" "=d")
5361 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5363 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5365 [(set_attr "type" "slt")
5366 (set_attr "mode" "<GPR:MODE>")])
5368 ;; Generate sltu unless using sne results in better code.
5369 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5370 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5371 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5372 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5378 [(set_attr "type" "slt")
5379 (set_attr "mode" "<GPR:MODE>")])
5381 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5382 [(set (match_operand:GPR2 0 "register_operand" "=d")
5383 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5384 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5387 [(set_attr "type" "slt")
5388 (set_attr "mode" "<GPR:MODE>")])
5390 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5391 [(set (match_operand:GPR2 0 "register_operand" "=t")
5392 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5393 (match_operand:GPR 2 "register_operand" "d")))]
5396 [(set_attr "type" "slt")
5397 (set_attr "mode" "<GPR:MODE>")])
5399 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5400 [(set (match_operand:GPR2 0 "register_operand" "=d")
5401 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5405 [(set_attr "type" "slt")
5406 (set_attr "mode" "<GPR:MODE>")])
5408 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5409 [(set (match_operand:GPR2 0 "register_operand" "=d")
5410 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5411 (match_operand:GPR 2 "arith_operand" "dI")))]
5414 [(set_attr "type" "slt")
5415 (set_attr "mode" "<GPR:MODE>")])
5417 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5418 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5419 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5420 (match_operand:GPR 2 "arith_operand" "d,I")))]
5423 [(set_attr "type" "slt")
5424 (set_attr "mode" "<GPR:MODE>")
5425 (set_attr_alternative "length"
5427 (if_then_else (match_operand 2 "m16_uimm8_1")
5431 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5432 [(set (match_operand:GPR2 0 "register_operand" "=d")
5433 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5434 (match_operand:GPR 2 "sle_operand" "")))]
5437 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5438 return "slt<u>\t%0,%1,%2";
5440 [(set_attr "type" "slt")
5441 (set_attr "mode" "<GPR:MODE>")])
5443 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5444 [(set (match_operand:GPR2 0 "register_operand" "=t")
5445 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5446 (match_operand:GPR 2 "sle_operand" "")))]
5449 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5450 return "slt<u>\t%1,%2";
5452 [(set_attr "type" "slt")
5453 (set_attr "mode" "<GPR:MODE>")
5454 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5459 ;; ....................
5461 ;; FLOATING POINT COMPARISONS
5463 ;; ....................
5465 (define_insn "s<code>_<mode>"
5466 [(set (match_operand:CC 0 "register_operand" "=z")
5467 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5468 (match_operand:SCALARF 2 "register_operand" "f")))]
5470 "c.<fcond>.<fmt>\t%Z0%1,%2"
5471 [(set_attr "type" "fcmp")
5472 (set_attr "mode" "FPSW")])
5474 (define_insn "s<code>_<mode>"
5475 [(set (match_operand:CC 0 "register_operand" "=z")
5476 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5477 (match_operand:SCALARF 2 "register_operand" "f")))]
5479 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5480 [(set_attr "type" "fcmp")
5481 (set_attr "mode" "FPSW")])
5484 ;; ....................
5486 ;; UNCONDITIONAL BRANCHES
5488 ;; ....................
5490 ;; Unconditional branches.
5494 (label_ref (match_operand 0 "" "")))]
5499 if (get_attr_length (insn) <= 8)
5500 return "%*b\t%l0%/";
5503 output_asm_insn (mips_output_load_label (), operands);
5504 return "%*jr\t%@%/%]";
5508 return "%*j\t%l0%/";
5510 [(set_attr "type" "jump")
5511 (set_attr "mode" "none")
5512 (set (attr "length")
5513 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5514 ;; in range, otherwise load the address of the branch target into
5515 ;; $at and then jump to it.
5517 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5518 (lt (abs (minus (match_dup 0)
5519 (plus (pc) (const_int 4))))
5520 (const_int 131072)))
5521 (const_int 4) (const_int 16)))])
5523 ;; We need a different insn for the mips16, because a mips16 branch
5524 ;; does not have a delay slot.
5528 (label_ref (match_operand 0 "" "")))]
5531 [(set_attr "type" "branch")
5532 (set_attr "mode" "none")])
5534 (define_expand "indirect_jump"
5535 [(set (pc) (match_operand 0 "register_operand"))]
5538 operands[0] = force_reg (Pmode, operands[0]);
5539 if (Pmode == SImode)
5540 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5542 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5546 (define_insn "indirect_jump<mode>"
5547 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5550 [(set_attr "type" "jump")
5551 (set_attr "mode" "none")])
5553 (define_expand "tablejump"
5555 (match_operand 0 "register_operand"))
5556 (use (label_ref (match_operand 1 "")))]
5559 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5560 operands[0] = expand_binop (Pmode, add_optab,
5561 convert_to_mode (Pmode, operands[0], false),
5562 gen_rtx_LABEL_REF (Pmode, operands[1]),
5564 else if (TARGET_GPWORD)
5565 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5566 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5567 else if (TARGET_RTP_PIC)
5569 /* When generating RTP PIC, we use case table entries that are relative
5570 to the start of the function. Add the function's address to the
5572 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5573 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5574 start, 0, 0, OPTAB_WIDEN);
5577 if (Pmode == SImode)
5578 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5580 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5584 (define_insn "tablejump<mode>"
5586 (match_operand:P 0 "register_operand" "d"))
5587 (use (label_ref (match_operand 1 "" "")))]
5590 [(set_attr "type" "jump")
5591 (set_attr "mode" "none")])
5593 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5594 ;; While it is possible to either pull it off the stack (in the
5595 ;; o32 case) or recalculate it given t9 and our target label,
5596 ;; it takes 3 or 4 insns to do so.
5598 (define_expand "builtin_setjmp_setup"
5599 [(use (match_operand 0 "register_operand"))]
5604 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5605 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5609 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5610 ;; that older code did recalculate the gp from $25. Continue to jump through
5611 ;; $25 for compatibility (we lose nothing by doing so).
5613 (define_expand "builtin_longjmp"
5614 [(use (match_operand 0 "register_operand"))]
5617 /* The elements of the buffer are, in order: */
5618 int W = GET_MODE_SIZE (Pmode);
5619 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5620 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5621 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5622 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5623 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5624 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5625 The target is bound to be using $28 as the global pointer
5626 but the current function might not be. */
5627 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5629 /* This bit is similar to expand_builtin_longjmp except that it
5630 restores $gp as well. */
5631 mips_emit_move (hard_frame_pointer_rtx, fp);
5632 mips_emit_move (pv, lab);
5633 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5634 mips_emit_move (gp, gpv);
5635 emit_use (hard_frame_pointer_rtx);
5636 emit_use (stack_pointer_rtx);
5638 emit_indirect_jump (pv);
5643 ;; ....................
5645 ;; Function prologue/epilogue
5647 ;; ....................
5650 (define_expand "prologue"
5654 mips_expand_prologue ();
5658 ;; Block any insns from being moved before this point, since the
5659 ;; profiling call to mcount can use various registers that aren't
5660 ;; saved or used to pass arguments.
5662 (define_insn "blockage"
5663 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5666 [(set_attr "type" "ghost")
5667 (set_attr "mode" "none")])
5669 (define_expand "epilogue"
5673 mips_expand_epilogue (false);
5677 (define_expand "sibcall_epilogue"
5681 mips_expand_epilogue (true);
5685 ;; Trivial return. Make it look like a normal return insn as that
5686 ;; allows jump optimizations to work better.
5688 (define_expand "return"
5690 "mips_can_use_return_insn ()"
5691 { mips_expand_before_return (); })
5693 (define_insn "*return"
5695 "mips_can_use_return_insn ()"
5697 [(set_attr "type" "jump")
5698 (set_attr "mode" "none")])
5702 (define_insn "return_internal"
5704 (use (match_operand 0 "pmode_register_operand" ""))]
5707 [(set_attr "type" "jump")
5708 (set_attr "mode" "none")])
5710 ;; Exception return.
5711 (define_insn "mips_eret"
5713 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5716 [(set_attr "type" "trap")
5717 (set_attr "mode" "none")])
5719 ;; Debug exception return.
5720 (define_insn "mips_deret"
5722 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5725 [(set_attr "type" "trap")
5726 (set_attr "mode" "none")])
5728 ;; Disable interrupts.
5729 (define_insn "mips_di"
5730 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5733 [(set_attr "type" "trap")
5734 (set_attr "mode" "none")])
5736 ;; Execution hazard barrier.
5737 (define_insn "mips_ehb"
5738 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5741 [(set_attr "type" "trap")
5742 (set_attr "mode" "none")])
5744 ;; Read GPR from previous shadow register set.
5745 (define_insn "mips_rdpgpr"
5746 [(set (match_operand:SI 0 "register_operand" "=d")
5747 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5751 [(set_attr "type" "move")
5752 (set_attr "mode" "SI")])
5754 ;; Move involving COP0 registers.
5755 (define_insn "cop0_move"
5756 [(set (match_operand:SI 0 "register_operand" "=B,d")
5757 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5760 { return mips_output_move (operands[0], operands[1]); }
5761 [(set_attr "type" "mtc,mfc")
5762 (set_attr "mode" "SI")])
5764 ;; This is used in compiling the unwind routines.
5765 (define_expand "eh_return"
5766 [(use (match_operand 0 "general_operand"))]
5769 if (GET_MODE (operands[0]) != word_mode)
5770 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5772 emit_insn (gen_eh_set_lr_di (operands[0]));
5774 emit_insn (gen_eh_set_lr_si (operands[0]));
5778 ;; Clobber the return address on the stack. We can't expand this
5779 ;; until we know where it will be put in the stack frame.
5781 (define_insn "eh_set_lr_si"
5782 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5783 (clobber (match_scratch:SI 1 "=&d"))]
5787 (define_insn "eh_set_lr_di"
5788 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5789 (clobber (match_scratch:DI 1 "=&d"))]
5794 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5795 (clobber (match_scratch 1))]
5799 mips_set_return_address (operands[0], operands[1]);
5803 (define_expand "exception_receiver"
5807 /* See the comment above load_call<mode> for details. */
5808 emit_insn (gen_set_got_version ());
5810 /* If we have a call-clobbered $gp, restore it from its save slot. */
5811 if (HAVE_restore_gp)
5812 emit_insn (gen_restore_gp ());
5816 (define_expand "nonlocal_goto_receiver"
5820 /* See the comment above load_call<mode> for details. */
5821 emit_insn (gen_set_got_version ());
5825 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5826 ;; volatile until all uses of $28 are exposed.
5827 (define_insn_and_split "restore_gp"
5829 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5830 (clobber (match_scratch:SI 0 "=&d"))]
5831 "TARGET_CALL_CLOBBERED_GP"
5833 "&& reload_completed"
5836 mips_restore_gp (operands[0]);
5839 [(set_attr "type" "load")
5840 (set_attr "length" "12")])
5843 ;; ....................
5847 ;; ....................
5849 ;; Instructions to load a call address from the GOT. The address might
5850 ;; point to a function or to a lazy binding stub. In the latter case,
5851 ;; the stub will use the dynamic linker to resolve the function, which
5852 ;; in turn will change the GOT entry to point to the function's real
5855 ;; This means that every call, even pure and constant ones, can
5856 ;; potentially modify the GOT entry. And once a stub has been called,
5857 ;; we must not call it again.
5859 ;; We represent this restriction using an imaginary, fixed, call-saved
5860 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5861 ;; live throughout the function and to change its value after every
5862 ;; potential call site. This stops any rtx value that uses the register
5863 ;; from being computed before an earlier call. To do this, we:
5865 ;; - Ensure that the register is live on entry to the function,
5866 ;; so that it is never thought to be used uninitalized.
5868 ;; - Ensure that the register is live on exit from the function,
5869 ;; so that it is live throughout.
5871 ;; - Make each call (lazily-bound or not) use the current value
5872 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5873 ;; not moved across call boundaries.
5875 ;; - Add "ghost" definitions of the register to the beginning of
5876 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5877 ;; edges may involve calls that normal paths don't. (E.g. the
5878 ;; unwinding code that handles a non-call exception may change
5879 ;; lazily-bound GOT entries.) We do this by making the
5880 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5881 ;; a set_got_version instruction.
5883 ;; - After each call (lazily-bound or not), use a "ghost"
5884 ;; update_got_version instruction to change the register's value.
5885 ;; This instruction mimics the _possible_ effect of the dynamic
5886 ;; resolver during the call and it remains live even if the call
5887 ;; itself becomes dead.
5889 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5890 ;; The register is therefore not a valid register_operand
5891 ;; and cannot be moved to or from other registers.
5893 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5894 (define_expand "unspec_call<mode>"
5895 [(unspec:P [(match_operand:P 0)
5897 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5899 (define_insn "load_call<mode>"
5900 [(set (match_operand:P 0 "register_operand" "=d")
5901 (unspec:P [(match_operand:P 1 "register_operand" "d")
5902 (match_operand:P 2 "immediate_operand" "")
5903 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5905 "<load>\t%0,%R2(%1)"
5906 [(set_attr "got" "load")
5907 (set_attr "mode" "<MODE>")])
5909 (define_insn "set_got_version"
5910 [(set (reg:SI GOT_VERSION_REGNUM)
5911 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5914 [(set_attr "type" "ghost")])
5916 (define_insn "update_got_version"
5917 [(set (reg:SI GOT_VERSION_REGNUM)
5918 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5921 [(set_attr "type" "ghost")])
5923 ;; Sibling calls. All these patterns use jump instructions.
5925 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5926 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5927 ;; is defined in terms of call_insn_operand, the same is true of the
5930 ;; When we use an indirect jump, we need a register that will be
5931 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5932 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5933 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5936 (define_expand "sibcall"
5937 [(parallel [(call (match_operand 0 "")
5938 (match_operand 1 ""))
5939 (use (match_operand 2 "")) ;; next_arg_reg
5940 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5943 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5944 operands[1], operands[2], false);
5948 (define_insn "sibcall_internal"
5949 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5950 (match_operand 1 "" ""))]
5951 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5952 { return MIPS_CALL ("j", operands, 0); }
5953 [(set_attr "type" "call")])
5955 (define_expand "sibcall_value"
5956 [(parallel [(set (match_operand 0 "")
5957 (call (match_operand 1 "")
5958 (match_operand 2 "")))
5959 (use (match_operand 3 ""))])] ;; next_arg_reg
5962 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5963 operands[2], operands[3], false);
5967 (define_insn "sibcall_value_internal"
5968 [(set (match_operand 0 "register_operand" "")
5969 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5970 (match_operand 2 "" "")))]
5971 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5972 { return MIPS_CALL ("j", operands, 1); }
5973 [(set_attr "type" "call")])
5975 (define_insn "sibcall_value_multiple_internal"
5976 [(set (match_operand 0 "register_operand" "")
5977 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5978 (match_operand 2 "" "")))
5979 (set (match_operand 3 "register_operand" "")
5980 (call (mem:SI (match_dup 1))
5982 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5983 { return MIPS_CALL ("j", operands, 1); }
5984 [(set_attr "type" "call")])
5986 (define_expand "call"
5987 [(parallel [(call (match_operand 0 "")
5988 (match_operand 1 ""))
5989 (use (match_operand 2 "")) ;; next_arg_reg
5990 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5993 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5994 operands[1], operands[2], false);
5998 ;; This instruction directly corresponds to an assembly-language "jal".
5999 ;; There are four cases:
6002 ;; Both symbolic and register destinations are OK. The pattern
6003 ;; always expands to a single mips instruction.
6005 ;; - -mabicalls/-mno-explicit-relocs:
6006 ;; Again, both symbolic and register destinations are OK.
6007 ;; The call is treated as a multi-instruction black box.
6009 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6010 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6013 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6014 ;; Only "jal $25" is allowed. The call is actually two instructions:
6015 ;; "jalr $25" followed by an insn to reload $gp.
6017 ;; In the last case, we can generate the individual instructions with
6018 ;; a define_split. There are several things to be wary of:
6020 ;; - We can't expose the load of $gp before reload. If we did,
6021 ;; it might get removed as dead, but reload can introduce new
6022 ;; uses of $gp by rematerializing constants.
6024 ;; - We shouldn't restore $gp after calls that never return.
6025 ;; It isn't valid to insert instructions between a noreturn
6026 ;; call and the following barrier.
6028 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6029 ;; instruction preserves $gp and so have no effect on its liveness.
6030 ;; But once we generate the separate insns, it becomes obvious that
6031 ;; $gp is not live on entry to the call.
6033 ;; ??? The operands[2] = insn check is a hack to make the original insn
6034 ;; available to the splitter.
6035 (define_insn_and_split "call_internal"
6036 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6037 (match_operand 1 "" ""))
6038 (clobber (reg:SI 31))]
6040 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
6041 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
6044 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
6047 [(set_attr "jal" "indirect,direct")])
6049 (define_insn "call_split"
6050 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
6051 (match_operand 1 "" ""))
6052 (clobber (reg:SI 31))
6053 (clobber (reg:SI 28))]
6054 "TARGET_SPLIT_CALLS"
6055 { return MIPS_CALL ("jal", operands, 0); }
6056 [(set_attr "type" "call")])
6058 ;; A pattern for calls that must be made directly. It is used for
6059 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6060 ;; stub; the linker relies on the call relocation type to detect when
6061 ;; such redirection is needed.
6062 (define_insn_and_split "call_internal_direct"
6063 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6066 (clobber (reg:SI 31))]
6068 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
6069 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
6072 mips_split_call (operands[2],
6073 gen_call_direct_split (operands[0], operands[1]));
6076 [(set_attr "type" "call")])
6078 (define_insn "call_direct_split"
6079 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6082 (clobber (reg:SI 31))
6083 (clobber (reg:SI 28))]
6084 "TARGET_SPLIT_CALLS"
6085 { return MIPS_CALL ("jal", operands, 0); }
6086 [(set_attr "type" "call")])
6088 (define_expand "call_value"
6089 [(parallel [(set (match_operand 0 "")
6090 (call (match_operand 1 "")
6091 (match_operand 2 "")))
6092 (use (match_operand 3 ""))])] ;; next_arg_reg
6095 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6096 operands[2], operands[3], false);
6100 ;; See comment for call_internal.
6101 (define_insn_and_split "call_value_internal"
6102 [(set (match_operand 0 "register_operand" "")
6103 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6104 (match_operand 2 "" "")))
6105 (clobber (reg:SI 31))]
6107 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6108 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6111 mips_split_call (operands[3],
6112 gen_call_value_split (operands[0], operands[1],
6116 [(set_attr "jal" "indirect,direct")])
6118 (define_insn "call_value_split"
6119 [(set (match_operand 0 "register_operand" "")
6120 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6121 (match_operand 2 "" "")))
6122 (clobber (reg:SI 31))
6123 (clobber (reg:SI 28))]
6124 "TARGET_SPLIT_CALLS"
6125 { return MIPS_CALL ("jal", operands, 1); }
6126 [(set_attr "type" "call")])
6128 ;; See call_internal_direct.
6129 (define_insn_and_split "call_value_internal_direct"
6130 [(set (match_operand 0 "register_operand")
6131 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6134 (clobber (reg:SI 31))]
6136 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6137 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6140 mips_split_call (operands[3],
6141 gen_call_value_direct_split (operands[0], operands[1],
6145 [(set_attr "type" "call")])
6147 (define_insn "call_value_direct_split"
6148 [(set (match_operand 0 "register_operand")
6149 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6152 (clobber (reg:SI 31))
6153 (clobber (reg:SI 28))]
6154 "TARGET_SPLIT_CALLS"
6155 { return MIPS_CALL ("jal", operands, 1); }
6156 [(set_attr "type" "call")])
6158 ;; See comment for call_internal.
6159 (define_insn_and_split "call_value_multiple_internal"
6160 [(set (match_operand 0 "register_operand" "")
6161 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6162 (match_operand 2 "" "")))
6163 (set (match_operand 3 "register_operand" "")
6164 (call (mem:SI (match_dup 1))
6166 (clobber (reg:SI 31))]
6168 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6169 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6172 mips_split_call (operands[4],
6173 gen_call_value_multiple_split (operands[0], operands[1],
6174 operands[2], operands[3]));
6177 [(set_attr "jal" "indirect,direct")])
6179 (define_insn "call_value_multiple_split"
6180 [(set (match_operand 0 "register_operand" "")
6181 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6182 (match_operand 2 "" "")))
6183 (set (match_operand 3 "register_operand" "")
6184 (call (mem:SI (match_dup 1))
6186 (clobber (reg:SI 31))
6187 (clobber (reg:SI 28))]
6188 "TARGET_SPLIT_CALLS"
6189 { return MIPS_CALL ("jal", operands, 1); }
6190 [(set_attr "type" "call")])
6192 ;; Call subroutine returning any type.
6194 (define_expand "untyped_call"
6195 [(parallel [(call (match_operand 0 "")
6197 (match_operand 1 "")
6198 (match_operand 2 "")])]
6203 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6205 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6207 rtx set = XVECEXP (operands[2], 0, i);
6208 mips_emit_move (SET_DEST (set), SET_SRC (set));
6211 emit_insn (gen_blockage ());
6216 ;; ....................
6220 ;; ....................
6224 (define_insn "prefetch"
6225 [(prefetch (match_operand:QI 0 "address_operand" "p")
6226 (match_operand 1 "const_int_operand" "n")
6227 (match_operand 2 "const_int_operand" "n"))]
6228 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6230 if (TARGET_LOONGSON_2EF)
6231 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6232 return "ld\t$0,%a0";
6233 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6234 return "pref\t%1,%a0";
6236 [(set_attr "type" "prefetch")])
6238 (define_insn "*prefetch_indexed_<mode>"
6239 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6240 (match_operand:P 1 "register_operand" "d"))
6241 (match_operand 2 "const_int_operand" "n")
6242 (match_operand 3 "const_int_operand" "n"))]
6243 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6245 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6246 return "prefx\t%2,%1(%0)";
6248 [(set_attr "type" "prefetchx")])
6254 [(set_attr "type" "nop")
6255 (set_attr "mode" "none")])
6257 ;; Like nop, but commented out when outside a .set noreorder block.
6258 (define_insn "hazard_nop"
6262 if (mips_noreorder.nesting_level > 0)
6267 [(set_attr "type" "nop")])
6269 ;; MIPS4 Conditional move instructions.
6271 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6272 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6274 (match_operator:MOVECC 4 "equality_operator"
6275 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6277 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6278 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6283 [(set_attr "type" "condmove")
6284 (set_attr "mode" "<GPR:MODE>")])
6286 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6287 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6288 (if_then_else:SCALARF
6289 (match_operator:MOVECC 4 "equality_operator"
6290 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6292 (match_operand:SCALARF 2 "register_operand" "f,0")
6293 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6294 "ISA_HAS_FP_CONDMOVE"
6296 mov%T4.<fmt>\t%0,%2,%1
6297 mov%t4.<fmt>\t%0,%3,%1"
6298 [(set_attr "type" "condmove")
6299 (set_attr "mode" "<SCALARF:MODE>")])
6301 ;; These are the main define_expand's used to make conditional moves.
6303 (define_expand "mov<mode>cc"
6304 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6305 (set (match_operand:GPR 0 "register_operand")
6306 (if_then_else:GPR (match_dup 5)
6307 (match_operand:GPR 2 "reg_or_0_operand")
6308 (match_operand:GPR 3 "reg_or_0_operand")))]
6311 mips_expand_conditional_move (operands);
6315 (define_expand "mov<mode>cc"
6316 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6317 (set (match_operand:SCALARF 0 "register_operand")
6318 (if_then_else:SCALARF (match_dup 5)
6319 (match_operand:SCALARF 2 "register_operand")
6320 (match_operand:SCALARF 3 "register_operand")))]
6321 "ISA_HAS_FP_CONDMOVE"
6323 mips_expand_conditional_move (operands);
6328 ;; ....................
6330 ;; mips16 inline constant tables
6332 ;; ....................
6335 (define_insn "consttable_int"
6336 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6337 (match_operand 1 "const_int_operand" "")]
6338 UNSPEC_CONSTTABLE_INT)]
6341 assemble_integer (operands[0], INTVAL (operands[1]),
6342 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6345 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6347 (define_insn "consttable_float"
6348 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6349 UNSPEC_CONSTTABLE_FLOAT)]
6354 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6355 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6356 assemble_real (d, GET_MODE (operands[0]),
6357 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6360 [(set (attr "length")
6361 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6363 (define_insn "align"
6364 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6367 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6370 [(match_operand 0 "small_data_pattern")]
6373 { operands[0] = mips_rewrite_small_data (operands[0]); })
6376 ;; ....................
6378 ;; MIPS16e Save/Restore
6380 ;; ....................
6383 (define_insn "*mips16e_save_restore"
6384 [(match_parallel 0 ""
6385 [(set (match_operand:SI 1 "register_operand")
6386 (plus:SI (match_dup 1)
6387 (match_operand:SI 2 "const_int_operand")))])]
6388 "operands[1] == stack_pointer_rtx
6389 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6390 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6391 [(set_attr "type" "arith")
6392 (set_attr "extended_mips16" "yes")])
6394 ;; Thread-Local Storage
6396 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6397 ;; MIPS architecture defines this register, and no current
6398 ;; implementation provides it; instead, any OS which supports TLS is
6399 ;; expected to trap and emulate this instruction. rdhwr is part of the
6400 ;; MIPS 32r2 specification, but we use it on any architecture because
6401 ;; we expect it to be emulated. Use .set to force the assembler to
6404 ;; We do not use a constraint to force the destination to be $3
6405 ;; because $3 can appear explicitly as a function return value.
6406 ;; If we leave the use of $3 implicit in the constraints until
6407 ;; reload, we may end up making a $3 return value live across
6408 ;; the instruction, leading to a spill failure when reloading it.
6409 (define_insn_and_split "tls_get_tp_<mode>"
6410 [(set (match_operand:P 0 "register_operand" "=d")
6411 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6412 (clobber (reg:P TLS_GET_TP_REGNUM))]
6413 "HAVE_AS_TLS && !TARGET_MIPS16"
6415 "&& reload_completed"
6416 [(set (reg:P TLS_GET_TP_REGNUM)
6417 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6418 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6420 [(set_attr "type" "unknown")
6421 ; Since rdhwr always generates a trap for now, putting it in a delay
6422 ; slot would make the kernel's emulation of it much slower.
6423 (set_attr "can_delay" "no")
6424 (set_attr "mode" "<MODE>")
6425 (set_attr "length" "8")])
6427 (define_insn "*tls_get_tp_<mode>_split"
6428 [(set (reg:P TLS_GET_TP_REGNUM)
6429 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6430 "HAVE_AS_TLS && !TARGET_MIPS16"
6431 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6432 [(set_attr "type" "unknown")
6433 ; See tls_get_tp_<mode>
6434 (set_attr "can_delay" "no")
6435 (set_attr "mode" "<MODE>")])
6437 ;; Synchronization instructions.
6441 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6443 (include "mips-ps-3d.md")
6445 ; The MIPS DSP Instructions.
6447 (include "mips-dsp.md")
6449 ; The MIPS DSP REV 2 Instructions.
6451 (include "mips-dspr2.md")
6453 ; MIPS fixed-point instructions.
6454 (include "mips-fixed.md")
6456 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6457 (include "loongson.md")