1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
113 ;; These are used with unspec.
114 (UNSPEC_COMPACT_ARGS 0)
127 (UNSPEC_INIT_TRAMP 13)
140 (UNSPEC_DIV_INV_M0 30)
141 (UNSPEC_DIV_INV_M1 31)
142 (UNSPEC_DIV_INV_M2 32)
143 (UNSPEC_DIV_INV_M3 33)
144 (UNSPEC_DIV_INV20 34)
145 (UNSPEC_DIV_INV_TABLE 37)
153 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
154 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
155 (UNSPEC_EXTRACT_S16 43)
156 (UNSPEC_EXTRACT_U16 44)
158 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
161 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
162 (UNSPEC_PCREL_SYMOFF 46)
165 (UNSPEC_BUILTIN_STRLEN 47)
167 ;; These are used with unspec_volatile.
173 (UNSPECV_WINDOW_END 10)
174 (UNSPECV_CONST_END 11)
175 (UNSPECV_EH_RETURN 12)
177 (UNSPECV_SP_SWITCH_B 14)
178 (UNSPECV_SP_SWITCH_E 15)
181 ;; -------------------------------------------------------------------------
183 ;; -------------------------------------------------------------------------
188 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
189 (const (symbol_ref "sh_cpu_attr")))
191 (define_attr "endian" "big,little"
192 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
193 (const_string "little") (const_string "big"))))
195 ;; Indicate if the default fpu mode is single precision.
196 (define_attr "fpu_single" "yes,no"
197 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
198 (const_string "yes") (const_string "no"))))
200 (define_attr "fmovd" "yes,no"
201 (const (if_then_else (symbol_ref "TARGET_FMOVD")
202 (const_string "yes") (const_string "no"))))
204 (define_attr "pipe_model" "sh1,sh4,sh5media"
206 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
207 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
208 (const_string "sh1"))))
210 ;; cbranch conditional branch instructions
211 ;; jump unconditional jumps
212 ;; arith ordinary arithmetic
213 ;; arith3 a compound insn that behaves similarly to a sequence of
214 ;; three insns of type arith
215 ;; arith3b like above, but might end with a redirected branch
217 ;; load_si Likewise, SImode variant for general register.
218 ;; fload Likewise, but load to fp register.
220 ;; fstore floating point register to memory
221 ;; move general purpose register to register
222 ;; movi8 8-bit immediate to general purpose register
223 ;; mt_group other sh4 mt instructions
224 ;; fmove register to register, floating point
225 ;; smpy word precision integer multiply
226 ;; dmpy longword or doublelongword precision integer multiply
228 ;; pload load of pr reg, which can't be put into delay slot of rts
229 ;; prset copy register to pr reg, ditto
230 ;; pstore store of pr reg, which can't be put into delay slot of jsr
231 ;; prget copy pr to register, ditto
232 ;; pcload pc relative load of constant value
233 ;; pcfload Likewise, but load to fp register.
234 ;; pcload_si Likewise, SImode variant for general register.
235 ;; rte return from exception
236 ;; sfunc special function call with known used registers
237 ;; call function call
239 ;; fpscr_toggle toggle a bit in the fpscr
240 ;; fdiv floating point divide (or square root)
241 ;; gp_fpul move from general purpose register to fpul
242 ;; fpul_gp move from fpul to general purpose register
243 ;; mac_gp move from mac[lh] to general purpose register
244 ;; gp_mac move from general purpose register to mac[lh]
245 ;; mac_mem move from mac[lh] to memory
246 ;; mem_mac move from memory to mac[lh]
247 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
248 ;; ftrc_s fix_truncsfsi2_i4
249 ;; dfdiv double precision floating point divide (or square root)
250 ;; cwb ic_invalidate_line_i
251 ;; movua SH4a unaligned load
252 ;; fsrra square root reciprocal approximate
253 ;; fsca sine and cosine approximate
254 ;; tls_load load TLS related address
255 ;; arith_media SHmedia arithmetic, logical, and shift instructions
256 ;; cbranch_media SHmedia conditional branch instructions
257 ;; cmp_media SHmedia compare instructions
258 ;; dfdiv_media SHmedia double precision divide and square root
259 ;; dfmul_media SHmedia double precision multiply instruction
260 ;; dfparith_media SHmedia double precision floating point arithmetic
261 ;; dfpconv_media SHmedia double precision floating point conversions
262 ;; dmpy_media SHmedia longword multiply
263 ;; fcmp_media SHmedia floating point compare instructions
264 ;; fdiv_media SHmedia single precision divide and square root
265 ;; fload_media SHmedia floating point register load instructions
266 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
267 ;; fparith_media SHmedia single precision floating point arithmetic
268 ;; fpconv_media SHmedia single precision floating point conversions
269 ;; fstore_media SHmedia floating point register store instructions
270 ;; gettr_media SHmedia gettr instruction
271 ;; invalidate_line_media SHmedia invalidate_line sequence
272 ;; jump_media SHmedia unconditional branch instructions
273 ;; load_media SHmedia general register load instructions
274 ;; pt_media SHmedia pt instruction (expanded by assembler)
275 ;; ptabs_media SHmedia ptabs instruction
276 ;; store_media SHmedia general register store instructions
277 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
278 ;; mac_media SHmedia mac-style fixed point operations
279 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
280 ;; atrans_media SHmedia approximate transcendental functions
281 ;; ustore_media SHmedia unaligned stores
282 ;; nil no-op move, will be deleted.
285 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
286 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
287 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
288 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
289 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
290 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
291 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
292 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
293 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
294 d2mpy_media,atrans_media,ustore_media,nil,other"
295 (const_string "other"))
297 ;; We define a new attribute namely "insn_class".We use
298 ;; this for the DFA based pipeline description.
300 ;; mt_group SH4 "mt" group instructions.
302 ;; ex_group SH4 "ex" group instructions.
304 ;; ls_group SH4 "ls" group instructions.
306 (define_attr "insn_class"
307 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
308 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
309 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
310 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
311 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
312 (eq_attr "type" "cbranch,jump") (const_string "br_group")
313 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
314 (const_string "fe_group")
315 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
316 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
317 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
318 (const_string "none")))
320 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
321 ;; so these do not belong in an insn group, although they are modeled
322 ;; with their own define_insn_reservations.
324 ;; Indicate what precision must be selected in fpscr for this insn, if any.
325 (define_attr "fp_mode" "single,double,none" (const_string "none"))
327 ;; Indicate if the fpu mode is set by this instruction
328 ;; "unknown" must have the value as "none" in fp_mode, and means
329 ;; that the instruction/abi has left the processor in an unknown
331 ;; "none" means that nothing has changed and no mode is set.
332 ;; This attribute is only used for the Renesas ABI.
333 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
335 ; If a conditional branch destination is within -252..258 bytes away
336 ; from the instruction it can be 2 bytes long. Something in the
337 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
338 ; branches are initially assumed to be 16 bytes long.
339 ; In machine_dependent_reorg, we split all branches that are longer than
342 ;; The maximum range used for SImode constant pool entries is 1018. A final
343 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
344 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
345 ;; instruction around the pool table, 2 bytes of alignment before the table,
346 ;; and 30 bytes of alignment after the table. That gives a maximum total
347 ;; pool size of 1058 bytes.
348 ;; Worst case code/pool content size ratio is 1:2 (using asms).
349 ;; Thus, in the worst case, there is one instruction in front of a maximum
350 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
351 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
352 ;; If we have a forward branch, the initial table will be put after the
353 ;; unconditional branch.
355 ;; ??? We could do much better by keeping track of the actual pcloads within
356 ;; the branch range and in the pcload range in front of the branch range.
358 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
360 (define_attr "short_cbranch_p" "no,yes"
361 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
365 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
367 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
369 ] (const_string "no")))
371 (define_attr "med_branch_p" "no,yes"
372 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
375 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
377 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
380 ] (const_string "no")))
382 (define_attr "med_cbranch_p" "no,yes"
383 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
386 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
388 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
391 ] (const_string "no")))
393 (define_attr "braf_branch_p" "no,yes"
394 (cond [(match_test "! TARGET_SH2")
396 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
404 ] (const_string "no")))
406 (define_attr "braf_cbranch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
417 ] (const_string "no")))
419 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
420 ;; For wider ranges, we need a combination of a code and a data part.
421 ;; If we can get a scratch register for a long range jump, the code
422 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
423 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
424 ;; long; otherwise, it must be 6 bytes long.
426 ;; All other instructions are two bytes long by default.
428 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
429 ;; but getattrtab doesn't understand this.
430 (define_attr "length" ""
431 (cond [(eq_attr "type" "cbranch")
432 (cond [(eq_attr "short_cbranch_p" "yes")
434 (eq_attr "med_cbranch_p" "yes")
436 (eq_attr "braf_cbranch_p" "yes")
438 ;; ??? using pc is not computed transitively.
439 (ne (match_dup 0) (match_dup 0))
441 (match_test "flag_pic")
444 (eq_attr "type" "jump")
445 (cond [(eq_attr "med_branch_p" "yes")
447 (and (match_test "prev_nonnote_insn (insn)")
448 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
450 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
451 (symbol_ref "code_for_indirect_jump_scratch"))))
452 (cond [(eq_attr "braf_branch_p" "yes")
454 (not (match_test "flag_pic"))
456 (match_test "TARGET_SH2")
457 (const_int 10)] (const_int 18))
458 (eq_attr "braf_branch_p" "yes")
460 ;; ??? using pc is not computed transitively.
461 (ne (match_dup 0) (match_dup 0))
463 (match_test "flag_pic")
466 (eq_attr "type" "pt_media")
467 (if_then_else (match_test "TARGET_SHMEDIA64")
468 (const_int 20) (const_int 12))
469 (and (eq_attr "type" "jump_media")
470 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
472 ] (if_then_else (match_test "TARGET_SHMEDIA")
476 ;; DFA descriptions for the pipelines
479 (include "shmedia.md")
482 (include "iterators.md")
483 (include "predicates.md")
484 (include "constraints.md")
486 ;; Definitions for filling delay slots
488 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
490 (define_attr "banked" "yes,no"
491 (cond [(match_test "sh_loads_bankedreg_p (insn)")
492 (const_string "yes")]
493 (const_string "no")))
495 ;; ??? This should be (nil) instead of (const_int 0)
496 (define_attr "hit_stack" "yes,no"
497 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
499 (const_string "yes")))
501 (define_attr "interrupt_function" "no,yes"
502 (const (symbol_ref "current_function_interrupt")))
504 (define_attr "in_delay_slot" "yes,no"
505 (cond [(eq_attr "type" "cbranch") (const_string "no")
506 (eq_attr "type" "pcload,pcload_si") (const_string "no")
507 (eq_attr "type" "fpscr_toggle") (const_string "no")
508 (eq_attr "needs_delay_slot" "yes") (const_string "no")
509 (eq_attr "length" "2") (const_string "yes")
510 ] (const_string "no")))
512 (define_attr "cond_delay_slot" "yes,no"
513 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
514 ] (const_string "no")))
516 (define_attr "is_sfunc" ""
517 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
519 (define_attr "is_mac_media" ""
520 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
522 (define_attr "branch_zero" "yes,no"
523 (cond [(eq_attr "type" "!cbranch") (const_string "no")
524 (ne (symbol_ref "(next_active_insn (insn)\
525 == (prev_active_insn\
526 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
527 && get_attr_length (next_active_insn (insn)) == 2")
529 (const_string "yes")]
530 (const_string "no")))
532 ;; SH4 Double-precision computation with double-precision result -
533 ;; the two halves are ready at different times.
534 (define_attr "dfp_comp" "yes,no"
535 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
536 (const_string "no")))
538 ;; Insns for which the latency of a preceding fp insn is decreased by one.
539 (define_attr "late_fp_use" "yes,no" (const_string "no"))
540 ;; And feeding insns for which this relevant.
541 (define_attr "any_fp_comp" "yes,no"
542 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
543 (const_string "yes")]
544 (const_string "no")))
546 (define_attr "any_int_load" "yes,no"
547 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
548 (const_string "yes")]
549 (const_string "no")))
551 (define_attr "highpart" "user, ignore, extend, depend, must_split"
552 (const_string "user"))
555 (eq_attr "needs_delay_slot" "yes")
556 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
558 ;; Since a normal return (rts) implicitly uses the PR register,
559 ;; we can't allow PR register loads in an rts delay slot.
560 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
561 ;; stack, and thus we can't put a pop instruction in its delay slot.
562 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
563 ;; pop instruction can go in the delay slot, unless it references a banked
564 ;; register (the register bank is switched by rte).
566 (eq_attr "type" "return")
567 [(and (eq_attr "in_delay_slot" "yes")
568 (ior (and (eq_attr "interrupt_function" "no")
569 (eq_attr "type" "!pload,prset"))
570 (and (eq_attr "interrupt_function" "yes")
571 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
572 (eq_attr "banked" "no"))))
575 ;; Since a call implicitly uses the PR register, we can't allow
576 ;; a PR register store in a jsr delay slot.
579 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
580 [(and (eq_attr "in_delay_slot" "yes")
581 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
583 ;; Say that we have annulled true branches, since this gives smaller and
584 ;; faster code when branches are predicted as not taken.
586 ;; ??? The non-annulled condition should really be "in_delay_slot",
587 ;; but insns that can be filled in non-annulled get priority over insns
588 ;; that can only be filled in anulled.
591 (and (eq_attr "type" "cbranch")
592 (match_test "TARGET_SH2"))
593 ;; SH2e has a hardware bug that pretty much prohibits the use of
594 ;; annulled delay slots.
595 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
596 (not (eq_attr "cpu" "sh2e"))) (nil)])
598 ;; -------------------------------------------------------------------------
599 ;; SImode signed integer comparisons
600 ;; -------------------------------------------------------------------------
602 ;; Various patterns to generate the TST #imm, R0 instruction.
603 ;; Although this adds some pressure on the R0 register, it can potentially
604 ;; result in faster code, even if the operand has to be moved to R0 first.
605 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
606 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
607 ;; is an EX group instruction but still can be executed in parallel with the
608 ;; MT group MOV Rm, Rn instruction.
610 ;; Usual TST #imm, R0 patterns for SI, HI and QI
611 ;; This is usually used for bit patterns other than contiguous bits
613 (define_insn "tstsi_t"
615 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
616 (match_operand:SI 1 "logical_operand" "K08,r"))
620 [(set_attr "type" "mt_group")])
622 (define_insn "tsthi_t"
624 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
625 (match_operand 1 "const_int_operand")) 0)
628 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
630 [(set_attr "type" "mt_group")])
632 (define_insn "tstqi_t"
634 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
635 (match_operand 1 "const_int_operand")) 0)
638 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
639 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
641 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
644 [(set_attr "type" "mt_group")])
646 ;; Test low QI subreg against zero.
647 ;; This avoids unnecessary zero extension before the test.
648 (define_insn "*tstqi_t_zero"
650 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
653 [(set_attr "type" "mt_group")])
655 ;; This pattern might be risky because it also tests the upper bits and not
656 ;; only the subreg. However, it seems that combine will get to this only
657 ;; when testing sign/zero extended values. In this case the extended upper
658 ;; bits do not matter.
659 (define_insn "*tst<mode>_t_zero"
663 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
664 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_le>)
666 "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
668 [(set_attr "type" "mt_group")])
670 (define_insn "*tst<mode>_t_zero"
674 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
675 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
677 "TARGET_SH1 && TARGET_BIG_ENDIAN"
679 [(set_attr "type" "mt_group")])
681 ;; Extract LSB, negate and store in T bit.
682 (define_insn "tstsi_t_and_not"
684 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
688 [(set_attr "type" "mt_group")])
690 ;; Extract contiguous bits and compare them against zero.
691 (define_insn "tst<mode>_t_zero_extract_eq"
693 (eq:SI (zero_extract:SI (match_operand:QIHISIDI 0 "logical_operand" "z")
694 (match_operand:SI 1 "const_int_operand")
695 (match_operand:SI 2 "const_int_operand"))
698 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
700 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
703 [(set_attr "type" "mt_group")])
705 ;; This split is required when testing bits in a QI subreg.
710 (zero_extract:SI (match_operand 0 "logical_operand")
711 (match_operand 1 "const_int_operand")
712 (match_operand 2 "const_int_operand"))
713 (match_operand 3 "const_int_operand")
717 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
718 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
719 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
722 if (GET_MODE (operands[0]) == QImode)
723 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
726 ;; Extract single bit, negate and store it in the T bit.
727 ;; Not used for SH4A.
728 (define_insn "tstsi_t_zero_extract_xor"
730 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
731 (match_operand:SI 3 "const_int_operand"))
732 (match_operand:SI 1 "const_int_operand")
733 (match_operand:SI 2 "const_int_operand")))]
735 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
736 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
738 [(set_attr "type" "mt_group")])
740 ;; Extract single bit, negate and store it in the T bit.
741 ;; Used for SH4A little endian.
742 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
745 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
746 (match_operand:SI 3 "const_int_operand")) 0)
747 (match_operand:SI 1 "const_int_operand")
748 (match_operand:SI 2 "const_int_operand")))]
749 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
750 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
751 == (INTVAL (operands[3]) & 255)
752 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
754 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
757 [(set_attr "type" "mt_group")])
759 ;; Extract single bit, negate and store it in the T bit.
760 ;; Used for SH4A big endian.
761 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
764 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
765 (match_operand:SI 3 "const_int_operand")) 3)
766 (match_operand:SI 1 "const_int_operand")
767 (match_operand:SI 2 "const_int_operand")))]
768 "TARGET_SH1 && TARGET_BIG_ENDIAN
769 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
770 == (INTVAL (operands[3]) & 255)
771 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
773 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
776 [(set_attr "type" "mt_group")])
778 (define_insn "cmpeqsi_t"
780 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
781 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
787 [(set_attr "type" "mt_group")])
789 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
790 ;; pattern by itself. What this actually does is:
791 ;; x == 0: (1 >> 0-0) & 1 = 1
792 ;; x != 0: (1 >> 0-x) & 1 = 0
793 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
794 (define_insn_and_split "*cmpeqsi_t"
798 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
803 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
805 (define_insn "cmpgtsi_t"
807 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
808 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
813 [(set_attr "type" "mt_group")])
815 (define_insn "cmpgesi_t"
817 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
818 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
823 [(set_attr "type" "mt_group")])
825 ;; FIXME: This is actually wrong. There is no way to literally move a
826 ;; general reg to t reg. Luckily, it seems that this pattern will be only
827 ;; used when the general reg is known be either '0' or '1' during combine.
828 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
829 ;; Due to interactions with other patterns, combine fails to pick the latter
830 ;; and invert the dependent logic.
831 (define_insn "*negtstsi"
832 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
835 [(set_attr "type" "mt_group")])
837 ;; Some integer sign comparison patterns can be realized with the div0s insn.
838 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
839 (define_insn "cmp_div0s_0"
841 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
842 (match_operand:SI 1 "arith_reg_operand" "r"))
846 [(set_attr "type" "arith")])
848 (define_insn "cmp_div0s_1"
850 (lt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
851 (match_operand:SI 1 "arith_reg_operand" "r"))
855 [(set_attr "type" "arith")])
857 (define_insn_and_split "*cmp_div0s_0"
858 [(set (match_operand:SI 0 "arith_reg_dest" "")
859 (lshiftrt:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
860 (match_operand:SI 2 "arith_reg_operand" ""))
862 (clobber (reg:SI T_REG))]
867 (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31)))
868 (set (match_dup 0) (reg:SI T_REG))])
870 (define_insn "*cmp_div0s_0"
872 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
874 (ge:SI (match_operand:SI 1 "arith_reg_operand")
878 [(set_attr "type" "arith")])
880 (define_insn_and_split "*cmp_div0s_1"
881 [(set (match_operand:SI 0 "arith_reg_dest" "")
882 (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
883 (match_operand:SI 2 "arith_reg_operand" ""))
885 (clobber (reg:SI T_REG))]
888 "&& can_create_pseudo_p ()"
890 ;; We have to go through the movnegt expander here which will handle the
891 ;; SH2A vs non-SH2A cases.
893 emit_insn (gen_cmp_div0s_1 (operands[1], operands[2]));
894 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
898 (define_insn_and_split "*cmp_div0s_1"
900 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
901 (match_operand:SI 1 "arith_reg_operand" ""))
905 "&& can_create_pseudo_p ()"
906 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
908 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
910 (define_insn_and_split "*cmp_div0s_1"
912 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
914 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
918 "&& can_create_pseudo_p ()"
919 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
921 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
923 ;; -------------------------------------------------------------------------
924 ;; SImode compare and branch
925 ;; -------------------------------------------------------------------------
927 (define_expand "cbranchsi4"
929 (if_then_else (match_operator 0 "comparison_operator"
930 [(match_operand:SI 1 "arith_operand" "")
931 (match_operand:SI 2 "arith_operand" "")])
932 (label_ref (match_operand 3 "" ""))
934 (clobber (reg:SI T_REG))]
938 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
939 operands[2], operands[3]));
941 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
946 ;; Combine patterns to invert compare and branch operations for which we
947 ;; don't have actual comparison insns. These patterns are used in cases
948 ;; which appear after the initial cbranchsi expansion, which also does
949 ;; some condition inversion.
952 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
953 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
954 (label_ref (match_operand 2))
956 (clobber (reg:SI T_REG))]
958 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
959 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
960 (label_ref (match_dup 2))
963 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
964 ;; and SH2A combine fails to simplify this pattern by itself.
965 ;; What this actually does is:
966 ;; x == 0: (1 >> 0-0) & 1 = 1
967 ;; x != 0: (1 >> 0-x) & 1 = 0
968 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
972 (eq (and:SI (lshiftrt:SI
974 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
977 (label_ref (match_operand 2))
979 (clobber (reg:SI T_REG))]
981 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
982 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
983 (label_ref (match_dup 2))
986 ;; FIXME: These could probably use code iterators for the compare op.
989 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
990 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
991 (label_ref (match_operand 2))
993 (clobber (reg:SI T_REG))]
995 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
996 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
997 (label_ref (match_dup 2))
1002 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1003 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1004 (label_ref (match_operand 2))
1006 (clobber (reg:SI T_REG))]
1008 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1009 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1010 (label_ref (match_dup 2))
1015 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1016 (match_operand:SI 1 "arith_reg_operand" ""))
1017 (label_ref (match_operand 2))
1019 (clobber (reg:SI T_REG))]
1021 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1022 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1023 (label_ref (match_dup 2))
1028 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1029 (match_operand:SI 1 "arith_reg_operand" ""))
1030 (label_ref (match_operand 2))
1032 (clobber (reg:SI T_REG))]
1034 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1035 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1036 (label_ref (match_dup 2))
1039 ;; Compare and branch combine patterns for div0s comparisons.
1040 (define_insn_and_split "*cbranch_div0s"
1042 (if_then_else (lt (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1043 (match_operand:SI 1 "arith_reg_operand" ""))
1045 (label_ref (match_operand 2))
1047 (clobber (reg:SI T_REG))]
1051 [(set (reg:SI T_REG)
1052 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1054 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1055 (label_ref (match_dup 2))
1058 (define_insn_and_split "*cbranch_div0s"
1060 (if_then_else (ge (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1061 (match_operand:SI 1 "arith_reg_operand" ""))
1063 (label_ref (match_operand 2))
1065 (clobber (reg:SI T_REG))]
1069 [(set (reg:SI T_REG)
1070 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1072 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1073 (label_ref (match_dup 2))
1076 ;; Conditional move combine pattern for div0s comparisons.
1077 ;; This is used when TARGET_PRETEND_CMOVE is in effect.
1078 (define_insn_and_split "*movsicc_div0s"
1079 [(set (match_operand:SI 0 "arith_reg_dest" "")
1080 (if_then_else:SI (ge (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
1081 (match_operand:SI 2 "arith_reg_operand" ""))
1083 (match_operand:SI 3 "arith_reg_operand" "")
1084 (match_operand:SI 4 "general_movsrc_operand" "")))
1085 (clobber (reg:SI T_REG))]
1086 "TARGET_PRETEND_CMOVE"
1089 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1092 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1096 (define_insn_and_split "*movsicc_div0s"
1097 [(set (match_operand:SI 0 "arith_reg_dest")
1098 (if_then_else:SI (eq (lshiftrt:SI
1099 (match_operand:SI 1 "arith_reg_operand")
1102 (match_operand:SI 2 "arith_reg_operand")
1104 (match_operand:SI 3 "arith_reg_operand")
1105 (match_operand:SI 4 "general_movsrc_operand")))
1106 (clobber (reg:SI T_REG))]
1107 "TARGET_PRETEND_CMOVE"
1110 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1113 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1117 ;; -------------------------------------------------------------------------
1118 ;; SImode unsigned integer comparisons
1119 ;; -------------------------------------------------------------------------
1121 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1122 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1123 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1124 ;; handled here, something else would just load a '0' into the second operand
1125 ;; and do the comparison. We can do slightly better by just setting the
1127 (define_insn_and_split "cmpgeusi_t"
1128 [(set (reg:SI T_REG)
1129 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1130 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1133 "&& satisfies_constraint_Z (operands[1])"
1134 [(set (reg:SI T_REG) (const_int 1))]
1136 [(set_attr "type" "mt_group")])
1138 (define_insn "cmpgtusi_t"
1139 [(set (reg:SI T_REG)
1140 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1141 (match_operand:SI 1 "arith_reg_operand" "r")))]
1144 [(set_attr "type" "mt_group")])
1146 ;; -------------------------------------------------------------------------
1147 ;; DImode compare and branch
1148 ;; -------------------------------------------------------------------------
1150 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1151 ;; Therefore, we aim to have a set of three branches that go straight to the
1152 ;; destination, i.e. only one of them is taken at any one time.
1153 ;; This mechanism should also be slightly better for the sh4-200.
1155 (define_expand "cbranchdi4"
1157 (if_then_else (match_operator 0 "comparison_operator"
1158 [(match_operand:DI 1 "arith_operand" "")
1159 (match_operand:DI 2 "arith_operand" "")])
1160 (label_ref (match_operand 3 "" ""))
1162 (clobber (match_dup 4))
1163 (clobber (reg:SI T_REG))]
1164 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1166 enum rtx_code comparison;
1170 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1171 operands[2], operands[3]));
1174 else if (!TARGET_CBRANCHDI4)
1176 sh_emit_compare_and_branch (operands, DImode);
1181 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1184 comparison = prepare_cbranch_operands (operands, DImode,
1185 LAST_AND_UNUSED_RTX_CODE);
1186 if (comparison != GET_CODE (operands[0]))
1188 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1189 operands[4] = gen_rtx_SCRATCH (SImode);
1193 (define_insn_and_split "cbranchdi4_i"
1195 (if_then_else (match_operator 0 "comparison_operator"
1196 [(match_operand:DI 1 "arith_operand" "r,r")
1197 (match_operand:DI 2 "arith_operand" "rN,I08")])
1198 (label_ref (match_operand 3 "" ""))
1200 (clobber (match_scratch:SI 4 "=X,&r"))
1201 (clobber (reg:SI T_REG))]
1204 "&& reload_completed"
1207 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1212 ;; -------------------------------------------------------------------------
1213 ;; DImode signed integer comparisons
1214 ;; -------------------------------------------------------------------------
1217 [(set (reg:SI T_REG)
1218 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1219 (match_operand:DI 1 "arith_operand" "r"))
1223 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1226 [(set_attr "length" "6")
1227 (set_attr "type" "arith3b")])
1229 (define_insn "cmpeqdi_t"
1230 [(set (reg:SI T_REG)
1231 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1232 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1235 static const char* alt[] =
1242 "cmp/eq %S1,%S0" "\n"
1244 " cmp/eq %R1,%R0" "\n"
1247 return alt[which_alternative];
1249 [(set_attr "length" "6")
1250 (set_attr "type" "arith3b")])
1253 [(set (reg:SI T_REG)
1254 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1255 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1256 ;; If we applied this split when not optimizing, it would only be
1257 ;; applied during the machine-dependent reorg, when no new basic blocks
1259 "TARGET_SH1 && reload_completed && optimize"
1260 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1261 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1262 (label_ref (match_dup 6))
1264 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1267 operands[2] = gen_highpart (SImode, operands[0]);
1268 operands[3] = operands[1] == const0_rtx
1270 : gen_highpart (SImode, operands[1]);
1271 operands[4] = gen_lowpart (SImode, operands[0]);
1272 operands[5] = gen_lowpart (SImode, operands[1]);
1273 operands[6] = gen_label_rtx ();
1276 (define_insn "cmpgtdi_t"
1277 [(set (reg:SI T_REG)
1278 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1279 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1282 static const char* alt[] =
1284 "cmp/eq %S1,%S0" "\n"
1286 " cmp/gt %S1,%S0" "\n"
1287 " cmp/hi %R1,%R0" "\n"
1293 " cmp/hi %S0,%R0" "\n"
1296 return alt[which_alternative];
1298 [(set_attr "length" "8")
1299 (set_attr "type" "arith3")])
1301 (define_insn "cmpgedi_t"
1302 [(set (reg:SI T_REG)
1303 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1304 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1307 static const char* alt[] =
1309 "cmp/eq %S1,%S0" "\n"
1311 " cmp/ge %S1,%S0" "\n"
1312 " cmp/hs %R1,%R0" "\n"
1317 return alt[which_alternative];
1319 [(set_attr "length" "8,2")
1320 (set_attr "type" "arith3,mt_group")])
1322 ;; -------------------------------------------------------------------------
1323 ;; DImode unsigned integer comparisons
1324 ;; -------------------------------------------------------------------------
1326 (define_insn "cmpgeudi_t"
1327 [(set (reg:SI T_REG)
1328 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1329 (match_operand:DI 1 "arith_reg_operand" "r")))]
1332 return "cmp/eq %S1,%S0" "\n"
1334 " cmp/hs %S1,%S0" "\n"
1335 " cmp/hs %R1,%R0" "\n"
1338 [(set_attr "length" "8")
1339 (set_attr "type" "arith3")])
1341 (define_insn "cmpgtudi_t"
1342 [(set (reg:SI T_REG)
1343 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1344 (match_operand:DI 1 "arith_reg_operand" "r")))]
1347 return "cmp/eq %S1,%S0" "\n"
1349 " cmp/hi %S1,%S0" "\n"
1350 " cmp/hi %R1,%R0" "\n"
1353 [(set_attr "length" "8")
1354 (set_attr "type" "arith3")])
1356 (define_insn "cmpeqsi_media"
1357 [(set (match_operand:SI 0 "register_operand" "=r")
1358 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1359 (match_operand:SI 2 "cmp_operand" "Nr")))]
1362 [(set_attr "type" "cmp_media")])
1364 (define_insn "cmpeqdi_media"
1365 [(set (match_operand:SI 0 "register_operand" "=r")
1366 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1367 (match_operand:DI 2 "cmp_operand" "Nr")))]
1370 [(set_attr "type" "cmp_media")])
1372 (define_insn "cmpgtsi_media"
1373 [(set (match_operand:SI 0 "register_operand" "=r")
1374 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1375 (match_operand:SI 2 "cmp_operand" "rN")))]
1377 "cmpgt %N1, %N2, %0"
1378 [(set_attr "type" "cmp_media")])
1380 (define_insn "cmpgtdi_media"
1381 [(set (match_operand:SI 0 "register_operand" "=r")
1382 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1383 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1385 "cmpgt %N1, %N2, %0"
1386 [(set_attr "type" "cmp_media")])
1388 (define_insn "cmpgtusi_media"
1389 [(set (match_operand:SI 0 "register_operand" "=r")
1390 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1391 (match_operand:SI 2 "cmp_operand" "rN")))]
1393 "cmpgtu %N1, %N2, %0"
1394 [(set_attr "type" "cmp_media")])
1396 (define_insn "cmpgtudi_media"
1397 [(set (match_operand:SI 0 "register_operand" "=r")
1398 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1399 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1401 "cmpgtu %N1, %N2, %0"
1402 [(set_attr "type" "cmp_media")])
1404 ; This pattern is for combine.
1405 (define_insn "*cmpne0sisi_media"
1406 [(set (match_operand:SI 0 "register_operand" "=r")
1407 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1410 [(set_attr "type" "cmp_media")])
1412 ;; -------------------------------------------------------------------------
1413 ;; Conditional move instructions
1414 ;; -------------------------------------------------------------------------
1416 ;; The insn names may seem reversed, but note that cmveq performs the move
1417 ;; if op1 == 0, and cmvne does it if op1 != 0.
1419 (define_insn "movdicc_false"
1420 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1421 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1423 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1424 (match_operand:DI 3 "arith_reg_operand" "0")))]
1427 [(set_attr "type" "arith_media")])
1429 (define_insn "movdicc_true"
1430 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1431 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1433 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1434 (match_operand:DI 3 "arith_reg_operand" "0")))]
1437 [(set_attr "type" "arith_media")])
1440 [(set (match_operand:DI 0 "arith_reg_dest" "")
1441 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1442 [(match_operand:DI 1 "arith_reg_operand" "")
1444 (match_operand:DI 2 "arith_reg_dest" "")
1446 (set (match_dup 2) (match_dup 0))]
1447 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1449 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1451 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1452 VOIDmode, operands[1], CONST0_RTX (DImode));
1456 [(set (match_operand:DI 0 "general_movdst_operand" "")
1457 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1458 (set (match_operand:DI 2 "arith_reg_dest" "")
1459 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1460 [(match_operand:DI 3 "arith_reg_operand" "")
1464 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1466 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1469 (define_expand "movdicc"
1470 [(set (match_operand:DI 0 "register_operand" "")
1471 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1472 (match_operand:DI 2 "register_operand" "")
1473 (match_operand:DI 3 "register_operand" "")))]
1476 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1477 && GET_MODE (XEXP (operands[1], 0)) == DImode
1478 && XEXP (operands[1], 1) == const0_rtx)
1482 if (!can_create_pseudo_p ())
1485 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1486 GET_CODE (operands[1]),
1487 XEXP (operands[1], 0),
1488 XEXP (operands[1], 1));
1494 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1495 ;; SImode to DImode.
1496 (define_insn "movsicc_false"
1497 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1498 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1500 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1501 (match_operand:SI 3 "arith_reg_operand" "0")))]
1504 [(set_attr "type" "arith_media")])
1506 (define_insn "movsicc_true"
1507 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1508 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1510 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1511 (match_operand:SI 3 "arith_reg_operand" "0")))]
1514 [(set_attr "type" "arith_media")])
1517 [(set (match_operand:SI 0 "arith_reg_dest" "")
1518 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1519 [(match_operand:SI 1 "arith_reg_operand" "")
1521 (match_operand:SI 2 "arith_reg_dest" "")
1523 (set (match_dup 2) (match_dup 0))]
1524 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1526 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1528 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1529 VOIDmode, operands[1], CONST0_RTX (SImode));
1533 [(set (match_operand:SI 0 "general_movdst_operand" "")
1534 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1535 (set (match_operand:SI 2 "arith_reg_dest" "")
1536 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1537 [(match_operand:SI 3 "arith_reg_operand" "")
1541 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1542 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1544 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1546 replace_rtx (operands[4], operands[0], operands[1]);
1550 [(set (match_operand 0 "any_register_operand" "")
1551 (match_operand 1 "any_register_operand" ""))
1552 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1553 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1554 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1555 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1556 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1557 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1558 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1559 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1560 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1561 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1562 && (REGNO_REG_CLASS (REGNO (operands[0]))
1563 == REGNO_REG_CLASS (REGNO (operands[2])))
1564 && (REGNO_REG_CLASS (REGNO (operands[1]))
1565 == REGNO_REG_CLASS (REGNO (operands[0])))"
1566 [(set (match_dup 0) (match_dup 3))
1567 (set (match_dup 4) (match_dup 5))]
1569 rtx set1, set2, insn2;
1570 rtx replacements[4];
1572 /* We want to replace occurrences of operands[0] with operands[1] and
1573 operands[2] with operands[0] in operands[4]/operands[5].
1574 Doing just two replace_rtx calls naively would result in the second
1575 replacement undoing all that the first did if operands[1] and operands[2]
1576 are identical, so we must do this simultaneously. */
1577 replacements[0] = operands[0];
1578 replacements[1] = operands[1];
1579 replacements[2] = operands[2];
1580 replacements[3] = operands[0];
1581 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1582 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1583 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1586 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1587 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1588 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1589 /* The operands array is aliased to recog_data.operand, which gets
1590 clobbered by extract_insn, so finish with it now. */
1591 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1592 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1593 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1594 always uses emit_insn. */
1595 /* Check that we don't violate matching constraints or earlyclobbers. */
1596 extract_insn (emit_insn (set1));
1597 if (! constrain_operands (1))
1599 insn2 = emit (set2);
1600 if (GET_CODE (insn2) == BARRIER)
1602 extract_insn (insn2);
1603 if (! constrain_operands (1))
1607 tmp = replacements[0];
1608 replacements[0] = replacements[1];
1609 replacements[1] = tmp;
1610 tmp = replacements[2];
1611 replacements[2] = replacements[3];
1612 replacements[3] = tmp;
1613 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1614 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1615 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1621 ;; The register allocator is rather clumsy in handling multi-way conditional
1622 ;; moves, so allow the combiner to make them, and we split them up after
1624 (define_insn_and_split "*movsicc_umin"
1625 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1626 (umin:SI (if_then_else:SI
1627 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1629 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1630 (match_operand:SI 3 "register_operand" "0"))
1631 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1632 (clobber (match_scratch:SI 5 "=&r"))]
1633 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1635 "TARGET_SHMEDIA && reload_completed"
1638 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1640 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1641 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1646 (define_insn "*movsicc_t_false"
1647 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1648 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1649 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1650 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1651 "TARGET_PRETEND_CMOVE
1652 && (arith_reg_operand (operands[1], SImode)
1653 || (immediate_operand (operands[1], SImode)
1654 && satisfies_constraint_I08 (operands[1])))"
1660 [(set_attr "type" "mt_group,arith") ;; poor approximation
1661 (set_attr "length" "4")])
1663 (define_insn "*movsicc_t_true"
1664 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1665 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1666 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1667 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1668 "TARGET_PRETEND_CMOVE
1669 && (arith_reg_operand (operands[1], SImode)
1670 || (immediate_operand (operands[1], SImode)
1671 && satisfies_constraint_I08 (operands[1])))"
1677 [(set_attr "type" "mt_group,arith") ;; poor approximation
1678 (set_attr "length" "4")])
1680 (define_expand "movsicc"
1681 [(set (match_operand:SI 0 "arith_reg_dest" "")
1682 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1683 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1684 (match_operand:SI 3 "arith_reg_operand" "")))]
1685 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1687 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1688 && GET_MODE (XEXP (operands[1], 0)) == SImode
1690 || (REG_P (XEXP (operands[1], 0))
1691 && REGNO (XEXP (operands[1], 0)) == T_REG))
1692 && XEXP (operands[1], 1) == const0_rtx)
1695 else if (TARGET_PRETEND_CMOVE)
1697 enum rtx_code code = GET_CODE (operands[1]);
1698 enum rtx_code new_code = code;
1699 rtx op0 = XEXP (operands[1], 0);
1700 rtx op1 = XEXP (operands[1], 1);
1702 if (! currently_expanding_to_rtl)
1706 case LT: case LE: case LEU: case LTU:
1707 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1710 new_code = reverse_condition (code);
1712 case EQ: case GT: case GE: case GEU: case GTU:
1717 sh_emit_scc_to_t (new_code, op0, op1);
1718 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1719 gen_rtx_REG (SImode, T_REG), const0_rtx);
1723 if (!can_create_pseudo_p ())
1726 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1727 GET_CODE (operands[1]),
1728 XEXP (operands[1], 0),
1729 XEXP (operands[1], 1));
1735 (define_expand "movqicc"
1736 [(set (match_operand:QI 0 "register_operand" "")
1737 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1738 (match_operand:QI 2 "register_operand" "")
1739 (match_operand:QI 3 "register_operand" "")))]
1742 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1743 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1744 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1745 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1749 ;; -------------------------------------------------------------------------
1750 ;; Addition instructions
1751 ;; -------------------------------------------------------------------------
1753 (define_expand "adddi3"
1754 [(set (match_operand:DI 0 "arith_reg_operand")
1755 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1756 (match_operand:DI 2 "arith_operand")))]
1761 operands[2] = force_reg (DImode, operands[2]);
1762 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1767 (define_insn "*adddi3_media"
1768 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1769 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1770 (match_operand:DI 2 "arith_operand" "r,I10")))]
1775 [(set_attr "type" "arith_media")])
1777 (define_insn "*adddisi3_media"
1778 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1779 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1780 (match_operand:DI 2 "arith_operand" "r,I10")))]
1785 [(set_attr "type" "arith_media")
1786 (set_attr "highpart" "ignore")])
1788 (define_insn "adddi3z_media"
1789 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1791 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1792 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1794 "addz.l %1, %N2, %0"
1795 [(set_attr "type" "arith_media")
1796 (set_attr "highpart" "ignore")])
1798 (define_insn_and_split "adddi3_compact"
1799 [(set (match_operand:DI 0 "arith_reg_dest")
1800 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1801 (match_operand:DI 2 "arith_reg_operand")))
1802 (clobber (reg:SI T_REG))]
1805 "&& can_create_pseudo_p ()"
1808 emit_insn (gen_clrt ());
1809 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1810 gen_lowpart (SImode, operands[1]),
1811 gen_lowpart (SImode, operands[2])));
1812 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1813 gen_highpart (SImode, operands[1]),
1814 gen_highpart (SImode, operands[2])));
1819 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1820 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1821 (match_operand:SI 2 "arith_reg_operand" "r"))
1824 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1827 [(set_attr "type" "arith")])
1829 ;; A simplified version of the addc insn, where the exact value of the
1830 ;; T bit doesn't matter. This is easier for combine to pick up.
1831 ;; We allow a reg or 0 for one of the operands in order to be able to
1832 ;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
1834 ;; FIXME: The load of constant 0 should be split out before reload, or else
1835 ;; it will be difficult to hoist or combine the constant load.
1836 (define_insn "*addc"
1837 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1838 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1839 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
1840 (match_operand:SI 3 "t_reg_operand" "")))
1841 (clobber (reg:SI T_REG))]
1844 [(set_attr "type" "arith")])
1846 ;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
1847 ;; better, if the sett insn can be done early.
1848 (define_insn_and_split "*addc_r_r_1"
1849 [(set (match_operand:SI 0 "arith_reg_dest" "")
1850 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
1851 (match_operand:SI 2 "arith_reg_operand" ""))
1853 (clobber (reg:SI T_REG))]
1857 [(set (reg:SI T_REG) (const_int 1))
1858 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1860 (clobber (reg:SI T_REG))])])
1862 ;; Left shifts by one are usually done with an add insn to avoid T_REG
1863 ;; clobbers. Thus addc can also be used to do something like '(x << 1) + 1'.
1864 (define_insn_and_split "*addc_2r_1"
1865 [(set (match_operand:SI 0 "arith_reg_dest")
1866 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
1869 (clobber (reg:SI T_REG))]
1873 [(set (reg:SI T_REG) (const_int 1))
1874 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1876 (clobber (reg:SI T_REG))])])
1878 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1879 ;; matched. Split this up into a simple sub add sequence, as this will save
1880 ;; us one sett insn.
1881 (define_insn_and_split "*minus_plus_one"
1882 [(set (match_operand:SI 0 "arith_reg_dest" "")
1883 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1884 (match_operand:SI 2 "arith_reg_operand" ""))
1889 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1890 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1892 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1893 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1894 ;; operation, as opposed to sequences such as
1898 ;; Even if the constant is not CSE-ed, a sequence such as
1901 ;; can be scheduled much better since the load of the constant can be
1902 ;; done earlier, before any comparison insns that store the result in
1904 (define_insn_and_split "*addc_t_r"
1905 [(set (match_operand:SI 0 "arith_reg_dest")
1906 (plus:SI (match_operand:SI 1 "t_reg_operand")
1907 (match_operand:SI 2 "arith_reg_operand")))
1908 (clobber (reg:SI T_REG))]
1912 [(parallel [(set (match_dup 0)
1913 (plus:SI (plus:SI (match_dup 2) (const_int 0))
1915 (clobber (reg:SI T_REG))])])
1917 (define_insn_and_split "*addc_r_t"
1918 [(set (match_operand:SI 0 "arith_reg_dest")
1919 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1920 (match_operand:SI 2 "t_reg_operand")))
1921 (clobber (reg:SI T_REG))]
1925 [(parallel [(set (match_dup 0)
1926 (plus:SI (plus:SI (match_dup 1) (const_int 0))
1928 (clobber (reg:SI T_REG))])])
1930 ;; Use shlr-addc to do 'reg + (reg & 1)'.
1931 (define_insn_and_split "*addc_r_lsb"
1932 [(set (match_operand:SI 0 "arith_reg_dest")
1933 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1935 (match_operand:SI 2 "arith_reg_operand")))
1936 (clobber (reg:SI T_REG))]
1939 "&& can_create_pseudo_p ()"
1940 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1941 (clobber (reg:SI T_REG))])]
1943 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1946 ;; Use shlr-addc to do 'reg + reg + (reg & 1)'.
1947 (define_insn_and_split "*addc_r_r_lsb"
1948 [(set (match_operand:SI 0 "arith_reg_dest")
1949 (plus:SI (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1951 (match_operand:SI 2 "arith_reg_operand"))
1952 (match_operand:SI 3 "arith_reg_operand")))
1953 (clobber (reg:SI T_REG))]
1956 "&& can_create_pseudo_p ()"
1957 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1959 (clobber (reg:SI T_REG))])]
1961 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1964 ;; Canonicalize 'reg + (reg & 1) + reg' into 'reg + reg + (reg & 1)'.
1965 (define_insn_and_split "*addc_r_lsb_r"
1966 [(set (match_operand:SI 0 "arith_reg_dest")
1967 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1969 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1970 (match_operand:SI 3 "arith_reg_operand"))))
1971 (clobber (reg:SI T_REG))]
1974 "&& can_create_pseudo_p ()"
1975 [(parallel [(set (match_dup 0)
1976 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1979 (clobber (reg:SI T_REG))])])
1981 ;; Canonicalize '2 * reg + (reg & 1)' into 'reg + reg + (reg & 1)'.
1982 (define_insn_and_split "*addc_2r_lsb"
1983 [(set (match_operand:SI 0 "arith_reg_dest")
1984 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1986 (mult:SI (match_operand:SI 2 "arith_reg_operand")
1988 (clobber (reg:SI T_REG))]
1991 "&& can_create_pseudo_p ()"
1992 [(parallel [(set (match_dup 0)
1993 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1996 (clobber (reg:SI T_REG))])])
1998 ;; Use shll-addc to do 'reg + ((unsigned int)reg >> 31)'.
1999 (define_insn_and_split "*addc_r_msb"
2000 [(set (match_operand:SI 0 "arith_reg_dest")
2001 (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
2003 (match_operand:SI 2 "arith_reg_operand")))
2004 (clobber (reg:SI T_REG))]
2007 "&& can_create_pseudo_p ()"
2008 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
2009 (clobber (reg:SI T_REG))])]
2011 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2014 ;; Use shll-addc to do 'reg + reg + ((unsigned int)reg >> 31)'.
2015 (define_insn_and_split "*addc_r_r_msb"
2016 [(set (match_operand:SI 0 "arith_reg_dest")
2017 (plus:SI (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
2019 (match_operand:SI 2 "arith_reg_operand"))
2020 (match_operand:SI 3 "arith_reg_operand")))
2021 (clobber (reg:SI T_REG))]
2024 "&& can_create_pseudo_p ()"
2025 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
2027 (clobber (reg:SI T_REG))])]
2029 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2032 ;; Canonicalize '2 * reg + ((unsigned int)reg >> 31)'
2033 ;; into 'reg + reg + (reg & 1)'.
2034 (define_insn_and_split "*addc_2r_msb"
2035 [(set (match_operand:SI 0 "arith_reg_dest")
2036 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
2038 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
2040 (clobber (reg:SI T_REG))]
2043 "&& can_create_pseudo_p ()"
2044 [(parallel [(set (match_dup 0)
2045 (plus:SI (plus:SI (lshiftrt:SI (match_dup 2) (const_int 31))
2048 (clobber (reg:SI T_REG))])])
2050 (define_expand "addsi3"
2051 [(set (match_operand:SI 0 "arith_reg_operand" "")
2052 (plus:SI (match_operand:SI 1 "arith_operand" "")
2053 (match_operand:SI 2 "arith_operand" "")))]
2057 operands[1] = force_reg (SImode, operands[1]);
2060 (define_insn "addsi3_media"
2061 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
2062 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
2063 (match_operand:SI 2 "arith_operand" "r,I10")))]
2068 [(set_attr "type" "arith_media")
2069 (set_attr "highpart" "ignore")])
2071 (define_insn "addsidi3_media"
2072 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
2073 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
2075 (match_operand:SI 2 "arith_operand"
2081 [(set_attr "type" "arith_media")
2082 (set_attr "highpart" "ignore")])
2084 (define_insn "*addsi3_compact"
2085 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2086 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
2087 (match_operand:SI 2 "arith_operand" "rI08")))]
2090 [(set_attr "type" "arith")])
2092 ;; -------------------------------------------------------------------------
2093 ;; Subtraction instructions
2094 ;; -------------------------------------------------------------------------
2096 (define_expand "subdi3"
2097 [(set (match_operand:DI 0 "arith_reg_operand" "")
2098 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
2099 (match_operand:DI 2 "arith_reg_operand" "")))]
2104 operands[1] = force_reg (DImode, operands[1]);
2105 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
2110 (define_insn "*subdi3_media"
2111 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2112 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2113 (match_operand:DI 2 "arith_reg_operand" "r")))]
2116 [(set_attr "type" "arith_media")])
2118 (define_insn "subdisi3_media"
2119 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
2120 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2121 (match_operand:DI 2 "arith_reg_operand" "r")))]
2124 [(set_attr "type" "arith_media")
2125 (set_attr "highpart" "ignore")])
2127 (define_insn_and_split "subdi3_compact"
2128 [(set (match_operand:DI 0 "arith_reg_dest")
2129 (minus:DI (match_operand:DI 1 "arith_reg_operand")
2130 (match_operand:DI 2 "arith_reg_operand")))
2131 (clobber (reg:SI T_REG))]
2134 "&& can_create_pseudo_p ()"
2137 emit_insn (gen_clrt ());
2138 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
2139 gen_lowpart (SImode, operands[1]),
2140 gen_lowpart (SImode, operands[2])));
2141 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
2142 gen_highpart (SImode, operands[1]),
2143 gen_highpart (SImode, operands[2])));
2148 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2149 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2150 (match_operand:SI 2 "arith_reg_operand" "r"))
2153 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2158 [(set_attr "type" "arith")])
2160 ;; A simplified version of the subc insn, where the exact value of the
2161 ;; T bit doesn't matter. This is easier for combine to pick up.
2162 ;; We allow a reg or 0 for one of the operands in order to be able to
2163 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2165 (define_insn "*subc"
2166 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2167 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2168 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
2169 (match_operand:SI 3 "t_reg_operand" "")))
2170 (clobber (reg:SI T_REG))]
2173 [(set_attr "type" "arith")])
2175 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2176 ;; better, if the sett insn can be done early.
2177 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2178 (define_insn_and_split "*subc"
2179 [(set (match_operand:SI 0 "arith_reg_dest" "")
2180 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2181 (match_operand:SI 2 "arith_reg_operand" "")))
2182 (clobber (reg:SI T_REG))]
2186 [(set (reg:SI T_REG) (const_int 1))
2187 (parallel [(set (match_dup 0)
2188 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2190 (clobber (reg:SI T_REG))])])
2192 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2193 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2194 ;; operation, as opposed to sequences such as
2198 ;; Even if the constant is not CSE-ed, a sequence such as
2201 ;; can be scheduled much better since the load of the constant can be
2202 ;; done earlier, before any comparison insns that store the result in
2204 (define_insn_and_split "*subc"
2205 [(set (match_operand:SI 0 "arith_reg_dest" "")
2206 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2207 (match_operand:SI 2 "t_reg_operand" "")))
2208 (clobber (reg:SI T_REG))]
2212 [(parallel [(set (match_dup 0)
2213 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2215 (clobber (reg:SI T_REG))])])
2217 (define_insn "*subsi3_internal"
2218 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2219 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2220 (match_operand:SI 2 "arith_reg_operand" "r")))]
2223 [(set_attr "type" "arith")])
2225 (define_insn_and_split "*subsi3_media"
2226 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2227 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2228 (match_operand:SI 2 "extend_reg_operand" "r")))]
2230 && (operands[1] != constm1_rtx
2231 || (GET_CODE (operands[2]) != TRUNCATE
2232 && GET_CODE (operands[2]) != SUBREG))"
2234 "operands[1] == constm1_rtx"
2235 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2237 [(set_attr "type" "arith_media")
2238 (set_attr "highpart" "ignore")])
2241 [(set (match_operand:SI 0 "arith_reg_dest" "")
2242 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2243 "general_extend_operand"
2245 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2246 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2247 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2251 [(set (match_operand:SI 0 "arith_reg_dest" "")
2252 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2253 "general_extend_operand"
2255 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
2256 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2257 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2265 ;; since this will sometimes save one instruction.
2266 ;; Otherwise we might get a sequence like
2270 ;; if the source and dest regs are the same.
2271 (define_expand "subsi3"
2272 [(set (match_operand:SI 0 "arith_reg_operand" "")
2273 (minus:SI (match_operand:SI 1 "arith_operand" "")
2274 (match_operand:SI 2 "arith_reg_operand" "")))]
2277 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2279 emit_insn (gen_negsi2 (operands[0], operands[2]));
2280 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2285 if (!can_create_pseudo_p ()
2286 && ! arith_reg_or_0_operand (operands[1], SImode))
2288 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2289 operands[1] = force_reg (SImode, operands[1]);
2293 ;; -------------------------------------------------------------------------
2294 ;; Division instructions
2295 ;; -------------------------------------------------------------------------
2297 ;; We take advantage of the library routines which don't clobber as many
2298 ;; registers as a normal function call would.
2300 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2301 ;; also has an effect on the register that holds the address of the sfunc.
2302 ;; To make this work, we have an extra dummy insn that shows the use
2303 ;; of this register for reorg.
2305 (define_insn "use_sfunc_addr"
2306 [(set (reg:SI PR_REG)
2307 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2308 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2310 [(set_attr "length" "0")])
2312 (define_insn "udivsi3_sh2a"
2313 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2314 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2315 (match_operand:SI 2 "arith_reg_operand" "z")))]
2318 [(set_attr "type" "arith")
2319 (set_attr "in_delay_slot" "no")])
2321 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2322 ;; hard register 0. If we used hard register 0, then the next instruction
2323 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2324 ;; gets allocated to a stack slot that needs its address reloaded, then
2325 ;; there is nothing to prevent reload from using r0 to reload the address.
2326 ;; This reload would clobber the value in r0 we are trying to store.
2327 ;; If we let reload allocate r0, then this problem can never happen.
2328 (define_insn "udivsi3_i1"
2329 [(set (match_operand:SI 0 "register_operand" "=z")
2330 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2331 (clobber (reg:SI T_REG))
2332 (clobber (reg:SI PR_REG))
2333 (clobber (reg:SI R1_REG))
2334 (clobber (reg:SI R4_REG))
2335 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2336 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2338 [(set_attr "type" "sfunc")
2339 (set_attr "needs_delay_slot" "yes")])
2341 ; Since shmedia-nofpu code could be linked against shcompact code, and
2342 ; the udivsi3 libcall has the same name, we must consider all registers
2343 ; clobbered that are in the union of the registers clobbered by the
2344 ; shmedia and the shcompact implementation. Note, if the shcompact
2345 ; implementation actually used shcompact code, we'd need to clobber
2346 ; also r23 and fr23.
2347 (define_insn "udivsi3_i1_media"
2348 [(set (match_operand:SI 0 "register_operand" "=z")
2349 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2350 (clobber (reg:SI T_MEDIA_REG))
2351 (clobber (reg:SI PR_MEDIA_REG))
2352 (clobber (reg:SI R20_REG))
2353 (clobber (reg:SI R21_REG))
2354 (clobber (reg:SI R22_REG))
2355 (clobber (reg:DI TR0_REG))
2356 (clobber (reg:DI TR1_REG))
2357 (clobber (reg:DI TR2_REG))
2358 (use (match_operand 1 "target_reg_operand" "b"))]
2359 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2361 [(set_attr "type" "sfunc")
2362 (set_attr "needs_delay_slot" "yes")])
2364 (define_expand "udivsi3_i4_media"
2366 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2368 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2369 (set (match_dup 5) (float:DF (match_dup 3)))
2370 (set (match_dup 6) (float:DF (match_dup 4)))
2371 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2372 (set (match_dup 8) (fix:DI (match_dup 7)))
2373 (set (match_operand:SI 0 "register_operand" "")
2374 (truncate:SI (match_dup 8)))]
2375 "TARGET_SHMEDIA_FPU"
2377 operands[3] = gen_reg_rtx (DImode);
2378 operands[4] = gen_reg_rtx (DImode);
2379 operands[5] = gen_reg_rtx (DFmode);
2380 operands[6] = gen_reg_rtx (DFmode);
2381 operands[7] = gen_reg_rtx (DFmode);
2382 operands[8] = gen_reg_rtx (DImode);
2385 (define_insn "udivsi3_i4"
2386 [(set (match_operand:SI 0 "register_operand" "=y")
2387 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2388 (clobber (reg:SI T_REG))
2389 (clobber (reg:SI PR_REG))
2390 (clobber (reg:DF DR0_REG))
2391 (clobber (reg:DF DR2_REG))
2392 (clobber (reg:DF DR4_REG))
2393 (clobber (reg:SI R0_REG))
2394 (clobber (reg:SI R1_REG))
2395 (clobber (reg:SI R4_REG))
2396 (clobber (reg:SI R5_REG))
2397 (use (reg:PSI FPSCR_REG))
2398 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2399 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2401 [(set_attr "type" "sfunc")
2402 (set_attr "fp_mode" "double")
2403 (set_attr "needs_delay_slot" "yes")])
2405 (define_insn "udivsi3_i4_single"
2406 [(set (match_operand:SI 0 "register_operand" "=y")
2407 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2408 (clobber (reg:SI T_REG))
2409 (clobber (reg:SI PR_REG))
2410 (clobber (reg:DF DR0_REG))
2411 (clobber (reg:DF DR2_REG))
2412 (clobber (reg:DF DR4_REG))
2413 (clobber (reg:SI R0_REG))
2414 (clobber (reg:SI R1_REG))
2415 (clobber (reg:SI R4_REG))
2416 (clobber (reg:SI R5_REG))
2417 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2418 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2419 && TARGET_FPU_SINGLE"
2421 [(set_attr "type" "sfunc")
2422 (set_attr "needs_delay_slot" "yes")])
2424 (define_insn "udivsi3_i4_int"
2425 [(set (match_operand:SI 0 "register_operand" "=z")
2426 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2427 (clobber (reg:SI T_REG))
2428 (clobber (reg:SI R1_REG))
2429 (clobber (reg:SI PR_REG))
2430 (clobber (reg:SI MACH_REG))
2431 (clobber (reg:SI MACL_REG))
2432 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2435 [(set_attr "type" "sfunc")
2436 (set_attr "needs_delay_slot" "yes")])
2439 (define_expand "udivsi3"
2440 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2441 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2442 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2443 (parallel [(set (match_operand:SI 0 "register_operand" "")
2444 (udiv:SI (reg:SI R4_REG)
2446 (clobber (reg:SI T_REG))
2447 (clobber (reg:SI PR_REG))
2448 (clobber (reg:SI R4_REG))
2449 (use (match_dup 3))])]
2454 operands[3] = gen_reg_rtx (Pmode);
2455 /* Emit the move of the address to a pseudo outside of the libcall. */
2456 if (TARGET_DIVIDE_CALL_TABLE)
2458 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2459 that causes problems when the divide code is supposed to come from a
2460 separate library. Division by zero is undefined, so dividing 1 can be
2461 implemented by comparing with the divisor. */
2462 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2464 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2465 emit_insn (gen_cstoresi4 (operands[0], test,
2466 operands[1], operands[2]));
2469 else if (operands[2] == const0_rtx)
2471 emit_move_insn (operands[0], operands[2]);
2474 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2475 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2477 else if (TARGET_DIVIDE_CALL_FP)
2479 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2480 if (TARGET_FPU_SINGLE)
2481 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2483 last = gen_udivsi3_i4 (operands[0], operands[3]);
2485 else if (TARGET_SHMEDIA_FPU)
2487 operands[1] = force_reg (SImode, operands[1]);
2488 operands[2] = force_reg (SImode, operands[2]);
2489 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2492 else if (TARGET_SH2A)
2494 operands[1] = force_reg (SImode, operands[1]);
2495 operands[2] = force_reg (SImode, operands[2]);
2496 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2499 else if (TARGET_SH5)
2501 function_symbol (operands[3],
2502 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2506 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2507 else if (TARGET_FPU_ANY)
2508 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2510 last = gen_udivsi3_i1 (operands[0], operands[3]);
2514 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2515 last = gen_udivsi3_i1 (operands[0], operands[3]);
2517 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2518 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2523 (define_insn "divsi3_sh2a"
2524 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2525 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2526 (match_operand:SI 2 "arith_reg_operand" "z")))]
2529 [(set_attr "type" "arith")
2530 (set_attr "in_delay_slot" "no")])
2532 (define_insn "divsi3_i1"
2533 [(set (match_operand:SI 0 "register_operand" "=z")
2534 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2535 (clobber (reg:SI T_REG))
2536 (clobber (reg:SI PR_REG))
2537 (clobber (reg:SI R1_REG))
2538 (clobber (reg:SI R2_REG))
2539 (clobber (reg:SI R3_REG))
2540 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2541 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2543 [(set_attr "type" "sfunc")
2544 (set_attr "needs_delay_slot" "yes")])
2546 (define_insn "divsi3_i1_media"
2547 [(set (match_operand:SI 0 "register_operand" "=z")
2548 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2549 (clobber (reg:SI T_MEDIA_REG))
2550 (clobber (reg:SI PR_MEDIA_REG))
2551 (clobber (reg:SI R1_REG))
2552 (clobber (reg:SI R20_REG))
2553 (clobber (reg:SI R21_REG))
2554 (clobber (reg:SI TR0_REG))
2555 (use (match_operand 1 "target_reg_operand" "b"))]
2556 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2558 [(set_attr "type" "sfunc")])
2560 (define_insn "divsi3_media_2"
2561 [(set (match_operand:SI 0 "register_operand" "=z")
2562 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2563 (clobber (reg:SI T_MEDIA_REG))
2564 (clobber (reg:SI PR_MEDIA_REG))
2565 (clobber (reg:SI R1_REG))
2566 (clobber (reg:SI R21_REG))
2567 (clobber (reg:SI TR0_REG))
2568 (use (reg:SI R20_REG))
2569 (use (match_operand 1 "target_reg_operand" "b"))]
2570 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2572 [(set_attr "type" "sfunc")])
2574 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2575 ;; hard reg clobbers and data dependencies that we need when we want
2576 ;; to rematerialize the division into a call.
2577 (define_insn_and_split "divsi_inv_call"
2578 [(set (match_operand:SI 0 "register_operand" "=r")
2579 (div:SI (match_operand:SI 1 "register_operand" "r")
2580 (match_operand:SI 2 "register_operand" "r")))
2581 (clobber (reg:SI R4_REG))
2582 (clobber (reg:SI R5_REG))
2583 (clobber (reg:SI T_MEDIA_REG))
2584 (clobber (reg:SI PR_MEDIA_REG))
2585 (clobber (reg:SI R1_REG))
2586 (clobber (reg:SI R21_REG))
2587 (clobber (reg:SI TR0_REG))
2588 (clobber (reg:SI R20_REG))
2589 (use (match_operand:SI 3 "register_operand" "r"))]
2592 "&& (reload_in_progress || reload_completed)"
2593 [(set (match_dup 0) (match_dup 3))]
2595 [(set_attr "highpart" "must_split")])
2597 ;; This is the combiner pattern for -mdiv=inv:call .
2598 (define_insn_and_split "*divsi_inv_call_combine"
2599 [(set (match_operand:SI 0 "register_operand" "=z")
2600 (div:SI (match_operand:SI 1 "register_operand" "r")
2601 (match_operand:SI 2 "register_operand" "r")))
2602 (clobber (reg:SI R4_REG))
2603 (clobber (reg:SI R5_REG))
2604 (clobber (reg:SI T_MEDIA_REG))
2605 (clobber (reg:SI PR_MEDIA_REG))
2606 (clobber (reg:SI R1_REG))
2607 (clobber (reg:SI R21_REG))
2608 (clobber (reg:SI TR0_REG))
2609 (clobber (reg:SI R20_REG))
2610 (use (unspec:SI [(match_dup 1)
2611 (match_operand:SI 3 "" "")
2612 (unspec:SI [(match_operand:SI 4 "" "")
2614 (match_operand:DI 5 "" "")]
2616 (match_operand:DI 6 "" "")
2619 UNSPEC_DIV_INV_M3))]
2622 "&& (reload_in_progress || reload_completed)"
2625 const char *name = sh_divsi3_libfunc;
2626 enum sh_function_kind kind = SFUNC_GOT;
2629 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2630 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2631 while (TARGET_DIVIDE_INV_CALL2)
2633 rtx x = operands[3];
2635 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2637 x = XVECEXP (x, 0, 0);
2638 name = "__sdivsi3_2";
2639 kind = SFUNC_STATIC;
2640 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2643 sym = function_symbol (NULL, name, kind);
2644 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2647 [(set_attr "highpart" "must_split")])
2649 (define_expand "divsi3_i4_media"
2650 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2651 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2652 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2653 (set (match_operand:SI 0 "register_operand" "=r")
2654 (fix:SI (match_dup 5)))]
2655 "TARGET_SHMEDIA_FPU"
2657 operands[3] = gen_reg_rtx (DFmode);
2658 operands[4] = gen_reg_rtx (DFmode);
2659 operands[5] = gen_reg_rtx (DFmode);
2662 (define_insn "divsi3_i4"
2663 [(set (match_operand:SI 0 "register_operand" "=y")
2664 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2665 (clobber (reg:SI PR_REG))
2666 (clobber (reg:DF DR0_REG))
2667 (clobber (reg:DF DR2_REG))
2668 (use (reg:PSI FPSCR_REG))
2669 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2670 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2672 [(set_attr "type" "sfunc")
2673 (set_attr "fp_mode" "double")
2674 (set_attr "needs_delay_slot" "yes")])
2676 (define_insn "divsi3_i4_single"
2677 [(set (match_operand:SI 0 "register_operand" "=y")
2678 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2679 (clobber (reg:SI PR_REG))
2680 (clobber (reg:DF DR0_REG))
2681 (clobber (reg:DF DR2_REG))
2682 (clobber (reg:SI R2_REG))
2683 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2684 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2685 && TARGET_FPU_SINGLE"
2687 [(set_attr "type" "sfunc")
2688 (set_attr "needs_delay_slot" "yes")])
2690 (define_insn "divsi3_i4_int"
2691 [(set (match_operand:SI 0 "register_operand" "=z")
2692 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2693 (clobber (reg:SI T_REG))
2694 (clobber (reg:SI PR_REG))
2695 (clobber (reg:SI R1_REG))
2696 (clobber (reg:SI MACH_REG))
2697 (clobber (reg:SI MACL_REG))
2698 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2701 [(set_attr "type" "sfunc")
2702 (set_attr "needs_delay_slot" "yes")])
2704 (define_expand "divsi3"
2705 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2706 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2707 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2708 (parallel [(set (match_operand:SI 0 "register_operand" "")
2709 (div:SI (reg:SI R4_REG)
2711 (clobber (reg:SI T_REG))
2712 (clobber (reg:SI PR_REG))
2713 (clobber (reg:SI R1_REG))
2714 (clobber (reg:SI R2_REG))
2715 (clobber (reg:SI R3_REG))
2716 (use (match_dup 3))])]
2721 operands[3] = gen_reg_rtx (Pmode);
2722 /* Emit the move of the address to a pseudo outside of the libcall. */
2723 if (TARGET_DIVIDE_CALL_TABLE)
2725 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2726 last = gen_divsi3_i4_int (operands[0], operands[3]);
2728 else if (TARGET_DIVIDE_CALL_FP)
2730 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2731 if (TARGET_FPU_SINGLE)
2732 last = gen_divsi3_i4_single (operands[0], operands[3]);
2734 last = gen_divsi3_i4 (operands[0], operands[3]);
2736 else if (TARGET_SH2A)
2738 operands[1] = force_reg (SImode, operands[1]);
2739 operands[2] = force_reg (SImode, operands[2]);
2740 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2743 else if (TARGET_DIVIDE_INV)
2745 rtx dividend = operands[1];
2746 rtx divisor = operands[2];
2748 rtx nsb_res = gen_reg_rtx (DImode);
2749 rtx norm64 = gen_reg_rtx (DImode);
2750 rtx tab_ix = gen_reg_rtx (DImode);
2751 rtx norm32 = gen_reg_rtx (SImode);
2752 rtx i92 = force_reg (DImode, GEN_INT (92));
2753 rtx scratch0a = gen_reg_rtx (DImode);
2754 rtx scratch0b = gen_reg_rtx (DImode);
2755 rtx inv0 = gen_reg_rtx (SImode);
2756 rtx scratch1a = gen_reg_rtx (DImode);
2757 rtx scratch1b = gen_reg_rtx (DImode);
2758 rtx shift = gen_reg_rtx (DImode);
2760 rtx inv1 = gen_reg_rtx (SImode);
2761 rtx scratch2a = gen_reg_rtx (DImode);
2762 rtx scratch2b = gen_reg_rtx (SImode);
2763 rtx inv2 = gen_reg_rtx (SImode);
2764 rtx scratch3a = gen_reg_rtx (DImode);
2765 rtx scratch3b = gen_reg_rtx (DImode);
2766 rtx scratch3c = gen_reg_rtx (DImode);
2767 rtx scratch3d = gen_reg_rtx (SImode);
2768 rtx scratch3e = gen_reg_rtx (DImode);
2769 rtx result = gen_reg_rtx (SImode);
2771 if (! arith_reg_or_0_operand (dividend, SImode))
2772 dividend = force_reg (SImode, dividend);
2773 if (! arith_reg_operand (divisor, SImode))
2774 divisor = force_reg (SImode, divisor);
2775 if (flag_pic && Pmode != DImode)
2777 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2778 tab_base = gen_datalabel_ref (tab_base);
2779 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2783 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2784 tab_base = gen_datalabel_ref (tab_base);
2785 tab_base = force_reg (DImode, tab_base);
2787 if (TARGET_DIVIDE_INV20U)
2788 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2790 i2p27 = GEN_INT (0);
2791 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2792 i43 = force_reg (DImode, GEN_INT (43));
2795 emit_insn (gen_nsbdi (nsb_res,
2796 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2797 emit_insn (gen_ashldi3_media (norm64,
2798 gen_rtx_SUBREG (DImode, divisor, 0),
2800 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2801 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2802 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2803 inv0, scratch0a, scratch0b,
2804 scratch1a, scratch1b));
2805 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2806 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2808 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2810 scratch3a, scratch3b, scratch3c,
2811 scratch2a, scratch2b, scratch3d, scratch3e));
2812 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2813 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2814 else if (TARGET_DIVIDE_INV_FP)
2815 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2816 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2817 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2818 gen_reg_rtx (DFmode)));
2820 emit_move_insn (operands[0], result);
2823 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2825 operands[1] = force_reg (SImode, operands[1]);
2826 operands[2] = force_reg (SImode, operands[2]);
2827 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2830 else if (TARGET_SH5)
2832 if (TARGET_DIVIDE_CALL2)
2834 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2835 tab_base = gen_datalabel_ref (tab_base);
2836 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2838 if (TARGET_FPU_ANY && TARGET_SH1)
2839 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2840 else if (TARGET_DIVIDE_CALL2)
2841 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
2843 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2846 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2847 (operands[0], operands[3]));
2848 else if (TARGET_FPU_ANY)
2849 last = gen_divsi3_i4_single (operands[0], operands[3]);
2851 last = gen_divsi3_i1 (operands[0], operands[3]);
2855 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2856 last = gen_divsi3_i1 (operands[0], operands[3]);
2858 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2859 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2864 ;; operands: scratch, tab_base, tab_ix
2865 ;; These are unspecs because we could generate an indexed addressing mode
2866 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2867 ;; confuse reload. See PR27117.
2868 (define_insn "divsi_inv_qitable"
2869 [(set (match_operand:DI 0 "register_operand" "=r")
2870 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2871 (match_operand:DI 2 "register_operand" "r")]
2872 UNSPEC_DIV_INV_TABLE)))]
2875 [(set_attr "type" "load_media")
2876 (set_attr "highpart" "user")])
2878 ;; operands: scratch, tab_base, tab_ix
2879 (define_insn "divsi_inv_hitable"
2880 [(set (match_operand:DI 0 "register_operand" "=r")
2881 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2882 (match_operand:DI 2 "register_operand" "r")]
2883 UNSPEC_DIV_INV_TABLE)))]
2886 [(set_attr "type" "load_media")
2887 (set_attr "highpart" "user")])
2889 ;; operands: inv0, tab_base, tab_ix, norm32
2890 ;; scratch equiv in sdivsi3_2: r19, r21
2891 (define_expand "divsi_inv_m0"
2892 [(set (match_operand:SI 0 "register_operand" "=r")
2893 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2894 (match_operand:DI 2 "register_operand" "r")
2895 (match_operand:SI 3 "register_operand" "r")]
2897 (clobber (match_operand:DI 4 "register_operand" "=r"))
2898 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2905 ldx.ub r20, r21, r19 // u0.8
2907 muls.l r25, r19, r19 // s2.38
2908 ldx.w r20, r21, r21 // s2.14
2909 shari r19, 24, r19 // truncate to s2.14
2910 sub r21, r19, r19 // some 11 bit inverse in s1.14
2913 rtx inv0 = operands[0];
2914 rtx tab_base = operands[1];
2915 rtx tab_ix = operands[2];
2916 rtx norm32 = operands[3];
2917 rtx scratch0 = operands[4];
2918 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2919 rtx scratch1 = operands[5];
2921 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2922 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2923 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2924 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2925 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2926 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2930 ;; operands: inv1, tab_base, tab_ix, norm32
2931 (define_insn_and_split "divsi_inv_m1"
2932 [(set (match_operand:SI 0 "register_operand" "=r")
2933 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2934 (match_operand:DI 2 "register_operand" "r")
2935 (match_operand:SI 3 "register_operand" "r")]
2937 (clobber (match_operand:SI 4 "register_operand" "=r"))
2938 (clobber (match_operand:DI 5 "register_operand" "=r"))
2939 (clobber (match_operand:DI 6 "register_operand" "=r"))
2940 (clobber (match_operand:DI 7 "register_operand" "=r"))
2941 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2944 "&& !can_create_pseudo_p ()"
2948 muls.l r19, r19, r18 // u0.28
2949 muls.l r25, r18, r18 // s2.58
2950 shlli r19, 45, r0 // multiply by two and convert to s2.58
2952 shari r18, 28, r18 // some 18 bit inverse in s1.30
2955 rtx inv1 = operands[0];
2956 rtx tab_base = operands[1];
2957 rtx tab_ix = operands[2];
2958 rtx norm32 = operands[3];
2959 rtx inv0 = operands[4];
2960 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2961 rtx scratch0a = operands[5];
2962 rtx scratch0b = operands[6];
2963 rtx scratch0 = operands[7];
2964 rtx scratch1 = operands[8];
2965 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2967 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2968 scratch0a, scratch0b));
2969 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2970 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2971 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2972 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2973 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2977 ;; operands: inv2, norm32, inv1, i92
2978 (define_insn_and_split "divsi_inv_m2"
2979 [(set (match_operand:SI 0 "register_operand" "=r")
2980 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2981 (match_operand:SI 2 "register_operand" "r")
2982 (match_operand:DI 3 "register_operand" "r")]
2984 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2987 "&& !can_create_pseudo_p ()"
2991 muls.l r18, r25, r0 // s2.60
2992 shari r0, 16, r0 // s-16.44
2994 muls.l r0, r18, r19 // s-16.74
2995 shari r19, 30, r19 // s-16.44
2997 rtx inv2 = operands[0];
2998 rtx norm32 = operands[1];
2999 rtx inv1 = operands[2];
3000 rtx i92 = operands[3];
3001 rtx scratch0 = operands[4];
3002 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3004 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
3005 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
3006 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
3007 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
3008 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
3012 (define_insn_and_split "divsi_inv_m3"
3013 [(set (match_operand:SI 0 "register_operand" "=r")
3014 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3015 (match_operand:SI 2 "register_operand" "r")
3016 (match_operand:SI 3 "register_operand" "r")
3017 (match_operand:DI 4 "register_operand" "r")
3018 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
3019 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
3021 (clobber (match_operand:DI 7 "register_operand" "=r"))
3022 (clobber (match_operand:DI 8 "register_operand" "=r"))
3023 (clobber (match_operand:DI 9 "register_operand" "=r"))
3024 (clobber (match_operand:DI 10 "register_operand" "=r"))
3025 (clobber (match_operand:SI 11 "register_operand" "=r"))
3026 (clobber (match_operand:SI 12 "register_operand" "=r"))
3027 (clobber (match_operand:DI 13 "register_operand" "=r"))]
3030 "&& !can_create_pseudo_p ()"
3034 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
3035 r0: scratch0 r19: scratch1 r21: scratch2
3037 muls.l r18, r4, r25 // s32.30
3038 muls.l r19, r4, r19 // s15.30
3040 shari r19, 14, r19 // s18.-14
3046 rtx result = operands[0];
3047 rtx dividend = operands[1];
3048 rtx inv1 = operands[2];
3049 rtx inv2 = operands[3];
3050 rtx shift = operands[4];
3051 rtx scratch0 = operands[7];
3052 rtx scratch1 = operands[8];
3053 rtx scratch2 = operands[9];
3055 if (satisfies_constraint_N (dividend))
3057 emit_move_insn (result, dividend);
3061 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
3062 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
3063 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
3064 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
3065 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
3066 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
3067 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
3071 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
3072 ;; inv1: tab_base, tab_ix, norm32
3073 ;; inv2: norm32, inv1, i92
3074 (define_insn_and_split "divsi_inv_m1_3"
3075 [(set (match_operand:SI 0 "register_operand" "=r")
3076 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3077 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
3078 (match_operand:DI 3 "register_operand" "r")
3079 (match_operand:SI 4 "register_operand" "r")]
3081 (unspec:SI [(match_dup 4)
3082 (unspec:SI [(match_dup 2)
3084 (match_dup 4)] UNSPEC_DIV_INV_M1)
3085 (match_operand:SI 5 "" "")]
3087 (match_operand:DI 6 "register_operand" "r")
3088 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
3089 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
3091 (clobber (match_operand:DI 9 "register_operand" "=r"))
3092 (clobber (match_operand:DI 10 "register_operand" "=r"))
3093 (clobber (match_operand:DI 11 "register_operand" "=r"))
3094 (clobber (match_operand:DI 12 "register_operand" "=r"))
3095 (clobber (match_operand:SI 13 "register_operand" "=r"))
3096 (clobber (match_operand:SI 14 "register_operand" "=r"))
3097 (clobber (match_operand:DI 15 "register_operand" "=r"))]
3099 && (TARGET_DIVIDE_INV_MINLAT
3100 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3102 "&& !can_create_pseudo_p ()"
3105 rtx result = operands[0];
3106 rtx dividend = operands[1];
3107 rtx tab_base = operands[2];
3108 rtx tab_ix = operands[3];
3109 rtx norm32 = operands[4];
3110 /* rtx i92 = operands[5]; */
3111 rtx shift = operands[6];
3112 rtx i2p27 = operands[7];
3113 rtx i43 = operands[8];
3114 rtx scratch0 = operands[9];
3115 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3116 rtx scratch1 = operands[10];
3117 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3118 rtx scratch2 = operands[11];
3119 rtx scratch3 = operands[12];
3120 rtx scratch4 = operands[13];
3121 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
3122 rtx scratch5 = operands[14];
3123 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
3124 rtx scratch6 = operands[15];
3126 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
3127 scratch0, scratch1));
3128 /* inv0 == scratch4 */
3129 if (! TARGET_DIVIDE_INV20U)
3131 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
3133 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3137 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3138 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3140 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3141 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3142 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3143 /* inv1 == scratch4 */
3145 if (TARGET_DIVIDE_INV_MINLAT)
3147 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3148 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3149 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3150 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3151 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3152 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3153 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3154 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3155 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3156 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3157 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3161 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3162 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3163 emit_insn (gen_nsbdi (scratch6,
3164 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3165 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3166 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3167 emit_insn (gen_divsi_inv20 (scratch2,
3168 norm32, scratch4, dividend,
3169 scratch6, scratch3, i43,
3170 /* scratch0 may be shared with i2p27. */
3171 scratch0, scratch1, scratch5,
3172 label, label, i2p27));
3174 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3175 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3179 (define_insn "divsi_inv20"
3180 [(set (match_operand:DI 0 "register_operand" "=&r")
3181 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3182 (match_operand:SI 2 "register_operand" "r")
3183 (match_operand:SI 3 "register_operand" "r")
3184 (match_operand:DI 4 "register_operand" "r")
3185 (match_operand:DI 5 "register_operand" "r")
3186 (match_operand:DI 6 "register_operand" "r")
3187 (match_operand:DI 12 "register_operand" "r")
3188 (match_operand 10 "target_operand" "b")
3189 (match_operand 11 "immediate_operand" "i")]
3191 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3192 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3193 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3195 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3197 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3198 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3199 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3200 %10 label (tr), %11 label (imm)
3202 muls.l inv1, norm32, scratch0 // s2.60
3203 muls.l inv1, dividend, result // s32.30
3204 xor i2p27, result_sign, round_scratch
3205 bge/u dividend_nsb, i43, tr.. (label)
3206 shari scratch0, 16, scratch0 // s-16.44
3207 muls.l sratch0_si, inv1, scratch0 // s-16.74
3208 sub result, round_scratch, result
3209 shari dividend, 14, scratch1 // s19.-14
3210 shari scratch0, 30, scratch0 // s-16.44
3211 muls.l scratch0, scratch1, round_scratch // s15.30
3213 sub result, round_scratch, result */
3215 const bool likely = TARGET_DIVIDE_INV20L;
3218 "muls.l %2, %3, %0" "\n"
3219 " xor %12, %5, %7" "\n"
3220 " bge/l %4, %6, %10" "\n"
3221 " muls.l %2, %1, %8" "\n"
3222 " shari %8, 16, %8" "\n"
3223 " muls.l %8, %2, %8" "\n"
3224 " shari %3, 14, %9" "\n"
3225 " shari %8, 30, %8" "\n"
3226 " muls.l %8, %9, %8" "\n"
3227 " sub %0, %8, %0" "\n"
3228 "%11: add %0, %7, %0";
3231 "muls.l %2, %1, %8" "\n"
3232 " muls.l %2, %3, %0" "\n"
3233 " xor %12, %5, %7" "\n"
3234 " bge/u %4, %6, %10" "\n"
3235 " shari %8, 16, %8" "\n"
3236 " muls.l %8, %2, %8" "\n"
3237 " sub %0, %7, %0" "\n"
3238 " shari %3, 14, %9" "\n"
3239 " shari %8, 30, %8" "\n"
3240 " muls.l %8, %9, %7" "\n"
3241 "%11: sub %0, %7, %0";
3244 (define_insn_and_split "divsi_inv_fp"
3245 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3246 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3247 (match_operand:SI 2 "register_operand" "rf")))
3248 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3249 (clobber (match_operand:SI 4 "register_operand" "=r"))
3250 (clobber (match_operand:SI 5 "register_operand" "=r"))
3251 (clobber (match_operand:DF 6 "register_operand" "=r"))
3252 (clobber (match_operand:DF 7 "register_operand" "=r"))
3253 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3254 "TARGET_SHMEDIA_FPU"
3256 "&& (reload_in_progress || reload_completed)"
3257 [(set (match_dup 0) (match_dup 3))]
3259 [(set_attr "highpart" "must_split")])
3261 ;; If a matching group of divide-by-inverse instructions is in the same
3262 ;; basic block after gcse & loop optimizations, we want to transform them
3263 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3264 (define_insn_and_split "*divsi_inv_fp_combine"
3265 [(set (match_operand:SI 0 "register_operand" "=f")
3266 (div:SI (match_operand:SI 1 "register_operand" "f")
3267 (match_operand:SI 2 "register_operand" "f")))
3268 (use (unspec:SI [(match_dup 1)
3269 (match_operand:SI 3 "" "")
3270 (unspec:SI [(match_operand:SI 4 "" "")
3272 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3273 (match_operand:DI 6 "" "")
3275 (const_int 0)] UNSPEC_DIV_INV_M3))
3276 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3277 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3278 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3279 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3280 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3281 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3284 [(set (match_dup 9) (float:DF (match_dup 1)))
3285 (set (match_dup 10) (float:DF (match_dup 2)))
3286 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3288 (fix:SI (match_dup 11)))
3289 (set (match_dup 0) (match_dup 8))]
3291 if (! fp_arith_reg_operand (operands[1], SImode))
3293 emit_move_insn (operands[7], operands[1]);
3294 operands[1] = operands[7];
3296 if (! fp_arith_reg_operand (operands[2], SImode))
3298 emit_move_insn (operands[8], operands[2]);
3299 operands[2] = operands[8];
3302 [(set_attr "highpart" "must_split")])
3304 ;; -------------------------------------------------------------------------
3305 ;; Multiplication instructions
3306 ;; -------------------------------------------------------------------------
3308 (define_insn "umulhisi3_i"
3309 [(set (reg:SI MACL_REG)
3310 (mult:SI (zero_extend:SI
3311 (match_operand:HI 0 "arith_reg_operand" "r"))
3313 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3316 [(set_attr "type" "smpy")])
3318 (define_insn "mulhisi3_i"
3319 [(set (reg:SI MACL_REG)
3320 (mult:SI (sign_extend:SI
3321 (match_operand:HI 0 "arith_reg_operand" "r"))
3323 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3326 [(set_attr "type" "smpy")])
3328 (define_expand "mulhisi3"
3329 [(set (reg:SI MACL_REG)
3330 (mult:SI (sign_extend:SI
3331 (match_operand:HI 1 "arith_reg_operand" ""))
3333 (match_operand:HI 2 "arith_reg_operand" ""))))
3334 (set (match_operand:SI 0 "arith_reg_operand" "")
3340 macl = gen_rtx_REG (SImode, MACL_REG);
3342 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3343 insn = get_insns ();
3345 /* expand_binop can't find a suitable code in umul_widen_optab to
3346 make a REG_EQUAL note from, so make one here.
3347 See also smulsi3_highpart.
3348 ??? Alternatively, we could put this at the calling site of expand_binop,
3349 i.e. expand_expr. */
3350 /* Use emit_libcall_block for loop invariant code motion and to make
3351 a REG_EQUAL note. */
3352 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3357 (define_expand "umulhisi3"
3358 [(set (reg:SI MACL_REG)
3359 (mult:SI (zero_extend:SI
3360 (match_operand:HI 1 "arith_reg_operand" ""))
3362 (match_operand:HI 2 "arith_reg_operand" ""))))
3363 (set (match_operand:SI 0 "arith_reg_operand" "")
3369 macl = gen_rtx_REG (SImode, MACL_REG);
3371 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3372 insn = get_insns ();
3374 /* expand_binop can't find a suitable code in umul_widen_optab to
3375 make a REG_EQUAL note from, so make one here.
3376 See also smulsi3_highpart.
3377 ??? Alternatively, we could put this at the calling site of expand_binop,
3378 i.e. expand_expr. */
3379 /* Use emit_libcall_block for loop invariant code motion and to make
3380 a REG_EQUAL note. */
3381 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3386 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3387 ;; a call to a routine which clobbers known registers.
3389 [(set (match_operand:SI 1 "register_operand" "=z")
3390 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3391 (clobber (reg:SI MACL_REG))
3392 (clobber (reg:SI T_REG))
3393 (clobber (reg:SI PR_REG))
3394 (clobber (reg:SI R3_REG))
3395 (clobber (reg:SI R2_REG))
3396 (clobber (reg:SI R1_REG))
3397 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3400 [(set_attr "type" "sfunc")
3401 (set_attr "needs_delay_slot" "yes")])
3403 (define_expand "mulsi3_call"
3404 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3405 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3406 (parallel[(set (match_operand:SI 0 "register_operand" "")
3407 (mult:SI (reg:SI R4_REG)
3409 (clobber (reg:SI MACL_REG))
3410 (clobber (reg:SI T_REG))
3411 (clobber (reg:SI PR_REG))
3412 (clobber (reg:SI R3_REG))
3413 (clobber (reg:SI R2_REG))
3414 (clobber (reg:SI R1_REG))
3415 (use (match_operand:SI 3 "register_operand" ""))])]
3419 (define_insn "mul_r"
3420 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3421 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3422 (match_operand:SI 2 "arith_reg_operand" "z")))]
3425 [(set_attr "type" "dmpy")])
3427 (define_insn "mul_l"
3428 [(set (reg:SI MACL_REG)
3429 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3430 (match_operand:SI 1 "arith_reg_operand" "r")))]
3433 [(set_attr "type" "dmpy")])
3435 (define_expand "mulsi3"
3436 [(set (reg:SI MACL_REG)
3437 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3438 (match_operand:SI 2 "arith_reg_operand" "")))
3439 (set (match_operand:SI 0 "arith_reg_operand" "")
3445 /* The address must be set outside the libcall,
3446 since it goes into a pseudo. */
3447 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3448 rtx addr = force_reg (SImode, sym);
3449 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3455 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3457 emit_insn (gen_mul_l (operands[1], operands[2]));
3458 /* consec_sets_giv can only recognize the first insn that sets a
3459 giv as the giv insn. So we must tag this also with a REG_EQUAL
3461 emit_insn (gen_movsi_i ((operands[0]), macl));
3466 (define_insn "mulsidi3_i"
3467 [(set (reg:SI MACH_REG)
3471 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3472 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3474 (set (reg:SI MACL_REG)
3475 (mult:SI (match_dup 0)
3479 [(set_attr "type" "dmpy")])
3481 (define_expand "mulsidi3"
3482 [(set (match_operand:DI 0 "arith_reg_dest" "")
3483 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3484 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3485 "TARGET_SH2 || TARGET_SHMEDIA"
3489 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3494 (define_insn "mulsidi3_media"
3495 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3496 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3497 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3500 [(set_attr "type" "dmpy_media")
3501 (set_attr "highpart" "ignore")])
3503 (define_insn_and_split "mulsidi3_compact"
3504 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3506 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3507 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3508 (clobber (reg:SI MACH_REG))
3509 (clobber (reg:SI MACL_REG))]
3515 rtx low_dst = gen_lowpart (SImode, operands[0]);
3516 rtx high_dst = gen_highpart (SImode, operands[0]);
3518 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3520 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3521 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3522 /* We need something to tag the possible REG_EQUAL notes on to. */
3523 emit_move_insn (operands[0], operands[0]);
3527 (define_insn "umulsidi3_i"
3528 [(set (reg:SI MACH_REG)
3532 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3533 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3535 (set (reg:SI MACL_REG)
3536 (mult:SI (match_dup 0)
3540 [(set_attr "type" "dmpy")])
3542 (define_expand "umulsidi3"
3543 [(set (match_operand:DI 0 "arith_reg_dest" "")
3544 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3545 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3546 "TARGET_SH2 || TARGET_SHMEDIA"
3550 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3555 (define_insn "umulsidi3_media"
3556 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3557 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3558 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3561 [(set_attr "type" "dmpy_media")
3562 (set_attr "highpart" "ignore")])
3564 (define_insn_and_split "umulsidi3_compact"
3565 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3567 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3568 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3569 (clobber (reg:SI MACH_REG))
3570 (clobber (reg:SI MACL_REG))]
3576 rtx low_dst = gen_lowpart (SImode, operands[0]);
3577 rtx high_dst = gen_highpart (SImode, operands[0]);
3579 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3581 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3582 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3583 /* We need something to tag the possible REG_EQUAL notes on to. */
3584 emit_move_insn (operands[0], operands[0]);
3588 (define_insn "smulsi3_highpart_i"
3589 [(set (reg:SI MACH_REG)
3593 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3594 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3596 (clobber (reg:SI MACL_REG))]
3599 [(set_attr "type" "dmpy")])
3601 (define_expand "smulsi3_highpart"
3603 [(set (reg:SI MACH_REG)
3607 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3608 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3610 (clobber (reg:SI MACL_REG))])
3611 (set (match_operand:SI 0 "arith_reg_operand" "")
3617 mach = gen_rtx_REG (SImode, MACH_REG);
3619 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3620 insn = get_insns ();
3622 /* expand_binop can't find a suitable code in mul_highpart_optab to
3623 make a REG_EQUAL note from, so make one here.
3624 See also {,u}mulhisi.
3625 ??? Alternatively, we could put this at the calling site of expand_binop,
3626 i.e. expand_mult_highpart. */
3627 /* Use emit_libcall_block for loop invariant code motion and to make
3628 a REG_EQUAL note. */
3629 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3634 (define_insn "umulsi3_highpart_i"
3635 [(set (reg:SI MACH_REG)
3639 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3640 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3642 (clobber (reg:SI MACL_REG))]
3645 [(set_attr "type" "dmpy")])
3647 (define_expand "umulsi3_highpart"
3649 [(set (reg:SI MACH_REG)
3653 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3654 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3656 (clobber (reg:SI MACL_REG))])
3657 (set (match_operand:SI 0 "arith_reg_operand" "")
3663 mach = gen_rtx_REG (SImode, MACH_REG);
3665 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3666 insn = get_insns ();
3668 /* Use emit_libcall_block for loop invariant code motion and to make
3669 a REG_EQUAL note. */
3670 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3675 (define_insn_and_split "muldi3"
3676 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3677 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3678 (match_operand:DI 2 "arith_reg_operand" "r")))
3679 (clobber (match_scratch:DI 3 "=&r"))
3680 (clobber (match_scratch:DI 4 "=r"))]
3686 rtx op3_v2si, op2_v2si;
3688 op3_v2si = operands[3];
3689 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3691 op3_v2si = XEXP (op3_v2si, 0);
3692 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3694 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3695 op2_v2si = operands[2];
3696 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3698 op2_v2si = XEXP (op2_v2si, 0);
3699 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3701 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3702 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3703 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3704 emit_insn (gen_umulsidi3_media (operands[4],
3705 sh_gen_truncate (SImode, operands[1], 0),
3706 sh_gen_truncate (SImode, operands[2], 0)));
3707 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3708 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3709 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3710 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3714 ;; -------------------------------------------------------------------------
3715 ;; Logical operations
3716 ;; -------------------------------------------------------------------------
3718 (define_expand "andsi3"
3719 [(set (match_operand:SI 0 "arith_reg_operand" "")
3720 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3721 (match_operand:SI 2 "logical_and_operand" "")))]
3724 /* If it is possible to turn the and insn into a zero extension
3725 already, redundant zero extensions will be folded, which results
3727 Ideally the splitter of *andsi_compact would be enough, if redundant
3728 zero extensions were detected after the combine pass, which does not
3729 happen at the moment. */
3732 if (satisfies_constraint_Jmb (operands[2]))
3734 emit_insn (gen_zero_extendqisi2 (operands[0],
3735 gen_lowpart (QImode, operands[1])));
3738 else if (satisfies_constraint_Jmw (operands[2]))
3740 emit_insn (gen_zero_extendhisi2 (operands[0],
3741 gen_lowpart (HImode, operands[1])));
3747 (define_insn_and_split "*andsi_compact"
3748 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3749 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3750 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3758 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3760 if (satisfies_constraint_Jmb (operands[2]))
3761 operands[1] = gen_lowpart (QImode, operands[1]);
3762 else if (satisfies_constraint_Jmw (operands[2]))
3763 operands[1] = gen_lowpart (HImode, operands[1]);
3767 [(set_attr "type" "arith")])
3769 (define_insn "*andsi3_media"
3770 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3771 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3772 (match_operand:SI 2 "logical_operand" "r,I10")))]
3777 [(set_attr "type" "arith_media")])
3779 (define_insn "*andsi3_bclr"
3780 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3781 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3782 (match_operand:SI 2 "const_int_operand" "Psz")))]
3783 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3785 [(set_attr "type" "arith")])
3787 (define_insn_and_split "anddi3"
3788 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3789 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3790 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3797 && ! logical_operand (operands[2], DImode)"
3800 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3801 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3803 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3806 [(set_attr "type" "arith_media")])
3808 (define_insn "andcsi3"
3809 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3810 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3811 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3814 [(set_attr "type" "arith_media")])
3816 (define_insn "andcdi3"
3817 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3818 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3819 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3822 [(set_attr "type" "arith_media")])
3824 (define_expand "iorsi3"
3825 [(set (match_operand:SI 0 "arith_reg_operand" "")
3826 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3827 (match_operand:SI 2 "logical_operand" "")))]
3831 (define_insn "*iorsi3_compact"
3832 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3833 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3834 (match_operand:SI 2 "logical_operand" "r,K08")))]
3836 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3838 [(set_attr "type" "arith")])
3840 (define_insn "*iorsi3_media"
3841 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3842 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3843 (match_operand:SI 2 "logical_operand" "r,I10")))]
3848 [(set_attr "type" "arith_media")])
3850 (define_insn "*iorsi3_bset"
3851 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3852 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3853 (match_operand:SI 2 "const_int_operand" "Pso")))]
3854 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3856 [(set_attr "type" "arith")])
3858 (define_insn "iordi3"
3859 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3860 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3861 (match_operand:DI 2 "logical_operand" "r,I10")))]
3866 [(set_attr "type" "arith_media")])
3868 (define_insn_and_split "*logical_sidi3"
3869 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3870 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3871 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3872 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3875 "&& reload_completed"
3876 [(set (match_dup 0) (match_dup 3))]
3879 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3880 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3881 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3884 (define_insn_and_split "*logical_sidisi3"
3885 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3886 (truncate:SI (sign_extend:DI
3887 (match_operator:SI 3 "logical_operator"
3888 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3889 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3893 [(set (match_dup 0) (match_dup 3))])
3895 (define_insn_and_split "*logical_sidi3_2"
3896 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3897 (sign_extend:DI (truncate:SI (sign_extend:DI
3898 (match_operator:SI 3 "logical_operator"
3899 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3900 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3904 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3906 (define_expand "xorsi3"
3907 [(set (match_operand:SI 0 "arith_reg_operand" "")
3908 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3909 (match_operand:SI 2 "xor_operand" "")))]
3913 (define_insn "*xorsi3_compact"
3914 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3915 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3916 (match_operand:SI 2 "logical_operand" "K08,r")))]
3919 [(set_attr "type" "arith")])
3921 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
3922 ;; of results where one of the inputs is a T bit store. Notice that this
3923 ;; pattern must not match during reload. If reload picks this pattern it
3924 ;; will be impossible to split it afterwards.
3925 (define_insn_and_split "*logical_op_t"
3926 [(set (match_operand:SI 0 "arith_reg_dest")
3927 (match_operator:SI 3 "logical_operator"
3928 [(match_operand:SI 1 "arith_reg_operand")
3929 (match_operand:SI 2 "t_reg_operand")]))]
3930 "TARGET_SH1 && can_create_pseudo_p ()"
3933 [(set (match_dup 4) (reg:SI T_REG))
3934 (set (match_dup 0) (match_dup 3))]
3936 operands[4] = gen_reg_rtx (SImode);
3937 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3938 operands[1], operands[4]);
3941 (define_insn "*xorsi3_media"
3942 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3943 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3944 (match_operand:SI 2 "xor_operand" "r,I06")))]
3949 [(set_attr "type" "arith_media")])
3951 (define_insn "xordi3"
3952 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3953 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3954 (match_operand:DI 2 "xor_operand" "r,I06")))]
3959 [(set_attr "type" "arith_media")])
3961 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3962 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3964 [(set (match_operand:DI 0 "arith_reg_dest" "")
3965 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3966 [(match_operand 1 "any_register_operand" "")
3967 (match_operand 2 "any_register_operand" "")])))]
3969 [(set (match_dup 5) (match_dup 4))
3970 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3972 enum machine_mode inmode = GET_MODE (operands[1]);
3975 if (GET_CODE (operands[0]) == SUBREG)
3977 offset = SUBREG_BYTE (operands[0]);
3978 operands[0] = SUBREG_REG (operands[0]);
3980 gcc_assert (REG_P (operands[0]));
3981 if (TARGET_BIG_ENDIAN)
3982 offset += 8 - GET_MODE_SIZE (inmode);
3983 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3986 ;; -------------------------------------------------------------------------
3987 ;; Shifts and rotates
3988 ;; -------------------------------------------------------------------------
3990 (define_expand "rotldi3"
3991 [(set (match_operand:DI 0 "arith_reg_dest" "")
3992 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
3993 (match_operand:HI 2 "mextr_bit_offset" "")))]
3996 if (! mextr_bit_offset (operands[2], HImode))
4000 (define_insn "rotldi3_mextr"
4001 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4002 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
4003 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4006 static char templ[16];
4007 sprintf (templ, "mextr%d %%1,%%1,%%0",
4008 8 - (int) (INTVAL (operands[2]) >> 3));
4011 [(set_attr "type" "arith_media")])
4013 (define_expand "rotrdi3"
4014 [(set (match_operand:DI 0 "arith_reg_dest" "")
4015 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
4016 (match_operand:HI 2 "mextr_bit_offset" "")))]
4019 if (! mextr_bit_offset (operands[2], HImode))
4023 (define_insn "rotrdi3_mextr"
4024 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4025 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
4026 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4029 static char templ[16];
4030 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
4033 [(set_attr "type" "arith_media")])
4036 [(set (match_operand:DI 0 "arith_reg_dest" "")
4037 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
4038 "ua_address_operand" "")))
4039 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
4041 (clobber (match_operand:DI 3 "register_operand" ""))]
4043 [(match_dup 4) (match_dup 5)]
4045 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
4046 (operands[3], operands[1]));
4047 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
4048 GEN_INT (56), GEN_INT (8));
4051 (define_expand "rotrsi3"
4052 [(set (match_operand:SI 0 "arith_reg_dest")
4053 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
4054 (match_operand:SI 2 "const_int_operand")))]
4057 HOST_WIDE_INT ival = INTVAL (operands[2]);
4060 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
4067 (define_insn "rotrsi3_1"
4068 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4069 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4072 (and:SI (match_dup 1) (const_int 1)))]
4075 [(set_attr "type" "arith")])
4077 ;; A slimplified version of rotr for combine.
4078 (define_insn "*rotrsi3_1"
4079 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4080 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4082 (clobber (reg:SI T_REG))]
4085 [(set_attr "type" "arith")])
4087 (define_insn "rotlsi3_1"
4088 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4089 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4092 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4095 [(set_attr "type" "arith")])
4097 ;; A simplified version of rotl for combine.
4098 (define_insn "*rotlsi3_1"
4099 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4100 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4102 (clobber (reg:SI T_REG))]
4105 [(set_attr "type" "arith")])
4107 (define_insn "rotlsi3_31"
4108 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4109 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4111 (clobber (reg:SI T_REG))]
4114 [(set_attr "type" "arith")])
4116 (define_insn "rotlsi3_16"
4117 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4118 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
4122 [(set_attr "type" "arith")])
4124 (define_expand "rotlsi3"
4125 [(set (match_operand:SI 0 "arith_reg_dest")
4126 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
4127 (match_operand:SI 2 "const_int_operand")))]
4130 static const char rot_tab[] = {
4131 000, 000, 000, 000, 000, 000, 010, 001,
4132 001, 001, 011, 013, 003, 003, 003, 003,
4133 003, 003, 003, 003, 003, 013, 012, 002,
4134 002, 002, 010, 000, 000, 000, 000, 000,
4137 int count = INTVAL (operands[2]);
4138 int choice = rot_tab[count];
4139 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4145 emit_move_insn (operands[0], operands[1]);
4146 count -= (count & 16) * 2;
4149 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4156 parts[0] = gen_reg_rtx (SImode);
4157 parts[1] = gen_reg_rtx (SImode);
4158 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4159 emit_move_insn (parts[choice-1], operands[1]);
4160 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4161 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4162 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4163 count = (count & ~16) - 8;
4167 for (; count > 0; count--)
4168 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4169 for (; count < 0; count++)
4170 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4175 (define_insn "rotlhi3_8"
4176 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4177 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4181 [(set_attr "type" "arith")])
4183 (define_expand "rotlhi3"
4184 [(set (match_operand:HI 0 "arith_reg_operand")
4185 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4186 (match_operand:HI 2 "const_int_operand")))]
4189 if (INTVAL (operands[2]) != 8)
4193 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4194 ;; They can also be used to implement things like
4196 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4197 ;; int x1 = (y << 1) | t; // rotcl
4198 (define_insn "rotcr"
4199 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4200 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4202 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4205 (and:SI (match_dup 1) (const_int 1)))]
4208 [(set_attr "type" "arith")])
4210 (define_insn "rotcl"
4211 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4212 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4214 (match_operand:SI 2 "t_reg_operand")))
4216 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4219 [(set_attr "type" "arith")])
4221 ;; Simplified rotcr version for combine, which allows arbitrary shift
4222 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4223 ;; directly. Otherwise we have to insert a shift in between.
4224 (define_insn_and_split "*rotcr"
4225 [(set (match_operand:SI 0 "arith_reg_dest")
4226 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4227 (match_operand:SI 2 "const_int_operand"))
4228 (ashift:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4230 (clobber (reg:SI T_REG))]
4233 "&& can_create_pseudo_p ()"
4236 if (INTVAL (operands[2]) > 1)
4238 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4239 rtx prev_set_t_insn = NULL_RTX;
4240 rtx tmp_t_reg = NULL_RTX;
4242 /* If we're going to emit a shift sequence that clobbers the T_REG,
4243 try to find the previous insn that sets the T_REG and emit the
4244 shift insn before that insn, to remove the T_REG dependency.
4245 If the insn that sets the T_REG cannot be found, store the T_REG
4246 in a temporary reg and restore it after the shift. */
4247 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4248 && ! sh_dynamicalize_shift_p (shift_count))
4250 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4252 /* Skip the nott insn, which was probably inserted by the splitter
4253 of *rotcr_neg_t. Don't use one of the recog functions
4254 here during insn splitting, since that causes problems in later
4256 if (prev_set_t_insn != NULL_RTX)
4258 rtx pat = PATTERN (prev_set_t_insn);
4259 if (GET_CODE (pat) == SET
4260 && t_reg_operand (XEXP (pat, 0), SImode)
4261 && negt_reg_operand (XEXP (pat, 1), SImode))
4262 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4265 if (! (prev_set_t_insn != NULL_RTX
4266 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4267 && ! reg_referenced_p (get_t_reg_rtx (),
4268 PATTERN (prev_set_t_insn))))
4270 prev_set_t_insn = NULL_RTX;
4271 tmp_t_reg = gen_reg_rtx (SImode);
4272 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4276 rtx shift_result = gen_reg_rtx (SImode);
4277 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4278 operands[1] = shift_result;
4280 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4281 if (prev_set_t_insn != NULL_RTX)
4282 emit_insn_before (shift_insn, prev_set_t_insn);
4284 emit_insn (shift_insn);
4286 /* Restore T_REG if it has been saved before. */
4287 if (tmp_t_reg != NULL_RTX)
4288 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4291 /* For the rotcr insn to work, operands[3] must be in T_REG.
4292 If it is not we can get it there by shifting it right one bit.
4293 In this case T_REG is not an input for this insn, thus we don't have to
4294 pay attention as of where to insert the shlr insn. */
4295 if (! t_reg_operand (operands[3], SImode))
4297 /* We don't care about the shifted result here, only the T_REG. */
4298 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4299 operands[3] = get_t_reg_rtx ();
4302 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4306 ;; If combine tries the same as above but with swapped operands, split
4307 ;; it so that it will try the pattern above.
4309 [(set (match_operand:SI 0 "arith_reg_dest")
4310 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4312 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4313 (match_operand:SI 3 "const_int_operand"))))]
4314 "TARGET_SH1 && can_create_pseudo_p ()"
4315 [(parallel [(set (match_dup 0)
4316 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4317 (ashift:SI (match_dup 1) (const_int 31))))
4318 (clobber (reg:SI T_REG))])])
4320 ;; Basically the same as the rotcr pattern above, but for rotcl.
4321 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4322 (define_insn_and_split "*rotcl"
4323 [(set (match_operand:SI 0 "arith_reg_dest")
4324 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4325 (match_operand:SI 2 "const_int_operand"))
4326 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4328 (clobber (reg:SI T_REG))]
4331 "&& can_create_pseudo_p ()"
4334 gcc_assert (INTVAL (operands[2]) > 0);
4336 if (INTVAL (operands[2]) > 1)
4338 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4339 rtx prev_set_t_insn = NULL_RTX;
4340 rtx tmp_t_reg = NULL_RTX;
4342 /* If we're going to emit a shift sequence that clobbers the T_REG,
4343 try to find the previous insn that sets the T_REG and emit the
4344 shift insn before that insn, to remove the T_REG dependency.
4345 If the insn that sets the T_REG cannot be found, store the T_REG
4346 in a temporary reg and restore it after the shift. */
4347 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4348 && ! sh_dynamicalize_shift_p (shift_count))
4350 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4352 /* Skip the nott insn, which was probably inserted by the splitter
4353 of *rotcl_neg_t. Don't use one of the recog functions
4354 here during insn splitting, since that causes problems in later
4356 if (prev_set_t_insn != NULL_RTX)
4358 rtx pat = PATTERN (prev_set_t_insn);
4359 if (GET_CODE (pat) == SET
4360 && t_reg_operand (XEXP (pat, 0), SImode)
4361 && negt_reg_operand (XEXP (pat, 1), SImode))
4362 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4365 if (! (prev_set_t_insn != NULL_RTX
4366 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4367 && ! reg_referenced_p (get_t_reg_rtx (),
4368 PATTERN (prev_set_t_insn))))
4370 prev_set_t_insn = NULL_RTX;
4371 tmp_t_reg = gen_reg_rtx (SImode);
4372 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4376 rtx shift_result = gen_reg_rtx (SImode);
4377 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4378 operands[1] = shift_result;
4380 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4381 if (prev_set_t_insn != NULL_RTX)
4382 emit_insn_before (shift_insn, prev_set_t_insn);
4384 emit_insn (shift_insn);
4386 /* Restore T_REG if it has been saved before. */
4387 if (tmp_t_reg != NULL_RTX)
4388 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4391 /* For the rotcl insn to work, operands[3] must be in T_REG.
4392 If it is not we can get it there by shifting it right one bit.
4393 In this case T_REG is not an input for this insn, thus we don't have to
4394 pay attention as of where to insert the shlr insn. */
4395 if (! t_reg_operand (operands[3], SImode))
4397 /* We don't care about the shifted result here, only the T_REG. */
4398 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4399 operands[3] = get_t_reg_rtx ();
4402 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4406 ;; rotcl combine pattern variations
4407 (define_insn_and_split "*rotcl"
4408 [(set (match_operand:SI 0 "arith_reg_dest")
4409 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4410 (match_operand:SI 2 "const_int_operand"))
4411 (match_operand:SI 3 "t_reg_operand")))
4412 (clobber (reg:SI T_REG))]
4415 "&& can_create_pseudo_p ()"
4416 [(parallel [(set (match_dup 0)
4417 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4418 (and:SI (match_dup 3) (const_int 1))))
4419 (clobber (reg:SI T_REG))])])
4421 (define_insn_and_split "*rotcl"
4422 [(set (match_operand:SI 0 "arith_reg_dest")
4423 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4425 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4426 (match_operand:SI 3 "const_int_operand"))))
4427 (clobber (reg:SI T_REG))]
4430 "&& can_create_pseudo_p ()"
4431 [(parallel [(set (match_dup 0)
4432 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4433 (and:SI (match_dup 1) (const_int 1))))
4434 (clobber (reg:SI T_REG))])])
4436 (define_insn_and_split "*rotcl"
4437 [(set (match_operand:SI 0 "arith_reg_dest")
4438 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4439 (match_operand:SI 2 "const_int_operand"))
4440 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4442 (clobber (reg:SI T_REG))]
4445 "&& can_create_pseudo_p ()"
4446 [(parallel [(set (match_dup 0)
4447 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4448 (and:SI (reg:SI T_REG) (const_int 1))))
4449 (clobber (reg:SI T_REG))])]
4451 /* We don't care about the result of the left shift, only the T_REG. */
4452 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4455 (define_insn_and_split "*rotcl"
4456 [(set (match_operand:SI 0 "arith_reg_dest")
4457 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4459 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4460 (match_operand:SI 2 "const_int_operand"))))
4461 (clobber (reg:SI T_REG))]
4464 "&& can_create_pseudo_p ()"
4465 [(parallel [(set (match_dup 0)
4466 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4467 (and:SI (reg:SI T_REG) (const_int 1))))
4468 (clobber (reg:SI T_REG))])]
4470 /* We don't care about the result of the left shift, only the T_REG. */
4471 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4474 ;; rotcr combine bridge pattern which will make combine try out more
4475 ;; complex patterns.
4476 (define_insn_and_split "*rotcr"
4477 [(set (match_operand:SI 0 "arith_reg_dest")
4478 (ashift:SI (match_operand:SI 1 "t_reg_operand") (const_int 31)))]
4482 [(set (match_dup 0) (match_dup 1))
4483 (parallel [(set (match_dup 0)
4484 (ior:SI (lshiftrt:SI (match_dup 0) (const_int 1))
4485 (ashift:SI (match_dup 1) (const_int 31))))
4487 (and:SI (match_dup 0) (const_int 1)))])])
4489 (define_insn_and_split "*rotcr"
4490 [(set (match_operand:SI 0 "arith_reg_dest")
4491 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4492 (const_int -2147483648)) ;; 0xffffffff80000000
4493 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4495 (clobber (reg:SI T_REG))]
4498 "&& can_create_pseudo_p ()"
4501 rtx tmp = gen_reg_rtx (SImode);
4502 emit_insn (gen_shll (tmp, operands[1]));
4503 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4507 ;; rotcr combine patterns for rotating in the negated T_REG value.
4508 (define_insn_and_split "*rotcr_neg_t"
4509 [(set (match_operand:SI 0 "arith_reg_dest")
4510 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4511 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4512 (match_operand:SI 3 "const_int_operand"))))
4513 (clobber (reg:SI T_REG))]
4516 "&& can_create_pseudo_p ()"
4517 [(parallel [(set (match_dup 0)
4518 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4519 (ashift:SI (reg:SI T_REG) (const_int 31))))
4520 (clobber (reg:SI T_REG))])]
4522 emit_insn (gen_nott (get_t_reg_rtx ()));
4525 (define_insn_and_split "*rotcr_neg_t"
4526 [(set (match_operand:SI 0 "arith_reg_dest")
4527 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4528 (match_operand:SI 2 "const_int_operand"))
4529 (match_operand:SI 3 "negt_reg_shl31_operand")))
4530 (clobber (reg:SI T_REG))]
4533 "&& can_create_pseudo_p ()"
4534 [(parallel [(set (match_dup 0)
4535 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4536 (ashift:SI (reg:SI T_REG) (const_int 31))))
4537 (clobber (reg:SI T_REG))])]
4539 emit_insn (gen_nott (get_t_reg_rtx ()));
4542 ;; rotcl combine patterns for rotating in the negated T_REG value.
4543 ;; For some strange reason these have to be specified as splits which combine
4544 ;; will pick up. If they are specified as insn_and_split like the
4545 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4546 ;; but not emit them on non-SH2A targets.
4548 [(set (match_operand:SI 0 "arith_reg_dest")
4549 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4550 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4551 (match_operand:SI 3 "const_int_operand"))))]
4553 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4554 (parallel [(set (match_dup 0)
4555 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4556 (and:SI (reg:SI T_REG) (const_int 1))))
4557 (clobber (reg:SI T_REG))])])
4560 [(set (match_operand:SI 0 "arith_reg_dest")
4561 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4562 (match_operand:SI 3 "const_int_operand"))
4563 (match_operand:SI 1 "negt_reg_operand")))]
4565 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4566 (parallel [(set (match_dup 0)
4567 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4568 (and:SI (reg:SI T_REG) (const_int 1))))
4569 (clobber (reg:SI T_REG))])])
4571 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4572 ;; SImode shift left
4574 (define_expand "ashlsi3"
4575 [(set (match_operand:SI 0 "arith_reg_operand" "")
4576 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4577 (match_operand:SI 2 "shift_count_operand" "")))]
4582 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4586 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4587 operands[2] = force_reg (SImode, operands[2]);
4589 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4591 if (CONST_INT_P (operands[2])
4592 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4593 && ! sh_dynamicalize_shift_p (operands[2]))
4595 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4600 /* Expand a library call for the dynamic shift. */
4601 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4603 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4604 rtx funcaddr = gen_reg_rtx (Pmode);
4605 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4606 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4612 (define_insn "ashlsi3_k"
4613 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4614 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4615 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4620 [(set_attr "type" "arith")])
4622 (define_insn_and_split "ashlsi3_d"
4623 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4624 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4625 (match_operand:SI 2 "shift_count_operand" "r")))]
4628 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4629 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4632 if (satisfies_constraint_P27 (operands[2]))
4634 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4637 else if (! satisfies_constraint_P27 (operands[2]))
4639 /* This must happen before reload, otherwise the constant will be moved
4640 into a register due to the "r" constraint, after which this split
4641 cannot be done anymore.
4642 Unfortunately the move insn will not always be eliminated.
4643 Also, here we must not create a shift sequence that clobbers the
4645 emit_move_insn (operands[0], operands[1]);
4646 gen_shifty_op (ASHIFT, operands);
4652 [(set_attr "type" "dyn_shift")])
4654 ;; If dynamic shifts are not available use a library function.
4655 ;; By specifying the pattern we reduce the number of call clobbered regs.
4656 ;; In order to make combine understand the truncation of the shift amount
4657 ;; operand we have to allow it to use pseudo regs for the shift operands.
4658 (define_insn "ashlsi3_d_call"
4659 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4660 (ashift:SI (reg:SI R4_REG)
4661 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4663 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4664 (clobber (reg:SI T_REG))
4665 (clobber (reg:SI PR_REG))]
4666 "TARGET_SH1 && !TARGET_DYNSHIFT"
4668 [(set_attr "type" "sfunc")
4669 (set_attr "needs_delay_slot" "yes")])
4671 (define_insn_and_split "ashlsi3_n"
4672 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4673 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4674 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4675 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4677 "&& (reload_completed
4678 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4681 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4683 /* If this pattern was picked and dynamic shifts are supported, switch
4684 to dynamic shift pattern before reload. */
4685 operands[2] = force_reg (SImode, operands[2]);
4686 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4689 gen_shifty_op (ASHIFT, operands);
4694 (define_insn_and_split "ashlsi3_n_clobbers_t"
4695 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4696 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4697 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
4698 (clobber (reg:SI T_REG))]
4699 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
4701 "&& (reload_completed || INTVAL (operands[2]) == 31
4702 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4705 if (INTVAL (operands[2]) == 31)
4707 /* If the shift amount is 31 we split into a different sequence before
4708 reload so that it gets a chance to allocate R0 for the sequence.
4709 If it fails to do so (due to pressure on R0), it will take one insn
4710 more for the and. */
4711 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
4712 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4714 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4716 /* If this pattern was picked and dynamic shifts are supported, switch
4717 to dynamic shift pattern before reload. */
4718 operands[2] = force_reg (SImode, operands[2]);
4719 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4722 gen_shifty_op (ASHIFT, operands);
4728 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4729 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
4731 (lt:SI (match_dup 1) (const_int 0)))]
4734 [(set_attr "type" "arith")])
4736 (define_insn "*ashlsi_c_void"
4737 [(set (reg:SI T_REG)
4738 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
4739 (clobber (match_scratch:SI 1 "=0"))]
4740 "TARGET_SH1 && cse_not_expected"
4742 [(set_attr "type" "arith")])
4745 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
4747 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
4749 && peep2_reg_dead_p (2, operands[0])
4750 && peep2_reg_dead_p (2, operands[1])"
4753 emit_insn (gen_shll (operands[1], operands[1]));
4757 (define_insn "ashlsi3_media"
4758 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4759 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4760 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4765 [(set_attr "type" "arith_media")
4766 (set_attr "highpart" "ignore")])
4768 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4769 ;; HImode shift left
4771 (define_expand "ashlhi3"
4772 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
4773 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
4774 (match_operand:SI 2 "nonmemory_operand" "")))
4775 (clobber (reg:SI T_REG))])]
4778 if (!CONST_INT_P (operands[2]))
4780 /* It may be possible to call gen_ashlhi3 directly with more generic
4781 operands. Make sure operands[1] is a HImode register here. */
4782 if (!arith_reg_operand (operands[1], HImode))
4783 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4786 (define_insn "ashlhi3_k"
4787 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
4788 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
4789 (match_operand:HI 2 "const_int_operand" "M,P27")))]
4790 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
4794 [(set_attr "type" "arith")])
4796 (define_insn_and_split "*ashlhi3_n"
4797 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4798 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
4799 (match_operand:HI 2 "const_int_operand" "n")))
4800 (clobber (reg:SI T_REG))]
4803 "&& reload_completed"
4804 [(use (reg:SI R0_REG))]
4806 gen_shifty_hi_op (ASHIFT, operands);
4810 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4811 ;; DImode shift left
4813 (define_expand "ashldi3"
4814 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4815 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4816 (match_operand:DI 2 "immediate_operand" "")))
4817 (clobber (reg:SI T_REG))])]
4822 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4825 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
4827 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4830 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
4832 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4839 ;; Expander for DImode shift left with SImode operations.
4840 (define_expand "ashldi3_std"
4841 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4842 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4843 (match_operand:DI 2 "const_int_operand" "n")))]
4844 "TARGET_SH1 && INTVAL (operands[2]) < 32"
4846 rtx low_src = gen_lowpart (SImode, operands[1]);
4847 rtx high_src = gen_highpart (SImode, operands[1]);
4848 rtx dst = gen_reg_rtx (DImode);
4849 rtx low_dst = gen_lowpart (SImode, dst);
4850 rtx high_dst = gen_highpart (SImode, dst);
4851 rtx tmp0 = gen_reg_rtx (SImode);
4852 rtx tmp1 = gen_reg_rtx (SImode);
4854 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
4855 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
4856 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
4857 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
4858 emit_move_insn (operands[0], dst);
4862 (define_insn_and_split "ashldi3_k"
4863 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4864 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
4866 (clobber (reg:SI T_REG))]
4869 "&& reload_completed"
4872 rtx high = gen_highpart (SImode, operands[0]);
4873 rtx low = gen_lowpart (SImode, operands[0]);
4874 emit_insn (gen_shll (low, low));
4875 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
4879 (define_insn "ashldi3_media"
4880 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4881 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4882 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4887 [(set_attr "type" "arith_media")])
4889 (define_insn "*ashldisi3_media"
4890 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4891 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4892 (match_operand:DI 2 "const_int_operand" "n")))]
4893 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4894 "shlli.l %1, %2, %0"
4895 [(set_attr "type" "arith_media")
4896 (set_attr "highpart" "ignore")])
4898 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4899 ;; SImode arithmetic shift right
4901 ;; We can't do HImode right shifts correctly unless we start out with an
4902 ;; explicit zero / sign extension; doing that would result in worse overall
4903 ;; code, so just let the machine independent code widen the mode.
4904 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
4906 (define_expand "ashrsi3"
4907 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4908 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4909 (match_operand:SI 2 "nonmemory_operand" "")))
4910 (clobber (reg:SI T_REG))])]
4915 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4918 if (expand_ashiftrt (operands))
4925 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4926 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4929 (and:SI (match_dup 1) (const_int 1)))]
4932 [(set_attr "type" "arith")])
4934 (define_insn "ashrsi3_k"
4935 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4936 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4937 (match_operand:SI 2 "const_int_operand" "M")))
4938 (clobber (reg:SI T_REG))]
4939 "TARGET_SH1 && INTVAL (operands[2]) == 1"
4941 [(set_attr "type" "arith")])
4943 (define_insn_and_split "ashrsi2_16"
4944 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4945 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
4950 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
4951 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
4953 operands[2] = gen_lowpart (HImode, operands[0]);
4956 (define_insn_and_split "ashrsi2_31"
4957 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4958 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4960 (clobber (reg:SI T_REG))]
4966 emit_insn (gen_shll (operands[0], operands[1]));
4967 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
4971 (define_insn "ashrsi3_d"
4972 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4973 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4974 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4977 [(set_attr "type" "dyn_shift")])
4979 (define_insn "ashrsi3_n"
4980 [(set (reg:SI R4_REG)
4981 (ashiftrt:SI (reg:SI R4_REG)
4982 (match_operand:SI 0 "const_int_operand" "i")))
4983 (clobber (reg:SI T_REG))
4984 (clobber (reg:SI PR_REG))
4985 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
4988 [(set_attr "type" "sfunc")
4989 (set_attr "needs_delay_slot" "yes")])
4991 (define_insn "ashrsi3_media"
4992 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4993 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4994 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4999 [(set_attr "type" "arith_media")
5000 (set_attr "highpart" "ignore")])
5002 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5003 ;; DImode arithmetic shift right
5005 (define_expand "ashrdi3"
5006 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5007 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5008 (match_operand:DI 2 "immediate_operand" "")))
5009 (clobber (reg:SI T_REG))])]
5014 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5017 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5021 (define_insn_and_split "ashrdi3_k"
5022 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5023 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5025 (clobber (reg:SI T_REG))]
5028 "&& reload_completed"
5031 rtx high = gen_highpart (SImode, operands[0]);
5032 rtx low = gen_lowpart (SImode, operands[0]);
5033 emit_insn (gen_shar (high, high));
5034 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5038 (define_insn "ashrdi3_media"
5039 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5040 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5041 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5043 && (arith_reg_dest (operands[0], DImode)
5044 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
5048 [(set_attr "type" "arith_media")])
5050 (define_insn "*ashrdisi3_media"
5051 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5052 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5053 (match_operand:DI 2 "const_int_operand" "n")))]
5054 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5055 "shari.l %1, %2, %0"
5056 [(set_attr "type" "arith_media")
5057 (set_attr "highpart" "ignore")])
5059 (define_insn "ashrdisi3_media_high"
5060 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5062 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5063 (match_operand:DI 2 "const_int_operand" "n"))))]
5064 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
5066 [(set_attr "type" "arith_media")])
5068 (define_insn "ashrdisi3_media_opaque"
5069 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5070 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
5071 (match_operand:DI 2 "const_int_operand" "n")]
5075 [(set_attr "type" "arith_media")])
5077 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5078 ;; SImode logical shift right
5080 (define_expand "lshrsi3"
5081 [(set (match_operand:SI 0 "arith_reg_dest" "")
5082 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5083 (match_operand:SI 2 "shift_count_operand" "")))]
5088 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
5092 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
5093 here, otherwise the pattern will never match due to the shift amount reg
5096 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
5098 rtx neg_count = force_reg (SImode,
5099 gen_int_mode (- INTVAL (operands[2]), SImode));
5100 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5104 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
5106 rtx neg_count = gen_reg_rtx (SImode);
5107 emit_insn (gen_negsi2 (neg_count, operands[2]));
5108 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5112 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
5114 if (CONST_INT_P (operands[2])
5115 && sh_lshrsi_clobbers_t_reg_p (operands[2])
5116 && ! sh_dynamicalize_shift_p (operands[2]))
5118 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
5123 /* Expand a library call for the dynamic shift. */
5124 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
5126 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
5127 rtx funcaddr = gen_reg_rtx (Pmode);
5128 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
5129 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
5134 (define_insn "lshrsi3_k"
5135 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5136 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5137 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5140 [(set_attr "type" "arith")])
5142 (define_insn_and_split "lshrsi3_d"
5143 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5144 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5145 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5148 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5149 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5152 if (satisfies_constraint_P27 (operands[2]))
5154 /* This will not be done for a shift amount of 1, because it would
5155 clobber the T_REG. */
5156 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5159 else if (! satisfies_constraint_P27 (operands[2]))
5161 /* This must happen before reload, otherwise the constant will be moved
5162 into a register due to the "r" constraint, after which this split
5163 cannot be done anymore.
5164 Unfortunately the move insn will not always be eliminated.
5165 Also, here we must not create a shift sequence that clobbers the
5167 emit_move_insn (operands[0], operands[1]);
5168 gen_shifty_op (LSHIFTRT, operands);
5174 [(set_attr "type" "dyn_shift")])
5176 ;; If dynamic shifts are not available use a library function.
5177 ;; By specifying the pattern we reduce the number of call clobbered regs.
5178 ;; In order to make combine understand the truncation of the shift amount
5179 ;; operand we have to allow it to use pseudo regs for the shift operands.
5180 (define_insn "lshrsi3_d_call"
5181 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5182 (lshiftrt:SI (reg:SI R4_REG)
5183 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5185 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5186 (clobber (reg:SI T_REG))
5187 (clobber (reg:SI PR_REG))]
5188 "TARGET_SH1 && !TARGET_DYNSHIFT"
5190 [(set_attr "type" "sfunc")
5191 (set_attr "needs_delay_slot" "yes")])
5193 (define_insn_and_split "lshrsi3_n"
5194 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5195 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5196 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5197 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5199 "&& (reload_completed
5200 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5203 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5205 /* If this pattern was picked and dynamic shifts are supported, switch
5206 to dynamic shift pattern before reload. */
5207 operands[2] = force_reg (SImode,
5208 gen_int_mode (- INTVAL (operands[2]), SImode));
5209 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5212 gen_shifty_op (LSHIFTRT, operands);
5217 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5218 ;; the shlr pattern.
5219 (define_insn_and_split "lshrsi3_n_clobbers_t"
5220 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5221 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5222 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5223 (clobber (reg:SI T_REG))]
5224 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5226 "&& (reload_completed || INTVAL (operands[2]) == 31
5227 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5230 if (INTVAL (operands[2]) == 31)
5232 emit_insn (gen_shll (operands[0], operands[1]));
5233 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5235 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5237 /* If this pattern was picked and dynamic shifts are supported, switch
5238 to dynamic shift pattern before reload. */
5239 operands[2] = force_reg (SImode,
5240 gen_int_mode (- INTVAL (operands[2]), SImode));
5241 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5244 gen_shifty_op (LSHIFTRT, operands);
5250 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5251 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5254 (and:SI (match_dup 1) (const_int 1)))]
5257 [(set_attr "type" "arith")])
5259 (define_insn "lshrsi3_media"
5260 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5261 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5262 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5267 [(set_attr "type" "arith_media")
5268 (set_attr "highpart" "ignore")])
5270 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5271 ;; DImode logical shift right
5273 (define_expand "lshrdi3"
5274 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5275 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5276 (match_operand:DI 2 "immediate_operand" "")))
5277 (clobber (reg:SI T_REG))])]
5282 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5285 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5289 (define_insn_and_split "lshrdi3_k"
5290 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5291 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5293 (clobber (reg:SI T_REG))]
5296 "&& reload_completed"
5299 rtx high = gen_highpart (SImode, operands[0]);
5300 rtx low = gen_lowpart (SImode, operands[0]);
5301 emit_insn (gen_shlr (high, high));
5302 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5306 (define_insn "lshrdi3_media"
5307 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5308 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5309 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5311 && (arith_reg_dest (operands[0], DImode)
5312 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5316 [(set_attr "type" "arith_media")])
5318 (define_insn "*lshrdisi3_media"
5319 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5320 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5321 (match_operand:DI 2 "const_int_operand" "n")))]
5322 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5323 "shlri.l %1, %2, %0"
5324 [(set_attr "type" "arith_media")
5325 (set_attr "highpart" "ignore")])
5327 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5328 ;; Combined left/right shifts
5331 [(set (match_operand:SI 0 "register_operand" "")
5332 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5333 (match_operand:SI 2 "const_int_operand" ""))
5334 (match_operand:SI 3 "const_int_operand" "")))]
5335 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5336 [(use (reg:SI R0_REG))]
5338 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5344 [(set (match_operand:SI 0 "register_operand" "")
5345 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5346 (match_operand:SI 2 "const_int_operand" ""))
5347 (match_operand:SI 3 "const_int_operand" "")))
5348 (clobber (reg:SI T_REG))]
5349 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5350 [(use (reg:SI R0_REG))]
5352 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5358 [(set (match_operand:SI 0 "register_operand" "=r")
5359 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5360 (match_operand:SI 2 "const_int_operand" "n"))
5361 (match_operand:SI 3 "const_int_operand" "n")))
5362 (clobber (reg:SI T_REG))]
5363 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5365 [(set (attr "length")
5366 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5368 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5370 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5372 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5374 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5376 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5378 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5379 (const_string "16")]
5380 (const_string "18")))
5381 (set_attr "type" "arith")])
5384 [(set (match_operand:SI 0 "register_operand" "=z")
5385 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5386 (match_operand:SI 2 "const_int_operand" "n"))
5387 (match_operand:SI 3 "const_int_operand" "n")))
5388 (clobber (reg:SI T_REG))]
5389 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5391 [(set (attr "length")
5392 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5394 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5396 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5398 (const_string "10")))
5399 (set_attr "type" "arith")])
5401 ;; shift left / and combination with a scratch register: The combine pass
5402 ;; does not accept the individual instructions, even though they are
5403 ;; cheap. But it needs a precise description so that it is usable after
5405 (define_insn "and_shl_scratch"
5406 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5410 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5411 (match_operand:SI 2 "const_int_operand" "N,n"))
5412 (match_operand:SI 3 "" "0,r"))
5413 (match_operand:SI 4 "const_int_operand" "n,n"))
5414 (match_operand:SI 5 "const_int_operand" "n,n")))
5415 (clobber (reg:SI T_REG))]
5418 [(set (attr "length")
5419 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5421 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5423 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5425 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5426 (const_string "10")]
5427 (const_string "12")))
5428 (set_attr "type" "arith")])
5431 [(set (match_operand:SI 0 "register_operand" "")
5435 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5436 (match_operand:SI 2 "const_int_operand" ""))
5437 (match_operand:SI 3 "register_operand" ""))
5438 (match_operand:SI 4 "const_int_operand" ""))
5439 (match_operand:SI 5 "const_int_operand" "")))
5440 (clobber (reg:SI T_REG))]
5442 [(use (reg:SI R0_REG))]
5444 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5446 if (INTVAL (operands[2]))
5448 gen_shifty_op (LSHIFTRT, operands);
5450 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5451 operands[2] = operands[4];
5452 gen_shifty_op (ASHIFT, operands);
5453 if (INTVAL (operands[5]))
5455 operands[2] = operands[5];
5456 gen_shifty_op (LSHIFTRT, operands);
5461 ;; signed left/right shift combination.
5463 [(set (match_operand:SI 0 "register_operand" "")
5465 (ashift:SI (match_operand:SI 1 "register_operand" "")
5466 (match_operand:SI 2 "const_int_operand" ""))
5467 (match_operand:SI 3 "const_int_operand" "")
5469 (clobber (reg:SI T_REG))]
5471 [(use (reg:SI R0_REG))]
5473 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5478 (define_insn "shl_sext_ext"
5479 [(set (match_operand:SI 0 "register_operand" "=r")
5481 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5482 (match_operand:SI 2 "const_int_operand" "n"))
5483 (match_operand:SI 3 "const_int_operand" "n")
5485 (clobber (reg:SI T_REG))]
5486 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5488 [(set (attr "length")
5489 (cond [(match_test "shl_sext_length (insn)")
5491 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5493 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5495 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5497 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5499 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5501 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5503 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5504 (const_string "16")]
5505 (const_string "18")))
5506 (set_attr "type" "arith")])
5508 (define_insn "shl_sext_sub"
5509 [(set (match_operand:SI 0 "register_operand" "=z")
5511 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5512 (match_operand:SI 2 "const_int_operand" "n"))
5513 (match_operand:SI 3 "const_int_operand" "n")
5515 (clobber (reg:SI T_REG))]
5516 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5518 [(set (attr "length")
5519 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5521 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5523 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5525 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5526 (const_string "12")]
5527 (const_string "14")))
5528 (set_attr "type" "arith")])
5530 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5531 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5533 (define_insn "xtrct_left"
5534 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5535 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5537 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5541 [(set_attr "type" "arith")])
5543 (define_insn "xtrct_right"
5544 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5545 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5547 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5551 [(set_attr "type" "arith")])
5553 ;; -------------------------------------------------------------------------
5555 ;; -------------------------------------------------------------------------
5558 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5559 (neg:SI (plus:SI (reg:SI T_REG)
5560 (match_operand:SI 1 "arith_reg_operand" "r"))))
5562 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5566 [(set_attr "type" "arith")])
5568 ;; A simplified version of the negc insn, where the exact value of the
5569 ;; T bit doesn't matter. This is easier for combine to pick up.
5570 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5571 ;; extra patterns for this case.
5572 (define_insn "*negc"
5573 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5574 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5575 (match_operand:SI 2 "t_reg_operand" "")))
5576 (clobber (reg:SI T_REG))]
5579 [(set_attr "type" "arith")])
5581 (define_insn "*negdi_media"
5582 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5583 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5586 [(set_attr "type" "arith_media")])
5588 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
5590 (define_expand "negdi2"
5591 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5592 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5593 (clobber (reg:SI T_REG))])]
5596 (define_insn_and_split "*negdi2"
5597 [(set (match_operand:DI 0 "arith_reg_dest")
5598 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5599 (clobber (reg:SI T_REG))]
5602 "&& can_create_pseudo_p ()"
5605 emit_insn (gen_clrt ());
5606 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5607 gen_lowpart (SImode, operands[1])));
5608 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5609 gen_highpart (SImode, operands[1])));
5613 (define_insn "negsi2"
5614 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5615 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5618 [(set_attr "type" "arith")])
5620 (define_insn_and_split "one_cmplsi2"
5621 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5622 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5625 "&& can_create_pseudo_p ()"
5626 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5627 (set (match_dup 0) (reg:SI T_REG))]
5630 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5633 (set (reg0) (not:SI (reg0) (reg1)))
5634 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5635 (clobber (reg:SI T_REG))])
5637 ... match and combine the sequence manually in the split pass after the
5638 combine pass. Notice that combine does try the target pattern of this
5639 split, but if the pattern is added it interferes with other patterns, in
5640 particular with the div0s comparisons.
5641 This could also be done with a peephole but doing it here before register
5642 allocation can save one temporary.
5643 When we're here, the not:SI pattern obviously has been matched already
5644 and we only have to see whether the following insn is the left shift. */
5646 rtx i = next_nonnote_insn_bb (curr_insn);
5647 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
5650 rtx p = PATTERN (i);
5651 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
5654 rtx p0 = XVECEXP (p, 0, 0);
5655 rtx p1 = XVECEXP (p, 0, 1);
5657 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
5658 GET_CODE (p0) == SET
5659 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
5660 && REG_P (XEXP (XEXP (p0, 1), 0))
5661 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
5662 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
5663 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
5665 /* (clobber (reg:SI T_REG)) */
5666 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
5667 && REGNO (XEXP (p1, 0)) == T_REG)
5669 operands[0] = XEXP (p0, 0);
5670 set_insn_deleted (i);
5675 [(set_attr "type" "arith")])
5677 (define_expand "one_cmpldi2"
5678 [(set (match_operand:DI 0 "arith_reg_dest" "")
5679 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
5681 "TARGET_SHMEDIA" "")
5683 (define_expand "abs<mode>2"
5684 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
5685 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5686 (clobber (reg:SI T_REG))])]
5689 (define_insn_and_split "*abs<mode>2"
5690 [(set (match_operand:SIDI 0 "arith_reg_dest")
5691 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5692 (clobber (reg:SI T_REG))]
5695 "&& can_create_pseudo_p ()"
5698 if (<MODE>mode == SImode)
5699 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5702 rtx high_src = gen_highpart (SImode, operands[1]);
5703 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5706 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5711 (define_insn_and_split "*negabs<mode>2"
5712 [(set (match_operand:SIDI 0 "arith_reg_dest")
5713 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
5714 (clobber (reg:SI T_REG))]
5717 "&& can_create_pseudo_p ()"
5720 if (<MODE>mode == SImode)
5721 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5724 rtx high_src = gen_highpart (SImode, operands[1]);
5725 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5728 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5733 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
5734 ;; This can be used as some kind of conditional execution, which is useful
5736 ;; Actually the instruction scheduling should decide whether to use a
5737 ;; zero-offset branch or not for any generic case involving a single
5738 ;; instruction on SH4 202.
5739 (define_insn_and_split "negsi_cond"
5740 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5742 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
5743 (match_operand:SI 1 "arith_reg_operand" "0,0")
5744 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
5745 "TARGET_SH1 && TARGET_ZDCBRANCH"
5747 static const char* alt[] =
5757 return alt[which_alternative];
5759 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
5762 rtx skip_neg_label = gen_label_rtx ();
5764 emit_move_insn (operands[0], operands[1]);
5766 emit_jump_insn (INTVAL (operands[3])
5767 ? gen_branch_true (skip_neg_label)
5768 : gen_branch_false (skip_neg_label));
5770 emit_label_after (skip_neg_label,
5771 emit_insn (gen_negsi2 (operands[0], operands[1])));
5774 [(set_attr "type" "arith") ;; poor approximation
5775 (set_attr "length" "4")])
5777 (define_insn_and_split "negdi_cond"
5778 [(set (match_operand:DI 0 "arith_reg_dest")
5780 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
5781 (match_operand:DI 1 "arith_reg_operand")
5782 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
5783 (clobber (reg:SI T_REG))]
5786 "&& can_create_pseudo_p ()"
5789 rtx skip_neg_label = gen_label_rtx ();
5791 emit_move_insn (operands[0], operands[1]);
5793 emit_jump_insn (INTVAL (operands[3])
5794 ? gen_branch_true (skip_neg_label)
5795 : gen_branch_false (skip_neg_label));
5797 if (!INTVAL (operands[3]))
5798 emit_insn (gen_clrt ());
5800 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5801 gen_lowpart (SImode, operands[1])));
5802 emit_label_after (skip_neg_label,
5803 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5804 gen_highpart (SImode, operands[1]))));
5808 (define_expand "bswapsi2"
5809 [(set (match_operand:SI 0 "arith_reg_dest" "")
5810 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
5813 if (! can_create_pseudo_p ())
5817 rtx tmp0 = gen_reg_rtx (SImode);
5818 rtx tmp1 = gen_reg_rtx (SImode);
5820 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
5821 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
5822 emit_insn (gen_swapbsi2 (operands[0], tmp1));
5827 (define_insn "swapbsi2"
5828 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5829 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
5830 (const_int 4294901760))
5831 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5833 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5834 (const_int 255)))))]
5837 [(set_attr "type" "arith")])
5839 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
5840 ;; partial byte swap expressions such as...
5841 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
5842 ;; ...which are currently not handled by the tree optimizers.
5843 ;; The combine pass will not initially try to combine the full expression,
5844 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
5845 ;; pattern acts as an intermediate pattern that will eventually lead combine
5846 ;; to the swapbsi2 pattern above.
5847 ;; As a side effect this also improves code that does (x & 0xFF) << 8
5848 ;; or (x << 8) & 0xFF00.
5849 (define_insn_and_split "*swapbisi2_and_shl8"
5850 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5851 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5854 (match_operand:SI 2 "arith_reg_operand" "r")))]
5855 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5857 "&& can_create_pseudo_p ()"
5860 rtx tmp0 = gen_reg_rtx (SImode);
5861 rtx tmp1 = gen_reg_rtx (SImode);
5863 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
5864 emit_insn (gen_swapbsi2 (tmp1, tmp0));
5865 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
5869 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
5870 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
5871 (define_insn_and_split "*swapbhisi2"
5872 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5873 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5876 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
5877 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5879 "&& can_create_pseudo_p ()"
5882 rtx tmp = gen_reg_rtx (SImode);
5884 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
5885 emit_insn (gen_swapbsi2 (operands[0], tmp));
5889 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
5893 ;; which can be simplified to...
5896 [(set (match_operand:SI 0 "arith_reg_dest" "")
5897 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5898 (const_int 4294901760))
5899 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5901 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5903 (set (match_operand:SI 2 "arith_reg_dest" "")
5905 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
5907 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5908 (const_int 4294901760))
5909 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5911 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5912 (const_int 255)))))])
5914 ;; -------------------------------------------------------------------------
5915 ;; Zero extension instructions
5916 ;; -------------------------------------------------------------------------
5918 (define_insn "zero_extendsidi2"
5919 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5920 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
5922 "addz.l %1, r63, %0"
5923 [(set_attr "type" "arith_media")
5924 (set_attr "highpart" "extend")])
5926 (define_insn "zero_extendhidi2"
5927 [(set (match_operand:DI 0 "register_operand" "=r,r")
5928 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5933 [(set_attr "type" "*,load_media")
5934 (set (attr "highpart")
5935 (cond [(match_test "sh_contains_memref_p (insn)")
5936 (const_string "user")]
5937 (const_string "ignore")))])
5940 [(set (match_operand:DI 0 "register_operand" "")
5941 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
5942 "TARGET_SHMEDIA && reload_completed"
5943 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
5944 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
5946 if (GET_CODE (operands[1]) == TRUNCATE)
5947 operands[1] = XEXP (operands[1], 0);
5950 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
5951 ;; reload the entire truncate expression.
5952 (define_insn_and_split "*loaddi_trunc"
5953 [(set (match_operand 0 "any_register_operand" "=r")
5954 (truncate (match_operand:DI 1 "memory_operand" "m")))]
5955 "TARGET_SHMEDIA && reload_completed"
5957 "TARGET_SHMEDIA && reload_completed"
5958 [(set (match_dup 0) (match_dup 1))]
5960 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
5963 (define_insn "zero_extendqidi2"
5964 [(set (match_operand:DI 0 "register_operand" "=r,r")
5965 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
5970 [(set_attr "type" "arith_media,load_media")
5971 (set (attr "highpart")
5972 (cond [(match_test "sh_contains_memref_p (insn)")
5973 (const_string "user")]
5974 (const_string "ignore")))])
5976 (define_expand "zero_extend<mode>si2"
5977 [(set (match_operand:SI 0 "arith_reg_dest")
5978 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
5980 (define_insn_and_split "*zero_extend<mode>si2_compact"
5981 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5982 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
5985 "&& can_create_pseudo_p ()"
5986 [(set (match_dup 0) (match_dup 2))]
5988 /* Sometimes combine fails to combine a T bit or negated T bit store to a
5989 reg with a following zero extension. In the split pass after combine,
5990 try to figure out how the extended reg was set. If it originated from
5991 the T bit we can replace the zero extension with a reg move, which will
5992 be eliminated. Notice that this also helps the *cbranch_t splitter when
5993 it tries to post-combine tests and conditional branches, as it does not
5994 check for zero extensions. */
5995 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
5996 if (operands[2] == NULL_RTX)
5999 [(set_attr "type" "arith")])
6001 (define_insn "*zero_extendhisi2_media"
6002 [(set (match_operand:SI 0 "register_operand" "=r,r")
6003 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6008 [(set_attr "type" "arith_media,load_media")
6009 (set (attr "highpart")
6010 (cond [(match_test "sh_contains_memref_p (insn)")
6011 (const_string "user")]
6012 (const_string "ignore")))])
6015 [(set (match_operand:SI 0 "register_operand" "")
6016 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6017 "TARGET_SHMEDIA && reload_completed"
6018 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6019 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
6021 rtx op1 = operands[1];
6023 if (GET_CODE (op1) == TRUNCATE)
6024 op1 = XEXP (op1, 0);
6026 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6027 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6030 (define_insn "*zero_extendqisi2_media"
6031 [(set (match_operand:SI 0 "register_operand" "=r,r")
6032 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6037 [(set_attr "type" "arith_media,load_media")
6038 (set (attr "highpart")
6039 (cond [(match_test "sh_contains_memref_p (insn)")
6040 (const_string "user")]
6041 (const_string "ignore")))])
6043 (define_insn "zero_extendqihi2"
6044 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6045 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6048 [(set_attr "type" "arith")])
6050 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
6051 ;; They could also be used for simple memory addresses like @Rn by setting
6052 ;; the displacement value to zero. However, doing so too early results in
6053 ;; missed opportunities for other optimizations such as post-inc or index
6054 ;; addressing loads.
6055 ;; Although the 'zero_extend_movu_operand' predicate does not allow simple
6056 ;; register addresses (an address without a displacement, index, post-inc),
6057 ;; zero-displacement addresses might be generated during reload, wich are
6058 ;; simplified to simple register addresses in turn. Thus, we have to
6059 ;; provide the Sdd and Sra alternatives in the patterns.
6060 (define_insn "*zero_extend<mode>si2_disp_mem"
6061 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6063 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
6067 movu.<bw> @(0,%t1),%0"
6068 [(set_attr "type" "load")
6069 (set_attr "length" "4")])
6071 ;; Convert the zero extending loads in sequences such as:
6072 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
6073 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6075 ;; back to sign extending loads like:
6076 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
6077 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6079 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
6080 ;; is only 2 bytes in size if the displacement is {K04|K05}.
6081 ;; If the displacement is greater it doesn't matter, so we convert anyways.
6083 [(set (match_operand:SI 0 "arith_reg_dest" "")
6084 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
6085 (set (match_operand 2 "nonimmediate_operand" "")
6086 (match_operand 3 "arith_reg_operand" ""))]
6088 && REGNO (operands[0]) == REGNO (operands[3])
6089 && peep2_reg_dead_p (2, operands[0])
6090 && GET_MODE_SIZE (GET_MODE (operands[2]))
6091 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
6092 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
6093 (set (match_dup 2) (match_dup 3))])
6095 ;; Fold sequences such as
6099 ;; movu.b @(0,r3),r7
6100 ;; This does not reduce the code size but the number of instructions is
6101 ;; halved, which results in faster code.
6103 [(set (match_operand:SI 0 "arith_reg_dest" "")
6104 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
6105 (set (match_operand:SI 2 "arith_reg_dest" "")
6106 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
6108 && GET_MODE (operands[1]) == GET_MODE (operands[3])
6109 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
6110 && REGNO (operands[0]) == REGNO (operands[3])
6111 && (REGNO (operands[2]) == REGNO (operands[0])
6112 || peep2_reg_dead_p (2, operands[0]))"
6113 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
6116 = replace_equiv_address (operands[1],
6117 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
6121 ;; -------------------------------------------------------------------------
6122 ;; Sign extension instructions
6123 ;; -------------------------------------------------------------------------
6125 ;; ??? This should be a define expand.
6126 ;; ??? Or perhaps it should be dropped?
6128 ;; convert_move generates good code for SH[1-4].
6129 (define_insn "extendsidi2"
6130 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6131 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6137 [(set_attr "type" "arith_media,load_media,fpconv_media")
6138 (set (attr "highpart")
6139 (cond [(match_test "sh_contains_memref_p (insn)")
6140 (const_string "user")]
6141 (const_string "extend")))])
6143 (define_insn "extendhidi2"
6144 [(set (match_operand:DI 0 "register_operand" "=r,r")
6145 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6150 [(set_attr "type" "*,load_media")
6151 (set (attr "highpart")
6152 (cond [(match_test "sh_contains_memref_p (insn)")
6153 (const_string "user")]
6154 (const_string "ignore")))])
6157 [(set (match_operand:DI 0 "register_operand" "")
6158 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6159 "TARGET_SHMEDIA && reload_completed"
6160 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6161 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6163 if (GET_CODE (operands[1]) == TRUNCATE)
6164 operands[1] = XEXP (operands[1], 0);
6167 (define_insn "extendqidi2"
6168 [(set (match_operand:DI 0 "register_operand" "=r,r")
6169 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6174 [(set_attr "type" "*,load_media")
6175 (set (attr "highpart")
6176 (cond [(match_test "sh_contains_memref_p (insn)")
6177 (const_string "user")]
6178 (const_string "ignore")))])
6181 [(set (match_operand:DI 0 "register_operand" "")
6182 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6183 "TARGET_SHMEDIA && reload_completed"
6184 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6185 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6187 if (GET_CODE (operands[1]) == TRUNCATE)
6188 operands[1] = XEXP (operands[1], 0);
6191 (define_expand "extend<mode>si2"
6192 [(set (match_operand:SI 0 "arith_reg_dest")
6193 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6195 (define_insn "*extendhisi2_media"
6196 [(set (match_operand:SI 0 "register_operand" "=r,r")
6197 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6202 [(set_attr "type" "arith_media,load_media")
6203 (set (attr "highpart")
6204 (cond [(match_test "sh_contains_memref_p (insn)")
6205 (const_string "user")]
6206 (const_string "ignore")))])
6209 [(set (match_operand:SI 0 "register_operand" "")
6210 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6211 "TARGET_SHMEDIA && reload_completed"
6212 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6213 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6215 rtx op1 = operands[1];
6216 if (GET_CODE (op1) == TRUNCATE)
6217 op1 = XEXP (op1, 0);
6219 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6220 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6223 (define_insn_and_split "*extend<mode>si2_compact_reg"
6224 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6225 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6228 "&& can_create_pseudo_p ()"
6229 [(set (match_dup 0) (match_dup 2))]
6231 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6232 reg with a following sign extension. In the split pass after combine,
6233 try to figure the extended reg was set. If it originated from the T
6234 bit we can replace the sign extension with a reg move, which will be
6236 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6237 if (operands[2] == NULL_RTX)
6240 [(set_attr "type" "arith")])
6242 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6244 (define_insn "*extend<mode>si2_compact_mem_disp"
6245 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6249 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6250 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6251 "TARGET_SH1 && ! TARGET_SH2A
6252 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6254 mov.<bw> @(%O2,%1),%0
6256 [(set_attr "type" "load")])
6258 (define_insn "*extend<mode>si2_compact_mem_disp"
6259 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6263 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6264 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6265 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6267 mov.<bw> @(%O2,%1),%0
6269 mov.<bw> @(%O2,%1),%0"
6270 [(set_attr "type" "load")
6271 (set_attr "length" "2,2,4")])
6273 ;; The *_snd patterns will take care of other QImode/HImode addressing
6274 ;; modes than displacement addressing. They must be defined _after_ the
6275 ;; displacement addressing patterns. Otherwise the displacement addressing
6276 ;; patterns will not be picked.
6277 (define_insn "*extend<mode>si2_compact_snd"
6278 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6280 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6283 [(set_attr "type" "load")])
6285 (define_insn "*extendqisi2_media"
6286 [(set (match_operand:SI 0 "register_operand" "=r,r")
6287 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6292 [(set_attr "type" "arith_media,load_media")
6293 (set (attr "highpart")
6294 (cond [(match_test "sh_contains_memref_p (insn)")
6295 (const_string "user")]
6296 (const_string "ignore")))])
6299 [(set (match_operand:SI 0 "register_operand" "")
6300 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6301 "TARGET_SHMEDIA && reload_completed"
6302 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6303 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6305 rtx op1 = operands[1];
6306 if (GET_CODE (op1) == TRUNCATE)
6307 op1 = XEXP (op1, 0);
6309 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6310 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6313 (define_expand "extendqihi2"
6314 [(set (match_operand:HI 0 "arith_reg_dest" "")
6315 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))]
6319 (define_insn "*extendqihi2_compact_reg"
6320 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6321 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6324 [(set_attr "type" "arith")])
6326 ;; It would seem useful to combine the truncXi patterns into the movXi
6327 ;; patterns, but unary operators are ignored when matching constraints,
6328 ;; so we need separate patterns.
6329 (define_insn "truncdisi2"
6330 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6331 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6340 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6341 fpconv_media,fmove_media")
6342 (set (attr "highpart")
6343 (cond [(match_test "sh_contains_memref_p (insn)")
6344 (const_string "user")]
6345 (const_string "extend")))])
6347 (define_insn "truncdihi2"
6348 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6349 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6352 static const char* alt[] =
6354 "shlli %1,48,%0" "\n"
6359 return alt[which_alternative];
6361 [(set_attr "type" "arith_media,store_media")
6362 (set_attr "length" "8,4")
6363 (set (attr "highpart")
6364 (cond [(match_test "sh_contains_memref_p (insn)")
6365 (const_string "user")]
6366 (const_string "extend")))])
6368 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6369 ; Because we use zero extension, we can't provide signed QImode compares
6370 ; using a simple compare or conditional branch insn.
6371 (define_insn "truncdiqi2"
6372 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6373 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6378 [(set_attr "type" "arith_media,store")
6379 (set (attr "highpart")
6380 (cond [(match_test "sh_contains_memref_p (insn)")
6381 (const_string "user")]
6382 (const_string "extend")))])
6384 ;; -------------------------------------------------------------------------
6385 ;; Move instructions
6386 ;; -------------------------------------------------------------------------
6388 ;; define push and pop so it is easy for sh.c
6389 ;; We can't use push and pop on SHcompact because the stack must always
6390 ;; be 8-byte aligned.
6391 (define_expand "push"
6392 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6393 (match_operand:SI 0 "register_operand" "r,l,x"))]
6394 "TARGET_SH1 && ! TARGET_SH5"
6397 (define_expand "pop"
6398 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6399 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6400 "TARGET_SH1 && ! TARGET_SH5"
6403 (define_expand "push_e"
6404 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6405 (match_operand:SF 0 "" ""))
6406 (use (reg:PSI FPSCR_REG))
6407 (clobber (scratch:SI))])]
6408 "TARGET_SH1 && ! TARGET_SH5"
6411 (define_insn "push_fpul"
6412 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6413 "TARGET_SH2E && ! TARGET_SH5"
6415 [(set_attr "type" "fstore")
6416 (set_attr "late_fp_use" "yes")
6417 (set_attr "hit_stack" "yes")])
6419 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6421 (define_expand "push_4"
6422 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6423 (match_operand:DF 0 "" ""))
6424 (use (reg:PSI FPSCR_REG))
6425 (clobber (scratch:SI))])]
6426 "TARGET_SH1 && ! TARGET_SH5"
6429 (define_expand "pop_e"
6430 [(parallel [(set (match_operand:SF 0 "" "")
6431 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6432 (use (reg:PSI FPSCR_REG))
6433 (clobber (scratch:SI))])]
6434 "TARGET_SH1 && ! TARGET_SH5"
6437 (define_insn "pop_fpul"
6438 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6439 "TARGET_SH2E && ! TARGET_SH5"
6441 [(set_attr "type" "load")
6442 (set_attr "hit_stack" "yes")])
6444 (define_expand "pop_4"
6445 [(parallel [(set (match_operand:DF 0 "" "")
6446 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6447 (use (reg:PSI FPSCR_REG))
6448 (clobber (scratch:SI))])]
6449 "TARGET_SH1 && ! TARGET_SH5"
6452 (define_expand "push_fpscr"
6456 rtx insn = emit_insn (gen_fpu_switch (gen_frame_mem (PSImode,
6457 gen_rtx_PRE_DEC (Pmode,
6458 stack_pointer_rtx)),
6460 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6464 (define_expand "pop_fpscr"
6468 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
6469 gen_frame_mem (PSImode,
6470 gen_rtx_POST_INC (Pmode,
6471 stack_pointer_rtx))));
6472 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6476 ;; The clrt and sett patterns can happen as the result of optimization and
6478 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6479 ;; In this case they might not disappear completely, because the T reg is
6480 ;; a fixed hard reg.
6481 ;; When DImode operations that use the T reg as carry/borrow are split into
6482 ;; individual SImode operations, the T reg is usually cleared before the
6483 ;; first SImode insn.
6485 [(set (reg:SI T_REG) (const_int 0))]
6488 [(set_attr "type" "mt_group")])
6491 [(set (reg:SI T_REG) (const_int 1))]
6494 [(set_attr "type" "mt_group")])
6496 ;; Use the combine pass to transform sequences such as
6500 ;; mov.l @(r0,r4),r0
6506 ;; See also PR 39423.
6507 ;; Notice that these patterns have a T_REG clobber, because the shift
6508 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6509 ;; clobber would be added conditionally, depending on the result of
6510 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6511 ;; through the ashlsi3 expander in order to get the right shift insn --
6512 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6513 ;; FIXME: Combine never tries this kind of patterns for DImode.
6514 (define_insn_and_split "*movsi_index_disp_load"
6515 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6516 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6517 (clobber (reg:SI T_REG))]
6520 "&& can_create_pseudo_p ()"
6521 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6522 (set (match_dup 0) (match_dup 7))]
6524 rtx mem = operands[1];
6525 rtx plus0_rtx = XEXP (mem, 0);
6526 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6527 rtx mult_rtx = XEXP (plus1_rtx, 0);
6529 operands[1] = XEXP (mult_rtx, 0);
6530 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6531 operands[3] = XEXP (plus1_rtx, 1);
6532 operands[4] = XEXP (plus0_rtx, 1);
6533 operands[5] = gen_reg_rtx (SImode);
6534 operands[6] = gen_reg_rtx (SImode);
6536 replace_equiv_address (mem,
6537 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6539 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6542 (define_insn_and_split "*movhi_index_disp_load"
6543 [(set (match_operand:SI 0 "arith_reg_dest")
6544 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6545 (clobber (reg:SI T_REG))]
6548 "&& can_create_pseudo_p ()"
6551 rtx mem = operands[1];
6552 rtx plus0_rtx = XEXP (mem, 0);
6553 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6554 rtx mult_rtx = XEXP (plus1_rtx, 0);
6556 rtx op_1 = XEXP (mult_rtx, 0);
6557 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6558 rtx op_3 = XEXP (plus1_rtx, 1);
6559 rtx op_4 = XEXP (plus0_rtx, 1);
6560 rtx op_5 = gen_reg_rtx (SImode);
6561 rtx op_6 = gen_reg_rtx (SImode);
6562 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6564 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6565 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6567 if (<CODE> == SIGN_EXTEND)
6569 emit_insn (gen_extendhisi2 (operands[0], op_7));
6572 else if (<CODE> == ZERO_EXTEND)
6574 /* On SH2A the movu.w insn can be used for zero extending loads. */
6576 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6579 emit_insn (gen_extendhisi2 (operands[0], op_7));
6580 emit_insn (gen_zero_extendhisi2 (operands[0],
6581 gen_lowpart (HImode, operands[0])));
6589 (define_insn_and_split "*mov<mode>_index_disp_store"
6590 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6591 (match_operand:HISI 1 "arith_reg_operand" "r"))
6592 (clobber (reg:SI T_REG))]
6595 "&& can_create_pseudo_p ()"
6596 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6597 (set (match_dup 7) (match_dup 1))]
6599 rtx mem = operands[0];
6600 rtx plus0_rtx = XEXP (mem, 0);
6601 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6602 rtx mult_rtx = XEXP (plus1_rtx, 0);
6604 operands[0] = XEXP (mult_rtx, 0);
6605 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6606 operands[3] = XEXP (plus1_rtx, 1);
6607 operands[4] = XEXP (plus0_rtx, 1);
6608 operands[5] = gen_reg_rtx (SImode);
6609 operands[6] = gen_reg_rtx (SImode);
6611 replace_equiv_address (mem,
6612 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6614 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6617 ;; t/r must come after r/r, lest reload will try to reload stuff like
6618 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6619 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6620 (define_insn "movsi_i"
6621 [(set (match_operand:SI 0 "general_movdst_operand"
6622 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6623 (match_operand:SI 1 "general_movsrc_operand"
6624 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6628 && (register_operand (operands[0], SImode)
6629 || register_operand (operands[1], SImode))"
6645 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
6646 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
6647 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
6649 ;; t/r must come after r/r, lest reload will try to reload stuff like
6650 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
6651 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
6652 ;; will require a reload.
6653 ;; ??? We can't include f/f because we need the proper FPSCR setting when
6654 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
6655 (define_insn "movsi_ie"
6656 [(set (match_operand:SI 0 "general_movdst_operand"
6657 "=r,r,r,r,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
6658 (match_operand:SI 1 "general_movsrc_operand"
6659 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
6660 "(TARGET_SH2E || TARGET_SH2A)
6661 && (register_operand (operands[0], SImode)
6662 || register_operand (operands[1], SImode))"
6687 ! move optimized away"
6688 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
6689 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
6690 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
6691 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
6692 (set_attr_alternative "length"
6699 (match_test "TARGET_SH2A")
6700 (const_int 4) (const_int 2))
6704 (match_test "TARGET_SH2A")
6705 (const_int 4) (const_int 2))
6722 (define_insn "movsi_i_lowpart"
6723 [(set (strict_low_part
6724 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
6725 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
6727 && (register_operand (operands[0], SImode)
6728 || register_operand (operands[1], SImode))"
6738 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
6740 (define_insn_and_split "load_ra"
6741 [(set (match_operand:SI 0 "general_movdst_operand" "")
6742 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
6745 "&& ! currently_expanding_to_rtl"
6746 [(set (match_dup 0) (match_dup 1))]
6748 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
6749 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
6752 ;; The '?'s in the following constraints may not reflect the time taken
6753 ;; to perform the move. They are there to discourage the use of floating-
6754 ;; point registers for storing integer values.
6755 (define_insn "*movsi_media"
6756 [(set (match_operand:SI 0 "general_movdst_operand"
6757 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
6758 (match_operand:SI 1 "general_movsrc_operand"
6759 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
6761 && (register_operand (operands[0], SImode)
6762 || sh_register_operand (operands[1], SImode)
6763 || GET_CODE (operands[1]) == TRUNCATE)"
6778 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6779 fload_media,fstore_media,fload_media,fpconv_media,
6780 fmove_media,ptabs_media,gettr_media,pt_media")
6781 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
6782 (set (attr "highpart")
6783 (cond [(match_test "sh_contains_memref_p (insn)")
6784 (const_string "user")]
6785 (const_string "ignore")))])
6787 (define_insn "*movsi_media_nofpu"
6788 [(set (match_operand:SI 0 "general_movdst_operand"
6789 "=r,r,r,r,m,*b,r,*b")
6790 (match_operand:SI 1 "general_movsrc_operand"
6791 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
6793 && (register_operand (operands[0], SImode)
6794 || sh_register_operand (operands[1], SImode)
6795 || GET_CODE (operands[1]) == TRUNCATE)"
6805 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6806 ptabs_media,gettr_media,pt_media")
6807 (set_attr "length" "4,4,8,4,4,4,4,12")
6808 (set (attr "highpart")
6809 (cond [(match_test "sh_contains_memref_p (insn)")
6810 (const_string "user")]
6811 (const_string "ignore")))])
6813 (define_expand "movsi_const"
6814 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6815 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6816 (const_int 16)] UNSPEC_EXTRACT_S16)))
6818 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
6819 (const:SI (unspec:SI [(match_dup 1)
6820 (const_int 0)] UNSPEC_EXTRACT_U16))))]
6821 "TARGET_SHMEDIA && reload_completed
6822 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6824 if (GET_CODE (operands[1]) == LABEL_REF
6825 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
6826 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
6827 else if (GOTOFF_P (operands[1]))
6829 rtx unspec = XEXP (operands[1], 0);
6831 if (! UNSPEC_GOTOFF_P (unspec))
6833 unspec = XEXP (unspec, 0);
6834 if (! UNSPEC_GOTOFF_P (unspec))
6837 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
6838 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
6839 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
6843 (define_expand "movsi_const_16bit"
6844 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6845 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6846 (const_int 0)] UNSPEC_EXTRACT_S16)))]
6847 "TARGET_SHMEDIA && flag_pic && reload_completed
6848 && GET_CODE (operands[1]) == SYMBOL_REF"
6852 [(set (match_operand:SI 0 "arith_reg_dest" "")
6853 (match_operand:SI 1 "immediate_operand" ""))]
6854 "TARGET_SHMEDIA && reload_completed
6855 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6858 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
6860 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
6866 [(set (match_operand:SI 0 "register_operand" "")
6867 (match_operand:SI 1 "immediate_operand" ""))]
6868 "TARGET_SHMEDIA && reload_completed
6869 && ((CONST_INT_P (operands[1])
6870 && ! satisfies_constraint_I16 (operands[1]))
6871 || GET_CODE (operands[1]) == CONST_DOUBLE)"
6872 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
6874 (define_expand "movsi"
6875 [(set (match_operand:SI 0 "general_movdst_operand" "")
6876 (match_operand:SI 1 "general_movsrc_operand" ""))]
6879 prepare_move_operands (operands, SImode);
6882 (define_expand "ic_invalidate_line"
6883 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
6884 (match_dup 1)] UNSPEC_ICACHE)
6885 (clobber (scratch:SI))])]
6886 "TARGET_HARD_SH4 || TARGET_SH5"
6890 emit_insn (gen_ic_invalidate_line_media (operands[0]));
6893 else if (TARGET_SHCOMPACT)
6895 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
6896 operands[1] = force_reg (Pmode, operands[1]);
6897 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
6900 else if (TARGET_SH4A_ARCH || TARGET_SH4_300)
6902 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
6905 operands[0] = force_reg (Pmode, operands[0]);
6906 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
6910 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
6911 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
6912 ;; the requirement *1*00 for associative address writes. The alignment of
6913 ;; %0 implies that its least significant bit is cleared,
6914 ;; thus we clear the V bit of a matching entry if there is one.
6915 (define_insn "ic_invalidate_line_i"
6916 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
6917 (match_operand:SI 1 "register_operand" "r")]
6919 (clobber (match_scratch:SI 2 "=&r"))]
6922 return "ocbwb @%0" "\n"
6923 " extu.w %0,%2" "\n"
6927 [(set_attr "length" "8")
6928 (set_attr "type" "cwb")])
6930 (define_insn "ic_invalidate_line_sh4a"
6931 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
6933 "TARGET_SH4A_ARCH || TARGET_SH4_300"
6935 return "ocbwb @%0" "\n"
6939 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
6940 (set_attr "type" "cwb")])
6942 ;; ??? could make arg 0 an offsettable memory operand to allow to save
6943 ;; an add in the code that calculates the address.
6944 (define_insn "ic_invalidate_line_media"
6945 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
6949 return "ocbwb %0,0" "\n"
6954 [(set_attr "length" "16")
6955 (set_attr "type" "invalidate_line_media")])
6957 (define_insn "ic_invalidate_line_compact"
6958 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6959 (match_operand:SI 1 "register_operand" "r")]
6961 (clobber (reg:SI PR_REG))]
6964 [(set_attr "type" "sfunc")
6965 (set_attr "needs_delay_slot" "yes")])
6967 (define_expand "initialize_trampoline"
6968 [(match_operand:SI 0 "" "")
6969 (match_operand:SI 1 "" "")
6970 (match_operand:SI 2 "" "")]
6975 tramp = force_reg (Pmode, operands[0]);
6976 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
6978 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
6979 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
6981 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
6985 (define_insn "initialize_trampoline_compact"
6986 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6987 (match_operand:SI 1 "register_operand" "r")
6988 (reg:SI R2_REG) (reg:SI R3_REG)]
6991 (clobber (reg:SI PR_REG))]
6994 [(set_attr "type" "sfunc")
6995 (set_attr "needs_delay_slot" "yes")])
6997 (define_expand "mov<mode>"
6998 [(set (match_operand:QIHI 0 "general_movdst_operand")
6999 (match_operand:QIHI 1 "general_movsrc_operand"))]
7002 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
7003 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
7005 rtx reg = gen_reg_rtx(SImode);
7006 emit_move_insn (reg, operands[1]);
7007 operands[1] = gen_lowpart (<MODE>mode, reg);
7010 prepare_move_operands (operands, <MODE>mode);
7013 ;; Specifying the displacement addressing load / store patterns separately
7014 ;; before the generic movqi / movhi pattern allows controlling the order
7015 ;; in which load / store insns are selected in a more fine grained way.
7016 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
7017 ;; "enabled" attribute as it is done in other targets.
7018 (define_insn "*mov<mode>_store_mem_disp04"
7020 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
7021 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
7022 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
7023 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
7025 mov.<bw> %2,@(%O1,%0)
7027 [(set_attr "type" "store")])
7029 (define_insn "*mov<mode>_store_mem_disp12"
7031 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
7032 (match_operand:SI 1 "const_int_operand" "<disp12>")))
7033 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
7034 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
7035 "mov.<bw> %2,@(%O1,%0)"
7036 [(set_attr "type" "store")
7037 (set_attr "length" "4")])
7039 (define_insn "*mov<mode>_load_mem_disp04"
7040 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
7042 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
7043 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
7044 "TARGET_SH1 && ! TARGET_SH2A
7045 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
7047 mov.<bw> @(%O2,%1),%0
7049 [(set_attr "type" "load")])
7051 (define_insn "*mov<mode>_load_mem_disp12"
7052 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
7055 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
7056 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
7057 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
7059 mov.<bw> @(%O2,%1),%0
7061 mov.<bw> @(%O2,%1),%0"
7062 [(set_attr "type" "load")
7063 (set_attr "length" "2,2,4")])
7065 ;; The order of the constraint alternatives is important here.
7066 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
7067 ;; placed into delay slots. Since there is no QImode PC relative load, the
7068 ;; Q constraint and general_movsrc_operand will reject it for QImode.
7069 ;; The Snd alternatives should come before Sdd in order to avoid a preference
7070 ;; of using r0 als the register operand for addressing modes other than
7071 ;; displacement addressing.
7072 ;; The Sdd alternatives allow only r0 as register operand, even though on
7073 ;; SH2A any register could be allowed by switching to a 32 bit insn.
7074 ;; Generally sticking to the r0 is preferrable, since it generates smaller
7075 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
7076 (define_insn "*mov<mode>"
7077 [(set (match_operand:QIHI 0 "general_movdst_operand"
7078 "=r,r,r,Snd,r, Sdd,z, r,l")
7079 (match_operand:QIHI 1 "general_movsrc_operand"
7080 "Q,r,i,r, Snd,z, Sdd,l,r"))]
7082 && (arith_reg_operand (operands[0], <MODE>mode)
7083 || arith_reg_operand (operands[1], <MODE>mode))"
7094 [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
7095 (set (attr "length")
7096 (cond [(and (match_operand 0 "displacement_mem_operand")
7097 (not (match_operand 0 "short_displacement_mem_operand")))
7099 (and (match_operand 1 "displacement_mem_operand")
7100 (not (match_operand 1 "short_displacement_mem_operand")))
7104 (define_insn "*movqi_media"
7105 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
7106 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
7108 && (arith_reg_operand (operands[0], QImode)
7109 || extend_reg_or_0_operand (operands[1], QImode))"
7115 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7116 (set (attr "highpart")
7117 (cond [(match_test "sh_contains_memref_p (insn)")
7118 (const_string "user")]
7119 (const_string "ignore")))])
7121 (define_expand "reload_inqi"
7122 [(set (match_operand:SI 2 "" "=&r")
7123 (match_operand:QI 1 "inqhi_operand" ""))
7124 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7125 (truncate:QI (match_dup 3)))]
7128 rtx inner = XEXP (operands[1], 0);
7129 int regno = REGNO (inner);
7131 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7132 operands[1] = gen_rtx_REG (SImode, regno);
7133 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7136 (define_insn "*movhi_media"
7137 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7138 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7140 && (arith_reg_operand (operands[0], HImode)
7141 || arith_reg_or_0_operand (operands[1], HImode))"
7148 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7149 (set (attr "highpart")
7150 (cond [(match_test "sh_contains_memref_p (insn)")
7151 (const_string "user")]
7152 (const_string "ignore")))])
7155 [(set (match_operand:HI 0 "register_operand" "")
7156 (match_operand:HI 1 "immediate_operand" ""))]
7157 "TARGET_SHMEDIA && reload_completed
7158 && ! satisfies_constraint_I16 (operands[1])"
7159 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7161 (define_expand "reload_inhi"
7162 [(set (match_operand:SI 2 "" "=&r")
7163 (match_operand:HI 1 "inqhi_operand" ""))
7164 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7165 (truncate:HI (match_dup 3)))]
7168 rtx inner = XEXP (operands[1], 0);
7169 int regno = REGNO (inner);
7171 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7172 operands[1] = gen_rtx_REG (SImode, regno);
7173 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7176 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7177 ;; compiled with -m2 -ml -O3 -funroll-loops
7178 (define_insn "*movdi_i"
7179 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7180 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7182 && (arith_reg_operand (operands[0], DImode)
7183 || arith_reg_operand (operands[1], DImode))"
7185 return output_movedouble (insn, operands, DImode);
7187 [(set_attr "length" "4")
7188 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7190 ;; If the output is a register and the input is memory or a register, we have
7191 ;; to be careful and see which word needs to be loaded first.
7193 [(set (match_operand:DI 0 "general_movdst_operand" "")
7194 (match_operand:DI 1 "general_movsrc_operand" ""))]
7195 "TARGET_SH1 && reload_completed"
7196 [(set (match_dup 2) (match_dup 3))
7197 (set (match_dup 4) (match_dup 5))]
7201 if ((MEM_P (operands[0])
7202 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7203 || (MEM_P (operands[1])
7204 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7207 switch (GET_CODE (operands[0]))
7210 regno = REGNO (operands[0]);
7213 regno = subreg_regno (operands[0]);
7223 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7225 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7226 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7227 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7228 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7232 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7233 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7234 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7235 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7238 if (operands[2] == 0 || operands[3] == 0
7239 || operands[4] == 0 || operands[5] == 0)
7243 ;; The '?'s in the following constraints may not reflect the time taken
7244 ;; to perform the move. They are there to discourage the use of floating-
7245 ;; point registers for storing integer values.
7246 (define_insn "*movdi_media"
7247 [(set (match_operand:DI 0 "general_movdst_operand"
7248 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7249 (match_operand:DI 1 "general_movsrc_operand"
7250 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7252 && (register_operand (operands[0], DImode)
7253 || sh_register_operand (operands[1], DImode))"
7268 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7269 fload_media,fstore_media,fload_media,dfpconv_media,
7270 fmove_media,ptabs_media,gettr_media,pt_media")
7271 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7273 (define_insn "*movdi_media_nofpu"
7274 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7275 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7277 && (register_operand (operands[0], DImode)
7278 || sh_register_operand (operands[1], DImode))"
7288 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7289 ptabs_media,gettr_media,pt_media")
7290 (set_attr "length" "4,4,16,4,4,4,4,*")])
7292 (define_insn "*movdi_media_I16"
7293 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7294 (match_operand:DI 1 "const_int_operand" "I16"))]
7295 "TARGET_SHMEDIA && reload_completed"
7297 [(set_attr "type" "arith_media")
7298 (set_attr "length" "4")])
7301 [(set (match_operand:DI 0 "arith_reg_dest" "")
7302 (match_operand:DI 1 "immediate_operand" ""))]
7303 "TARGET_SHMEDIA && reload_completed
7304 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7305 [(set (match_dup 0) (match_dup 1))]
7309 if (TARGET_SHMEDIA64)
7310 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7312 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7314 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7319 (define_expand "movdi_const"
7320 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7321 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7322 (const_int 48)] UNSPEC_EXTRACT_S16)))
7324 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7325 (const:DI (unspec:DI [(match_dup 1)
7326 (const_int 32)] UNSPEC_EXTRACT_U16))))
7328 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7329 (const:DI (unspec:DI [(match_dup 1)
7330 (const_int 16)] UNSPEC_EXTRACT_U16))))
7332 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7333 (const:DI (unspec:DI [(match_dup 1)
7334 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7335 "TARGET_SHMEDIA64 && reload_completed
7336 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7338 sh_mark_label (operands[1], 4);
7341 (define_expand "movdi_const_32bit"
7342 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7343 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7344 (const_int 16)] UNSPEC_EXTRACT_S16)))
7346 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7347 (const:DI (unspec:DI [(match_dup 1)
7348 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7349 "TARGET_SHMEDIA32 && reload_completed
7350 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7352 sh_mark_label (operands[1], 2);
7355 (define_expand "movdi_const_16bit"
7356 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7357 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7358 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7359 "TARGET_SHMEDIA && flag_pic && reload_completed
7360 && GET_CODE (operands[1]) == SYMBOL_REF"
7364 [(set (match_operand:DI 0 "ext_dest_operand" "")
7365 (match_operand:DI 1 "immediate_operand" ""))]
7366 "TARGET_SHMEDIA && reload_completed
7367 && CONST_INT_P (operands[1])
7368 && ! satisfies_constraint_I16 (operands[1])"
7369 [(set (match_dup 0) (match_dup 2))
7372 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7373 unsigned HOST_WIDE_INT low = val;
7374 unsigned HOST_WIDE_INT high = val;
7375 unsigned HOST_WIDE_INT sign;
7376 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7378 /* Zero-extend the 16 least-significant bits. */
7381 /* Arithmetic shift right the word by 16 bits. */
7383 if (GET_CODE (operands[0]) == SUBREG
7384 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7393 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7399 /* If we can't generate the constant with a two-insn movi / shori
7400 sequence, try some other strategies. */
7401 if (! CONST_OK_FOR_I16 (high))
7403 /* Try constant load / left shift. We know VAL != 0. */
7404 val2 = val ^ (val-1);
7407 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7409 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7410 || (! CONST_OK_FOR_I16 (high >> 16)
7411 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7413 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7414 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7415 GEN_INT (trailing_zeroes));
7419 /* Try constant load / right shift. */
7420 val2 = (val >> 15) + 1;
7421 if (val2 == (val2 & -val2))
7423 int shift = 49 - exact_log2 (val2);
7425 val2 = trunc_int_for_mode (val << shift, DImode);
7426 if (CONST_OK_FOR_I16 (val2))
7428 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7434 val2 = val & 0xffff;
7435 if ((val >> 16 & 0xffff) == val2
7436 && (val >> 32 & 0xffff) == val2
7437 && (val >> 48 & 0xffff) == val2)
7439 val2 = (HOST_WIDE_INT) val >> 48;
7440 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7441 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7444 /* Try movi / mshflo.l */
7445 val2 = (HOST_WIDE_INT) val >> 32;
7446 if (val2 == ((unsigned HOST_WIDE_INT)
7447 trunc_int_for_mode (val, SImode)))
7449 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7453 /* Try movi / mshflo.l w/ r63. */
7454 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7455 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7457 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7463 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7466 operands[2] = GEN_INT (val2);
7470 [(set (match_operand:DI 0 "ext_dest_operand" "")
7471 (match_operand:DI 1 "immediate_operand" ""))]
7472 "TARGET_SHMEDIA && reload_completed
7473 && GET_CODE (operands[1]) == CONST_DOUBLE"
7474 [(set (match_dup 0) (match_dup 2))
7476 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7478 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7479 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7480 unsigned HOST_WIDE_INT val = low;
7481 unsigned HOST_WIDE_INT sign;
7483 /* Zero-extend the 16 least-significant bits. */
7485 operands[1] = GEN_INT (val);
7487 /* Arithmetic shift right the double-word by 16 bits. */
7489 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7492 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7496 /* This will only be true if high is a sign-extension of low, i.e.,
7497 it must be either 0 or (unsigned)-1, and be zero iff the
7498 most-significant bit of low is set. */
7499 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7500 operands[2] = GEN_INT (low);
7502 operands[2] = immed_double_const (low, high, DImode);
7505 (define_insn "shori_media"
7506 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7507 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7509 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7510 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7514 [(set_attr "type" "arith_media,*")])
7516 (define_insn "*shori_media_si"
7517 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7518 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7520 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7524 (define_expand "movdi"
7525 [(set (match_operand:DI 0 "general_movdst_operand" "")
7526 (match_operand:DI 1 "general_movsrc_operand" ""))]
7529 prepare_move_operands (operands, DImode);
7532 (define_insn "movdf_media"
7533 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7534 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7536 && (register_operand (operands[0], DFmode)
7537 || sh_register_operand (operands[1], DFmode))"
7548 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7549 fload_media,fstore_media,load_media,store_media")])
7551 (define_insn "movdf_media_nofpu"
7552 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7553 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7555 && (register_operand (operands[0], DFmode)
7556 || sh_register_operand (operands[1], DFmode))"
7562 [(set_attr "type" "arith_media,*,load_media,store_media")])
7565 [(set (match_operand:DF 0 "arith_reg_dest" "")
7566 (match_operand:DF 1 "immediate_operand" ""))]
7567 "TARGET_SHMEDIA && reload_completed"
7568 [(set (match_dup 3) (match_dup 2))]
7570 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7572 REAL_VALUE_TYPE value;
7574 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7575 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7577 if (HOST_BITS_PER_WIDE_INT >= 64)
7578 operands[2] = immed_double_const ((unsigned long) values[endian]
7579 | ((HOST_WIDE_INT) values[1 - endian]
7583 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7584 operands[2] = immed_double_const (values[endian], values[1 - endian],
7588 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7591 ;; FIXME: This should be a define_insn_and_split.
7592 (define_insn "movdf_k"
7593 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7594 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7596 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7597 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7598 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7599 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7600 && (arith_reg_operand (operands[0], DFmode)
7601 || arith_reg_operand (operands[1], DFmode))"
7603 return output_movedouble (insn, operands, DFmode);
7605 [(set_attr "length" "4")
7606 (set_attr "type" "move,pcload,load,store")])
7608 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7609 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7610 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7611 ;; the d/m/c/X alternative, which is split later into single-precision
7612 ;; instructions. And when not optimizing, no splits are done before fixing
7613 ;; up pcloads, so we need usable length information for that.
7614 (define_insn "movdf_i4"
7615 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7616 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7617 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
7618 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
7619 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7620 && (arith_reg_operand (operands[0], DFmode)
7621 || arith_reg_operand (operands[1], DFmode))"
7623 switch (which_alternative)
7627 return "fmov %1,%0";
7628 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7629 return "fmov %R1,%R0" "\n"
7632 return "fmov %S1,%S0" "\n"
7636 return "fmov.d %1,%0";
7641 [(set_attr_alternative "length"
7642 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
7644 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7645 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7646 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7648 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
7649 ;; We can't use 4-byte push/pop on SHcompact, so we have to
7650 ;; increment or decrement r15 explicitly.
7652 (match_test "TARGET_SHCOMPACT")
7653 (const_int 10) (const_int 8))
7655 (match_test "TARGET_SHCOMPACT")
7656 (const_int 10) (const_int 8))])
7657 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
7658 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
7659 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
7660 (const_string "double")
7661 (const_string "none")))])
7663 ;; Moving DFmode between fp/general registers through memory
7664 ;; (the top of the stack) is faster than moving through fpul even for
7665 ;; little endian. Because the type of an instruction is important for its
7666 ;; scheduling, it is beneficial to split these operations, rather than
7667 ;; emitting them in one single chunk, even if this will expose a stack
7668 ;; use that will prevent scheduling of other stack accesses beyond this
7671 [(set (match_operand:DF 0 "register_operand" "")
7672 (match_operand:DF 1 "register_operand" ""))
7673 (use (match_operand:PSI 2 "fpscr_operand" ""))
7674 (clobber (match_scratch:SI 3 "=X"))]
7675 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
7676 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
7681 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
7683 emit_move_insn (stack_pointer_rtx,
7684 plus_constant (Pmode, stack_pointer_rtx, -8));
7685 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7688 tos = gen_tmp_stack_mem (DFmode,
7689 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
7690 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
7691 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
7692 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7693 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7694 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7696 tos = gen_tmp_stack_mem (DFmode,
7697 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
7698 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
7699 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7700 emit_move_insn (stack_pointer_rtx,
7701 plus_constant (Pmode, stack_pointer_rtx, 8));
7703 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7707 ;; local-alloc sometimes allocates scratch registers even when not required,
7708 ;; so we must be prepared to handle these.
7710 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
7712 [(set (match_operand:DF 0 "general_movdst_operand" "")
7713 (match_operand:DF 1 "general_movsrc_operand" ""))
7714 (use (match_operand:PSI 2 "fpscr_operand" ""))
7715 (clobber (match_scratch:SI 3 ""))]
7716 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7718 && true_regnum (operands[0]) < 16
7719 && true_regnum (operands[1]) < 16"
7720 [(set (match_dup 0) (match_dup 1))]
7722 /* If this was a reg <-> mem operation with base + index reg addressing,
7723 we have to handle this in a special way. */
7724 rtx mem = operands[0];
7726 if (! memory_operand (mem, DFmode))
7731 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
7732 mem = SUBREG_REG (mem);
7735 rtx addr = XEXP (mem, 0);
7736 if (GET_CODE (addr) == PLUS
7737 && REG_P (XEXP (addr, 0))
7738 && REG_P (XEXP (addr, 1)))
7741 rtx reg0 = gen_rtx_REG (Pmode, 0);
7742 rtx regop = operands[store_p], word0 ,word1;
7744 if (GET_CODE (regop) == SUBREG)
7745 alter_subreg (®op, true);
7746 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
7750 mem = copy_rtx (mem);
7751 PUT_MODE (mem, SImode);
7752 word0 = gen_rtx_SUBREG (SImode, regop, 0);
7753 alter_subreg (&word0, true);
7754 word1 = gen_rtx_SUBREG (SImode, regop, 4);
7755 alter_subreg (&word1, true);
7756 if (store_p || ! refers_to_regno_p (REGNO (word0),
7757 REGNO (word0) + 1, addr, 0))
7760 ? gen_movsi_ie (mem, word0)
7761 : gen_movsi_ie (word0, mem));
7762 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7763 mem = copy_rtx (mem);
7765 ? gen_movsi_ie (mem, word1)
7766 : gen_movsi_ie (word1, mem));
7767 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7771 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7772 emit_insn (gen_movsi_ie (word1, mem));
7773 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7774 mem = copy_rtx (mem);
7775 emit_insn (gen_movsi_ie (word0, mem));
7782 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
7784 [(set (match_operand:DF 0 "register_operand" "")
7785 (match_operand:DF 1 "memory_operand" ""))
7786 (use (match_operand:PSI 2 "fpscr_operand" ""))
7787 (clobber (reg:SI R0_REG))]
7788 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
7789 [(parallel [(set (match_dup 0) (match_dup 1))
7791 (clobber (scratch:SI))])]
7794 (define_expand "reload_indf__frn"
7795 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
7796 (match_operand:DF 1 "immediate_operand" "FQ"))
7797 (use (reg:PSI FPSCR_REG))
7798 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7802 (define_expand "reload_outdf__RnFRm"
7803 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
7804 (match_operand:DF 1 "register_operand" "af,r"))
7805 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
7809 ;; Simplify no-op moves.
7811 [(set (match_operand:SF 0 "register_operand" "")
7812 (match_operand:SF 1 "register_operand" ""))
7813 (use (match_operand:PSI 2 "fpscr_operand" ""))
7814 (clobber (match_scratch:SI 3 ""))]
7815 "TARGET_SH2E && reload_completed
7816 && true_regnum (operands[0]) == true_regnum (operands[1])"
7817 [(set (match_dup 0) (match_dup 0))]
7820 ;; fmovd substitute post-reload splits
7822 [(set (match_operand:DF 0 "register_operand" "")
7823 (match_operand:DF 1 "register_operand" ""))
7824 (use (match_operand:PSI 2 "fpscr_operand" ""))
7825 (clobber (match_scratch:SI 3 ""))]
7826 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
7827 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7828 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7831 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
7832 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
7833 gen_rtx_REG (SFmode, src), operands[2]));
7834 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
7835 gen_rtx_REG (SFmode, src + 1), operands[2]));
7840 [(set (match_operand:DF 0 "register_operand" "")
7841 (mem:DF (match_operand:SI 1 "register_operand" "")))
7842 (use (match_operand:PSI 2 "fpscr_operand" ""))
7843 (clobber (match_scratch:SI 3 ""))]
7844 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7845 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7846 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
7849 int regno = true_regnum (operands[0]);
7851 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
7853 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
7854 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7855 regno + SH_REG_MSW_OFFSET),
7856 mem2, operands[2]));
7857 add_reg_note (insn, REG_INC, operands[1]);
7858 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7859 regno + SH_REG_LSW_OFFSET),
7860 change_address (mem, SFmode, NULL_RTX),
7866 [(set (match_operand:DF 0 "register_operand" "")
7867 (match_operand:DF 1 "memory_operand" ""))
7868 (use (match_operand:PSI 2 "fpscr_operand" ""))
7869 (clobber (match_scratch:SI 3 ""))]
7870 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7871 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
7874 int regno = true_regnum (operands[0]);
7876 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
7877 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7878 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7880 operands[1] = copy_rtx (mem2);
7881 addr = XEXP (mem2, 0);
7883 switch (GET_CODE (addr))
7886 /* This is complicated. If the register is an arithmetic register
7887 we can just fall through to the REG+DISP case below. Otherwise
7888 we have to use a combination of POST_INC and REG addressing... */
7889 if (! arith_reg_operand (operands[1], SFmode))
7891 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
7892 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
7893 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7895 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7897 /* If we have modified the stack pointer, the value that we have
7898 read with post-increment might be modified by an interrupt,
7899 so write it back. */
7900 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
7901 emit_insn (gen_push_e (reg0));
7903 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
7910 emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7911 operands[1] = copy_rtx (operands[1]);
7912 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
7913 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7917 insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7918 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7920 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7921 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7933 [(set (match_operand:DF 0 "memory_operand" "")
7934 (match_operand:DF 1 "register_operand" ""))
7935 (use (match_operand:PSI 2 "fpscr_operand" ""))
7936 (clobber (match_scratch:SI 3 ""))]
7937 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7938 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7941 int regno = true_regnum (operands[1]);
7943 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7944 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7946 operands[0] = copy_rtx (operands[0]);
7947 PUT_MODE (operands[0], SFmode);
7948 addr = XEXP (operands[0], 0);
7950 switch (GET_CODE (addr))
7953 /* This is complicated. If the register is an arithmetic register
7954 we can just fall through to the REG+DISP case below. Otherwise
7955 we have to use a combination of REG and PRE_DEC addressing... */
7956 if (! arith_reg_operand (operands[0], SFmode))
7958 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
7959 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7961 operands[0] = copy_rtx (operands[0]);
7962 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
7964 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7965 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7971 /* Since REG+DISP addressing has already been decided upon by gcc
7972 we can rely upon it having chosen an arithmetic register as the
7973 register component of the address. Just emit the lower numbered
7974 register first, to the lower address, then the higher numbered
7975 register to the higher address. */
7976 emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7978 operands[0] = copy_rtx (operands[0]);
7979 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
7981 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7985 /* This is easy. Output the word to go to the higher address
7986 first (ie the word in the higher numbered register) then the
7987 word to go to the lower address. */
7989 insn = emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7990 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7992 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7993 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8005 ;; If the output is a register and the input is memory or a register, we have
8006 ;; to be careful and see which word needs to be loaded first.
8008 [(set (match_operand:DF 0 "general_movdst_operand" "")
8009 (match_operand:DF 1 "general_movsrc_operand" ""))]
8010 "TARGET_SH1 && reload_completed"
8011 [(set (match_dup 2) (match_dup 3))
8012 (set (match_dup 4) (match_dup 5))]
8016 if ((MEM_P (operands[0])
8017 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
8018 || (MEM_P (operands[1])
8019 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
8022 switch (GET_CODE (operands[0]))
8025 regno = REGNO (operands[0]);
8028 regno = subreg_regno (operands[0]);
8038 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
8040 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
8041 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
8042 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
8043 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
8047 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
8048 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
8049 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
8050 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
8053 if (operands[2] == 0 || operands[3] == 0
8054 || operands[4] == 0 || operands[5] == 0)
8058 (define_expand "movdf"
8059 [(set (match_operand:DF 0 "general_movdst_operand" "")
8060 (match_operand:DF 1 "general_movsrc_operand" ""))]
8063 prepare_move_operands (operands, DFmode);
8066 if (TARGET_SHMEDIA_FPU)
8067 emit_insn (gen_movdf_media (operands[0], operands[1]));
8069 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
8072 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8074 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8079 ;;This is incompatible with the way gcc uses subregs.
8080 ;;(define_insn "movv2sf_i"
8081 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
8082 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
8083 ;; "TARGET_SHMEDIA_FPU
8084 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
8085 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
8089 ;; fst%M0.p %m0, %1"
8090 ;; [(set_attr "type" "*,fload_media,fstore_media")])
8091 (define_insn_and_split "movv2sf_i"
8092 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8093 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8094 "TARGET_SHMEDIA_FPU"
8096 "TARGET_SHMEDIA_FPU && reload_completed"
8097 [(set (match_dup 0) (match_dup 1))]
8099 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
8100 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
8103 (define_expand "movv2sf"
8104 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
8105 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
8106 "TARGET_SHMEDIA_FPU"
8108 prepare_move_operands (operands, V2SFmode);
8111 (define_expand "addv2sf3"
8112 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8113 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8114 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8115 "TARGET_SHMEDIA_FPU"
8117 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8121 (define_expand "subv2sf3"
8122 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8123 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8124 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8125 "TARGET_SHMEDIA_FPU"
8127 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8131 (define_expand "mulv2sf3"
8132 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8133 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8134 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8135 "TARGET_SHMEDIA_FPU"
8137 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8141 (define_expand "divv2sf3"
8142 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8143 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8144 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8145 "TARGET_SHMEDIA_FPU"
8147 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8151 (define_insn_and_split "*movv4sf_i"
8152 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8153 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8154 "TARGET_SHMEDIA_FPU"
8156 "&& reload_completed"
8159 for (int i = 0; i < 4/2; i++)
8163 if (MEM_P (operands[0]))
8164 x = adjust_address (operands[0], V2SFmode,
8165 i * GET_MODE_SIZE (V2SFmode));
8167 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8169 if (MEM_P (operands[1]))
8170 y = adjust_address (operands[1], V2SFmode,
8171 i * GET_MODE_SIZE (V2SFmode));
8173 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8175 emit_insn (gen_movv2sf_i (x, y));
8180 [(set_attr "length" "8")])
8182 (define_expand "movv4sf"
8183 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8184 (match_operand:V4SF 1 "general_operand" ""))]
8185 "TARGET_SHMEDIA_FPU"
8187 prepare_move_operands (operands, V4SFmode);
8190 (define_insn_and_split "*movv16sf_i"
8191 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8192 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8193 "TARGET_SHMEDIA_FPU"
8195 "&& reload_completed"
8198 for (int i = 0; i < 16/2; i++)
8202 if (MEM_P (operands[0]))
8203 x = adjust_address (operands[0], V2SFmode,
8204 i * GET_MODE_SIZE (V2SFmode));
8207 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8208 alter_subreg (&x, true);
8211 if (MEM_P (operands[1]))
8212 y = adjust_address (operands[1], V2SFmode,
8213 i * GET_MODE_SIZE (V2SFmode));
8216 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8217 alter_subreg (&y, true);
8220 emit_insn (gen_movv2sf_i (x, y));
8225 [(set_attr "length" "32")])
8227 (define_expand "movv16sf"
8228 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8229 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8230 "TARGET_SHMEDIA_FPU"
8232 prepare_move_operands (operands, V16SFmode);
8235 (define_insn "movsf_media"
8236 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8237 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8239 && (register_operand (operands[0], SFmode)
8240 || sh_register_operand (operands[1], SFmode))"
8251 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8252 (set (attr "highpart")
8253 (cond [(match_test "sh_contains_memref_p (insn)")
8254 (const_string "user")]
8255 (const_string "ignore")))])
8257 (define_insn "movsf_media_nofpu"
8258 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8259 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8261 && (register_operand (operands[0], SFmode)
8262 || sh_register_operand (operands[1], SFmode))"
8268 [(set_attr "type" "arith_media,*,load_media,store_media")
8269 (set (attr "highpart")
8270 (cond [(match_test "sh_contains_memref_p (insn)")
8271 (const_string "user")]
8272 (const_string "ignore")))])
8275 [(set (match_operand:SF 0 "arith_reg_dest" "")
8276 (match_operand:SF 1 "immediate_operand" ""))]
8277 "TARGET_SHMEDIA && reload_completed
8278 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8279 [(set (match_dup 3) (match_dup 2))]
8282 REAL_VALUE_TYPE value;
8284 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8285 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8286 operands[2] = GEN_INT (values);
8288 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8291 (define_insn "movsf_i"
8292 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8293 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8296 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8297 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8298 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8299 && (arith_reg_operand (operands[0], SFmode)
8300 || arith_reg_operand (operands[1], SFmode))"
8309 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8311 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8312 ;; update_flow_info would not know where to put REG_EQUAL notes
8313 ;; when the destination changes mode.
8314 (define_insn "movsf_ie"
8315 [(set (match_operand:SF 0 "general_movdst_operand"
8316 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8317 (match_operand:SF 1 "general_movsrc_operand"
8318 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8319 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
8320 (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8322 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8323 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8324 || arith_reg_operand (operands[3], SImode))"
8344 ! move optimized away"
8345 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8346 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8347 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8348 (set_attr_alternative "length"
8355 (match_test "TARGET_SH2A")
8356 (const_int 4) (const_int 2))
8358 (match_test "TARGET_SH2A")
8359 (const_int 4) (const_int 2))
8362 (match_test "TARGET_SH2A")
8363 (const_int 4) (const_int 2))
8365 (match_test "TARGET_SH2A")
8366 (const_int 4) (const_int 2))
8376 (set_attr_alternative "fp_mode"
8377 [(if_then_else (eq_attr "fmovd" "yes")
8378 (const_string "single") (const_string "none"))
8379 (const_string "none")
8380 (const_string "single")
8381 (const_string "single")
8382 (const_string "none")
8383 (if_then_else (eq_attr "fmovd" "yes")
8384 (const_string "single") (const_string "none"))
8385 (if_then_else (eq_attr "fmovd" "yes")
8386 (const_string "single") (const_string "none"))
8387 (const_string "none")
8388 (const_string "none")
8389 (const_string "none")
8390 (const_string "none")
8391 (const_string "none")
8392 (const_string "none")
8393 (const_string "none")
8394 (const_string "none")
8395 (const_string "none")
8396 (const_string "none")
8397 (const_string "none")
8398 (const_string "none")])])
8401 [(set (match_operand:SF 0 "register_operand" "")
8402 (match_operand:SF 1 "register_operand" ""))
8403 (use (match_operand:PSI 2 "fpscr_operand" ""))
8404 (clobber (reg:SI FPUL_REG))]
8406 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8408 (clobber (scratch:SI))])
8409 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8411 (clobber (scratch:SI))])]
8414 (define_expand "movsf"
8415 [(set (match_operand:SF 0 "general_movdst_operand" "")
8416 (match_operand:SF 1 "general_movsrc_operand" ""))]
8419 prepare_move_operands (operands, SFmode);
8422 if (TARGET_SHMEDIA_FPU)
8423 emit_insn (gen_movsf_media (operands[0], operands[1]));
8425 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8430 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
8435 (define_insn "mov_nop"
8436 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8439 [(set_attr "length" "0")
8440 (set_attr "type" "nil")])
8442 (define_expand "reload_insf__frn"
8443 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8444 (match_operand:SF 1 "immediate_operand" "FQ"))
8445 (use (reg:PSI FPSCR_REG))
8446 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8450 (define_expand "reload_insi__i_fpul"
8451 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8452 (match_operand:SI 1 "immediate_operand" "i"))
8453 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8457 (define_expand "ptabs"
8458 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8461 if (!TARGET_PT_FIXED)
8463 rtx eq = operands[1];
8465 /* ??? For canonical RTL we really should remove any CONST from EQ
8466 before wrapping it in the AND, and finally wrap the EQ into a
8467 const if is constant. However, for reload we must expose the
8468 input register or symbolic constant, and we can't have
8469 different insn structures outside of the operands for different
8470 alternatives of the same pattern. */
8471 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8474 = (gen_rtx_IF_THEN_ELSE
8477 gen_rtx_MEM (PDImode, operands[1]),
8478 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8479 PDImode, operands[1])));
8483 ;; expanded by ptabs expander.
8484 (define_insn "*extendsipdi_media"
8485 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8486 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8490 (mem:PDI (match_dup 1))
8491 (sign_extend:PDI (match_dup 1))))]
8492 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8496 [(set_attr "type" "ptabs_media,pt_media")
8497 (set_attr "length" "4,*")])
8499 (define_insn "*truncdipdi_media"
8500 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8501 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8505 (mem:PDI (match_dup 1))
8506 (truncate:PDI (match_dup 1))))]
8507 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8511 [(set_attr "type" "ptabs_media,pt_media")
8512 (set_attr "length" "4,*")])
8514 (define_insn "*movsi_y"
8515 [(set (match_operand:SI 0 "register_operand" "=y,y")
8516 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8517 (clobber (match_scratch:SI 2 "=&z,r"))]
8519 && (reload_in_progress || reload_completed)"
8521 [(set_attr "length" "4")
8522 (set_attr "type" "pcload,move")])
8525 [(set (match_operand:SI 0 "register_operand" "")
8526 (match_operand:SI 1 "immediate_operand" ""))
8527 (clobber (match_operand:SI 2 "register_operand" ""))]
8529 [(set (match_dup 2) (match_dup 1))
8530 (set (match_dup 0) (match_dup 2))]
8533 ;; ------------------------------------------------------------------------
8534 ;; Define the real conditional branch instructions.
8535 ;; ------------------------------------------------------------------------
8537 (define_expand "branch_true"
8538 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
8539 (label_ref (match_operand 0))
8543 (define_expand "branch_false"
8544 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8545 (label_ref (match_operand 0))
8549 (define_insn_and_split "*cbranch_t"
8550 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
8551 (label_ref (match_operand 0))
8555 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
8560 /* Try to canonicalize the branch condition if it is not one of:
8561 (ne (reg:SI T_REG) (const_int 0))
8562 (eq (reg:SI T_REG) (const_int 0))
8564 Instead of splitting out a new insn, we modify the current insn's
8565 operands as needed. This preserves things such as REG_DEAD notes. */
8567 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
8568 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
8569 && XEXP (operands[1], 1) == const0_rtx)
8572 int branch_cond = sh_eval_treg_value (operands[1]);
8573 rtx new_cond_rtx = NULL_RTX;
8575 if (branch_cond == 0)
8576 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
8577 else if (branch_cond == 1)
8578 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
8580 if (new_cond_rtx != NULL_RTX)
8581 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
8582 new_cond_rtx, false);
8585 [(set_attr "type" "cbranch")])
8587 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
8588 ;; which destination is too far away.
8589 ;; The const_int_operand is distinct for each branch target; it avoids
8590 ;; unwanted matches with redundant_insn.
8591 (define_insn "block_branch_redirect"
8592 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
8595 [(set_attr "length" "0")])
8597 ;; This one has the additional purpose to record a possible scratch register
8598 ;; for the following branch.
8599 ;; ??? Unfortunately, just setting the scratch register is not good enough,
8600 ;; because the insn then might be deemed dead and deleted. And we can't
8601 ;; make the use in the jump insn explicit because that would disable
8602 ;; delay slot scheduling from the target.
8603 (define_insn "indirect_jump_scratch"
8604 [(set (match_operand:SI 0 "register_operand" "=r")
8605 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
8606 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
8609 [(set_attr "length" "0")])
8611 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
8612 ;; being pulled into the delay slot of a condbranch that has been made to
8613 ;; jump around the unconditional jump because it was out of range.
8614 (define_insn "stuff_delay_slot"
8616 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
8617 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
8620 [(set_attr "length" "0")
8621 (set_attr "cond_delay_slot" "yes")])
8623 ;; Conditional branch insns
8625 (define_expand "cbranchint4_media"
8627 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
8628 [(match_operand 1 "" "")
8629 (match_operand 2 "" "")])
8630 (match_operand 3 "" "")
8634 enum machine_mode mode = GET_MODE (operands[1]);
8635 if (mode == VOIDmode)
8636 mode = GET_MODE (operands[2]);
8637 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
8639 operands[1] = force_reg (mode, operands[1]);
8640 if (CONSTANT_P (operands[2])
8641 && (! satisfies_constraint_I06 (operands[2])))
8642 operands[2] = force_reg (mode, operands[2]);
8646 if (operands[1] != const0_rtx)
8647 operands[1] = force_reg (mode, operands[1]);
8648 if (operands[2] != const0_rtx)
8649 operands[2] = force_reg (mode, operands[2]);
8651 switch (GET_CODE (operands[0]))
8657 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
8658 VOIDmode, operands[2], operands[1]);
8659 operands[1] = XEXP (operands[0], 0);
8660 operands[2] = XEXP (operands[0], 1);
8663 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
8664 VOIDmode, operands[1], operands[2]);
8667 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8670 (define_expand "cbranchfp4_media"
8672 (if_then_else (match_operator 0 "sh_float_comparison_operator"
8673 [(match_operand 1 "" "")
8674 (match_operand 2 "" "")])
8675 (match_operand 3 "" "")
8679 rtx tmp = gen_reg_rtx (SImode);
8681 if (GET_CODE (operands[0]) == NE)
8682 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
8684 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
8685 operands[1], operands[2]);
8687 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
8689 if (GET_CODE (cmp) == GET_CODE (operands[0]))
8690 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
8692 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8694 operands[2] = const0_rtx;
8695 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8698 (define_insn "*beq_media_i"
8700 (if_then_else (match_operator 3 "equality_comparison_operator"
8701 [(match_operand:DI 1 "arith_reg_operand" "r,r")
8702 (match_operand:DI 2 "arith_operand" "r,I06")])
8703 (match_operand 0 "target_operand" "b,b")
8708 b%o3i%' %1, %2, %0%>"
8709 [(set_attr "type" "cbranch_media")])
8711 (define_insn "*beq_media_i32"
8713 (if_then_else (match_operator 3 "equality_comparison_operator"
8714 [(match_operand:SI 1 "arith_reg_operand" "r,r")
8715 (match_operand:SI 2 "arith_operand" "r,I06")])
8716 (match_operand 0 "target_operand" "b,b")
8721 b%o3i%' %1, %2, %0%>"
8722 [(set_attr "type" "cbranch_media")])
8724 (define_insn "*bgt_media_i"
8726 (if_then_else (match_operator 3 "greater_comparison_operator"
8727 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8728 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8729 (match_operand 0 "target_operand" "b")
8732 "b%o3%' %N1, %N2, %0%>"
8733 [(set_attr "type" "cbranch_media")])
8735 (define_insn "*bgt_media_i32"
8737 (if_then_else (match_operator 3 "greater_comparison_operator"
8738 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8739 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8740 (match_operand 0 "target_operand" "b")
8743 "b%o3%' %N1, %N2, %0%>"
8744 [(set_attr "type" "cbranch_media")])
8746 ;; These are only needed to make invert_jump() happy - otherwise, jump
8747 ;; optimization will be silently disabled.
8748 (define_insn "*blt_media_i"
8750 (if_then_else (match_operator 3 "less_comparison_operator"
8751 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8752 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8753 (match_operand 0 "target_operand" "b")
8756 "b%o3%' %N2, %N1, %0%>"
8757 [(set_attr "type" "cbranch_media")])
8759 (define_insn "*blt_media_i32"
8761 (if_then_else (match_operator 3 "less_comparison_operator"
8762 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8763 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8764 (match_operand 0 "target_operand" "b")
8767 "b%o3%' %N2, %N1, %0%>"
8768 [(set_attr "type" "cbranch_media")])
8770 ;; combiner splitter for test-and-branch on single bit in register. This
8771 ;; is endian dependent because the non-paradoxical subreg looks different
8776 (match_operator 3 "equality_comparison_operator"
8779 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
8781 (match_operand 2 "const_int_operand" "")) 0)
8783 (match_operand 0 "target_operand" "")
8785 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
8786 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
8787 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
8788 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
8790 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
8791 operands[6] = (GET_CODE (operands[3]) == EQ
8792 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
8793 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
8796 ; operand 0 is the loop count pseudo register
8797 ; operand 1 is the label to jump to at the top of the loop
8798 (define_expand "doloop_end"
8799 [(parallel [(set (pc)
8800 (if_then_else (ne:SI (match_operand:SI 0 "" "")
8802 (label_ref (match_operand 1 "" ""))
8805 (plus:SI (match_dup 0) (const_int -1)))
8806 (clobber (reg:SI T_REG))])]
8809 if (GET_MODE (operands[0]) != SImode)
8811 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
8815 (define_insn_and_split "doloop_end_split"
8817 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
8819 (label_ref (match_operand 1 "" ""))
8821 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8822 (plus:SI (match_dup 2) (const_int -1)))
8823 (clobber (reg:SI T_REG))]
8827 [(parallel [(set (reg:SI T_REG)
8828 (eq:SI (match_dup 2) (const_int 1)))
8829 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
8830 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8831 (label_ref (match_dup 1))
8834 [(set_attr "type" "cbranch")])
8836 ;; ------------------------------------------------------------------------
8837 ;; Jump and linkage insns
8838 ;; ------------------------------------------------------------------------
8840 (define_insn "jump_compact"
8842 (label_ref (match_operand 0 "" "")))]
8843 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
8845 /* The length is 16 if the delay slot is unfilled. */
8846 if (get_attr_length(insn) > 4)
8847 return output_far_jump(insn, operands[0]);
8851 [(set_attr "type" "jump")
8852 (set_attr "needs_delay_slot" "yes")])
8854 ;; ??? It would be much saner to explicitly use the scratch register
8855 ;; in the jump insn, and have indirect_jump_scratch only set it,
8856 ;; but fill_simple_delay_slots would refuse to do delay slot filling
8857 ;; from the target then, as it uses simplejump_p.
8858 ;;(define_insn "jump_compact_far"
8860 ;; (label_ref (match_operand 0 "" "")))
8861 ;; (use (match_operand 1 "register_operand" "r")]
8863 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
8864 ;; [(set_attr "type" "jump")
8865 ;; (set_attr "needs_delay_slot" "yes")])
8867 (define_insn "jump_media"
8869 (match_operand 0 "target_operand" "b"))]
8872 [(set_attr "type" "jump_media")])
8874 (define_expand "jump"
8876 (label_ref (match_operand 0 "" "")))]
8880 emit_jump_insn (gen_jump_compact (operands[0]));
8881 else if (TARGET_SHMEDIA)
8883 if (reload_in_progress || reload_completed)
8885 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
8890 (define_insn "force_mode_for_call"
8891 [(use (reg:PSI FPSCR_REG))]
8894 [(set_attr "length" "0")
8895 (set (attr "fp_mode")
8896 (if_then_else (eq_attr "fpu_single" "yes")
8897 (const_string "single") (const_string "double")))])
8899 (define_insn "calli"
8900 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8901 (match_operand 1 "" ""))
8902 (use (reg:PSI FPSCR_REG))
8903 (clobber (reg:SI PR_REG))]
8906 if (TARGET_SH2A && (dbr_sequence_length () == 0))
8911 [(set_attr "type" "call")
8912 (set (attr "fp_mode")
8913 (if_then_else (eq_attr "fpu_single" "yes")
8914 (const_string "single") (const_string "double")))
8915 (set_attr "needs_delay_slot" "yes")
8916 (set_attr "fp_set" "unknown")])
8918 ;; This is TBR relative jump instruction for SH2A architecture.
8919 ;; Its use is enabled by assigning an attribute "function_vector"
8920 ;; and the vector number to a function during its declaration.
8921 (define_insn "calli_tbr_rel"
8922 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
8923 (match_operand 1 "" ""))
8924 (use (reg:PSI FPSCR_REG))
8925 (clobber (reg:SI PR_REG))]
8926 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
8928 unsigned HOST_WIDE_INT vect_num;
8929 vect_num = sh2a_get_function_vector_number (operands[0]);
8930 operands[2] = GEN_INT (vect_num * 4);
8932 return "jsr/n @@(%O2,tbr)";
8934 [(set_attr "type" "call")
8935 (set (attr "fp_mode")
8936 (if_then_else (eq_attr "fpu_single" "yes")
8937 (const_string "single") (const_string "double")))
8938 (set_attr "needs_delay_slot" "no")
8939 (set_attr "fp_set" "unknown")])
8941 ;; This is a pc-rel call, using bsrf, for use with PIC.
8942 (define_insn "calli_pcrel"
8943 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8944 (match_operand 1 "" ""))
8945 (use (reg:PSI FPSCR_REG))
8946 (use (reg:SI PIC_REG))
8947 (use (match_operand 2 "" ""))
8948 (clobber (reg:SI PR_REG))]
8951 return "bsrf %0" "\n"
8954 [(set_attr "type" "call")
8955 (set (attr "fp_mode")
8956 (if_then_else (eq_attr "fpu_single" "yes")
8957 (const_string "single") (const_string "double")))
8958 (set_attr "needs_delay_slot" "yes")
8959 (set_attr "fp_set" "unknown")])
8961 (define_insn_and_split "call_pcrel"
8962 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
8963 (match_operand 1 "" ""))
8964 (use (reg:PSI FPSCR_REG))
8965 (use (reg:SI PIC_REG))
8966 (clobber (reg:SI PR_REG))
8967 (clobber (match_scratch:SI 2 "=r"))]
8973 rtx lab = PATTERN (gen_call_site ());
8975 if (SYMBOL_REF_LOCAL_P (operands[0]))
8976 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
8978 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
8979 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
8982 [(set_attr "type" "call")
8983 (set (attr "fp_mode")
8984 (if_then_else (eq_attr "fpu_single" "yes")
8985 (const_string "single") (const_string "double")))
8986 (set_attr "needs_delay_slot" "yes")
8987 (set_attr "fp_set" "unknown")])
8989 (define_insn "call_compact"
8990 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8991 (match_operand 1 "" ""))
8992 (match_operand 2 "immediate_operand" "n")
8993 (use (reg:SI R0_REG))
8994 (use (reg:SI R1_REG))
8995 (use (reg:PSI FPSCR_REG))
8996 (clobber (reg:SI PR_REG))]
8997 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
8999 [(set_attr "type" "call")
9000 (set (attr "fp_mode")
9001 (if_then_else (eq_attr "fpu_single" "yes")
9002 (const_string "single") (const_string "double")))
9003 (set_attr "needs_delay_slot" "yes")])
9005 (define_insn "call_compact_rettramp"
9006 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9007 (match_operand 1 "" ""))
9008 (match_operand 2 "immediate_operand" "n")
9009 (use (reg:SI R0_REG))
9010 (use (reg:SI R1_REG))
9011 (use (reg:PSI FPSCR_REG))
9012 (clobber (reg:SI R10_REG))
9013 (clobber (reg:SI PR_REG))]
9014 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9016 [(set_attr "type" "call")
9017 (set (attr "fp_mode")
9018 (if_then_else (eq_attr "fpu_single" "yes")
9019 (const_string "single") (const_string "double")))
9020 (set_attr "needs_delay_slot" "yes")])
9022 (define_insn "call_media"
9023 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
9024 (match_operand 1 "" ""))
9025 (clobber (reg:DI PR_MEDIA_REG))]
9028 [(set_attr "type" "jump_media")])
9030 (define_insn "call_valuei"
9031 [(set (match_operand 0 "" "=rf")
9032 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9033 (match_operand 2 "" "")))
9034 (use (reg:PSI FPSCR_REG))
9035 (clobber (reg:SI PR_REG))]
9038 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9043 [(set_attr "type" "call")
9044 (set (attr "fp_mode")
9045 (if_then_else (eq_attr "fpu_single" "yes")
9046 (const_string "single") (const_string "double")))
9047 (set_attr "needs_delay_slot" "yes")
9048 (set_attr "fp_set" "unknown")])
9050 ;; This is TBR relative jump instruction for SH2A architecture.
9051 ;; Its use is enabled by assigning an attribute "function_vector"
9052 ;; and the vector number to a function during its declaration.
9053 (define_insn "call_valuei_tbr_rel"
9054 [(set (match_operand 0 "" "=rf")
9055 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9056 (match_operand 2 "" "")))
9057 (use (reg:PSI FPSCR_REG))
9058 (clobber (reg:SI PR_REG))]
9059 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
9061 unsigned HOST_WIDE_INT vect_num;
9062 vect_num = sh2a_get_function_vector_number (operands[1]);
9063 operands[3] = GEN_INT (vect_num * 4);
9065 return "jsr/n @@(%O3,tbr)";
9067 [(set_attr "type" "call")
9068 (set (attr "fp_mode")
9069 (if_then_else (eq_attr "fpu_single" "yes")
9070 (const_string "single") (const_string "double")))
9071 (set_attr "needs_delay_slot" "no")
9072 (set_attr "fp_set" "unknown")])
9074 (define_insn "call_valuei_pcrel"
9075 [(set (match_operand 0 "" "=rf")
9076 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9077 (match_operand 2 "" "")))
9078 (use (reg:PSI FPSCR_REG))
9079 (use (reg:SI PIC_REG))
9080 (use (match_operand 3 "" ""))
9081 (clobber (reg:SI PR_REG))]
9084 return "bsrf %1" "\n"
9087 [(set_attr "type" "call")
9088 (set (attr "fp_mode")
9089 (if_then_else (eq_attr "fpu_single" "yes")
9090 (const_string "single") (const_string "double")))
9091 (set_attr "needs_delay_slot" "yes")
9092 (set_attr "fp_set" "unknown")])
9094 (define_insn_and_split "call_value_pcrel"
9095 [(set (match_operand 0 "" "=rf")
9096 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9097 (match_operand 2 "" "")))
9098 (use (reg:PSI FPSCR_REG))
9099 (use (reg:SI PIC_REG))
9100 (clobber (reg:SI PR_REG))
9101 (clobber (match_scratch:SI 3 "=r"))]
9107 rtx lab = PATTERN (gen_call_site ());
9109 if (SYMBOL_REF_LOCAL_P (operands[1]))
9110 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9112 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9113 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9114 operands[2], copy_rtx (lab)));
9117 [(set_attr "type" "call")
9118 (set (attr "fp_mode")
9119 (if_then_else (eq_attr "fpu_single" "yes")
9120 (const_string "single") (const_string "double")))
9121 (set_attr "needs_delay_slot" "yes")
9122 (set_attr "fp_set" "unknown")])
9124 (define_insn "call_value_compact"
9125 [(set (match_operand 0 "" "=rf")
9126 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9127 (match_operand 2 "" "")))
9128 (match_operand 3 "immediate_operand" "n")
9129 (use (reg:SI R0_REG))
9130 (use (reg:SI R1_REG))
9131 (use (reg:PSI FPSCR_REG))
9132 (clobber (reg:SI PR_REG))]
9133 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9135 [(set_attr "type" "call")
9136 (set (attr "fp_mode")
9137 (if_then_else (eq_attr "fpu_single" "yes")
9138 (const_string "single") (const_string "double")))
9139 (set_attr "needs_delay_slot" "yes")])
9141 (define_insn "call_value_compact_rettramp"
9142 [(set (match_operand 0 "" "=rf")
9143 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9144 (match_operand 2 "" "")))
9145 (match_operand 3 "immediate_operand" "n")
9146 (use (reg:SI R0_REG))
9147 (use (reg:SI R1_REG))
9148 (use (reg:PSI FPSCR_REG))
9149 (clobber (reg:SI R10_REG))
9150 (clobber (reg:SI PR_REG))]
9151 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9153 [(set_attr "type" "call")
9154 (set (attr "fp_mode")
9155 (if_then_else (eq_attr "fpu_single" "yes")
9156 (const_string "single") (const_string "double")))
9157 (set_attr "needs_delay_slot" "yes")])
9159 (define_insn "call_value_media"
9160 [(set (match_operand 0 "" "=rf")
9161 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9162 (match_operand 2 "" "")))
9163 (clobber (reg:DI PR_MEDIA_REG))]
9166 [(set_attr "type" "jump_media")])
9168 (define_expand "call"
9169 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9170 (match_operand 1 "" ""))
9171 (match_operand 2 "" "")
9172 (use (reg:PSI FPSCR_REG))
9173 (clobber (reg:SI PR_REG))])]
9178 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9179 emit_call_insn (gen_call_media (operands[0], operands[1]));
9182 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9184 rtx cookie_rtx = operands[2];
9185 long cookie = INTVAL (cookie_rtx);
9186 rtx func = XEXP (operands[0], 0);
9191 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9193 rtx reg = gen_reg_rtx (Pmode);
9195 emit_insn (gen_symGOTPLT2reg (reg, func));
9199 func = legitimize_pic_address (func, Pmode, 0);
9202 r0 = gen_rtx_REG (SImode, R0_REG);
9203 r1 = gen_rtx_REG (SImode, R1_REG);
9205 /* Since such a call function may use all call-clobbered
9206 registers, we force a mode switch earlier, so that we don't
9207 run out of registers when adjusting fpscr for the call. */
9208 emit_insn (gen_force_mode_for_call ());
9211 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9212 operands[0] = force_reg (SImode, operands[0]);
9214 emit_move_insn (r0, func);
9215 emit_move_insn (r1, cookie_rtx);
9217 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9218 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9221 emit_call_insn (gen_call_compact (operands[0], operands[1],
9226 else if (TARGET_SHCOMPACT && flag_pic
9227 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9228 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9230 rtx reg = gen_reg_rtx (Pmode);
9232 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9233 XEXP (operands[0], 0) = reg;
9235 if (!flag_pic && TARGET_SH2A
9236 && MEM_P (operands[0])
9237 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9239 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9241 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9246 if (flag_pic && TARGET_SH2
9247 && MEM_P (operands[0])
9248 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9250 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9255 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9256 operands[1] = operands[2];
9259 emit_call_insn (gen_calli (operands[0], operands[1]));
9263 (define_insn "call_pop_compact"
9264 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9265 (match_operand 1 "" ""))
9266 (match_operand 2 "immediate_operand" "n")
9267 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9268 (match_operand 3 "immediate_operand" "n")))
9269 (use (reg:SI R0_REG))
9270 (use (reg:SI R1_REG))
9271 (use (reg:PSI FPSCR_REG))
9272 (clobber (reg:SI PR_REG))]
9273 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9275 [(set_attr "type" "call")
9276 (set (attr "fp_mode")
9277 (if_then_else (eq_attr "fpu_single" "yes")
9278 (const_string "single") (const_string "double")))
9279 (set_attr "needs_delay_slot" "yes")])
9281 (define_insn "call_pop_compact_rettramp"
9282 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9283 (match_operand 1 "" ""))
9284 (match_operand 2 "immediate_operand" "n")
9285 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9286 (match_operand 3 "immediate_operand" "n")))
9287 (use (reg:SI R0_REG))
9288 (use (reg:SI R1_REG))
9289 (use (reg:PSI FPSCR_REG))
9290 (clobber (reg:SI R10_REG))
9291 (clobber (reg:SI PR_REG))]
9292 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9294 [(set_attr "type" "call")
9295 (set (attr "fp_mode")
9296 (if_then_else (eq_attr "fpu_single" "yes")
9297 (const_string "single") (const_string "double")))
9298 (set_attr "needs_delay_slot" "yes")])
9300 (define_expand "call_pop"
9301 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9302 (match_operand 1 "" ""))
9303 (match_operand 2 "" "")
9304 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9305 (match_operand 3 "" "")))])]
9313 gcc_assert (operands[2] && INTVAL (operands[2]));
9314 cookie_rtx = operands[2];
9315 cookie = INTVAL (cookie_rtx);
9316 func = XEXP (operands[0], 0);
9320 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9322 rtx reg = gen_reg_rtx (Pmode);
9323 emit_insn (gen_symGOTPLT2reg (reg, func));
9327 func = legitimize_pic_address (func, Pmode, 0);
9330 r0 = gen_rtx_REG (SImode, R0_REG);
9331 r1 = gen_rtx_REG (SImode, R1_REG);
9333 /* Since such a call function may use all call-clobbered
9334 registers, we force a mode switch earlier, so that we don't
9335 run out of registers when adjusting fpscr for the call. */
9336 emit_insn (gen_force_mode_for_call ());
9338 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9340 operands[0] = force_reg (SImode, operands[0]);
9342 emit_move_insn (r0, func);
9343 emit_move_insn (r1, cookie_rtx);
9345 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9346 emit_call_insn (gen_call_pop_compact_rettramp
9347 (operands[0], operands[1], operands[2], operands[3]));
9349 emit_call_insn (gen_call_pop_compact
9350 (operands[0], operands[1], operands[2], operands[3]));
9355 (define_expand "call_value"
9356 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9357 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9358 (match_operand 2 "" "")))
9359 (match_operand 3 "" "")
9360 (use (reg:PSI FPSCR_REG))
9361 (clobber (reg:SI PR_REG))])]
9366 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9367 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9371 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9373 rtx cookie_rtx = operands[3];
9374 long cookie = INTVAL (cookie_rtx);
9375 rtx func = XEXP (operands[1], 0);
9380 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9382 rtx reg = gen_reg_rtx (Pmode);
9384 emit_insn (gen_symGOTPLT2reg (reg, func));
9388 func = legitimize_pic_address (func, Pmode, 0);
9391 r0 = gen_rtx_REG (SImode, R0_REG);
9392 r1 = gen_rtx_REG (SImode, R1_REG);
9394 /* Since such a call function may use all call-clobbered
9395 registers, we force a mode switch earlier, so that we don't
9396 run out of registers when adjusting fpscr for the call. */
9397 emit_insn (gen_force_mode_for_call ());
9400 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9401 operands[1] = force_reg (SImode, operands[1]);
9403 emit_move_insn (r0, func);
9404 emit_move_insn (r1, cookie_rtx);
9406 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9407 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9412 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9413 operands[2], operands[3]));
9417 else if (TARGET_SHCOMPACT && flag_pic
9418 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9419 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9421 rtx reg = gen_reg_rtx (Pmode);
9423 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9424 XEXP (operands[1], 0) = reg;
9426 if (!flag_pic && TARGET_SH2A
9427 && MEM_P (operands[1])
9428 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9430 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9432 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9433 XEXP (operands[1], 0), operands[2]));
9437 if (flag_pic && TARGET_SH2
9438 && MEM_P (operands[1])
9439 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9441 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9446 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9448 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9452 (define_insn "sibcalli"
9453 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9454 (match_operand 1 "" ""))
9455 (use (reg:PSI FPSCR_REG))
9459 [(set_attr "needs_delay_slot" "yes")
9460 (set (attr "fp_mode")
9461 (if_then_else (eq_attr "fpu_single" "yes")
9462 (const_string "single") (const_string "double")))
9463 (set_attr "type" "jump_ind")])
9465 (define_insn "sibcalli_pcrel"
9466 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9467 (match_operand 1 "" ""))
9468 (use (match_operand 2 "" ""))
9469 (use (reg:PSI FPSCR_REG))
9473 return "braf %0" "\n"
9476 [(set_attr "needs_delay_slot" "yes")
9477 (set (attr "fp_mode")
9478 (if_then_else (eq_attr "fpu_single" "yes")
9479 (const_string "single") (const_string "double")))
9480 (set_attr "type" "jump_ind")])
9482 ;; This uses an unspec to describe that the symbol_ref is very close.
9483 (define_insn "sibcalli_thunk"
9484 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9486 (match_operand 1 "" ""))
9487 (use (reg:PSI FPSCR_REG))
9491 [(set_attr "needs_delay_slot" "yes")
9492 (set (attr "fp_mode")
9493 (if_then_else (eq_attr "fpu_single" "yes")
9494 (const_string "single") (const_string "double")))
9495 (set_attr "type" "jump")
9496 (set_attr "length" "2")])
9498 (define_insn_and_split "sibcall_pcrel"
9499 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9500 (match_operand 1 "" ""))
9501 (use (reg:PSI FPSCR_REG))
9502 (clobber (match_scratch:SI 2 "=k"))
9509 rtx lab = PATTERN (gen_call_site ());
9512 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9513 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9515 SIBLING_CALL_P (call_insn) = 1;
9518 [(set_attr "needs_delay_slot" "yes")
9519 (set (attr "fp_mode")
9520 (if_then_else (eq_attr "fpu_single" "yes")
9521 (const_string "single") (const_string "double")))
9522 (set_attr "type" "jump_ind")])
9524 (define_insn "sibcall_compact"
9525 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
9526 (match_operand 1 "" ""))
9528 (use (match_operand:SI 2 "register_operand" "z,x"))
9529 (use (reg:SI R1_REG))
9530 (use (reg:PSI FPSCR_REG))
9531 ;; We want to make sure the `x' above will only match MACH_REG
9532 ;; because sibcall_epilogue may clobber MACL_REG.
9533 (clobber (reg:SI MACL_REG))]
9536 static const char* alt[] =
9543 return alt[which_alternative];
9545 [(set_attr "needs_delay_slot" "yes,no")
9546 (set_attr "length" "2,4")
9547 (set (attr "fp_mode") (const_string "single"))
9548 (set_attr "type" "jump_ind")])
9550 (define_insn "sibcall_media"
9551 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
9552 (match_operand 1 "" ""))
9553 (use (reg:SI PR_MEDIA_REG))
9557 [(set_attr "type" "jump_media")])
9559 (define_expand "sibcall"
9561 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9562 (match_operand 1 "" ""))
9563 (match_operand 2 "" "")
9564 (use (reg:PSI FPSCR_REG))
9570 operands[0] = shmedia_prepare_call_address (operands[0], 1);
9571 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
9574 else if (TARGET_SHCOMPACT && operands[2]
9575 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9577 rtx cookie_rtx = operands[2];
9578 long cookie = INTVAL (cookie_rtx);
9579 rtx func = XEXP (operands[0], 0);
9584 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9586 rtx reg = gen_reg_rtx (Pmode);
9588 emit_insn (gen_symGOT2reg (reg, func));
9592 func = legitimize_pic_address (func, Pmode, 0);
9595 /* FIXME: if we could tell whether all argument registers are
9596 already taken, we could decide whether to force the use of
9597 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9598 simple way to tell. We could use the CALL_COOKIE, but we
9599 can't currently tell a register used for regular argument
9600 passing from one that is unused. If we leave it up to reload
9601 to decide which register to use, it seems to always choose
9602 R0_REG, which leaves no available registers in SIBCALL_REGS
9603 to hold the address of the trampoline. */
9604 mach = gen_rtx_REG (SImode, MACH_REG);
9605 r1 = gen_rtx_REG (SImode, R1_REG);
9607 /* Since such a call function may use all call-clobbered
9608 registers, we force a mode switch earlier, so that we don't
9609 run out of registers when adjusting fpscr for the call. */
9610 emit_insn (gen_force_mode_for_call ());
9613 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9614 operands[0] = force_reg (SImode, operands[0]);
9616 /* We don't need a return trampoline, since the callee will
9617 return directly to the upper caller. */
9618 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9620 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9621 cookie_rtx = GEN_INT (cookie);
9624 emit_move_insn (mach, func);
9625 emit_move_insn (r1, cookie_rtx);
9627 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
9630 else if (TARGET_SHCOMPACT && flag_pic
9631 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9632 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9634 rtx reg = gen_reg_rtx (Pmode);
9636 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
9637 XEXP (operands[0], 0) = reg;
9639 if (flag_pic && TARGET_SH2
9640 && MEM_P (operands[0])
9641 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9642 /* The PLT needs the PIC register, but the epilogue would have
9643 to restore it, so we can only use PC-relative PIC calls for
9644 static functions. */
9645 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9647 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
9651 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9653 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
9657 (define_insn "sibcall_valuei"
9658 [(set (match_operand 0 "" "=rf")
9659 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
9660 (match_operand 2 "" "")))
9661 (use (reg:PSI FPSCR_REG))
9665 [(set_attr "needs_delay_slot" "yes")
9666 (set (attr "fp_mode")
9667 (if_then_else (eq_attr "fpu_single" "yes")
9668 (const_string "single") (const_string "double")))
9669 (set_attr "type" "jump_ind")])
9671 (define_insn "sibcall_valuei_pcrel"
9672 [(set (match_operand 0 "" "=rf")
9673 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
9674 (match_operand 2 "" "")))
9675 (use (match_operand 3 "" ""))
9676 (use (reg:PSI FPSCR_REG))
9680 return "braf %1" "\n"
9683 [(set_attr "needs_delay_slot" "yes")
9684 (set (attr "fp_mode")
9685 (if_then_else (eq_attr "fpu_single" "yes")
9686 (const_string "single") (const_string "double")))
9687 (set_attr "type" "jump_ind")])
9689 (define_insn_and_split "sibcall_value_pcrel"
9690 [(set (match_operand 0 "" "=rf")
9691 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9692 (match_operand 2 "" "")))
9693 (use (reg:PSI FPSCR_REG))
9694 (clobber (match_scratch:SI 3 "=k"))
9701 rtx lab = PATTERN (gen_call_site ());
9704 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9705 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
9709 SIBLING_CALL_P (call_insn) = 1;
9712 [(set_attr "needs_delay_slot" "yes")
9713 (set (attr "fp_mode")
9714 (if_then_else (eq_attr "fpu_single" "yes")
9715 (const_string "single") (const_string "double")))
9716 (set_attr "type" "jump_ind")])
9718 (define_insn "sibcall_value_compact"
9719 [(set (match_operand 0 "" "=rf,rf")
9720 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
9721 (match_operand 2 "" "")))
9723 (use (match_operand:SI 3 "register_operand" "z,x"))
9724 (use (reg:SI R1_REG))
9725 (use (reg:PSI FPSCR_REG))
9726 ;; We want to make sure the `x' above will only match MACH_REG
9727 ;; because sibcall_epilogue may clobber MACL_REG.
9728 (clobber (reg:SI MACL_REG))]
9731 static const char* alt[] =
9738 return alt[which_alternative];
9740 [(set_attr "needs_delay_slot" "yes,no")
9741 (set_attr "length" "2,4")
9742 (set (attr "fp_mode") (const_string "single"))
9743 (set_attr "type" "jump_ind")])
9745 (define_insn "sibcall_value_media"
9746 [(set (match_operand 0 "" "=rf")
9747 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
9748 (match_operand 2 "" "")))
9749 (use (reg:SI PR_MEDIA_REG))
9753 [(set_attr "type" "jump_media")])
9755 (define_expand "sibcall_value"
9757 [(set (match_operand 0 "arith_reg_operand" "")
9758 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9759 (match_operand 2 "" "")))
9760 (match_operand 3 "" "")
9761 (use (reg:PSI FPSCR_REG))
9767 operands[1] = shmedia_prepare_call_address (operands[1], 1);
9768 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
9772 else if (TARGET_SHCOMPACT && operands[3]
9773 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9775 rtx cookie_rtx = operands[3];
9776 long cookie = INTVAL (cookie_rtx);
9777 rtx func = XEXP (operands[1], 0);
9782 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9784 rtx reg = gen_reg_rtx (Pmode);
9786 emit_insn (gen_symGOT2reg (reg, func));
9790 func = legitimize_pic_address (func, Pmode, 0);
9793 /* FIXME: if we could tell whether all argument registers are
9794 already taken, we could decide whether to force the use of
9795 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9796 simple way to tell. We could use the CALL_COOKIE, but we
9797 can't currently tell a register used for regular argument
9798 passing from one that is unused. If we leave it up to reload
9799 to decide which register to use, it seems to always choose
9800 R0_REG, which leaves no available registers in SIBCALL_REGS
9801 to hold the address of the trampoline. */
9802 mach = gen_rtx_REG (SImode, MACH_REG);
9803 r1 = gen_rtx_REG (SImode, R1_REG);
9805 /* Since such a call function may use all call-clobbered
9806 registers, we force a mode switch earlier, so that we don't
9807 run out of registers when adjusting fpscr for the call. */
9808 emit_insn (gen_force_mode_for_call ());
9811 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9812 operands[1] = force_reg (SImode, operands[1]);
9814 /* We don't need a return trampoline, since the callee will
9815 return directly to the upper caller. */
9816 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9818 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9819 cookie_rtx = GEN_INT (cookie);
9822 emit_move_insn (mach, func);
9823 emit_move_insn (r1, cookie_rtx);
9825 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
9826 operands[2], mach));
9829 else if (TARGET_SHCOMPACT && flag_pic
9830 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9831 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9833 rtx reg = gen_reg_rtx (Pmode);
9835 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
9836 XEXP (operands[1], 0) = reg;
9838 if (flag_pic && TARGET_SH2
9839 && MEM_P (operands[1])
9840 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9841 /* The PLT needs the PIC register, but the epilogue would have
9842 to restore it, so we can only use PC-relative PIC calls for
9843 static functions. */
9844 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9846 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
9847 XEXP (operands[1], 0),
9852 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9854 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
9858 (define_insn "call_value_pop_compact"
9859 [(set (match_operand 0 "" "=rf")
9860 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9861 (match_operand 2 "" "")))
9862 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9863 (match_operand 4 "immediate_operand" "n")))
9864 (match_operand 3 "immediate_operand" "n")
9865 (use (reg:SI R0_REG))
9866 (use (reg:SI R1_REG))
9867 (use (reg:PSI FPSCR_REG))
9868 (clobber (reg:SI PR_REG))]
9869 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9871 [(set_attr "type" "call")
9872 (set (attr "fp_mode")
9873 (if_then_else (eq_attr "fpu_single" "yes")
9874 (const_string "single") (const_string "double")))
9875 (set_attr "needs_delay_slot" "yes")])
9877 (define_insn "call_value_pop_compact_rettramp"
9878 [(set (match_operand 0 "" "=rf")
9879 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9880 (match_operand 2 "" "")))
9881 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9882 (match_operand 4 "immediate_operand" "n")))
9883 (match_operand 3 "immediate_operand" "n")
9884 (use (reg:SI R0_REG))
9885 (use (reg:SI R1_REG))
9886 (use (reg:PSI FPSCR_REG))
9887 (clobber (reg:SI R10_REG))
9888 (clobber (reg:SI PR_REG))]
9889 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9891 [(set_attr "type" "call")
9892 (set (attr "fp_mode")
9893 (if_then_else (eq_attr "fpu_single" "yes")
9894 (const_string "single") (const_string "double")))
9895 (set_attr "needs_delay_slot" "yes")])
9897 (define_expand "call_value_pop"
9898 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9899 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9900 (match_operand 2 "" "")))
9901 (match_operand 3 "" "")
9902 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9903 (match_operand 4 "" "")))])]
9911 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
9912 cookie_rtx = operands[3];
9913 cookie = INTVAL (cookie_rtx);
9914 func = XEXP (operands[1], 0);
9918 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9920 rtx reg = gen_reg_rtx (Pmode);
9922 emit_insn (gen_symGOTPLT2reg (reg, func));
9926 func = legitimize_pic_address (func, Pmode, 0);
9929 r0 = gen_rtx_REG (SImode, R0_REG);
9930 r1 = gen_rtx_REG (SImode, R1_REG);
9932 /* Since such a call function may use all call-clobbered
9933 registers, we force a mode switch earlier, so that we don't
9934 run out of registers when adjusting fpscr for the call. */
9935 emit_insn (gen_force_mode_for_call ());
9937 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9939 operands[1] = force_reg (SImode, operands[1]);
9941 emit_move_insn (r0, func);
9942 emit_move_insn (r1, cookie_rtx);
9944 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9945 emit_call_insn (gen_call_value_pop_compact_rettramp
9946 (operands[0], operands[1], operands[2],
9947 operands[3], operands[4]));
9949 emit_call_insn (gen_call_value_pop_compact
9950 (operands[0], operands[1], operands[2],
9951 operands[3], operands[4]));
9956 (define_expand "sibcall_epilogue"
9960 sh_expand_epilogue (true);
9961 if (TARGET_SHCOMPACT)
9965 /* If epilogue clobbers r0, preserve it in macl. */
9966 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9967 if ((set = single_set (insn))
9968 && REG_P (SET_DEST (set))
9969 && REGNO (SET_DEST (set)) == R0_REG)
9971 rtx r0 = gen_rtx_REG (SImode, R0_REG);
9972 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
9974 /* We can't tell at this point whether the sibcall is a
9975 sibcall_compact and, if it is, whether it uses r0 or
9976 mach as operand 2, so let the instructions that
9977 preserve r0 be optimized away if r0 turns out to be
9979 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
9980 emit_move_insn (r0, tmp);
9987 (define_insn "indirect_jump_compact"
9989 (match_operand:SI 0 "arith_reg_operand" "r"))]
9992 [(set_attr "needs_delay_slot" "yes")
9993 (set_attr "type" "jump_ind")])
9995 (define_expand "indirect_jump"
9997 (match_operand 0 "register_operand" ""))]
10000 if (GET_MODE (operands[0]) != Pmode)
10001 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
10004 ;; The use of operand 1 / 2 helps us distinguish case table jumps
10005 ;; which can be present in structured code from indirect jumps which can not
10006 ;; be present in structured code. This allows -fprofile-arcs to work.
10008 ;; For SH1 processors.
10009 (define_insn "casesi_jump_1"
10011 (match_operand:SI 0 "register_operand" "r"))
10012 (use (label_ref (match_operand 1 "" "")))]
10015 [(set_attr "needs_delay_slot" "yes")
10016 (set_attr "type" "jump_ind")])
10018 ;; For all later processors.
10019 (define_insn "casesi_jump_2"
10020 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
10021 (label_ref (match_operand 1 "" ""))))
10022 (use (label_ref (match_operand 2 "" "")))]
10024 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
10026 [(set_attr "needs_delay_slot" "yes")
10027 (set_attr "type" "jump_ind")])
10029 (define_insn "casesi_jump_media"
10030 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
10031 (use (label_ref (match_operand 1 "" "")))]
10034 [(set_attr "type" "jump_media")])
10036 ;; Call subroutine returning any type.
10037 ;; ??? This probably doesn't work.
10038 (define_expand "untyped_call"
10039 [(parallel [(call (match_operand 0 "" "")
10041 (match_operand 1 "" "")
10042 (match_operand 2 "" "")])]
10043 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
10045 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10047 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10049 rtx set = XVECEXP (operands[2], 0, i);
10050 emit_move_insn (SET_DEST (set), SET_SRC (set));
10053 /* The optimizer does not know that the call sets the function value
10054 registers we stored in the result block. We avoid problems by
10055 claiming that all hard registers are used and clobbered at this
10057 emit_insn (gen_blockage ());
10062 ;; ------------------------------------------------------------------------
10064 ;; ------------------------------------------------------------------------
10066 (define_insn "dect"
10067 [(set (reg:SI T_REG)
10068 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
10069 (set (match_operand:SI 0 "arith_reg_dest" "=r")
10070 (plus:SI (match_dup 1) (const_int -1)))]
10073 [(set_attr "type" "arith")])
10080 ;; Load address of a label. This is only generated by the casesi expand,
10081 ;; and by machine_dependent_reorg (fixing up fp moves).
10082 ;; This must use unspec, because this only works for labels that are
10084 (define_insn "mova"
10085 [(set (reg:SI R0_REG)
10086 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10089 [(set_attr "in_delay_slot" "no")
10090 (set_attr "type" "arith")])
10092 ;; machine_dependent_reorg will make this a `mova'.
10093 (define_insn "mova_const"
10094 [(set (reg:SI R0_REG)
10095 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10098 [(set_attr "in_delay_slot" "no")
10099 (set_attr "type" "arith")])
10101 (define_expand "GOTaddr2picreg"
10102 [(set (reg:SI R0_REG)
10103 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10105 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10106 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10109 if (TARGET_VXWORKS_RTP)
10111 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10112 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10113 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10117 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10118 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10120 if (TARGET_SHMEDIA)
10122 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10123 rtx pic = operands[0];
10124 rtx lab = PATTERN (gen_call_site ());
10127 equiv = operands[1];
10128 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10129 UNSPEC_PCREL_SYMOFF);
10130 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10132 if (Pmode == SImode)
10134 emit_insn (gen_movsi_const (pic, operands[1]));
10135 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10139 emit_insn (gen_movdi_const (pic, operands[1]));
10140 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10143 insn = emit_move_insn (operands[0], tr);
10145 set_unique_reg_note (insn, REG_EQUAL, equiv);
10151 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10153 (define_expand "vxworks_picreg"
10154 [(set (reg:SI PIC_REG)
10155 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10156 (set (reg:SI R0_REG)
10157 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10158 (set (reg:SI PIC_REG)
10159 (mem:SI (reg:SI PIC_REG)))
10160 (set (reg:SI PIC_REG)
10161 (mem:SI (plus:SI (reg:SI PIC_REG)
10162 (reg:SI R0_REG))))]
10163 "TARGET_VXWORKS_RTP")
10165 (define_insn "*ptb"
10166 [(set (match_operand 0 "target_reg_operand" "=b")
10167 (const (unspec [(match_operand 1 "" "Csy")]
10168 UNSPEC_DATALABEL)))]
10169 "TARGET_SHMEDIA && flag_pic
10170 && satisfies_constraint_Csy (operands[1])"
10171 "ptb/u datalabel %1, %0"
10172 [(set_attr "type" "ptabs_media")
10173 (set_attr "length" "*")])
10175 (define_insn "ptrel_si"
10176 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10177 (plus:SI (match_operand:SI 1 "register_operand" "r")
10179 (match_operand:SI 2 "" "")]
10181 "%O2: ptrel/u %1, %0"
10182 [(set_attr "type" "ptabs_media")])
10184 (define_insn "ptrel_di"
10185 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10186 (plus:DI (match_operand:DI 1 "register_operand" "r")
10188 (match_operand:DI 2 "" "")]
10190 "%O2: ptrel/u %1, %0"
10191 [(set_attr "type" "ptabs_media")])
10193 (define_expand "builtin_setjmp_receiver"
10194 [(match_operand 0 "" "")]
10197 emit_insn (gen_GOTaddr2picreg ());
10201 (define_expand "call_site"
10202 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10205 static HOST_WIDE_INT i = 0;
10206 operands[0] = GEN_INT (i);
10210 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10211 ;; in symGOT_load expand.
10212 (define_insn_and_split "chk_guard_add"
10213 [(set (match_operand:SI 0 "register_operand" "=&r")
10214 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10219 "TARGET_SH1 && reload_completed"
10220 [(set (match_dup 0) (reg:SI PIC_REG))
10221 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10223 [(set_attr "type" "arith")])
10225 (define_expand "sym_label2reg"
10226 [(set (match_operand:SI 0 "" "")
10227 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10228 (const (plus:SI (match_operand:SI 2 "" "")
10233 (define_expand "symGOT_load"
10234 [(set (match_dup 2) (match_operand 1 "" ""))
10235 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10236 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10241 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10242 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10244 if (TARGET_SHMEDIA)
10246 rtx reg = operands[2];
10248 if (Pmode == DImode)
10251 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10253 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10258 emit_insn (gen_movsi_const (reg, operands[1]));
10260 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10264 emit_move_insn (operands[2], operands[1]);
10266 /* When stack protector inserts codes after the result is set to
10267 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10268 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10269 when rX is a GOT address for the guard symbol. Ugly but doesn't
10270 matter because this is a rare situation. */
10271 if (!TARGET_SHMEDIA
10272 && flag_stack_protect
10273 && GET_CODE (operands[1]) == CONST
10274 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10275 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10276 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10277 "__stack_chk_guard") == 0)
10278 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10280 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10281 gen_rtx_REG (Pmode, PIC_REG)));
10283 /* N.B. This is not constant for a GOTPLT relocation. */
10284 mem = gen_rtx_MEM (Pmode, operands[3]);
10285 MEM_NOTRAP_P (mem) = 1;
10286 /* ??? Should we have a special alias set for the GOT? */
10287 emit_move_insn (operands[0], mem);
10292 (define_expand "sym2GOT"
10293 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10297 (define_expand "symGOT2reg"
10298 [(match_operand 0 "" "") (match_operand 1 "" "")]
10303 gotsym = gen_sym2GOT (operands[1]);
10304 PUT_MODE (gotsym, Pmode);
10305 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10307 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10312 (define_expand "symGOTPLT2reg"
10313 [(match_operand 0 "" "") (match_operand 1 "" "")]
10316 rtx pltsym = gen_rtx_CONST (Pmode,
10317 gen_rtx_UNSPEC (Pmode,
10318 gen_rtvec (1, operands[1]),
10320 emit_insn (gen_symGOT_load (operands[0], pltsym));
10324 (define_expand "sym2GOTOFF"
10325 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10329 (define_expand "symGOTOFF2reg"
10330 [(match_operand 0 "" "") (match_operand 1 "" "")]
10333 rtx gotoffsym, insn;
10334 rtx t = (!can_create_pseudo_p ()
10336 : gen_reg_rtx (GET_MODE (operands[0])));
10338 gotoffsym = gen_sym2GOTOFF (operands[1]);
10339 PUT_MODE (gotoffsym, Pmode);
10340 emit_move_insn (t, gotoffsym);
10341 insn = emit_move_insn (operands[0],
10342 gen_rtx_PLUS (Pmode, t,
10343 gen_rtx_REG (Pmode, PIC_REG)));
10345 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10350 (define_expand "symPLT_label2reg"
10351 [(set (match_operand:SI 0 "" "")
10354 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10355 (const:SI (plus:SI (match_operand:SI 2 "" "")
10356 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10357 ;; Even though the PIC register is not really used by the call
10358 ;; sequence in which this is expanded, the PLT code assumes the PIC
10359 ;; register is set, so we must not skip its initialization. Since
10360 ;; we only use this expand as part of calling sequences, and never
10361 ;; to take the address of a function, this is the best point to
10362 ;; insert the (use). Using the PLT to take the address of a
10363 ;; function would be wrong, not only because the PLT entry could
10364 ;; then be called from a function that doesn't initialize the PIC
10365 ;; register to the proper GOT, but also because pointers to the
10366 ;; same function might not compare equal, should they be set by
10367 ;; different shared libraries.
10368 (use (reg:SI PIC_REG))]
10372 (define_expand "sym2PIC"
10373 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10377 ;; -------------------------------------------------------------------------
10378 ;; TLS code generation.
10380 ;; FIXME: The multi-insn asm blocks should be converted to use
10381 ;; define_insn_and_split.
10382 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10383 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10386 (define_insn "tls_global_dynamic"
10387 [(set (match_operand:SI 0 "register_operand" "=&z")
10388 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10391 (use (reg:PSI FPSCR_REG))
10392 (use (reg:SI PIC_REG))
10393 (clobber (reg:SI PR_REG))
10394 (clobber (scratch:SI))]
10397 return "mov.l 1f,r4" "\n"
10399 " mov.l 2f,r1" "\n"
10406 "1: .long %a1@TLSGD" "\n"
10407 "2: .long __tls_get_addr@PLT" "\n"
10410 [(set_attr "type" "tls_load")
10411 (set_attr "length" "26")])
10413 (define_insn "tls_local_dynamic"
10414 [(set (match_operand:SI 0 "register_operand" "=&z")
10415 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10418 (use (reg:PSI FPSCR_REG))
10419 (use (reg:SI PIC_REG))
10420 (clobber (reg:SI PR_REG))
10421 (clobber (scratch:SI))]
10424 return "mov.l 1f,r4" "\n"
10426 " mov.l 2f,r1" "\n"
10433 "1: .long %a1@TLSLDM" "\n"
10434 "2: .long __tls_get_addr@PLT" "\n"
10437 [(set_attr "type" "tls_load")
10438 (set_attr "length" "26")])
10440 (define_expand "sym2DTPOFF"
10441 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10445 (define_expand "symDTPOFF2reg"
10446 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10450 rtx t = (!can_create_pseudo_p ()
10452 : gen_reg_rtx (GET_MODE (operands[0])));
10454 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10455 PUT_MODE (dtpoffsym, Pmode);
10456 emit_move_insn (t, dtpoffsym);
10457 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10461 (define_expand "sym2GOTTPOFF"
10462 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10466 (define_insn "tls_initial_exec"
10467 [(set (match_operand:SI 0 "register_operand" "=&r")
10468 (unspec:SI [(match_operand:SI 1 "" "")]
10470 (use (reg:SI GBR_REG))
10471 (use (reg:SI PIC_REG))
10472 (clobber (reg:SI R0_REG))]
10475 return "mov.l 1f,r0" "\n"
10477 " mov.l @(r0,r12),r0" "\n"
10481 "1: .long %a1" "\n"
10484 [(set_attr "type" "tls_load")
10485 (set_attr "length" "16")])
10487 (define_expand "sym2TPOFF"
10488 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10492 (define_expand "symTPOFF2reg"
10493 [(match_operand 0 "" "") (match_operand 1 "" "")]
10498 tpoffsym = gen_sym2TPOFF (operands[1]);
10499 PUT_MODE (tpoffsym, Pmode);
10500 emit_move_insn (operands[0], tpoffsym);
10504 ;;------------------------------------------------------------------------------
10505 ;; Thread pointer getter and setter.
10507 ;; On SH the thread pointer is kept in the GBR.
10508 ;; These patterns are usually expanded from the respective built-in functions.
10509 (define_expand "get_thread_pointersi"
10510 [(set (match_operand:SI 0 "register_operand") (reg:SI GBR_REG))]
10513 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
10514 (define_insn "store_gbr"
10515 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))]
10518 [(set_attr "type" "tls_load")])
10520 (define_expand "set_thread_pointersi"
10521 [(set (reg:SI GBR_REG)
10522 (unspec_volatile:SI [(match_operand:SI 0 "register_operand")]
10526 (define_insn "load_gbr"
10527 [(set (reg:SI GBR_REG)
10528 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10532 [(set_attr "type" "move")])
10534 ;;------------------------------------------------------------------------------
10535 ;; Thread pointer relative memory loads and stores.
10537 ;; On SH there are GBR displacement address modes which can be utilized to
10538 ;; access memory behind the thread pointer.
10539 ;; Since we do not allow using GBR for general purpose memory accesses, these
10540 ;; GBR addressing modes are formed by the combine pass.
10541 ;; This could be done with fewer patterns than below by using a mem predicate
10542 ;; for the GBR mem, but then reload would try to reload addresses with a
10543 ;; zero displacement for some strange reason.
10545 (define_insn "*mov<mode>_gbr_load"
10546 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10547 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10548 (match_operand:QIHISI 1 "gbr_displacement"))))]
10550 "mov.<bwl> @(%O1,gbr),%0"
10551 [(set_attr "type" "load")])
10553 (define_insn "*mov<mode>_gbr_load"
10554 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10555 (mem:QIHISI (reg:SI GBR_REG)))]
10557 "mov.<bwl> @(0,gbr),%0"
10558 [(set_attr "type" "load")])
10560 (define_insn "*mov<mode>_gbr_load"
10561 [(set (match_operand:SI 0 "register_operand" "=z")
10563 (mem:QIHI (plus:SI (reg:SI GBR_REG)
10564 (match_operand:QIHI 1 "gbr_displacement")))))]
10566 "mov.<bw> @(%O1,gbr),%0"
10567 [(set_attr "type" "load")])
10569 (define_insn "*mov<mode>_gbr_load"
10570 [(set (match_operand:SI 0 "register_operand" "=z")
10571 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
10573 "mov.<bw> @(0,gbr),%0"
10574 [(set_attr "type" "load")])
10576 (define_insn "*mov<mode>_gbr_store"
10577 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10578 (match_operand:QIHISI 0 "gbr_displacement")))
10579 (match_operand:QIHISI 1 "register_operand" "z"))]
10581 "mov.<bwl> %1,@(%O0,gbr)"
10582 [(set_attr "type" "store")])
10584 (define_insn "*mov<mode>_gbr_store"
10585 [(set (mem:QIHISI (reg:SI GBR_REG))
10586 (match_operand:QIHISI 0 "register_operand" "z"))]
10588 "mov.<bwl> %0,@(0,gbr)"
10589 [(set_attr "type" "store")])
10591 ;; DImode memory accesses have to be split in two SImode accesses.
10592 ;; Split them before reload, so that it gets a better chance to figure out
10593 ;; how to deal with the R0 restriction for the individual SImode accesses.
10594 ;; Do not match this insn during or after reload because it can't be split
10596 (define_insn_and_split "*movdi_gbr_load"
10597 [(set (match_operand:DI 0 "register_operand")
10598 (match_operand:DI 1 "gbr_address_mem"))]
10599 "TARGET_SH1 && can_create_pseudo_p ()"
10602 [(set (match_dup 3) (match_dup 5))
10603 (set (match_dup 4) (match_dup 6))]
10605 /* Swap low/high part load order on little endian, so that the result reg
10606 of the second load can be used better. */
10607 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
10608 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10609 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10610 operands[4 - off] = gen_highpart (SImode, operands[0]);
10611 operands[6 - off] = gen_highpart (SImode, operands[1]);
10614 (define_insn_and_split "*movdi_gbr_store"
10615 [(set (match_operand:DI 0 "gbr_address_mem")
10616 (match_operand:DI 1 "register_operand"))]
10617 "TARGET_SH1 && can_create_pseudo_p ()"
10620 [(set (match_dup 3) (match_dup 5))
10621 (set (match_dup 4) (match_dup 6))]
10623 /* Swap low/high part store order on big endian, so that stores of function
10624 call results can save a reg copy. */
10625 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
10626 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10627 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10628 operands[4 - off] = gen_highpart (SImode, operands[0]);
10629 operands[6 - off] = gen_highpart (SImode, operands[1]);
10632 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
10633 ;; in particular when the displacements are in the range of the regular move
10634 ;; insns. Thus, in the first split pass after the combine pass we search
10635 ;; for missed opportunities and try to fix them up ourselves.
10636 ;; If an equivalent GBR address can be determined the load / store is split
10637 ;; into one of the GBR load / store patterns.
10638 ;; All of that must happen before reload (GBR address modes use R0 as the
10639 ;; other operand) and there's no point of doing it if the GBR is not
10640 ;; referenced in a function at all.
10642 [(set (match_operand:QIHISIDI 0 "register_operand")
10643 (match_operand:QIHISIDI 1 "memory_operand"))]
10644 "TARGET_SH1 && !reload_in_progress && !reload_completed
10645 && df_regs_ever_live_p (GBR_REG)"
10646 [(set (match_dup 0) (match_dup 1))]
10648 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10649 if (gbr_mem != NULL_RTX)
10650 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10656 [(set (match_operand:SI 0 "register_operand")
10657 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10658 "TARGET_SH1 && !reload_in_progress && !reload_completed
10659 && df_regs_ever_live_p (GBR_REG)"
10660 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
10662 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10663 if (gbr_mem != NULL_RTX)
10664 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10669 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
10670 ;; Split those so that a GBR load can be used.
10672 [(set (match_operand:SI 0 "register_operand")
10673 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10674 "TARGET_SH2A && !reload_in_progress && !reload_completed
10675 && df_regs_ever_live_p (GBR_REG)"
10676 [(set (match_dup 2) (match_dup 1))
10677 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10679 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10680 if (gbr_mem != NULL_RTX)
10682 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
10683 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10690 [(set (match_operand:QIHISIDI 0 "memory_operand")
10691 (match_operand:QIHISIDI 1 "register_operand"))]
10692 "TARGET_SH1 && !reload_in_progress && !reload_completed
10693 && df_regs_ever_live_p (GBR_REG)"
10694 [(set (match_dup 0) (match_dup 1))]
10696 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
10697 if (gbr_mem != NULL_RTX)
10698 operands[0] = replace_equiv_address (operands[0], gbr_mem);
10703 ;;------------------------------------------------------------------------------
10704 ;; case instruction for switch statements.
10706 ;; operand 0 is index
10707 ;; operand 1 is the minimum bound
10708 ;; operand 2 is the maximum bound - minimum bound + 1
10709 ;; operand 3 is CODE_LABEL for the table;
10710 ;; operand 4 is the CODE_LABEL to go to if index out of range.
10711 (define_expand "casesi"
10712 [(match_operand:SI 0 "arith_reg_operand" "")
10713 (match_operand:SI 1 "arith_reg_operand" "")
10714 (match_operand:SI 2 "arith_reg_operand" "")
10715 (match_operand 3 "" "") (match_operand 4 "" "")]
10718 rtx reg = gen_reg_rtx (SImode);
10719 rtx reg2 = gen_reg_rtx (SImode);
10720 if (TARGET_SHMEDIA)
10722 rtx reg = gen_reg_rtx (DImode);
10723 rtx reg2 = gen_reg_rtx (DImode);
10724 rtx reg3 = gen_reg_rtx (Pmode);
10725 rtx reg4 = gen_reg_rtx (Pmode);
10726 rtx reg5 = gen_reg_rtx (Pmode);
10729 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
10730 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
10731 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
10733 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
10734 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
10736 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
10737 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
10738 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
10739 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
10740 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
10741 (Pmode, operands[3])));
10742 /* Messy: can we subreg to clean this up? */
10743 if (Pmode == DImode)
10744 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
10746 load = gen_casesi_load_media (reg4,
10747 gen_rtx_SUBREG (DImode, reg3, 0),
10748 reg2, operands[3]);
10749 PUT_MODE (SET_SRC (load), Pmode);
10751 /* ??? The following add could be eliminated if we used ptrel. */
10752 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
10753 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
10757 operands[1] = copy_to_mode_reg (SImode, operands[1]);
10758 operands[2] = copy_to_mode_reg (SImode, operands[2]);
10759 /* If optimizing, casesi_worker depends on the mode of the instruction
10760 before label it 'uses' - operands[3]. */
10761 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
10763 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
10765 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
10767 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
10768 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
10769 operands[3], but to lab. We will fix this up in
10770 machine_dependent_reorg. */
10775 (define_expand "casesi_0"
10776 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
10777 (set (match_dup 4) (minus:SI (match_dup 4)
10778 (match_operand:SI 1 "arith_operand" "")))
10779 (set (reg:SI T_REG)
10780 (gtu:SI (match_dup 4)
10781 (match_operand:SI 2 "arith_reg_operand" "")))
10783 (if_then_else (ne (reg:SI T_REG)
10785 (label_ref (match_operand 3 "" ""))
10790 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
10791 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
10792 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
10793 (define_insn "casesi_worker_0"
10794 [(set (match_operand:SI 0 "register_operand" "=r,r")
10795 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
10796 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10797 (clobber (match_scratch:SI 3 "=X,1"))
10798 (clobber (match_scratch:SI 4 "=&z,z"))]
10803 [(set (match_operand:SI 0 "register_operand" "")
10804 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10805 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10806 (clobber (match_scratch:SI 3 ""))
10807 (clobber (match_scratch:SI 4 ""))]
10808 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
10809 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10810 (parallel [(set (match_dup 0)
10811 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10812 (label_ref (match_dup 2))] UNSPEC_CASESI))
10813 (clobber (match_dup 3))])
10814 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10816 if (GET_CODE (operands[2]) == CODE_LABEL)
10817 LABEL_NUSES (operands[2])++;
10821 [(set (match_operand:SI 0 "register_operand" "")
10822 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10823 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10824 (clobber (match_scratch:SI 3 ""))
10825 (clobber (match_scratch:SI 4 ""))]
10826 "TARGET_SH2 && reload_completed"
10827 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10828 (parallel [(set (match_dup 0)
10829 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10830 (label_ref (match_dup 2))] UNSPEC_CASESI))
10831 (clobber (match_dup 3))])]
10833 if (GET_CODE (operands[2]) == CODE_LABEL)
10834 LABEL_NUSES (operands[2])++;
10837 (define_insn "casesi_worker_1"
10838 [(set (match_operand:SI 0 "register_operand" "=r,r")
10839 (unspec:SI [(reg:SI R0_REG)
10840 (match_operand:SI 1 "register_operand" "0,r")
10841 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10842 (clobber (match_scratch:SI 3 "=X,1"))]
10845 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10847 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10849 switch (GET_MODE (diff_vec))
10852 return "shll2 %1" "\n"
10853 " mov.l @(r0,%1),%0";
10855 return "add %1,%1" "\n"
10856 " mov.w @(r0,%1),%0";
10858 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10859 return "mov.b @(r0,%1),%0" "\n"
10862 return "mov.b @(r0,%1),%0";
10865 gcc_unreachable ();
10868 [(set_attr "length" "4")])
10870 (define_insn "casesi_worker_2"
10871 [(set (match_operand:SI 0 "register_operand" "=r,r")
10872 (unspec:SI [(reg:SI R0_REG)
10873 (match_operand:SI 1 "register_operand" "0,r")
10874 (label_ref (match_operand 2 "" ""))
10875 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
10876 (clobber (match_operand:SI 4 "" "=X,1"))]
10877 "TARGET_SH2 && reload_completed && flag_pic"
10879 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10880 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10882 switch (GET_MODE (diff_vec))
10885 return "shll2 %1" "\n"
10887 " mova %O3,r0" "\n"
10888 " mov.l @(r0,%1),%0";
10890 return "add %1,%1" "\n"
10892 " mova %O3,r0" "\n"
10893 " mov.w @(r0,%1),%0";
10895 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10896 return "add r0,%1" "\n"
10897 " mova %O3,r0" "\n"
10898 " mov.b @(r0,%1),%0" "\n"
10901 return "add r0,%1" "\n"
10902 " mova %O3,r0" "\n"
10903 " mov.b @(r0,%1),%0";
10905 gcc_unreachable ();
10908 [(set_attr "length" "8")])
10910 (define_insn "casesi_shift_media"
10911 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10912 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
10913 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
10917 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10919 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10921 switch (GET_MODE (diff_vec))
10924 return "shlli %1, 2, %0";
10926 return "shlli %1, 1, %0";
10928 if (rtx_equal_p (operands[0], operands[1]))
10930 return "add %1, r63, %0";
10932 gcc_unreachable ();
10935 [(set_attr "type" "arith_media")])
10937 (define_insn "casesi_load_media"
10938 [(set (match_operand 0 "any_arith_reg_dest" "=r")
10939 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
10940 (match_operand:DI 2 "arith_reg_operand" "r")
10941 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
10944 rtx diff_vec = PATTERN (NEXT_INSN (operands[3]));
10946 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10948 switch (GET_MODE (diff_vec))
10951 return "ldx.l %1, %2, %0";
10954 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10955 return "ldx.uw %1, %2, %0";
10957 return "ldx.w %1, %2, %0";
10959 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10960 return "ldx.ub %1, %2, %0";
10961 return "ldx.b %1, %2, %0";
10963 gcc_unreachable ();
10966 [(set_attr "type" "load_media")])
10968 (define_expand "simple_return"
10970 "sh_can_use_simple_return_p ()")
10972 (define_expand "return"
10974 "reload_completed && epilogue_completed"
10976 if (TARGET_SHMEDIA)
10978 emit_jump_insn (gen_return_media ());
10982 if (TARGET_SHCOMPACT
10983 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
10985 emit_jump_insn (gen_shcompact_return_tramp ());
10990 (define_insn "*<code>_i"
10992 "TARGET_SH1 && ! (TARGET_SHCOMPACT
10993 && (crtl->args.info.call_cookie
10994 & CALL_COOKIE_RET_TRAMP (1)))
10995 && reload_completed
10996 && ! sh_cfun_trap_exit_p ()"
10998 if (TARGET_SH2A && (dbr_sequence_length () == 0)
10999 && !current_function_interrupt)
11004 [(set_attr "type" "return")
11005 (set_attr "needs_delay_slot" "yes")])
11007 ;; trapa has no delay slot.
11008 (define_insn "*return_trapa"
11010 "TARGET_SH1 && !TARGET_SHCOMPACT
11011 && reload_completed"
11013 [(set_attr "type" "return")])
11015 (define_expand "shcompact_return_tramp"
11018 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11020 rtx reg = gen_rtx_REG (Pmode, R0_REG);
11022 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
11023 emit_jump_insn (gen_shcompact_return_tramp_i ());
11027 (define_insn "shcompact_return_tramp_i"
11028 [(parallel [(return) (use (reg:SI R0_REG))])]
11030 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11032 [(set_attr "type" "jump_ind")
11033 (set_attr "needs_delay_slot" "yes")])
11035 (define_insn "return_media_i"
11036 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
11037 "TARGET_SHMEDIA && reload_completed"
11039 [(set_attr "type" "jump_media")])
11041 (define_insn "return_media_rte"
11043 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
11045 [(set_attr "type" "jump_media")])
11047 (define_expand "return_media"
11049 "TARGET_SHMEDIA && reload_completed"
11051 int tr_regno = sh_media_register_for_return ();
11054 if (current_function_interrupt)
11056 emit_jump_insn (gen_return_media_rte ());
11061 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
11063 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
11064 tr_regno = TR0_REG;
11065 tr = gen_rtx_REG (Pmode, tr_regno);
11066 emit_move_insn (tr, r18);
11069 tr = gen_rtx_REG (Pmode, tr_regno);
11071 emit_jump_insn (gen_return_media_i (tr));
11075 (define_insn "shcompact_preserve_incoming_args"
11076 [(set (match_operand:SI 0 "register_operand" "+r")
11077 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11080 [(set_attr "length" "0")])
11082 (define_insn "shcompact_incoming_args"
11083 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11084 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11085 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11086 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11087 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11088 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11089 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11090 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11091 (set (mem:BLK (reg:SI MACL_REG))
11092 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11093 (use (reg:SI R0_REG))
11094 (clobber (reg:SI R0_REG))
11095 (clobber (reg:SI MACL_REG))
11096 (clobber (reg:SI MACH_REG))
11097 (clobber (reg:SI PR_REG))]
11100 [(set_attr "needs_delay_slot" "yes")])
11102 (define_insn "shmedia_save_restore_regs_compact"
11103 [(set (reg:SI SP_REG)
11104 (plus:SI (reg:SI SP_REG)
11105 (match_operand:SI 0 "immediate_operand" "i")))
11106 (use (reg:SI R0_REG))
11107 (clobber (reg:SI PR_REG))]
11109 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11110 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11112 [(set_attr "needs_delay_slot" "yes")])
11114 (define_expand "prologue"
11118 sh_expand_prologue ();
11122 (define_expand "epilogue"
11126 sh_expand_epilogue (false);
11128 || (TARGET_SHCOMPACT
11129 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11131 emit_jump_insn (gen_return ());
11136 (define_expand "eh_return"
11137 [(use (match_operand 0 "register_operand" ""))]
11140 rtx ra = operands[0];
11142 if (TARGET_SHMEDIA64)
11143 emit_insn (gen_eh_set_ra_di (ra));
11145 emit_insn (gen_eh_set_ra_si (ra));
11150 ;; Clobber the return address on the stack. We can't expand this
11151 ;; until we know where it will be put in the stack frame.
11153 (define_insn "eh_set_ra_si"
11154 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11156 (clobber (match_scratch:SI 1 "=&r"))]
11157 "! TARGET_SHMEDIA64"
11160 (define_insn "eh_set_ra_di"
11161 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11163 (clobber (match_scratch:DI 1 "=&r"))]
11168 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11170 (clobber (match_scratch 1 ""))]
11174 sh_set_return_address (operands[0], operands[1]);
11178 (define_insn "blockage"
11179 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11182 [(set_attr "length" "0")])
11184 ;; Define movml instructions for SH2A target. Currently they are
11185 ;; used to push and pop all banked registers only.
11187 (define_insn "movml_push_banked"
11188 [(set (match_operand:SI 0 "register_operand" "=r")
11189 (plus (match_dup 0) (const_int -32)))
11190 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11191 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11192 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11193 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11194 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11195 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11196 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11197 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11198 "TARGET_SH2A && REGNO (operands[0]) == 15"
11200 [(set_attr "in_delay_slot" "no")])
11202 (define_insn "movml_pop_banked"
11203 [(set (match_operand:SI 0 "register_operand" "=r")
11204 (plus (match_dup 0) (const_int 32)))
11205 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11206 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11207 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11208 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11209 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11210 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11211 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11212 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11213 "TARGET_SH2A && REGNO (operands[0]) == 15"
11215 [(set_attr "in_delay_slot" "no")])
11217 ;; ------------------------------------------------------------------------
11218 ;; Scc instructions
11219 ;; ------------------------------------------------------------------------
11221 (define_insn "movt"
11222 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11223 (match_operand:SI 1 "t_reg_operand"))]
11226 [(set_attr "type" "arith")])
11228 (define_insn "movrt"
11229 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11230 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11233 [(set_attr "type" "arith")])
11235 (define_expand "cstore4_media"
11236 [(set (match_operand:SI 0 "register_operand" "=r")
11237 (match_operator:SI 1 "sh_float_comparison_operator"
11238 [(match_operand 2 "logical_operand" "")
11239 (match_operand 3 "cmp_operand" "")]))]
11242 enum machine_mode mode = GET_MODE (operands[2]);
11243 enum rtx_code code = GET_CODE (operands[1]);
11245 if (mode == VOIDmode)
11246 mode = GET_MODE (operands[3]);
11247 if (operands[2] == const0_rtx)
11249 if (code == EQ || code == NE)
11250 operands[2] = operands[3], operands[3] = const0_rtx;
11253 operands[2] = force_reg (mode, operands[2]);
11254 if (operands[3] != const0_rtx)
11255 operands[3] = force_reg (mode, operands[3]);
11261 swap = invert = !FLOAT_MODE_P (mode);
11266 swap = FLOAT_MODE_P (mode), invert = !swap;
11271 swap = true, invert = false;
11278 swap = invert = false;
11282 swap = invert = true;
11286 gcc_unreachable ();
11291 rtx tem = operands[2];
11292 operands[2] = operands[3];
11294 code = swap_condition (code);
11299 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11300 code = reverse_condition (code);
11301 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11302 emit_insn (gen_cstore4_media (tem, operands[1],
11303 operands[2], operands[3]));
11306 operands[3] = const0_rtx;
11309 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11312 (define_expand "cstoresi4"
11313 [(set (match_operand:SI 0 "register_operand" "=r")
11314 (match_operator:SI 1 "comparison_operator"
11315 [(match_operand:SI 2 "cmpsi_operand" "")
11316 (match_operand:SI 3 "arith_operand" "")]))]
11317 "TARGET_SH1 || TARGET_SHMEDIA"
11319 if (TARGET_SHMEDIA)
11321 emit_insn (gen_cstore4_media (operands[0], operands[1],
11322 operands[2], operands[3]));
11326 if (sh_expand_t_scc (operands))
11329 if (! currently_expanding_to_rtl)
11332 sh_emit_compare_and_set (operands, SImode);
11336 (define_expand "cstoredi4"
11337 [(set (match_operand:SI 0 "register_operand" "=r")
11338 (match_operator:SI 1 "comparison_operator"
11339 [(match_operand:DI 2 "arith_operand" "")
11340 (match_operand:DI 3 "arith_operand" "")]))]
11341 "TARGET_SH2 || TARGET_SHMEDIA"
11343 if (TARGET_SHMEDIA)
11345 emit_insn (gen_cstore4_media (operands[0], operands[1],
11346 operands[2], operands[3]));
11350 if (sh_expand_t_scc (operands))
11353 if (! currently_expanding_to_rtl)
11356 sh_emit_compare_and_set (operands, DImode);
11360 ;; Move the complement of the T reg to a reg.
11361 ;; On SH2A the movrt insn can be used.
11362 ;; On anything else than SH2A this has to be done with multiple instructions.
11363 ;; One obvious way would be:
11368 ;; However, this puts pressure on r0 in most cases and thus the following is
11374 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11375 ;; becomes a one instruction operation. Moreover, care must be taken that
11376 ;; the insn can still be combined with inverted compare and branch code
11377 ;; around it. On the other hand, if a function returns the complement of
11378 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11379 ;; lead to better code.
11380 (define_expand "movnegt"
11381 [(set (match_operand:SI 0 "arith_reg_dest" "")
11382 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11386 emit_insn (gen_movrt (operands[0], operands[1]));
11389 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11390 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11395 (define_insn "movrt_negc"
11396 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11397 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11398 (set (reg:SI T_REG) (const_int 1))
11399 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11402 [(set_attr "type" "arith")])
11404 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11405 ;; pattern can be used by the combine pass. Using a scratch reg for the
11406 ;; -1 constant results in slightly better register allocations compared to
11407 ;; generating a pseudo reg before reload.
11408 (define_insn_and_split "*movrt_negc"
11409 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11410 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11411 (clobber (match_scratch:SI 2 "=r"))
11412 (clobber (reg:SI T_REG))]
11413 "TARGET_SH1 && ! TARGET_SH2A"
11415 "&& reload_completed"
11416 [(set (match_dup 2) (const_int -1))
11418 [(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
11419 (set (reg:SI T_REG) (const_int 1))
11420 (use (match_dup 2))])])
11422 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11423 ;; clobber the T bit, which is useful when storing the T bit and the
11424 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11425 ;; Usually we don't want this insn to be matched, except for cases where the
11426 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11427 (define_insn_and_split "movrt_xor"
11428 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11429 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11430 (use (reg:SI T_REG))]
11431 "TARGET_SH1 && !TARGET_SH2A"
11433 "&& reload_completed"
11434 [(set (match_dup 0) (reg:SI T_REG))
11435 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11437 ;; Store the T bit and the negated T bit in two regs in parallel. There is
11438 ;; no real insn to do that, but specifying this pattern will give combine
11439 ;; some opportunities.
11440 (define_insn_and_split "*movt_movrt"
11441 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11442 (match_operand:SI 1 "negt_reg_operand"))
11443 (set (match_operand:SI 2 "arith_reg_dest")
11444 (match_operand:SI 3 "t_reg_operand"))])]
11450 rtx i = TARGET_SH2A
11451 ? gen_movrt (operands[0], get_t_reg_rtx ())
11452 : gen_movrt_xor (operands[0], get_t_reg_rtx ());
11455 emit_insn (gen_movt (operands[2], get_t_reg_rtx ()));
11459 (define_insn_and_split "*movt_movrt"
11460 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11461 (match_operand:SI 1 "t_reg_operand"))
11462 (set (match_operand:SI 2 "arith_reg_dest")
11463 (match_operand:SI 3 "negt_reg_operand"))])]
11467 [(parallel [(set (match_dup 2) (match_dup 3))
11468 (set (match_dup 0) (match_dup 1))])])
11470 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11471 ;; T = 1: 0x80000000 -> reg
11472 ;; T = 0: 0x7FFFFFFF -> reg
11473 ;; This works because 0 - 0x80000000 = 0x80000000.
11475 ;; This insn must not match again after it has been split into the constant
11476 ;; load and negc. This is accomplished by the special negc insn that
11477 ;; has a use on the operand.
11478 (define_insn_and_split "*mov_t_msb_neg"
11479 [(set (match_operand:SI 0 "arith_reg_dest")
11480 (minus:SI (const_int -2147483648) ;; 0x80000000
11481 (match_operand 1 "t_reg_operand")))
11482 (clobber (reg:SI T_REG))]
11485 "&& can_create_pseudo_p ()"
11486 [(set (match_dup 2) (const_int -2147483648))
11487 (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2))
11489 (clobber (reg:SI T_REG))
11490 (use (match_dup 2))])]
11492 operands[2] = gen_reg_rtx (SImode);
11495 (define_insn "*mov_t_msb_neg_negc"
11496 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11497 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
11498 (match_operand:SI 2 "t_reg_operand")))
11499 (clobber (reg:SI T_REG))
11500 (use (match_dup 1))]
11503 [(set_attr "type" "arith")])
11505 ;; These are essentially the same as above, but with the inverted T bit.
11506 ;; Combine recognizes the split patterns, but does not take them sometimes
11507 ;; if the T_REG clobber is specified. Instead it tries to split out the
11508 ;; T bit negation. Since these splits are supposed to be taken only by
11509 ;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this
11512 [(set (match_operand:SI 0 "arith_reg_dest")
11513 (plus:SI (match_operand 1 "negt_reg_operand")
11514 (const_int 2147483647)))] ;; 0x7fffffff
11515 "TARGET_SH1 && can_create_pseudo_p ()"
11516 [(parallel [(set (match_dup 0)
11517 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11518 (clobber (reg:SI T_REG))])])
11521 [(set (match_operand:SI 0 "arith_reg_dest")
11522 (if_then_else:SI (match_operand 1 "t_reg_operand")
11523 (const_int 2147483647) ;; 0x7fffffff
11524 (const_int -2147483648)))] ;; 0x80000000
11525 "TARGET_SH1 && can_create_pseudo_p ()"
11526 [(parallel [(set (match_dup 0)
11527 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11528 (clobber (reg:SI T_REG))])])
11530 ;; The *negnegt pattern helps the combine pass to figure out how to fold
11531 ;; an explicit double T bit negation.
11532 (define_insn_and_split "*negnegt"
11533 [(set (reg:SI T_REG)
11534 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
11540 ;; Store T bit as all zeros or ones in a reg.
11541 (define_insn "mov_neg_si_t"
11542 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11543 (neg:SI (match_operand 1 "t_reg_operand" "")))]
11546 [(set_attr "type" "arith")])
11548 ;; Store negated T bit as all zeros or ones in a reg.
11549 ;; Use the following sequence:
11550 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
11551 ;; not Rn,Rn ! Rn = 0 - Rn
11553 [(set (match_operand:SI 0 "arith_reg_dest" "")
11554 (neg:SI (match_operand 1 "negt_reg_operand" "")))]
11556 [(set (match_dup 0) (neg:SI (reg:SI T_REG)))
11557 (set (match_dup 0) (not:SI (match_dup 0)))])
11559 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
11560 (define_insn_and_split "*movtt"
11561 [(set (reg:SI T_REG)
11562 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
11568 ;; Invert the T bit.
11569 ;; On SH2A we can use the nott insn. On anything else this must be done with
11570 ;; multiple insns like:
11573 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
11574 ;; pass will look for this insn. Disallow using it if pseudos can't be
11576 (define_insn_and_split "nott"
11577 [(set (reg:SI T_REG)
11578 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
11579 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
11581 gcc_assert (TARGET_SH2A);
11584 "! TARGET_SH2A && can_create_pseudo_p ()"
11585 [(set (match_dup 0) (reg:SI T_REG))
11586 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
11588 operands[0] = gen_reg_rtx (SImode);
11591 ;; Store T bit as MSB in a reg.
11592 ;; T = 0: 0x00000000 -> reg
11593 ;; T = 1: 0x80000000 -> reg
11594 (define_insn_and_split "*movt_msb"
11595 [(set (match_operand:SI 0 "arith_reg_dest")
11596 (mult:SI (match_operand:SI 1 "t_reg_operand")
11597 (const_int -2147483648))) ;; 0xffffffff80000000
11598 (clobber (reg:SI T_REG))]
11602 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
11604 ;; Store inverted T bit as MSB in a reg.
11605 ;; T = 0: 0x80000000 -> reg
11606 ;; T = 1: 0x00000000 -> reg
11607 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
11608 ;; On non SH2A we resort to the following sequence:
11612 ;; The T bit value will be modified during the sequence, but the rotcr insn
11613 ;; will restore its original value.
11614 (define_insn_and_split "*negt_msb"
11615 [(set (match_operand:SI 0 "arith_reg_dest")
11616 (match_operand:SI 1 "negt_reg_shl31_operand"))]
11619 "&& can_create_pseudo_p ()"
11622 rtx tmp = gen_reg_rtx (SImode);
11626 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
11627 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
11631 emit_move_insn (tmp, get_t_reg_rtx ());
11632 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
11633 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
11638 ;; The *cset_zero patterns convert optimizations such as
11639 ;; "if (test) x = 0;"
11641 ;; "x &= -(test == 0);"
11642 ;; back to conditional branch sequences if zero-displacement branches
11644 ;; FIXME: These patterns can be removed when conditional execution patterns
11645 ;; are implemented, since ifcvt will not perform these optimizations if
11646 ;; conditional execution is supported.
11647 (define_insn "*cset_zero"
11648 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11649 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
11651 (match_operand:SI 2 "arith_reg_operand" "0")))]
11652 "TARGET_SH1 && TARGET_ZDCBRANCH"
11654 return "bf 0f" "\n"
11658 [(set_attr "type" "arith") ;; poor approximation
11659 (set_attr "length" "4")])
11661 (define_insn "*cset_zero"
11662 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11663 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
11664 (match_operand:SI 2 "arith_reg_operand" "0")
11666 "TARGET_SH1 && TARGET_ZDCBRANCH"
11668 int tval = sh_eval_treg_value (operands[1]);
11670 return "bt 0f" "\n"
11673 else if (tval == false)
11674 return "bf 0f" "\n"
11678 gcc_unreachable ();
11680 [(set_attr "type" "arith") ;; poor approximation
11681 (set_attr "length" "4")])
11683 (define_expand "cstoresf4"
11684 [(set (match_operand:SI 0 "register_operand" "=r")
11685 (match_operator:SI 1 "sh_float_comparison_operator"
11686 [(match_operand:SF 2 "arith_operand" "")
11687 (match_operand:SF 3 "arith_operand" "")]))]
11688 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
11690 if (TARGET_SHMEDIA)
11692 emit_insn (gen_cstore4_media (operands[0], operands[1],
11693 operands[2], operands[3]));
11697 if (! currently_expanding_to_rtl)
11700 sh_emit_compare_and_set (operands, SFmode);
11704 (define_expand "cstoredf4"
11705 [(set (match_operand:SI 0 "register_operand" "=r")
11706 (match_operator:SI 1 "sh_float_comparison_operator"
11707 [(match_operand:DF 2 "arith_operand" "")
11708 (match_operand:DF 3 "arith_operand" "")]))]
11709 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11711 if (TARGET_SHMEDIA)
11713 emit_insn (gen_cstore4_media (operands[0], operands[1],
11714 operands[2], operands[3]));
11718 if (! currently_expanding_to_rtl)
11721 sh_emit_compare_and_set (operands, DFmode);
11725 ;; -------------------------------------------------------------------------
11726 ;; Instructions to cope with inline literal tables
11727 ;; -------------------------------------------------------------------------
11729 ;; 2 byte integer in line
11730 (define_insn "consttable_2"
11731 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11732 (match_operand 1 "" "")]
11736 if (operands[1] != const0_rtx)
11737 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
11740 [(set_attr "length" "2")
11741 (set_attr "in_delay_slot" "no")])
11743 ;; 4 byte integer in line
11744 (define_insn "consttable_4"
11745 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11746 (match_operand 1 "" "")]
11750 if (operands[1] != const0_rtx)
11752 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
11753 mark_symbol_refs_as_used (operands[0]);
11757 [(set_attr "length" "4")
11758 (set_attr "in_delay_slot" "no")])
11760 ;; 8 byte integer in line
11761 (define_insn "consttable_8"
11762 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11763 (match_operand 1 "" "")]
11767 if (operands[1] != const0_rtx)
11768 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
11771 [(set_attr "length" "8")
11772 (set_attr "in_delay_slot" "no")])
11774 ;; 4 byte floating point
11775 (define_insn "consttable_sf"
11776 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
11777 (match_operand 1 "" "")]
11781 if (operands[1] != const0_rtx)
11784 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11785 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
11789 [(set_attr "length" "4")
11790 (set_attr "in_delay_slot" "no")])
11792 ;; 8 byte floating point
11793 (define_insn "consttable_df"
11794 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
11795 (match_operand 1 "" "")]
11799 if (operands[1] != const0_rtx)
11802 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11803 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
11807 [(set_attr "length" "8")
11808 (set_attr "in_delay_slot" "no")])
11810 ;; Alignment is needed for some constant tables; it may also be added for
11811 ;; Instructions at the start of loops, or after unconditional branches.
11812 ;; ??? We would get more accurate lengths if we did instruction
11813 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
11814 ;; here is too conservative.
11816 ;; align to a two byte boundary
11817 (define_expand "align_2"
11818 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
11822 ;; Align to a four byte boundary.
11823 ;; align_4 and align_log are instructions for the starts of loops, or
11824 ;; after unconditional branches, which may take up extra room.
11825 (define_expand "align_4"
11826 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
11830 ;; Align to a cache line boundary.
11831 (define_insn "align_log"
11832 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
11835 [(set_attr "length" "0")
11836 (set_attr "in_delay_slot" "no")])
11838 ;; Emitted at the end of the literal table, used to emit the
11839 ;; 32bit branch labels if needed.
11840 (define_insn "consttable_end"
11841 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
11844 return output_jump_label_table ();
11846 [(set_attr "in_delay_slot" "no")])
11848 ;; Emitted at the end of the window in the literal table.
11849 (define_insn "consttable_window_end"
11850 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
11853 [(set_attr "length" "0")
11854 (set_attr "in_delay_slot" "no")])
11856 ;; -------------------------------------------------------------------------
11857 ;; Minimum / maximum operations.
11858 ;; -------------------------------------------------------------------------
11860 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
11861 ;; and smax standard name patterns are defined, they will be used during
11862 ;; initial expansion and combine will then be able to form the actual min-max
11864 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
11865 ;; clipped, but there is currently no way of making use of this information.
11866 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11867 (define_expand "<code>si3"
11868 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11869 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11870 (match_operand 2 "const_int_operand")))
11871 (clobber (reg:SI T_REG))])]
11874 /* Force the comparison value into a register, because greater-than
11875 comparisons can work only on registers. Combine will be able to pick up
11876 the constant value from the REG_EQUAL note when trying to form a min-max
11878 operands[2] = force_reg (SImode, operands[2]);
11882 ;; smax (smin (...))
11884 ;; smin (smax (...))
11885 (define_insn_and_split "*clips"
11886 [(set (match_operand:SI 0 "arith_reg_dest")
11887 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
11888 (match_operand 2 "clips_max_const_int"))
11889 (match_operand 3 "clips_min_const_int")))]
11893 [(set (match_dup 0)
11894 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
11896 (define_insn "*clips"
11897 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11898 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
11899 (match_operand 2 "clips_min_const_int"))
11900 (match_operand 3 "clips_max_const_int")))]
11903 if (INTVAL (operands[3]) == 127)
11904 return "clips.b %0";
11905 else if (INTVAL (operands[3]) == 32767)
11906 return "clips.w %0";
11908 gcc_unreachable ();
11910 [(set_attr "type" "arith")])
11912 ;; If the expanded smin or smax patterns were not combined, split them into
11913 ;; a compare and branch sequence, because there are no real smin or smax
11915 (define_insn_and_split "*<code>si3"
11916 [(set (match_operand:SI 0 "arith_reg_dest")
11917 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11918 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
11919 (clobber (reg:SI T_REG))]
11920 "TARGET_SH2A && can_create_pseudo_p ()"
11925 rtx skip_label = gen_label_rtx ();
11926 emit_move_insn (operands[0], operands[1]);
11928 rtx cmp_val = operands[2];
11929 if (satisfies_constraint_M (cmp_val))
11930 cmp_val = const0_rtx;
11932 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
11933 emit_jump_insn (<CODE> == SMIN
11934 ? gen_branch_false (skip_label)
11935 : gen_branch_true (skip_label));
11937 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
11941 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
11942 ;; with a register and a constant.
11943 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
11944 ;; clipped, but there is currently no way of making use of this information.
11945 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11946 (define_expand "uminsi3"
11947 [(set (match_operand:SI 0 "arith_reg_dest")
11948 (umin:SI (match_operand:SI 1 "arith_reg_operand")
11949 (match_operand 2 "const_int_operand")))]
11952 if (INTVAL (operands[2]) == 1)
11954 emit_insn (gen_clipu_one (operands[0], operands[1]));
11957 else if (! clipu_max_const_int (operands[2], VOIDmode))
11961 (define_insn "*clipu"
11962 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11963 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
11964 (match_operand 2 "clipu_max_const_int")))]
11967 if (INTVAL (operands[2]) == 255)
11968 return "clipu.b %0";
11969 else if (INTVAL (operands[2]) == 65535)
11970 return "clipu.w %0";
11972 gcc_unreachable ();
11974 [(set_attr "type" "arith")])
11976 (define_insn_and_split "clipu_one"
11977 [(set (match_operand:SI 0 "arith_reg_dest")
11978 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
11979 (clobber (reg:SI T_REG))]
11982 "&& can_create_pseudo_p ()"
11985 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
11986 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
11990 ;; -------------------------------------------------------------------------
11992 ;; -------------------------------------------------------------------------
11994 ;; String/block move insn.
11996 (define_expand "movmemsi"
11997 [(parallel [(set (mem:BLK (match_operand:BLK 0))
11998 (mem:BLK (match_operand:BLK 1)))
11999 (use (match_operand:SI 2 "nonmemory_operand"))
12000 (use (match_operand:SI 3 "immediate_operand"))
12001 (clobber (reg:SI PR_REG))
12002 (clobber (reg:SI R4_REG))
12003 (clobber (reg:SI R5_REG))
12004 (clobber (reg:SI R0_REG))])]
12005 "TARGET_SH1 && ! TARGET_SH5"
12007 if (expand_block_move (operands))
12013 (define_insn "block_move_real"
12014 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12015 (mem:BLK (reg:SI R5_REG)))
12016 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12017 (clobber (reg:SI PR_REG))
12018 (clobber (reg:SI R0_REG))])]
12019 "TARGET_SH1 && ! TARGET_HARD_SH4"
12021 [(set_attr "type" "sfunc")
12022 (set_attr "needs_delay_slot" "yes")])
12024 (define_insn "block_lump_real"
12025 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12026 (mem:BLK (reg:SI R5_REG)))
12027 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12028 (use (reg:SI R6_REG))
12029 (clobber (reg:SI PR_REG))
12030 (clobber (reg:SI T_REG))
12031 (clobber (reg:SI R4_REG))
12032 (clobber (reg:SI R5_REG))
12033 (clobber (reg:SI R6_REG))
12034 (clobber (reg:SI R0_REG))])]
12035 "TARGET_SH1 && ! TARGET_HARD_SH4"
12037 [(set_attr "type" "sfunc")
12038 (set_attr "needs_delay_slot" "yes")])
12040 (define_insn "block_move_real_i4"
12041 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12042 (mem:BLK (reg:SI R5_REG)))
12043 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12044 (clobber (reg:SI PR_REG))
12045 (clobber (reg:SI R0_REG))
12046 (clobber (reg:SI R1_REG))
12047 (clobber (reg:SI R2_REG))])]
12050 [(set_attr "type" "sfunc")
12051 (set_attr "needs_delay_slot" "yes")])
12053 (define_insn "block_lump_real_i4"
12054 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12055 (mem:BLK (reg:SI R5_REG)))
12056 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12057 (use (reg:SI R6_REG))
12058 (clobber (reg:SI PR_REG))
12059 (clobber (reg:SI T_REG))
12060 (clobber (reg:SI R4_REG))
12061 (clobber (reg:SI R5_REG))
12062 (clobber (reg:SI R6_REG))
12063 (clobber (reg:SI R0_REG))
12064 (clobber (reg:SI R1_REG))
12065 (clobber (reg:SI R2_REG))
12066 (clobber (reg:SI R3_REG))])]
12069 [(set_attr "type" "sfunc")
12070 (set_attr "needs_delay_slot" "yes")])
12072 ;; byte compare pattern
12074 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
12075 (define_insn "cmpstr_t"
12076 [(set (reg:SI T_REG)
12081 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
12082 (match_operand:SI 1 "arith_reg_operand" "r"))
12083 (const_int 8) (const_int 0))
12084 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12085 (const_int 8) (const_int 8)))
12086 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12087 (const_int 8) (const_int 16)))
12088 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12089 (const_int 8) (const_int 24)))
12093 [(set_attr "type" "mt_group")])
12095 (define_expand "cmpstrsi"
12096 [(set (match_operand:SI 0 "register_operand")
12097 (compare:SI (match_operand:BLK 1 "memory_operand")
12098 (match_operand:BLK 2 "memory_operand")))
12099 (use (match_operand 3 "immediate_operand"))]
12100 "TARGET_SH1 && optimize"
12102 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
12108 (define_expand "cmpstrnsi"
12109 [(set (match_operand:SI 0 "register_operand")
12110 (compare:SI (match_operand:BLK 1 "memory_operand")
12111 (match_operand:BLK 2 "memory_operand")))
12112 (use (match_operand:SI 3 "immediate_operand"))
12113 (use (match_operand:SI 4 "immediate_operand"))]
12114 "TARGET_SH1 && optimize"
12116 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
12122 (define_expand "strlensi"
12123 [(set (match_operand:SI 0 "register_operand")
12124 (unspec:SI [(match_operand:BLK 1 "memory_operand")
12125 (match_operand:SI 2 "immediate_operand")
12126 (match_operand:SI 3 "immediate_operand")]
12127 UNSPEC_BUILTIN_STRLEN))]
12128 "TARGET_SH1 && optimize"
12130 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
12136 (define_expand "setmemqi"
12137 [(parallel [(set (match_operand:BLK 0 "memory_operand")
12138 (match_operand 2 "const_int_operand"))
12139 (use (match_operand:QI 1 "const_int_operand"))
12140 (use (match_operand:QI 3 "const_int_operand"))])]
12141 "TARGET_SH1 && optimize"
12143 if (optimize_insn_for_size_p ())
12146 sh_expand_setmem (operands);
12151 ;; -------------------------------------------------------------------------
12152 ;; Floating point instructions.
12153 ;; -------------------------------------------------------------------------
12155 ;; ??? All patterns should have a type attribute.
12157 (define_expand "movpsi"
12158 [(set (match_operand:PSI 0 "register_operand" "")
12159 (match_operand:PSI 1 "general_movsrc_operand" ""))]
12160 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12163 ;; The c / m alternative is a fake to guide reload to load directly into
12164 ;; fpscr, since reload doesn't know how to use post-increment.
12165 ;; TARGET_LEGITIMATE_ADDRESS_P guards about bogus addresses before reload,
12166 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
12167 ;; predicate after reload.
12168 ;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
12169 ;; like a mac -> gpr move.
12170 (define_insn "fpu_switch"
12171 [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
12172 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
12174 && (! reload_completed
12175 || true_regnum (operands[0]) != FPSCR_REG
12176 || !MEM_P (operands[1])
12177 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
12179 ! precision stays the same
12188 [(set_attr "length" "0,2,2,4,2,2,2,2,2")
12189 (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,
12193 [(set (reg:PSI FPSCR_REG)
12194 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12195 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && peep2_reg_dead_p (1, operands[0])"
12198 rtx fpscr, mem, new_insn;
12200 fpscr = SET_DEST (PATTERN (curr_insn));
12201 mem = SET_SRC (PATTERN (curr_insn));
12202 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12204 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12205 add_reg_note (new_insn, REG_INC, operands[0]);
12210 [(set (reg:PSI FPSCR_REG)
12211 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12212 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
12213 && (flag_peephole2 ? epilogue_completed : reload_completed)"
12216 rtx fpscr, mem, new_insn;
12218 fpscr = SET_DEST (PATTERN (curr_insn));
12219 mem = SET_SRC (PATTERN (curr_insn));
12220 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12222 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12223 add_reg_note (new_insn, REG_INC, operands[0]);
12225 if (!find_regno_note (curr_insn, REG_DEAD, true_regnum (operands[0])))
12226 emit_insn (gen_addsi3 (operands[0], operands[0], GEN_INT (-4)));
12230 ;; ??? This uses the fp unit, but has no type indicating that.
12231 ;; If we did that, this would either give a bogus latency or introduce
12232 ;; a bogus FIFO constraint.
12233 ;; Since this insn is currently only used for prologues/epilogues,
12234 ;; it is probably best to claim no function unit, which matches the
12235 ;; current setting.
12236 (define_insn "toggle_sz"
12237 [(set (reg:PSI FPSCR_REG)
12238 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
12239 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12241 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12243 ;; Toggle FPU precision PR mode.
12245 (define_insn "toggle_pr"
12246 [(set (reg:PSI FPSCR_REG)
12247 (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
12250 [(set_attr "type" "fpscr_toggle")])
12252 (define_expand "addsf3"
12253 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12254 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
12255 (match_operand:SF 2 "fp_arith_reg_operand")))]
12256 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12260 expand_sf_binop (&gen_addsf3_i, operands);
12265 (define_insn "*addsf3_media"
12266 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12267 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12268 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12269 "TARGET_SHMEDIA_FPU"
12270 "fadd.s %1, %2, %0"
12271 [(set_attr "type" "fparith_media")])
12273 (define_insn_and_split "unary_sf_op"
12274 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12279 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12280 (match_operator:SF 2 "unary_float_operator"
12281 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12282 (parallel [(match_operand 4
12283 "const_int_operand" "n")]))]))
12284 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12285 "TARGET_SHMEDIA_FPU"
12287 "TARGET_SHMEDIA_FPU && reload_completed"
12288 [(set (match_dup 5) (match_dup 6))]
12290 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12291 rtx op1 = gen_rtx_REG (SFmode,
12292 (true_regnum (operands[1])
12293 + (INTVAL (operands[4]) ^ endian)));
12295 operands[7] = gen_rtx_REG (SFmode,
12296 (true_regnum (operands[0])
12297 + (INTVAL (operands[3]) ^ endian)));
12298 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12300 [(set_attr "type" "fparith_media")])
12302 (define_insn_and_split "binary_sf_op0"
12303 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12305 (match_operator:SF 3 "binary_float_operator"
12306 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12307 (parallel [(const_int 0)]))
12308 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12309 (parallel [(const_int 0)]))])
12312 (parallel [(const_int 1)]))))]
12313 "TARGET_SHMEDIA_FPU"
12315 "&& reload_completed"
12316 [(set (match_dup 4) (match_dup 5))]
12318 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12319 rtx op1 = gen_rtx_REG (SFmode,
12320 true_regnum (operands[1]) + endian);
12321 rtx op2 = gen_rtx_REG (SFmode,
12322 true_regnum (operands[2]) + endian);
12324 operands[4] = gen_rtx_REG (SFmode,
12325 true_regnum (operands[0]) + endian);
12326 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12328 [(set_attr "type" "fparith_media")])
12330 (define_insn_and_split "binary_sf_op1"
12331 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12335 (parallel [(const_int 0)]))
12336 (match_operator:SF 3 "binary_float_operator"
12337 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12338 (parallel [(const_int 1)]))
12339 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12340 (parallel [(const_int 1)]))])))]
12341 "TARGET_SHMEDIA_FPU"
12343 "&& reload_completed"
12344 [(set (match_dup 4) (match_dup 5))]
12346 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12347 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12348 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12350 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12351 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12353 [(set_attr "type" "fparith_media")])
12355 (define_insn "addsf3_i"
12356 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12357 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12358 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12359 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12362 [(set_attr "type" "fp")
12363 (set_attr "fp_mode" "single")])
12365 (define_expand "subsf3"
12366 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12367 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12368 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12369 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12373 expand_sf_binop (&gen_subsf3_i, operands);
12378 (define_insn "*subsf3_media"
12379 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12380 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12381 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12382 "TARGET_SHMEDIA_FPU"
12383 "fsub.s %1, %2, %0"
12384 [(set_attr "type" "fparith_media")])
12386 (define_insn "subsf3_i"
12387 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12388 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12389 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12390 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12393 [(set_attr "type" "fp")
12394 (set_attr "fp_mode" "single")])
12396 (define_expand "mulsf3"
12397 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12398 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12399 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12400 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12404 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2],
12405 get_fpscr_rtx ()));
12410 (define_insn "*mulsf3_media"
12411 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12412 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12413 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12414 "TARGET_SHMEDIA_FPU"
12415 "fmul.s %1, %2, %0"
12416 [(set_attr "type" "fparith_media")])
12418 (define_insn "mulsf3_i"
12419 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12420 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12421 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12422 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12425 [(set_attr "type" "fp")
12426 (set_attr "fp_mode" "single")])
12428 ;; FMA (fused multiply-add) patterns
12429 (define_expand "fmasf4"
12430 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12431 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
12432 (match_operand:SF 2 "fp_arith_reg_operand")
12433 (match_operand:SF 3 "fp_arith_reg_operand")))]
12434 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12438 emit_sf_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
12439 operands[3], get_fpscr_rtx ()));
12444 (define_insn "fmasf4_i"
12445 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12446 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
12447 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12448 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
12449 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
12452 [(set_attr "type" "fp")
12453 (set_attr "fp_mode" "single")])
12455 (define_insn "fmasf4_media"
12456 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12457 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12458 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12459 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12460 "TARGET_SHMEDIA_FPU"
12461 "fmac.s %1, %2, %0"
12462 [(set_attr "type" "fparith_media")])
12464 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
12465 ;; previous transformations. If FMA is generally allowed, let the combine
12466 ;; pass utilize it.
12467 (define_insn_and_split "*fmasf4"
12468 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12469 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
12470 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12471 (match_operand:SF 3 "arith_reg_operand" "0")))
12472 (use (match_operand:PSI 4 "fpscr_operand"))]
12473 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
12475 "&& can_create_pseudo_p ()"
12476 [(parallel [(set (match_dup 0)
12477 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
12478 (use (match_dup 4))])]
12480 /* Change 'b * a + a' into 'a * b + a'.
12481 This is better for register allocation. */
12482 if (REGNO (operands[2]) == REGNO (operands[3]))
12484 rtx tmp = operands[1];
12485 operands[1] = operands[2];
12489 [(set_attr "type" "fp")
12490 (set_attr "fp_mode" "single")])
12492 (define_insn "*fmasf4_media"
12493 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12494 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12495 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12496 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12497 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
12498 "fmac.s %1, %2, %0"
12499 [(set_attr "type" "fparith_media")])
12501 (define_expand "divsf3"
12502 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12503 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
12504 (match_operand:SF 2 "fp_arith_reg_operand")))]
12505 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12509 expand_sf_binop (&gen_divsf3_i, operands);
12514 (define_insn "*divsf3_media"
12515 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12516 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12517 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12518 "TARGET_SHMEDIA_FPU"
12519 "fdiv.s %1, %2, %0"
12520 [(set_attr "type" "fdiv_media")])
12522 (define_insn "divsf3_i"
12523 [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f")
12524 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12525 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12526 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12529 [(set_attr "type" "fdiv")
12530 (set_attr "fp_mode" "single")])
12532 (define_insn "floatdisf2"
12533 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12534 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12535 "TARGET_SHMEDIA_FPU"
12537 [(set_attr "type" "fpconv_media")])
12539 (define_expand "floatsisf2"
12540 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12541 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
12542 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12544 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12546 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1],
12547 get_fpscr_rtx ()));
12552 (define_insn "*floatsisf2_media"
12553 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12554 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12555 "TARGET_SHMEDIA_FPU"
12557 [(set_attr "type" "fpconv_media")])
12559 (define_insn "floatsisf2_i4"
12560 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12561 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
12562 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12563 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12565 [(set_attr "type" "fp")
12566 (set_attr "fp_mode" "single")])
12568 (define_insn "*floatsisf2_ie"
12569 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12570 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
12571 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12573 [(set_attr "type" "fp")])
12575 (define_insn "fix_truncsfdi2"
12576 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12577 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12578 "TARGET_SHMEDIA_FPU"
12580 [(set_attr "type" "fpconv_media")])
12582 (define_expand "fix_truncsfsi2"
12583 [(set (match_operand:SI 0 "fpul_operand" "=y")
12584 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12585 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12587 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12589 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1],
12590 get_fpscr_rtx ()));
12595 (define_insn "*fix_truncsfsi2_media"
12596 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12597 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12598 "TARGET_SHMEDIA_FPU"
12600 [(set_attr "type" "fpconv_media")])
12602 (define_insn "fix_truncsfsi2_i4"
12603 [(set (match_operand:SI 0 "fpul_operand" "=y")
12604 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12605 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12606 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12608 [(set_attr "type" "ftrc_s")
12609 (set_attr "fp_mode" "single")])
12611 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
12612 ;; fix_truncsfsi2_i4.
12613 ;; (define_insn "fix_truncsfsi2_i4_2"
12614 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12615 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12616 ;; (use (reg:PSI FPSCR_REG))
12617 ;; (clobber (reg:SI FPUL_REG))]
12620 ;; [(set_attr "length" "4")
12621 ;; (set_attr "fp_mode" "single")])
12624 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12625 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12626 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
12627 ;; (clobber (reg:SI FPUL_REG))]
12629 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
12630 ;; (use (match_dup 2))])
12631 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
12633 (define_insn "*fixsfsi"
12634 [(set (match_operand:SI 0 "fpul_operand" "=y")
12635 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12636 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12638 [(set_attr "type" "fp")])
12640 (define_insn "cmpgtsf_t"
12641 [(set (reg:SI T_REG)
12642 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12643 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12644 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12646 [(set_attr "type" "fp_cmp")
12647 (set_attr "fp_mode" "single")])
12649 (define_insn "cmpeqsf_t"
12650 [(set (reg:SI T_REG)
12651 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12652 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12653 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12655 [(set_attr "type" "fp_cmp")
12656 (set_attr "fp_mode" "single")])
12658 (define_insn "ieee_ccmpeqsf_t"
12659 [(set (reg:SI T_REG)
12660 (ior:SI (reg:SI T_REG)
12661 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12662 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
12663 "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12665 return output_ieee_ccmpeq (insn, operands);
12667 [(set_attr "length" "4")])
12670 (define_insn "cmpgtsf_t_i4"
12671 [(set (reg:SI T_REG)
12672 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12673 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12674 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12675 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12677 [(set_attr "type" "fp_cmp")
12678 (set_attr "fp_mode" "single")])
12680 (define_insn "cmpeqsf_t_i4"
12681 [(set (reg:SI T_REG)
12682 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12683 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12684 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12685 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12687 [(set_attr "type" "fp_cmp")
12688 (set_attr "fp_mode" "single")])
12690 (define_insn "*ieee_ccmpeqsf_t_4"
12691 [(set (reg:SI T_REG)
12692 (ior:SI (reg:SI T_REG)
12693 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12694 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
12695 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12696 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12698 return output_ieee_ccmpeq (insn, operands);
12700 [(set_attr "length" "4")
12701 (set_attr "fp_mode" "single")])
12703 (define_insn "cmpeqsf_media"
12704 [(set (match_operand:SI 0 "register_operand" "=r")
12705 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12706 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12707 "TARGET_SHMEDIA_FPU"
12708 "fcmpeq.s %1, %2, %0"
12709 [(set_attr "type" "fcmp_media")])
12711 (define_insn "cmpgtsf_media"
12712 [(set (match_operand:SI 0 "register_operand" "=r")
12713 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12714 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12715 "TARGET_SHMEDIA_FPU"
12716 "fcmpgt.s %1, %2, %0"
12717 [(set_attr "type" "fcmp_media")])
12719 (define_insn "cmpgesf_media"
12720 [(set (match_operand:SI 0 "register_operand" "=r")
12721 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12722 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12723 "TARGET_SHMEDIA_FPU"
12724 "fcmpge.s %1, %2, %0"
12725 [(set_attr "type" "fcmp_media")])
12727 (define_insn "cmpunsf_media"
12728 [(set (match_operand:SI 0 "register_operand" "=r")
12729 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12730 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12731 "TARGET_SHMEDIA_FPU"
12732 "fcmpun.s %1, %2, %0"
12733 [(set_attr "type" "fcmp_media")])
12735 (define_expand "cbranchsf4"
12737 (if_then_else (match_operator 0 "sh_float_comparison_operator"
12738 [(match_operand:SF 1 "arith_operand" "")
12739 (match_operand:SF 2 "arith_operand" "")])
12740 (match_operand 3 "" "")
12742 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12744 if (TARGET_SHMEDIA)
12745 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
12748 sh_emit_compare_and_branch (operands, SFmode);
12752 (define_expand "negsf2"
12753 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12754 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12755 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12759 expand_sf_unop (&gen_negsf2_i, operands);
12764 (define_insn "*negsf2_media"
12765 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12766 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12767 "TARGET_SHMEDIA_FPU"
12769 [(set_attr "type" "fmove_media")])
12771 (define_insn "negsf2_i"
12772 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12773 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12774 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12777 [(set_attr "type" "fmove")
12778 (set_attr "fp_mode" "single")])
12780 (define_expand "sqrtsf2"
12781 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12782 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12783 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
12787 expand_sf_unop (&gen_sqrtsf2_i, operands);
12792 (define_insn "*sqrtsf2_media"
12793 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12794 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12795 "TARGET_SHMEDIA_FPU"
12797 [(set_attr "type" "fdiv_media")])
12799 (define_insn "sqrtsf2_i"
12800 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12801 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12802 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12805 [(set_attr "type" "fdiv")
12806 (set_attr "fp_mode" "single")])
12808 (define_insn "rsqrtsf2"
12809 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12810 (div:SF (match_operand:SF 1 "immediate_operand" "i")
12811 (sqrt:SF (match_operand:SF 2 "fp_arith_reg_operand" "0"))))
12812 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12813 "TARGET_FPU_ANY && TARGET_FSRRA
12814 && operands[1] == CONST1_RTX (SFmode)"
12816 [(set_attr "type" "fsrra")
12817 (set_attr "fp_mode" "single")])
12819 ;; When the sincos pattern is defined, the builtin functions sin and cos
12820 ;; will be expanded to the sincos pattern and one of the output values will
12822 (define_expand "sincossf3"
12823 [(set (match_operand:SF 0 "nonimmediate_operand")
12824 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
12825 (set (match_operand:SF 1 "nonimmediate_operand")
12826 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
12827 "TARGET_FPU_ANY && TARGET_FSCA"
12829 rtx scaled = gen_reg_rtx (SFmode);
12830 rtx truncated = gen_reg_rtx (SImode);
12831 rtx fsca = gen_reg_rtx (V2SFmode);
12832 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
12834 emit_sf_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
12835 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
12836 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
12837 get_fpscr_rtx ()));
12839 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
12840 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
12844 (define_insn_and_split "fsca"
12845 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12847 (unspec:SF [(mult:SF
12848 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
12849 (match_operand:SF 2 "fsca_scale_factor" "i"))
12851 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
12853 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12854 "TARGET_FPU_ANY && TARGET_FSCA"
12856 "&& !fpul_operand (operands[1], SImode)"
12859 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
12860 to a simple reg, otherwise reload will have trouble reloading the
12861 pseudo into fpul. */
12862 rtx x = XEXP (operands[1], 0);
12863 while (x != NULL_RTX && !fpul_operand (x, SImode))
12865 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
12869 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
12870 emit_insn (gen_fsca (operands[0], x, operands[2], operands[3]));
12873 [(set_attr "type" "fsca")
12874 (set_attr "fp_mode" "single")])
12876 (define_expand "abssf2"
12877 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12878 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12879 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12883 expand_sf_unop (&gen_abssf2_i, operands);
12888 (define_insn "*abssf2_media"
12889 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12890 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12891 "TARGET_SHMEDIA_FPU"
12893 [(set_attr "type" "fmove_media")])
12895 (define_insn "abssf2_i"
12896 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12897 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12898 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12901 [(set_attr "type" "fmove")
12902 (set_attr "fp_mode" "single")])
12904 (define_expand "adddf3"
12905 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12906 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12907 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12908 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12910 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12912 expand_df_binop (&gen_adddf3_i, operands);
12917 (define_insn "*adddf3_media"
12918 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12919 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12920 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12921 "TARGET_SHMEDIA_FPU"
12922 "fadd.d %1, %2, %0"
12923 [(set_attr "type" "dfparith_media")])
12925 (define_insn "adddf3_i"
12926 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12927 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12928 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12929 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12930 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12932 [(set_attr "type" "dfp_arith")
12933 (set_attr "fp_mode" "double")])
12935 (define_expand "subdf3"
12936 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12937 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12938 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12939 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12941 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12943 expand_df_binop (&gen_subdf3_i, operands);
12948 (define_insn "*subdf3_media"
12949 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12950 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12951 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12952 "TARGET_SHMEDIA_FPU"
12953 "fsub.d %1, %2, %0"
12954 [(set_attr "type" "dfparith_media")])
12956 (define_insn "subdf3_i"
12957 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12958 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12959 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12960 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12961 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12963 [(set_attr "type" "dfp_arith")
12964 (set_attr "fp_mode" "double")])
12966 (define_expand "muldf3"
12967 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12968 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12969 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12970 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12972 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12974 expand_df_binop (&gen_muldf3_i, operands);
12979 (define_insn "*muldf3_media"
12980 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12981 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12982 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12983 "TARGET_SHMEDIA_FPU"
12984 "fmul.d %1, %2, %0"
12985 [(set_attr "type" "dfmul_media")])
12987 (define_insn "muldf3_i"
12988 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12989 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12990 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12991 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12992 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12994 [(set_attr "type" "dfp_mul")
12995 (set_attr "fp_mode" "double")])
12997 (define_expand "divdf3"
12998 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12999 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13000 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13001 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13003 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13005 expand_df_binop (&gen_divdf3_i, operands);
13010 (define_insn "*divdf3_media"
13011 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13012 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
13013 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13014 "TARGET_SHMEDIA_FPU"
13015 "fdiv.d %1, %2, %0"
13016 [(set_attr "type" "dfdiv_media")])
13018 (define_insn "divdf3_i"
13019 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13020 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13021 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13022 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
13023 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13025 [(set_attr "type" "dfdiv")
13026 (set_attr "fp_mode" "double")])
13028 (define_insn "floatdidf2"
13029 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13030 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
13031 "TARGET_SHMEDIA_FPU"
13033 [(set_attr "type" "dfpconv_media")])
13035 (define_expand "floatsidf2"
13036 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13037 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
13038 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13040 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13042 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
13043 get_fpscr_rtx ()));
13048 (define_insn "*floatsidf2_media"
13049 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13050 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
13051 "TARGET_SHMEDIA_FPU"
13053 [(set_attr "type" "dfpconv_media")])
13055 (define_insn "floatsidf2_i"
13056 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13057 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
13058 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13059 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13061 [(set_attr "type" "dfp_conv")
13062 (set_attr "fp_mode" "double")])
13064 (define_insn "fix_truncdfdi2"
13065 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
13066 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13067 "TARGET_SHMEDIA_FPU"
13069 [(set_attr "type" "dfpconv_media")])
13071 (define_expand "fix_truncdfsi2"
13072 [(set (match_operand:SI 0 "fpul_operand" "")
13073 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13074 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13076 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13078 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
13079 get_fpscr_rtx ()));
13084 (define_insn "*fix_truncdfsi2_media"
13085 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13086 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13087 "TARGET_SHMEDIA_FPU"
13089 [(set_attr "type" "dfpconv_media")])
13091 (define_insn "fix_truncdfsi2_i"
13092 [(set (match_operand:SI 0 "fpul_operand" "=y")
13093 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13094 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13095 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13097 [(set_attr "type" "dfp_conv")
13098 (set_attr "dfp_comp" "no")
13099 (set_attr "fp_mode" "double")])
13101 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
13102 ;; fix_truncdfsi2_i.
13103 ;; (define_insn "fix_truncdfsi2_i4"
13104 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13105 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
13106 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
13107 ;; (clobber (reg:SI FPUL_REG))]
13110 ;; [(set_attr "length" "4")
13111 ;; (set_attr "fp_mode" "double")])
13114 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13115 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
13116 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
13117 ;; (clobber (reg:SI FPUL_REG))]
13119 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
13120 ;; (use (match_dup 2))])
13121 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
13123 (define_insn "cmpgtdf_t"
13124 [(set (reg:SI T_REG)
13125 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13126 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13127 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13128 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13130 [(set_attr "type" "dfp_cmp")
13131 (set_attr "fp_mode" "double")])
13133 (define_insn "cmpeqdf_t"
13134 [(set (reg:SI T_REG)
13135 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13136 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13137 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13138 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13140 [(set_attr "type" "dfp_cmp")
13141 (set_attr "fp_mode" "double")])
13143 (define_insn "*ieee_ccmpeqdf_t"
13144 [(set (reg:SI T_REG)
13145 (ior:SI (reg:SI T_REG)
13146 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13147 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
13148 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13149 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13151 return output_ieee_ccmpeq (insn, operands);
13153 [(set_attr "length" "4")
13154 (set_attr "fp_mode" "double")])
13156 (define_insn "cmpeqdf_media"
13157 [(set (match_operand:SI 0 "register_operand" "=r")
13158 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13159 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13160 "TARGET_SHMEDIA_FPU"
13161 "fcmpeq.d %1,%2,%0"
13162 [(set_attr "type" "fcmp_media")])
13164 (define_insn "cmpgtdf_media"
13165 [(set (match_operand:SI 0 "register_operand" "=r")
13166 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13167 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13168 "TARGET_SHMEDIA_FPU"
13169 "fcmpgt.d %1,%2,%0"
13170 [(set_attr "type" "fcmp_media")])
13172 (define_insn "cmpgedf_media"
13173 [(set (match_operand:SI 0 "register_operand" "=r")
13174 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13175 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13176 "TARGET_SHMEDIA_FPU"
13177 "fcmpge.d %1,%2,%0"
13178 [(set_attr "type" "fcmp_media")])
13180 (define_insn "cmpundf_media"
13181 [(set (match_operand:SI 0 "register_operand" "=r")
13182 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13183 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13184 "TARGET_SHMEDIA_FPU"
13185 "fcmpun.d %1,%2,%0"
13186 [(set_attr "type" "fcmp_media")])
13188 (define_expand "cbranchdf4"
13190 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13191 [(match_operand:DF 1 "arith_operand" "")
13192 (match_operand:DF 2 "arith_operand" "")])
13193 (match_operand 3 "" "")
13195 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13197 if (TARGET_SHMEDIA)
13198 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13201 sh_emit_compare_and_branch (operands, DFmode);
13205 (define_expand "negdf2"
13206 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13207 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13208 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13210 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13212 expand_df_unop (&gen_negdf2_i, operands);
13217 (define_insn "*negdf2_media"
13218 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13219 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13220 "TARGET_SHMEDIA_FPU"
13222 [(set_attr "type" "fmove_media")])
13224 (define_insn "negdf2_i"
13225 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13226 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13227 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13228 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13230 [(set_attr "type" "fmove")
13231 (set_attr "fp_mode" "double")])
13233 (define_expand "sqrtdf2"
13234 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13235 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13236 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13238 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13240 expand_df_unop (&gen_sqrtdf2_i, operands);
13245 (define_insn "*sqrtdf2_media"
13246 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13247 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13248 "TARGET_SHMEDIA_FPU"
13250 [(set_attr "type" "dfdiv_media")])
13252 (define_insn "sqrtdf2_i"
13253 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13254 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13255 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13256 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13258 [(set_attr "type" "dfdiv")
13259 (set_attr "fp_mode" "double")])
13261 (define_expand "absdf2"
13262 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13263 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13264 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13266 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13268 expand_df_unop (&gen_absdf2_i, operands);
13273 (define_insn "*absdf2_media"
13274 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13275 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13276 "TARGET_SHMEDIA_FPU"
13278 [(set_attr "type" "fmove_media")])
13280 (define_insn "absdf2_i"
13281 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13282 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13283 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13284 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13286 [(set_attr "type" "fmove")
13287 (set_attr "fp_mode" "double")])
13289 (define_expand "extendsfdf2"
13290 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13291 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13292 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13294 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13296 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
13297 get_fpscr_rtx ()));
13302 (define_insn "*extendsfdf2_media"
13303 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13304 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13305 "TARGET_SHMEDIA_FPU"
13307 [(set_attr "type" "dfpconv_media")])
13309 (define_insn "extendsfdf2_i4"
13310 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13311 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13312 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13313 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13315 [(set_attr "type" "fp")
13316 (set_attr "fp_mode" "double")])
13318 (define_expand "truncdfsf2"
13319 [(set (match_operand:SF 0 "fpul_operand" "")
13320 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13321 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13323 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13325 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
13326 get_fpscr_rtx ()));
13331 (define_insn "*truncdfsf2_media"
13332 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13333 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13334 "TARGET_SHMEDIA_FPU"
13336 [(set_attr "type" "dfpconv_media")])
13338 (define_insn "truncdfsf2_i4"
13339 [(set (match_operand:SF 0 "fpul_operand" "=y")
13340 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13341 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13342 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13344 [(set_attr "type" "fp")
13345 (set_attr "fp_mode" "double")])
13347 ;; -------------------------------------------------------------------------
13348 ;; Bit field extract patterns.
13349 ;; -------------------------------------------------------------------------
13351 ;; These give better code for packed bitfields, because they allow
13352 ;; auto-increment addresses to be generated.
13354 (define_expand "insv"
13355 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13356 (match_operand:SI 1 "immediate_operand" "")
13357 (match_operand:SI 2 "immediate_operand" ""))
13358 (match_operand:SI 3 "general_operand" ""))]
13359 "TARGET_SH1 && TARGET_BIG_ENDIAN"
13361 rtx addr_target, orig_address, shift_reg, qi_val;
13362 HOST_WIDE_INT bitsize, size, v = 0;
13363 rtx x = operands[3];
13365 if (TARGET_SH2A && TARGET_BITOPS
13366 && (satisfies_constraint_Sbw (operands[0])
13367 || satisfies_constraint_Sbv (operands[0]))
13368 && satisfies_constraint_M (operands[1])
13369 && satisfies_constraint_K03 (operands[2]))
13371 if (satisfies_constraint_N (operands[3]))
13373 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13376 else if (satisfies_constraint_M (operands[3]))
13378 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13381 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13382 && satisfies_constraint_M (operands[1]))
13384 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13387 else if (REG_P (operands[3])
13388 && satisfies_constraint_M (operands[1]))
13390 emit_insn (gen_bld_reg (operands[3], const0_rtx));
13391 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13395 /* ??? expmed doesn't care for non-register predicates. */
13396 if (! memory_operand (operands[0], VOIDmode)
13397 || ! immediate_operand (operands[1], VOIDmode)
13398 || ! immediate_operand (operands[2], VOIDmode)
13399 || ! general_operand (x, VOIDmode))
13401 /* If this isn't a 16 / 24 / 32 bit field, or if
13402 it doesn't start on a byte boundary, then fail. */
13403 bitsize = INTVAL (operands[1]);
13404 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13405 || (INTVAL (operands[2]) % 8) != 0)
13408 size = bitsize / 8;
13409 orig_address = XEXP (operands[0], 0);
13410 shift_reg = gen_reg_rtx (SImode);
13411 if (CONST_INT_P (x))
13414 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13418 emit_insn (gen_movsi (shift_reg, operands[3]));
13419 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13421 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13422 orig_address, size - 1));
13424 operands[0] = replace_equiv_address (operands[0], addr_target);
13425 emit_insn (gen_movqi (operands[0], qi_val));
13429 if (CONST_INT_P (x))
13431 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13434 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13435 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13437 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13438 emit_insn (gen_movqi (operands[0], qi_val));
13444 (define_insn "movua"
13445 [(set (match_operand:SI 0 "register_operand" "=z")
13446 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13450 [(set_attr "type" "movua")])
13452 ;; We shouldn't need this, but cse replaces increments with references
13453 ;; to other regs before flow has a chance to create post_inc
13454 ;; addressing modes, and only postreload's cse_move2add brings the
13455 ;; increments back to a usable form.
13457 [(set (match_operand:SI 0 "register_operand" "")
13458 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13459 (const_int 32) (const_int 0)))
13460 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13461 "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
13462 [(set (match_operand:SI 0 "register_operand" "")
13463 (sign_extract:SI (mem:SI (post_inc:SI
13464 (match_operand:SI 1 "register_operand" "")))
13465 (const_int 32) (const_int 0)))]
13468 (define_expand "extv"
13469 [(set (match_operand:SI 0 "register_operand" "")
13470 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13471 (match_operand 2 "const_int_operand" "")
13472 (match_operand 3 "const_int_operand" "")))]
13473 "TARGET_SH4A_ARCH || TARGET_SH2A"
13475 if (TARGET_SH2A && TARGET_BITOPS
13476 && (satisfies_constraint_Sbw (operands[1])
13477 || satisfies_constraint_Sbv (operands[1]))
13478 && satisfies_constraint_M (operands[2])
13479 && satisfies_constraint_K03 (operands[3]))
13481 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13482 if (REGNO (operands[0]) != T_REG)
13483 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13486 if (TARGET_SH4A_ARCH
13487 && INTVAL (operands[2]) == 32
13488 && INTVAL (operands[3]) == 0
13489 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13491 rtx src = adjust_address (operands[1], BLKmode, 0);
13492 set_mem_size (src, 4);
13493 emit_insn (gen_movua (operands[0], src));
13500 (define_expand "extzv"
13501 [(set (match_operand:SI 0 "register_operand" "")
13502 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13503 (match_operand 2 "const_int_operand" "")
13504 (match_operand 3 "const_int_operand" "")))]
13505 "TARGET_SH4A_ARCH || TARGET_SH2A"
13507 if (TARGET_SH2A && TARGET_BITOPS
13508 && (satisfies_constraint_Sbw (operands[1])
13509 || satisfies_constraint_Sbv (operands[1]))
13510 && satisfies_constraint_M (operands[2])
13511 && satisfies_constraint_K03 (operands[3]))
13513 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13514 if (REGNO (operands[0]) != T_REG)
13515 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13518 if (TARGET_SH4A_ARCH
13519 && INTVAL (operands[2]) == 32
13520 && INTVAL (operands[3]) == 0
13521 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13523 rtx src = adjust_address (operands[1], BLKmode, 0);
13524 set_mem_size (src, 4);
13525 emit_insn (gen_movua (operands[0], src));
13532 ;; SH2A instructions for bitwise operations.
13533 ;; FIXME: Convert multiple instruction insns to insn_and_split.
13534 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
13536 ;; Clear a bit in a memory location.
13537 (define_insn "bclr_m2a"
13538 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13540 (not:QI (ashift:QI (const_int 1)
13541 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13543 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13546 bclr.b %1,@(0,%t0)"
13547 [(set_attr "length" "4,4")])
13549 (define_insn "bclrmem_m2a"
13550 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13551 (and:QI (match_dup 0)
13552 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
13553 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
13556 bclr.b %W1,@(0,%t0)"
13557 [(set_attr "length" "4,4")])
13559 ;; Set a bit in a memory location.
13560 (define_insn "bset_m2a"
13561 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13563 (ashift:QI (const_int 1)
13564 (match_operand:QI 1 "const_int_operand" "K03,K03"))
13566 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13569 bset.b %1,@(0,%t0)"
13570 [(set_attr "length" "4,4")])
13572 (define_insn "bsetmem_m2a"
13573 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13574 (ior:QI (match_dup 0)
13575 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
13576 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
13579 bset.b %V1,@(0,%t0)"
13580 [(set_attr "length" "4,4")])
13582 ;;; Transfer the contents of the T bit to a specified bit of memory.
13583 (define_insn "bst_m2a"
13584 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
13585 (if_then_else (eq (reg:SI T_REG) (const_int 0))
13587 (not:QI (ashift:QI (const_int 1)
13588 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13591 (ashift:QI (const_int 1) (match_dup 1))
13593 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13597 [(set_attr "length" "4")])
13599 ;; Store a specified bit of memory in the T bit.
13600 (define_insn "bld_m2a"
13601 [(set (reg:SI T_REG)
13603 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
13605 (match_operand 1 "const_int_operand" "K03,K03")))]
13606 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13610 [(set_attr "length" "4,4")])
13612 ;; Store a specified bit of memory in the T bit.
13613 (define_insn "bldsign_m2a"
13614 [(set (reg:SI T_REG)
13616 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13618 (match_operand 1 "const_int_operand" "K03,K03")))]
13619 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13623 [(set_attr "length" "4,4")])
13625 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
13626 (define_insn "bld_reg"
13627 [(set (reg:SI T_REG)
13628 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
13630 (match_operand 1 "const_int_operand" "K03")))]
13631 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13634 (define_insn "*bld_regqi"
13635 [(set (reg:SI T_REG)
13636 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
13638 (match_operand 1 "const_int_operand" "K03")))]
13639 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13642 ;; Take logical and of a specified bit of memory with the T bit and
13643 ;; store its result in the T bit.
13644 (define_insn "band_m2a"
13645 [(set (reg:SI T_REG)
13646 (and:SI (reg:SI T_REG)
13648 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13650 (match_operand 1 "const_int_operand" "K03,K03"))))]
13651 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13654 band.b %1,@(0,%t0)"
13655 [(set_attr "length" "4,4")])
13657 (define_insn "bandreg_m2a"
13658 [(set (match_operand:SI 0 "register_operand" "=r,r")
13659 (and:SI (zero_extract:SI
13660 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13662 (match_operand 2 "const_int_operand" "K03,K03"))
13663 (match_operand:SI 3 "register_operand" "r,r")))]
13664 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13666 static const char* alt[] =
13668 "band.b %2,%1" "\n"
13671 "band.b %2,@(0,%t1)" "\n"
13674 return alt[which_alternative];
13676 [(set_attr "length" "6,6")])
13678 ;; Take logical or of a specified bit of memory with the T bit and
13679 ;; store its result in the T bit.
13680 (define_insn "bor_m2a"
13681 [(set (reg:SI T_REG)
13682 (ior:SI (reg:SI T_REG)
13684 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13686 (match_operand 1 "const_int_operand" "K03,K03"))))]
13687 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13691 [(set_attr "length" "4,4")])
13693 (define_insn "borreg_m2a"
13694 [(set (match_operand:SI 0 "register_operand" "=r,r")
13695 (ior:SI (zero_extract:SI
13696 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13698 (match_operand 2 "const_int_operand" "K03,K03"))
13699 (match_operand:SI 3 "register_operand" "=r,r")))]
13700 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13702 static const char* alt[] =
13707 "bor.b %2,@(0,%t1)" "\n"
13710 return alt[which_alternative];
13712 [(set_attr "length" "6,6")])
13714 ;; Take exclusive or of a specified bit of memory with the T bit and
13715 ;; store its result in the T bit.
13716 (define_insn "bxor_m2a"
13717 [(set (reg:SI T_REG)
13718 (xor:SI (reg:SI T_REG)
13720 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13722 (match_operand 1 "const_int_operand" "K03,K03"))))]
13723 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13726 bxor.b %1,@(0,%t0)"
13727 [(set_attr "length" "4,4")])
13729 (define_insn "bxorreg_m2a"
13730 [(set (match_operand:SI 0 "register_operand" "=r,r")
13731 (xor:SI (zero_extract:SI
13732 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13734 (match_operand 2 "const_int_operand" "K03,K03"))
13735 (match_operand:SI 3 "register_operand" "=r,r")))]
13736 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13738 static const char* alt[] =
13740 "bxor.b %2,%1" "\n"
13743 "bxor.b %2,@(0,%t1)" "\n"
13746 return alt[which_alternative];
13748 [(set_attr "length" "6,6")])
13750 ;; -------------------------------------------------------------------------
13752 ;; -------------------------------------------------------------------------
13753 ;; This matches cases where the bit in a memory location is set.
13755 [(set (match_operand:SI 0 "register_operand")
13756 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13758 (ior:SI (match_dup 0)
13759 (match_operand:SI 2 "const_int_operand")))
13761 (match_operand 3 "arith_reg_operand"))]
13762 "TARGET_SH2A && TARGET_BITOPS
13763 && satisfies_constraint_Pso (operands[2])
13764 && REGNO (operands[0]) == REGNO (operands[3])"
13765 [(set (match_dup 1)
13766 (ior:QI (match_dup 1) (match_dup 2)))]
13769 ;; This matches cases where the bit in a memory location is cleared.
13771 [(set (match_operand:SI 0 "register_operand")
13772 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13774 (and:SI (match_dup 0)
13775 (match_operand:SI 2 "const_int_operand")))
13777 (match_operand 3 "arith_reg_operand"))]
13778 "TARGET_SH2A && TARGET_BITOPS
13779 && satisfies_constraint_Psz (operands[2])
13780 && REGNO (operands[0]) == REGNO (operands[3])"
13781 [(set (match_dup 1)
13782 (and:QI (match_dup 1) (match_dup 2)))]
13785 ;; This matches cases where a stack pointer increment at the start of the
13786 ;; epilogue combines with a stack slot read loading the return value.
13788 [(set (match_operand:SI 0 "arith_reg_operand" "")
13789 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
13790 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13791 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
13794 ;; See the comment on the dt combiner pattern above.
13796 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13797 (plus:SI (match_dup 0)
13799 (set (reg:SI T_REG)
13800 (eq:SI (match_dup 0) (const_int 0)))]
13804 ;; The following peepholes fold load sequences for which reload was not
13805 ;; able to generate a displacement addressing move insn.
13806 ;; This can happen when reload has to transform a move insn
13807 ;; without displacement into one with displacement. Or when reload can't
13808 ;; fit a displacement into the insn's constraints. In the latter case, the
13809 ;; load destination reg remains at r0, which reload compensates by inserting
13810 ;; another mov insn.
13814 ;; mov.{b,w} @(r0,r15),r0
13817 ;; mov.{b,w} @(54,r15),r3
13820 [(set (match_operand:SI 0 "arith_reg_dest" "")
13821 (match_operand:SI 1 "const_int_operand" ""))
13822 (set (match_operand:SI 2 "arith_reg_dest" "")
13824 (mem:QI (plus:SI (match_dup 0)
13825 (match_operand:SI 3 "arith_reg_operand" "")))))
13826 (set (match_operand:QI 4 "arith_reg_dest" "")
13827 (match_operand:QI 5 "arith_reg_operand" ""))]
13829 && sh_legitimate_index_p (QImode, operands[1], true, true)
13830 && REGNO (operands[2]) == REGNO (operands[5])
13831 && peep2_reg_dead_p (3, operands[5])"
13832 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
13836 [(set (match_operand:SI 0 "arith_reg_dest" "")
13837 (match_operand:SI 1 "const_int_operand" ""))
13838 (set (match_operand:SI 2 "arith_reg_dest" "")
13840 (mem:HI (plus:SI (match_dup 0)
13841 (match_operand:SI 3 "arith_reg_operand" "")))))
13842 (set (match_operand:HI 4 "arith_reg_dest" "")
13843 (match_operand:HI 5 "arith_reg_operand" ""))]
13845 && sh_legitimate_index_p (HImode, operands[1], true, true)
13846 && REGNO (operands[2]) == REGNO (operands[5])
13847 && peep2_reg_dead_p (3, operands[5])"
13848 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
13853 ;; mov.{b,w} @(r0,r15),r1
13855 ;; mov.{b,w} @(54,r15),r1
13858 [(set (match_operand:SI 0 "arith_reg_dest" "")
13859 (match_operand:SI 1 "const_int_operand" ""))
13860 (set (match_operand:SI 2 "arith_reg_dest" "")
13862 (mem:QI (plus:SI (match_dup 0)
13863 (match_operand:SI 3 "arith_reg_operand" "")))))]
13865 && sh_legitimate_index_p (QImode, operands[1], true, true)
13866 && (peep2_reg_dead_p (2, operands[0])
13867 || REGNO (operands[0]) == REGNO (operands[2]))"
13868 [(set (match_dup 2)
13869 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
13873 [(set (match_operand:SI 0 "arith_reg_dest" "")
13874 (match_operand:SI 1 "const_int_operand" ""))
13875 (set (match_operand:SI 2 "arith_reg_dest" "")
13877 (mem:HI (plus:SI (match_dup 0)
13878 (match_operand:SI 3 "arith_reg_operand" "")))))]
13880 && sh_legitimate_index_p (HImode, operands[1], true, true)
13881 && (peep2_reg_dead_p (2, operands[0])
13882 || REGNO (operands[0]) == REGNO (operands[2]))"
13883 [(set (match_dup 2)
13884 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
13888 ;; mov.{b,w} @(r0,r15),r0
13891 ;; mov.{b,w} @(r0,r15),r3
13893 ;; This can happen when initially a displacement address is picked, where
13894 ;; the destination reg is fixed to r0, and then the address is transformed
13895 ;; into 'r0 + reg'.
13897 [(set (match_operand:SI 0 "arith_reg_dest" "")
13899 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13900 (match_operand:SI 2 "arith_reg_operand" "")))))
13901 (set (match_operand:QI 3 "arith_reg_dest" "")
13902 (match_operand:QI 4 "arith_reg_operand" ""))]
13904 && REGNO (operands[0]) == REGNO (operands[4])
13905 && peep2_reg_dead_p (2, operands[0])"
13906 [(set (match_dup 3)
13907 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
13911 [(set (match_operand:SI 0 "arith_reg_dest" "")
13913 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13914 (match_operand:SI 2 "arith_reg_operand" "")))))
13915 (set (match_operand:HI 3 "arith_reg_dest" "")
13916 (match_operand:HI 4 "arith_reg_operand" ""))]
13918 && REGNO (operands[0]) == REGNO (operands[4])
13919 && peep2_reg_dead_p (2, operands[0])"
13920 [(set (match_dup 3)
13921 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
13925 [(set (match_operand:SI 0 "register_operand" "=r")
13926 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13927 (set (mem:SF (match_dup 0))
13928 (match_operand:SF 2 "general_movsrc_operand" ""))]
13929 "TARGET_SH1 && REGNO (operands[0]) == 0
13930 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13931 || (GET_CODE (operands[2]) == SUBREG
13932 && REGNO (SUBREG_REG (operands[2])) < 16))
13933 && reg_unused_after (operands[0], insn)"
13934 "mov.l %2,@(%0,%1)")
13937 [(set (match_operand:SI 0 "register_operand" "=r")
13938 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13939 (set (match_operand:SF 2 "general_movdst_operand" "")
13941 (mem:SF (match_dup 0)))]
13942 "TARGET_SH1 && REGNO (operands[0]) == 0
13943 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13944 || (GET_CODE (operands[2]) == SUBREG
13945 && REGNO (SUBREG_REG (operands[2])) < 16))
13946 && reg_unused_after (operands[0], insn)"
13947 "mov.l @(%0,%1),%2")
13950 [(set (match_operand:SI 0 "register_operand" "=r")
13951 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13952 (set (mem:SF (match_dup 0))
13953 (match_operand:SF 2 "general_movsrc_operand" ""))]
13954 "TARGET_SH2E && REGNO (operands[0]) == 0
13955 && ((REG_P (operands[2])
13956 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13957 || (GET_CODE (operands[2]) == SUBREG
13958 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13959 && reg_unused_after (operands[0], insn)"
13960 "fmov{.s|} %2,@(%0,%1)")
13963 [(set (match_operand:SI 0 "register_operand" "=r")
13964 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13965 (set (match_operand:SF 2 "general_movdst_operand" "")
13967 (mem:SF (match_dup 0)))]
13968 "TARGET_SH2E && REGNO (operands[0]) == 0
13969 && ((REG_P (operands[2])
13970 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13971 || (GET_CODE (operands[2]) == SUBREG
13972 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13973 && reg_unused_after (operands[0], insn)"
13974 "fmov{.s|} @(%0,%1),%2")
13976 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
13977 (define_insn "sp_switch_1"
13978 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
13979 UNSPECV_SP_SWITCH_B))]
13982 return "mov.l r0,@-r15" "\n"
13983 " mov.l %0,r0" "\n"
13984 " mov.l @r0,r0" "\n"
13985 " mov.l r15,@-r0" "\n"
13988 [(set_attr "length" "10")])
13990 ;; Switch back to the original stack for interrupt functions with the
13991 ;; sp_switch attribute.
13992 (define_insn "sp_switch_2"
13993 [(unspec_volatile [(const_int 0)]
13994 UNSPECV_SP_SWITCH_E)]
13997 return "mov.l @r15,r15" "\n"
14000 [(set_attr "length" "4")])
14002 ;; -------------------------------------------------------------------------
14003 ;; Integer vector moves
14004 ;; -------------------------------------------------------------------------
14006 (define_expand "movv8qi"
14007 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
14008 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
14011 prepare_move_operands (operands, V8QImode);
14014 (define_insn "movv8qi_i"
14015 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
14016 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14018 && (register_operand (operands[0], V8QImode)
14019 || sh_register_operand (operands[1], V8QImode))"
14026 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14027 (set_attr "length" "4,4,16,4,4")])
14030 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
14031 (subreg:V8QI (const_int 0) 0))]
14033 [(set (match_dup 0)
14034 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
14035 (const_int 0) (const_int 0) (const_int 0)
14036 (const_int 0) (const_int 0)]))])
14039 [(set (match_operand 0 "arith_reg_dest" "")
14040 (match_operand 1 "sh_rep_vec" ""))]
14041 "TARGET_SHMEDIA && reload_completed
14042 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14043 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
14044 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
14045 && (XVECEXP (operands[1], 0, 0) != const0_rtx
14046 || XVECEXP (operands[1], 0, 1) != const0_rtx)
14047 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
14048 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
14049 [(set (match_dup 0) (match_dup 1))
14052 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
14053 rtx elt1 = XVECEXP (operands[1], 0, 1);
14056 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
14060 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
14061 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
14063 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
14064 operands[1] = XVECEXP (operands[1], 0, 0);
14067 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
14069 = GEN_INT (TARGET_LITTLE_ENDIAN
14070 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
14071 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
14074 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
14076 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
14082 [(set (match_operand 0 "arith_reg_dest" "")
14083 (match_operand 1 "sh_const_vec" ""))]
14084 "TARGET_SHMEDIA && reload_completed
14085 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14086 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
14087 [(set (match_dup 0) (match_dup 1))]
14089 rtx v = operands[1];
14090 enum machine_mode new_mode
14091 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
14093 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
14095 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
14098 (define_expand "movv2hi"
14099 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
14100 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
14103 prepare_move_operands (operands, V2HImode);
14106 (define_insn "movv2hi_i"
14107 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14108 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14110 && (register_operand (operands[0], V2HImode)
14111 || sh_register_operand (operands[1], V2HImode))"
14118 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14119 (set_attr "length" "4,4,16,4,4")
14120 (set (attr "highpart")
14121 (cond [(match_test "sh_contains_memref_p (insn)")
14122 (const_string "user")]
14123 (const_string "ignore")))])
14125 (define_expand "movv4hi"
14126 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
14127 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
14130 prepare_move_operands (operands, V4HImode);
14133 (define_insn "movv4hi_i"
14134 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14135 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14137 && (register_operand (operands[0], V4HImode)
14138 || sh_register_operand (operands[1], V4HImode))"
14145 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14146 (set_attr "length" "4,4,16,4,4")
14147 (set_attr "highpart" "depend")])
14149 (define_expand "movv2si"
14150 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
14151 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
14154 prepare_move_operands (operands, V2SImode);
14157 (define_insn "movv2si_i"
14158 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
14159 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14161 && (register_operand (operands[0], V2SImode)
14162 || sh_register_operand (operands[1], V2SImode))"
14169 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14170 (set_attr "length" "4,4,16,4,4")
14171 (set_attr "highpart" "depend")])
14173 ;; -------------------------------------------------------------------------
14174 ;; Multimedia Intrinsics
14175 ;; -------------------------------------------------------------------------
14177 (define_insn "absv2si2"
14178 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14179 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
14182 [(set_attr "type" "mcmp_media")
14183 (set_attr "highpart" "depend")])
14185 (define_insn "absv4hi2"
14186 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14187 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
14190 [(set_attr "type" "mcmp_media")
14191 (set_attr "highpart" "depend")])
14193 (define_insn "addv2si3"
14194 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14195 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14196 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14198 "madd.l %1, %2, %0"
14199 [(set_attr "type" "arith_media")
14200 (set_attr "highpart" "depend")])
14202 (define_insn "addv4hi3"
14203 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14204 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14205 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14207 "madd.w %1, %2, %0"
14208 [(set_attr "type" "arith_media")
14209 (set_attr "highpart" "depend")])
14211 (define_insn_and_split "addv2hi3"
14212 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
14213 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
14214 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
14220 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
14221 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
14222 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
14223 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
14224 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
14226 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
14227 emit_insn (gen_truncdisi2 (si_dst, di_dst));
14230 [(set_attr "highpart" "must_split")])
14232 (define_insn "ssaddv2si3"
14233 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14234 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14235 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14237 "madds.l %1, %2, %0"
14238 [(set_attr "type" "mcmp_media")
14239 (set_attr "highpart" "depend")])
14241 (define_insn "usaddv8qi3"
14242 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14243 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
14244 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
14246 "madds.ub %1, %2, %0"
14247 [(set_attr "type" "mcmp_media")
14248 (set_attr "highpart" "depend")])
14250 (define_insn "ssaddv4hi3"
14251 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14252 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14253 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14255 "madds.w %1, %2, %0"
14256 [(set_attr "type" "mcmp_media")
14257 (set_attr "highpart" "depend")])
14259 (define_insn "negcmpeqv8qi"
14260 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14262 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14263 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14265 "mcmpeq.b %N1, %N2, %0"
14266 [(set_attr "type" "mcmp_media")
14267 (set_attr "highpart" "depend")])
14269 (define_insn "negcmpeqv2si"
14270 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14272 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14273 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14275 "mcmpeq.l %N1, %N2, %0"
14276 [(set_attr "type" "mcmp_media")
14277 (set_attr "highpart" "depend")])
14279 (define_insn "negcmpeqv4hi"
14280 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14282 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14283 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14285 "mcmpeq.w %N1, %N2, %0"
14286 [(set_attr "type" "mcmp_media")
14287 (set_attr "highpart" "depend")])
14289 (define_insn "negcmpgtuv8qi"
14290 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14291 (neg:V8QI (gtu:V8QI
14292 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14293 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14295 "mcmpgt.ub %N1, %N2, %0"
14296 [(set_attr "type" "mcmp_media")
14297 (set_attr "highpart" "depend")])
14299 (define_insn "negcmpgtv2si"
14300 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14302 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14303 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14305 "mcmpgt.l %N1, %N2, %0"
14306 [(set_attr "type" "mcmp_media")
14307 (set_attr "highpart" "depend")])
14309 (define_insn "negcmpgtv4hi"
14310 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14312 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14313 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14315 "mcmpgt.w %N1, %N2, %0"
14316 [(set_attr "type" "mcmp_media")
14317 (set_attr "highpart" "depend")])
14319 (define_insn "mcmv"
14320 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14321 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14322 (match_operand:DI 2 "arith_reg_operand" "r"))
14323 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
14324 (not:DI (match_dup 2)))))]
14327 [(set_attr "type" "arith_media")
14328 (set_attr "highpart" "depend")])
14330 (define_insn "mcnvs_lw"
14331 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14333 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
14335 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14337 "mcnvs.lw %N1, %N2, %0"
14338 [(set_attr "type" "mcmp_media")])
14340 (define_insn "mcnvs_wb"
14341 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14343 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14345 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14347 "mcnvs.wb %N1, %N2, %0"
14348 [(set_attr "type" "mcmp_media")])
14350 (define_insn "mcnvs_wub"
14351 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14353 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14355 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14357 "mcnvs.wub %N1, %N2, %0"
14358 [(set_attr "type" "mcmp_media")])
14360 (define_insn "mextr_rl"
14361 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14362 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14363 (match_operand:HI 3 "mextr_bit_offset" "i"))
14364 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14365 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14366 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14368 static char templ[21];
14369 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
14370 (int) INTVAL (operands[3]) >> 3);
14373 [(set_attr "type" "arith_media")])
14375 (define_insn "*mextr_lr"
14376 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14377 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14378 (match_operand:HI 3 "mextr_bit_offset" "i"))
14379 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14380 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14381 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14383 static char templ[21];
14384 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
14385 (int) INTVAL (operands[4]) >> 3);
14388 [(set_attr "type" "arith_media")])
14390 ; mextrN can be modelled with vec_select / vec_concat, but the selection
14391 ; vector then varies depending on endianness.
14392 (define_expand "mextr1"
14393 [(match_operand:DI 0 "arith_reg_dest" "")
14394 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14395 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14398 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14399 GEN_INT (1 * 8), GEN_INT (7 * 8)));
14403 (define_expand "mextr2"
14404 [(match_operand:DI 0 "arith_reg_dest" "")
14405 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14406 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14409 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14410 GEN_INT (2 * 8), GEN_INT (6 * 8)));
14414 (define_expand "mextr3"
14415 [(match_operand:DI 0 "arith_reg_dest" "")
14416 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14417 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14420 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14421 GEN_INT (3 * 8), GEN_INT (5 * 8)));
14425 (define_expand "mextr4"
14426 [(match_operand:DI 0 "arith_reg_dest" "")
14427 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14428 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14431 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14432 GEN_INT (4 * 8), GEN_INT (4 * 8)));
14436 (define_expand "mextr5"
14437 [(match_operand:DI 0 "arith_reg_dest" "")
14438 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14439 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14442 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14443 GEN_INT (5 * 8), GEN_INT (3 * 8)));
14447 (define_expand "mextr6"
14448 [(match_operand:DI 0 "arith_reg_dest" "")
14449 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14450 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14453 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14454 GEN_INT (6 * 8), GEN_INT (2 * 8)));
14458 (define_expand "mextr7"
14459 [(match_operand:DI 0 "arith_reg_dest" "")
14460 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14461 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14464 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14465 GEN_INT (7 * 8), GEN_INT (1 * 8)));
14469 (define_expand "mmacfx_wl"
14470 [(match_operand:V2SI 0 "arith_reg_dest" "")
14471 (match_operand:V2HI 1 "extend_reg_operand" "")
14472 (match_operand:V2HI 2 "extend_reg_operand" "")
14473 (match_operand:V2SI 3 "arith_reg_operand" "")]
14476 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
14477 operands[1], operands[2]));
14481 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
14483 (define_insn "mmacfx_wl_i"
14484 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14486 (match_operand:V2SI 1 "arith_reg_operand" "0")
14491 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14492 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14495 "mmacfx.wl %2, %3, %0"
14496 [(set_attr "type" "mac_media")
14497 (set_attr "highpart" "depend")])
14499 (define_expand "mmacnfx_wl"
14500 [(match_operand:V2SI 0 "arith_reg_dest" "")
14501 (match_operand:V2HI 1 "extend_reg_operand" "")
14502 (match_operand:V2HI 2 "extend_reg_operand" "")
14503 (match_operand:V2SI 3 "arith_reg_operand" "")]
14506 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
14507 operands[1], operands[2]));
14511 (define_insn "mmacnfx_wl_i"
14512 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14514 (match_operand:V2SI 1 "arith_reg_operand" "0")
14519 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14520 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14523 "mmacnfx.wl %2, %3, %0"
14524 [(set_attr "type" "mac_media")
14525 (set_attr "highpart" "depend")])
14527 (define_insn "mulv2si3"
14528 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14529 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14530 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14532 "mmul.l %1, %2, %0"
14533 [(set_attr "type" "d2mpy_media")
14534 (set_attr "highpart" "depend")])
14536 (define_insn "mulv4hi3"
14537 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14538 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14539 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14541 "mmul.w %1, %2, %0"
14542 [(set_attr "type" "dmpy_media")
14543 (set_attr "highpart" "depend")])
14545 (define_insn "mmulfx_l"
14546 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14550 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14551 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
14554 "mmulfx.l %1, %2, %0"
14555 [(set_attr "type" "d2mpy_media")
14556 (set_attr "highpart" "depend")])
14558 (define_insn "mmulfx_w"
14559 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14563 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14564 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14567 "mmulfx.w %1, %2, %0"
14568 [(set_attr "type" "dmpy_media")
14569 (set_attr "highpart" "depend")])
14571 (define_insn "mmulfxrp_w"
14572 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14577 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14578 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14582 "mmulfxrp.w %1, %2, %0"
14583 [(set_attr "type" "dmpy_media")
14584 (set_attr "highpart" "depend")])
14587 (define_expand "mmulhi_wl"
14588 [(match_operand:V2SI 0 "arith_reg_dest" "")
14589 (match_operand:V4HI 1 "arith_reg_operand" "")
14590 (match_operand:V4HI 2 "arith_reg_operand" "")]
14593 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
14594 (operands[0], operands[1], operands[2]));
14598 (define_expand "mmullo_wl"
14599 [(match_operand:V2SI 0 "arith_reg_dest" "")
14600 (match_operand:V4HI 1 "arith_reg_operand" "")
14601 (match_operand:V4HI 2 "arith_reg_operand" "")]
14604 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
14605 (operands[0], operands[1], operands[2]));
14609 (define_insn "mmul23_wl"
14610 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14613 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14614 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14615 (parallel [(const_int 2) (const_int 3)])))]
14618 return (TARGET_LITTLE_ENDIAN
14619 ? "mmulhi.wl %1, %2, %0"
14620 : "mmullo.wl %1, %2, %0");
14622 [(set_attr "type" "dmpy_media")
14623 (set (attr "highpart")
14624 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14625 (const_string "user")))])
14627 (define_insn "mmul01_wl"
14628 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14631 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14632 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14633 (parallel [(const_int 0) (const_int 1)])))]
14636 return (TARGET_LITTLE_ENDIAN
14637 ? "mmullo.wl %1, %2, %0"
14638 : "mmulhi.wl %1, %2, %0");
14640 [(set_attr "type" "dmpy_media")
14641 (set (attr "highpart")
14642 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14643 (const_string "user")))])
14646 (define_expand "mmulsum_wq"
14647 [(match_operand:DI 0 "arith_reg_dest" "")
14648 (match_operand:V4HI 1 "arith_reg_operand" "")
14649 (match_operand:V4HI 2 "arith_reg_operand" "")
14650 (match_operand:DI 3 "arith_reg_operand" "")]
14653 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
14654 operands[1], operands[2]));
14658 (define_insn "mmulsum_wq_i"
14659 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14660 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
14665 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
14666 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
14667 (parallel [(const_int 0)]))
14668 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14669 (sign_extend:V4DI (match_dup 3)))
14670 (parallel [(const_int 1)])))
14672 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14673 (sign_extend:V4DI (match_dup 3)))
14674 (parallel [(const_int 2)]))
14675 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14676 (sign_extend:V4DI (match_dup 3)))
14677 (parallel [(const_int 3)]))))))]
14679 "mmulsum.wq %2, %3, %0"
14680 [(set_attr "type" "mac_media")])
14682 (define_expand "mperm_w"
14683 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
14684 (match_operand:V4HI 1 "arith_reg_operand" "r")
14685 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
14688 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
14689 (operands[0], operands[1], operands[2]));
14693 ; This use of vec_select isn't exactly correct according to rtl.texi
14694 ; (because not constant), but it seems a straightforward extension.
14695 (define_insn "mperm_w_little"
14696 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14698 (match_operand:V4HI 1 "arith_reg_operand" "r")
14700 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
14701 (const_int 2) (const_int 0))
14702 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
14703 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
14704 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
14705 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
14706 "mperm.w %1, %N2, %0"
14707 [(set_attr "type" "arith_media")])
14709 (define_insn "mperm_w_big"
14710 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14712 (match_operand:V4HI 1 "arith_reg_operand" "r")
14714 [(zero_extract:QI (not:QI (match_operand:QI 2
14715 "extend_reg_or_0_operand" "rZ"))
14716 (const_int 2) (const_int 0))
14717 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
14718 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
14719 (zero_extract:QI (not:QI (match_dup 2))
14720 (const_int 2) (const_int 6))])))]
14721 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
14722 "mperm.w %1, %N2, %0"
14723 [(set_attr "type" "arith_media")])
14725 (define_insn "mperm_w0"
14726 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14727 (vec_duplicate:V4HI (truncate:HI (match_operand 1
14728 "trunc_hi_operand" "r"))))]
14730 "mperm.w %1, r63, %0"
14731 [(set_attr "type" "arith_media")
14732 (set_attr "highpart" "ignore")])
14734 (define_expand "msad_ubq"
14735 [(match_operand:DI 0 "arith_reg_dest" "")
14736 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
14737 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
14738 (match_operand:DI 3 "arith_reg_operand" "")]
14741 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
14742 operands[1], operands[2]));
14746 (define_insn "msad_ubq_i"
14747 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14752 (match_operand:DI 1 "arith_reg_operand" "0")
14753 (abs:DI (vec_select:DI
14756 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14758 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
14759 (parallel [(const_int 0)]))))
14760 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14761 (zero_extend:V8DI (match_dup 3)))
14762 (parallel [(const_int 1)]))))
14764 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14765 (zero_extend:V8DI (match_dup 3)))
14766 (parallel [(const_int 2)])))
14767 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14768 (zero_extend:V8DI (match_dup 3)))
14769 (parallel [(const_int 3)])))))
14772 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14773 (zero_extend:V8DI (match_dup 3)))
14774 (parallel [(const_int 4)])))
14775 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14776 (zero_extend:V8DI (match_dup 3)))
14777 (parallel [(const_int 5)]))))
14779 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14780 (zero_extend:V8DI (match_dup 3)))
14781 (parallel [(const_int 6)])))
14782 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14783 (zero_extend:V8DI (match_dup 3)))
14784 (parallel [(const_int 7)])))))))]
14786 "msad.ubq %N2, %N3, %0"
14787 [(set_attr "type" "mac_media")])
14789 (define_insn "mshalds_l"
14790 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14793 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14794 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14795 (const_int 31)))))]
14797 "mshalds.l %1, %2, %0"
14798 [(set_attr "type" "mcmp_media")
14799 (set_attr "highpart" "depend")])
14801 (define_insn "mshalds_w"
14802 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14805 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14806 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14807 (const_int 15)))))]
14809 "mshalds.w %1, %2, %0"
14810 [(set_attr "type" "mcmp_media")
14811 (set_attr "highpart" "depend")])
14813 (define_insn "ashrv2si3"
14814 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14815 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14816 (match_operand:DI 2 "arith_reg_operand" "r")))]
14818 "mshard.l %1, %2, %0"
14819 [(set_attr "type" "arith_media")
14820 (set_attr "highpart" "depend")])
14822 (define_insn "ashrv4hi3"
14823 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14824 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14825 (match_operand:DI 2 "arith_reg_operand" "r")))]
14827 "mshard.w %1, %2, %0"
14828 [(set_attr "type" "arith_media")
14829 (set_attr "highpart" "depend")])
14831 (define_insn "mshards_q"
14832 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
14834 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
14835 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
14837 "mshards.q %1, %N2, %0"
14838 [(set_attr "type" "mcmp_media")])
14840 (define_expand "mshfhi_b"
14841 [(match_operand:V8QI 0 "arith_reg_dest" "")
14842 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14843 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14846 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
14847 (operands[0], operands[1], operands[2]));
14851 (define_expand "mshflo_b"
14852 [(match_operand:V8QI 0 "arith_reg_dest" "")
14853 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14854 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14857 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
14858 (operands[0], operands[1], operands[2]));
14862 (define_insn "mshf4_b"
14864 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14866 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14867 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14868 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
14869 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
14872 return (TARGET_LITTLE_ENDIAN
14873 ? "mshfhi.b %N1, %N2, %0"
14874 : "mshflo.b %N1, %N2, %0");
14876 [(set_attr "type" "arith_media")
14877 (set (attr "highpart")
14878 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14879 (const_string "user")))])
14881 (define_insn "mshf0_b"
14883 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14885 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14886 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14887 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
14888 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
14891 return (TARGET_LITTLE_ENDIAN
14892 ? "mshflo.b %N1, %N2, %0"
14893 : "mshfhi.b %N1, %N2, %0");
14895 [(set_attr "type" "arith_media")
14896 (set (attr "highpart")
14897 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14898 (const_string "user")))])
14900 (define_expand "mshfhi_l"
14901 [(match_operand:V2SI 0 "arith_reg_dest" "")
14902 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14903 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14906 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
14907 (operands[0], operands[1], operands[2]));
14911 (define_expand "mshflo_l"
14912 [(match_operand:V2SI 0 "arith_reg_dest" "")
14913 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14914 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14917 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
14918 (operands[0], operands[1], operands[2]));
14922 (define_insn "mshf4_l"
14923 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14925 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14926 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14927 (parallel [(const_int 1) (const_int 3)])))]
14930 return (TARGET_LITTLE_ENDIAN
14931 ? "mshfhi.l %N1, %N2, %0"
14932 : "mshflo.l %N1, %N2, %0");
14934 [(set_attr "type" "arith_media")
14935 (set (attr "highpart")
14936 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14937 (const_string "user")))])
14939 (define_insn "mshf0_l"
14940 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14942 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14943 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14944 (parallel [(const_int 0) (const_int 2)])))]
14947 return (TARGET_LITTLE_ENDIAN
14948 ? "mshflo.l %N1, %N2, %0"
14949 : "mshfhi.l %N1, %N2, %0");
14951 [(set_attr "type" "arith_media")
14952 (set (attr "highpart")
14953 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14954 (const_string "user")))])
14956 (define_expand "mshfhi_w"
14957 [(match_operand:V4HI 0 "arith_reg_dest" "")
14958 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14959 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14962 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
14963 (operands[0], operands[1], operands[2]));
14967 (define_expand "mshflo_w"
14968 [(match_operand:V4HI 0 "arith_reg_dest" "")
14969 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14970 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14973 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
14974 (operands[0], operands[1], operands[2]));
14978 (define_insn "mshf4_w"
14979 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14981 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14982 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14983 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
14986 return (TARGET_LITTLE_ENDIAN
14987 ? "mshfhi.w %N1, %N2, %0"
14988 : "mshflo.w %N1, %N2, %0");
14990 [(set_attr "type" "arith_media")
14991 (set (attr "highpart")
14992 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14993 (const_string "user")))])
14995 (define_insn "mshf0_w"
14996 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14998 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14999 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15000 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
15003 return (TARGET_LITTLE_ENDIAN
15004 ? "mshflo.w %N1, %N2, %0"
15005 : "mshfhi.w %N1, %N2, %0");
15007 [(set_attr "type" "arith_media")
15008 (set (attr "highpart")
15009 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15010 (const_string "user")))])
15012 (define_insn "mshflo_w_x"
15013 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15015 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
15016 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
15017 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
15019 "mshflo.w %N1, %N2, %0"
15020 [(set_attr "type" "arith_media")
15021 (set_attr "highpart" "ignore")])
15023 ;; These are useful to expand ANDs and as combiner patterns.
15024 (define_insn_and_split "mshfhi_l_di"
15025 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
15026 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
15028 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
15029 (const_int -4294967296))))]
15032 mshfhi.l %N1, %N2, %0
15034 "TARGET_SHMEDIA && reload_completed
15035 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15036 [(set (match_dup 3) (match_dup 4))
15037 (set (match_dup 5) (match_dup 6))]
15039 operands[3] = gen_lowpart (SImode, operands[0]);
15040 operands[4] = gen_highpart (SImode, operands[1]);
15041 operands[5] = gen_highpart (SImode, operands[0]);
15042 operands[6] = gen_highpart (SImode, operands[2]);
15044 [(set_attr "type" "arith_media")])
15046 (define_insn "*mshfhi_l_di_rev"
15047 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15048 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15049 (const_int -4294967296))
15050 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15053 "mshfhi.l %N2, %N1, %0"
15054 [(set_attr "type" "arith_media")])
15057 [(set (match_operand:DI 0 "arith_reg_dest" "")
15058 (ior:DI (zero_extend:DI (match_operand:SI 1
15059 "extend_reg_or_0_operand" ""))
15060 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
15061 (const_int -4294967296))))
15062 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
15066 emit_insn (gen_ashldi3_media (operands[3],
15067 simplify_gen_subreg (DImode, operands[1],
15070 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
15074 (define_insn "mshflo_l_di"
15075 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15076 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15077 (const_int 4294967295))
15078 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15082 "mshflo.l %N1, %N2, %0"
15083 [(set_attr "type" "arith_media")
15084 (set_attr "highpart" "ignore")])
15086 (define_insn "*mshflo_l_di_rev"
15087 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15088 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15090 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15091 (const_int 4294967295))))]
15094 "mshflo.l %N2, %N1, %0"
15095 [(set_attr "type" "arith_media")
15096 (set_attr "highpart" "ignore")])
15098 ;; Combiner pattern for trampoline initialization.
15099 (define_insn_and_split "*double_shori"
15100 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15101 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
15103 (match_operand:DI 2 "const_int_operand" "n")))]
15105 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
15107 "rtx_equal_p (operands[0], operands[1])"
15110 HOST_WIDE_INT v = INTVAL (operands[2]);
15112 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
15113 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
15116 [(set_attr "highpart" "ignore")])
15118 (define_insn "*mshflo_l_di_x"
15119 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15120 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
15122 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15125 "mshflo.l %N1, %N2, %0"
15126 [(set_attr "type" "arith_media")
15127 (set_attr "highpart" "ignore")])
15129 (define_insn_and_split "concat_v2sf"
15130 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
15131 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
15132 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
15133 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
15136 mshflo.l %N1, %N2, %0
15139 "TARGET_SHMEDIA && reload_completed
15140 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15141 [(set (match_dup 3) (match_dup 1))
15142 (set (match_dup 4) (match_dup 2))]
15144 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
15145 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
15147 [(set_attr "type" "arith_media")
15148 (set_attr "highpart" "ignore")])
15150 (define_insn "*mshflo_l_di_x_rev"
15151 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15152 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15155 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
15157 "mshflo.l %N2, %N1, %0"
15158 [(set_attr "type" "arith_media")
15159 (set_attr "highpart" "ignore")])
15161 (define_insn "ashlv2si3"
15162 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15163 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15164 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15166 "mshlld.l %1, %2, %0"
15167 [(set_attr "type" "arith_media")
15168 (set_attr "highpart" "depend")])
15171 [(set (match_operand 0 "any_register_operand" "")
15172 (match_operator 3 "shift_operator"
15173 [(match_operand 1 "any_register_operand" "")
15174 (match_operand 2 "shift_count_reg_operand" "")]))]
15175 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
15176 [(set (match_dup 0) (match_dup 3))]
15178 rtx count = operands[2];
15179 enum machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
15181 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
15182 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
15183 || GET_CODE (count) == TRUNCATE)
15184 count = XEXP (count, 0);
15185 inner_mode = GET_MODE (count);
15186 count = simplify_gen_subreg (outer_mode, count, inner_mode,
15187 subreg_lowpart_offset (outer_mode, inner_mode));
15188 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
15189 operands[1], count);
15192 (define_insn "ashlv4hi3"
15193 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15194 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15195 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15197 "mshlld.w %1, %2, %0"
15198 [(set_attr "type" "arith_media")
15199 (set_attr "highpart" "depend")])
15201 (define_insn "lshrv2si3"
15202 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15203 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15204 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15206 "mshlrd.l %1, %2, %0"
15207 [(set_attr "type" "arith_media")
15208 (set_attr "highpart" "depend")])
15210 (define_insn "lshrv4hi3"
15211 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15212 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15213 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15215 "mshlrd.w %1, %2, %0"
15216 [(set_attr "type" "arith_media")
15217 (set_attr "highpart" "depend")])
15219 (define_insn "subv2si3"
15220 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15221 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15222 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15224 "msub.l %N1, %2, %0"
15225 [(set_attr "type" "arith_media")
15226 (set_attr "highpart" "depend")])
15228 (define_insn "subv4hi3"
15229 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15230 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15231 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15233 "msub.w %N1, %2, %0"
15234 [(set_attr "type" "arith_media")
15235 (set_attr "highpart" "depend")])
15237 (define_insn_and_split "subv2hi3"
15238 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15239 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
15240 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
15246 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15247 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15248 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15249 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15250 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15252 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
15253 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15256 [(set_attr "highpart" "must_split")])
15258 (define_insn "sssubv2si3"
15259 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15260 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15261 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15263 "msubs.l %N1, %2, %0"
15264 [(set_attr "type" "mcmp_media")
15265 (set_attr "highpart" "depend")])
15267 (define_insn "ussubv8qi3"
15268 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15269 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15270 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15272 "msubs.ub %N1, %2, %0"
15273 [(set_attr "type" "mcmp_media")
15274 (set_attr "highpart" "depend")])
15276 (define_insn "sssubv4hi3"
15277 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15278 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15279 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15281 "msubs.w %N1, %2, %0"
15282 [(set_attr "type" "mcmp_media")
15283 (set_attr "highpart" "depend")])
15285 ;; -------------------------------------------------------------------------
15286 ;; Floating Point Intrinsics
15287 ;; -------------------------------------------------------------------------
15289 (define_insn "fcosa_s"
15290 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15291 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15295 [(set_attr "type" "atrans_media")])
15297 (define_insn "fsina_s"
15298 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15299 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15303 [(set_attr "type" "atrans_media")])
15305 (define_insn "fipr"
15306 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15307 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
15308 "fp_arith_reg_operand" "f")
15309 (match_operand:V4SF 2
15310 "fp_arith_reg_operand" "f"))
15311 (parallel [(const_int 0)]))
15312 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15313 (parallel [(const_int 1)])))
15314 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15315 (parallel [(const_int 2)]))
15316 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15317 (parallel [(const_int 3)])))))]
15319 "fipr.s %1, %2, %0"
15320 [(set_attr "type" "fparith_media")])
15322 (define_insn "fsrra_s"
15323 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15324 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
15328 [(set_attr "type" "atrans_media")])
15330 (define_insn "ftrv"
15331 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
15335 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
15336 (parallel [(const_int 0) (const_int 5)
15337 (const_int 10) (const_int 15)]))
15338 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
15340 (vec_select:V4SF (match_dup 1)
15341 (parallel [(const_int 4) (const_int 9)
15342 (const_int 14) (const_int 3)]))
15343 (vec_select:V4SF (match_dup 2)
15344 (parallel [(const_int 1) (const_int 2)
15345 (const_int 3) (const_int 0)]))))
15348 (vec_select:V4SF (match_dup 1)
15349 (parallel [(const_int 8) (const_int 13)
15350 (const_int 2) (const_int 7)]))
15351 (vec_select:V4SF (match_dup 2)
15352 (parallel [(const_int 2) (const_int 3)
15353 (const_int 0) (const_int 1)])))
15355 (vec_select:V4SF (match_dup 1)
15356 (parallel [(const_int 12) (const_int 1)
15357 (const_int 6) (const_int 11)]))
15358 (vec_select:V4SF (match_dup 2)
15359 (parallel [(const_int 3) (const_int 0)
15360 (const_int 1) (const_int 2)]))))))]
15362 "ftrv.s %1, %2, %0"
15363 [(set_attr "type" "fparith_media")])
15365 (define_insn "ldhi_l"
15366 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15368 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15371 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
15375 [(set_attr "type" "load_media")])
15377 (define_insn "ldhi_q"
15378 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15380 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15383 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
15387 [(set_attr "type" "load_media")])
15389 (define_insn_and_split "*ldhi_q_comb0"
15390 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15392 (mem:DI (plus:SI (ior:SI (plus:SI
15393 (match_operand:SI 1 "register_operand" "r")
15394 (match_operand:SI 2 "ua_offset" "I06"))
15397 (plus:SI (and:SI (match_dup 1) (const_int 7))
15400 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15405 emit_insn (gen_ldhi_q (operands[0],
15406 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15410 (define_insn_and_split "*ldhi_q_comb1"
15411 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15413 (mem:DI (plus:SI (ior:SI (plus:SI
15414 (match_operand:SI 1 "register_operand" "r")
15415 (match_operand:SI 2 "ua_offset" "I06"))
15418 (plus:SI (and:SI (plus:SI (match_dup 1)
15419 (match_operand:SI 3 "ua_offset" "I06"))
15423 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15424 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15429 emit_insn (gen_ldhi_q (operands[0],
15430 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15434 (define_insn "ldlo_l"
15435 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15437 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15439 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
15440 (and:SI (match_dup 1) (const_int 3))))]
15443 [(set_attr "type" "load_media")])
15445 (define_insn "ldlo_q"
15446 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15448 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15450 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15451 (and:SI (match_dup 1) (const_int 7))))]
15454 [(set_attr "type" "load_media")])
15456 (define_insn_and_split "*ldlo_q_comb0"
15457 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15459 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15460 (match_operand:SI 2 "ua_offset" "I06"))
15462 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15463 (and:SI (match_dup 1) (const_int 7))))]
15464 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15469 emit_insn (gen_ldlo_q (operands[0],
15470 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15474 (define_insn_and_split "*ldlo_q_comb1"
15475 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15477 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15478 (match_operand:SI 2 "ua_offset" "I06"))
15480 (minus:SI (const_int 8)
15481 (and:SI (plus:SI (match_dup 1)
15482 (match_operand:SI 3 "ua_offset" "I06"))
15484 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
15485 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15486 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15491 emit_insn (gen_ldlo_q (operands[0],
15492 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15496 (define_insn "sthi_l"
15497 [(set (zero_extract:SI
15498 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15501 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
15503 (match_operand:SI 1 "arith_reg_operand" "r"))]
15506 [(set_attr "type" "ustore_media")])
15508 ;; All unaligned stores are considered to be 'narrow' because they typically
15509 ;; operate on less that a quadword, and when they operate on a full quadword,
15510 ;; the vanilla store high / store low sequence will cause a stall if not
15511 ;; scheduled apart.
15512 (define_insn "sthi_q"
15513 [(set (zero_extract:DI
15514 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15517 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15519 (match_operand:DI 1 "arith_reg_operand" "r"))]
15522 [(set_attr "type" "ustore_media")])
15524 (define_insn_and_split "*sthi_q_comb0"
15525 [(set (zero_extract:DI
15526 (mem:DI (plus:SI (ior:SI (plus:SI
15527 (match_operand:SI 0 "register_operand" "r")
15528 (match_operand:SI 1 "ua_offset" "I06"))
15531 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15533 (match_operand:DI 2 "arith_reg_operand" "r"))]
15534 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15539 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15544 (define_insn_and_split "*sthi_q_comb1"
15545 [(set (zero_extract:DI
15546 (mem:DI (plus:SI (ior:SI (plus:SI
15547 (match_operand:SI 0 "register_operand" "r")
15548 (match_operand:SI 1 "ua_offset" "I06"))
15551 (plus:SI (and:SI (plus:SI (match_dup 0)
15552 (match_operand:SI 2 "ua_offset" "I06"))
15556 (match_operand:DI 3 "arith_reg_operand" "r"))]
15557 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
15558 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15563 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15568 ;; This is highpart user because the address is used as full 64 bit.
15569 (define_insn "stlo_l"
15570 [(set (zero_extract:SI
15571 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15573 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
15574 (and:SI (match_dup 0) (const_int 3)))
15575 (match_operand:SI 1 "arith_reg_operand" "r"))]
15578 [(set_attr "type" "ustore_media")])
15580 (define_insn "stlo_q"
15581 [(set (zero_extract:DI
15582 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15584 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15585 (and:SI (match_dup 0) (const_int 7)))
15586 (match_operand:DI 1 "arith_reg_operand" "r"))]
15589 [(set_attr "type" "ustore_media")])
15591 (define_insn_and_split "*stlo_q_comb0"
15592 [(set (zero_extract:DI
15593 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15594 (match_operand:SI 1 "ua_offset" "I06"))
15596 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15597 (and:SI (match_dup 0) (const_int 7)))
15598 (match_operand:DI 2 "arith_reg_operand" "r"))]
15599 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15604 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15609 (define_insn_and_split "*stlo_q_comb1"
15610 [(set (zero_extract:DI
15611 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15612 (match_operand:SI 1 "ua_offset" "I06"))
15614 (minus:SI (const_int 8)
15615 (and:SI (plus:SI (match_dup 0)
15616 (match_operand:SI 2 "ua_offset" "I06"))
15618 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
15619 (match_operand:DI 3 "arith_reg_operand" "r"))]
15620 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15625 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15630 (define_insn "ldhi_l64"
15631 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15633 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15636 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
15640 [(set_attr "type" "load_media")])
15642 (define_insn "ldhi_q64"
15643 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15645 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15648 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
15652 [(set_attr "type" "load_media")])
15654 (define_insn "ldlo_l64"
15655 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15657 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15659 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
15660 (and:DI (match_dup 1) (const_int 3))))]
15663 [(set_attr "type" "load_media")])
15665 (define_insn "ldlo_q64"
15666 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15668 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15670 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
15671 (and:DI (match_dup 1) (const_int 7))))]
15674 [(set_attr "type" "load_media")])
15676 (define_insn "sthi_l64"
15677 [(set (zero_extract:SI
15678 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15681 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
15683 (match_operand:SI 1 "arith_reg_operand" "r"))]
15686 [(set_attr "type" "ustore_media")])
15688 (define_insn "sthi_q64"
15689 [(set (zero_extract:DI
15690 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15693 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
15695 (match_operand:DI 1 "arith_reg_operand" "r"))]
15698 [(set_attr "type" "ustore_media")])
15700 (define_insn "stlo_l64"
15701 [(set (zero_extract:SI
15702 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15704 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
15705 (and:DI (match_dup 0) (const_int 3)))
15706 (match_operand:SI 1 "arith_reg_operand" "r"))]
15709 [(set_attr "type" "ustore_media")])
15711 (define_insn "stlo_q64"
15712 [(set (zero_extract:DI
15713 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15715 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
15716 (and:DI (match_dup 0) (const_int 7)))
15717 (match_operand:DI 1 "arith_reg_operand" "r"))]
15720 [(set_attr "type" "ustore_media")])
15723 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
15724 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15728 [(set_attr "type" "arith_media")])
15730 (define_insn "nsbsi"
15731 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15733 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15737 [(set_attr "type" "arith_media")])
15739 (define_insn "nsbdi"
15740 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15742 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15746 [(set_attr "type" "arith_media")])
15748 (define_expand "ffsdi2"
15749 [(set (match_operand:DI 0 "arith_reg_dest" "")
15750 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
15753 rtx scratch = gen_reg_rtx (DImode);
15756 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
15757 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
15758 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
15759 emit_insn (gen_nsbdi (scratch, scratch));
15760 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
15761 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
15762 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
15763 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
15768 (define_expand "ffssi2"
15769 [(set (match_operand:SI 0 "arith_reg_dest" "")
15770 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
15773 rtx scratch = gen_reg_rtx (SImode);
15774 rtx discratch = gen_reg_rtx (DImode);
15777 emit_insn (gen_adddi3 (discratch,
15778 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15780 emit_insn (gen_andcdi3 (discratch,
15781 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15783 emit_insn (gen_nsbsi (scratch, discratch));
15784 last = emit_insn (gen_subsi3 (operands[0],
15785 force_reg (SImode, GEN_INT (63)), scratch));
15786 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
15791 (define_insn "byterev"
15792 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15793 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
15794 (parallel [(const_int 7) (const_int 6) (const_int 5)
15795 (const_int 4) (const_int 3) (const_int 2)
15796 (const_int 1) (const_int 0)])))]
15799 [(set_attr "type" "arith_media")])
15801 ;; In user mode, the "pref" instruction will raise a RADDERR exception
15802 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
15803 ;; implementation of __builtin_prefetch for VxWorks RTPs.
15804 (define_expand "prefetch"
15805 [(prefetch (match_operand 0 "address_operand" "")
15806 (match_operand:SI 1 "const_int_operand" "")
15807 (match_operand:SI 2 "const_int_operand" ""))]
15808 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
15809 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
15811 (define_insn "*prefetch"
15812 [(prefetch (match_operand:SI 0 "register_operand" "r")
15813 (match_operand:SI 1 "const_int_operand" "n")
15814 (match_operand:SI 2 "const_int_operand" "n"))]
15815 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
15817 [(set_attr "type" "other")])
15819 (define_insn "*prefetch_media"
15820 [(prefetch (match_operand:QI 0 "address_operand" "p")
15821 (match_operand:SI 1 "const_int_operand" "n")
15822 (match_operand:SI 2 "const_int_operand" "n"))]
15825 operands[0] = gen_rtx_MEM (QImode, operands[0]);
15826 output_asm_insn ("ld%M0.b %m0,r63", operands);
15829 [(set_attr "type" "other")])
15831 (define_insn "alloco_i"
15832 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
15833 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
15838 if (GET_CODE (operands[0]) == PLUS)
15840 xops[0] = XEXP (operands[0], 0);
15841 xops[1] = XEXP (operands[0], 1);
15845 xops[0] = operands[0];
15846 xops[1] = const0_rtx;
15848 output_asm_insn ("alloco %0, %1", xops);
15851 [(set_attr "type" "other")])
15854 [(set (match_operand 0 "any_register_operand" "")
15855 (match_operand 1 "" ""))]
15856 "TARGET_SHMEDIA && reload_completed"
15857 [(set (match_dup 0) (match_dup 1))]
15861 for_each_rtx (&operands[1], shmedia_cleanup_truncate, &n_changes);
15866 ;; -------------------------------------------------------------------------
15867 ;; Stack Protector Patterns
15868 ;; -------------------------------------------------------------------------
15870 (define_expand "stack_protect_set"
15871 [(set (match_operand 0 "memory_operand" "")
15872 (match_operand 1 "memory_operand" ""))]
15875 if (TARGET_SHMEDIA)
15877 if (TARGET_SHMEDIA64)
15878 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
15880 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
15883 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
15888 (define_insn "stack_protect_set_si"
15889 [(set (match_operand:SI 0 "memory_operand" "=m")
15890 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15891 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15894 return "mov.l %1,%2" "\n"
15895 " mov.l %2,%0" "\n"
15898 [(set_attr "type" "other")
15899 (set_attr "length" "6")])
15901 (define_insn "stack_protect_set_si_media"
15902 [(set (match_operand:SI 0 "memory_operand" "=m")
15903 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15904 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15907 return "ld%M1.l %m1,%2" "\n"
15908 " st%M0.l %m0,%2" "\n"
15911 [(set_attr "type" "other")
15912 (set_attr "length" "12")])
15914 (define_insn "stack_protect_set_di_media"
15915 [(set (match_operand:DI 0 "memory_operand" "=m")
15916 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15917 (set (match_scratch:DI 2 "=&r") (const_int 0))]
15920 return "ld%M1.q %m1,%2" "\n"
15921 " st%M0.q %m0,%2" "\n"
15924 [(set_attr "type" "other")
15925 (set_attr "length" "12")])
15927 (define_expand "stack_protect_test"
15928 [(match_operand 0 "memory_operand" "")
15929 (match_operand 1 "memory_operand" "")
15930 (match_operand 2 "" "")]
15933 if (TARGET_SHMEDIA)
15935 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
15938 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15939 if (TARGET_SHMEDIA64)
15941 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
15943 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
15947 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
15949 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
15954 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
15955 emit_jump_insn (gen_branch_true (operands[2]));
15961 (define_insn "stack_protect_test_si"
15962 [(set (reg:SI T_REG)
15963 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
15964 (match_operand:SI 1 "memory_operand" "m")]
15966 (set (match_scratch:SI 2 "=&r") (const_int 0))
15967 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15970 return "mov.l %0,%2" "\n"
15971 " mov.l %1,%3" "\n"
15972 " cmp/eq %2,%3" "\n"
15976 [(set_attr "type" "other")
15977 (set_attr "length" "10")])
15979 (define_insn "stack_protect_test_si_media"
15980 [(set (match_operand:SI 0 "register_operand" "=&r")
15981 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
15982 (match_operand:SI 2 "memory_operand" "m")]
15984 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15987 return "ld%M1.l %m1,%0" "\n"
15988 " ld%M2.l %m2,%3" "\n"
15989 " cmpeq %0,%3,%0" "\n"
15992 [(set_attr "type" "other")
15993 (set_attr "length" "16")])
15995 (define_insn "stack_protect_test_di_media"
15996 [(set (match_operand:DI 0 "register_operand" "=&r")
15997 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
15998 (match_operand:DI 2 "memory_operand" "m")]
16000 (set (match_scratch:DI 3 "=&r") (const_int 0))]
16003 return "ld%M1.q %m1,%0" "\n"
16004 " ld%M2.q %m2,%3" "\n"
16005 " cmpeq %0,%3,%0" "\n"
16008 [(set_attr "type" "other")
16009 (set_attr "length" "16")])
16011 ;; -------------------------------------------------------------------------
16012 ;; Atomic operations
16013 ;; -------------------------------------------------------------------------
16015 (include "sync.md")