1 ;; Scheduling description for PowerPC A2 processors.
2 ;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
3 ;; Contributed by Ben Elliston (bje@au.ibm.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_automaton "ppca2")
25 ;; The multiplier pipeline.
26 (define_cpu_unit "mult" "ppca2")
28 ;; The auxiliary processor unit (FP/vector unit).
29 (define_cpu_unit "axu" "ppca2")
32 ;; Some peculiarities for certain SPRs
34 (define_insn_reservation "ppca2-mfcr" 1
35 (and (eq_attr "type" "mfcr")
36 (eq_attr "cpu" "ppca2"))
39 (define_insn_reservation "ppca2-mfjmpr" 5
40 (and (eq_attr "type" "mfjmpr")
41 (eq_attr "cpu" "ppca2"))
44 (define_insn_reservation "ppca2-mtjmpr" 5
45 (and (eq_attr "type" "mtjmpr")
46 (eq_attr "cpu" "ppca2"))
50 (define_insn_reservation "ppca2-imul" 1
51 (and (eq_attr "type" "mul")
52 (eq_attr "size" "8,16,32")
53 (eq_attr "cpu" "ppca2"))
56 ;; FIXME: latency and multiplier reservation for 64-bit multiply?
57 (define_insn_reservation "ppca2-lmul" 6
58 (and (eq_attr "type" "mul")
60 (eq_attr "cpu" "ppca2"))
64 (define_insn_reservation "ppca2-idiv" 32
65 (and (eq_attr "type" "div")
67 (eq_attr "cpu" "ppca2"))
70 (define_insn_reservation "ppca2-ldiv" 65
71 (and (eq_attr "type" "div")
73 (eq_attr "cpu" "ppca2"))
77 (define_insn_reservation "ppca2-load" 5
78 (and (eq_attr "type" "load")
79 (eq_attr "cpu" "ppca2"))
83 (define_insn_reservation "ppca2-fp" 6
84 (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
85 (eq_attr "cpu" "ppca2"))
89 (define_insn_reservation "ppca2-fp-load" 6
90 (and (eq_attr "type" "fpload")
91 (eq_attr "cpu" "ppca2"))
95 (define_insn_reservation "ppca2-fp-store" 2
96 (and (eq_attr "type" "fpstore")
97 (eq_attr "cpu" "ppca2"))
101 (define_insn_reservation "ppca2-fpcompare" 5
102 (and (eq_attr "type" "fpcompare")
103 (eq_attr "cpu" "ppca2"))
108 ;; Instructions from the same thread succeeding the floating-point
109 ;; divide cannot be executed until the floating-point divide has
110 ;; completed. Since there is nothing else we can do, this thread will
111 ;; just have to stall.
113 (define_insn_reservation "ppca2-ddiv" 72
114 (and (eq_attr "type" "ddiv")
115 (eq_attr "cpu" "ppca2"))
118 (define_insn_reservation "ppca2-sdiv" 59
119 (and (eq_attr "type" "sdiv")
120 (eq_attr "cpu" "ppca2"))
125 ;; Instructions from the same thread succeeding the floating-point
126 ;; divide cannot be executed until the floating-point divide has
127 ;; completed. Since there is nothing else we can do, this thread will
128 ;; just have to stall.
130 (define_insn_reservation "ppca2-dsqrt" 69
131 (and (eq_attr "type" "dsqrt")
132 (eq_attr "cpu" "ppca2"))
135 (define_insn_reservation "ppca2-ssqrt" 65
136 (and (eq_attr "type" "ssqrt")
137 (eq_attr "cpu" "ppca2"))