1 ;; Machine description of the Lattice Mico32 architecture for GNU C compiler.
2 ;; Contributed by Jon Beniston <jon@beniston.com>
4 ;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Include predicate and constraint definitions
23 (include "predicates.md")
24 (include "constraints.md")
29 [(RA_REGNUM 29) ; return address register.
33 ;; LM32 specific volatile operations
35 [(UNSPECV_BLOCKAGE 1)] ; prevent scheduling across pro/epilog boundaries
38 ;; LM32 specific operations
41 (UNSPEC_GOTOFF_HI16 3)
42 (UNSPEC_GOTOFF_LO16 4)]
45 ;; ---------------------------------
47 ;; ---------------------------------
50 "unknown,load,store,arith,compare,shift,multiply,divide,call,icall,ubranch,uibranch,cbranch"
51 (const_string "unknown"))
53 ;; ---------------------------------
54 ;; instruction lengths
55 ;; ---------------------------------
57 ; All instructions are 4 bytes
58 ; Except for branches that are out of range, and have to be implemented
60 (define_attr "length" ""
62 (eq_attr "type" "cbranch")
64 (lt (abs (minus (match_dup 2) (pc)))
74 ;; ---------------------------------
76 ;; ---------------------------------
78 (define_automaton "lm32")
80 (define_cpu_unit "x" "lm32")
81 (define_cpu_unit "m" "lm32")
82 (define_cpu_unit "w" "lm32")
84 (define_insn_reservation "singlecycle" 1
85 (eq_attr "type" "store,arith,call,icall,ubranch,uibranch,cbranch")
88 (define_insn_reservation "twocycle" 2
89 (eq_attr "type" "compare,shift,divide")
92 (define_insn_reservation "threecycle" 3
93 (eq_attr "type" "load,multiply")
96 ;; ---------------------------------
98 ;; ---------------------------------
100 (define_expand "movqi"
101 [(set (match_operand:QI 0 "general_operand" "")
102 (match_operand:QI 1 "general_operand" ""))]
106 if (can_create_pseudo_p ())
108 if (GET_CODE (operand0) == MEM)
110 /* Source operand for store must be in a register. */
111 operands[1] = force_reg (QImode, operands[1]);
116 (define_expand "movhi"
117 [(set (match_operand:HI 0 "general_operand" "")
118 (match_operand:HI 1 "general_operand" ""))]
122 if (can_create_pseudo_p ())
124 if (GET_CODE (operands[0]) == MEM)
126 /* Source operand for store must be in a register. */
127 operands[1] = force_reg (HImode, operands[1]);
132 (define_expand "movsi"
133 [(set (match_operand:SI 0 "general_operand" "")
134 (match_operand:SI 1 "general_operand" ""))]
138 if (can_create_pseudo_p ())
140 if (GET_CODE (operands[0]) == MEM
141 || (GET_CODE (operands[0]) == SUBREG
142 && GET_CODE (SUBREG_REG (operands[0])) == MEM))
144 /* Source operand for store must be in a register. */
145 operands[1] = force_reg (SImode, operands[1]);
149 if (flag_pic && symbolic_operand (operands[1], SImode))
151 if (GET_CODE (operands[1]) == LABEL_REF
152 || (GET_CODE (operands[1]) == SYMBOL_REF
153 && SYMBOL_REF_LOCAL_P (operands[1])
154 && !SYMBOL_REF_WEAK (operands[1])))
156 emit_insn (gen_movsi_gotoff_hi16 (operands[0], operands[1]));
157 emit_insn (gen_addsi3 (operands[0],
159 pic_offset_table_rtx));
160 emit_insn (gen_movsi_gotoff_lo16 (operands[0],
165 emit_insn (gen_movsi_got (operands[0], operands[1]));
166 crtl->uses_pic_offset_table = 1;
169 else if (flag_pic && GET_CODE (operands[1]) == CONST)
171 rtx op = XEXP (operands[1], 0);
172 if (GET_CODE (op) == PLUS)
174 rtx arg0 = XEXP (op, 0);
175 rtx arg1 = XEXP (op, 1);
176 if (GET_CODE (arg0) == LABEL_REF
177 || (GET_CODE (arg0) == SYMBOL_REF
178 && SYMBOL_REF_LOCAL_P (arg0)
179 && !SYMBOL_REF_WEAK (arg0)))
181 emit_insn (gen_movsi_gotoff_hi16 (operands[0], arg0));
182 emit_insn (gen_addsi3 (operands[0],
184 pic_offset_table_rtx));
185 emit_insn (gen_movsi_gotoff_lo16 (operands[0],
190 emit_insn (gen_movsi_got (operands[0], arg0));
191 emit_insn (gen_addsi3 (operands[0], operands[0], arg1));
192 crtl->uses_pic_offset_table = 1;
196 else if (!flag_pic && reloc_operand (operands[1], GET_MODE (operands[1])))
198 emit_insn (gen_rtx_SET (SImode, operands[0], gen_rtx_HIGH (SImode, operands[1])));
199 emit_insn (gen_rtx_SET (SImode, operands[0], gen_rtx_LO_SUM (SImode, operands[0], operands[1])));
202 else if (GET_CODE (operands[1]) == CONST_INT)
204 if (!(satisfies_constraint_K (operands[1])
205 || satisfies_constraint_L (operands[1])
206 || satisfies_constraint_U (operands[1])))
208 emit_insn (gen_movsi_insn (operands[0],
209 GEN_INT (INTVAL (operands[1]) & ~0xffff)));
210 emit_insn (gen_iorsi3 (operands[0],
212 GEN_INT (INTVAL (operands[1]) & 0xffff)));
218 (define_expand "movmemsi"
219 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
220 (match_operand:BLK 1 "general_operand" ""))
221 (use (match_operand:SI 2 "" ""))
222 (use (match_operand:SI 3 "const_int_operand" ""))])]
225 if (!lm32_expand_block_move (operands))
230 ;; ---------------------------------
232 ;; ---------------------------------
234 (define_insn "movsi_got"
235 [(set (match_operand:SI 0 "register_operand" "=r")
236 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOT))]
238 "lw %0, (gp+got(%1))"
239 [(set_attr "type" "load")]
242 (define_insn "movsi_gotoff_hi16"
243 [(set (match_operand:SI 0 "register_operand" "=r")
244 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF_HI16))]
246 "orhi %0, r0, gotoffhi16(%1)"
247 [(set_attr "type" "load")]
250 (define_insn "movsi_gotoff_lo16"
251 [(set (match_operand:SI 0 "register_operand" "=r")
252 (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "0")
253 (match_operand 2 "" ""))] UNSPEC_GOTOFF_LO16))]
255 "addi %0, %1, gotofflo16(%2)"
256 [(set_attr "type" "arith")]
259 (define_insn "*movsi_lo_sum"
260 [(set (match_operand:SI 0 "register_operand" "=r")
261 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
262 (match_operand:SI 2 "reloc_operand" "i")))]
265 [(set_attr "type" "arith")]
268 (define_insn "*movqi_insn"
269 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,m,r")
270 (match_operand:QI 1 "general_operand" "m,r,r,J,n"))]
271 "lm32_move_ok (QImode, operands)"
278 [(set_attr "type" "load,arith,store,store,arith")]
281 (define_insn "*movhi_insn"
282 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,m,r,r")
283 (match_operand:HI 1 "general_operand" "m,r,r,J,K,L"))]
284 "lm32_move_ok (HImode, operands)"
292 [(set_attr "type" "load,arith,store,store,arith,arith")]
295 (define_insn "movsi_insn"
296 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,m,r,r,r,r,r,r")
297 (match_operand:SI 1 "general_operand" "m,r,r,J,K,L,U,S,Y,n"))]
298 "lm32_move_ok (SImode, operands)"
309 ori %0, r0, lo(%1); orhi %0, %0, hi(%1)"
310 [(set_attr "type" "load,arith,store,store,arith,arith,arith,arith,arith,arith")]
313 ;; ---------------------------------
314 ;; sign and zero extension
315 ;; ---------------------------------
317 (define_insn "*extendqihi2"
318 [(set (match_operand:HI 0 "register_operand" "=r,r")
319 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
320 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
324 [(set_attr "type" "load,arith")]
327 (define_insn "zero_extendqihi2"
328 [(set (match_operand:HI 0 "register_operand" "=r,r")
329 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
334 [(set_attr "type" "load,arith")]
337 (define_insn "*extendqisi2"
338 [(set (match_operand:SI 0 "register_operand" "=r,r")
339 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
340 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
344 [(set_attr "type" "load,arith")]
347 (define_insn "zero_extendqisi2"
348 [(set (match_operand:SI 0 "register_operand" "=r,r")
349 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
354 [(set_attr "type" "load,arith")]
357 (define_insn "*extendhisi2"
358 [(set (match_operand:SI 0 "register_operand" "=r,r")
359 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
360 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
364 [(set_attr "type" "load,arith")]
367 (define_insn "zero_extendhisi2"
368 [(set (match_operand:SI 0 "register_operand" "=r,r")
369 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
374 [(set_attr "type" "load,arith")]
377 ;; ---------------------------------
379 ;; ---------------------------------
381 (define_expand "cstoresi4"
382 [(set (match_operand:SI 0 "register_operand")
383 (match_operator:SI 1 "ordered_comparison_operator"
384 [(match_operand:SI 2 "register_operand")
385 (match_operand:SI 3 "register_or_int_operand")]))]
388 lm32_expand_scc (operands);
393 [(set (match_operand:SI 0 "register_operand" "=r,r")
394 (eq:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
395 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
400 [(set_attr "type" "compare")]
404 [(set (match_operand:SI 0 "register_operand" "=r,r")
405 (ne:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
406 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
411 [(set_attr "type" "compare")]
415 [(set (match_operand:SI 0 "register_operand" "=r,r")
416 (gt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
417 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
422 [(set_attr "type" "compare")]
426 [(set (match_operand:SI 0 "register_operand" "=r,r")
427 (ge:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
428 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
433 [(set_attr "type" "compare")]
437 [(set (match_operand:SI 0 "register_operand" "=r,r")
438 (gtu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
439 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
444 [(set_attr "type" "compare")]
448 [(set (match_operand:SI 0 "register_operand" "=r,r")
449 (geu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
450 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
455 [(set_attr "type" "compare")]
458 ;; ---------------------------------
459 ;; unconditional branch
460 ;; ---------------------------------
463 [(set (pc) (label_ref (match_operand 0 "" "")))]
466 [(set_attr "type" "ubranch")]
469 (define_insn "indirect_jump"
470 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
473 [(set_attr "type" "uibranch")]
476 ;; ---------------------------------
477 ;; conditional branch
478 ;; ---------------------------------
480 (define_expand "cbranchsi4"
482 (if_then_else (match_operator 0 "comparison_operator"
483 [(match_operand:SI 1 "register_operand")
484 (match_operand:SI 2 "nonmemory_operand")])
485 (label_ref (match_operand 3 "" ""))
490 lm32_expand_conditional_branch (operands);
496 (if_then_else (eq:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
497 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
498 (label_ref (match_operand 2 "" ""))
502 return get_attr_length (insn) == 4
504 : "bne %z0,%z1,8\n\tbi %2";
506 [(set_attr "type" "cbranch")])
510 (if_then_else (ne:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
511 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
512 (label_ref (match_operand 2 "" ""))
516 return get_attr_length (insn) == 4
518 : "be %z0,%z1,8\n\tbi %2";
520 [(set_attr "type" "cbranch")])
524 (if_then_else (gt:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
525 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
526 (label_ref (match_operand 2 "" ""))
530 return get_attr_length (insn) == 4
532 : "bge %z1,%z0,8\n\tbi %2";
534 [(set_attr "type" "cbranch")])
538 (if_then_else (ge:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
539 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
540 (label_ref (match_operand 2 "" ""))
544 return get_attr_length (insn) == 4
546 : "bg %z1,%z0,8\n\tbi %2";
548 [(set_attr "type" "cbranch")])
552 (if_then_else (gtu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
553 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
554 (label_ref (match_operand 2 "" ""))
558 return get_attr_length (insn) == 4
560 : "bgeu %z1,%z0,8\n\tbi %2";
562 [(set_attr "type" "cbranch")])
566 (if_then_else (geu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
567 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
568 (label_ref (match_operand 2 "" ""))
572 return get_attr_length (insn) == 4
574 : "bgu %z1,%z0,8\n\tbi %2";
576 [(set_attr "type" "cbranch")])
578 ;; ---------------------------------
580 ;; ---------------------------------
582 (define_expand "call"
583 [(parallel [(call (match_operand 0 "" "")
584 (match_operand 1 "" ""))
585 (clobber (reg:SI RA_REGNUM))
590 rtx addr = XEXP (operands[0], 0);
591 if (!CONSTANT_ADDRESS_P (addr))
592 XEXP (operands[0], 0) = force_reg (Pmode, addr);
596 [(call (mem:SI (match_operand:SI 0 "call_operand" "r,s"))
597 (match_operand 1 "" ""))
598 (clobber (reg:SI RA_REGNUM))]
603 [(set_attr "type" "call,icall")]
606 (define_expand "call_value"
607 [(parallel [(set (match_operand 0 "" "")
608 (call (match_operand 1 "" "")
609 (match_operand 2 "" "")))
610 (clobber (reg:SI RA_REGNUM))
615 rtx addr = XEXP (operands[1], 0);
616 if (!CONSTANT_ADDRESS_P (addr))
617 XEXP (operands[1], 0) = force_reg (Pmode, addr);
620 (define_insn "*call_value"
621 [(set (match_operand 0 "register_operand" "=r,r")
622 (call (mem:SI (match_operand:SI 1 "call_operand" "r,s"))
623 (match_operand 2 "" "")))
624 (clobber (reg:SI RA_REGNUM))]
629 [(set_attr "type" "call,icall")]
632 (define_insn "return_internal"
633 [(use (match_operand:SI 0 "register_operand" "r"))
637 [(set_attr "type" "uibranch")]
640 (define_expand "return"
642 "lm32_can_use_return ()"
646 (define_expand "simple_return"
652 (define_insn "*return"
656 [(set_attr "type" "uibranch")]
659 (define_insn "*simple_return"
663 [(set_attr "type" "uibranch")]
666 ;; ---------------------------------
667 ;; switch/case statements
668 ;; ---------------------------------
670 (define_expand "tablejump"
671 [(set (pc) (match_operand 0 "register_operand" ""))
672 (use (label_ref (match_operand 1 "" "")))]
676 rtx target = operands[0];
679 /* For PIC, the table entry is relative to the start of the table. */
680 rtx label = gen_reg_rtx (SImode);
681 target = gen_reg_rtx (SImode);
682 emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
683 emit_insn (gen_addsi3 (target, operands[0], label));
685 emit_jump_insn (gen_tablejumpsi (target, operands[1]));
689 (define_insn "tablejumpsi"
690 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
691 (use (label_ref (match_operand 1 "" "")))]
694 [(set_attr "type" "ubranch")]
697 ;; ---------------------------------
699 ;; ---------------------------------
701 (define_insn "addsi3"
702 [(set (match_operand:SI 0 "register_operand" "=r,r")
703 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
704 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
709 [(set_attr "type" "arith")]
712 (define_insn "subsi3"
713 [(set (match_operand:SI 0 "register_operand" "=r")
714 (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
715 (match_operand:SI 2 "register_or_zero_operand" "rJ")))]
718 [(set_attr "type" "arith")]
721 (define_insn "mulsi3"
722 [(set (match_operand:SI 0 "register_operand" "=r,r")
723 (mult:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
724 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
725 "TARGET_MULTIPLY_ENABLED"
729 [(set_attr "type" "multiply")]
732 (define_insn "udivsi3"
733 [(set (match_operand:SI 0 "register_operand" "=r")
734 (udiv:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
735 (match_operand:SI 2 "register_operand" "r")))]
736 "TARGET_DIVIDE_ENABLED"
738 [(set_attr "type" "divide")]
741 (define_insn "umodsi3"
742 [(set (match_operand:SI 0 "register_operand" "=r")
743 (umod:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
744 (match_operand:SI 2 "register_operand" "r")))]
745 "TARGET_DIVIDE_ENABLED"
747 [(set_attr "type" "divide")]
750 ;; ---------------------------------
751 ;; negation and inversion
752 ;; ---------------------------------
754 (define_insn "negsi2"
755 [(set (match_operand:SI 0 "register_operand" "=r")
756 (neg:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
759 [(set_attr "type" "arith")]
762 (define_insn "one_cmplsi2"
763 [(set (match_operand:SI 0 "register_operand" "=r")
764 (not:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
767 [(set_attr "type" "arith")]
770 ;; ---------------------------------
772 ;; ---------------------------------
774 (define_insn "andsi3"
775 [(set (match_operand:SI 0 "register_operand" "=r,r")
776 (and:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
777 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
782 [(set_attr "type" "arith")]
785 (define_insn "iorsi3"
786 [(set (match_operand:SI 0 "register_operand" "=r,r")
787 (ior:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
788 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
793 [(set_attr "type" "arith")]
796 (define_insn "xorsi3"
797 [(set (match_operand:SI 0 "register_operand" "=r,r")
798 (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
799 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
804 [(set_attr "type" "arith")]
807 (define_insn "*norsi3"
808 [(set (match_operand:SI 0 "register_operand" "=r,r")
809 (not:SI (ior:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
810 (match_operand:SI 2 "register_or_L_operand" "r,L"))))]
815 [(set_attr "type" "arith")]
818 (define_insn "*xnorsi3"
819 [(set (match_operand:SI 0 "register_operand" "=r,r")
820 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
821 (match_operand:SI 2 "register_or_L_operand" "r,L"))))]
826 [(set_attr "type" "arith")]
829 ;; ---------------------------------
831 ;; ---------------------------------
833 (define_expand "ashlsi3"
834 [(set (match_operand:SI 0 "register_operand" "")
835 (ashift:SI (match_operand:SI 1 "register_or_zero_operand" "")
836 (match_operand:SI 2 "register_or_L_operand" "")))]
839 if (!TARGET_BARREL_SHIFT_ENABLED)
842 && satisfies_constraint_L (operands[2])
843 && INTVAL (operands[2]) <= 8)
846 int shifts = INTVAL (operands[2]);
849 emit_move_insn (operands[0], operands[1]);
851 emit_insn (gen_addsi3 (operands[0], operands[1], operands[1]));
852 for (i = 1; i < shifts; i++)
853 emit_insn (gen_addsi3 (operands[0], operands[0], operands[0]));
861 (define_insn "*ashlsi3"
862 [(set (match_operand:SI 0 "register_operand" "=r,r")
863 (ashift:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
864 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
865 "TARGET_BARREL_SHIFT_ENABLED"
869 [(set_attr "type" "shift")]
872 (define_expand "ashrsi3"
873 [(set (match_operand:SI 0 "register_operand" "")
874 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "")
875 (match_operand:SI 2 "register_or_L_operand" "")))]
878 if (!TARGET_BARREL_SHIFT_ENABLED)
881 && satisfies_constraint_L (operands[2])
882 && INTVAL (operands[2]) <= 8)
885 int shifts = INTVAL (operands[2]);
886 rtx one = GEN_INT (1);
889 emit_move_insn (operands[0], operands[1]);
891 emit_insn (gen_ashrsi3_1bit (operands[0], operands[1], one));
892 for (i = 1; i < shifts; i++)
893 emit_insn (gen_ashrsi3_1bit (operands[0], operands[0], one));
901 (define_insn "*ashrsi3"
902 [(set (match_operand:SI 0 "register_operand" "=r,r")
903 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
904 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
905 "TARGET_BARREL_SHIFT_ENABLED"
909 [(set_attr "type" "shift")]
912 (define_insn "ashrsi3_1bit"
913 [(set (match_operand:SI 0 "register_operand" "=r")
914 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
915 (match_operand:SI 2 "constant_M_operand" "M")))]
916 "!TARGET_BARREL_SHIFT_ENABLED"
918 [(set_attr "type" "shift")]
921 (define_expand "lshrsi3"
922 [(set (match_operand:SI 0 "register_operand" "")
923 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "")
924 (match_operand:SI 2 "register_or_L_operand" "")))]
927 if (!TARGET_BARREL_SHIFT_ENABLED)
930 && satisfies_constraint_L (operands[2])
931 && INTVAL (operands[2]) <= 8)
934 int shifts = INTVAL (operands[2]);
935 rtx one = GEN_INT (1);
938 emit_move_insn (operands[0], operands[1]);
940 emit_insn (gen_lshrsi3_1bit (operands[0], operands[1], one));
941 for (i = 1; i < shifts; i++)
942 emit_insn (gen_lshrsi3_1bit (operands[0], operands[0], one));
950 (define_insn "*lshrsi3"
951 [(set (match_operand:SI 0 "register_operand" "=r,r")
952 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
953 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
954 "TARGET_BARREL_SHIFT_ENABLED"
958 [(set_attr "type" "shift")]
961 (define_insn "lshrsi3_1bit"
962 [(set (match_operand:SI 0 "register_operand" "=r")
963 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
964 (match_operand:SI 2 "constant_M_operand" "M")))]
965 "!TARGET_BARREL_SHIFT_ENABLED"
967 [(set_attr "type" "shift")]
970 ;; ---------------------------------
971 ;; function entry / exit
972 ;; ---------------------------------
974 (define_expand "prologue"
979 lm32_expand_prologue ();
983 (define_expand "epilogue"
988 lm32_expand_epilogue ();
992 ;; ---------------------------------
994 ;; ---------------------------------
1000 [(set_attr "type" "arith")]
1003 ;; ---------------------------------
1005 ;; ---------------------------------
1007 ;; used to stop the scheduler from
1008 ;; scheduling code across certain boundaries
1010 (define_insn "blockage"
1011 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
1014 [(set_attr "length" "0")]