1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2014 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 (define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
41 (define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
45 (define_predicate "imm_for_neon_logic_operand"
46 (match_code "const_vector")
49 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
52 (define_predicate "neon_logic_op2"
53 (ior (match_operand 0 "imm_for_neon_logic_operand")
54 (match_operand 0 "s_register_operand")))
56 ;; Any general register.
57 (define_predicate "arm_hard_general_register_operand"
60 return REGNO (op) <= LAST_ARM_REGNUM;
64 (define_predicate "low_register_operand"
65 (and (match_code "reg")
66 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
68 ;; A low register or const_int.
69 (define_predicate "low_reg_or_int_operand"
70 (ior (match_code "const_int")
71 (match_operand 0 "low_register_operand")))
73 ;; Any core register, or any pseudo. */
74 (define_predicate "arm_general_register_operand"
75 (match_code "reg,subreg")
77 if (GET_CODE (op) == SUBREG)
81 && (REGNO (op) <= LAST_ARM_REGNUM
82 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
85 (define_predicate "vfp_register_operand"
86 (match_code "reg,subreg")
88 if (GET_CODE (op) == SUBREG)
91 /* We don't consider registers whose class is NO_REGS
92 to be a register operand. */
94 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
95 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
96 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
98 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
101 (define_predicate "vfp_hard_register_operand"
104 return (IS_VFP_REGNUM (REGNO (op)));
107 (define_predicate "zero_operand"
108 (and (match_code "const_int,const_double,const_vector")
109 (match_test "op == CONST0_RTX (mode)")))
111 ;; Match a register, or zero in the appropriate mode.
112 (define_predicate "reg_or_zero_operand"
113 (ior (match_operand 0 "s_register_operand")
114 (match_operand 0 "zero_operand")))
116 (define_special_predicate "subreg_lowpart_operator"
117 (and (match_code "subreg")
118 (match_test "subreg_lowpart_p (op)")))
120 ;; Reg, subreg(reg) or const_int.
121 (define_predicate "reg_or_int_operand"
122 (ior (match_code "const_int")
123 (match_operand 0 "s_register_operand")))
125 (define_predicate "arm_immediate_operand"
126 (and (match_code "const_int")
127 (match_test "const_ok_for_arm (INTVAL (op))")))
129 ;; A constant value which fits into two instructions, each taking
130 ;; an arithmetic constant operand for one of the words.
131 (define_predicate "arm_immediate_di_operand"
132 (and (match_code "const_int,const_double")
133 (match_test "arm_const_double_by_immediates (op)")))
135 (define_predicate "arm_neg_immediate_operand"
136 (and (match_code "const_int")
137 (match_test "const_ok_for_arm (-INTVAL (op))")))
139 (define_predicate "arm_not_immediate_operand"
140 (and (match_code "const_int")
141 (match_test "const_ok_for_arm (~INTVAL (op))")))
143 (define_predicate "const0_operand"
144 (and (match_code "const_int")
145 (match_test "INTVAL (op) == 0")))
147 ;; Something valid on the RHS of an ARM data-processing instruction
148 (define_predicate "arm_rhs_operand"
149 (ior (match_operand 0 "s_register_operand")
150 (match_operand 0 "arm_immediate_operand")))
152 (define_predicate "arm_rhsm_operand"
153 (ior (match_operand 0 "arm_rhs_operand")
154 (match_operand 0 "memory_operand")))
156 (define_predicate "const_int_I_operand"
157 (and (match_operand 0 "const_int_operand")
158 (match_test "satisfies_constraint_I (op)")))
160 (define_predicate "const_int_M_operand"
161 (and (match_operand 0 "const_int_operand")
162 (match_test "satisfies_constraint_M (op)")))
164 ;; This doesn't have to do much because the constant is already checked
165 ;; in the shift_operator predicate.
166 (define_predicate "shift_amount_operand"
167 (ior (and (match_test "TARGET_ARM")
168 (match_operand 0 "s_register_operand"))
169 (match_operand 0 "const_int_operand")))
171 (define_predicate "const_neon_scalar_shift_amount_operand"
172 (and (match_code "const_int")
173 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
174 && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
176 (define_predicate "ldrd_strd_offset_operand"
177 (and (match_operand 0 "const_int_operand")
178 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
180 (define_predicate "arm_add_operand"
181 (ior (match_operand 0 "arm_rhs_operand")
182 (match_operand 0 "arm_neg_immediate_operand")))
184 (define_predicate "arm_anddi_operand_neon"
185 (ior (match_operand 0 "s_register_operand")
186 (and (match_code "const_int")
187 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
188 (match_operand 0 "neon_inv_logic_op2")))
190 (define_predicate "arm_iordi_operand_neon"
191 (ior (match_operand 0 "s_register_operand")
192 (and (match_code "const_int")
193 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
194 (match_operand 0 "neon_logic_op2")))
196 (define_predicate "arm_xordi_operand"
197 (ior (match_operand 0 "s_register_operand")
198 (and (match_code "const_int")
199 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
201 (define_predicate "arm_adddi_operand"
202 (ior (match_operand 0 "s_register_operand")
203 (and (match_code "const_int")
204 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
206 (define_predicate "arm_addimm_operand"
207 (ior (match_operand 0 "arm_immediate_operand")
208 (match_operand 0 "arm_neg_immediate_operand")))
210 (define_predicate "arm_not_operand"
211 (ior (match_operand 0 "arm_rhs_operand")
212 (match_operand 0 "arm_not_immediate_operand")))
214 (define_predicate "arm_di_operand"
215 (ior (match_operand 0 "s_register_operand")
216 (match_operand 0 "arm_immediate_di_operand")))
218 ;; True if the operand is a memory reference which contains an
219 ;; offsettable address.
220 (define_predicate "offsettable_memory_operand"
221 (and (match_code "mem")
223 "offsettable_address_p (reload_completed | reload_in_progress,
224 mode, XEXP (op, 0))")))
226 ;; True if the operand is a memory operand that does not have an
227 ;; automodified base register (and thus will not generate output reloads).
228 (define_predicate "call_memory_operand"
229 (and (match_code "mem")
230 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
232 (match_operand 0 "memory_operand"))))
234 (define_predicate "arm_reload_memory_operand"
235 (and (match_code "mem,reg,subreg")
236 (match_test "(!CONSTANT_P (op)
237 && (true_regnum(op) == -1
239 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
241 (define_predicate "vfp_compare_operand"
242 (ior (match_operand 0 "s_register_operand")
243 (and (match_code "const_double")
244 (match_test "arm_const_double_rtx (op)"))))
246 (define_predicate "arm_float_compare_operand"
247 (if_then_else (match_test "TARGET_VFP")
248 (match_operand 0 "vfp_compare_operand")
249 (match_operand 0 "s_register_operand")))
251 ;; True for valid index operands.
252 (define_predicate "index_operand"
253 (ior (match_operand 0 "s_register_operand")
254 (and (match_operand 0 "immediate_operand")
255 (match_test "(!CONST_INT_P (op)
256 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
258 ;; True for operators that can be combined with a shift in ARM state.
259 (define_special_predicate "shiftable_operator"
260 (and (match_code "plus,minus,ior,xor,and")
261 (match_test "mode == GET_MODE (op)")))
263 (define_special_predicate "shiftable_operator_strict_it"
264 (and (match_code "plus,and")
265 (match_test "mode == GET_MODE (op)")))
267 ;; True for logical binary operators.
268 (define_special_predicate "logical_binary_operator"
269 (and (match_code "ior,xor,and")
270 (match_test "mode == GET_MODE (op)")))
272 ;; True for commutative operators
273 (define_special_predicate "commutative_binary_operator"
274 (and (match_code "ior,xor,and,plus")
275 (match_test "mode == GET_MODE (op)")))
277 ;; True for shift operators.
279 ;; * mult is only permitted with a constant shift amount
280 ;; * patterns that permit register shift amounts only in ARM mode use
281 ;; shift_amount_operand, patterns that always allow registers do not,
282 ;; so we don't have to worry about that sort of thing here.
283 (define_special_predicate "shift_operator"
284 (and (ior (ior (and (match_code "mult")
285 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
286 (and (match_code "rotate")
287 (match_test "CONST_INT_P (XEXP (op, 1))
288 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
289 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
290 (match_test "!CONST_INT_P (XEXP (op, 1))
291 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
292 (match_test "mode == GET_MODE (op)")))
294 (define_special_predicate "shift_nomul_operator"
295 (and (ior (and (match_code "rotate")
296 (match_test "CONST_INT_P (XEXP (op, 1))
297 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
298 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
299 (match_test "!CONST_INT_P (XEXP (op, 1))
300 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
301 (match_test "mode == GET_MODE (op)")))
303 ;; True for shift operators which can be used with saturation instructions.
304 (define_special_predicate "sat_shift_operator"
305 (and (ior (and (match_code "mult")
306 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
307 (and (match_code "ashift,ashiftrt")
308 (match_test "CONST_INT_P (XEXP (op, 1))
309 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
310 (match_test "mode == GET_MODE (op)")))
312 ;; True for MULT, to identify which variant of shift_operator is in use.
313 (define_special_predicate "mult_operator"
316 ;; True for operators that have 16-bit thumb variants. */
317 (define_special_predicate "thumb_16bit_operator"
318 (match_code "plus,minus,and,ior,xor"))
321 (define_special_predicate "equality_operator"
322 (match_code "eq,ne"))
324 ;; True for integer comparisons and, if FP is active, for comparisons
325 ;; other than LTGT or UNEQ.
326 (define_special_predicate "expandable_comparison_operator"
327 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
328 unordered,ordered,unlt,unle,unge,ungt"))
330 ;; Likewise, but only accept comparisons that are directly supported
331 ;; by ARM condition codes.
332 (define_special_predicate "arm_comparison_operator"
333 (and (match_operand 0 "expandable_comparison_operator")
334 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
336 (define_special_predicate "lt_ge_comparison_operator"
337 (match_code "lt,ge"))
339 ;; The vsel instruction only accepts the ARM condition codes listed below.
340 (define_special_predicate "arm_vsel_comparison_operator"
341 (and (match_operand 0 "expandable_comparison_operator")
342 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
343 || maybe_get_arm_condition_code (op) == ARM_GT
344 || maybe_get_arm_condition_code (op) == ARM_EQ
345 || maybe_get_arm_condition_code (op) == ARM_VS
346 || maybe_get_arm_condition_code (op) == ARM_LT
347 || maybe_get_arm_condition_code (op) == ARM_LE
348 || maybe_get_arm_condition_code (op) == ARM_NE
349 || maybe_get_arm_condition_code (op) == ARM_VC")))
351 (define_special_predicate "arm_cond_move_operator"
352 (if_then_else (match_test "arm_restrict_it")
353 (and (match_test "TARGET_FPU_ARMV8")
354 (match_operand 0 "arm_vsel_comparison_operator"))
355 (match_operand 0 "expandable_comparison_operator")))
357 (define_special_predicate "noov_comparison_operator"
358 (match_code "lt,ge,eq,ne"))
360 (define_special_predicate "minmax_operator"
361 (and (match_code "smin,smax,umin,umax")
362 (match_test "mode == GET_MODE (op)")))
364 (define_special_predicate "cc_register"
365 (and (match_code "reg")
366 (and (match_test "REGNO (op) == CC_REGNUM")
367 (ior (match_test "mode == GET_MODE (op)")
368 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
370 (define_special_predicate "dominant_cc_register"
373 if (mode == VOIDmode)
375 mode = GET_MODE (op);
377 if (GET_MODE_CLASS (mode) != MODE_CC)
381 return (cc_register (op, mode)
382 && (mode == CC_DNEmode
383 || mode == CC_DEQmode
384 || mode == CC_DLEmode
385 || mode == CC_DLTmode
386 || mode == CC_DGEmode
387 || mode == CC_DGTmode
388 || mode == CC_DLEUmode
389 || mode == CC_DLTUmode
390 || mode == CC_DGEUmode
391 || mode == CC_DGTUmode));
394 (define_special_predicate "arm_extendqisi_mem_op"
395 (and (match_operand 0 "memory_operand")
396 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
400 : memory_address_p (QImode, XEXP (op, 0))")))
402 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
403 (ior (match_operand 0 "arm_extendqisi_mem_op")
404 (match_operand 0 "s_register_operand")))
406 (define_predicate "power_of_two_operand"
407 (match_code "const_int")
409 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
411 return value != 0 && (value & (value - 1)) == 0;
414 (define_predicate "nonimmediate_di_operand"
415 (match_code "reg,subreg,mem")
417 if (s_register_operand (op, mode))
420 if (GET_CODE (op) == SUBREG)
421 op = SUBREG_REG (op);
423 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
426 (define_predicate "di_operand"
427 (ior (match_code "const_int,const_double")
428 (and (match_code "reg,subreg,mem")
429 (match_operand 0 "nonimmediate_di_operand"))))
431 (define_predicate "nonimmediate_soft_df_operand"
432 (match_code "reg,subreg,mem")
434 if (s_register_operand (op, mode))
437 if (GET_CODE (op) == SUBREG)
438 op = SUBREG_REG (op);
440 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
443 (define_predicate "soft_df_operand"
444 (ior (match_code "const_double")
445 (and (match_code "reg,subreg,mem")
446 (match_operand 0 "nonimmediate_soft_df_operand"))))
448 (define_special_predicate "load_multiple_operation"
449 (match_code "parallel")
451 return ldm_stm_operation_p (op, /*load=*/true, SImode,
452 /*consecutive=*/false,
453 /*return_pc=*/false);
456 (define_special_predicate "store_multiple_operation"
457 (match_code "parallel")
459 return ldm_stm_operation_p (op, /*load=*/false, SImode,
460 /*consecutive=*/false,
461 /*return_pc=*/false);
464 (define_special_predicate "pop_multiple_return"
465 (match_code "parallel")
467 return ldm_stm_operation_p (op, /*load=*/true, SImode,
468 /*consecutive=*/false,
472 (define_special_predicate "pop_multiple_fp"
473 (match_code "parallel")
475 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
476 /*consecutive=*/true,
477 /*return_pc=*/false);
480 (define_special_predicate "multi_register_push"
481 (match_code "parallel")
483 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
484 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
485 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
491 (define_predicate "push_mult_memory_operand"
494 /* ??? Given how PUSH_MULT is generated in the prologues, is there
495 any point in testing for thumb1 specially? All of the variants
496 use the same form. */
499 /* ??? No attempt is made to represent STMIA, or validate that
500 the stack adjustment matches the register count. This is
501 true of the ARM/Thumb2 path as well. */
502 rtx x = XEXP (op, 0);
503 if (GET_CODE (x) != PRE_MODIFY)
505 if (XEXP (x, 0) != stack_pointer_rtx)
508 if (GET_CODE (x) != PLUS)
510 if (XEXP (x, 0) != stack_pointer_rtx)
512 return CONST_INT_P (XEXP (x, 1));
515 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
516 return memory_operand (op, mode);
519 ;;-------------------------------------------------------------------------
524 (define_predicate "thumb1_cmp_operand"
525 (ior (and (match_code "reg,subreg")
526 (match_operand 0 "s_register_operand"))
527 (and (match_code "const_int")
528 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
530 (define_predicate "thumb1_cmpneg_operand"
531 (and (match_code "const_int")
532 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
534 ;; Return TRUE if a result can be stored in OP without clobbering the
535 ;; condition code register. Prior to reload we only accept a
536 ;; register. After reload we have to be able to handle memory as
537 ;; well, since a pseudo may not get a hard reg and reload cannot
538 ;; handle output-reloads on jump insns.
540 ;; We could possibly handle mem before reload as well, but that might
541 ;; complicate things with the need to handle increment
543 (define_predicate "thumb_cbrch_target_operand"
544 (and (match_code "reg,subreg,mem")
545 (ior (match_operand 0 "s_register_operand")
546 (and (match_test "reload_in_progress || reload_completed")
547 (match_operand 0 "memory_operand")))))
549 ;;-------------------------------------------------------------------------
554 (define_predicate "imm_or_reg_operand"
555 (ior (match_operand 0 "immediate_operand")
556 (match_operand 0 "register_operand")))
560 (define_predicate "const_multiple_of_8_operand"
561 (match_code "const_int")
563 unsigned HOST_WIDE_INT val = INTVAL (op);
564 return (val & 7) == 0;
567 (define_predicate "imm_for_neon_mov_operand"
568 (match_code "const_vector,const_int")
570 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
573 (define_predicate "imm_for_neon_lshift_operand"
574 (match_code "const_vector")
576 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
579 (define_predicate "imm_for_neon_rshift_operand"
580 (match_code "const_vector")
582 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
585 (define_predicate "imm_lshift_or_reg_neon"
586 (ior (match_operand 0 "s_register_operand")
587 (match_operand 0 "imm_for_neon_lshift_operand")))
589 (define_predicate "imm_rshift_or_reg_neon"
590 (ior (match_operand 0 "s_register_operand")
591 (match_operand 0 "imm_for_neon_rshift_operand")))
593 ;; Predicates for named expanders that overlap multiple ISAs.
595 (define_predicate "cmpdi_operand"
596 (and (match_test "TARGET_32BIT")
597 (match_operand 0 "arm_di_operand")))
599 ;; True if the operand is memory reference suitable for a ldrex/strex.
600 (define_predicate "arm_sync_memory_operand"
601 (and (match_operand 0 "memory_operand")
602 (match_code "reg" "0")))
604 ;; Predicates for parallel expanders based on mode.
605 (define_special_predicate "vect_par_constant_high"
606 (match_code "parallel")
608 HOST_WIDE_INT count = XVECLEN (op, 0);
610 int base = GET_MODE_NUNITS (mode);
613 || (count != base/2))
616 if (!VECTOR_MODE_P (mode))
619 for (i = 0; i < count; i++)
621 rtx elt = XVECEXP (op, 0, i);
624 if (!CONST_INT_P (elt))
628 if (val != (base/2) + i)
634 (define_special_predicate "vect_par_constant_low"
635 (match_code "parallel")
637 HOST_WIDE_INT count = XVECLEN (op, 0);
639 int base = GET_MODE_NUNITS (mode);
642 || (count != base/2))
645 if (!VECTOR_MODE_P (mode))
648 for (i = 0; i < count; i++)
650 rtx elt = XVECEXP (op, 0, i);
653 if (!CONST_INT_P (elt))
663 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
664 (and (match_code "const_double")
665 (match_test "TARGET_32BIT && TARGET_VFP
666 && vfp3_const_double_for_fract_bits (op)")))
668 (define_predicate "const_double_vcvt_power_of_two"
669 (and (match_code "const_double")
670 (match_test "TARGET_32BIT && TARGET_VFP
671 && vfp3_const_double_for_bits (op)")))
673 (define_predicate "neon_struct_operand"
674 (and (match_code "mem")
675 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
677 (define_predicate "neon_permissive_struct_operand"
678 (and (match_code "mem")
679 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
681 (define_predicate "neon_perm_struct_or_reg_operand"
682 (ior (match_operand 0 "neon_permissive_struct_operand")
683 (match_operand 0 "s_register_operand")))
685 (define_special_predicate "add_operator"
688 (define_predicate "mem_noofs_operand"
689 (and (match_code "mem")
690 (match_code "reg" "0")))
692 (define_predicate "call_insn_operand"
693 (ior (and (match_code "symbol_ref")
694 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
695 (match_operand 0 "s_register_operand")))