1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2014 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #ifndef GCC_AARCH64_PROTOS_H
23 #define GCC_AARCH64_PROTOS_H
27 The symbol is used in a load-address operation.
29 The symbol is used as the address in a MEM.
31 enum aarch64_symbol_context
37 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
38 high and lo relocs that calculate the base address using a PC
40 So to get the address of foo, we generate
44 To load or store something to foo, we could use the corresponding
45 load store variants that generate an
46 ldr x0, [x0,:lo12:foo]
48 str x1, [x0, :lo12:foo]
50 This corresponds to the small code model of the compiler.
52 SYMBOL_SMALL_GOT: Similar to the one above but this
53 gives us the GOT entry of the symbol being referred to :
54 Thus calculating the GOT entry for foo is done using the
55 following sequence of instructions. The ADRP instruction
56 gets us to the page containing the GOT entry of the symbol
57 and the got_lo12 gets us the actual offset in it.
60 ldr x0, [x0, :gotoff_lo12:foo]
62 This corresponds to the small PIC model of the compiler.
68 Each of of these represents a thread-local symbol, and corresponds to the
69 thread local storage relocation operator for the symbol being referred to.
73 Generate symbol accesses as a PC relative address using a single
74 instruction. To compute the address of symbol foo, we generate:
80 Generate symbol accesses via the GOT using a single PC relative
81 instruction. To compute the address of symbol foo, we generate:
85 The value of foo can subsequently read using:
89 SYMBOL_FORCE_TO_MEM : Global variables are addressed using
90 constant pool. All variable addresses are spilled into constant
91 pools. The constant pools themselves are addressed using PC
92 relative accesses. This only works for the large code model.
94 enum aarch64_symbol_type
96 SYMBOL_SMALL_ABSOLUTE
,
100 SYMBOL_SMALL_GOTTPREL
,
102 SYMBOL_TINY_ABSOLUTE
,
107 /* A set of tuning parameters contains references to size and time
108 cost models and vectors for address cost calculations, register
109 move costs and memory move costs. */
111 /* Scaled addressing modes can vary cost depending on the mode of the
112 value to be loaded/stored. QImode values cannot use scaled
115 struct scale_addr_mode_cost
123 /* Additional cost for addresses. */
124 struct cpu_addrcost_table
126 const struct scale_addr_mode_cost addr_scale_costs
;
127 const int pre_modify
;
128 const int post_modify
;
129 const int register_offset
;
130 const int register_extend
;
131 const int imm_offset
;
134 /* Additional costs for register copies. Cost is for one register. */
135 struct cpu_regmove_cost
143 /* Cost for vector insn classes. */
144 struct cpu_vector_cost
146 const int scalar_stmt_cost
; /* Cost of any scalar operation,
147 excluding load and store. */
148 const int scalar_load_cost
; /* Cost of scalar load. */
149 const int scalar_store_cost
; /* Cost of scalar store. */
150 const int vec_stmt_cost
; /* Cost of any vector operation,
151 excluding load, store,
153 scalar-to-vector operation. */
154 const int vec_to_scalar_cost
; /* Cost of vec-to-scalar operation. */
155 const int scalar_to_vec_cost
; /* Cost of scalar-to-vector
157 const int vec_align_load_cost
; /* Cost of aligned vector load. */
158 const int vec_unalign_load_cost
; /* Cost of unaligned vector load. */
159 const int vec_unalign_store_cost
; /* Cost of unaligned vector store. */
160 const int vec_store_cost
; /* Cost of vector store. */
161 const int cond_taken_branch_cost
; /* Cost of taken branch. */
162 const int cond_not_taken_branch_cost
; /* Cost of not taken branch. */
167 const struct cpu_cost_table
*const insn_extra_cost
;
168 const struct cpu_addrcost_table
*const addr_cost
;
169 const struct cpu_regmove_cost
*const regmove_cost
;
170 const struct cpu_vector_cost
*const vec_costs
;
171 const int memmov_cost
;
172 const int issue_rate
;
175 HOST_WIDE_INT
aarch64_initial_elimination_offset (unsigned, unsigned);
176 bool aarch64_bitmask_imm (HOST_WIDE_INT val
, enum machine_mode
);
177 bool aarch64_cannot_change_mode_class (enum machine_mode
,
180 enum aarch64_symbol_type
181 aarch64_classify_symbolic_expression (rtx
, enum aarch64_symbol_context
);
182 bool aarch64_constant_address_p (rtx
);
183 bool aarch64_expand_movmem (rtx
*);
184 bool aarch64_float_const_zero_rtx_p (rtx
);
185 bool aarch64_function_arg_regno_p (unsigned);
186 bool aarch64_gen_movmemqi (rtx
*);
187 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator
*);
188 bool aarch64_is_extend_from_extract (enum machine_mode
, rtx
, rtx
);
189 bool aarch64_is_long_call_p (rtx
);
190 bool aarch64_label_mentioned_p (rtx
);
191 bool aarch64_legitimate_pic_operand_p (rtx
);
192 bool aarch64_modes_tieable_p (enum machine_mode mode1
,
193 enum machine_mode mode2
);
194 bool aarch64_move_imm (HOST_WIDE_INT
, enum machine_mode
);
195 bool aarch64_mov_operand_p (rtx
, enum aarch64_symbol_context
,
197 bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode
, HOST_WIDE_INT
);
198 char *aarch64_output_scalar_simd_mov_immediate (rtx
, enum machine_mode
);
199 char *aarch64_output_simd_mov_immediate (rtx
, enum machine_mode
, unsigned);
200 bool aarch64_pad_arg_upward (enum machine_mode
, const_tree
);
201 bool aarch64_pad_reg_upward (enum machine_mode
, const_tree
, bool);
202 bool aarch64_regno_ok_for_base_p (int, bool);
203 bool aarch64_regno_ok_for_index_p (int, bool);
204 bool aarch64_simd_check_vect_par_cnst_half (rtx op
, enum machine_mode mode
,
206 bool aarch64_simd_imm_scalar_p (rtx x
, enum machine_mode mode
);
207 bool aarch64_simd_imm_zero_p (rtx
, enum machine_mode
);
208 bool aarch64_simd_scalar_immediate_valid_for_move (rtx
, enum machine_mode
);
209 bool aarch64_simd_shift_imm_p (rtx
, enum machine_mode
, bool);
210 bool aarch64_simd_valid_immediate (rtx
, enum machine_mode
, bool,
211 struct simd_immediate_info
*);
212 bool aarch64_symbolic_address_p (rtx
);
213 bool aarch64_uimm12_shift (HOST_WIDE_INT
);
214 const char *aarch64_output_casesi (rtx
*);
215 const char *aarch64_rewrite_selected_cpu (const char *name
);
217 enum aarch64_symbol_type
aarch64_classify_symbol (rtx
,
218 enum aarch64_symbol_context
);
219 enum aarch64_symbol_type
aarch64_classify_tls_symbol (rtx
);
220 enum reg_class
aarch64_regno_regclass (unsigned);
221 int aarch64_asm_preferred_eh_data_format (int, int);
222 enum machine_mode
aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
224 int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode
);
225 int aarch64_hard_regno_nregs (unsigned, enum machine_mode
);
226 int aarch64_simd_attr_length_move (rtx
);
227 int aarch64_uxt_size (int, HOST_WIDE_INT
);
228 rtx
aarch64_final_eh_return_addr (void);
229 rtx
aarch64_legitimize_reload_address (rtx
*, enum machine_mode
, int, int, int);
230 const char *aarch64_output_move_struct (rtx
*operands
);
231 rtx
aarch64_return_addr (int, rtx
);
232 rtx
aarch64_simd_gen_const_vector_dup (enum machine_mode
, int);
233 bool aarch64_simd_mem_operand_p (rtx
);
234 rtx
aarch64_simd_vect_par_cnst_half (enum machine_mode
, bool);
235 rtx
aarch64_tls_get_addr (void);
236 tree
aarch64_fold_builtin (tree
, int, tree
*, bool);
237 unsigned aarch64_dbx_register_number (unsigned);
238 unsigned aarch64_trampoline_size (void);
239 void aarch64_asm_output_labelref (FILE *, const char *);
240 void aarch64_elf_asm_named_section (const char *, unsigned, tree
);
241 void aarch64_expand_epilogue (bool);
242 void aarch64_expand_mov_immediate (rtx
, rtx
);
243 void aarch64_expand_prologue (void);
244 void aarch64_expand_vector_init (rtx
, rtx
);
245 void aarch64_function_profiler (FILE *, int);
246 void aarch64_init_cumulative_args (CUMULATIVE_ARGS
*, const_tree
, rtx
,
247 const_tree
, unsigned);
248 void aarch64_init_expanders (void);
249 void aarch64_print_operand (FILE *, rtx
, char);
250 void aarch64_print_operand_address (FILE *, rtx
);
251 void aarch64_emit_call_insn (rtx
);
253 /* Initialize builtins for SIMD intrinsics. */
254 void init_aarch64_simd_builtins (void);
256 void aarch64_simd_const_bounds (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
257 void aarch64_simd_disambiguate_copy (rtx
*, rtx
*, rtx
*, unsigned int);
259 /* Emit code to place a AdvSIMD pair result in memory locations (with equal
261 void aarch64_simd_emit_pair_result_insn (enum machine_mode
,
262 rtx (*intfn
) (rtx
, rtx
, rtx
), rtx
,
265 /* Expand builtins for SIMD intrinsics. */
266 rtx
aarch64_simd_expand_builtin (int, tree
, rtx
);
268 void aarch64_simd_lane_bounds (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
270 /* Emit code for reinterprets. */
271 void aarch64_simd_reinterpret (rtx
, rtx
);
273 void aarch64_split_128bit_move (rtx
, rtx
);
275 bool aarch64_split_128bit_move_p (rtx
, rtx
);
277 void aarch64_split_simd_combine (rtx
, rtx
, rtx
);
279 void aarch64_split_simd_move (rtx
, rtx
);
281 /* Check for a legitimate floating point constant for FMOV. */
282 bool aarch64_float_const_representable_p (rtx
);
284 #if defined (RTX_CODE)
286 bool aarch64_legitimate_address_p (enum machine_mode
, rtx
, RTX_CODE
, bool);
287 enum machine_mode
aarch64_select_cc_mode (RTX_CODE
, rtx
, rtx
);
288 rtx
aarch64_gen_compare_reg (RTX_CODE
, rtx
, rtx
);
289 rtx
aarch64_load_tp (rtx
);
291 void aarch64_expand_compare_and_swap (rtx op
[]);
292 void aarch64_split_compare_and_swap (rtx op
[]);
293 void aarch64_split_atomic_op (enum rtx_code
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
295 #endif /* RTX_CODE */
297 void aarch64_init_builtins (void);
298 rtx
aarch64_expand_builtin (tree exp
,
300 rtx subtarget ATTRIBUTE_UNUSED
,
301 enum machine_mode mode ATTRIBUTE_UNUSED
,
302 int ignore ATTRIBUTE_UNUSED
);
303 tree
aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED
);
306 aarch64_builtin_vectorized_function (tree fndecl
,
310 extern void aarch64_split_combinev16qi (rtx operands
[3]);
311 extern void aarch64_expand_vec_perm (rtx target
, rtx op0
, rtx op1
, rtx sel
);
313 aarch64_expand_vec_perm_const (rtx target
, rtx op0
, rtx op1
, rtx sel
);
314 void aarch64_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
315 #endif /* GCC_AARCH64_PROTOS_H */