* fold-const.c (c_getstr): Clamp STRING_LENGTH to STRING_SIZE.
[official-gcc.git] / gcc / lra-constraints.c
blob8be4d46c8ad79b68397e9ec6ab49a262ccec36d1
1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
107 #undef REG_OK_STRICT
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "memmodel.h"
119 #include "tm_p.h"
120 #include "expmed.h"
121 #include "optabs.h"
122 #include "regs.h"
123 #include "ira.h"
124 #include "recog.h"
125 #include "output.h"
126 #include "addresses.h"
127 #include "expr.h"
128 #include "cfgrtl.h"
129 #include "rtl-error.h"
130 #include "params.h"
131 #include "lra.h"
132 #include "lra-int.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 reload insns. */
138 static int bb_reload_num;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn *curr_insn;
144 static rtx curr_insn_set;
145 static basic_block curr_bb;
146 static lra_insn_recog_data_t curr_id;
147 static struct lra_static_insn_data *curr_static_id;
148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
156 /* Start numbers for new registers and insns at the current constraints
157 pass start. */
158 static int new_regno_start;
159 static int new_insn_uid_start;
161 /* If LOC is nonnull, strip any outer subreg from it. */
162 static inline rtx *
163 strip_subreg (rtx *loc)
165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
170 static int
171 get_try_hard_regno (int regno)
173 int hard_regno;
174 enum reg_class rclass;
176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177 hard_regno = lra_get_regno_hard_regno (regno);
178 if (hard_regno >= 0)
179 return hard_regno;
180 rclass = lra_get_allocno_class (regno);
181 if (rclass == NO_REGS)
182 return -1;
183 return ira_class_hard_regs[rclass][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
190 static int
191 get_hard_regno (rtx x, bool final_p)
193 rtx reg;
194 int hard_regno;
196 reg = x;
197 if (SUBREG_P (x))
198 reg = SUBREG_REG (x);
199 if (! REG_P (reg))
200 return -1;
201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202 hard_regno = lra_get_regno_hard_regno (hard_regno);
203 if (hard_regno < 0)
204 return -1;
205 if (final_p)
206 hard_regno = lra_get_elimination_hard_regno (hard_regno);
207 if (SUBREG_P (x))
208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 SUBREG_BYTE (x), GET_MODE (x));
210 return hard_regno;
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno)
220 int hard_regno;
222 if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223 hard_regno = lra_get_regno_hard_regno (regno);
224 if (hard_regno >= 0)
226 hard_regno = lra_get_elimination_hard_regno (hard_regno);
227 return REGNO_REG_CLASS (hard_regno);
229 if (regno >= new_regno_start)
230 return lra_get_allocno_class (regno);
231 return NO_REGS;
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
242 static bool
243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
245 enum reg_class rclass, common_class;
246 machine_mode reg_mode;
247 int class_size, hard_regno, nregs, i, j;
248 int regno = REGNO (reg);
250 if (new_class != NULL)
251 *new_class = NO_REGS;
252 if (regno < FIRST_PSEUDO_REGISTER)
254 rtx final_reg = reg;
255 rtx *final_loc = &final_reg;
257 lra_eliminate_reg_if_possible (final_loc);
258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
260 reg_mode = GET_MODE (reg);
261 rclass = get_reg_class (regno);
262 if (regno < new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn) >= new_insn_uid_start
269 && curr_insn_set != NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno >= new_regno_start && rclass == ALL_REGS)
278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 && ! hard_reg_set_subset_p (reg_class_contents[cl],
280 lra_no_alloc_regs)));
281 else
283 common_class = ira_reg_class_subset[rclass][cl];
284 if (new_class != NULL)
285 *new_class = common_class;
286 if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 lra_no_alloc_regs))
288 return false;
289 /* Check that there are enough allocatable regs. */
290 class_size = ira_class_hard_regs_num[common_class];
291 for (i = 0; i < class_size; i++)
293 hard_regno = ira_class_hard_regs[common_class][i];
294 nregs = hard_regno_nregs (hard_regno, reg_mode);
295 if (nregs == 1)
296 return true;
297 for (j = 0; j < nregs; j++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 hard_regno + j))
301 break;
302 if (j >= nregs)
303 return true;
305 return false;
309 /* Return true if REGNO satisfies a memory constraint. */
310 static bool
311 in_mem_p (int regno)
313 return get_reg_class (regno) == NO_REGS;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
318 reg. */
319 static int
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 rtx addr, addr_space_t as)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as));
325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326 return 0;
328 win:
329 return 1;
330 #else
331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332 #endif
335 namespace {
336 /* Temporarily eliminates registers in an address (for the lifetime of
337 the object). */
338 class address_eliminator {
339 public:
340 address_eliminator (struct address_info *ad);
341 ~address_eliminator ();
343 private:
344 struct address_info *m_ad;
345 rtx *m_base_loc;
346 rtx m_base_reg;
347 rtx *m_index_loc;
348 rtx m_index_reg;
352 address_eliminator::address_eliminator (struct address_info *ad)
353 : m_ad (ad),
354 m_base_loc (strip_subreg (ad->base_term)),
355 m_base_reg (NULL_RTX),
356 m_index_loc (strip_subreg (ad->index_term)),
357 m_index_reg (NULL_RTX)
359 if (m_base_loc != NULL)
361 m_base_reg = *m_base_loc;
362 lra_eliminate_reg_if_possible (m_base_loc);
363 if (m_ad->base_term2 != NULL)
364 *m_ad->base_term2 = *m_ad->base_term;
366 if (m_index_loc != NULL)
368 m_index_reg = *m_index_loc;
369 lra_eliminate_reg_if_possible (m_index_loc);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc && *m_base_loc != m_base_reg)
377 *m_base_loc = m_base_reg;
378 if (m_ad->base_term2 != NULL)
379 *m_ad->base_term2 = *m_ad->base_term;
381 if (m_index_loc && *m_index_loc != m_index_reg)
382 *m_index_loc = m_index_reg;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
386 static bool
387 valid_address_p (struct address_info *ad)
389 address_eliminator eliminator (ad);
390 return valid_address_p (ad->mode, *ad->outer, ad->as);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
395 static bool
396 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
398 struct address_info ad;
400 decompose_mem_address (&ad, op);
401 address_eliminator eliminator (&ad);
402 return constraint_satisfied_p (op, constraint);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
407 static bool
408 satisfies_address_constraint_p (struct address_info *ad,
409 enum constraint_num constraint)
411 address_eliminator eliminator (ad);
412 return constraint_satisfied_p (*ad->outer, constraint);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
417 static bool
418 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
420 struct address_info ad;
422 decompose_lea_address (&ad, &op);
423 return satisfies_address_constraint_p (&ad, constraint);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
429 void
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
435 rtx res;
437 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
438 ira_reg_equiv[i].memory = copy_rtx (res);
439 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
440 ira_reg_equiv[i].invariant = copy_rtx (res);
444 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
448 equivalences. */
449 static void
450 update_equiv (int regno)
452 rtx x;
454 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
455 ira_reg_equiv[regno].memory
456 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
457 NULL_RTX);
458 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
459 ira_reg_equiv[regno].invariant
460 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
461 NULL_RTX);
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
466 static rtx
467 get_equiv (rtx x)
469 int regno;
470 rtx res;
472 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv[regno].defined_p
474 || ! ira_reg_equiv[regno].profitable_p
475 || lra_get_regno_hard_regno (regno) >= 0)
476 return x;
477 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
479 if (targetm.cannot_substitute_mem_equiv_p (res))
480 return x;
481 return res;
483 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
484 return res;
485 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
486 return res;
487 gcc_unreachable ();
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
492 X. */
493 static rtx
494 get_equiv_with_elimination (rtx x, rtx_insn *insn)
496 rtx res = get_equiv (x);
498 if (x == res || CONSTANT_P (res))
499 return res;
500 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
505 static void
506 init_curr_operand_mode (void)
508 int nop = curr_static_id->n_operands;
509 for (int i = 0; i < nop; i++)
511 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
512 if (mode == VOIDmode)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
517 mode = Pmode;
518 else
519 mode = curr_static_id->operand[i].mode;
521 curr_operand_mode[i] = mode;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
530 struct input_reload
532 /* True for input reload of matched operands. */
533 bool match_p;
534 /* Reloaded value. */
535 rtx input;
536 /* Reload pseudo used. */
537 rtx reg;
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
546 /* Initiate data concerning reuse of input reloads for the current
547 insn. */
548 static void
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num = 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
561 static bool
562 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
563 enum reg_class rclass, bool in_subreg_p,
564 const char *title, rtx *result_reg)
566 int i, regno;
567 enum reg_class new_class;
568 bool unique_p = false;
570 if (type == OP_OUT)
572 *result_reg
573 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
574 return true;
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original))
579 for (i = 0; i < curr_insn_input_reloads_num; i++)
581 if (! curr_insn_input_reloads[i].match_p
582 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
583 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
585 rtx reg = curr_insn_input_reloads[i].reg;
586 regno = REGNO (reg);
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg) != mode)
592 if (in_subreg_p)
593 continue;
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
595 GET_MODE_SIZE (mode)))
596 continue;
597 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
598 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
599 continue;
601 *result_reg = reg;
602 if (lra_dump_file != NULL)
604 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
605 dump_value_slim (lra_dump_file, original, 1);
607 if (new_class != lra_get_allocno_class (regno))
608 lra_change_class (regno, new_class, ", change to", false);
609 if (lra_dump_file != NULL)
610 fprintf (lra_dump_file, "\n");
611 return false;
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original)
616 && REG_P (curr_insn_input_reloads[i].input)
617 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
618 && (GET_MODE (original)
619 != GET_MODE (curr_insn_input_reloads[i].input)))
620 unique_p = true;
622 *result_reg = (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg) (mode, original, rclass, title);
625 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
626 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
627 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
628 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
629 return true;
634 /* The page contains code to extract memory address parts. */
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 static inline bool
638 ok_for_index_p_nonstrict (rtx reg)
640 unsigned regno = REGNO (reg);
642 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
647 static inline bool
648 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
649 enum rtx_code outer_code, enum rtx_code index_code)
651 unsigned regno = REGNO (reg);
653 if (regno >= FIRST_PSEUDO_REGISTER)
654 return true;
655 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
663 /* Return the offset from REGNO of the least significant register
664 in (reg:MODE REGNO).
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
672 lra_constraint_offset (int regno, machine_mode mode)
674 lra_assert (regno < FIRST_PSEUDO_REGISTER);
676 scalar_int_mode int_mode;
677 if (WORDS_BIG_ENDIAN
678 && is_a <scalar_int_mode> (mode, &int_mode)
679 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
680 return hard_regno_nregs (regno, mode) - 1;
681 return 0;
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
693 negative value. */
694 static bool
695 operands_match_p (rtx x, rtx y, int y_hard_regno)
697 int i;
698 RTX_CODE code = GET_CODE (x);
699 const char *fmt;
701 if (x == y)
702 return true;
703 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
704 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
706 int j;
708 i = get_hard_regno (x, false);
709 if (i < 0)
710 goto slow;
712 if ((j = y_hard_regno) < 0)
713 goto slow;
715 i += lra_constraint_offset (i, GET_MODE (x));
716 j += lra_constraint_offset (j, GET_MODE (y));
718 return i == j;
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
727 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
733 || GET_CODE (y) == PRE_MODIFY)
734 return operands_match_p (x, XEXP (y, 0), -1);
736 slow:
738 if (code == REG && REG_P (y))
739 return REGNO (x) == REGNO (y);
741 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
742 && x == SUBREG_REG (y))
743 return true;
744 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
745 && SUBREG_REG (x) == y)
746 return true;
748 /* Now we have disposed of all the cases in which different rtx
749 codes can match. */
750 if (code != GET_CODE (y))
751 return false;
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x) != GET_MODE (y))
755 return false;
757 switch (code)
759 CASE_CONST_UNIQUE:
760 return false;
762 case LABEL_REF:
763 return label_ref_label (x) == label_ref_label (y);
764 case SYMBOL_REF:
765 return XSTR (x, 0) == XSTR (y, 0);
767 default:
768 break;
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
774 fmt = GET_RTX_FORMAT (code);
775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
777 int val, j;
778 switch (fmt[i])
780 case 'w':
781 if (XWINT (x, i) != XWINT (y, i))
782 return false;
783 break;
785 case 'i':
786 if (XINT (x, i) != XINT (y, i))
787 return false;
788 break;
790 case 'p':
791 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
792 return false;
793 break;
795 case 'e':
796 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
797 if (val == 0)
798 return false;
799 break;
801 case '0':
802 break;
804 case 'E':
805 if (XVECLEN (x, i) != XVECLEN (y, i))
806 return false;
807 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
809 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
810 if (val == 0)
811 return false;
813 break;
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
818 default:
819 gcc_unreachable ();
822 return true;
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
829 && CONSTANT_P (X) \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
842 static void
843 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
845 enum reg_class rclass;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn) >= new_insn_uid_start)
852 return;
853 if (GET_CODE (reg) == SUBREG)
854 reg = SUBREG_REG (reg);
855 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
856 return;
857 if (in_class_p (reg, cl, &rclass) && rclass != cl)
858 lra_change_class (REGNO (reg), rclass, " Change to", true);
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
863 returns NULL_RTX. */
864 static rtx
865 regno_val_use_in (unsigned int regno, rtx x)
867 const char *fmt;
868 int i, j;
869 rtx tem;
871 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
872 return x;
874 fmt = GET_RTX_FORMAT (GET_CODE (x));
875 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
877 if (fmt[i] == 'e')
879 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
880 return tem;
882 else if (fmt[i] == 'E')
883 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
884 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
885 return tem;
888 return NULL_RTX;
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
893 as REGNO. */
894 static bool
895 check_conflict_input_operands (int regno, signed char *ins)
897 int in;
898 int n_operands = curr_static_id->n_operands;
900 for (int nop = 0; nop < n_operands; nop++)
901 if (! curr_static_id->operand[nop].is_operator
902 && curr_static_id->operand[nop].type != OP_OUT)
904 for (int i = 0; (in = ins[i]) >= 0; i++)
905 if (in == nop)
906 break;
907 if (in < 0
908 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
909 return false;
911 return true;
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
921 static void
922 match_reload (signed char out, signed char *ins, signed char *outs,
923 enum reg_class goal_class, rtx_insn **before,
924 rtx_insn **after, bool early_clobber_p)
926 bool out_conflict;
927 int i, in;
928 rtx new_in_reg, new_out_reg, reg;
929 machine_mode inmode, outmode;
930 rtx in_rtx = *curr_id->operand_loc[ins[0]];
931 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
933 inmode = curr_operand_mode[ins[0]];
934 outmode = out < 0 ? inmode : curr_operand_mode[out];
935 push_to_sequence (*before);
936 if (inmode != outmode)
938 /* process_alt_operands has already checked that the mode sizes
939 are ordered. */
940 if (partial_subreg_p (outmode, inmode))
942 reg = new_in_reg
943 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
944 goal_class, "");
945 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
946 LRA_SUBREG_P (new_out_reg) = 1;
947 /* If the input reg is dying here, we can use the same hard
948 register for REG and IN_RTX. We do it only for original
949 pseudos as reload pseudos can die although original
950 pseudos still live where reload pseudos dies. */
951 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
952 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
953 && (!early_clobber_p
954 || check_conflict_input_operands(REGNO (in_rtx), ins)))
955 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
957 else
959 reg = new_out_reg
960 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
961 goal_class, "");
962 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
963 /* NEW_IN_REG is non-paradoxical subreg. We don't want
964 NEW_OUT_REG living above. We add clobber clause for
965 this. This is just a temporary clobber. We can remove
966 it at the end of LRA work. */
967 rtx_insn *clobber = emit_clobber (new_out_reg);
968 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
969 LRA_SUBREG_P (new_in_reg) = 1;
970 if (GET_CODE (in_rtx) == SUBREG)
972 rtx subreg_reg = SUBREG_REG (in_rtx);
974 /* If SUBREG_REG is dying here and sub-registers IN_RTX
975 and NEW_IN_REG are similar, we can use the same hard
976 register for REG and SUBREG_REG. */
977 if (REG_P (subreg_reg)
978 && (int) REGNO (subreg_reg) < lra_new_regno_start
979 && GET_MODE (subreg_reg) == outmode
980 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
981 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
982 && (! early_clobber_p
983 || check_conflict_input_operands (REGNO (subreg_reg),
984 ins)))
985 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
989 else
991 /* Pseudos have values -- see comments for lra_reg_info.
992 Different pseudos with the same value do not conflict even if
993 they live in the same place. When we create a pseudo we
994 assign value of original pseudo (if any) from which we
995 created the new pseudo. If we create the pseudo from the
996 input pseudo, the new pseudo will have no conflict with the
997 input pseudo which is wrong when the input pseudo lives after
998 the insn and as the new pseudo value is changed by the insn
999 output. Therefore we create the new pseudo from the output
1000 except the case when we have single matched dying input
1001 pseudo.
1003 We cannot reuse the current output register because we might
1004 have a situation like "a <- a op b", where the constraints
1005 force the second input operand ("b") to match the output
1006 operand ("a"). "b" must then be copied into a new register
1007 so that it doesn't clobber the current value of "a".
1009 We can not use the same value if the output pseudo is
1010 early clobbered or the input pseudo is mentioned in the
1011 output, e.g. as an address part in memory, because
1012 output reload will actually extend the pseudo liveness.
1013 We don't care about eliminable hard regs here as we are
1014 interesting only in pseudos. */
1016 /* Matching input's register value is the same as one of the other
1017 output operand. Output operands in a parallel insn must be in
1018 different registers. */
1019 out_conflict = false;
1020 if (REG_P (in_rtx))
1022 for (i = 0; outs[i] >= 0; i++)
1024 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1025 if (REG_P (other_out_rtx)
1026 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1027 != NULL_RTX))
1029 out_conflict = true;
1030 break;
1035 new_in_reg = new_out_reg
1036 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1037 && (int) REGNO (in_rtx) < lra_new_regno_start
1038 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1039 && (! early_clobber_p
1040 || check_conflict_input_operands (REGNO (in_rtx), ins))
1041 && (out < 0
1042 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1043 && !out_conflict
1044 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1045 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1046 goal_class, ""));
1048 /* In operand can be got from transformations before processing insn
1049 constraints. One example of such transformations is subreg
1050 reloading (see function simplify_operand_subreg). The new
1051 pseudos created by the transformations might have inaccurate
1052 class (ALL_REGS) and we should make their classes more
1053 accurate. */
1054 narrow_reload_pseudo_class (in_rtx, goal_class);
1055 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1056 *before = get_insns ();
1057 end_sequence ();
1058 /* Add the new pseudo to consider values of subsequent input reload
1059 pseudos. */
1060 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1061 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1062 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1063 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1064 for (i = 0; (in = ins[i]) >= 0; i++)
1066 lra_assert
1067 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1068 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1069 *curr_id->operand_loc[in] = new_in_reg;
1071 lra_update_dups (curr_id, ins);
1072 if (out < 0)
1073 return;
1074 /* See a comment for the input operand above. */
1075 narrow_reload_pseudo_class (out_rtx, goal_class);
1076 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1078 start_sequence ();
1079 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1080 emit_insn (*after);
1081 *after = get_insns ();
1082 end_sequence ();
1084 *curr_id->operand_loc[out] = new_out_reg;
1085 lra_update_dup (curr_id, out);
1088 /* Return register class which is union of all reg classes in insn
1089 constraint alternative string starting with P. */
1090 static enum reg_class
1091 reg_class_from_constraints (const char *p)
1093 int c, len;
1094 enum reg_class op_class = NO_REGS;
1097 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1099 case '#':
1100 case ',':
1101 return op_class;
1103 case 'g':
1104 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1105 break;
1107 default:
1108 enum constraint_num cn = lookup_constraint (p);
1109 enum reg_class cl = reg_class_for_constraint (cn);
1110 if (cl == NO_REGS)
1112 if (insn_extra_address_constraint (cn))
1113 op_class
1114 = (reg_class_subunion
1115 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1116 ADDRESS, SCRATCH)]);
1117 break;
1120 op_class = reg_class_subunion[op_class][cl];
1121 break;
1123 while ((p += len), c);
1124 return op_class;
1127 /* If OP is a register, return the class of the register as per
1128 get_reg_class, otherwise return NO_REGS. */
1129 static inline enum reg_class
1130 get_op_class (rtx op)
1132 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1135 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1136 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1137 SUBREG for VAL to make them equal. */
1138 static rtx_insn *
1139 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1141 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1143 /* Usually size of mem_pseudo is greater than val size but in
1144 rare cases it can be less as it can be defined by target
1145 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1146 if (! MEM_P (val))
1148 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1149 GET_CODE (val) == SUBREG
1150 ? SUBREG_REG (val) : val);
1151 LRA_SUBREG_P (val) = 1;
1153 else
1155 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1156 LRA_SUBREG_P (mem_pseudo) = 1;
1159 return to_p ? gen_move_insn (mem_pseudo, val)
1160 : gen_move_insn (val, mem_pseudo);
1163 /* Process a special case insn (register move), return true if we
1164 don't need to process it anymore. INSN should be a single set
1165 insn. Set up that RTL was changed through CHANGE_P and that hook
1166 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1167 SEC_MEM_P. */
1168 static bool
1169 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1171 int sregno, dregno;
1172 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1173 rtx_insn *before;
1174 enum reg_class dclass, sclass, secondary_class;
1175 secondary_reload_info sri;
1177 lra_assert (curr_insn_set != NULL_RTX);
1178 dreg = dest = SET_DEST (curr_insn_set);
1179 sreg = src = SET_SRC (curr_insn_set);
1180 if (GET_CODE (dest) == SUBREG)
1181 dreg = SUBREG_REG (dest);
1182 if (GET_CODE (src) == SUBREG)
1183 sreg = SUBREG_REG (src);
1184 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1185 return false;
1186 sclass = dclass = NO_REGS;
1187 if (REG_P (dreg))
1188 dclass = get_reg_class (REGNO (dreg));
1189 gcc_assert (dclass < LIM_REG_CLASSES);
1190 if (dclass == ALL_REGS)
1191 /* ALL_REGS is used for new pseudos created by transformations
1192 like reload of SUBREG_REG (see function
1193 simplify_operand_subreg). We don't know their class yet. We
1194 should figure out the class from processing the insn
1195 constraints not in this fast path function. Even if ALL_REGS
1196 were a right class for the pseudo, secondary_... hooks usually
1197 are not define for ALL_REGS. */
1198 return false;
1199 if (REG_P (sreg))
1200 sclass = get_reg_class (REGNO (sreg));
1201 gcc_assert (sclass < LIM_REG_CLASSES);
1202 if (sclass == ALL_REGS)
1203 /* See comments above. */
1204 return false;
1205 if (sclass == NO_REGS && dclass == NO_REGS)
1206 return false;
1207 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1208 && ((sclass != NO_REGS && dclass != NO_REGS)
1209 || (GET_MODE (src)
1210 != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1212 *sec_mem_p = true;
1213 return false;
1215 if (! REG_P (dreg) || ! REG_P (sreg))
1216 return false;
1217 sri.prev_sri = NULL;
1218 sri.icode = CODE_FOR_nothing;
1219 sri.extra_cost = 0;
1220 secondary_class = NO_REGS;
1221 /* Set up hard register for a reload pseudo for hook
1222 secondary_reload because some targets just ignore unassigned
1223 pseudos in the hook. */
1224 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1226 dregno = REGNO (dreg);
1227 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1229 else
1230 dregno = -1;
1231 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1233 sregno = REGNO (sreg);
1234 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1236 else
1237 sregno = -1;
1238 if (sclass != NO_REGS)
1239 secondary_class
1240 = (enum reg_class) targetm.secondary_reload (false, dest,
1241 (reg_class_t) sclass,
1242 GET_MODE (src), &sri);
1243 if (sclass == NO_REGS
1244 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1245 && dclass != NO_REGS))
1247 enum reg_class old_sclass = secondary_class;
1248 secondary_reload_info old_sri = sri;
1250 sri.prev_sri = NULL;
1251 sri.icode = CODE_FOR_nothing;
1252 sri.extra_cost = 0;
1253 secondary_class
1254 = (enum reg_class) targetm.secondary_reload (true, src,
1255 (reg_class_t) dclass,
1256 GET_MODE (src), &sri);
1257 /* Check the target hook consistency. */
1258 lra_assert
1259 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1260 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1261 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1263 if (sregno >= 0)
1264 reg_renumber [sregno] = -1;
1265 if (dregno >= 0)
1266 reg_renumber [dregno] = -1;
1267 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1268 return false;
1269 *change_p = true;
1270 new_reg = NULL_RTX;
1271 if (secondary_class != NO_REGS)
1272 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1273 secondary_class,
1274 "secondary");
1275 start_sequence ();
1276 if (sri.icode == CODE_FOR_nothing)
1277 lra_emit_move (new_reg, src);
1278 else
1280 enum reg_class scratch_class;
1282 scratch_class = (reg_class_from_constraints
1283 (insn_data[sri.icode].operand[2].constraint));
1284 scratch_reg = (lra_create_new_reg_with_unique_value
1285 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1286 scratch_class, "scratch"));
1287 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1288 src, scratch_reg));
1290 before = get_insns ();
1291 end_sequence ();
1292 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1293 if (new_reg != NULL_RTX)
1294 SET_SRC (curr_insn_set) = new_reg;
1295 else
1297 if (lra_dump_file != NULL)
1299 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1300 dump_insn_slim (lra_dump_file, curr_insn);
1302 lra_set_insn_deleted (curr_insn);
1303 return true;
1305 return false;
1308 /* The following data describe the result of process_alt_operands.
1309 The data are used in curr_insn_transform to generate reloads. */
1311 /* The chosen reg classes which should be used for the corresponding
1312 operands. */
1313 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1314 /* True if the operand should be the same as another operand and that
1315 other operand does not need a reload. */
1316 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1317 /* True if the operand does not need a reload. */
1318 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1319 /* True if the operand can be offsetable memory. */
1320 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1321 /* The number of an operand to which given operand can be matched to. */
1322 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1323 /* The number of elements in the following array. */
1324 static int goal_alt_dont_inherit_ops_num;
1325 /* Numbers of operands whose reload pseudos should not be inherited. */
1326 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1327 /* True if the insn commutative operands should be swapped. */
1328 static bool goal_alt_swapped;
1329 /* The chosen insn alternative. */
1330 static int goal_alt_number;
1332 /* True if the corresponding operand is the result of an equivalence
1333 substitution. */
1334 static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1336 /* The following five variables are used to choose the best insn
1337 alternative. They reflect final characteristics of the best
1338 alternative. */
1340 /* Number of necessary reloads and overall cost reflecting the
1341 previous value and other unpleasantness of the best alternative. */
1342 static int best_losers, best_overall;
1343 /* Overall number hard registers used for reloads. For example, on
1344 some targets we need 2 general registers to reload DFmode and only
1345 one floating point register. */
1346 static int best_reload_nregs;
1347 /* Overall number reflecting distances of previous reloading the same
1348 value. The distances are counted from the current BB start. It is
1349 used to improve inheritance chances. */
1350 static int best_reload_sum;
1352 /* True if the current insn should have no correspondingly input or
1353 output reloads. */
1354 static bool no_input_reloads_p, no_output_reloads_p;
1356 /* True if we swapped the commutative operands in the current
1357 insn. */
1358 static int curr_swapped;
1360 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1361 register of class CL. Add any input reloads to list BEFORE. AFTER
1362 is nonnull if *LOC is an automodified value; handle that case by
1363 adding the required output reloads to list AFTER. Return true if
1364 the RTL was changed.
1366 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1367 register. Return false if the address register is correct. */
1368 static bool
1369 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1370 enum reg_class cl)
1372 int regno;
1373 enum reg_class rclass, new_class;
1374 rtx reg;
1375 rtx new_reg;
1376 machine_mode mode;
1377 bool subreg_p, before_p = false;
1379 subreg_p = GET_CODE (*loc) == SUBREG;
1380 if (subreg_p)
1382 reg = SUBREG_REG (*loc);
1383 mode = GET_MODE (reg);
1385 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1386 between two registers with different classes, but there normally will
1387 be "mov" which transfers element of vector register into the general
1388 register, and this normally will be a subreg which should be reloaded
1389 as a whole. This is particularly likely to be triggered when
1390 -fno-split-wide-types specified. */
1391 if (!REG_P (reg)
1392 || in_class_p (reg, cl, &new_class)
1393 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1394 loc = &SUBREG_REG (*loc);
1397 reg = *loc;
1398 mode = GET_MODE (reg);
1399 if (! REG_P (reg))
1401 if (check_only_p)
1402 return true;
1403 /* Always reload memory in an address even if the target supports
1404 such addresses. */
1405 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1406 before_p = true;
1408 else
1410 regno = REGNO (reg);
1411 rclass = get_reg_class (regno);
1412 if (! check_only_p
1413 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1415 if (lra_dump_file != NULL)
1417 fprintf (lra_dump_file,
1418 "Changing pseudo %d in address of insn %u on equiv ",
1419 REGNO (reg), INSN_UID (curr_insn));
1420 dump_value_slim (lra_dump_file, *loc, 1);
1421 fprintf (lra_dump_file, "\n");
1423 *loc = copy_rtx (*loc);
1425 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1427 if (check_only_p)
1428 return true;
1429 reg = *loc;
1430 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1431 mode, reg, cl, subreg_p, "address", &new_reg))
1432 before_p = true;
1434 else if (new_class != NO_REGS && rclass != new_class)
1436 if (check_only_p)
1437 return true;
1438 lra_change_class (regno, new_class, " Change to", true);
1439 return false;
1441 else
1442 return false;
1444 if (before_p)
1446 push_to_sequence (*before);
1447 lra_emit_move (new_reg, reg);
1448 *before = get_insns ();
1449 end_sequence ();
1451 *loc = new_reg;
1452 if (after != NULL)
1454 start_sequence ();
1455 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1456 emit_insn (*after);
1457 *after = get_insns ();
1458 end_sequence ();
1460 return true;
1463 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1464 the insn to be inserted before curr insn. AFTER returns the
1465 the insn to be inserted after curr insn. ORIGREG and NEWREG
1466 are the original reg and new reg for reload. */
1467 static void
1468 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1469 rtx newreg)
1471 if (before)
1473 push_to_sequence (*before);
1474 lra_emit_move (newreg, origreg);
1475 *before = get_insns ();
1476 end_sequence ();
1478 if (after)
1480 start_sequence ();
1481 lra_emit_move (origreg, newreg);
1482 emit_insn (*after);
1483 *after = get_insns ();
1484 end_sequence ();
1488 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1489 static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1491 /* Make reloads for subreg in operand NOP with internal subreg mode
1492 REG_MODE, add new reloads for further processing. Return true if
1493 any change was done. */
1494 static bool
1495 simplify_operand_subreg (int nop, machine_mode reg_mode)
1497 int hard_regno;
1498 rtx_insn *before, *after;
1499 machine_mode mode, innermode;
1500 rtx reg, new_reg;
1501 rtx operand = *curr_id->operand_loc[nop];
1502 enum reg_class regclass;
1503 enum op_type type;
1505 before = after = NULL;
1507 if (GET_CODE (operand) != SUBREG)
1508 return false;
1510 mode = GET_MODE (operand);
1511 reg = SUBREG_REG (operand);
1512 innermode = GET_MODE (reg);
1513 type = curr_static_id->operand[nop].type;
1514 if (MEM_P (reg))
1516 const bool addr_was_valid
1517 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1518 alter_subreg (curr_id->operand_loc[nop], false);
1519 rtx subst = *curr_id->operand_loc[nop];
1520 lra_assert (MEM_P (subst));
1522 if (!addr_was_valid
1523 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1524 MEM_ADDR_SPACE (subst))
1525 || ((get_constraint_type (lookup_constraint
1526 (curr_static_id->operand[nop].constraint))
1527 != CT_SPECIAL_MEMORY)
1528 /* We still can reload address and if the address is
1529 valid, we can remove subreg without reloading its
1530 inner memory. */
1531 && valid_address_p (GET_MODE (subst),
1532 regno_reg_rtx
1533 [ira_class_hard_regs
1534 [base_reg_class (GET_MODE (subst),
1535 MEM_ADDR_SPACE (subst),
1536 ADDRESS, SCRATCH)][0]],
1537 MEM_ADDR_SPACE (subst))))
1539 /* If we change the address for a paradoxical subreg of memory, the
1540 new address might violate the necessary alignment or the access
1541 might be slow; take this into consideration. We need not worry
1542 about accesses beyond allocated memory for paradoxical memory
1543 subregs as we don't substitute such equiv memory (see processing
1544 equivalences in function lra_constraints) and because for spilled
1545 pseudos we allocate stack memory enough for the biggest
1546 corresponding paradoxical subreg.
1548 However, do not blindly simplify a (subreg (mem ...)) for
1549 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1550 data into a register when the inner is narrower than outer or
1551 missing important data from memory when the inner is wider than
1552 outer. This rule only applies to modes that are no wider than
1553 a word. */
1554 if (!(maybe_ne (GET_MODE_PRECISION (mode),
1555 GET_MODE_PRECISION (innermode))
1556 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1557 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1558 && WORD_REGISTER_OPERATIONS)
1559 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1560 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1561 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1562 && targetm.slow_unaligned_access (innermode,
1563 MEM_ALIGN (reg)))))
1564 return true;
1566 *curr_id->operand_loc[nop] = operand;
1568 /* But if the address was not valid, we cannot reload the MEM without
1569 reloading the address first. */
1570 if (!addr_was_valid)
1571 process_address (nop, false, &before, &after);
1573 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1574 enum reg_class rclass
1575 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1576 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1577 reg, rclass, TRUE, "slow mem", &new_reg))
1579 bool insert_before, insert_after;
1580 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1582 insert_before = (type != OP_OUT
1583 || partial_subreg_p (mode, innermode));
1584 insert_after = type != OP_IN;
1585 insert_move_for_subreg (insert_before ? &before : NULL,
1586 insert_after ? &after : NULL,
1587 reg, new_reg);
1589 SUBREG_REG (operand) = new_reg;
1591 /* Convert to MODE. */
1592 reg = operand;
1593 rclass
1594 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1595 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1596 rclass, TRUE, "slow mem", &new_reg))
1598 bool insert_before, insert_after;
1599 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1601 insert_before = type != OP_OUT;
1602 insert_after = type != OP_IN;
1603 insert_move_for_subreg (insert_before ? &before : NULL,
1604 insert_after ? &after : NULL,
1605 reg, new_reg);
1607 *curr_id->operand_loc[nop] = new_reg;
1608 lra_process_new_insns (curr_insn, before, after,
1609 "Inserting slow mem reload");
1610 return true;
1613 /* If the address was valid and became invalid, prefer to reload
1614 the memory. Typical case is when the index scale should
1615 correspond the memory. */
1616 *curr_id->operand_loc[nop] = operand;
1617 /* Do not return false here as the MEM_P (reg) will be processed
1618 later in this function. */
1620 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1622 alter_subreg (curr_id->operand_loc[nop], false);
1623 return true;
1625 else if (CONSTANT_P (reg))
1627 /* Try to simplify subreg of constant. It is usually result of
1628 equivalence substitution. */
1629 if (innermode == VOIDmode
1630 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1631 innermode = curr_static_id->operand[nop].mode;
1632 if ((new_reg = simplify_subreg (mode, reg, innermode,
1633 SUBREG_BYTE (operand))) != NULL_RTX)
1635 *curr_id->operand_loc[nop] = new_reg;
1636 return true;
1639 /* Put constant into memory when we have mixed modes. It generates
1640 a better code in most cases as it does not need a secondary
1641 reload memory. It also prevents LRA looping when LRA is using
1642 secondary reload memory again and again. */
1643 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1644 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1646 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1647 alter_subreg (curr_id->operand_loc[nop], false);
1648 return true;
1650 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1651 if there may be a problem accessing OPERAND in the outer
1652 mode. */
1653 if ((REG_P (reg)
1654 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1655 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1656 /* Don't reload paradoxical subregs because we could be looping
1657 having repeatedly final regno out of hard regs range. */
1658 && (hard_regno_nregs (hard_regno, innermode)
1659 >= hard_regno_nregs (hard_regno, mode))
1660 && simplify_subreg_regno (hard_regno, innermode,
1661 SUBREG_BYTE (operand), mode) < 0
1662 /* Don't reload subreg for matching reload. It is actually
1663 valid subreg in LRA. */
1664 && ! LRA_SUBREG_P (operand))
1665 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1667 enum reg_class rclass;
1669 if (REG_P (reg))
1670 /* There is a big probability that we will get the same class
1671 for the new pseudo and we will get the same insn which
1672 means infinite looping. So spill the new pseudo. */
1673 rclass = NO_REGS;
1674 else
1675 /* The class will be defined later in curr_insn_transform. */
1676 rclass
1677 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1679 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1680 rclass, TRUE, "subreg reg", &new_reg))
1682 bool insert_before, insert_after;
1683 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1685 insert_before = (type != OP_OUT
1686 || read_modify_subreg_p (operand));
1687 insert_after = (type != OP_IN);
1688 insert_move_for_subreg (insert_before ? &before : NULL,
1689 insert_after ? &after : NULL,
1690 reg, new_reg);
1692 SUBREG_REG (operand) = new_reg;
1693 lra_process_new_insns (curr_insn, before, after,
1694 "Inserting subreg reload");
1695 return true;
1697 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1698 IRA allocates hardreg to the inner pseudo reg according to its mode
1699 instead of the outermode, so the size of the hardreg may not be enough
1700 to contain the outermode operand, in that case we may need to insert
1701 reload for the reg. For the following two types of paradoxical subreg,
1702 we need to insert reload:
1703 1. If the op_type is OP_IN, and the hardreg could not be paired with
1704 other hardreg to contain the outermode operand
1705 (checked by in_hard_reg_set_p), we need to insert the reload.
1706 2. If the op_type is OP_OUT or OP_INOUT.
1708 Here is a paradoxical subreg example showing how the reload is generated:
1710 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1711 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1713 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1714 here, if reg107 is assigned to hardreg R15, because R15 is the last
1715 hardreg, compiler cannot find another hardreg to pair with R15 to
1716 contain TImode data. So we insert a TImode reload reg180 for it.
1717 After reload is inserted:
1719 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1720 (reg:DI 107 [ __comp ])) -1
1721 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1722 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1724 Two reload hard registers will be allocated to reg180 to save TImode data
1725 in LRA_assign.
1727 For LRA pseudos this should normally be handled by the biggest_mode
1728 mechanism. However, it's possible for new uses of an LRA pseudo
1729 to be introduced after we've allocated it, such as when undoing
1730 inheritance, and the allocated register might not then be appropriate
1731 for the new uses. */
1732 else if (REG_P (reg)
1733 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1734 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1735 && (hard_regno_nregs (hard_regno, innermode)
1736 < hard_regno_nregs (hard_regno, mode))
1737 && (regclass = lra_get_allocno_class (REGNO (reg)))
1738 && (type != OP_IN
1739 || !in_hard_reg_set_p (reg_class_contents[regclass],
1740 mode, hard_regno)
1741 || overlaps_hard_reg_set_p (lra_no_alloc_regs,
1742 mode, hard_regno)))
1744 /* The class will be defined later in curr_insn_transform. */
1745 enum reg_class rclass
1746 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1748 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1749 rclass, TRUE, "paradoxical subreg", &new_reg))
1751 rtx subreg;
1752 bool insert_before, insert_after;
1754 PUT_MODE (new_reg, mode);
1755 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1756 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1758 insert_before = (type != OP_OUT);
1759 insert_after = (type != OP_IN);
1760 insert_move_for_subreg (insert_before ? &before : NULL,
1761 insert_after ? &after : NULL,
1762 reg, subreg);
1764 SUBREG_REG (operand) = new_reg;
1765 lra_process_new_insns (curr_insn, before, after,
1766 "Inserting paradoxical subreg reload");
1767 return true;
1769 return false;
1772 /* Return TRUE if X refers for a hard register from SET. */
1773 static bool
1774 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1776 int i, j, x_hard_regno;
1777 machine_mode mode;
1778 const char *fmt;
1779 enum rtx_code code;
1781 if (x == NULL_RTX)
1782 return false;
1783 code = GET_CODE (x);
1784 mode = GET_MODE (x);
1785 if (code == SUBREG)
1787 mode = wider_subreg_mode (x);
1788 x = SUBREG_REG (x);
1789 code = GET_CODE (x);
1792 if (REG_P (x))
1794 x_hard_regno = get_hard_regno (x, true);
1795 return (x_hard_regno >= 0
1796 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1798 if (MEM_P (x))
1800 struct address_info ad;
1802 decompose_mem_address (&ad, x);
1803 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1804 return true;
1805 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1806 return true;
1808 fmt = GET_RTX_FORMAT (code);
1809 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1811 if (fmt[i] == 'e')
1813 if (uses_hard_regs_p (XEXP (x, i), set))
1814 return true;
1816 else if (fmt[i] == 'E')
1818 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1819 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1820 return true;
1823 return false;
1826 /* Return true if OP is a spilled pseudo. */
1827 static inline bool
1828 spilled_pseudo_p (rtx op)
1830 return (REG_P (op)
1831 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1834 /* Return true if X is a general constant. */
1835 static inline bool
1836 general_constant_p (rtx x)
1838 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1841 static bool
1842 reg_in_class_p (rtx reg, enum reg_class cl)
1844 if (cl == NO_REGS)
1845 return get_reg_class (REGNO (reg)) == NO_REGS;
1846 return in_class_p (reg, cl, NULL);
1849 /* Return true if SET of RCLASS contains no hard regs which can be
1850 used in MODE. */
1851 static bool
1852 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1853 HARD_REG_SET &set,
1854 machine_mode mode)
1856 HARD_REG_SET temp;
1858 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1859 COPY_HARD_REG_SET (temp, set);
1860 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1861 return (hard_reg_set_subset_p
1862 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1866 /* Used to check validity info about small class input operands. It
1867 should be incremented at start of processing an insn
1868 alternative. */
1869 static unsigned int curr_small_class_check = 0;
1871 /* Update number of used inputs of class OP_CLASS for operand NOP.
1872 Return true if we have more such class operands than the number of
1873 available regs. */
1874 static bool
1875 update_and_check_small_class_inputs (int nop, enum reg_class op_class)
1877 static unsigned int small_class_check[LIM_REG_CLASSES];
1878 static int small_class_input_nums[LIM_REG_CLASSES];
1880 if (SMALL_REGISTER_CLASS_P (op_class)
1881 /* We are interesting in classes became small because of fixing
1882 some hard regs, e.g. by an user through GCC options. */
1883 && hard_reg_set_intersect_p (reg_class_contents[op_class],
1884 ira_no_alloc_regs)
1885 && (curr_static_id->operand[nop].type != OP_OUT
1886 || curr_static_id->operand[nop].early_clobber))
1888 if (small_class_check[op_class] == curr_small_class_check)
1889 small_class_input_nums[op_class]++;
1890 else
1892 small_class_check[op_class] = curr_small_class_check;
1893 small_class_input_nums[op_class] = 1;
1895 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1896 return true;
1898 return false;
1901 /* Major function to choose the current insn alternative and what
1902 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1903 negative we should consider only this alternative. Return false if
1904 we can not choose the alternative or find how to reload the
1905 operands. */
1906 static bool
1907 process_alt_operands (int only_alternative)
1909 bool ok_p = false;
1910 int nop, overall, nalt;
1911 int n_alternatives = curr_static_id->n_alternatives;
1912 int n_operands = curr_static_id->n_operands;
1913 /* LOSERS counts the operands that don't fit this alternative and
1914 would require loading. */
1915 int losers;
1916 int addr_losers;
1917 /* REJECT is a count of how undesirable this alternative says it is
1918 if any reloading is required. If the alternative matches exactly
1919 then REJECT is ignored, but otherwise it gets this much counted
1920 against it in addition to the reloading needed. */
1921 int reject;
1922 /* This is defined by '!' or '?' alternative constraint and added to
1923 reject. But in some cases it can be ignored. */
1924 int static_reject;
1925 int op_reject;
1926 /* The number of elements in the following array. */
1927 int early_clobbered_regs_num;
1928 /* Numbers of operands which are early clobber registers. */
1929 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1930 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1931 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1932 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1933 bool curr_alt_win[MAX_RECOG_OPERANDS];
1934 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1935 int curr_alt_matches[MAX_RECOG_OPERANDS];
1936 /* The number of elements in the following array. */
1937 int curr_alt_dont_inherit_ops_num;
1938 /* Numbers of operands whose reload pseudos should not be inherited. */
1939 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1940 rtx op;
1941 /* The register when the operand is a subreg of register, otherwise the
1942 operand itself. */
1943 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1944 /* The register if the operand is a register or subreg of register,
1945 otherwise NULL. */
1946 rtx operand_reg[MAX_RECOG_OPERANDS];
1947 int hard_regno[MAX_RECOG_OPERANDS];
1948 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1949 int reload_nregs, reload_sum;
1950 bool costly_p;
1951 enum reg_class cl;
1953 /* Calculate some data common for all alternatives to speed up the
1954 function. */
1955 for (nop = 0; nop < n_operands; nop++)
1957 rtx reg;
1959 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1960 /* The real hard regno of the operand after the allocation. */
1961 hard_regno[nop] = get_hard_regno (op, true);
1963 operand_reg[nop] = reg = op;
1964 biggest_mode[nop] = GET_MODE (op);
1965 if (GET_CODE (op) == SUBREG)
1967 biggest_mode[nop] = wider_subreg_mode (op);
1968 operand_reg[nop] = reg = SUBREG_REG (op);
1970 if (! REG_P (reg))
1971 operand_reg[nop] = NULL_RTX;
1972 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1973 || ((int) REGNO (reg)
1974 == lra_get_elimination_hard_regno (REGNO (reg))))
1975 no_subreg_reg_operand[nop] = reg;
1976 else
1977 operand_reg[nop] = no_subreg_reg_operand[nop]
1978 /* Just use natural mode for elimination result. It should
1979 be enough for extra constraints hooks. */
1980 = regno_reg_rtx[hard_regno[nop]];
1983 /* The constraints are made of several alternatives. Each operand's
1984 constraint looks like foo,bar,... with commas separating the
1985 alternatives. The first alternatives for all operands go
1986 together, the second alternatives go together, etc.
1988 First loop over alternatives. */
1989 alternative_mask preferred = curr_id->preferred_alternatives;
1990 if (only_alternative >= 0)
1991 preferred &= ALTERNATIVE_BIT (only_alternative);
1993 for (nalt = 0; nalt < n_alternatives; nalt++)
1995 /* Loop over operands for one constraint alternative. */
1996 if (!TEST_BIT (preferred, nalt))
1997 continue;
1999 curr_small_class_check++;
2000 overall = losers = addr_losers = 0;
2001 static_reject = reject = reload_nregs = reload_sum = 0;
2002 for (nop = 0; nop < n_operands; nop++)
2004 int inc = (curr_static_id
2005 ->operand_alternative[nalt * n_operands + nop].reject);
2006 if (lra_dump_file != NULL && inc != 0)
2007 fprintf (lra_dump_file,
2008 " Staticly defined alt reject+=%d\n", inc);
2009 static_reject += inc;
2011 reject += static_reject;
2012 early_clobbered_regs_num = 0;
2014 for (nop = 0; nop < n_operands; nop++)
2016 const char *p;
2017 char *end;
2018 int len, c, m, i, opalt_num, this_alternative_matches;
2019 bool win, did_match, offmemok, early_clobber_p;
2020 /* false => this operand can be reloaded somehow for this
2021 alternative. */
2022 bool badop;
2023 /* true => this operand can be reloaded if the alternative
2024 allows regs. */
2025 bool winreg;
2026 /* True if a constant forced into memory would be OK for
2027 this operand. */
2028 bool constmemok;
2029 enum reg_class this_alternative, this_costly_alternative;
2030 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2031 bool this_alternative_match_win, this_alternative_win;
2032 bool this_alternative_offmemok;
2033 bool scratch_p;
2034 machine_mode mode;
2035 enum constraint_num cn;
2037 opalt_num = nalt * n_operands + nop;
2038 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2040 /* Fast track for no constraints at all. */
2041 curr_alt[nop] = NO_REGS;
2042 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2043 curr_alt_win[nop] = true;
2044 curr_alt_match_win[nop] = false;
2045 curr_alt_offmemok[nop] = false;
2046 curr_alt_matches[nop] = -1;
2047 continue;
2050 op = no_subreg_reg_operand[nop];
2051 mode = curr_operand_mode[nop];
2053 win = did_match = winreg = offmemok = constmemok = false;
2054 badop = true;
2056 early_clobber_p = false;
2057 p = curr_static_id->operand_alternative[opalt_num].constraint;
2059 this_costly_alternative = this_alternative = NO_REGS;
2060 /* We update set of possible hard regs besides its class
2061 because reg class might be inaccurate. For example,
2062 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2063 is translated in HI_REGS because classes are merged by
2064 pairs and there is no accurate intermediate class. */
2065 CLEAR_HARD_REG_SET (this_alternative_set);
2066 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2067 this_alternative_win = false;
2068 this_alternative_match_win = false;
2069 this_alternative_offmemok = false;
2070 this_alternative_matches = -1;
2072 /* An empty constraint should be excluded by the fast
2073 track. */
2074 lra_assert (*p != 0 && *p != ',');
2076 op_reject = 0;
2077 /* Scan this alternative's specs for this operand; set WIN
2078 if the operand fits any letter in this alternative.
2079 Otherwise, clear BADOP if this operand could fit some
2080 letter after reloads, or set WINREG if this operand could
2081 fit after reloads provided the constraint allows some
2082 registers. */
2083 costly_p = false;
2086 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2088 case '\0':
2089 len = 0;
2090 break;
2091 case ',':
2092 c = '\0';
2093 break;
2095 case '&':
2096 early_clobber_p = true;
2097 break;
2099 case '$':
2100 op_reject += LRA_MAX_REJECT;
2101 break;
2102 case '^':
2103 op_reject += LRA_LOSER_COST_FACTOR;
2104 break;
2106 case '#':
2107 /* Ignore rest of this alternative. */
2108 c = '\0';
2109 break;
2111 case '0': case '1': case '2': case '3': case '4':
2112 case '5': case '6': case '7': case '8': case '9':
2114 int m_hregno;
2115 bool match_p;
2117 m = strtoul (p, &end, 10);
2118 p = end;
2119 len = 0;
2120 lra_assert (nop > m);
2122 /* Reject matches if we don't know which operand is
2123 bigger. This situation would arguably be a bug in
2124 an .md pattern, but could also occur in a user asm. */
2125 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2126 GET_MODE_SIZE (biggest_mode[nop])))
2127 break;
2129 /* Don't match wrong asm insn operands for proper
2130 diagnostic later. */
2131 if (INSN_CODE (curr_insn) < 0
2132 && (curr_operand_mode[m] == BLKmode
2133 || curr_operand_mode[nop] == BLKmode)
2134 && curr_operand_mode[m] != curr_operand_mode[nop])
2135 break;
2137 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2138 /* We are supposed to match a previous operand.
2139 If we do, we win if that one did. If we do
2140 not, count both of the operands as losers.
2141 (This is too conservative, since most of the
2142 time only a single reload insn will be needed
2143 to make the two operands win. As a result,
2144 this alternative may be rejected when it is
2145 actually desirable.) */
2146 match_p = false;
2147 if (operands_match_p (*curr_id->operand_loc[nop],
2148 *curr_id->operand_loc[m], m_hregno))
2150 /* We should reject matching of an early
2151 clobber operand if the matching operand is
2152 not dying in the insn. */
2153 if (! curr_static_id->operand[m].early_clobber
2154 || operand_reg[nop] == NULL_RTX
2155 || (find_regno_note (curr_insn, REG_DEAD,
2156 REGNO (op))
2157 || REGNO (op) == REGNO (operand_reg[m])))
2158 match_p = true;
2160 if (match_p)
2162 /* If we are matching a non-offsettable
2163 address where an offsettable address was
2164 expected, then we must reject this
2165 combination, because we can't reload
2166 it. */
2167 if (curr_alt_offmemok[m]
2168 && MEM_P (*curr_id->operand_loc[m])
2169 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2170 continue;
2172 else
2174 /* Operands don't match. Both operands must
2175 allow a reload register, otherwise we
2176 cannot make them match. */
2177 if (curr_alt[m] == NO_REGS)
2178 break;
2179 /* Retroactively mark the operand we had to
2180 match as a loser, if it wasn't already and
2181 it wasn't matched to a register constraint
2182 (e.g it might be matched by memory). */
2183 if (curr_alt_win[m]
2184 && (operand_reg[m] == NULL_RTX
2185 || hard_regno[m] < 0))
2187 losers++;
2188 reload_nregs
2189 += (ira_reg_class_max_nregs[curr_alt[m]]
2190 [GET_MODE (*curr_id->operand_loc[m])]);
2193 /* Prefer matching earlyclobber alternative as
2194 it results in less hard regs required for
2195 the insn than a non-matching earlyclobber
2196 alternative. */
2197 if (curr_static_id->operand[m].early_clobber)
2199 if (lra_dump_file != NULL)
2200 fprintf
2201 (lra_dump_file,
2202 " %d Matching earlyclobber alt:"
2203 " reject--\n",
2204 nop);
2205 reject--;
2207 /* Otherwise we prefer no matching
2208 alternatives because it gives more freedom
2209 in RA. */
2210 else if (operand_reg[nop] == NULL_RTX
2211 || (find_regno_note (curr_insn, REG_DEAD,
2212 REGNO (operand_reg[nop]))
2213 == NULL_RTX))
2215 if (lra_dump_file != NULL)
2216 fprintf
2217 (lra_dump_file,
2218 " %d Matching alt: reject+=2\n",
2219 nop);
2220 reject += 2;
2223 /* If we have to reload this operand and some
2224 previous operand also had to match the same
2225 thing as this operand, we don't know how to do
2226 that. */
2227 if (!match_p || !curr_alt_win[m])
2229 for (i = 0; i < nop; i++)
2230 if (curr_alt_matches[i] == m)
2231 break;
2232 if (i < nop)
2233 break;
2235 else
2236 did_match = true;
2238 this_alternative_matches = m;
2239 /* This can be fixed with reloads if the operand
2240 we are supposed to match can be fixed with
2241 reloads. */
2242 badop = false;
2243 this_alternative = curr_alt[m];
2244 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2245 winreg = this_alternative != NO_REGS;
2246 break;
2249 case 'g':
2250 if (MEM_P (op)
2251 || general_constant_p (op)
2252 || spilled_pseudo_p (op))
2253 win = true;
2254 cl = GENERAL_REGS;
2255 goto reg;
2257 default:
2258 cn = lookup_constraint (p);
2259 switch (get_constraint_type (cn))
2261 case CT_REGISTER:
2262 cl = reg_class_for_constraint (cn);
2263 if (cl != NO_REGS)
2264 goto reg;
2265 break;
2267 case CT_CONST_INT:
2268 if (CONST_INT_P (op)
2269 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2270 win = true;
2271 break;
2273 case CT_MEMORY:
2274 if (MEM_P (op)
2275 && satisfies_memory_constraint_p (op, cn))
2276 win = true;
2277 else if (spilled_pseudo_p (op))
2278 win = true;
2280 /* If we didn't already win, we can reload constants
2281 via force_const_mem or put the pseudo value into
2282 memory, or make other memory by reloading the
2283 address like for 'o'. */
2284 if (CONST_POOL_OK_P (mode, op)
2285 || MEM_P (op) || REG_P (op)
2286 /* We can restore the equiv insn by a
2287 reload. */
2288 || equiv_substition_p[nop])
2289 badop = false;
2290 constmemok = true;
2291 offmemok = true;
2292 break;
2294 case CT_ADDRESS:
2295 /* An asm operand with an address constraint
2296 that doesn't satisfy address_operand has
2297 is_address cleared, so that we don't try to
2298 make a non-address fit. */
2299 if (!curr_static_id->operand[nop].is_address)
2300 break;
2301 /* If we didn't already win, we can reload the address
2302 into a base register. */
2303 if (satisfies_address_constraint_p (op, cn))
2304 win = true;
2305 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2306 ADDRESS, SCRATCH);
2307 badop = false;
2308 goto reg;
2310 case CT_FIXED_FORM:
2311 if (constraint_satisfied_p (op, cn))
2312 win = true;
2313 break;
2315 case CT_SPECIAL_MEMORY:
2316 if (MEM_P (op)
2317 && satisfies_memory_constraint_p (op, cn))
2318 win = true;
2319 else if (spilled_pseudo_p (op))
2320 win = true;
2321 break;
2323 break;
2325 reg:
2326 this_alternative = reg_class_subunion[this_alternative][cl];
2327 IOR_HARD_REG_SET (this_alternative_set,
2328 reg_class_contents[cl]);
2329 if (costly_p)
2331 this_costly_alternative
2332 = reg_class_subunion[this_costly_alternative][cl];
2333 IOR_HARD_REG_SET (this_costly_alternative_set,
2334 reg_class_contents[cl]);
2336 if (mode == BLKmode)
2337 break;
2338 winreg = true;
2339 if (REG_P (op))
2341 if (hard_regno[nop] >= 0
2342 && in_hard_reg_set_p (this_alternative_set,
2343 mode, hard_regno[nop]))
2344 win = true;
2345 else if (hard_regno[nop] < 0
2346 && in_class_p (op, this_alternative, NULL))
2347 win = true;
2349 break;
2351 if (c != ' ' && c != '\t')
2352 costly_p = c == '*';
2354 while ((p += len), c);
2356 scratch_p = (operand_reg[nop] != NULL_RTX
2357 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2358 /* Record which operands fit this alternative. */
2359 if (win)
2361 this_alternative_win = true;
2362 if (operand_reg[nop] != NULL_RTX)
2364 if (hard_regno[nop] >= 0)
2366 if (in_hard_reg_set_p (this_costly_alternative_set,
2367 mode, hard_regno[nop]))
2369 if (lra_dump_file != NULL)
2370 fprintf (lra_dump_file,
2371 " %d Costly set: reject++\n",
2372 nop);
2373 reject++;
2376 else
2378 /* Prefer won reg to spilled pseudo under other
2379 equal conditions for possibe inheritance. */
2380 if (! scratch_p)
2382 if (lra_dump_file != NULL)
2383 fprintf
2384 (lra_dump_file,
2385 " %d Non pseudo reload: reject++\n",
2386 nop);
2387 reject++;
2389 if (in_class_p (operand_reg[nop],
2390 this_costly_alternative, NULL))
2392 if (lra_dump_file != NULL)
2393 fprintf
2394 (lra_dump_file,
2395 " %d Non pseudo costly reload:"
2396 " reject++\n",
2397 nop);
2398 reject++;
2401 /* We simulate the behavior of old reload here.
2402 Although scratches need hard registers and it
2403 might result in spilling other pseudos, no reload
2404 insns are generated for the scratches. So it
2405 might cost something but probably less than old
2406 reload pass believes. */
2407 if (scratch_p)
2409 if (lra_dump_file != NULL)
2410 fprintf (lra_dump_file,
2411 " %d Scratch win: reject+=2\n",
2412 nop);
2413 reject += 2;
2417 else if (did_match)
2418 this_alternative_match_win = true;
2419 else
2421 int const_to_mem = 0;
2422 bool no_regs_p;
2424 reject += op_reject;
2425 /* Never do output reload of stack pointer. It makes
2426 impossible to do elimination when SP is changed in
2427 RTL. */
2428 if (op == stack_pointer_rtx && ! frame_pointer_needed
2429 && curr_static_id->operand[nop].type != OP_IN)
2430 goto fail;
2432 /* If this alternative asks for a specific reg class, see if there
2433 is at least one allocatable register in that class. */
2434 no_regs_p
2435 = (this_alternative == NO_REGS
2436 || (hard_reg_set_subset_p
2437 (reg_class_contents[this_alternative],
2438 lra_no_alloc_regs)));
2440 /* For asms, verify that the class for this alternative is possible
2441 for the mode that is specified. */
2442 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2444 int i;
2445 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2446 if (targetm.hard_regno_mode_ok (i, mode)
2447 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2448 mode, i))
2449 break;
2450 if (i == FIRST_PSEUDO_REGISTER)
2451 winreg = false;
2454 /* If this operand accepts a register, and if the
2455 register class has at least one allocatable register,
2456 then this operand can be reloaded. */
2457 if (winreg && !no_regs_p)
2458 badop = false;
2460 if (badop)
2462 if (lra_dump_file != NULL)
2463 fprintf (lra_dump_file,
2464 " alt=%d: Bad operand -- refuse\n",
2465 nalt);
2466 goto fail;
2469 if (this_alternative != NO_REGS)
2471 HARD_REG_SET available_regs;
2473 COPY_HARD_REG_SET (available_regs,
2474 reg_class_contents[this_alternative]);
2475 AND_COMPL_HARD_REG_SET
2476 (available_regs,
2477 ira_prohibited_class_mode_regs[this_alternative][mode]);
2478 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
2479 if (hard_reg_set_empty_p (available_regs))
2481 /* There are no hard regs holding a value of given
2482 mode. */
2483 if (offmemok)
2485 this_alternative = NO_REGS;
2486 if (lra_dump_file != NULL)
2487 fprintf (lra_dump_file,
2488 " %d Using memory because of"
2489 " a bad mode: reject+=2\n",
2490 nop);
2491 reject += 2;
2493 else
2495 if (lra_dump_file != NULL)
2496 fprintf (lra_dump_file,
2497 " alt=%d: Wrong mode -- refuse\n",
2498 nalt);
2499 goto fail;
2504 /* If not assigned pseudo has a class which a subset of
2505 required reg class, it is a less costly alternative
2506 as the pseudo still can get a hard reg of necessary
2507 class. */
2508 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2509 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2510 && ira_class_subset_p[this_alternative][cl])
2512 if (lra_dump_file != NULL)
2513 fprintf
2514 (lra_dump_file,
2515 " %d Super set class reg: reject-=3\n", nop);
2516 reject -= 3;
2519 this_alternative_offmemok = offmemok;
2520 if (this_costly_alternative != NO_REGS)
2522 if (lra_dump_file != NULL)
2523 fprintf (lra_dump_file,
2524 " %d Costly loser: reject++\n", nop);
2525 reject++;
2527 /* If the operand is dying, has a matching constraint,
2528 and satisfies constraints of the matched operand
2529 which failed to satisfy the own constraints, most probably
2530 the reload for this operand will be gone. */
2531 if (this_alternative_matches >= 0
2532 && !curr_alt_win[this_alternative_matches]
2533 && REG_P (op)
2534 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2535 && (hard_regno[nop] >= 0
2536 ? in_hard_reg_set_p (this_alternative_set,
2537 mode, hard_regno[nop])
2538 : in_class_p (op, this_alternative, NULL)))
2540 if (lra_dump_file != NULL)
2541 fprintf
2542 (lra_dump_file,
2543 " %d Dying matched operand reload: reject++\n",
2544 nop);
2545 reject++;
2547 else
2549 /* Strict_low_part requires to reload the register
2550 not the sub-register. In this case we should
2551 check that a final reload hard reg can hold the
2552 value mode. */
2553 if (curr_static_id->operand[nop].strict_low
2554 && REG_P (op)
2555 && hard_regno[nop] < 0
2556 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2557 && ira_class_hard_regs_num[this_alternative] > 0
2558 && (!targetm.hard_regno_mode_ok
2559 (ira_class_hard_regs[this_alternative][0],
2560 GET_MODE (*curr_id->operand_loc[nop]))))
2562 if (lra_dump_file != NULL)
2563 fprintf
2564 (lra_dump_file,
2565 " alt=%d: Strict low subreg reload -- refuse\n",
2566 nalt);
2567 goto fail;
2569 losers++;
2571 if (operand_reg[nop] != NULL_RTX
2572 /* Output operands and matched input operands are
2573 not inherited. The following conditions do not
2574 exactly describe the previous statement but they
2575 are pretty close. */
2576 && curr_static_id->operand[nop].type != OP_OUT
2577 && (this_alternative_matches < 0
2578 || curr_static_id->operand[nop].type != OP_IN))
2580 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2581 (operand_reg[nop])]
2582 .last_reload);
2584 /* The value of reload_sum has sense only if we
2585 process insns in their order. It happens only on
2586 the first constraints sub-pass when we do most of
2587 reload work. */
2588 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2589 reload_sum += last_reload - bb_reload_num;
2591 /* If this is a constant that is reloaded into the
2592 desired class by copying it to memory first, count
2593 that as another reload. This is consistent with
2594 other code and is required to avoid choosing another
2595 alternative when the constant is moved into memory.
2596 Note that the test here is precisely the same as in
2597 the code below that calls force_const_mem. */
2598 if (CONST_POOL_OK_P (mode, op)
2599 && ((targetm.preferred_reload_class
2600 (op, this_alternative) == NO_REGS)
2601 || no_input_reloads_p))
2603 const_to_mem = 1;
2604 if (! no_regs_p)
2605 losers++;
2608 /* Alternative loses if it requires a type of reload not
2609 permitted for this insn. We can always reload
2610 objects with a REG_UNUSED note. */
2611 if ((curr_static_id->operand[nop].type != OP_IN
2612 && no_output_reloads_p
2613 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2614 || (curr_static_id->operand[nop].type != OP_OUT
2615 && no_input_reloads_p && ! const_to_mem)
2616 || (this_alternative_matches >= 0
2617 && (no_input_reloads_p
2618 || (no_output_reloads_p
2619 && (curr_static_id->operand
2620 [this_alternative_matches].type != OP_IN)
2621 && ! find_reg_note (curr_insn, REG_UNUSED,
2622 no_subreg_reg_operand
2623 [this_alternative_matches])))))
2625 if (lra_dump_file != NULL)
2626 fprintf
2627 (lra_dump_file,
2628 " alt=%d: No input/otput reload -- refuse\n",
2629 nalt);
2630 goto fail;
2633 /* Alternative loses if it required class pseudo can not
2634 hold value of required mode. Such insns can be
2635 described by insn definitions with mode iterators. */
2636 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2637 && ! hard_reg_set_empty_p (this_alternative_set)
2638 /* It is common practice for constraints to use a
2639 class which does not have actually enough regs to
2640 hold the value (e.g. x86 AREG for mode requiring
2641 more one general reg). Therefore we have 2
2642 conditions to check that the reload pseudo can
2643 not hold the mode value. */
2644 && (!targetm.hard_regno_mode_ok
2645 (ira_class_hard_regs[this_alternative][0],
2646 GET_MODE (*curr_id->operand_loc[nop])))
2647 /* The above condition is not enough as the first
2648 reg in ira_class_hard_regs can be not aligned for
2649 multi-words mode values. */
2650 && (prohibited_class_reg_set_mode_p
2651 (this_alternative, this_alternative_set,
2652 GET_MODE (*curr_id->operand_loc[nop]))))
2654 if (lra_dump_file != NULL)
2655 fprintf (lra_dump_file,
2656 " alt=%d: reload pseudo for op %d "
2657 " can not hold the mode value -- refuse\n",
2658 nalt, nop);
2659 goto fail;
2662 /* Check strong discouragement of reload of non-constant
2663 into class THIS_ALTERNATIVE. */
2664 if (! CONSTANT_P (op) && ! no_regs_p
2665 && (targetm.preferred_reload_class
2666 (op, this_alternative) == NO_REGS
2667 || (curr_static_id->operand[nop].type == OP_OUT
2668 && (targetm.preferred_output_reload_class
2669 (op, this_alternative) == NO_REGS))))
2671 if (lra_dump_file != NULL)
2672 fprintf (lra_dump_file,
2673 " %d Non-prefered reload: reject+=%d\n",
2674 nop, LRA_MAX_REJECT);
2675 reject += LRA_MAX_REJECT;
2678 if (! (MEM_P (op) && offmemok)
2679 && ! (const_to_mem && constmemok))
2681 /* We prefer to reload pseudos over reloading other
2682 things, since such reloads may be able to be
2683 eliminated later. So bump REJECT in other cases.
2684 Don't do this in the case where we are forcing a
2685 constant into memory and it will then win since
2686 we don't want to have a different alternative
2687 match then. */
2688 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2690 if (lra_dump_file != NULL)
2691 fprintf
2692 (lra_dump_file,
2693 " %d Non-pseudo reload: reject+=2\n",
2694 nop);
2695 reject += 2;
2698 if (! no_regs_p)
2699 reload_nregs
2700 += ira_reg_class_max_nregs[this_alternative][mode];
2702 if (SMALL_REGISTER_CLASS_P (this_alternative))
2704 if (lra_dump_file != NULL)
2705 fprintf
2706 (lra_dump_file,
2707 " %d Small class reload: reject+=%d\n",
2708 nop, LRA_LOSER_COST_FACTOR / 2);
2709 reject += LRA_LOSER_COST_FACTOR / 2;
2713 /* We are trying to spill pseudo into memory. It is
2714 usually more costly than moving to a hard register
2715 although it might takes the same number of
2716 reloads.
2718 Non-pseudo spill may happen also. Suppose a target allows both
2719 register and memory in the operand constraint alternatives,
2720 then it's typical that an eliminable register has a substition
2721 of "base + offset" which can either be reloaded by a simple
2722 "new_reg <= base + offset" which will match the register
2723 constraint, or a similar reg addition followed by further spill
2724 to and reload from memory which will match the memory
2725 constraint, but this memory spill will be much more costly
2726 usually.
2728 Code below increases the reject for both pseudo and non-pseudo
2729 spill. */
2730 if (no_regs_p
2731 && !(MEM_P (op) && offmemok)
2732 && !(REG_P (op) && hard_regno[nop] < 0))
2734 if (lra_dump_file != NULL)
2735 fprintf
2736 (lra_dump_file,
2737 " %d Spill %spseudo into memory: reject+=3\n",
2738 nop, REG_P (op) ? "" : "Non-");
2739 reject += 3;
2740 if (VECTOR_MODE_P (mode))
2742 /* Spilling vectors into memory is usually more
2743 costly as they contain big values. */
2744 if (lra_dump_file != NULL)
2745 fprintf
2746 (lra_dump_file,
2747 " %d Spill vector pseudo: reject+=2\n",
2748 nop);
2749 reject += 2;
2753 /* When we use an operand requiring memory in given
2754 alternative, the insn should write *and* read the
2755 value to/from memory it is costly in comparison with
2756 an insn alternative which does not use memory
2757 (e.g. register or immediate operand). We exclude
2758 memory operand for such case as we can satisfy the
2759 memory constraints by reloading address. */
2760 if (no_regs_p && offmemok && !MEM_P (op))
2762 if (lra_dump_file != NULL)
2763 fprintf
2764 (lra_dump_file,
2765 " Using memory insn operand %d: reject+=3\n",
2766 nop);
2767 reject += 3;
2770 /* If reload requires moving value through secondary
2771 memory, it will need one more insn at least. */
2772 if (this_alternative != NO_REGS
2773 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2774 && ((curr_static_id->operand[nop].type != OP_OUT
2775 && targetm.secondary_memory_needed (GET_MODE (op), cl,
2776 this_alternative))
2777 || (curr_static_id->operand[nop].type != OP_IN
2778 && (targetm.secondary_memory_needed
2779 (GET_MODE (op), this_alternative, cl)))))
2780 losers++;
2782 /* Input reloads can be inherited more often than output
2783 reloads can be removed, so penalize output
2784 reloads. */
2785 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2787 if (lra_dump_file != NULL)
2788 fprintf
2789 (lra_dump_file,
2790 " %d Non input pseudo reload: reject++\n",
2791 nop);
2792 reject++;
2795 if (MEM_P (op) && offmemok)
2796 addr_losers++;
2797 else if (curr_static_id->operand[nop].type == OP_INOUT)
2799 if (lra_dump_file != NULL)
2800 fprintf
2801 (lra_dump_file,
2802 " %d Input/Output reload: reject+=%d\n",
2803 nop, LRA_LOSER_COST_FACTOR);
2804 reject += LRA_LOSER_COST_FACTOR;
2808 if (early_clobber_p && ! scratch_p)
2810 if (lra_dump_file != NULL)
2811 fprintf (lra_dump_file,
2812 " %d Early clobber: reject++\n", nop);
2813 reject++;
2815 /* ??? We check early clobbers after processing all operands
2816 (see loop below) and there we update the costs more.
2817 Should we update the cost (may be approximately) here
2818 because of early clobber register reloads or it is a rare
2819 or non-important thing to be worth to do it. */
2820 overall = (losers * LRA_LOSER_COST_FACTOR + reject
2821 - (addr_losers == losers ? static_reject : 0));
2822 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2824 if (lra_dump_file != NULL)
2825 fprintf (lra_dump_file,
2826 " alt=%d,overall=%d,losers=%d -- refuse\n",
2827 nalt, overall, losers);
2828 goto fail;
2831 if (update_and_check_small_class_inputs (nop, this_alternative))
2833 if (lra_dump_file != NULL)
2834 fprintf (lra_dump_file,
2835 " alt=%d, not enough small class regs -- refuse\n",
2836 nalt);
2837 goto fail;
2839 curr_alt[nop] = this_alternative;
2840 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2841 curr_alt_win[nop] = this_alternative_win;
2842 curr_alt_match_win[nop] = this_alternative_match_win;
2843 curr_alt_offmemok[nop] = this_alternative_offmemok;
2844 curr_alt_matches[nop] = this_alternative_matches;
2846 if (this_alternative_matches >= 0
2847 && !did_match && !this_alternative_win)
2848 curr_alt_win[this_alternative_matches] = false;
2850 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2851 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2854 if (curr_insn_set != NULL_RTX && n_operands == 2
2855 /* Prevent processing non-move insns. */
2856 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2857 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2858 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2859 && REG_P (no_subreg_reg_operand[0])
2860 && REG_P (no_subreg_reg_operand[1])
2861 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2862 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2863 || (! curr_alt_win[0] && curr_alt_win[1]
2864 && REG_P (no_subreg_reg_operand[1])
2865 /* Check that we reload memory not the memory
2866 address. */
2867 && ! (curr_alt_offmemok[0]
2868 && MEM_P (no_subreg_reg_operand[0]))
2869 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2870 || (curr_alt_win[0] && ! curr_alt_win[1]
2871 && REG_P (no_subreg_reg_operand[0])
2872 /* Check that we reload memory not the memory
2873 address. */
2874 && ! (curr_alt_offmemok[1]
2875 && MEM_P (no_subreg_reg_operand[1]))
2876 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2877 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2878 no_subreg_reg_operand[1])
2879 || (targetm.preferred_reload_class
2880 (no_subreg_reg_operand[1],
2881 (enum reg_class) curr_alt[1]) != NO_REGS))
2882 /* If it is a result of recent elimination in move
2883 insn we can transform it into an add still by
2884 using this alternative. */
2885 && GET_CODE (no_subreg_reg_operand[1]) != PLUS
2886 /* Likewise if the source has been replaced with an
2887 equivalent value. This only happens once -- the reload
2888 will use the equivalent value instead of the register it
2889 replaces -- so there should be no danger of cycling. */
2890 && !equiv_substition_p[1])))
2892 /* We have a move insn and a new reload insn will be similar
2893 to the current insn. We should avoid such situation as
2894 it results in LRA cycling. */
2895 if (lra_dump_file != NULL)
2896 fprintf (lra_dump_file,
2897 " Cycle danger: overall += LRA_MAX_REJECT\n");
2898 overall += LRA_MAX_REJECT;
2900 ok_p = true;
2901 curr_alt_dont_inherit_ops_num = 0;
2902 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2904 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2905 HARD_REG_SET temp_set;
2907 i = early_clobbered_nops[nop];
2908 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2909 || hard_regno[i] < 0)
2910 continue;
2911 lra_assert (operand_reg[i] != NULL_RTX);
2912 clobbered_hard_regno = hard_regno[i];
2913 CLEAR_HARD_REG_SET (temp_set);
2914 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2915 first_conflict_j = last_conflict_j = -1;
2916 for (j = 0; j < n_operands; j++)
2917 if (j == i
2918 /* We don't want process insides of match_operator and
2919 match_parallel because otherwise we would process
2920 their operands once again generating a wrong
2921 code. */
2922 || curr_static_id->operand[j].is_operator)
2923 continue;
2924 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2925 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2926 continue;
2927 /* If we don't reload j-th operand, check conflicts. */
2928 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2929 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2931 if (first_conflict_j < 0)
2932 first_conflict_j = j;
2933 last_conflict_j = j;
2935 if (last_conflict_j < 0)
2936 continue;
2937 /* If earlyclobber operand conflicts with another
2938 non-matching operand which is actually the same register
2939 as the earlyclobber operand, it is better to reload the
2940 another operand as an operand matching the earlyclobber
2941 operand can be also the same. */
2942 if (first_conflict_j == last_conflict_j
2943 && operand_reg[last_conflict_j] != NULL_RTX
2944 && ! curr_alt_match_win[last_conflict_j]
2945 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2947 curr_alt_win[last_conflict_j] = false;
2948 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2949 = last_conflict_j;
2950 losers++;
2951 /* Early clobber was already reflected in REJECT. */
2952 lra_assert (reject > 0);
2953 if (lra_dump_file != NULL)
2954 fprintf
2955 (lra_dump_file,
2956 " %d Conflict early clobber reload: reject--\n",
2958 reject--;
2959 overall += LRA_LOSER_COST_FACTOR - 1;
2961 else
2963 /* We need to reload early clobbered register and the
2964 matched registers. */
2965 for (j = 0; j < n_operands; j++)
2966 if (curr_alt_matches[j] == i)
2968 curr_alt_match_win[j] = false;
2969 losers++;
2970 overall += LRA_LOSER_COST_FACTOR;
2972 if (! curr_alt_match_win[i])
2973 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2974 else
2976 /* Remember pseudos used for match reloads are never
2977 inherited. */
2978 lra_assert (curr_alt_matches[i] >= 0);
2979 curr_alt_win[curr_alt_matches[i]] = false;
2981 curr_alt_win[i] = curr_alt_match_win[i] = false;
2982 losers++;
2983 /* Early clobber was already reflected in REJECT. */
2984 lra_assert (reject > 0);
2985 if (lra_dump_file != NULL)
2986 fprintf
2987 (lra_dump_file,
2988 " %d Matched conflict early clobber reloads: "
2989 "reject--\n",
2991 reject--;
2992 overall += LRA_LOSER_COST_FACTOR - 1;
2995 if (lra_dump_file != NULL)
2996 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2997 nalt, overall, losers, reload_nregs);
2999 /* If this alternative can be made to work by reloading, and it
3000 needs less reloading than the others checked so far, record
3001 it as the chosen goal for reloading. */
3002 if ((best_losers != 0 && losers == 0)
3003 || (((best_losers == 0 && losers == 0)
3004 || (best_losers != 0 && losers != 0))
3005 && (best_overall > overall
3006 || (best_overall == overall
3007 /* If the cost of the reloads is the same,
3008 prefer alternative which requires minimal
3009 number of reload regs. */
3010 && (reload_nregs < best_reload_nregs
3011 || (reload_nregs == best_reload_nregs
3012 && (best_reload_sum < reload_sum
3013 || (best_reload_sum == reload_sum
3014 && nalt < goal_alt_number))))))))
3016 for (nop = 0; nop < n_operands; nop++)
3018 goal_alt_win[nop] = curr_alt_win[nop];
3019 goal_alt_match_win[nop] = curr_alt_match_win[nop];
3020 goal_alt_matches[nop] = curr_alt_matches[nop];
3021 goal_alt[nop] = curr_alt[nop];
3022 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3024 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3025 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3026 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3027 goal_alt_swapped = curr_swapped;
3028 best_overall = overall;
3029 best_losers = losers;
3030 best_reload_nregs = reload_nregs;
3031 best_reload_sum = reload_sum;
3032 goal_alt_number = nalt;
3034 if (losers == 0)
3035 /* Everything is satisfied. Do not process alternatives
3036 anymore. */
3037 break;
3038 fail:
3041 return ok_p;
3044 /* Make reload base reg from address AD. */
3045 static rtx
3046 base_to_reg (struct address_info *ad)
3048 enum reg_class cl;
3049 int code = -1;
3050 rtx new_inner = NULL_RTX;
3051 rtx new_reg = NULL_RTX;
3052 rtx_insn *insn;
3053 rtx_insn *last_insn = get_last_insn();
3055 lra_assert (ad->disp == ad->disp_term);
3056 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3057 get_index_code (ad));
3058 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3059 cl, "base");
3060 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3061 ad->disp_term == NULL
3062 ? const0_rtx
3063 : *ad->disp_term);
3064 if (!valid_address_p (ad->mode, new_inner, ad->as))
3065 return NULL_RTX;
3066 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3067 code = recog_memoized (insn);
3068 if (code < 0)
3070 delete_insns_since (last_insn);
3071 return NULL_RTX;
3074 return new_inner;
3077 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3078 static rtx
3079 base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3081 enum reg_class cl;
3082 rtx new_reg;
3084 lra_assert (ad->base == ad->base_term);
3085 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3086 get_index_code (ad));
3087 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3088 cl, "base + disp");
3089 lra_emit_add (new_reg, *ad->base_term, disp);
3090 return new_reg;
3093 /* Make reload of index part of address AD. Return the new
3094 pseudo. */
3095 static rtx
3096 index_part_to_reg (struct address_info *ad)
3098 rtx new_reg;
3100 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3101 INDEX_REG_CLASS, "index term");
3102 expand_mult (GET_MODE (*ad->index), *ad->index_term,
3103 GEN_INT (get_index_scale (ad)), new_reg, 1);
3104 return new_reg;
3107 /* Return true if we can add a displacement to address AD, even if that
3108 makes the address invalid. The fix-up code requires any new address
3109 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3110 static bool
3111 can_add_disp_p (struct address_info *ad)
3113 return (!ad->autoinc_p
3114 && ad->segment == NULL
3115 && ad->base == ad->base_term
3116 && ad->disp == ad->disp_term);
3119 /* Make equiv substitution in address AD. Return true if a substitution
3120 was made. */
3121 static bool
3122 equiv_address_substitution (struct address_info *ad)
3124 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3125 poly_int64 disp;
3126 HOST_WIDE_INT scale;
3127 bool change_p;
3129 base_term = strip_subreg (ad->base_term);
3130 if (base_term == NULL)
3131 base_reg = new_base_reg = NULL_RTX;
3132 else
3134 base_reg = *base_term;
3135 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3137 index_term = strip_subreg (ad->index_term);
3138 if (index_term == NULL)
3139 index_reg = new_index_reg = NULL_RTX;
3140 else
3142 index_reg = *index_term;
3143 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3145 if (base_reg == new_base_reg && index_reg == new_index_reg)
3146 return false;
3147 disp = 0;
3148 change_p = false;
3149 if (lra_dump_file != NULL)
3151 fprintf (lra_dump_file, "Changing address in insn %d ",
3152 INSN_UID (curr_insn));
3153 dump_value_slim (lra_dump_file, *ad->outer, 1);
3155 if (base_reg != new_base_reg)
3157 poly_int64 offset;
3158 if (REG_P (new_base_reg))
3160 *base_term = new_base_reg;
3161 change_p = true;
3163 else if (GET_CODE (new_base_reg) == PLUS
3164 && REG_P (XEXP (new_base_reg, 0))
3165 && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3166 && can_add_disp_p (ad))
3168 disp += offset;
3169 *base_term = XEXP (new_base_reg, 0);
3170 change_p = true;
3172 if (ad->base_term2 != NULL)
3173 *ad->base_term2 = *ad->base_term;
3175 if (index_reg != new_index_reg)
3177 poly_int64 offset;
3178 if (REG_P (new_index_reg))
3180 *index_term = new_index_reg;
3181 change_p = true;
3183 else if (GET_CODE (new_index_reg) == PLUS
3184 && REG_P (XEXP (new_index_reg, 0))
3185 && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3186 && can_add_disp_p (ad)
3187 && (scale = get_index_scale (ad)))
3189 disp += offset * scale;
3190 *index_term = XEXP (new_index_reg, 0);
3191 change_p = true;
3194 if (maybe_ne (disp, 0))
3196 if (ad->disp != NULL)
3197 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3198 else
3200 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3201 update_address (ad);
3203 change_p = true;
3205 if (lra_dump_file != NULL)
3207 if (! change_p)
3208 fprintf (lra_dump_file, " -- no change\n");
3209 else
3211 fprintf (lra_dump_file, " on equiv ");
3212 dump_value_slim (lra_dump_file, *ad->outer, 1);
3213 fprintf (lra_dump_file, "\n");
3216 return change_p;
3219 /* Major function to make reloads for an address in operand NOP or
3220 check its correctness (If CHECK_ONLY_P is true). The supported
3221 cases are:
3223 1) an address that existed before LRA started, at which point it
3224 must have been valid. These addresses are subject to elimination
3225 and may have become invalid due to the elimination offset being out
3226 of range.
3228 2) an address created by forcing a constant to memory
3229 (force_const_to_mem). The initial form of these addresses might
3230 not be valid, and it is this function's job to make them valid.
3232 3) a frame address formed from a register and a (possibly zero)
3233 constant offset. As above, these addresses might not be valid and
3234 this function must make them so.
3236 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3237 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3238 address. Return true for any RTL change.
3240 The function is a helper function which does not produce all
3241 transformations (when CHECK_ONLY_P is false) which can be
3242 necessary. It does just basic steps. To do all necessary
3243 transformations use function process_address. */
3244 static bool
3245 process_address_1 (int nop, bool check_only_p,
3246 rtx_insn **before, rtx_insn **after)
3248 struct address_info ad;
3249 rtx new_reg;
3250 HOST_WIDE_INT scale;
3251 rtx op = *curr_id->operand_loc[nop];
3252 const char *constraint = curr_static_id->operand[nop].constraint;
3253 enum constraint_num cn = lookup_constraint (constraint);
3254 bool change_p = false;
3256 if (MEM_P (op)
3257 && GET_MODE (op) == BLKmode
3258 && GET_CODE (XEXP (op, 0)) == SCRATCH)
3259 return false;
3261 if (insn_extra_address_constraint (cn)
3262 /* When we find an asm operand with an address constraint that
3263 doesn't satisfy address_operand to begin with, we clear
3264 is_address, so that we don't try to make a non-address fit.
3265 If the asm statement got this far, it's because other
3266 constraints are available, and we'll use them, disregarding
3267 the unsatisfiable address ones. */
3268 && curr_static_id->operand[nop].is_address)
3269 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3270 /* Do not attempt to decompose arbitrary addresses generated by combine
3271 for asm operands with loose constraints, e.g 'X'. */
3272 else if (MEM_P (op)
3273 && !(INSN_CODE (curr_insn) < 0
3274 && get_constraint_type (cn) == CT_FIXED_FORM
3275 && constraint_satisfied_p (op, cn)))
3276 decompose_mem_address (&ad, op);
3277 else if (GET_CODE (op) == SUBREG
3278 && MEM_P (SUBREG_REG (op)))
3279 decompose_mem_address (&ad, SUBREG_REG (op));
3280 else
3281 return false;
3282 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3283 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3284 when INDEX_REG_CLASS is a single register class. */
3285 if (ad.base_term != NULL
3286 && ad.index_term != NULL
3287 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3288 && REG_P (*ad.base_term)
3289 && REG_P (*ad.index_term)
3290 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3291 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3293 std::swap (ad.base, ad.index);
3294 std::swap (ad.base_term, ad.index_term);
3296 if (! check_only_p)
3297 change_p = equiv_address_substitution (&ad);
3298 if (ad.base_term != NULL
3299 && (process_addr_reg
3300 (ad.base_term, check_only_p, before,
3301 (ad.autoinc_p
3302 && !(REG_P (*ad.base_term)
3303 && find_regno_note (curr_insn, REG_DEAD,
3304 REGNO (*ad.base_term)) != NULL_RTX)
3305 ? after : NULL),
3306 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3307 get_index_code (&ad)))))
3309 change_p = true;
3310 if (ad.base_term2 != NULL)
3311 *ad.base_term2 = *ad.base_term;
3313 if (ad.index_term != NULL
3314 && process_addr_reg (ad.index_term, check_only_p,
3315 before, NULL, INDEX_REG_CLASS))
3316 change_p = true;
3318 /* Target hooks sometimes don't treat extra-constraint addresses as
3319 legitimate address_operands, so handle them specially. */
3320 if (insn_extra_address_constraint (cn)
3321 && satisfies_address_constraint_p (&ad, cn))
3322 return change_p;
3324 if (check_only_p)
3325 return change_p;
3327 /* There are three cases where the shape of *AD.INNER may now be invalid:
3329 1) the original address was valid, but either elimination or
3330 equiv_address_substitution was applied and that made
3331 the address invalid.
3333 2) the address is an invalid symbolic address created by
3334 force_const_to_mem.
3336 3) the address is a frame address with an invalid offset.
3338 4) the address is a frame address with an invalid base.
3340 All these cases involve a non-autoinc address, so there is no
3341 point revalidating other types. */
3342 if (ad.autoinc_p || valid_address_p (&ad))
3343 return change_p;
3345 /* Any index existed before LRA started, so we can assume that the
3346 presence and shape of the index is valid. */
3347 push_to_sequence (*before);
3348 lra_assert (ad.disp == ad.disp_term);
3349 if (ad.base == NULL)
3351 if (ad.index == NULL)
3353 rtx_insn *insn;
3354 rtx_insn *last = get_last_insn ();
3355 int code = -1;
3356 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3357 SCRATCH, SCRATCH);
3358 rtx addr = *ad.inner;
3360 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3361 if (HAVE_lo_sum)
3363 /* addr => lo_sum (new_base, addr), case (2) above. */
3364 insn = emit_insn (gen_rtx_SET
3365 (new_reg,
3366 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3367 code = recog_memoized (insn);
3368 if (code >= 0)
3370 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3371 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3373 /* Try to put lo_sum into register. */
3374 insn = emit_insn (gen_rtx_SET
3375 (new_reg,
3376 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3377 code = recog_memoized (insn);
3378 if (code >= 0)
3380 *ad.inner = new_reg;
3381 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3383 *ad.inner = addr;
3384 code = -1;
3390 if (code < 0)
3391 delete_insns_since (last);
3394 if (code < 0)
3396 /* addr => new_base, case (2) above. */
3397 lra_emit_move (new_reg, addr);
3399 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3400 insn != NULL_RTX;
3401 insn = NEXT_INSN (insn))
3402 if (recog_memoized (insn) < 0)
3403 break;
3404 if (insn != NULL_RTX)
3406 /* Do nothing if we cannot generate right insns.
3407 This is analogous to reload pass behavior. */
3408 delete_insns_since (last);
3409 end_sequence ();
3410 return false;
3412 *ad.inner = new_reg;
3415 else
3417 /* index * scale + disp => new base + index * scale,
3418 case (1) above. */
3419 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3420 GET_CODE (*ad.index));
3422 lra_assert (INDEX_REG_CLASS != NO_REGS);
3423 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3424 lra_emit_move (new_reg, *ad.disp);
3425 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3426 new_reg, *ad.index);
3429 else if (ad.index == NULL)
3431 int regno;
3432 enum reg_class cl;
3433 rtx set;
3434 rtx_insn *insns, *last_insn;
3435 /* Try to reload base into register only if the base is invalid
3436 for the address but with valid offset, case (4) above. */
3437 start_sequence ();
3438 new_reg = base_to_reg (&ad);
3440 /* base + disp => new base, cases (1) and (3) above. */
3441 /* Another option would be to reload the displacement into an
3442 index register. However, postreload has code to optimize
3443 address reloads that have the same base and different
3444 displacements, so reloading into an index register would
3445 not necessarily be a win. */
3446 if (new_reg == NULL_RTX)
3448 /* See if the target can split the displacement into a
3449 legitimate new displacement from a local anchor. */
3450 gcc_assert (ad.disp == ad.disp_term);
3451 poly_int64 orig_offset;
3452 rtx offset1, offset2;
3453 if (poly_int_rtx_p (*ad.disp, &orig_offset)
3454 && targetm.legitimize_address_displacement (&offset1, &offset2,
3455 orig_offset,
3456 ad.mode))
3458 new_reg = base_plus_disp_to_reg (&ad, offset1);
3459 new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2);
3461 else
3462 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3464 insns = get_insns ();
3465 last_insn = get_last_insn ();
3466 /* If we generated at least two insns, try last insn source as
3467 an address. If we succeed, we generate one less insn. */
3468 if (REG_P (new_reg)
3469 && last_insn != insns
3470 && (set = single_set (last_insn)) != NULL_RTX
3471 && GET_CODE (SET_SRC (set)) == PLUS
3472 && REG_P (XEXP (SET_SRC (set), 0))
3473 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3475 *ad.inner = SET_SRC (set);
3476 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3478 *ad.base_term = XEXP (SET_SRC (set), 0);
3479 *ad.disp_term = XEXP (SET_SRC (set), 1);
3480 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3481 get_index_code (&ad));
3482 regno = REGNO (*ad.base_term);
3483 if (regno >= FIRST_PSEUDO_REGISTER
3484 && cl != lra_get_allocno_class (regno))
3485 lra_change_class (regno, cl, " Change to", true);
3486 new_reg = SET_SRC (set);
3487 delete_insns_since (PREV_INSN (last_insn));
3490 end_sequence ();
3491 emit_insn (insns);
3492 *ad.inner = new_reg;
3494 else if (ad.disp_term != NULL)
3496 /* base + scale * index + disp => new base + scale * index,
3497 case (1) above. */
3498 gcc_assert (ad.disp == ad.disp_term);
3499 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3500 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3501 new_reg, *ad.index);
3503 else if ((scale = get_index_scale (&ad)) == 1)
3505 /* The last transformation to one reg will be made in
3506 curr_insn_transform function. */
3507 end_sequence ();
3508 return false;
3510 else if (scale != 0)
3512 /* base + scale * index => base + new_reg,
3513 case (1) above.
3514 Index part of address may become invalid. For example, we
3515 changed pseudo on the equivalent memory and a subreg of the
3516 pseudo onto the memory of different mode for which the scale is
3517 prohibitted. */
3518 new_reg = index_part_to_reg (&ad);
3519 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3520 *ad.base_term, new_reg);
3522 else
3524 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3525 SCRATCH, SCRATCH);
3526 rtx addr = *ad.inner;
3528 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3529 /* addr => new_base. */
3530 lra_emit_move (new_reg, addr);
3531 *ad.inner = new_reg;
3533 *before = get_insns ();
3534 end_sequence ();
3535 return true;
3538 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3539 Use process_address_1 as a helper function. Return true for any
3540 RTL changes.
3542 If CHECK_ONLY_P is true, just check address correctness. Return
3543 false if the address correct. */
3544 static bool
3545 process_address (int nop, bool check_only_p,
3546 rtx_insn **before, rtx_insn **after)
3548 bool res = false;
3550 while (process_address_1 (nop, check_only_p, before, after))
3552 if (check_only_p)
3553 return true;
3554 res = true;
3556 return res;
3559 /* Emit insns to reload VALUE into a new register. VALUE is an
3560 auto-increment or auto-decrement RTX whose operand is a register or
3561 memory location; so reloading involves incrementing that location.
3562 IN is either identical to VALUE, or some cheaper place to reload
3563 value being incremented/decremented from.
3565 INC_AMOUNT is the number to increment or decrement by (always
3566 positive and ignored for POST_MODIFY/PRE_MODIFY).
3568 Return pseudo containing the result. */
3569 static rtx
3570 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3572 /* REG or MEM to be copied and incremented. */
3573 rtx incloc = XEXP (value, 0);
3574 /* Nonzero if increment after copying. */
3575 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3576 || GET_CODE (value) == POST_MODIFY);
3577 rtx_insn *last;
3578 rtx inc;
3579 rtx_insn *add_insn;
3580 int code;
3581 rtx real_in = in == value ? incloc : in;
3582 rtx result;
3583 bool plus_p = true;
3585 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3587 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3588 || GET_CODE (XEXP (value, 1)) == MINUS);
3589 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3590 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3591 inc = XEXP (XEXP (value, 1), 1);
3593 else
3595 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3596 inc_amount = -inc_amount;
3598 inc = gen_int_mode (inc_amount, GET_MODE (value));
3601 if (! post && REG_P (incloc))
3602 result = incloc;
3603 else
3604 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3605 "INC/DEC result");
3607 if (real_in != result)
3609 /* First copy the location to the result register. */
3610 lra_assert (REG_P (result));
3611 emit_insn (gen_move_insn (result, real_in));
3614 /* We suppose that there are insns to add/sub with the constant
3615 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3616 old reload worked with this assumption. If the assumption
3617 becomes wrong, we should use approach in function
3618 base_plus_disp_to_reg. */
3619 if (in == value)
3621 /* See if we can directly increment INCLOC. */
3622 last = get_last_insn ();
3623 add_insn = emit_insn (plus_p
3624 ? gen_add2_insn (incloc, inc)
3625 : gen_sub2_insn (incloc, inc));
3627 code = recog_memoized (add_insn);
3628 if (code >= 0)
3630 if (! post && result != incloc)
3631 emit_insn (gen_move_insn (result, incloc));
3632 return result;
3634 delete_insns_since (last);
3637 /* If couldn't do the increment directly, must increment in RESULT.
3638 The way we do this depends on whether this is pre- or
3639 post-increment. For pre-increment, copy INCLOC to the reload
3640 register, increment it there, then save back. */
3641 if (! post)
3643 if (real_in != result)
3644 emit_insn (gen_move_insn (result, real_in));
3645 if (plus_p)
3646 emit_insn (gen_add2_insn (result, inc));
3647 else
3648 emit_insn (gen_sub2_insn (result, inc));
3649 if (result != incloc)
3650 emit_insn (gen_move_insn (incloc, result));
3652 else
3654 /* Post-increment.
3656 Because this might be a jump insn or a compare, and because
3657 RESULT may not be available after the insn in an input
3658 reload, we must do the incrementing before the insn being
3659 reloaded for.
3661 We have already copied IN to RESULT. Increment the copy in
3662 RESULT, save that back, then decrement RESULT so it has
3663 the original value. */
3664 if (plus_p)
3665 emit_insn (gen_add2_insn (result, inc));
3666 else
3667 emit_insn (gen_sub2_insn (result, inc));
3668 emit_insn (gen_move_insn (incloc, result));
3669 /* Restore non-modified value for the result. We prefer this
3670 way because it does not require an additional hard
3671 register. */
3672 if (plus_p)
3674 poly_int64 offset;
3675 if (poly_int_rtx_p (inc, &offset))
3676 emit_insn (gen_add2_insn (result,
3677 gen_int_mode (-offset,
3678 GET_MODE (result))));
3679 else
3680 emit_insn (gen_sub2_insn (result, inc));
3682 else
3683 emit_insn (gen_add2_insn (result, inc));
3685 return result;
3688 /* Return true if the current move insn does not need processing as we
3689 already know that it satisfies its constraints. */
3690 static bool
3691 simple_move_p (void)
3693 rtx dest, src;
3694 enum reg_class dclass, sclass;
3696 lra_assert (curr_insn_set != NULL_RTX);
3697 dest = SET_DEST (curr_insn_set);
3698 src = SET_SRC (curr_insn_set);
3700 /* If the instruction has multiple sets we need to process it even if it
3701 is single_set. This can happen if one or more of the SETs are dead.
3702 See PR73650. */
3703 if (multiple_sets (curr_insn))
3704 return false;
3706 return ((dclass = get_op_class (dest)) != NO_REGS
3707 && (sclass = get_op_class (src)) != NO_REGS
3708 /* The backend guarantees that register moves of cost 2
3709 never need reloads. */
3710 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3713 /* Swap operands NOP and NOP + 1. */
3714 static inline void
3715 swap_operands (int nop)
3717 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3718 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3719 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3720 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3721 /* Swap the duplicates too. */
3722 lra_update_dup (curr_id, nop);
3723 lra_update_dup (curr_id, nop + 1);
3726 /* Main entry point of the constraint code: search the body of the
3727 current insn to choose the best alternative. It is mimicking insn
3728 alternative cost calculation model of former reload pass. That is
3729 because machine descriptions were written to use this model. This
3730 model can be changed in future. Make commutative operand exchange
3731 if it is chosen.
3733 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3734 constraints. Return true if any change happened during function
3735 call.
3737 If CHECK_ONLY_P is true then don't do any transformation. Just
3738 check that the insn satisfies all constraints. If the insn does
3739 not satisfy any constraint, return true. */
3740 static bool
3741 curr_insn_transform (bool check_only_p)
3743 int i, j, k;
3744 int n_operands;
3745 int n_alternatives;
3746 int n_outputs;
3747 int commutative;
3748 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3749 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3750 signed char outputs[MAX_RECOG_OPERANDS + 1];
3751 rtx_insn *before, *after;
3752 bool alt_p = false;
3753 /* Flag that the insn has been changed through a transformation. */
3754 bool change_p;
3755 bool sec_mem_p;
3756 bool use_sec_mem_p;
3757 int max_regno_before;
3758 int reused_alternative_num;
3760 curr_insn_set = single_set (curr_insn);
3761 if (curr_insn_set != NULL_RTX && simple_move_p ())
3763 /* We assume that the corresponding insn alternative has no
3764 earlier clobbers. If it is not the case, don't define move
3765 cost equal to 2 for the corresponding register classes. */
3766 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT);
3767 return false;
3770 no_input_reloads_p = no_output_reloads_p = false;
3771 goal_alt_number = -1;
3772 change_p = sec_mem_p = false;
3773 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3774 reloads; neither are insns that SET cc0. Insns that use CC0 are
3775 not allowed to have any input reloads. */
3776 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3777 no_output_reloads_p = true;
3779 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3780 no_input_reloads_p = true;
3781 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3782 no_output_reloads_p = true;
3784 n_operands = curr_static_id->n_operands;
3785 n_alternatives = curr_static_id->n_alternatives;
3787 /* Just return "no reloads" if insn has no operands with
3788 constraints. */
3789 if (n_operands == 0 || n_alternatives == 0)
3790 return false;
3792 max_regno_before = max_reg_num ();
3794 for (i = 0; i < n_operands; i++)
3796 goal_alt_matched[i][0] = -1;
3797 goal_alt_matches[i] = -1;
3800 commutative = curr_static_id->commutative;
3802 /* Now see what we need for pseudos that didn't get hard regs or got
3803 the wrong kind of hard reg. For this, we must consider all the
3804 operands together against the register constraints. */
3806 best_losers = best_overall = INT_MAX;
3807 best_reload_sum = 0;
3809 curr_swapped = false;
3810 goal_alt_swapped = false;
3812 if (! check_only_p)
3813 /* Make equivalence substitution and memory subreg elimination
3814 before address processing because an address legitimacy can
3815 depend on memory mode. */
3816 for (i = 0; i < n_operands; i++)
3818 rtx op, subst, old;
3819 bool op_change_p = false;
3821 if (curr_static_id->operand[i].is_operator)
3822 continue;
3824 old = op = *curr_id->operand_loc[i];
3825 if (GET_CODE (old) == SUBREG)
3826 old = SUBREG_REG (old);
3827 subst = get_equiv_with_elimination (old, curr_insn);
3828 original_subreg_reg_mode[i] = VOIDmode;
3829 equiv_substition_p[i] = false;
3830 if (subst != old)
3832 equiv_substition_p[i] = true;
3833 subst = copy_rtx (subst);
3834 lra_assert (REG_P (old));
3835 if (GET_CODE (op) != SUBREG)
3836 *curr_id->operand_loc[i] = subst;
3837 else
3839 SUBREG_REG (op) = subst;
3840 if (GET_MODE (subst) == VOIDmode)
3841 original_subreg_reg_mode[i] = GET_MODE (old);
3843 if (lra_dump_file != NULL)
3845 fprintf (lra_dump_file,
3846 "Changing pseudo %d in operand %i of insn %u on equiv ",
3847 REGNO (old), i, INSN_UID (curr_insn));
3848 dump_value_slim (lra_dump_file, subst, 1);
3849 fprintf (lra_dump_file, "\n");
3851 op_change_p = change_p = true;
3853 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3855 change_p = true;
3856 lra_update_dup (curr_id, i);
3860 /* Reload address registers and displacements. We do it before
3861 finding an alternative because of memory constraints. */
3862 before = after = NULL;
3863 for (i = 0; i < n_operands; i++)
3864 if (! curr_static_id->operand[i].is_operator
3865 && process_address (i, check_only_p, &before, &after))
3867 if (check_only_p)
3868 return true;
3869 change_p = true;
3870 lra_update_dup (curr_id, i);
3873 if (change_p)
3874 /* If we've changed the instruction then any alternative that
3875 we chose previously may no longer be valid. */
3876 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT);
3878 if (! check_only_p && curr_insn_set != NULL_RTX
3879 && check_and_process_move (&change_p, &sec_mem_p))
3880 return change_p;
3882 try_swapped:
3884 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative;
3885 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3886 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3887 reused_alternative_num, INSN_UID (curr_insn));
3889 if (process_alt_operands (reused_alternative_num))
3890 alt_p = true;
3892 if (check_only_p)
3893 return ! alt_p || best_losers != 0;
3895 /* If insn is commutative (it's safe to exchange a certain pair of
3896 operands) then we need to try each alternative twice, the second
3897 time matching those two operands as if we had exchanged them. To
3898 do this, really exchange them in operands.
3900 If we have just tried the alternatives the second time, return
3901 operands to normal and drop through. */
3903 if (reused_alternative_num < 0 && commutative >= 0)
3905 curr_swapped = !curr_swapped;
3906 if (curr_swapped)
3908 swap_operands (commutative);
3909 goto try_swapped;
3911 else
3912 swap_operands (commutative);
3915 if (! alt_p && ! sec_mem_p)
3917 /* No alternative works with reloads?? */
3918 if (INSN_CODE (curr_insn) >= 0)
3919 fatal_insn ("unable to generate reloads for:", curr_insn);
3920 error_for_asm (curr_insn,
3921 "inconsistent operand constraints in an %<asm%>");
3922 /* Avoid further trouble with this insn. Don't generate use
3923 pattern here as we could use the insn SP offset. */
3924 lra_set_insn_deleted (curr_insn);
3925 return true;
3928 /* If the best alternative is with operands 1 and 2 swapped, swap
3929 them. Update the operand numbers of any reloads already
3930 pushed. */
3932 if (goal_alt_swapped)
3934 if (lra_dump_file != NULL)
3935 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3936 INSN_UID (curr_insn));
3938 /* Swap the duplicates too. */
3939 swap_operands (commutative);
3940 change_p = true;
3943 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3944 too conservatively. So we use the secondary memory only if there
3945 is no any alternative without reloads. */
3946 use_sec_mem_p = false;
3947 if (! alt_p)
3948 use_sec_mem_p = true;
3949 else if (sec_mem_p)
3951 for (i = 0; i < n_operands; i++)
3952 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3953 break;
3954 use_sec_mem_p = i < n_operands;
3957 if (use_sec_mem_p)
3959 int in = -1, out = -1;
3960 rtx new_reg, src, dest, rld;
3961 machine_mode sec_mode, rld_mode;
3963 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3964 dest = SET_DEST (curr_insn_set);
3965 src = SET_SRC (curr_insn_set);
3966 for (i = 0; i < n_operands; i++)
3967 if (*curr_id->operand_loc[i] == dest)
3968 out = i;
3969 else if (*curr_id->operand_loc[i] == src)
3970 in = i;
3971 for (i = 0; i < curr_static_id->n_dups; i++)
3972 if (out < 0 && *curr_id->dup_loc[i] == dest)
3973 out = curr_static_id->dup_num[i];
3974 else if (in < 0 && *curr_id->dup_loc[i] == src)
3975 in = curr_static_id->dup_num[i];
3976 lra_assert (out >= 0 && in >= 0
3977 && curr_static_id->operand[out].type == OP_OUT
3978 && curr_static_id->operand[in].type == OP_IN);
3979 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
3980 rld_mode = GET_MODE (rld);
3981 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
3982 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3983 NO_REGS, "secondary");
3984 /* If the mode is changed, it should be wider. */
3985 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
3986 if (sec_mode != rld_mode)
3988 /* If the target says specifically to use another mode for
3989 secondary memory moves we can not reuse the original
3990 insn. */
3991 after = emit_spill_move (false, new_reg, dest);
3992 lra_process_new_insns (curr_insn, NULL, after,
3993 "Inserting the sec. move");
3994 /* We may have non null BEFORE here (e.g. after address
3995 processing. */
3996 push_to_sequence (before);
3997 before = emit_spill_move (true, new_reg, src);
3998 emit_insn (before);
3999 before = get_insns ();
4000 end_sequence ();
4001 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
4002 lra_set_insn_deleted (curr_insn);
4004 else if (dest == rld)
4006 *curr_id->operand_loc[out] = new_reg;
4007 lra_update_dup (curr_id, out);
4008 after = emit_spill_move (false, new_reg, dest);
4009 lra_process_new_insns (curr_insn, NULL, after,
4010 "Inserting the sec. move");
4012 else
4014 *curr_id->operand_loc[in] = new_reg;
4015 lra_update_dup (curr_id, in);
4016 /* See comments above. */
4017 push_to_sequence (before);
4018 before = emit_spill_move (true, new_reg, src);
4019 emit_insn (before);
4020 before = get_insns ();
4021 end_sequence ();
4022 lra_process_new_insns (curr_insn, before, NULL,
4023 "Inserting the sec. move");
4025 lra_update_insn_regno_info (curr_insn);
4026 return true;
4029 lra_assert (goal_alt_number >= 0);
4030 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4032 if (lra_dump_file != NULL)
4034 const char *p;
4036 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4037 goal_alt_number, INSN_UID (curr_insn));
4038 for (i = 0; i < n_operands; i++)
4040 p = (curr_static_id->operand_alternative
4041 [goal_alt_number * n_operands + i].constraint);
4042 if (*p == '\0')
4043 continue;
4044 fprintf (lra_dump_file, " (%d) ", i);
4045 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4046 fputc (*p, lra_dump_file);
4048 if (INSN_CODE (curr_insn) >= 0
4049 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4050 fprintf (lra_dump_file, " {%s}", p);
4051 if (maybe_ne (curr_id->sp_offset, 0))
4053 fprintf (lra_dump_file, " (sp_off=");
4054 print_dec (curr_id->sp_offset, lra_dump_file);
4055 fprintf (lra_dump_file, ")");
4057 fprintf (lra_dump_file, "\n");
4060 /* Right now, for any pair of operands I and J that are required to
4061 match, with J < I, goal_alt_matches[I] is J. Add I to
4062 goal_alt_matched[J]. */
4064 for (i = 0; i < n_operands; i++)
4065 if ((j = goal_alt_matches[i]) >= 0)
4067 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4069 /* We allow matching one output operand and several input
4070 operands. */
4071 lra_assert (k == 0
4072 || (curr_static_id->operand[j].type == OP_OUT
4073 && curr_static_id->operand[i].type == OP_IN
4074 && (curr_static_id->operand
4075 [goal_alt_matched[j][0]].type == OP_IN)));
4076 goal_alt_matched[j][k] = i;
4077 goal_alt_matched[j][k + 1] = -1;
4080 for (i = 0; i < n_operands; i++)
4081 goal_alt_win[i] |= goal_alt_match_win[i];
4083 /* Any constants that aren't allowed and can't be reloaded into
4084 registers are here changed into memory references. */
4085 for (i = 0; i < n_operands; i++)
4086 if (goal_alt_win[i])
4088 int regno;
4089 enum reg_class new_class;
4090 rtx reg = *curr_id->operand_loc[i];
4092 if (GET_CODE (reg) == SUBREG)
4093 reg = SUBREG_REG (reg);
4095 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4097 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4099 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4101 lra_assert (ok_p);
4102 lra_change_class (regno, new_class, " Change to", true);
4106 else
4108 const char *constraint;
4109 char c;
4110 rtx op = *curr_id->operand_loc[i];
4111 rtx subreg = NULL_RTX;
4112 machine_mode mode = curr_operand_mode[i];
4114 if (GET_CODE (op) == SUBREG)
4116 subreg = op;
4117 op = SUBREG_REG (op);
4118 mode = GET_MODE (op);
4121 if (CONST_POOL_OK_P (mode, op)
4122 && ((targetm.preferred_reload_class
4123 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4124 || no_input_reloads_p))
4126 rtx tem = force_const_mem (mode, op);
4128 change_p = true;
4129 if (subreg != NULL_RTX)
4130 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4132 *curr_id->operand_loc[i] = tem;
4133 lra_update_dup (curr_id, i);
4134 process_address (i, false, &before, &after);
4136 /* If the alternative accepts constant pool refs directly
4137 there will be no reload needed at all. */
4138 if (subreg != NULL_RTX)
4139 continue;
4140 /* Skip alternatives before the one requested. */
4141 constraint = (curr_static_id->operand_alternative
4142 [goal_alt_number * n_operands + i].constraint);
4143 for (;
4144 (c = *constraint) && c != ',' && c != '#';
4145 constraint += CONSTRAINT_LEN (c, constraint))
4147 enum constraint_num cn = lookup_constraint (constraint);
4148 if ((insn_extra_memory_constraint (cn)
4149 || insn_extra_special_memory_constraint (cn))
4150 && satisfies_memory_constraint_p (tem, cn))
4151 break;
4153 if (c == '\0' || c == ',' || c == '#')
4154 continue;
4156 goal_alt_win[i] = true;
4160 n_outputs = 0;
4161 outputs[0] = -1;
4162 for (i = 0; i < n_operands; i++)
4164 int regno;
4165 bool optional_p = false;
4166 rtx old, new_reg;
4167 rtx op = *curr_id->operand_loc[i];
4169 if (goal_alt_win[i])
4171 if (goal_alt[i] == NO_REGS
4172 && REG_P (op)
4173 /* When we assign NO_REGS it means that we will not
4174 assign a hard register to the scratch pseudo by
4175 assigment pass and the scratch pseudo will be
4176 spilled. Spilled scratch pseudos are transformed
4177 back to scratches at the LRA end. */
4178 && lra_former_scratch_operand_p (curr_insn, i)
4179 && lra_former_scratch_p (REGNO (op)))
4181 int regno = REGNO (op);
4182 lra_change_class (regno, NO_REGS, " Change to", true);
4183 if (lra_get_regno_hard_regno (regno) >= 0)
4184 /* We don't have to mark all insn affected by the
4185 spilled pseudo as there is only one such insn, the
4186 current one. */
4187 reg_renumber[regno] = -1;
4188 lra_assert (bitmap_single_bit_set_p
4189 (&lra_reg_info[REGNO (op)].insn_bitmap));
4191 /* We can do an optional reload. If the pseudo got a hard
4192 reg, we might improve the code through inheritance. If
4193 it does not get a hard register we coalesce memory/memory
4194 moves later. Ignore move insns to avoid cycling. */
4195 if (! lra_simple_p
4196 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4197 && goal_alt[i] != NO_REGS && REG_P (op)
4198 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4199 && regno < new_regno_start
4200 && ! lra_former_scratch_p (regno)
4201 && reg_renumber[regno] < 0
4202 /* Check that the optional reload pseudo will be able to
4203 hold given mode value. */
4204 && ! (prohibited_class_reg_set_mode_p
4205 (goal_alt[i], reg_class_contents[goal_alt[i]],
4206 PSEUDO_REGNO_MODE (regno)))
4207 && (curr_insn_set == NULL_RTX
4208 || !((REG_P (SET_SRC (curr_insn_set))
4209 || MEM_P (SET_SRC (curr_insn_set))
4210 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4211 && (REG_P (SET_DEST (curr_insn_set))
4212 || MEM_P (SET_DEST (curr_insn_set))
4213 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4214 optional_p = true;
4215 else
4216 continue;
4219 /* Operands that match previous ones have already been handled. */
4220 if (goal_alt_matches[i] >= 0)
4221 continue;
4223 /* We should not have an operand with a non-offsettable address
4224 appearing where an offsettable address will do. It also may
4225 be a case when the address should be special in other words
4226 not a general one (e.g. it needs no index reg). */
4227 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4229 enum reg_class rclass;
4230 rtx *loc = &XEXP (op, 0);
4231 enum rtx_code code = GET_CODE (*loc);
4233 push_to_sequence (before);
4234 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4235 MEM, SCRATCH);
4236 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4237 new_reg = emit_inc (rclass, *loc, *loc,
4238 /* This value does not matter for MODIFY. */
4239 GET_MODE_SIZE (GET_MODE (op)));
4240 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4241 "offsetable address", &new_reg))
4243 rtx addr = *loc;
4244 enum rtx_code code = GET_CODE (addr);
4246 if (code == AND && CONST_INT_P (XEXP (addr, 1)))
4247 /* (and ... (const_int -X)) is used to align to X bytes. */
4248 addr = XEXP (*loc, 0);
4249 lra_emit_move (new_reg, addr);
4250 if (addr != *loc)
4251 emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1)));
4253 before = get_insns ();
4254 end_sequence ();
4255 *loc = new_reg;
4256 lra_update_dup (curr_id, i);
4258 else if (goal_alt_matched[i][0] == -1)
4260 machine_mode mode;
4261 rtx reg, *loc;
4262 int hard_regno;
4263 enum op_type type = curr_static_id->operand[i].type;
4265 loc = curr_id->operand_loc[i];
4266 mode = curr_operand_mode[i];
4267 if (GET_CODE (*loc) == SUBREG)
4269 reg = SUBREG_REG (*loc);
4270 poly_int64 byte = SUBREG_BYTE (*loc);
4271 if (REG_P (reg)
4272 /* Strict_low_part requires reloading the register and not
4273 just the subreg. Likewise for a strict subreg no wider
4274 than a word for WORD_REGISTER_OPERATIONS targets. */
4275 && (curr_static_id->operand[i].strict_low
4276 || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4277 && (hard_regno
4278 = get_try_hard_regno (REGNO (reg))) >= 0
4279 && (simplify_subreg_regno
4280 (hard_regno,
4281 GET_MODE (reg), byte, mode) < 0)
4282 && (goal_alt[i] == NO_REGS
4283 || (simplify_subreg_regno
4284 (ira_class_hard_regs[goal_alt[i]][0],
4285 GET_MODE (reg), byte, mode) >= 0)))
4286 || (partial_subreg_p (mode, GET_MODE (reg))
4287 && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4288 UNITS_PER_WORD)
4289 && WORD_REGISTER_OPERATIONS)))
4291 /* An OP_INOUT is required when reloading a subreg of a
4292 mode wider than a word to ensure that data beyond the
4293 word being reloaded is preserved. Also automatically
4294 ensure that strict_low_part reloads are made into
4295 OP_INOUT which should already be true from the backend
4296 constraints. */
4297 if (type == OP_OUT
4298 && (curr_static_id->operand[i].strict_low
4299 || read_modify_subreg_p (*loc)))
4300 type = OP_INOUT;
4301 loc = &SUBREG_REG (*loc);
4302 mode = GET_MODE (*loc);
4305 old = *loc;
4306 if (get_reload_reg (type, mode, old, goal_alt[i],
4307 loc != curr_id->operand_loc[i], "", &new_reg)
4308 && type != OP_OUT)
4310 push_to_sequence (before);
4311 lra_emit_move (new_reg, old);
4312 before = get_insns ();
4313 end_sequence ();
4315 *loc = new_reg;
4316 if (type != OP_IN
4317 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4319 start_sequence ();
4320 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4321 emit_insn (after);
4322 after = get_insns ();
4323 end_sequence ();
4324 *loc = new_reg;
4326 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4327 if (goal_alt_dont_inherit_ops[j] == i)
4329 lra_set_regno_unique_value (REGNO (new_reg));
4330 break;
4332 lra_update_dup (curr_id, i);
4334 else if (curr_static_id->operand[i].type == OP_IN
4335 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4336 == OP_OUT
4337 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4338 == OP_INOUT
4339 && (operands_match_p
4340 (*curr_id->operand_loc[i],
4341 *curr_id->operand_loc[goal_alt_matched[i][0]],
4342 -1)))))
4344 /* generate reloads for input and matched outputs. */
4345 match_inputs[0] = i;
4346 match_inputs[1] = -1;
4347 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4348 goal_alt[i], &before, &after,
4349 curr_static_id->operand_alternative
4350 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4351 .earlyclobber);
4353 else if ((curr_static_id->operand[i].type == OP_OUT
4354 || (curr_static_id->operand[i].type == OP_INOUT
4355 && (operands_match_p
4356 (*curr_id->operand_loc[i],
4357 *curr_id->operand_loc[goal_alt_matched[i][0]],
4358 -1))))
4359 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4360 == OP_IN))
4361 /* Generate reloads for output and matched inputs. */
4362 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4363 &after, curr_static_id->operand_alternative
4364 [goal_alt_number * n_operands + i].earlyclobber);
4365 else if (curr_static_id->operand[i].type == OP_IN
4366 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4367 == OP_IN))
4369 /* Generate reloads for matched inputs. */
4370 match_inputs[0] = i;
4371 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4372 match_inputs[j + 1] = k;
4373 match_inputs[j + 1] = -1;
4374 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4375 &after, false);
4377 else
4378 /* We must generate code in any case when function
4379 process_alt_operands decides that it is possible. */
4380 gcc_unreachable ();
4382 /* Memorise processed outputs so that output remaining to be processed
4383 can avoid using the same register value (see match_reload). */
4384 if (curr_static_id->operand[i].type == OP_OUT)
4386 outputs[n_outputs++] = i;
4387 outputs[n_outputs] = -1;
4390 if (optional_p)
4392 rtx reg = op;
4394 lra_assert (REG_P (reg));
4395 regno = REGNO (reg);
4396 op = *curr_id->operand_loc[i]; /* Substitution. */
4397 if (GET_CODE (op) == SUBREG)
4398 op = SUBREG_REG (op);
4399 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4400 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4401 lra_reg_info[REGNO (op)].restore_rtx = reg;
4402 if (lra_dump_file != NULL)
4403 fprintf (lra_dump_file,
4404 " Making reload reg %d for reg %d optional\n",
4405 REGNO (op), regno);
4408 if (before != NULL_RTX || after != NULL_RTX
4409 || max_regno_before != max_reg_num ())
4410 change_p = true;
4411 if (change_p)
4413 lra_update_operator_dups (curr_id);
4414 /* Something changes -- process the insn. */
4415 lra_update_insn_regno_info (curr_insn);
4417 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4418 return change_p;
4421 /* Return true if INSN satisfies all constraints. In other words, no
4422 reload insns are needed. */
4423 bool
4424 lra_constrain_insn (rtx_insn *insn)
4426 int saved_new_regno_start = new_regno_start;
4427 int saved_new_insn_uid_start = new_insn_uid_start;
4428 bool change_p;
4430 curr_insn = insn;
4431 curr_id = lra_get_insn_recog_data (curr_insn);
4432 curr_static_id = curr_id->insn_static_data;
4433 new_insn_uid_start = get_max_uid ();
4434 new_regno_start = max_reg_num ();
4435 change_p = curr_insn_transform (true);
4436 new_regno_start = saved_new_regno_start;
4437 new_insn_uid_start = saved_new_insn_uid_start;
4438 return ! change_p;
4441 /* Return true if X is in LIST. */
4442 static bool
4443 in_list_p (rtx x, rtx list)
4445 for (; list != NULL_RTX; list = XEXP (list, 1))
4446 if (XEXP (list, 0) == x)
4447 return true;
4448 return false;
4451 /* Return true if X contains an allocatable hard register (if
4452 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4453 static bool
4454 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4456 int i, j;
4457 const char *fmt;
4458 enum rtx_code code;
4460 code = GET_CODE (x);
4461 if (REG_P (x))
4463 int regno = REGNO (x);
4464 HARD_REG_SET alloc_regs;
4466 if (hard_reg_p)
4468 if (regno >= FIRST_PSEUDO_REGISTER)
4469 regno = lra_get_regno_hard_regno (regno);
4470 if (regno < 0)
4471 return false;
4472 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4473 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4475 else
4477 if (regno < FIRST_PSEUDO_REGISTER)
4478 return false;
4479 if (! spilled_p)
4480 return true;
4481 return lra_get_regno_hard_regno (regno) < 0;
4484 fmt = GET_RTX_FORMAT (code);
4485 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4487 if (fmt[i] == 'e')
4489 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4490 return true;
4492 else if (fmt[i] == 'E')
4494 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4495 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4496 return true;
4499 return false;
4502 /* Process all regs in location *LOC and change them on equivalent
4503 substitution. Return true if any change was done. */
4504 static bool
4505 loc_equivalence_change_p (rtx *loc)
4507 rtx subst, reg, x = *loc;
4508 bool result = false;
4509 enum rtx_code code = GET_CODE (x);
4510 const char *fmt;
4511 int i, j;
4513 if (code == SUBREG)
4515 reg = SUBREG_REG (x);
4516 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4517 && GET_MODE (subst) == VOIDmode)
4519 /* We cannot reload debug location. Simplify subreg here
4520 while we know the inner mode. */
4521 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4522 GET_MODE (reg), SUBREG_BYTE (x));
4523 return true;
4526 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4528 *loc = subst;
4529 return true;
4532 /* Scan all the operand sub-expressions. */
4533 fmt = GET_RTX_FORMAT (code);
4534 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4536 if (fmt[i] == 'e')
4537 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4538 else if (fmt[i] == 'E')
4539 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4540 result
4541 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4543 return result;
4546 /* Similar to loc_equivalence_change_p, but for use as
4547 simplify_replace_fn_rtx callback. DATA is insn for which the
4548 elimination is done. If it null we don't do the elimination. */
4549 static rtx
4550 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4552 if (!REG_P (loc))
4553 return NULL_RTX;
4555 rtx subst = (data == NULL
4556 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4557 if (subst != loc)
4558 return subst;
4560 return NULL_RTX;
4563 /* Maximum number of generated reload insns per an insn. It is for
4564 preventing this pass cycling in a bug case. */
4565 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4567 /* The current iteration number of this LRA pass. */
4568 int lra_constraint_iter;
4570 /* True if we substituted equiv which needs checking register
4571 allocation correctness because the equivalent value contains
4572 allocatable hard registers or when we restore multi-register
4573 pseudo. */
4574 bool lra_risky_transformations_p;
4576 /* Return true if REGNO is referenced in more than one block. */
4577 static bool
4578 multi_block_pseudo_p (int regno)
4580 basic_block bb = NULL;
4581 unsigned int uid;
4582 bitmap_iterator bi;
4584 if (regno < FIRST_PSEUDO_REGISTER)
4585 return false;
4587 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4588 if (bb == NULL)
4589 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4590 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4591 return true;
4592 return false;
4595 /* Return true if LIST contains a deleted insn. */
4596 static bool
4597 contains_deleted_insn_p (rtx_insn_list *list)
4599 for (; list != NULL_RTX; list = list->next ())
4600 if (NOTE_P (list->insn ())
4601 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4602 return true;
4603 return false;
4606 /* Return true if X contains a pseudo dying in INSN. */
4607 static bool
4608 dead_pseudo_p (rtx x, rtx_insn *insn)
4610 int i, j;
4611 const char *fmt;
4612 enum rtx_code code;
4614 if (REG_P (x))
4615 return (insn != NULL_RTX
4616 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4617 code = GET_CODE (x);
4618 fmt = GET_RTX_FORMAT (code);
4619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4621 if (fmt[i] == 'e')
4623 if (dead_pseudo_p (XEXP (x, i), insn))
4624 return true;
4626 else if (fmt[i] == 'E')
4628 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4629 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4630 return true;
4633 return false;
4636 /* Return true if INSN contains a dying pseudo in INSN right hand
4637 side. */
4638 static bool
4639 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4641 rtx set = single_set (insn);
4643 gcc_assert (set != NULL);
4644 return dead_pseudo_p (SET_SRC (set), insn);
4647 /* Return true if any init insn of REGNO contains a dying pseudo in
4648 insn right hand side. */
4649 static bool
4650 init_insn_rhs_dead_pseudo_p (int regno)
4652 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4654 if (insns == NULL)
4655 return false;
4656 for (; insns != NULL_RTX; insns = insns->next ())
4657 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4658 return true;
4659 return false;
4662 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4663 reverse only if we have one init insn with given REGNO as a
4664 source. */
4665 static bool
4666 reverse_equiv_p (int regno)
4668 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4669 rtx set;
4671 if (insns == NULL)
4672 return false;
4673 if (! INSN_P (insns->insn ())
4674 || insns->next () != NULL)
4675 return false;
4676 if ((set = single_set (insns->insn ())) == NULL_RTX)
4677 return false;
4678 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4681 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4682 call this function only for non-reverse equivalence. */
4683 static bool
4684 contains_reloaded_insn_p (int regno)
4686 rtx set;
4687 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4689 for (; list != NULL; list = list->next ())
4690 if ((set = single_set (list->insn ())) == NULL_RTX
4691 || ! REG_P (SET_DEST (set))
4692 || (int) REGNO (SET_DEST (set)) != regno)
4693 return true;
4694 return false;
4697 /* Entry function of LRA constraint pass. Return true if the
4698 constraint pass did change the code. */
4699 bool
4700 lra_constraints (bool first_p)
4702 bool changed_p;
4703 int i, hard_regno, new_insns_num;
4704 unsigned int min_len, new_min_len, uid;
4705 rtx set, x, reg, dest_reg;
4706 basic_block last_bb;
4707 bitmap_iterator bi;
4709 lra_constraint_iter++;
4710 if (lra_dump_file != NULL)
4711 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4712 lra_constraint_iter);
4713 changed_p = false;
4714 if (pic_offset_table_rtx
4715 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4716 lra_risky_transformations_p = true;
4717 else
4718 /* On the first iteration we should check IRA assignment
4719 correctness. In rare cases, the assignments can be wrong as
4720 early clobbers operands are ignored in IRA. */
4721 lra_risky_transformations_p = first_p;
4722 new_insn_uid_start = get_max_uid ();
4723 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4724 /* Mark used hard regs for target stack size calulations. */
4725 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4726 if (lra_reg_info[i].nrefs != 0
4727 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4729 int j, nregs;
4731 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4732 for (j = 0; j < nregs; j++)
4733 df_set_regs_ever_live (hard_regno + j, true);
4735 /* Do elimination before the equivalence processing as we can spill
4736 some pseudos during elimination. */
4737 lra_eliminate (false, first_p);
4738 auto_bitmap equiv_insn_bitmap (&reg_obstack);
4739 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4740 if (lra_reg_info[i].nrefs != 0)
4742 ira_reg_equiv[i].profitable_p = true;
4743 reg = regno_reg_rtx[i];
4744 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4746 bool pseudo_p = contains_reg_p (x, false, false);
4748 /* After RTL transformation, we can not guarantee that
4749 pseudo in the substitution was not reloaded which might
4750 make equivalence invalid. For example, in reverse
4751 equiv of p0
4753 p0 <- ...
4755 equiv_mem <- p0
4757 the memory address register was reloaded before the 2nd
4758 insn. */
4759 if ((! first_p && pseudo_p)
4760 /* We don't use DF for compilation speed sake. So it
4761 is problematic to update live info when we use an
4762 equivalence containing pseudos in more than one
4763 BB. */
4764 || (pseudo_p && multi_block_pseudo_p (i))
4765 /* If an init insn was deleted for some reason, cancel
4766 the equiv. We could update the equiv insns after
4767 transformations including an equiv insn deletion
4768 but it is not worthy as such cases are extremely
4769 rare. */
4770 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4771 /* If it is not a reverse equivalence, we check that a
4772 pseudo in rhs of the init insn is not dying in the
4773 insn. Otherwise, the live info at the beginning of
4774 the corresponding BB might be wrong after we
4775 removed the insn. When the equiv can be a
4776 constant, the right hand side of the init insn can
4777 be a pseudo. */
4778 || (! reverse_equiv_p (i)
4779 && (init_insn_rhs_dead_pseudo_p (i)
4780 /* If we reloaded the pseudo in an equivalence
4781 init insn, we can not remove the equiv init
4782 insns and the init insns might write into
4783 const memory in this case. */
4784 || contains_reloaded_insn_p (i)))
4785 /* Prevent access beyond equivalent memory for
4786 paradoxical subregs. */
4787 || (MEM_P (x)
4788 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
4789 GET_MODE_SIZE (GET_MODE (x))))
4790 || (pic_offset_table_rtx
4791 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4792 && (targetm.preferred_reload_class
4793 (x, lra_get_allocno_class (i)) == NO_REGS))
4794 || contains_symbol_ref_p (x))))
4795 ira_reg_equiv[i].defined_p = false;
4796 if (contains_reg_p (x, false, true))
4797 ira_reg_equiv[i].profitable_p = false;
4798 if (get_equiv (reg) != reg)
4799 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4802 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4803 update_equiv (i);
4804 /* We should add all insns containing pseudos which should be
4805 substituted by their equivalences. */
4806 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
4807 lra_push_insn_by_uid (uid);
4808 min_len = lra_insn_stack_length ();
4809 new_insns_num = 0;
4810 last_bb = NULL;
4811 changed_p = false;
4812 while ((new_min_len = lra_insn_stack_length ()) != 0)
4814 curr_insn = lra_pop_insn ();
4815 --new_min_len;
4816 curr_bb = BLOCK_FOR_INSN (curr_insn);
4817 if (curr_bb != last_bb)
4819 last_bb = curr_bb;
4820 bb_reload_num = lra_curr_reload_num;
4822 if (min_len > new_min_len)
4824 min_len = new_min_len;
4825 new_insns_num = 0;
4827 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4828 internal_error
4829 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4830 MAX_RELOAD_INSNS_NUMBER);
4831 new_insns_num++;
4832 if (DEBUG_INSN_P (curr_insn))
4834 /* We need to check equivalence in debug insn and change
4835 pseudo to the equivalent value if necessary. */
4836 curr_id = lra_get_insn_recog_data (curr_insn);
4837 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
4839 rtx old = *curr_id->operand_loc[0];
4840 *curr_id->operand_loc[0]
4841 = simplify_replace_fn_rtx (old, NULL_RTX,
4842 loc_equivalence_callback, curr_insn);
4843 if (old != *curr_id->operand_loc[0])
4845 lra_update_insn_regno_info (curr_insn);
4846 changed_p = true;
4850 else if (INSN_P (curr_insn))
4852 if ((set = single_set (curr_insn)) != NULL_RTX)
4854 dest_reg = SET_DEST (set);
4855 /* The equivalence pseudo could be set up as SUBREG in a
4856 case when it is a call restore insn in a mode
4857 different from the pseudo mode. */
4858 if (GET_CODE (dest_reg) == SUBREG)
4859 dest_reg = SUBREG_REG (dest_reg);
4860 if ((REG_P (dest_reg)
4861 && (x = get_equiv (dest_reg)) != dest_reg
4862 /* Remove insns which set up a pseudo whose value
4863 can not be changed. Such insns might be not in
4864 init_insns because we don't update equiv data
4865 during insn transformations.
4867 As an example, let suppose that a pseudo got
4868 hard register and on the 1st pass was not
4869 changed to equivalent constant. We generate an
4870 additional insn setting up the pseudo because of
4871 secondary memory movement. Then the pseudo is
4872 spilled and we use the equiv constant. In this
4873 case we should remove the additional insn and
4874 this insn is not init_insns list. */
4875 && (! MEM_P (x) || MEM_READONLY_P (x)
4876 /* Check that this is actually an insn setting
4877 up the equivalence. */
4878 || in_list_p (curr_insn,
4879 ira_reg_equiv
4880 [REGNO (dest_reg)].init_insns)))
4881 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4882 && in_list_p (curr_insn,
4883 ira_reg_equiv
4884 [REGNO (SET_SRC (set))].init_insns)))
4886 /* This is equiv init insn of pseudo which did not get a
4887 hard register -- remove the insn. */
4888 if (lra_dump_file != NULL)
4890 fprintf (lra_dump_file,
4891 " Removing equiv init insn %i (freq=%d)\n",
4892 INSN_UID (curr_insn),
4893 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4894 dump_insn_slim (lra_dump_file, curr_insn);
4896 if (contains_reg_p (x, true, false))
4897 lra_risky_transformations_p = true;
4898 lra_set_insn_deleted (curr_insn);
4899 continue;
4902 curr_id = lra_get_insn_recog_data (curr_insn);
4903 curr_static_id = curr_id->insn_static_data;
4904 init_curr_insn_input_reloads ();
4905 init_curr_operand_mode ();
4906 if (curr_insn_transform (false))
4907 changed_p = true;
4908 /* Check non-transformed insns too for equiv change as USE
4909 or CLOBBER don't need reloads but can contain pseudos
4910 being changed on their equivalences. */
4911 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
4912 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4914 lra_update_insn_regno_info (curr_insn);
4915 changed_p = true;
4920 /* If we used a new hard regno, changed_p should be true because the
4921 hard reg is assigned to a new pseudo. */
4922 if (flag_checking && !changed_p)
4924 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4925 if (lra_reg_info[i].nrefs != 0
4926 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4928 int j, nregs = hard_regno_nregs (hard_regno,
4929 PSEUDO_REGNO_MODE (i));
4931 for (j = 0; j < nregs; j++)
4932 lra_assert (df_regs_ever_live_p (hard_regno + j));
4935 return changed_p;
4938 static void initiate_invariants (void);
4939 static void finish_invariants (void);
4941 /* Initiate the LRA constraint pass. It is done once per
4942 function. */
4943 void
4944 lra_constraints_init (void)
4946 initiate_invariants ();
4949 /* Finalize the LRA constraint pass. It is done once per
4950 function. */
4951 void
4952 lra_constraints_finish (void)
4954 finish_invariants ();
4959 /* Structure describes invariants for ineheritance. */
4960 struct lra_invariant
4962 /* The order number of the invariant. */
4963 int num;
4964 /* The invariant RTX. */
4965 rtx invariant_rtx;
4966 /* The origin insn of the invariant. */
4967 rtx_insn *insn;
4970 typedef lra_invariant invariant_t;
4971 typedef invariant_t *invariant_ptr_t;
4972 typedef const invariant_t *const_invariant_ptr_t;
4974 /* Pointer to the inheritance invariants. */
4975 static vec<invariant_ptr_t> invariants;
4977 /* Allocation pool for the invariants. */
4978 static object_allocator<lra_invariant> *invariants_pool;
4980 /* Hash table for the invariants. */
4981 static htab_t invariant_table;
4983 /* Hash function for INVARIANT. */
4984 static hashval_t
4985 invariant_hash (const void *invariant)
4987 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
4988 return lra_rtx_hash (inv);
4991 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4992 static int
4993 invariant_eq_p (const void *invariant1, const void *invariant2)
4995 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
4996 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
4998 return rtx_equal_p (inv1, inv2);
5001 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5002 invariant which is in the table. */
5003 static invariant_ptr_t
5004 insert_invariant (rtx invariant_rtx)
5006 void **entry_ptr;
5007 invariant_t invariant;
5008 invariant_ptr_t invariant_ptr;
5010 invariant.invariant_rtx = invariant_rtx;
5011 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5012 if (*entry_ptr == NULL)
5014 invariant_ptr = invariants_pool->allocate ();
5015 invariant_ptr->invariant_rtx = invariant_rtx;
5016 invariant_ptr->insn = NULL;
5017 invariants.safe_push (invariant_ptr);
5018 *entry_ptr = (void *) invariant_ptr;
5020 return (invariant_ptr_t) *entry_ptr;
5023 /* Initiate the invariant table. */
5024 static void
5025 initiate_invariants (void)
5027 invariants.create (100);
5028 invariants_pool
5029 = new object_allocator<lra_invariant> ("Inheritance invariants");
5030 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5033 /* Finish the invariant table. */
5034 static void
5035 finish_invariants (void)
5037 htab_delete (invariant_table);
5038 delete invariants_pool;
5039 invariants.release ();
5042 /* Make the invariant table empty. */
5043 static void
5044 clear_invariants (void)
5046 htab_empty (invariant_table);
5047 invariants_pool->release ();
5048 invariants.truncate (0);
5053 /* This page contains code to do inheritance/split
5054 transformations. */
5056 /* Number of reloads passed so far in current EBB. */
5057 static int reloads_num;
5059 /* Number of calls passed so far in current EBB. */
5060 static int calls_num;
5062 /* Current reload pseudo check for validity of elements in
5063 USAGE_INSNS. */
5064 static int curr_usage_insns_check;
5066 /* Info about last usage of registers in EBB to do inheritance/split
5067 transformation. Inheritance transformation is done from a spilled
5068 pseudo and split transformations from a hard register or a pseudo
5069 assigned to a hard register. */
5070 struct usage_insns
5072 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5073 value INSNS is valid. The insns is chain of optional debug insns
5074 and a finishing non-debug insn using the corresponding reg. The
5075 value is also used to mark the registers which are set up in the
5076 current insn. The negated insn uid is used for this. */
5077 int check;
5078 /* Value of global reloads_num at the last insn in INSNS. */
5079 int reloads_num;
5080 /* Value of global reloads_nums at the last insn in INSNS. */
5081 int calls_num;
5082 /* It can be true only for splitting. And it means that the restore
5083 insn should be put after insn given by the following member. */
5084 bool after_p;
5085 /* Next insns in the current EBB which use the original reg and the
5086 original reg value is not changed between the current insn and
5087 the next insns. In order words, e.g. for inheritance, if we need
5088 to use the original reg value again in the next insns we can try
5089 to use the value in a hard register from a reload insn of the
5090 current insn. */
5091 rtx insns;
5094 /* Map: regno -> corresponding pseudo usage insns. */
5095 static struct usage_insns *usage_insns;
5097 static void
5098 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5100 usage_insns[regno].check = curr_usage_insns_check;
5101 usage_insns[regno].insns = insn;
5102 usage_insns[regno].reloads_num = reloads_num;
5103 usage_insns[regno].calls_num = calls_num;
5104 usage_insns[regno].after_p = after_p;
5107 /* The function is used to form list REGNO usages which consists of
5108 optional debug insns finished by a non-debug insn using REGNO.
5109 RELOADS_NUM is current number of reload insns processed so far. */
5110 static void
5111 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5113 rtx next_usage_insns;
5115 if (usage_insns[regno].check == curr_usage_insns_check
5116 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5117 && DEBUG_INSN_P (insn))
5119 /* Check that we did not add the debug insn yet. */
5120 if (next_usage_insns != insn
5121 && (GET_CODE (next_usage_insns) != INSN_LIST
5122 || XEXP (next_usage_insns, 0) != insn))
5123 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5124 next_usage_insns);
5126 else if (NONDEBUG_INSN_P (insn))
5127 setup_next_usage_insn (regno, insn, reloads_num, false);
5128 else
5129 usage_insns[regno].check = 0;
5132 /* Return first non-debug insn in list USAGE_INSNS. */
5133 static rtx_insn *
5134 skip_usage_debug_insns (rtx usage_insns)
5136 rtx insn;
5138 /* Skip debug insns. */
5139 for (insn = usage_insns;
5140 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5141 insn = XEXP (insn, 1))
5143 return safe_as_a <rtx_insn *> (insn);
5146 /* Return true if we need secondary memory moves for insn in
5147 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5148 into the insn. */
5149 static bool
5150 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5151 rtx usage_insns ATTRIBUTE_UNUSED)
5153 rtx_insn *insn;
5154 rtx set, dest;
5155 enum reg_class cl;
5157 if (inher_cl == ALL_REGS
5158 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5159 return false;
5160 lra_assert (INSN_P (insn));
5161 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5162 return false;
5163 dest = SET_DEST (set);
5164 if (! REG_P (dest))
5165 return false;
5166 lra_assert (inher_cl != NO_REGS);
5167 cl = get_reg_class (REGNO (dest));
5168 return (cl != NO_REGS && cl != ALL_REGS
5169 && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5172 /* Registers involved in inheritance/split in the current EBB
5173 (inheritance/split pseudos and original registers). */
5174 static bitmap_head check_only_regs;
5176 /* Reload pseudos can not be involded in invariant inheritance in the
5177 current EBB. */
5178 static bitmap_head invalid_invariant_regs;
5180 /* Do inheritance transformations for insn INSN, which defines (if
5181 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5182 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5183 form as the "insns" field of usage_insns. Return true if we
5184 succeed in such transformation.
5186 The transformations look like:
5188 p <- ... i <- ...
5189 ... p <- i (new insn)
5190 ... =>
5191 <- ... p ... <- ... i ...
5193 ... i <- p (new insn)
5194 <- ... p ... <- ... i ...
5195 ... =>
5196 <- ... p ... <- ... i ...
5197 where p is a spilled original pseudo and i is a new inheritance pseudo.
5200 The inheritance pseudo has the smallest class of two classes CL and
5201 class of ORIGINAL REGNO. */
5202 static bool
5203 inherit_reload_reg (bool def_p, int original_regno,
5204 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5206 if (optimize_function_for_size_p (cfun))
5207 return false;
5209 enum reg_class rclass = lra_get_allocno_class (original_regno);
5210 rtx original_reg = regno_reg_rtx[original_regno];
5211 rtx new_reg, usage_insn;
5212 rtx_insn *new_insns;
5214 lra_assert (! usage_insns[original_regno].after_p);
5215 if (lra_dump_file != NULL)
5216 fprintf (lra_dump_file,
5217 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5218 if (! ira_reg_classes_intersect_p[cl][rclass])
5220 if (lra_dump_file != NULL)
5222 fprintf (lra_dump_file,
5223 " Rejecting inheritance for %d "
5224 "because of disjoint classes %s and %s\n",
5225 original_regno, reg_class_names[cl],
5226 reg_class_names[rclass]);
5227 fprintf (lra_dump_file,
5228 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5230 return false;
5232 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5233 /* We don't use a subset of two classes because it can be
5234 NO_REGS. This transformation is still profitable in most
5235 cases even if the classes are not intersected as register
5236 move is probably cheaper than a memory load. */
5237 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5239 if (lra_dump_file != NULL)
5240 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5241 reg_class_names[cl], reg_class_names[rclass]);
5243 rclass = cl;
5245 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5247 /* Reject inheritance resulting in secondary memory moves.
5248 Otherwise, there is a danger in LRA cycling. Also such
5249 transformation will be unprofitable. */
5250 if (lra_dump_file != NULL)
5252 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5253 rtx set = single_set (insn);
5255 lra_assert (set != NULL_RTX);
5257 rtx dest = SET_DEST (set);
5259 lra_assert (REG_P (dest));
5260 fprintf (lra_dump_file,
5261 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5262 "as secondary mem is needed\n",
5263 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5264 original_regno, reg_class_names[rclass]);
5265 fprintf (lra_dump_file,
5266 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5268 return false;
5270 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5271 rclass, "inheritance");
5272 start_sequence ();
5273 if (def_p)
5274 lra_emit_move (original_reg, new_reg);
5275 else
5276 lra_emit_move (new_reg, original_reg);
5277 new_insns = get_insns ();
5278 end_sequence ();
5279 if (NEXT_INSN (new_insns) != NULL_RTX)
5281 if (lra_dump_file != NULL)
5283 fprintf (lra_dump_file,
5284 " Rejecting inheritance %d->%d "
5285 "as it results in 2 or more insns:\n",
5286 original_regno, REGNO (new_reg));
5287 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5288 fprintf (lra_dump_file,
5289 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5291 return false;
5293 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5294 lra_update_insn_regno_info (insn);
5295 if (! def_p)
5296 /* We now have a new usage insn for original regno. */
5297 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5298 if (lra_dump_file != NULL)
5299 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5300 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5301 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5302 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5303 bitmap_set_bit (&check_only_regs, original_regno);
5304 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5305 if (def_p)
5306 lra_process_new_insns (insn, NULL, new_insns,
5307 "Add original<-inheritance");
5308 else
5309 lra_process_new_insns (insn, new_insns, NULL,
5310 "Add inheritance<-original");
5311 while (next_usage_insns != NULL_RTX)
5313 if (GET_CODE (next_usage_insns) != INSN_LIST)
5315 usage_insn = next_usage_insns;
5316 lra_assert (NONDEBUG_INSN_P (usage_insn));
5317 next_usage_insns = NULL;
5319 else
5321 usage_insn = XEXP (next_usage_insns, 0);
5322 lra_assert (DEBUG_INSN_P (usage_insn));
5323 next_usage_insns = XEXP (next_usage_insns, 1);
5325 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5326 DEBUG_INSN_P (usage_insn));
5327 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5328 if (lra_dump_file != NULL)
5330 basic_block bb = BLOCK_FOR_INSN (usage_insn);
5331 fprintf (lra_dump_file,
5332 " Inheritance reuse change %d->%d (bb%d):\n",
5333 original_regno, REGNO (new_reg),
5334 bb ? bb->index : -1);
5335 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5338 if (lra_dump_file != NULL)
5339 fprintf (lra_dump_file,
5340 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5341 return true;
5344 /* Return true if we need a caller save/restore for pseudo REGNO which
5345 was assigned to a hard register. */
5346 static inline bool
5347 need_for_call_save_p (int regno)
5349 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5350 return (usage_insns[regno].calls_num < calls_num
5351 && (overlaps_hard_reg_set_p
5352 ((flag_ipa_ra &&
5353 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
5354 ? lra_reg_info[regno].actual_call_used_reg_set
5355 : call_used_reg_set,
5356 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
5357 || (targetm.hard_regno_call_part_clobbered
5358 (reg_renumber[regno], PSEUDO_REGNO_MODE (regno)))));
5361 /* Global registers occurring in the current EBB. */
5362 static bitmap_head ebb_global_regs;
5364 /* Return true if we need a split for hard register REGNO or pseudo
5365 REGNO which was assigned to a hard register.
5366 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5367 used for reloads since the EBB end. It is an approximation of the
5368 used hard registers in the split range. The exact value would
5369 require expensive calculations. If we were aggressive with
5370 splitting because of the approximation, the split pseudo will save
5371 the same hard register assignment and will be removed in the undo
5372 pass. We still need the approximation because too aggressive
5373 splitting would result in too inaccurate cost calculation in the
5374 assignment pass because of too many generated moves which will be
5375 probably removed in the undo pass. */
5376 static inline bool
5377 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5379 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5381 lra_assert (hard_regno >= 0);
5382 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5383 /* Don't split eliminable hard registers, otherwise we can
5384 split hard registers like hard frame pointer, which
5385 lives on BB start/end according to DF-infrastructure,
5386 when there is a pseudo assigned to the register and
5387 living in the same BB. */
5388 && (regno >= FIRST_PSEUDO_REGISTER
5389 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5390 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5391 /* Don't split call clobbered hard regs living through
5392 calls, otherwise we might have a check problem in the
5393 assign sub-pass as in the most cases (exception is a
5394 situation when lra_risky_transformations_p value is
5395 true) the assign pass assumes that all pseudos living
5396 through calls are assigned to call saved hard regs. */
5397 && (regno >= FIRST_PSEUDO_REGISTER
5398 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
5399 || usage_insns[regno].calls_num == calls_num)
5400 /* We need at least 2 reloads to make pseudo splitting
5401 profitable. We should provide hard regno splitting in
5402 any case to solve 1st insn scheduling problem when
5403 moving hard register definition up might result in
5404 impossibility to find hard register for reload pseudo of
5405 small register class. */
5406 && (usage_insns[regno].reloads_num
5407 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5408 && (regno < FIRST_PSEUDO_REGISTER
5409 /* For short living pseudos, spilling + inheritance can
5410 be considered a substitution for splitting.
5411 Therefore we do not splitting for local pseudos. It
5412 decreases also aggressiveness of splitting. The
5413 minimal number of references is chosen taking into
5414 account that for 2 references splitting has no sense
5415 as we can just spill the pseudo. */
5416 || (regno >= FIRST_PSEUDO_REGISTER
5417 && lra_reg_info[regno].nrefs > 3
5418 && bitmap_bit_p (&ebb_global_regs, regno))))
5419 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5422 /* Return class for the split pseudo created from original pseudo with
5423 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5424 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5425 results in no secondary memory movements. */
5426 static enum reg_class
5427 choose_split_class (enum reg_class allocno_class,
5428 int hard_regno ATTRIBUTE_UNUSED,
5429 machine_mode mode ATTRIBUTE_UNUSED)
5431 int i;
5432 enum reg_class cl, best_cl = NO_REGS;
5433 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5434 = REGNO_REG_CLASS (hard_regno);
5436 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5437 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5438 return allocno_class;
5439 for (i = 0;
5440 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5441 i++)
5442 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5443 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5444 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5445 && (best_cl == NO_REGS
5446 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
5447 best_cl = cl;
5448 return best_cl;
5451 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5452 It only makes sense to call this function if NEW_REGNO is always
5453 equal to ORIGINAL_REGNO. */
5455 static void
5456 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5458 if (!ira_reg_equiv[original_regno].defined_p)
5459 return;
5461 ira_expand_reg_equiv ();
5462 ira_reg_equiv[new_regno].defined_p = true;
5463 if (ira_reg_equiv[original_regno].memory)
5464 ira_reg_equiv[new_regno].memory
5465 = copy_rtx (ira_reg_equiv[original_regno].memory);
5466 if (ira_reg_equiv[original_regno].constant)
5467 ira_reg_equiv[new_regno].constant
5468 = copy_rtx (ira_reg_equiv[original_regno].constant);
5469 if (ira_reg_equiv[original_regno].invariant)
5470 ira_reg_equiv[new_regno].invariant
5471 = copy_rtx (ira_reg_equiv[original_regno].invariant);
5474 /* Do split transformations for insn INSN, which defines or uses
5475 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5476 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5477 "insns" field of usage_insns. If TO is not NULL, we don't use
5478 usage_insns, we put restore insns after TO insn.
5480 The transformations look like:
5482 p <- ... p <- ...
5483 ... s <- p (new insn -- save)
5484 ... =>
5485 ... p <- s (new insn -- restore)
5486 <- ... p ... <- ... p ...
5488 <- ... p ... <- ... p ...
5489 ... s <- p (new insn -- save)
5490 ... =>
5491 ... p <- s (new insn -- restore)
5492 <- ... p ... <- ... p ...
5494 where p is an original pseudo got a hard register or a hard
5495 register and s is a new split pseudo. The save is put before INSN
5496 if BEFORE_P is true. Return true if we succeed in such
5497 transformation. */
5498 static bool
5499 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5500 rtx next_usage_insns, rtx_insn *to)
5502 enum reg_class rclass;
5503 rtx original_reg;
5504 int hard_regno, nregs;
5505 rtx new_reg, usage_insn;
5506 rtx_insn *restore, *save;
5507 bool after_p;
5508 bool call_save_p;
5509 machine_mode mode;
5511 if (original_regno < FIRST_PSEUDO_REGISTER)
5513 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5514 hard_regno = original_regno;
5515 call_save_p = false;
5516 nregs = 1;
5517 mode = lra_reg_info[hard_regno].biggest_mode;
5518 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5519 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5520 as part of a multi-word register. In that case, or if the biggest
5521 mode was larger than a register, just use the reg_rtx. Otherwise,
5522 limit the size to that of the biggest access in the function. */
5523 if (mode == VOIDmode
5524 || paradoxical_subreg_p (mode, reg_rtx_mode))
5526 original_reg = regno_reg_rtx[hard_regno];
5527 mode = reg_rtx_mode;
5529 else
5530 original_reg = gen_rtx_REG (mode, hard_regno);
5532 else
5534 mode = PSEUDO_REGNO_MODE (original_regno);
5535 hard_regno = reg_renumber[original_regno];
5536 nregs = hard_regno_nregs (hard_regno, mode);
5537 rclass = lra_get_allocno_class (original_regno);
5538 original_reg = regno_reg_rtx[original_regno];
5539 call_save_p = need_for_call_save_p (original_regno);
5541 lra_assert (hard_regno >= 0);
5542 if (lra_dump_file != NULL)
5543 fprintf (lra_dump_file,
5544 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5546 if (call_save_p)
5548 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5549 hard_regno_nregs (hard_regno, mode),
5550 mode);
5551 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5553 else
5555 rclass = choose_split_class (rclass, hard_regno, mode);
5556 if (rclass == NO_REGS)
5558 if (lra_dump_file != NULL)
5560 fprintf (lra_dump_file,
5561 " Rejecting split of %d(%s): "
5562 "no good reg class for %d(%s)\n",
5563 original_regno,
5564 reg_class_names[lra_get_allocno_class (original_regno)],
5565 hard_regno,
5566 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5567 fprintf
5568 (lra_dump_file,
5569 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5571 return false;
5573 /* Split_if_necessary can split hard registers used as part of a
5574 multi-register mode but splits each register individually. The
5575 mode used for each independent register may not be supported
5576 so reject the split. Splitting the wider mode should theoretically
5577 be possible but is not implemented. */
5578 if (!targetm.hard_regno_mode_ok (hard_regno, mode))
5580 if (lra_dump_file != NULL)
5582 fprintf (lra_dump_file,
5583 " Rejecting split of %d(%s): unsuitable mode %s\n",
5584 original_regno,
5585 reg_class_names[lra_get_allocno_class (original_regno)],
5586 GET_MODE_NAME (mode));
5587 fprintf
5588 (lra_dump_file,
5589 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5591 return false;
5593 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5594 reg_renumber[REGNO (new_reg)] = hard_regno;
5596 int new_regno = REGNO (new_reg);
5597 save = emit_spill_move (true, new_reg, original_reg);
5598 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5600 if (lra_dump_file != NULL)
5602 fprintf
5603 (lra_dump_file,
5604 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5605 original_regno, new_regno);
5606 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5607 fprintf (lra_dump_file,
5608 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5610 return false;
5612 restore = emit_spill_move (false, new_reg, original_reg);
5613 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5615 if (lra_dump_file != NULL)
5617 fprintf (lra_dump_file,
5618 " Rejecting split %d->%d "
5619 "resulting in > 2 restore insns:\n",
5620 original_regno, new_regno);
5621 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5622 fprintf (lra_dump_file,
5623 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5625 return false;
5627 /* Transfer equivalence information to the spill register, so that
5628 if we fail to allocate the spill register, we have the option of
5629 rematerializing the original value instead of spilling to the stack. */
5630 if (!HARD_REGISTER_NUM_P (original_regno)
5631 && mode == PSEUDO_REGNO_MODE (original_regno))
5632 lra_copy_reg_equiv (new_regno, original_regno);
5633 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
5634 bitmap_set_bit (&check_only_regs, new_regno);
5635 bitmap_set_bit (&check_only_regs, original_regno);
5636 bitmap_set_bit (&lra_split_regs, new_regno);
5637 if (to != NULL)
5639 usage_insn = to;
5640 after_p = TRUE;
5642 else
5644 after_p = usage_insns[original_regno].after_p;
5645 for (;;)
5647 if (GET_CODE (next_usage_insns) != INSN_LIST)
5649 usage_insn = next_usage_insns;
5650 break;
5652 usage_insn = XEXP (next_usage_insns, 0);
5653 lra_assert (DEBUG_INSN_P (usage_insn));
5654 next_usage_insns = XEXP (next_usage_insns, 1);
5655 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5656 true);
5657 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5658 if (lra_dump_file != NULL)
5660 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5661 original_regno, new_regno);
5662 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5666 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5667 lra_assert (usage_insn != insn || (after_p && before_p));
5668 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5669 after_p ? NULL : restore,
5670 after_p ? restore : NULL,
5671 call_save_p
5672 ? "Add reg<-save" : "Add reg<-split");
5673 lra_process_new_insns (insn, before_p ? save : NULL,
5674 before_p ? NULL : save,
5675 call_save_p
5676 ? "Add save<-reg" : "Add split<-reg");
5677 if (nregs > 1)
5678 /* If we are trying to split multi-register. We should check
5679 conflicts on the next assignment sub-pass. IRA can allocate on
5680 sub-register levels, LRA do this on pseudos level right now and
5681 this discrepancy may create allocation conflicts after
5682 splitting. */
5683 lra_risky_transformations_p = true;
5684 if (lra_dump_file != NULL)
5685 fprintf (lra_dump_file,
5686 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5687 return true;
5690 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5691 in the range [FROM, TO]. Return true if did a split. Otherwise,
5692 return false. */
5693 bool
5694 spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to)
5696 int i, hard_regno;
5697 int rclass_size;
5698 rtx_insn *insn;
5699 unsigned int uid;
5700 bitmap_iterator bi;
5701 HARD_REG_SET ignore;
5703 lra_assert (from != NULL && to != NULL);
5704 CLEAR_HARD_REG_SET (ignore);
5705 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
5707 lra_insn_recog_data_t id = lra_insn_recog_data[uid];
5708 struct lra_static_insn_data *static_id = id->insn_static_data;
5709 struct lra_insn_reg *reg;
5711 for (reg = id->regs; reg != NULL; reg = reg->next)
5712 if (reg->regno < FIRST_PSEUDO_REGISTER)
5713 SET_HARD_REG_BIT (ignore, reg->regno);
5714 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5715 SET_HARD_REG_BIT (ignore, reg->regno);
5717 rclass_size = ira_class_hard_regs_num[rclass];
5718 for (i = 0; i < rclass_size; i++)
5720 hard_regno = ira_class_hard_regs[rclass][i];
5721 if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
5722 || TEST_HARD_REG_BIT (ignore, hard_regno))
5723 continue;
5724 for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
5726 lra_insn_recog_data_t id = lra_insn_recog_data[uid = INSN_UID (insn)];
5727 struct lra_static_insn_data *static_id = id->insn_static_data;
5728 struct lra_insn_reg *reg;
5730 if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, uid))
5731 break;
5732 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5733 if (reg->regno == hard_regno)
5734 break;
5735 if (reg != NULL)
5736 break;
5738 if (insn != NEXT_INSN (to))
5739 continue;
5740 if (split_reg (TRUE, hard_regno, from, NULL, to))
5741 return true;
5743 return false;
5746 /* Recognize that we need a split transformation for insn INSN, which
5747 defines or uses REGNO in its insn biggest MODE (we use it only if
5748 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5749 hard registers which might be used for reloads since the EBB end.
5750 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5751 uid before starting INSN processing. Return true if we succeed in
5752 such transformation. */
5753 static bool
5754 split_if_necessary (int regno, machine_mode mode,
5755 HARD_REG_SET potential_reload_hard_regs,
5756 bool before_p, rtx_insn *insn, int max_uid)
5758 bool res = false;
5759 int i, nregs = 1;
5760 rtx next_usage_insns;
5762 if (regno < FIRST_PSEUDO_REGISTER)
5763 nregs = hard_regno_nregs (regno, mode);
5764 for (i = 0; i < nregs; i++)
5765 if (usage_insns[regno + i].check == curr_usage_insns_check
5766 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5767 /* To avoid processing the register twice or more. */
5768 && ((GET_CODE (next_usage_insns) != INSN_LIST
5769 && INSN_UID (next_usage_insns) < max_uid)
5770 || (GET_CODE (next_usage_insns) == INSN_LIST
5771 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5772 && need_for_split_p (potential_reload_hard_regs, regno + i)
5773 && split_reg (before_p, regno + i, insn, next_usage_insns, NULL))
5774 res = true;
5775 return res;
5778 /* Return TRUE if rtx X is considered as an invariant for
5779 inheritance. */
5780 static bool
5781 invariant_p (const_rtx x)
5783 machine_mode mode;
5784 const char *fmt;
5785 enum rtx_code code;
5786 int i, j;
5788 code = GET_CODE (x);
5789 mode = GET_MODE (x);
5790 if (code == SUBREG)
5792 x = SUBREG_REG (x);
5793 code = GET_CODE (x);
5794 mode = wider_subreg_mode (mode, GET_MODE (x));
5797 if (MEM_P (x))
5798 return false;
5800 if (REG_P (x))
5802 int i, nregs, regno = REGNO (x);
5804 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
5805 || TEST_HARD_REG_BIT (eliminable_regset, regno)
5806 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
5807 return false;
5808 nregs = hard_regno_nregs (regno, mode);
5809 for (i = 0; i < nregs; i++)
5810 if (! fixed_regs[regno + i]
5811 /* A hard register may be clobbered in the current insn
5812 but we can ignore this case because if the hard
5813 register is used it should be set somewhere after the
5814 clobber. */
5815 || bitmap_bit_p (&invalid_invariant_regs, regno + i))
5816 return false;
5818 fmt = GET_RTX_FORMAT (code);
5819 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5821 if (fmt[i] == 'e')
5823 if (! invariant_p (XEXP (x, i)))
5824 return false;
5826 else if (fmt[i] == 'E')
5828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5829 if (! invariant_p (XVECEXP (x, i, j)))
5830 return false;
5833 return true;
5836 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5837 inheritance transformation (using dest_reg instead invariant in a
5838 subsequent insn). */
5839 static bool
5840 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
5842 invariant_ptr_t invariant_ptr;
5843 rtx_insn *insn, *new_insns;
5844 rtx insn_set, insn_reg, new_reg;
5845 int insn_regno;
5846 bool succ_p = false;
5847 int dst_regno = REGNO (dst_reg);
5848 machine_mode dst_mode = GET_MODE (dst_reg);
5849 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
5851 invariant_ptr = insert_invariant (invariant_rtx);
5852 if ((insn = invariant_ptr->insn) != NULL_RTX)
5854 /* We have a subsequent insn using the invariant. */
5855 insn_set = single_set (insn);
5856 lra_assert (insn_set != NULL);
5857 insn_reg = SET_DEST (insn_set);
5858 lra_assert (REG_P (insn_reg));
5859 insn_regno = REGNO (insn_reg);
5860 insn_reg_cl = lra_get_allocno_class (insn_regno);
5862 if (dst_mode == GET_MODE (insn_reg)
5863 /* We should consider only result move reg insns which are
5864 cheap. */
5865 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
5866 && targetm.register_move_cost (dst_mode, cl, cl) == 2)
5868 if (lra_dump_file != NULL)
5869 fprintf (lra_dump_file,
5870 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5871 new_reg = lra_create_new_reg (dst_mode, dst_reg,
5872 cl, "invariant inheritance");
5873 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5874 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5875 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
5876 start_sequence ();
5877 lra_emit_move (new_reg, dst_reg);
5878 new_insns = get_insns ();
5879 end_sequence ();
5880 lra_process_new_insns (curr_insn, NULL, new_insns,
5881 "Add invariant inheritance<-original");
5882 start_sequence ();
5883 lra_emit_move (SET_DEST (insn_set), new_reg);
5884 new_insns = get_insns ();
5885 end_sequence ();
5886 lra_process_new_insns (insn, NULL, new_insns,
5887 "Changing reload<-inheritance");
5888 lra_set_insn_deleted (insn);
5889 succ_p = true;
5890 if (lra_dump_file != NULL)
5892 fprintf (lra_dump_file,
5893 " Invariant inheritance reuse change %d (bb%d):\n",
5894 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5895 dump_insn_slim (lra_dump_file, insn);
5896 fprintf (lra_dump_file,
5897 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5901 invariant_ptr->insn = curr_insn;
5902 return succ_p;
5905 /* Check only registers living at the current program point in the
5906 current EBB. */
5907 static bitmap_head live_regs;
5909 /* Update live info in EBB given by its HEAD and TAIL insns after
5910 inheritance/split transformation. The function removes dead moves
5911 too. */
5912 static void
5913 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5915 unsigned int j;
5916 int i, regno;
5917 bool live_p;
5918 rtx_insn *prev_insn;
5919 rtx set;
5920 bool remove_p;
5921 basic_block last_bb, prev_bb, curr_bb;
5922 bitmap_iterator bi;
5923 struct lra_insn_reg *reg;
5924 edge e;
5925 edge_iterator ei;
5927 last_bb = BLOCK_FOR_INSN (tail);
5928 prev_bb = NULL;
5929 for (curr_insn = tail;
5930 curr_insn != PREV_INSN (head);
5931 curr_insn = prev_insn)
5933 prev_insn = PREV_INSN (curr_insn);
5934 /* We need to process empty blocks too. They contain
5935 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5936 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5937 continue;
5938 curr_bb = BLOCK_FOR_INSN (curr_insn);
5939 if (curr_bb != prev_bb)
5941 if (prev_bb != NULL)
5943 /* Update df_get_live_in (prev_bb): */
5944 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5945 if (bitmap_bit_p (&live_regs, j))
5946 bitmap_set_bit (df_get_live_in (prev_bb), j);
5947 else
5948 bitmap_clear_bit (df_get_live_in (prev_bb), j);
5950 if (curr_bb != last_bb)
5952 /* Update df_get_live_out (curr_bb): */
5953 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5955 live_p = bitmap_bit_p (&live_regs, j);
5956 if (! live_p)
5957 FOR_EACH_EDGE (e, ei, curr_bb->succs)
5958 if (bitmap_bit_p (df_get_live_in (e->dest), j))
5960 live_p = true;
5961 break;
5963 if (live_p)
5964 bitmap_set_bit (df_get_live_out (curr_bb), j);
5965 else
5966 bitmap_clear_bit (df_get_live_out (curr_bb), j);
5969 prev_bb = curr_bb;
5970 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5972 if (! NONDEBUG_INSN_P (curr_insn))
5973 continue;
5974 curr_id = lra_get_insn_recog_data (curr_insn);
5975 curr_static_id = curr_id->insn_static_data;
5976 remove_p = false;
5977 if ((set = single_set (curr_insn)) != NULL_RTX
5978 && REG_P (SET_DEST (set))
5979 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5980 && SET_DEST (set) != pic_offset_table_rtx
5981 && bitmap_bit_p (&check_only_regs, regno)
5982 && ! bitmap_bit_p (&live_regs, regno))
5983 remove_p = true;
5984 /* See which defined values die here. */
5985 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5986 if (reg->type == OP_OUT && ! reg->subreg_p)
5987 bitmap_clear_bit (&live_regs, reg->regno);
5988 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5989 if (reg->type == OP_OUT && ! reg->subreg_p)
5990 bitmap_clear_bit (&live_regs, reg->regno);
5991 if (curr_id->arg_hard_regs != NULL)
5992 /* Make clobbered argument hard registers die. */
5993 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5994 if (regno >= FIRST_PSEUDO_REGISTER)
5995 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
5996 /* Mark each used value as live. */
5997 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5998 if (reg->type != OP_OUT
5999 && bitmap_bit_p (&check_only_regs, reg->regno))
6000 bitmap_set_bit (&live_regs, reg->regno);
6001 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6002 if (reg->type != OP_OUT
6003 && bitmap_bit_p (&check_only_regs, reg->regno))
6004 bitmap_set_bit (&live_regs, reg->regno);
6005 if (curr_id->arg_hard_regs != NULL)
6006 /* Make used argument hard registers live. */
6007 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6008 if (regno < FIRST_PSEUDO_REGISTER
6009 && bitmap_bit_p (&check_only_regs, regno))
6010 bitmap_set_bit (&live_regs, regno);
6011 /* It is quite important to remove dead move insns because it
6012 means removing dead store. We don't need to process them for
6013 constraints. */
6014 if (remove_p)
6016 if (lra_dump_file != NULL)
6018 fprintf (lra_dump_file, " Removing dead insn:\n ");
6019 dump_insn_slim (lra_dump_file, curr_insn);
6021 lra_set_insn_deleted (curr_insn);
6026 /* The structure describes info to do an inheritance for the current
6027 insn. We need to collect such info first before doing the
6028 transformations because the transformations change the insn
6029 internal representation. */
6030 struct to_inherit
6032 /* Original regno. */
6033 int regno;
6034 /* Subsequent insns which can inherit original reg value. */
6035 rtx insns;
6038 /* Array containing all info for doing inheritance from the current
6039 insn. */
6040 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
6042 /* Number elements in the previous array. */
6043 static int to_inherit_num;
6045 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6046 structure to_inherit. */
6047 static void
6048 add_to_inherit (int regno, rtx insns)
6050 int i;
6052 for (i = 0; i < to_inherit_num; i++)
6053 if (to_inherit[i].regno == regno)
6054 return;
6055 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
6056 to_inherit[to_inherit_num].regno = regno;
6057 to_inherit[to_inherit_num++].insns = insns;
6060 /* Return the last non-debug insn in basic block BB, or the block begin
6061 note if none. */
6062 static rtx_insn *
6063 get_last_insertion_point (basic_block bb)
6065 rtx_insn *insn;
6067 FOR_BB_INSNS_REVERSE (bb, insn)
6068 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
6069 return insn;
6070 gcc_unreachable ();
6073 /* Set up RES by registers living on edges FROM except the edge (FROM,
6074 TO) or by registers set up in a jump insn in BB FROM. */
6075 static void
6076 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
6078 rtx_insn *last;
6079 struct lra_insn_reg *reg;
6080 edge e;
6081 edge_iterator ei;
6083 lra_assert (to != NULL);
6084 bitmap_clear (res);
6085 FOR_EACH_EDGE (e, ei, from->succs)
6086 if (e->dest != to)
6087 bitmap_ior_into (res, df_get_live_in (e->dest));
6088 last = get_last_insertion_point (from);
6089 if (! JUMP_P (last))
6090 return;
6091 curr_id = lra_get_insn_recog_data (last);
6092 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6093 if (reg->type != OP_IN)
6094 bitmap_set_bit (res, reg->regno);
6097 /* Used as a temporary results of some bitmap calculations. */
6098 static bitmap_head temp_bitmap;
6100 /* We split for reloads of small class of hard regs. The following
6101 defines how many hard regs the class should have to be qualified as
6102 small. The code is mostly oriented to x86/x86-64 architecture
6103 where some insns need to use only specific register or pair of
6104 registers and these register can live in RTL explicitly, e.g. for
6105 parameter passing. */
6106 static const int max_small_class_regs_num = 2;
6108 /* Do inheritance/split transformations in EBB starting with HEAD and
6109 finishing on TAIL. We process EBB insns in the reverse order.
6110 Return true if we did any inheritance/split transformation in the
6111 EBB.
6113 We should avoid excessive splitting which results in worse code
6114 because of inaccurate cost calculations for spilling new split
6115 pseudos in such case. To achieve this we do splitting only if
6116 register pressure is high in given basic block and there are reload
6117 pseudos requiring hard registers. We could do more register
6118 pressure calculations at any given program point to avoid necessary
6119 splitting even more but it is to expensive and the current approach
6120 works well enough. */
6121 static bool
6122 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6124 int i, src_regno, dst_regno, nregs;
6125 bool change_p, succ_p, update_reloads_num_p;
6126 rtx_insn *prev_insn, *last_insn;
6127 rtx next_usage_insns, curr_set;
6128 enum reg_class cl;
6129 struct lra_insn_reg *reg;
6130 basic_block last_processed_bb, curr_bb = NULL;
6131 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6132 bitmap to_process;
6133 unsigned int j;
6134 bitmap_iterator bi;
6135 bool head_p, after_p;
6137 change_p = false;
6138 curr_usage_insns_check++;
6139 clear_invariants ();
6140 reloads_num = calls_num = 0;
6141 bitmap_clear (&check_only_regs);
6142 bitmap_clear (&invalid_invariant_regs);
6143 last_processed_bb = NULL;
6144 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6145 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
6146 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
6147 /* We don't process new insns generated in the loop. */
6148 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6150 prev_insn = PREV_INSN (curr_insn);
6151 if (BLOCK_FOR_INSN (curr_insn) != NULL)
6152 curr_bb = BLOCK_FOR_INSN (curr_insn);
6153 if (last_processed_bb != curr_bb)
6155 /* We are at the end of BB. Add qualified living
6156 pseudos for potential splitting. */
6157 to_process = df_get_live_out (curr_bb);
6158 if (last_processed_bb != NULL)
6160 /* We are somewhere in the middle of EBB. */
6161 get_live_on_other_edges (curr_bb, last_processed_bb,
6162 &temp_bitmap);
6163 to_process = &temp_bitmap;
6165 last_processed_bb = curr_bb;
6166 last_insn = get_last_insertion_point (curr_bb);
6167 after_p = (! JUMP_P (last_insn)
6168 && (! CALL_P (last_insn)
6169 || (find_reg_note (last_insn,
6170 REG_NORETURN, NULL_RTX) == NULL_RTX
6171 && ! SIBLING_CALL_P (last_insn))));
6172 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6173 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6175 if ((int) j >= lra_constraint_new_regno_start)
6176 break;
6177 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6179 if (j < FIRST_PSEUDO_REGISTER)
6180 SET_HARD_REG_BIT (live_hard_regs, j);
6181 else
6182 add_to_hard_reg_set (&live_hard_regs,
6183 PSEUDO_REGNO_MODE (j),
6184 reg_renumber[j]);
6185 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6189 src_regno = dst_regno = -1;
6190 curr_set = single_set (curr_insn);
6191 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6192 dst_regno = REGNO (SET_DEST (curr_set));
6193 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6194 src_regno = REGNO (SET_SRC (curr_set));
6195 update_reloads_num_p = true;
6196 if (src_regno < lra_constraint_new_regno_start
6197 && src_regno >= FIRST_PSEUDO_REGISTER
6198 && reg_renumber[src_regno] < 0
6199 && dst_regno >= lra_constraint_new_regno_start
6200 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6202 /* 'reload_pseudo <- original_pseudo'. */
6203 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6204 reloads_num++;
6205 update_reloads_num_p = false;
6206 succ_p = false;
6207 if (usage_insns[src_regno].check == curr_usage_insns_check
6208 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6209 succ_p = inherit_reload_reg (false, src_regno, cl,
6210 curr_insn, next_usage_insns);
6211 if (succ_p)
6212 change_p = true;
6213 else
6214 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6215 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6216 IOR_HARD_REG_SET (potential_reload_hard_regs,
6217 reg_class_contents[cl]);
6219 else if (src_regno < 0
6220 && dst_regno >= lra_constraint_new_regno_start
6221 && invariant_p (SET_SRC (curr_set))
6222 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6223 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6224 && ! bitmap_bit_p (&invalid_invariant_regs,
6225 ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6227 /* 'reload_pseudo <- invariant'. */
6228 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6229 reloads_num++;
6230 update_reloads_num_p = false;
6231 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6232 change_p = true;
6233 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6234 IOR_HARD_REG_SET (potential_reload_hard_regs,
6235 reg_class_contents[cl]);
6237 else if (src_regno >= lra_constraint_new_regno_start
6238 && dst_regno < lra_constraint_new_regno_start
6239 && dst_regno >= FIRST_PSEUDO_REGISTER
6240 && reg_renumber[dst_regno] < 0
6241 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6242 && usage_insns[dst_regno].check == curr_usage_insns_check
6243 && (next_usage_insns
6244 = usage_insns[dst_regno].insns) != NULL_RTX)
6246 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6247 reloads_num++;
6248 update_reloads_num_p = false;
6249 /* 'original_pseudo <- reload_pseudo'. */
6250 if (! JUMP_P (curr_insn)
6251 && inherit_reload_reg (true, dst_regno, cl,
6252 curr_insn, next_usage_insns))
6253 change_p = true;
6254 /* Invalidate. */
6255 usage_insns[dst_regno].check = 0;
6256 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6257 IOR_HARD_REG_SET (potential_reload_hard_regs,
6258 reg_class_contents[cl]);
6260 else if (INSN_P (curr_insn))
6262 int iter;
6263 int max_uid = get_max_uid ();
6265 curr_id = lra_get_insn_recog_data (curr_insn);
6266 curr_static_id = curr_id->insn_static_data;
6267 to_inherit_num = 0;
6268 /* Process insn definitions. */
6269 for (iter = 0; iter < 2; iter++)
6270 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6271 reg != NULL;
6272 reg = reg->next)
6273 if (reg->type != OP_IN
6274 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6276 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6277 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6278 && usage_insns[dst_regno].check == curr_usage_insns_check
6279 && (next_usage_insns
6280 = usage_insns[dst_regno].insns) != NULL_RTX)
6282 struct lra_insn_reg *r;
6284 for (r = curr_id->regs; r != NULL; r = r->next)
6285 if (r->type != OP_OUT && r->regno == dst_regno)
6286 break;
6287 /* Don't do inheritance if the pseudo is also
6288 used in the insn. */
6289 if (r == NULL)
6290 /* We can not do inheritance right now
6291 because the current insn reg info (chain
6292 regs) can change after that. */
6293 add_to_inherit (dst_regno, next_usage_insns);
6295 /* We can not process one reg twice here because of
6296 usage_insns invalidation. */
6297 if ((dst_regno < FIRST_PSEUDO_REGISTER
6298 || reg_renumber[dst_regno] >= 0)
6299 && ! reg->subreg_p && reg->type != OP_IN)
6301 HARD_REG_SET s;
6303 if (split_if_necessary (dst_regno, reg->biggest_mode,
6304 potential_reload_hard_regs,
6305 false, curr_insn, max_uid))
6306 change_p = true;
6307 CLEAR_HARD_REG_SET (s);
6308 if (dst_regno < FIRST_PSEUDO_REGISTER)
6309 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6310 else
6311 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6312 reg_renumber[dst_regno]);
6313 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
6315 /* We should invalidate potential inheritance or
6316 splitting for the current insn usages to the next
6317 usage insns (see code below) as the output pseudo
6318 prevents this. */
6319 if ((dst_regno >= FIRST_PSEUDO_REGISTER
6320 && reg_renumber[dst_regno] < 0)
6321 || (reg->type == OP_OUT && ! reg->subreg_p
6322 && (dst_regno < FIRST_PSEUDO_REGISTER
6323 || reg_renumber[dst_regno] >= 0)))
6325 /* Invalidate and mark definitions. */
6326 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6327 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6328 else
6330 nregs = hard_regno_nregs (dst_regno,
6331 reg->biggest_mode);
6332 for (i = 0; i < nregs; i++)
6333 usage_insns[dst_regno + i].check
6334 = -(int) INSN_UID (curr_insn);
6338 /* Process clobbered call regs. */
6339 if (curr_id->arg_hard_regs != NULL)
6340 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6341 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6342 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6343 = -(int) INSN_UID (curr_insn);
6344 if (! JUMP_P (curr_insn))
6345 for (i = 0; i < to_inherit_num; i++)
6346 if (inherit_reload_reg (true, to_inherit[i].regno,
6347 ALL_REGS, curr_insn,
6348 to_inherit[i].insns))
6349 change_p = true;
6350 if (CALL_P (curr_insn))
6352 rtx cheap, pat, dest;
6353 rtx_insn *restore;
6354 int regno, hard_regno;
6356 calls_num++;
6357 if ((cheap = find_reg_note (curr_insn,
6358 REG_RETURNED, NULL_RTX)) != NULL_RTX
6359 && ((cheap = XEXP (cheap, 0)), true)
6360 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6361 && (hard_regno = reg_renumber[regno]) >= 0
6362 && usage_insns[regno].check == curr_usage_insns_check
6363 /* If there are pending saves/restores, the
6364 optimization is not worth. */
6365 && usage_insns[regno].calls_num == calls_num - 1
6366 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
6368 /* Restore the pseudo from the call result as
6369 REG_RETURNED note says that the pseudo value is
6370 in the call result and the pseudo is an argument
6371 of the call. */
6372 pat = PATTERN (curr_insn);
6373 if (GET_CODE (pat) == PARALLEL)
6374 pat = XVECEXP (pat, 0, 0);
6375 dest = SET_DEST (pat);
6376 /* For multiple return values dest is PARALLEL.
6377 Currently we handle only single return value case. */
6378 if (REG_P (dest))
6380 start_sequence ();
6381 emit_move_insn (cheap, copy_rtx (dest));
6382 restore = get_insns ();
6383 end_sequence ();
6384 lra_process_new_insns (curr_insn, NULL, restore,
6385 "Inserting call parameter restore");
6386 /* We don't need to save/restore of the pseudo from
6387 this call. */
6388 usage_insns[regno].calls_num = calls_num;
6389 bitmap_set_bit (&check_only_regs, regno);
6393 to_inherit_num = 0;
6394 /* Process insn usages. */
6395 for (iter = 0; iter < 2; iter++)
6396 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6397 reg != NULL;
6398 reg = reg->next)
6399 if ((reg->type != OP_OUT
6400 || (reg->type == OP_OUT && reg->subreg_p))
6401 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6403 if (src_regno >= FIRST_PSEUDO_REGISTER
6404 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6406 if (usage_insns[src_regno].check == curr_usage_insns_check
6407 && (next_usage_insns
6408 = usage_insns[src_regno].insns) != NULL_RTX
6409 && NONDEBUG_INSN_P (curr_insn))
6410 add_to_inherit (src_regno, next_usage_insns);
6411 else if (usage_insns[src_regno].check
6412 != -(int) INSN_UID (curr_insn))
6413 /* Add usages but only if the reg is not set up
6414 in the same insn. */
6415 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6417 else if (src_regno < FIRST_PSEUDO_REGISTER
6418 || reg_renumber[src_regno] >= 0)
6420 bool before_p;
6421 rtx_insn *use_insn = curr_insn;
6423 before_p = (JUMP_P (curr_insn)
6424 || (CALL_P (curr_insn) && reg->type == OP_IN));
6425 if (NONDEBUG_INSN_P (curr_insn)
6426 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
6427 && split_if_necessary (src_regno, reg->biggest_mode,
6428 potential_reload_hard_regs,
6429 before_p, curr_insn, max_uid))
6431 if (reg->subreg_p)
6432 lra_risky_transformations_p = true;
6433 change_p = true;
6434 /* Invalidate. */
6435 usage_insns[src_regno].check = 0;
6436 if (before_p)
6437 use_insn = PREV_INSN (curr_insn);
6439 if (NONDEBUG_INSN_P (curr_insn))
6441 if (src_regno < FIRST_PSEUDO_REGISTER)
6442 add_to_hard_reg_set (&live_hard_regs,
6443 reg->biggest_mode, src_regno);
6444 else
6445 add_to_hard_reg_set (&live_hard_regs,
6446 PSEUDO_REGNO_MODE (src_regno),
6447 reg_renumber[src_regno]);
6449 if (src_regno >= FIRST_PSEUDO_REGISTER)
6450 add_next_usage_insn (src_regno, use_insn, reloads_num);
6451 else
6453 for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++)
6454 add_next_usage_insn (src_regno + i, use_insn, reloads_num);
6458 /* Process used call regs. */
6459 if (curr_id->arg_hard_regs != NULL)
6460 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6461 if (src_regno < FIRST_PSEUDO_REGISTER)
6463 SET_HARD_REG_BIT (live_hard_regs, src_regno);
6464 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6466 for (i = 0; i < to_inherit_num; i++)
6468 src_regno = to_inherit[i].regno;
6469 if (inherit_reload_reg (false, src_regno, ALL_REGS,
6470 curr_insn, to_inherit[i].insns))
6471 change_p = true;
6472 else
6473 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6476 if (update_reloads_num_p
6477 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
6479 int regno = -1;
6480 if ((REG_P (SET_DEST (curr_set))
6481 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
6482 && reg_renumber[regno] < 0
6483 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
6484 || (REG_P (SET_SRC (curr_set))
6485 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
6486 && reg_renumber[regno] < 0
6487 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
6489 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6490 reloads_num++;
6491 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6492 IOR_HARD_REG_SET (potential_reload_hard_regs,
6493 reg_class_contents[cl]);
6496 if (NONDEBUG_INSN_P (curr_insn))
6498 int regno;
6500 /* Invalidate invariants with changed regs. */
6501 curr_id = lra_get_insn_recog_data (curr_insn);
6502 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6503 if (reg->type != OP_IN)
6505 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6506 bitmap_set_bit (&invalid_invariant_regs,
6507 ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
6509 curr_static_id = curr_id->insn_static_data;
6510 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6511 if (reg->type != OP_IN)
6512 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6513 if (curr_id->arg_hard_regs != NULL)
6514 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6515 if (regno >= FIRST_PSEUDO_REGISTER)
6516 bitmap_set_bit (&invalid_invariant_regs,
6517 regno - FIRST_PSEUDO_REGISTER);
6519 /* We reached the start of the current basic block. */
6520 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
6521 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
6523 /* We reached the beginning of the current block -- do
6524 rest of spliting in the current BB. */
6525 to_process = df_get_live_in (curr_bb);
6526 if (BLOCK_FOR_INSN (head) != curr_bb)
6528 /* We are somewhere in the middle of EBB. */
6529 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
6530 curr_bb, &temp_bitmap);
6531 to_process = &temp_bitmap;
6533 head_p = true;
6534 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6536 if ((int) j >= lra_constraint_new_regno_start)
6537 break;
6538 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6539 && usage_insns[j].check == curr_usage_insns_check
6540 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
6542 if (need_for_split_p (potential_reload_hard_regs, j))
6544 if (lra_dump_file != NULL && head_p)
6546 fprintf (lra_dump_file,
6547 " ----------------------------------\n");
6548 head_p = false;
6550 if (split_reg (false, j, bb_note (curr_bb),
6551 next_usage_insns, NULL))
6552 change_p = true;
6554 usage_insns[j].check = 0;
6559 return change_p;
6562 /* This value affects EBB forming. If probability of edge from EBB to
6563 a BB is not greater than the following value, we don't add the BB
6564 to EBB. */
6565 #define EBB_PROBABILITY_CUTOFF \
6566 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6568 /* Current number of inheritance/split iteration. */
6569 int lra_inheritance_iter;
6571 /* Entry function for inheritance/split pass. */
6572 void
6573 lra_inheritance (void)
6575 int i;
6576 basic_block bb, start_bb;
6577 edge e;
6579 lra_inheritance_iter++;
6580 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6581 return;
6582 timevar_push (TV_LRA_INHERITANCE);
6583 if (lra_dump_file != NULL)
6584 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
6585 lra_inheritance_iter);
6586 curr_usage_insns_check = 0;
6587 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
6588 for (i = 0; i < lra_constraint_new_regno_start; i++)
6589 usage_insns[i].check = 0;
6590 bitmap_initialize (&check_only_regs, &reg_obstack);
6591 bitmap_initialize (&invalid_invariant_regs, &reg_obstack);
6592 bitmap_initialize (&live_regs, &reg_obstack);
6593 bitmap_initialize (&temp_bitmap, &reg_obstack);
6594 bitmap_initialize (&ebb_global_regs, &reg_obstack);
6595 FOR_EACH_BB_FN (bb, cfun)
6597 start_bb = bb;
6598 if (lra_dump_file != NULL)
6599 fprintf (lra_dump_file, "EBB");
6600 /* Form a EBB starting with BB. */
6601 bitmap_clear (&ebb_global_regs);
6602 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
6603 for (;;)
6605 if (lra_dump_file != NULL)
6606 fprintf (lra_dump_file, " %d", bb->index);
6607 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
6608 || LABEL_P (BB_HEAD (bb->next_bb)))
6609 break;
6610 e = find_fallthru_edge (bb->succs);
6611 if (! e)
6612 break;
6613 if (e->probability.initialized_p ()
6614 && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
6615 break;
6616 bb = bb->next_bb;
6618 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
6619 if (lra_dump_file != NULL)
6620 fprintf (lra_dump_file, "\n");
6621 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
6622 /* Remember that the EBB head and tail can change in
6623 inherit_in_ebb. */
6624 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
6626 bitmap_clear (&ebb_global_regs);
6627 bitmap_clear (&temp_bitmap);
6628 bitmap_clear (&live_regs);
6629 bitmap_clear (&invalid_invariant_regs);
6630 bitmap_clear (&check_only_regs);
6631 free (usage_insns);
6633 timevar_pop (TV_LRA_INHERITANCE);
6638 /* This page contains code to undo failed inheritance/split
6639 transformations. */
6641 /* Current number of iteration undoing inheritance/split. */
6642 int lra_undo_inheritance_iter;
6644 /* Fix BB live info LIVE after removing pseudos created on pass doing
6645 inheritance/split which are REMOVED_PSEUDOS. */
6646 static void
6647 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
6649 unsigned int regno;
6650 bitmap_iterator bi;
6652 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
6653 if (bitmap_clear_bit (live, regno)
6654 && REG_P (lra_reg_info[regno].restore_rtx))
6655 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
6658 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6659 number. */
6660 static int
6661 get_regno (rtx reg)
6663 if (GET_CODE (reg) == SUBREG)
6664 reg = SUBREG_REG (reg);
6665 if (REG_P (reg))
6666 return REGNO (reg);
6667 return -1;
6670 /* Delete a move INSN with destination reg DREGNO and a previous
6671 clobber insn with the same regno. The inheritance/split code can
6672 generate moves with preceding clobber and when we delete such moves
6673 we should delete the clobber insn too to keep the correct life
6674 info. */
6675 static void
6676 delete_move_and_clobber (rtx_insn *insn, int dregno)
6678 rtx_insn *prev_insn = PREV_INSN (insn);
6680 lra_set_insn_deleted (insn);
6681 lra_assert (dregno >= 0);
6682 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
6683 && GET_CODE (PATTERN (prev_insn)) == CLOBBER
6684 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
6685 lra_set_insn_deleted (prev_insn);
6688 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6689 return true if we did any change. The undo transformations for
6690 inheritance looks like
6691 i <- i2
6692 p <- i => p <- i2
6693 or removing
6694 p <- i, i <- p, and i <- i3
6695 where p is original pseudo from which inheritance pseudo i was
6696 created, i and i3 are removed inheritance pseudos, i2 is another
6697 not removed inheritance pseudo. All split pseudos or other
6698 occurrences of removed inheritance pseudos are changed on the
6699 corresponding original pseudos.
6701 The function also schedules insns changed and created during
6702 inheritance/split pass for processing by the subsequent constraint
6703 pass. */
6704 static bool
6705 remove_inheritance_pseudos (bitmap remove_pseudos)
6707 basic_block bb;
6708 int regno, sregno, prev_sregno, dregno;
6709 rtx restore_rtx;
6710 rtx set, prev_set;
6711 rtx_insn *prev_insn;
6712 bool change_p, done_p;
6714 change_p = ! bitmap_empty_p (remove_pseudos);
6715 /* We can not finish the function right away if CHANGE_P is true
6716 because we need to marks insns affected by previous
6717 inheritance/split pass for processing by the subsequent
6718 constraint pass. */
6719 FOR_EACH_BB_FN (bb, cfun)
6721 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
6722 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
6723 FOR_BB_INSNS_REVERSE (bb, curr_insn)
6725 if (! INSN_P (curr_insn))
6726 continue;
6727 done_p = false;
6728 sregno = dregno = -1;
6729 if (change_p && NONDEBUG_INSN_P (curr_insn)
6730 && (set = single_set (curr_insn)) != NULL_RTX)
6732 dregno = get_regno (SET_DEST (set));
6733 sregno = get_regno (SET_SRC (set));
6736 if (sregno >= 0 && dregno >= 0)
6738 if (bitmap_bit_p (remove_pseudos, dregno)
6739 && ! REG_P (lra_reg_info[dregno].restore_rtx))
6741 /* invariant inheritance pseudo <- original pseudo */
6742 if (lra_dump_file != NULL)
6744 fprintf (lra_dump_file, " Removing invariant inheritance:\n");
6745 dump_insn_slim (lra_dump_file, curr_insn);
6746 fprintf (lra_dump_file, "\n");
6748 delete_move_and_clobber (curr_insn, dregno);
6749 done_p = true;
6751 else if (bitmap_bit_p (remove_pseudos, sregno)
6752 && ! REG_P (lra_reg_info[sregno].restore_rtx))
6754 /* reload pseudo <- invariant inheritance pseudo */
6755 start_sequence ();
6756 /* We can not just change the source. It might be
6757 an insn different from the move. */
6758 emit_insn (lra_reg_info[sregno].restore_rtx);
6759 rtx_insn *new_insns = get_insns ();
6760 end_sequence ();
6761 lra_assert (single_set (new_insns) != NULL
6762 && SET_DEST (set) == SET_DEST (single_set (new_insns)));
6763 lra_process_new_insns (curr_insn, NULL, new_insns,
6764 "Changing reload<-invariant inheritance");
6765 delete_move_and_clobber (curr_insn, dregno);
6766 done_p = true;
6768 else if ((bitmap_bit_p (remove_pseudos, sregno)
6769 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
6770 || (bitmap_bit_p (remove_pseudos, dregno)
6771 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6772 && (get_regno (lra_reg_info[sregno].restore_rtx)
6773 == get_regno (lra_reg_info[dregno].restore_rtx)))))
6774 || (bitmap_bit_p (remove_pseudos, dregno)
6775 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
6776 /* One of the following cases:
6777 original <- removed inheritance pseudo
6778 removed inherit pseudo <- another removed inherit pseudo
6779 removed inherit pseudo <- original pseudo
6781 removed_split_pseudo <- original_reg
6782 original_reg <- removed_split_pseudo */
6784 if (lra_dump_file != NULL)
6786 fprintf (lra_dump_file, " Removing %s:\n",
6787 bitmap_bit_p (&lra_split_regs, sregno)
6788 || bitmap_bit_p (&lra_split_regs, dregno)
6789 ? "split" : "inheritance");
6790 dump_insn_slim (lra_dump_file, curr_insn);
6792 delete_move_and_clobber (curr_insn, dregno);
6793 done_p = true;
6795 else if (bitmap_bit_p (remove_pseudos, sregno)
6796 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6798 /* Search the following pattern:
6799 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6800 original_pseudo <- inherit_or_split_pseudo1
6801 where the 2nd insn is the current insn and
6802 inherit_or_split_pseudo2 is not removed. If it is found,
6803 change the current insn onto:
6804 original_pseudo <- inherit_or_split_pseudo2. */
6805 for (prev_insn = PREV_INSN (curr_insn);
6806 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6807 prev_insn = PREV_INSN (prev_insn))
6809 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6810 && (prev_set = single_set (prev_insn)) != NULL_RTX
6811 /* There should be no subregs in insn we are
6812 searching because only the original reg might
6813 be in subreg when we changed the mode of
6814 load/store for splitting. */
6815 && REG_P (SET_DEST (prev_set))
6816 && REG_P (SET_SRC (prev_set))
6817 && (int) REGNO (SET_DEST (prev_set)) == sregno
6818 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6819 >= FIRST_PSEUDO_REGISTER)
6820 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
6822 /* As we consider chain of inheritance or
6823 splitting described in above comment we should
6824 check that sregno and prev_sregno were
6825 inheritance/split pseudos created from the
6826 same original regno. */
6827 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6828 && (get_regno (lra_reg_info[sregno].restore_rtx)
6829 == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
6830 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6832 lra_assert (GET_MODE (SET_SRC (prev_set))
6833 == GET_MODE (regno_reg_rtx[sregno]));
6834 /* Although we have a single set, the insn can
6835 contain more one sregno register occurrence
6836 as a source. Change all occurrences. */
6837 lra_substitute_pseudo_within_insn (curr_insn, sregno,
6838 SET_SRC (prev_set),
6839 false);
6840 /* As we are finishing with processing the insn
6841 here, check the destination too as it might
6842 inheritance pseudo for another pseudo. */
6843 if (bitmap_bit_p (remove_pseudos, dregno)
6844 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
6845 && (restore_rtx
6846 = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
6848 if (GET_CODE (SET_DEST (set)) == SUBREG)
6849 SUBREG_REG (SET_DEST (set)) = restore_rtx;
6850 else
6851 SET_DEST (set) = restore_rtx;
6853 lra_push_insn_and_update_insn_regno_info (curr_insn);
6854 lra_set_used_insn_alternative_by_uid
6855 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6856 done_p = true;
6857 if (lra_dump_file != NULL)
6859 fprintf (lra_dump_file, " Change reload insn:\n");
6860 dump_insn_slim (lra_dump_file, curr_insn);
6865 if (! done_p)
6867 struct lra_insn_reg *reg;
6868 bool restored_regs_p = false;
6869 bool kept_regs_p = false;
6871 curr_id = lra_get_insn_recog_data (curr_insn);
6872 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6874 regno = reg->regno;
6875 restore_rtx = lra_reg_info[regno].restore_rtx;
6876 if (restore_rtx != NULL_RTX)
6878 if (change_p && bitmap_bit_p (remove_pseudos, regno))
6880 lra_substitute_pseudo_within_insn
6881 (curr_insn, regno, restore_rtx, false);
6882 restored_regs_p = true;
6884 else
6885 kept_regs_p = true;
6888 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
6890 /* The instruction has changed since the previous
6891 constraints pass. */
6892 lra_push_insn_and_update_insn_regno_info (curr_insn);
6893 lra_set_used_insn_alternative_by_uid
6894 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6896 else if (restored_regs_p)
6897 /* The instruction has been restored to the form that
6898 it had during the previous constraints pass. */
6899 lra_update_insn_regno_info (curr_insn);
6900 if (restored_regs_p && lra_dump_file != NULL)
6902 fprintf (lra_dump_file, " Insn after restoring regs:\n");
6903 dump_insn_slim (lra_dump_file, curr_insn);
6908 return change_p;
6911 /* If optional reload pseudos failed to get a hard register or was not
6912 inherited, it is better to remove optional reloads. We do this
6913 transformation after undoing inheritance to figure out necessity to
6914 remove optional reloads easier. Return true if we do any
6915 change. */
6916 static bool
6917 undo_optional_reloads (void)
6919 bool change_p, keep_p;
6920 unsigned int regno, uid;
6921 bitmap_iterator bi, bi2;
6922 rtx_insn *insn;
6923 rtx set, src, dest;
6924 auto_bitmap removed_optional_reload_pseudos (&reg_obstack);
6926 bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
6927 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6929 keep_p = false;
6930 /* Keep optional reloads from previous subpasses. */
6931 if (lra_reg_info[regno].restore_rtx == NULL_RTX
6932 /* If the original pseudo changed its allocation, just
6933 removing the optional pseudo is dangerous as the original
6934 pseudo will have longer live range. */
6935 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
6936 keep_p = true;
6937 else if (reg_renumber[regno] >= 0)
6938 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6940 insn = lra_insn_recog_data[uid]->insn;
6941 if ((set = single_set (insn)) == NULL_RTX)
6942 continue;
6943 src = SET_SRC (set);
6944 dest = SET_DEST (set);
6945 if (! REG_P (src) || ! REG_P (dest))
6946 continue;
6947 if (REGNO (dest) == regno
6948 /* Ignore insn for optional reloads itself. */
6949 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src)
6950 /* Check only inheritance on last inheritance pass. */
6951 && (int) REGNO (src) >= new_regno_start
6952 /* Check that the optional reload was inherited. */
6953 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6955 keep_p = true;
6956 break;
6959 if (keep_p)
6961 bitmap_clear_bit (removed_optional_reload_pseudos, regno);
6962 if (lra_dump_file != NULL)
6963 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6966 change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
6967 auto_bitmap insn_bitmap (&reg_obstack);
6968 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
6970 if (lra_dump_file != NULL)
6971 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6972 bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6973 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
6975 insn = lra_insn_recog_data[uid]->insn;
6976 if ((set = single_set (insn)) != NULL_RTX)
6978 src = SET_SRC (set);
6979 dest = SET_DEST (set);
6980 if (REG_P (src) && REG_P (dest)
6981 && ((REGNO (src) == regno
6982 && (REGNO (lra_reg_info[regno].restore_rtx)
6983 == REGNO (dest)))
6984 || (REGNO (dest) == regno
6985 && (REGNO (lra_reg_info[regno].restore_rtx)
6986 == REGNO (src)))))
6988 if (lra_dump_file != NULL)
6990 fprintf (lra_dump_file, " Deleting move %u\n",
6991 INSN_UID (insn));
6992 dump_insn_slim (lra_dump_file, insn);
6994 delete_move_and_clobber (insn, REGNO (dest));
6995 continue;
6997 /* We should not worry about generation memory-memory
6998 moves here as if the corresponding inheritance did
6999 not work (inheritance pseudo did not get a hard reg),
7000 we remove the inheritance pseudo and the optional
7001 reload. */
7003 lra_substitute_pseudo_within_insn
7004 (insn, regno, lra_reg_info[regno].restore_rtx, false);
7005 lra_update_insn_regno_info (insn);
7006 if (lra_dump_file != NULL)
7008 fprintf (lra_dump_file,
7009 " Restoring original insn:\n");
7010 dump_insn_slim (lra_dump_file, insn);
7014 /* Clear restore_regnos. */
7015 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7016 lra_reg_info[regno].restore_rtx = NULL_RTX;
7017 return change_p;
7020 /* Entry function for undoing inheritance/split transformation. Return true
7021 if we did any RTL change in this pass. */
7022 bool
7023 lra_undo_inheritance (void)
7025 unsigned int regno;
7026 int hard_regno;
7027 int n_all_inherit, n_inherit, n_all_split, n_split;
7028 rtx restore_rtx;
7029 bitmap_iterator bi;
7030 bool change_p;
7032 lra_undo_inheritance_iter++;
7033 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7034 return false;
7035 if (lra_dump_file != NULL)
7036 fprintf (lra_dump_file,
7037 "\n********** Undoing inheritance #%d: **********\n\n",
7038 lra_undo_inheritance_iter);
7039 auto_bitmap remove_pseudos (&reg_obstack);
7040 n_inherit = n_all_inherit = 0;
7041 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7042 if (lra_reg_info[regno].restore_rtx != NULL_RTX)
7044 n_all_inherit++;
7045 if (reg_renumber[regno] < 0
7046 /* If the original pseudo changed its allocation, just
7047 removing inheritance is dangerous as for changing
7048 allocation we used shorter live-ranges. */
7049 && (! REG_P (lra_reg_info[regno].restore_rtx)
7050 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
7051 bitmap_set_bit (remove_pseudos, regno);
7052 else
7053 n_inherit++;
7055 if (lra_dump_file != NULL && n_all_inherit != 0)
7056 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
7057 n_inherit, n_all_inherit,
7058 (double) n_inherit / n_all_inherit * 100);
7059 n_split = n_all_split = 0;
7060 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7061 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
7063 int restore_regno = REGNO (restore_rtx);
7065 n_all_split++;
7066 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
7067 ? reg_renumber[restore_regno] : restore_regno);
7068 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
7069 bitmap_set_bit (remove_pseudos, regno);
7070 else
7072 n_split++;
7073 if (lra_dump_file != NULL)
7074 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
7075 regno, restore_regno);
7078 if (lra_dump_file != NULL && n_all_split != 0)
7079 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
7080 n_split, n_all_split,
7081 (double) n_split / n_all_split * 100);
7082 change_p = remove_inheritance_pseudos (remove_pseudos);
7083 /* Clear restore_regnos. */
7084 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7085 lra_reg_info[regno].restore_rtx = NULL_RTX;
7086 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7087 lra_reg_info[regno].restore_rtx = NULL_RTX;
7088 change_p = undo_optional_reloads () || change_p;
7089 return change_p;