1 /* Change pseudos by memory.
2 Copyright (C) 2010-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for a pass to change spilled pseudos into
25 The pass creates necessary stack slots and assigns spilled pseudos
26 to the stack slots in following way:
28 for all spilled pseudos P most frequently used first do
29 for all stack slots S do
30 if P doesn't conflict with pseudos assigned to S then
31 assign S to P and goto to the next pseudo process
34 create new stack slot S and assign P to S
37 The actual algorithm is bit more complicated because of different
40 After that the code changes spilled pseudos (except ones created
41 from scratches) by corresponding stack slot memory in RTL.
43 If at least one stack slot was created, we need to run more passes
44 because we have new addresses which should be checked and because
45 the old address displacements might change and address constraints
46 (or insn memory constraints) might not be satisfied any more.
48 For some targets, the pass can spill some pseudos into hard
49 registers of different class (usually into vector registers)
50 instead of spilling them into memory if it is possible and
51 profitable. Spilling GENERAL_REGS pseudo into SSE registers for
52 Intel Corei7 is an example of such optimization. And this is
53 actually recommended by Intel optimization guide.
55 The file also contains code for final change of pseudos on hard
56 regs correspondingly assigned to them. */
60 #include "coretypes.h"
65 #include "insn-config.h"
76 /* Max regno at the start of the pass. */
79 /* Map spilled regno -> hard regno used instead of memory for
81 static rtx
*spill_hard_reg
;
83 /* The structure describes stack slot of a spilled pseudo. */
86 /* Number (0, 1, ...) of the stack slot to which given pseudo
89 /* First or next slot with the same slot number. */
90 struct pseudo_slot
*next
, *first
;
91 /* Memory representing the spilled pseudo. */
95 /* The stack slots for each spilled pseudo. Indexed by regnos. */
96 static struct pseudo_slot
*pseudo_slots
;
98 /* The structure describes a register or a stack slot which can be
99 used for several spilled pseudos. */
103 /* First pseudo with given stack slot. */
105 /* Hard reg into which the slot pseudos are spilled. The value is
106 negative for pseudos spilled into memory. */
108 /* Maximum alignment required by all users of the slot. */
110 /* Maximum size required by all users of the slot. */
112 /* Memory representing the all stack slot. It can be different from
113 memory representing a pseudo belonging to give stack slot because
114 pseudo can be placed in a part of the corresponding stack slot.
115 The value is NULL for pseudos spilled into a hard reg. */
117 /* Combined live ranges of all pseudos belonging to given slot. It
118 is used to figure out that a new spilled pseudo can use given
120 lra_live_range_t live_ranges
;
123 /* Array containing info about the stack slots. The array element is
124 indexed by the stack slot number in the range [0..slots_num). */
125 static class slot
*slots
;
126 /* The number of the stack slots currently existing. */
127 static int slots_num
;
129 /* Set up memory of the spilled pseudo I. The function can allocate
130 the corresponding stack slot if it is not done yet. */
132 assign_mem_slot (int i
)
135 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
136 poly_int64 inherent_size
= PSEUDO_REGNO_BYTES (i
);
137 machine_mode wider_mode
138 = wider_subreg_mode (mode
, lra_reg_info
[i
].biggest_mode
);
139 poly_int64 total_size
= GET_MODE_SIZE (wider_mode
);
140 poly_int64 adjust
= 0;
142 lra_assert (regno_reg_rtx
[i
] != NULL_RTX
&& REG_P (regno_reg_rtx
[i
])
143 && lra_reg_info
[i
].nrefs
!= 0 && reg_renumber
[i
] < 0);
145 unsigned int slot_num
= pseudo_slots
[i
].slot_num
;
146 x
= slots
[slot_num
].mem
;
149 x
= assign_stack_local (BLKmode
, slots
[slot_num
].size
,
150 slots
[slot_num
].align
);
151 slots
[slot_num
].mem
= x
;
154 /* On a big endian machine, the "address" of the slot is the address
155 of the low part that fits its inherent mode. */
156 adjust
+= subreg_size_lowpart_offset (inherent_size
, total_size
);
157 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
159 /* Set all of the memory attributes as appropriate for a spill. */
160 set_mem_attrs_for_spill (x
);
161 pseudo_slots
[i
].mem
= x
;
164 /* Sort pseudos according their usage frequencies. */
166 regno_freq_compare (const void *v1p
, const void *v2p
)
168 const int regno1
= *(const int *) v1p
;
169 const int regno2
= *(const int *) v2p
;
172 if ((diff
= lra_reg_info
[regno2
].freq
- lra_reg_info
[regno1
].freq
) != 0)
174 return regno1
- regno2
;
177 /* Sort pseudos according to their slots, putting the slots in the order
178 that they should be allocated.
180 First prefer to group slots with variable sizes together and slots
181 with constant sizes together, since that usually makes them easier
182 to address from a common anchor point. E.g. loads of polynomial-sized
183 registers tend to take polynomial offsets while loads of constant-sized
184 registers tend to take constant (non-polynomial) offsets.
186 Next, slots with lower numbers have the highest priority and should
187 get the smallest displacement from the stack or frame pointer
188 (whichever is being used).
190 The first allocated slot is always closest to the frame pointer,
191 so prefer lower slot numbers when frame_pointer_needed. If the stack
192 and frame grow in the same direction, then the first allocated slot is
193 always closest to the initial stack pointer and furthest away from the
194 final stack pointer, so allocate higher numbers first when using the
195 stack pointer in that case. The reverse is true if the stack and
196 frame grow in opposite directions. */
198 pseudo_reg_slot_compare (const void *v1p
, const void *v2p
)
200 const int regno1
= *(const int *) v1p
;
201 const int regno2
= *(const int *) v2p
;
202 int diff
, slot_num1
, slot_num2
;
204 slot_num1
= pseudo_slots
[regno1
].slot_num
;
205 slot_num2
= pseudo_slots
[regno2
].slot_num
;
206 diff
= (int (slots
[slot_num1
].size
.is_constant ())
207 - int (slots
[slot_num2
].size
.is_constant ()));
210 if ((diff
= slot_num1
- slot_num2
) != 0)
211 return (frame_pointer_needed
212 || (!FRAME_GROWS_DOWNWARD
) == STACK_GROWS_DOWNWARD
? diff
: -diff
);
213 poly_int64 total_size1
= GET_MODE_SIZE (lra_reg_info
[regno1
].biggest_mode
);
214 poly_int64 total_size2
= GET_MODE_SIZE (lra_reg_info
[regno2
].biggest_mode
);
215 if ((diff
= compare_sizes_for_sort (total_size2
, total_size1
)) != 0)
217 return regno1
- regno2
;
220 /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is
221 sorted in order of highest frequency first. Put the pseudos which
222 did not get a spill hard register at the beginning of array
223 PSEUDO_REGNOS. Return the number of such pseudos. */
225 assign_spill_hard_regs (int *pseudo_regnos
, int n
)
227 int i
, k
, p
, regno
, res
, spill_class_size
, hard_regno
, nr
;
228 enum reg_class rclass
, spill_class
;
234 HARD_REG_SET conflict_hard_regs
;
235 bitmap setjump_crosses
= regstat_get_setjmp_crosses ();
236 /* Hard registers which cannot be used for any purpose at given
237 program point because they are unallocatable or already allocated
238 for other pseudos. */
239 HARD_REG_SET
*reserved_hard_regs
;
241 if (! lra_reg_spill_p
)
243 /* Set up reserved hard regs for every program point. */
244 reserved_hard_regs
= XNEWVEC (HARD_REG_SET
, lra_live_max_point
);
245 for (p
= 0; p
< lra_live_max_point
; p
++)
246 COPY_HARD_REG_SET (reserved_hard_regs
[p
], lra_no_alloc_regs
);
247 for (i
= FIRST_PSEUDO_REGISTER
; i
< regs_num
; i
++)
248 if (lra_reg_info
[i
].nrefs
!= 0
249 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
250 for (r
= lra_reg_info
[i
].live_ranges
; r
!= NULL
; r
= r
->next
)
251 for (p
= r
->start
; p
<= r
->finish
; p
++)
252 add_to_hard_reg_set (&reserved_hard_regs
[p
],
253 lra_reg_info
[i
].biggest_mode
, hard_regno
);
254 auto_bitmap
ok_insn_bitmap (®_obstack
);
255 FOR_EACH_BB_FN (bb
, cfun
)
256 FOR_BB_INSNS (bb
, insn
)
257 if (DEBUG_INSN_P (insn
)
258 || ((set
= single_set (insn
)) != NULL_RTX
259 && REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))))
260 bitmap_set_bit (ok_insn_bitmap
, INSN_UID (insn
));
261 for (res
= i
= 0; i
< n
; i
++)
263 regno
= pseudo_regnos
[i
];
264 rclass
= lra_get_allocno_class (regno
);
265 if (bitmap_bit_p (setjump_crosses
, regno
)
268 targetm
.spill_class ((reg_class_t
) rclass
,
269 PSEUDO_REGNO_MODE (regno
)))) == NO_REGS
270 || bitmap_intersect_compl_p (&lra_reg_info
[regno
].insn_bitmap
,
273 pseudo_regnos
[res
++] = regno
;
276 lra_assert (spill_class
!= NO_REGS
);
277 COPY_HARD_REG_SET (conflict_hard_regs
,
278 lra_reg_info
[regno
].conflict_hard_regs
);
279 for (r
= lra_reg_info
[regno
].live_ranges
; r
!= NULL
; r
= r
->next
)
280 for (p
= r
->start
; p
<= r
->finish
; p
++)
281 IOR_HARD_REG_SET (conflict_hard_regs
, reserved_hard_regs
[p
]);
282 spill_class_size
= ira_class_hard_regs_num
[spill_class
];
283 mode
= lra_reg_info
[regno
].biggest_mode
;
284 for (k
= 0; k
< spill_class_size
; k
++)
286 hard_regno
= ira_class_hard_regs
[spill_class
][k
];
287 if (! overlaps_hard_reg_set_p (conflict_hard_regs
, mode
, hard_regno
))
290 if (k
>= spill_class_size
)
292 /* There is no available regs -- assign memory later. */
293 pseudo_regnos
[res
++] = regno
;
296 if (lra_dump_file
!= NULL
)
297 fprintf (lra_dump_file
, " Spill r%d into hr%d\n", regno
, hard_regno
);
298 add_to_hard_reg_set (&hard_regs_spilled_into
,
299 lra_reg_info
[regno
].biggest_mode
, hard_regno
);
300 /* Update reserved_hard_regs. */
301 for (r
= lra_reg_info
[regno
].live_ranges
; r
!= NULL
; r
= r
->next
)
302 for (p
= r
->start
; p
<= r
->finish
; p
++)
303 add_to_hard_reg_set (&reserved_hard_regs
[p
],
304 lra_reg_info
[regno
].biggest_mode
, hard_regno
);
305 spill_hard_reg
[regno
]
306 = gen_raw_REG (PSEUDO_REGNO_MODE (regno
), hard_regno
);
308 nr
< hard_regno_nregs (hard_regno
,
309 lra_reg_info
[regno
].biggest_mode
);
312 df_set_regs_ever_live (hard_regno
+ nr
, true);
314 free (reserved_hard_regs
);
318 /* Add pseudo REGNO to slot SLOT_NUM. */
320 add_pseudo_to_slot (int regno
, int slot_num
)
322 struct pseudo_slot
*first
;
324 /* Each pseudo has an inherent size which comes from its own mode,
325 and a total size which provides room for paradoxical subregs.
326 We need to make sure the size and alignment of the slot are
327 sufficient for both. */
328 machine_mode mode
= wider_subreg_mode (PSEUDO_REGNO_MODE (regno
),
329 lra_reg_info
[regno
].biggest_mode
);
330 unsigned int align
= spill_slot_alignment (mode
);
331 slots
[slot_num
].align
= MAX (slots
[slot_num
].align
, align
);
332 slots
[slot_num
].size
= upper_bound (slots
[slot_num
].size
,
333 GET_MODE_SIZE (mode
));
335 if (slots
[slot_num
].regno
< 0)
337 /* It is the first pseudo in the slot. */
338 slots
[slot_num
].regno
= regno
;
339 pseudo_slots
[regno
].first
= &pseudo_slots
[regno
];
340 pseudo_slots
[regno
].next
= NULL
;
344 first
= pseudo_slots
[regno
].first
= &pseudo_slots
[slots
[slot_num
].regno
];
345 pseudo_slots
[regno
].next
= first
->next
;
346 first
->next
= &pseudo_slots
[regno
];
348 pseudo_slots
[regno
].mem
= NULL_RTX
;
349 pseudo_slots
[regno
].slot_num
= slot_num
;
350 slots
[slot_num
].live_ranges
351 = lra_merge_live_ranges (slots
[slot_num
].live_ranges
,
352 lra_copy_live_range_list
353 (lra_reg_info
[regno
].live_ranges
));
356 /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of
357 length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning
358 memory stack slots. */
360 assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos
, int n
)
365 /* Assign stack slot numbers to spilled pseudos, use smaller numbers
366 for most frequently used pseudos. */
367 for (i
= 0; i
< n
; i
++)
369 regno
= pseudo_regnos
[i
];
370 if (! flag_ira_share_spill_slots
)
375 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno
),
376 lra_reg_info
[regno
].biggest_mode
);
377 for (j
= 0; j
< slots_num
; j
++)
378 if (slots
[j
].hard_regno
< 0
379 /* Although it's possible to share slots between modes
380 with constant and non-constant widths, we usually
381 get better spill code by keeping the constant and
382 non-constant areas separate. */
383 && (GET_MODE_SIZE (mode
).is_constant ()
384 == slots
[j
].size
.is_constant ())
385 && ! (lra_intersected_live_ranges_p
386 (slots
[j
].live_ranges
,
387 lra_reg_info
[regno
].live_ranges
)))
393 slots
[j
].live_ranges
= NULL
;
395 slots
[j
].align
= BITS_PER_UNIT
;
396 slots
[j
].regno
= slots
[j
].hard_regno
= -1;
397 slots
[j
].mem
= NULL_RTX
;
400 add_pseudo_to_slot (regno
, j
);
402 /* Sort regnos according to their slot numbers. */
403 qsort (pseudo_regnos
, n
, sizeof (int), pseudo_reg_slot_compare
);
406 /* Recursively process LOC in INSN and change spilled pseudos to the
407 corresponding memory or spilled hard reg. Ignore spilled pseudos
408 created from the scratches. Return true if the pseudo nrefs equal
409 to 0 (don't change the pseudo in this case). Otherwise return false. */
411 remove_pseudos (rtx
*loc
, rtx_insn
*insn
)
419 if (*loc
== NULL_RTX
)
421 code
= GET_CODE (*loc
);
422 if (code
== REG
&& (i
= REGNO (*loc
)) >= FIRST_PSEUDO_REGISTER
423 && lra_get_regno_hard_regno (i
) < 0
424 /* We do not want to assign memory for former scratches because
425 it might result in an address reload for some targets. In
426 any case we transform such pseudos not getting hard registers
427 into scratches back. */
428 && ! lra_former_scratch_p (i
))
430 if (lra_reg_info
[i
].nrefs
== 0
431 && pseudo_slots
[i
].mem
== NULL
&& spill_hard_reg
[i
] == NULL
)
433 if ((hard_reg
= spill_hard_reg
[i
]) != NULL_RTX
)
434 *loc
= copy_rtx (hard_reg
);
437 rtx x
= lra_eliminate_regs_1 (insn
, pseudo_slots
[i
].mem
,
438 GET_MODE (pseudo_slots
[i
].mem
),
439 false, false, 0, true);
440 *loc
= x
!= pseudo_slots
[i
].mem
? x
: copy_rtx (x
);
445 fmt
= GET_RTX_FORMAT (code
);
446 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
449 res
= remove_pseudos (&XEXP (*loc
, i
), insn
) || res
;
450 else if (fmt
[i
] == 'E')
454 for (j
= XVECLEN (*loc
, i
) - 1; j
>= 0; j
--)
455 res
= remove_pseudos (&XVECEXP (*loc
, i
, j
), insn
) || res
;
461 /* Convert spilled pseudos into their stack slots or spill hard regs,
462 put insns to process on the constraint stack (that is all insns in
463 which pseudos were changed to memory or spill hard regs). */
468 rtx_insn
*insn
, *curr
;
471 auto_bitmap
spilled_pseudos (®_obstack
);
472 auto_bitmap
changed_insns (®_obstack
);
473 for (i
= FIRST_PSEUDO_REGISTER
; i
< regs_num
; i
++)
475 if (lra_reg_info
[i
].nrefs
!= 0 && lra_get_regno_hard_regno (i
) < 0
476 && ! lra_former_scratch_p (i
))
478 bitmap_set_bit (spilled_pseudos
, i
);
479 bitmap_ior_into (changed_insns
, &lra_reg_info
[i
].insn_bitmap
);
482 FOR_EACH_BB_FN (bb
, cfun
)
484 FOR_BB_INSNS_SAFE (bb
, insn
, curr
)
486 bool removed_pseudo_p
= false;
488 if (bitmap_bit_p (changed_insns
, INSN_UID (insn
)))
492 removed_pseudo_p
= remove_pseudos (&PATTERN (insn
), insn
);
494 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn
), insn
))
495 removed_pseudo_p
= true;
496 for (link_loc
= ®_NOTES (insn
);
497 (link
= *link_loc
) != NULL_RTX
;
498 link_loc
= &XEXP (link
, 1))
500 switch (REG_NOTE_KIND (link
))
502 case REG_FRAME_RELATED_EXPR
:
503 case REG_CFA_DEF_CFA
:
504 case REG_CFA_ADJUST_CFA
:
506 case REG_CFA_REGISTER
:
507 case REG_CFA_EXPRESSION
:
508 case REG_CFA_RESTORE
:
509 case REG_CFA_SET_VDRAP
:
510 if (remove_pseudos (&XEXP (link
, 0), insn
))
511 removed_pseudo_p
= true;
517 if (lra_dump_file
!= NULL
)
518 fprintf (lra_dump_file
,
519 "Changing spilled pseudos to memory in insn #%u\n",
521 lra_push_insn (insn
);
522 if (lra_reg_spill_p
|| targetm
.different_addr_displacement_p ())
523 lra_set_used_insn_alternative (insn
, LRA_UNKNOWN_ALT
);
525 else if (CALL_P (insn
)
526 /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE
527 does not affect value of insn_bitmap of the
528 corresponding lra_reg_info. That is because we
529 don't need to reload pseudos in
530 CALL_INSN_FUNCTION_USAGEs. So if we process only
531 insns in the insn_bitmap of given pseudo here, we
532 can miss the pseudo in some
533 CALL_INSN_FUNCTION_USAGEs. */
534 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn
), insn
))
535 removed_pseudo_p
= true;
536 if (removed_pseudo_p
)
538 lra_assert (DEBUG_INSN_P (insn
));
539 lra_invalidate_insn_data (insn
);
540 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
541 if (lra_dump_file
!= NULL
)
542 fprintf (lra_dump_file
,
543 "Debug insn #%u is reset because it referenced "
544 "removed pseudo\n", INSN_UID (insn
));
546 bitmap_and_compl_into (df_get_live_in (bb
), spilled_pseudos
);
547 bitmap_and_compl_into (df_get_live_out (bb
), spilled_pseudos
);
552 /* Return true if we need to change some pseudos into memory. */
554 lra_need_for_spills_p (void)
556 int i
; max_regno
= max_reg_num ();
558 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
559 if (lra_reg_info
[i
].nrefs
!= 0 && lra_get_regno_hard_regno (i
) < 0
560 && ! lra_former_scratch_p (i
))
565 /* Change spilled pseudos into memory or spill hard regs. Put changed
566 insns on the constraint stack (these insns will be considered on
567 the next constraint pass). The changed insns are all insns in
568 which pseudos were changed. */
572 int i
, n
, curr_regno
;
575 regs_num
= max_reg_num ();
576 spill_hard_reg
= XNEWVEC (rtx
, regs_num
);
577 pseudo_regnos
= XNEWVEC (int, regs_num
);
578 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< regs_num
; i
++)
579 if (lra_reg_info
[i
].nrefs
!= 0 && lra_get_regno_hard_regno (i
) < 0
580 /* We do not want to assign memory for former scratches. */
581 && ! lra_former_scratch_p (i
))
582 pseudo_regnos
[n
++] = i
;
584 pseudo_slots
= XNEWVEC (struct pseudo_slot
, regs_num
);
585 for (i
= FIRST_PSEUDO_REGISTER
; i
< regs_num
; i
++)
587 spill_hard_reg
[i
] = NULL_RTX
;
588 pseudo_slots
[i
].mem
= NULL_RTX
;
590 slots
= XNEWVEC (class slot
, regs_num
);
591 /* Sort regnos according their usage frequencies. */
592 qsort (pseudo_regnos
, n
, sizeof (int), regno_freq_compare
);
593 n
= assign_spill_hard_regs (pseudo_regnos
, n
);
594 assign_stack_slot_num_and_sort_pseudos (pseudo_regnos
, n
);
595 for (i
= 0; i
< n
; i
++)
596 if (pseudo_slots
[pseudo_regnos
[i
]].mem
== NULL_RTX
)
597 assign_mem_slot (pseudo_regnos
[i
]);
598 if (n
> 0 && crtl
->stack_alignment_needed
)
599 /* If we have a stack frame, we must align it now. The stack size
600 may be a part of the offset computation for register
602 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
603 if (lra_dump_file
!= NULL
)
605 for (i
= 0; i
< slots_num
; i
++)
607 fprintf (lra_dump_file
, " Slot %d regnos (width = ", i
);
608 print_dec (GET_MODE_SIZE (GET_MODE (slots
[i
].mem
)),
609 lra_dump_file
, SIGNED
);
610 fprintf (lra_dump_file
, "):");
611 for (curr_regno
= slots
[i
].regno
;;
612 curr_regno
= pseudo_slots
[curr_regno
].next
- pseudo_slots
)
614 fprintf (lra_dump_file
, " %d", curr_regno
);
615 if (pseudo_slots
[curr_regno
].next
== NULL
)
618 fprintf (lra_dump_file
, "\n");
624 free (pseudo_regnos
);
625 free (spill_hard_reg
);
628 /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for
629 alter_subreg calls. Return true if any subreg of reg is
632 alter_subregs (rtx
*loc
, bool final_p
)
643 if (code
== SUBREG
&& REG_P (SUBREG_REG (x
)))
645 lra_assert (REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
);
646 alter_subreg (loc
, final_p
);
649 fmt
= GET_RTX_FORMAT (code
);
651 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
655 if (alter_subregs (&XEXP (x
, i
), final_p
))
658 else if (fmt
[i
] == 'E')
662 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
663 if (alter_subregs (&XVECEXP (x
, i
, j
), final_p
))
670 /* Return true if REGNO is used for return in the current
673 return_regno_p (unsigned int regno
)
675 rtx outgoing
= crtl
->return_rtx
;
680 if (REG_P (outgoing
))
681 return REGNO (outgoing
) == regno
;
682 else if (GET_CODE (outgoing
) == PARALLEL
)
686 for (i
= 0; i
< XVECLEN (outgoing
, 0); i
++)
688 rtx x
= XEXP (XVECEXP (outgoing
, 0, i
), 0);
690 if (REG_P (x
) && REGNO (x
) == regno
)
697 /* Return true if REGNO is in one of subsequent USE after INSN in the
700 regno_in_use_p (rtx_insn
*insn
, unsigned int regno
)
702 static lra_insn_recog_data_t id
;
703 static struct lra_static_insn_data
*static_id
;
704 struct lra_insn_reg
*reg
;
706 basic_block bb
= BLOCK_FOR_INSN (insn
);
708 while ((insn
= next_nondebug_insn (insn
)) != NULL_RTX
)
710 if (BARRIER_P (insn
) || bb
!= BLOCK_FOR_INSN (insn
))
714 if (GET_CODE (PATTERN (insn
)) == USE
715 && REG_P (XEXP (PATTERN (insn
), 0))
716 && regno
== REGNO (XEXP (PATTERN (insn
), 0)))
718 /* Check that the regno is not modified. */
719 id
= lra_get_insn_recog_data (insn
);
720 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
721 if (reg
->type
!= OP_IN
&& reg
->regno
== (int) regno
)
723 static_id
= id
->insn_static_data
;
724 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
725 if (reg
->type
!= OP_IN
&& reg
->regno
== (int) regno
)
727 if (id
->arg_hard_regs
!= NULL
)
728 for (i
= 0; (arg_regno
= id
->arg_hard_regs
[i
]) >= 0; i
++)
729 if ((int) regno
== (arg_regno
>= FIRST_PSEUDO_REGISTER
730 ? arg_regno
: arg_regno
- FIRST_PSEUDO_REGISTER
))
736 /* Final change of pseudos got hard registers into the corresponding
737 hard registers and removing temporary clobbers. */
739 lra_final_code_change (void)
743 rtx_insn
*insn
, *curr
;
745 int max_regno
= max_reg_num ();
747 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
748 if (lra_reg_info
[i
].nrefs
!= 0
749 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
750 SET_REGNO (regno_reg_rtx
[i
], hard_regno
);
751 FOR_EACH_BB_FN (bb
, cfun
)
752 FOR_BB_INSNS_SAFE (bb
, insn
, curr
)
755 rtx pat
= PATTERN (insn
);
757 if (GET_CODE (pat
) == CLOBBER
&& LRA_TEMP_CLOBBER_P (pat
))
759 /* Remove clobbers temporarily created in LRA. We don't
760 need them anymore and don't want to waste compiler
761 time processing them in a few subsequent passes. */
762 lra_invalidate_insn_data (insn
);
767 /* IRA can generate move insns involving pseudos. It is
768 better remove them earlier to speed up compiler a bit.
769 It is also better to do it here as they might not pass
770 final RTL check in LRA, (e.g. insn moving a control
771 register into itself). So remove an useless move insn
772 unless next insn is USE marking the return reg (we should
773 save this as some subsequent optimizations assume that
774 such original insns are saved). */
775 if (NONJUMP_INSN_P (insn
) && GET_CODE (pat
) == SET
776 && REG_P (SET_SRC (pat
)) && REG_P (SET_DEST (pat
))
777 && REGNO (SET_SRC (pat
)) == REGNO (SET_DEST (pat
))
778 && (! return_regno_p (REGNO (SET_SRC (pat
)))
779 || ! regno_in_use_p (insn
, REGNO (SET_SRC (pat
)))))
781 lra_invalidate_insn_data (insn
);
786 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
787 struct lra_insn_reg
*reg
;
789 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
790 if (reg
->regno
>= FIRST_PSEUDO_REGISTER
791 && lra_reg_info
[reg
->regno
].nrefs
== 0)
796 /* Pseudos still can be in debug insns in some very rare
797 and complicated cases, e.g. the pseudo was removed by
798 inheritance and the debug insn is not EBBs where the
799 inheritance happened. It is difficult and time
800 consuming to find what hard register corresponds the
801 pseudo -- so just remove the debug insn. Another
802 solution could be assigning hard reg/memory but it
803 would be a misleading info. It is better not to have
804 info than have it wrong. */
805 lra_assert (DEBUG_INSN_P (insn
));
806 lra_invalidate_insn_data (insn
);
811 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
812 bool insn_change_p
= false;
814 for (i
= id
->insn_static_data
->n_operands
- 1; i
>= 0; i
--)
815 if ((DEBUG_INSN_P (insn
) || ! static_id
->operand
[i
].is_operator
)
816 && alter_subregs (id
->operand_loc
[i
], ! DEBUG_INSN_P (insn
)))
818 lra_update_dup (id
, i
);
819 insn_change_p
= true;
822 lra_update_operator_dups (id
);
824 if ((set
= single_set (insn
)) != NULL
825 && REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
826 && REGNO (SET_SRC (set
)) == REGNO (SET_DEST (set
)))
828 /* Remove an useless move insn. IRA can generate move
829 insns involving pseudos. It is better remove them
830 earlier to speed up compiler a bit. It is also
831 better to do it here as they might not pass final RTL
832 check in LRA, (e.g. insn moving a control register
834 lra_invalidate_insn_data (insn
);