Daily bump.
[official-gcc.git] / gcc / lra-constraints.c
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1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2020 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
107 #undef REG_OK_STRICT
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "memmodel.h"
119 #include "tm_p.h"
120 #include "expmed.h"
121 #include "optabs.h"
122 #include "regs.h"
123 #include "ira.h"
124 #include "recog.h"
125 #include "output.h"
126 #include "addresses.h"
127 #include "expr.h"
128 #include "cfgrtl.h"
129 #include "rtl-error.h"
130 #include "lra.h"
131 #include "lra-int.h"
132 #include "print-rtl.h"
133 #include "function-abi.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 reload insns. */
138 static int bb_reload_num;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn *curr_insn;
144 static rtx curr_insn_set;
145 static basic_block curr_bb;
146 static lra_insn_recog_data_t curr_id;
147 static struct lra_static_insn_data *curr_static_id;
148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
156 /* Start numbers for new registers and insns at the current constraints
157 pass start. */
158 static int new_regno_start;
159 static int new_insn_uid_start;
161 /* If LOC is nonnull, strip any outer subreg from it. */
162 static inline rtx *
163 strip_subreg (rtx *loc)
165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
170 static int
171 get_try_hard_regno (int regno)
173 int hard_regno;
174 enum reg_class rclass;
176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177 hard_regno = lra_get_regno_hard_regno (regno);
178 if (hard_regno >= 0)
179 return hard_regno;
180 rclass = lra_get_allocno_class (regno);
181 if (rclass == NO_REGS)
182 return -1;
183 return ira_class_hard_regs[rclass][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
190 static int
191 get_hard_regno (rtx x, bool final_p)
193 rtx reg;
194 int hard_regno;
196 reg = x;
197 if (SUBREG_P (x))
198 reg = SUBREG_REG (x);
199 if (! REG_P (reg))
200 return -1;
201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202 hard_regno = lra_get_regno_hard_regno (hard_regno);
203 if (hard_regno < 0)
204 return -1;
205 if (final_p)
206 hard_regno = lra_get_elimination_hard_regno (hard_regno);
207 if (SUBREG_P (x))
208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 SUBREG_BYTE (x), GET_MODE (x));
210 return hard_regno;
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno)
220 int hard_regno;
222 if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223 hard_regno = lra_get_regno_hard_regno (regno);
224 if (hard_regno >= 0)
226 hard_regno = lra_get_elimination_hard_regno (hard_regno);
227 return REGNO_REG_CLASS (hard_regno);
229 if (regno >= new_regno_start)
230 return lra_get_allocno_class (regno);
231 return NO_REGS;
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
242 static bool
243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
245 enum reg_class rclass, common_class;
246 machine_mode reg_mode;
247 int class_size, hard_regno, nregs, i, j;
248 int regno = REGNO (reg);
250 if (new_class != NULL)
251 *new_class = NO_REGS;
252 if (regno < FIRST_PSEUDO_REGISTER)
254 rtx final_reg = reg;
255 rtx *final_loc = &final_reg;
257 lra_eliminate_reg_if_possible (final_loc);
258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
260 reg_mode = GET_MODE (reg);
261 rclass = get_reg_class (regno);
262 if (regno < new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn) >= new_insn_uid_start
269 && curr_insn_set != NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno >= new_regno_start && rclass == ALL_REGS)
278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 && ! hard_reg_set_subset_p (reg_class_contents[cl],
280 lra_no_alloc_regs)));
281 else
283 common_class = ira_reg_class_subset[rclass][cl];
284 if (new_class != NULL)
285 *new_class = common_class;
286 if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 lra_no_alloc_regs))
288 return false;
289 /* Check that there are enough allocatable regs. */
290 class_size = ira_class_hard_regs_num[common_class];
291 for (i = 0; i < class_size; i++)
293 hard_regno = ira_class_hard_regs[common_class][i];
294 nregs = hard_regno_nregs (hard_regno, reg_mode);
295 if (nregs == 1)
296 return true;
297 for (j = 0; j < nregs; j++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 hard_regno + j))
301 break;
302 if (j >= nregs)
303 return true;
305 return false;
309 /* Return true if REGNO satisfies a memory constraint. */
310 static bool
311 in_mem_p (int regno)
313 return get_reg_class (regno) == NO_REGS;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
318 reg. */
319 static int
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 rtx addr, addr_space_t as)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as));
325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326 return 0;
328 win:
329 return 1;
330 #else
331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332 #endif
335 namespace {
336 /* Temporarily eliminates registers in an address (for the lifetime of
337 the object). */
338 class address_eliminator {
339 public:
340 address_eliminator (struct address_info *ad);
341 ~address_eliminator ();
343 private:
344 struct address_info *m_ad;
345 rtx *m_base_loc;
346 rtx m_base_reg;
347 rtx *m_index_loc;
348 rtx m_index_reg;
352 address_eliminator::address_eliminator (struct address_info *ad)
353 : m_ad (ad),
354 m_base_loc (strip_subreg (ad->base_term)),
355 m_base_reg (NULL_RTX),
356 m_index_loc (strip_subreg (ad->index_term)),
357 m_index_reg (NULL_RTX)
359 if (m_base_loc != NULL)
361 m_base_reg = *m_base_loc;
362 /* If we have non-legitimate address which is decomposed not in
363 the way we expected, don't do elimination here. In such case
364 the address will be reloaded and elimination will be done in
365 reload insn finally. */
366 if (REG_P (m_base_reg))
367 lra_eliminate_reg_if_possible (m_base_loc);
368 if (m_ad->base_term2 != NULL)
369 *m_ad->base_term2 = *m_ad->base_term;
371 if (m_index_loc != NULL)
373 m_index_reg = *m_index_loc;
374 if (REG_P (m_index_reg))
375 lra_eliminate_reg_if_possible (m_index_loc);
379 address_eliminator::~address_eliminator ()
381 if (m_base_loc && *m_base_loc != m_base_reg)
383 *m_base_loc = m_base_reg;
384 if (m_ad->base_term2 != NULL)
385 *m_ad->base_term2 = *m_ad->base_term;
387 if (m_index_loc && *m_index_loc != m_index_reg)
388 *m_index_loc = m_index_reg;
391 /* Return true if the eliminated form of AD is a legitimate target address.
392 If OP is a MEM, AD is the address within OP, otherwise OP should be
393 ignored. CONSTRAINT is one constraint that the operand may need
394 to meet. */
395 static bool
396 valid_address_p (rtx op, struct address_info *ad,
397 enum constraint_num constraint)
399 address_eliminator eliminator (ad);
401 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
402 forgiving than "m". */
403 if (MEM_P (op)
404 && (insn_extra_memory_constraint (constraint)
405 || insn_extra_special_memory_constraint (constraint))
406 && constraint_satisfied_p (op, constraint))
407 return true;
409 return valid_address_p (ad->mode, *ad->outer, ad->as);
412 /* Return true if the eliminated form of memory reference OP satisfies
413 extra (special) memory constraint CONSTRAINT. */
414 static bool
415 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
417 struct address_info ad;
419 decompose_mem_address (&ad, op);
420 address_eliminator eliminator (&ad);
421 return constraint_satisfied_p (op, constraint);
424 /* Return true if the eliminated form of address AD satisfies extra
425 address constraint CONSTRAINT. */
426 static bool
427 satisfies_address_constraint_p (struct address_info *ad,
428 enum constraint_num constraint)
430 address_eliminator eliminator (ad);
431 return constraint_satisfied_p (*ad->outer, constraint);
434 /* Return true if the eliminated form of address OP satisfies extra
435 address constraint CONSTRAINT. */
436 static bool
437 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
439 struct address_info ad;
441 decompose_lea_address (&ad, &op);
442 return satisfies_address_constraint_p (&ad, constraint);
445 /* Initiate equivalences for LRA. As we keep original equivalences
446 before any elimination, we need to make copies otherwise any change
447 in insns might change the equivalences. */
448 void
449 lra_init_equiv (void)
451 ira_expand_reg_equiv ();
452 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
454 rtx res;
456 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
457 ira_reg_equiv[i].memory = copy_rtx (res);
458 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
459 ira_reg_equiv[i].invariant = copy_rtx (res);
463 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
465 /* Update equivalence for REGNO. We need to this as the equivalence
466 might contain other pseudos which are changed by their
467 equivalences. */
468 static void
469 update_equiv (int regno)
471 rtx x;
473 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
474 ira_reg_equiv[regno].memory
475 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
476 NULL_RTX);
477 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
478 ira_reg_equiv[regno].invariant
479 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
480 NULL_RTX);
483 /* If we have decided to substitute X with another value, return that
484 value, otherwise return X. */
485 static rtx
486 get_equiv (rtx x)
488 int regno;
489 rtx res;
491 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
492 || ! ira_reg_equiv[regno].defined_p
493 || ! ira_reg_equiv[regno].profitable_p
494 || lra_get_regno_hard_regno (regno) >= 0)
495 return x;
496 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
498 if (targetm.cannot_substitute_mem_equiv_p (res))
499 return x;
500 return res;
502 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
503 return res;
504 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
505 return res;
506 gcc_unreachable ();
509 /* If we have decided to substitute X with the equivalent value,
510 return that value after elimination for INSN, otherwise return
511 X. */
512 static rtx
513 get_equiv_with_elimination (rtx x, rtx_insn *insn)
515 rtx res = get_equiv (x);
517 if (x == res || CONSTANT_P (res))
518 return res;
519 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
520 false, false, 0, true);
523 /* Set up curr_operand_mode. */
524 static void
525 init_curr_operand_mode (void)
527 int nop = curr_static_id->n_operands;
528 for (int i = 0; i < nop; i++)
530 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
531 if (mode == VOIDmode)
533 /* The .md mode for address operands is the mode of the
534 addressed value rather than the mode of the address itself. */
535 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
536 mode = Pmode;
537 else
538 mode = curr_static_id->operand[i].mode;
540 curr_operand_mode[i] = mode;
546 /* The page contains code to reuse input reloads. */
548 /* Structure describes input reload of the current insns. */
549 struct input_reload
551 /* True for input reload of matched operands. */
552 bool match_p;
553 /* Reloaded value. */
554 rtx input;
555 /* Reload pseudo used. */
556 rtx reg;
559 /* The number of elements in the following array. */
560 static int curr_insn_input_reloads_num;
561 /* Array containing info about input reloads. It is used to find the
562 same input reload and reuse the reload pseudo in this case. */
563 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
565 /* Initiate data concerning reuse of input reloads for the current
566 insn. */
567 static void
568 init_curr_insn_input_reloads (void)
570 curr_insn_input_reloads_num = 0;
573 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
574 created input reload pseudo (only if TYPE is not OP_OUT). Don't
575 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
576 wrapped up in SUBREG. The result pseudo is returned through
577 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
578 reused the already created input reload pseudo. Use TITLE to
579 describe new registers for debug purposes. */
580 static bool
581 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
582 enum reg_class rclass, bool in_subreg_p,
583 const char *title, rtx *result_reg)
585 int i, regno;
586 enum reg_class new_class;
587 bool unique_p = false;
589 if (type == OP_OUT)
591 *result_reg
592 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
593 return true;
595 /* Prevent reuse value of expression with side effects,
596 e.g. volatile memory. */
597 if (! side_effects_p (original))
598 for (i = 0; i < curr_insn_input_reloads_num; i++)
600 if (! curr_insn_input_reloads[i].match_p
601 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
602 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
604 rtx reg = curr_insn_input_reloads[i].reg;
605 regno = REGNO (reg);
606 /* If input is equal to original and both are VOIDmode,
607 GET_MODE (reg) might be still different from mode.
608 Ensure we don't return *result_reg with wrong mode. */
609 if (GET_MODE (reg) != mode)
611 if (in_subreg_p)
612 continue;
613 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
614 GET_MODE_SIZE (mode)))
615 continue;
616 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
617 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
618 continue;
620 *result_reg = reg;
621 if (lra_dump_file != NULL)
623 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
624 dump_value_slim (lra_dump_file, original, 1);
626 if (new_class != lra_get_allocno_class (regno))
627 lra_change_class (regno, new_class, ", change to", false);
628 if (lra_dump_file != NULL)
629 fprintf (lra_dump_file, "\n");
630 return false;
632 /* If we have an input reload with a different mode, make sure it
633 will get a different hard reg. */
634 else if (REG_P (original)
635 && REG_P (curr_insn_input_reloads[i].input)
636 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
637 && (GET_MODE (original)
638 != GET_MODE (curr_insn_input_reloads[i].input)))
639 unique_p = true;
641 *result_reg = (unique_p
642 ? lra_create_new_reg_with_unique_value
643 : lra_create_new_reg) (mode, original, rclass, title);
644 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
645 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
646 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
647 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
648 return true;
652 /* The page contains major code to choose the current insn alternative
653 and generate reloads for it. */
655 /* Return the offset from REGNO of the least significant register
656 in (reg:MODE REGNO).
658 This function is used to tell whether two registers satisfy
659 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
661 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
662 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
664 lra_constraint_offset (int regno, machine_mode mode)
666 lra_assert (regno < FIRST_PSEUDO_REGISTER);
668 scalar_int_mode int_mode;
669 if (WORDS_BIG_ENDIAN
670 && is_a <scalar_int_mode> (mode, &int_mode)
671 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
672 return hard_regno_nregs (regno, mode) - 1;
673 return 0;
676 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
677 if they are the same hard reg, and has special hacks for
678 auto-increment and auto-decrement. This is specifically intended for
679 process_alt_operands to use in determining whether two operands
680 match. X is the operand whose number is the lower of the two.
682 It is supposed that X is the output operand and Y is the input
683 operand. Y_HARD_REGNO is the final hard regno of register Y or
684 register in subreg Y as we know it now. Otherwise, it is a
685 negative value. */
686 static bool
687 operands_match_p (rtx x, rtx y, int y_hard_regno)
689 int i;
690 RTX_CODE code = GET_CODE (x);
691 const char *fmt;
693 if (x == y)
694 return true;
695 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
696 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
698 int j;
700 i = get_hard_regno (x, false);
701 if (i < 0)
702 goto slow;
704 if ((j = y_hard_regno) < 0)
705 goto slow;
707 i += lra_constraint_offset (i, GET_MODE (x));
708 j += lra_constraint_offset (j, GET_MODE (y));
710 return i == j;
713 /* If two operands must match, because they are really a single
714 operand of an assembler insn, then two post-increments are invalid
715 because the assembler insn would increment only once. On the
716 other hand, a post-increment matches ordinary indexing if the
717 post-increment is the output operand. */
718 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
719 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
721 /* Two pre-increments are invalid because the assembler insn would
722 increment only once. On the other hand, a pre-increment matches
723 ordinary indexing if the pre-increment is the input operand. */
724 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
725 || GET_CODE (y) == PRE_MODIFY)
726 return operands_match_p (x, XEXP (y, 0), -1);
728 slow:
730 if (code == REG && REG_P (y))
731 return REGNO (x) == REGNO (y);
733 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
734 && x == SUBREG_REG (y))
735 return true;
736 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
737 && SUBREG_REG (x) == y)
738 return true;
740 /* Now we have disposed of all the cases in which different rtx
741 codes can match. */
742 if (code != GET_CODE (y))
743 return false;
745 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
746 if (GET_MODE (x) != GET_MODE (y))
747 return false;
749 switch (code)
751 CASE_CONST_UNIQUE:
752 return false;
754 case LABEL_REF:
755 return label_ref_label (x) == label_ref_label (y);
756 case SYMBOL_REF:
757 return XSTR (x, 0) == XSTR (y, 0);
759 default:
760 break;
763 /* Compare the elements. If any pair of corresponding elements fail
764 to match, return false for the whole things. */
766 fmt = GET_RTX_FORMAT (code);
767 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
769 int val, j;
770 switch (fmt[i])
772 case 'w':
773 if (XWINT (x, i) != XWINT (y, i))
774 return false;
775 break;
777 case 'i':
778 if (XINT (x, i) != XINT (y, i))
779 return false;
780 break;
782 case 'p':
783 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
784 return false;
785 break;
787 case 'e':
788 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
789 if (val == 0)
790 return false;
791 break;
793 case '0':
794 break;
796 case 'E':
797 if (XVECLEN (x, i) != XVECLEN (y, i))
798 return false;
799 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
801 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
802 if (val == 0)
803 return false;
805 break;
807 /* It is believed that rtx's at this level will never
808 contain anything but integers and other rtx's, except for
809 within LABEL_REFs and SYMBOL_REFs. */
810 default:
811 gcc_unreachable ();
814 return true;
817 /* True if X is a constant that can be forced into the constant pool.
818 MODE is the mode of the operand, or VOIDmode if not known. */
819 #define CONST_POOL_OK_P(MODE, X) \
820 ((MODE) != VOIDmode \
821 && CONSTANT_P (X) \
822 && GET_CODE (X) != HIGH \
823 && GET_MODE_SIZE (MODE).is_constant () \
824 && !targetm.cannot_force_const_mem (MODE, X))
826 /* True if C is a non-empty register class that has too few registers
827 to be safely used as a reload target class. */
828 #define SMALL_REGISTER_CLASS_P(C) \
829 (ira_class_hard_regs_num [(C)] == 1 \
830 || (ira_class_hard_regs_num [(C)] >= 1 \
831 && targetm.class_likely_spilled_p (C)))
833 /* If REG is a reload pseudo, try to make its class satisfying CL. */
834 static void
835 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
837 enum reg_class rclass;
839 /* Do not make more accurate class from reloads generated. They are
840 mostly moves with a lot of constraints. Making more accurate
841 class may results in very narrow class and impossibility of find
842 registers for several reloads of one insn. */
843 if (INSN_UID (curr_insn) >= new_insn_uid_start)
844 return;
845 if (GET_CODE (reg) == SUBREG)
846 reg = SUBREG_REG (reg);
847 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
848 return;
849 if (in_class_p (reg, cl, &rclass) && rclass != cl)
850 lra_change_class (REGNO (reg), rclass, " Change to", true);
853 /* Searches X for any reference to a reg with the same value as REGNO,
854 returning the rtx of the reference found if any. Otherwise,
855 returns NULL_RTX. */
856 static rtx
857 regno_val_use_in (unsigned int regno, rtx x)
859 const char *fmt;
860 int i, j;
861 rtx tem;
863 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
864 return x;
866 fmt = GET_RTX_FORMAT (GET_CODE (x));
867 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
869 if (fmt[i] == 'e')
871 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
872 return tem;
874 else if (fmt[i] == 'E')
875 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
876 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
877 return tem;
880 return NULL_RTX;
883 /* Return true if all current insn non-output operands except INS (it
884 has a negaitve end marker) do not use pseudos with the same value
885 as REGNO. */
886 static bool
887 check_conflict_input_operands (int regno, signed char *ins)
889 int in;
890 int n_operands = curr_static_id->n_operands;
892 for (int nop = 0; nop < n_operands; nop++)
893 if (! curr_static_id->operand[nop].is_operator
894 && curr_static_id->operand[nop].type != OP_OUT)
896 for (int i = 0; (in = ins[i]) >= 0; i++)
897 if (in == nop)
898 break;
899 if (in < 0
900 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
901 return false;
903 return true;
906 /* Generate reloads for matching OUT and INS (array of input operand
907 numbers with end marker -1) with reg class GOAL_CLASS, considering
908 output operands OUTS (similar array to INS) needing to be in different
909 registers. Add input and output reloads correspondingly to the lists
910 *BEFORE and *AFTER. OUT might be negative. In this case we generate
911 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
912 that the output operand is early clobbered for chosen alternative. */
913 static void
914 match_reload (signed char out, signed char *ins, signed char *outs,
915 enum reg_class goal_class, rtx_insn **before,
916 rtx_insn **after, bool early_clobber_p)
918 bool out_conflict;
919 int i, in;
920 rtx new_in_reg, new_out_reg, reg;
921 machine_mode inmode, outmode;
922 rtx in_rtx = *curr_id->operand_loc[ins[0]];
923 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
925 inmode = curr_operand_mode[ins[0]];
926 outmode = out < 0 ? inmode : curr_operand_mode[out];
927 push_to_sequence (*before);
928 if (inmode != outmode)
930 /* process_alt_operands has already checked that the mode sizes
931 are ordered. */
932 if (partial_subreg_p (outmode, inmode))
934 reg = new_in_reg
935 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
936 goal_class, "");
937 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
938 LRA_SUBREG_P (new_out_reg) = 1;
939 /* If the input reg is dying here, we can use the same hard
940 register for REG and IN_RTX. We do it only for original
941 pseudos as reload pseudos can die although original
942 pseudos still live where reload pseudos dies. */
943 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
944 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
945 && (!early_clobber_p
946 || check_conflict_input_operands(REGNO (in_rtx), ins)))
947 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
949 else
951 reg = new_out_reg
952 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
953 goal_class, "");
954 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
955 /* NEW_IN_REG is non-paradoxical subreg. We don't want
956 NEW_OUT_REG living above. We add clobber clause for
957 this. This is just a temporary clobber. We can remove
958 it at the end of LRA work. */
959 rtx_insn *clobber = emit_clobber (new_out_reg);
960 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
961 LRA_SUBREG_P (new_in_reg) = 1;
962 if (GET_CODE (in_rtx) == SUBREG)
964 rtx subreg_reg = SUBREG_REG (in_rtx);
966 /* If SUBREG_REG is dying here and sub-registers IN_RTX
967 and NEW_IN_REG are similar, we can use the same hard
968 register for REG and SUBREG_REG. */
969 if (REG_P (subreg_reg)
970 && (int) REGNO (subreg_reg) < lra_new_regno_start
971 && GET_MODE (subreg_reg) == outmode
972 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
973 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
974 && (! early_clobber_p
975 || check_conflict_input_operands (REGNO (subreg_reg),
976 ins)))
977 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
981 else
983 /* Pseudos have values -- see comments for lra_reg_info.
984 Different pseudos with the same value do not conflict even if
985 they live in the same place. When we create a pseudo we
986 assign value of original pseudo (if any) from which we
987 created the new pseudo. If we create the pseudo from the
988 input pseudo, the new pseudo will have no conflict with the
989 input pseudo which is wrong when the input pseudo lives after
990 the insn and as the new pseudo value is changed by the insn
991 output. Therefore we create the new pseudo from the output
992 except the case when we have single matched dying input
993 pseudo.
995 We cannot reuse the current output register because we might
996 have a situation like "a <- a op b", where the constraints
997 force the second input operand ("b") to match the output
998 operand ("a"). "b" must then be copied into a new register
999 so that it doesn't clobber the current value of "a".
1001 We cannot use the same value if the output pseudo is
1002 early clobbered or the input pseudo is mentioned in the
1003 output, e.g. as an address part in memory, because
1004 output reload will actually extend the pseudo liveness.
1005 We don't care about eliminable hard regs here as we are
1006 interesting only in pseudos. */
1008 /* Matching input's register value is the same as one of the other
1009 output operand. Output operands in a parallel insn must be in
1010 different registers. */
1011 out_conflict = false;
1012 if (REG_P (in_rtx))
1014 for (i = 0; outs[i] >= 0; i++)
1016 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1017 if (REG_P (other_out_rtx)
1018 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1019 != NULL_RTX))
1021 out_conflict = true;
1022 break;
1027 new_in_reg = new_out_reg
1028 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1029 && (int) REGNO (in_rtx) < lra_new_regno_start
1030 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1031 && (! early_clobber_p
1032 || check_conflict_input_operands (REGNO (in_rtx), ins))
1033 && (out < 0
1034 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1035 && !out_conflict
1036 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1037 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1038 goal_class, ""));
1040 /* In operand can be got from transformations before processing insn
1041 constraints. One example of such transformations is subreg
1042 reloading (see function simplify_operand_subreg). The new
1043 pseudos created by the transformations might have inaccurate
1044 class (ALL_REGS) and we should make their classes more
1045 accurate. */
1046 narrow_reload_pseudo_class (in_rtx, goal_class);
1047 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1048 *before = get_insns ();
1049 end_sequence ();
1050 /* Add the new pseudo to consider values of subsequent input reload
1051 pseudos. */
1052 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1053 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1054 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1055 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1056 for (i = 0; (in = ins[i]) >= 0; i++)
1057 if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1058 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]))
1059 *curr_id->operand_loc[in] = new_in_reg;
1060 else
1062 lra_assert
1063 (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in]));
1064 *curr_id->operand_loc[in] = new_out_reg;
1066 lra_update_dups (curr_id, ins);
1067 if (out < 0)
1068 return;
1069 /* See a comment for the input operand above. */
1070 narrow_reload_pseudo_class (out_rtx, goal_class);
1071 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1073 start_sequence ();
1074 if (out >= 0 && curr_static_id->operand[out].strict_low)
1075 out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx);
1076 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1077 emit_insn (*after);
1078 *after = get_insns ();
1079 end_sequence ();
1081 *curr_id->operand_loc[out] = new_out_reg;
1082 lra_update_dup (curr_id, out);
1085 /* Return register class which is union of all reg classes in insn
1086 constraint alternative string starting with P. */
1087 static enum reg_class
1088 reg_class_from_constraints (const char *p)
1090 int c, len;
1091 enum reg_class op_class = NO_REGS;
1094 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1096 case '#':
1097 case ',':
1098 return op_class;
1100 case 'g':
1101 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1102 break;
1104 default:
1105 enum constraint_num cn = lookup_constraint (p);
1106 enum reg_class cl = reg_class_for_constraint (cn);
1107 if (cl == NO_REGS)
1109 if (insn_extra_address_constraint (cn))
1110 op_class
1111 = (reg_class_subunion
1112 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1113 ADDRESS, SCRATCH)]);
1114 break;
1117 op_class = reg_class_subunion[op_class][cl];
1118 break;
1120 while ((p += len), c);
1121 return op_class;
1124 /* If OP is a register, return the class of the register as per
1125 get_reg_class, otherwise return NO_REGS. */
1126 static inline enum reg_class
1127 get_op_class (rtx op)
1129 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1132 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1133 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1134 SUBREG for VAL to make them equal. */
1135 static rtx_insn *
1136 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1138 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1140 /* Usually size of mem_pseudo is greater than val size but in
1141 rare cases it can be less as it can be defined by target
1142 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1143 if (! MEM_P (val))
1145 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1146 GET_CODE (val) == SUBREG
1147 ? SUBREG_REG (val) : val);
1148 LRA_SUBREG_P (val) = 1;
1150 else
1152 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1153 LRA_SUBREG_P (mem_pseudo) = 1;
1156 return to_p ? gen_move_insn (mem_pseudo, val)
1157 : gen_move_insn (val, mem_pseudo);
1160 /* Process a special case insn (register move), return true if we
1161 don't need to process it anymore. INSN should be a single set
1162 insn. Set up that RTL was changed through CHANGE_P and that hook
1163 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1164 SEC_MEM_P. */
1165 static bool
1166 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1168 int sregno, dregno;
1169 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1170 rtx_insn *before;
1171 enum reg_class dclass, sclass, secondary_class;
1172 secondary_reload_info sri;
1174 lra_assert (curr_insn_set != NULL_RTX);
1175 dreg = dest = SET_DEST (curr_insn_set);
1176 sreg = src = SET_SRC (curr_insn_set);
1177 if (GET_CODE (dest) == SUBREG)
1178 dreg = SUBREG_REG (dest);
1179 if (GET_CODE (src) == SUBREG)
1180 sreg = SUBREG_REG (src);
1181 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1182 return false;
1183 sclass = dclass = NO_REGS;
1184 if (REG_P (dreg))
1185 dclass = get_reg_class (REGNO (dreg));
1186 gcc_assert (dclass < LIM_REG_CLASSES);
1187 if (dclass == ALL_REGS)
1188 /* ALL_REGS is used for new pseudos created by transformations
1189 like reload of SUBREG_REG (see function
1190 simplify_operand_subreg). We don't know their class yet. We
1191 should figure out the class from processing the insn
1192 constraints not in this fast path function. Even if ALL_REGS
1193 were a right class for the pseudo, secondary_... hooks usually
1194 are not define for ALL_REGS. */
1195 return false;
1196 if (REG_P (sreg))
1197 sclass = get_reg_class (REGNO (sreg));
1198 gcc_assert (sclass < LIM_REG_CLASSES);
1199 if (sclass == ALL_REGS)
1200 /* See comments above. */
1201 return false;
1202 if (sclass == NO_REGS && dclass == NO_REGS)
1203 return false;
1204 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1205 && ((sclass != NO_REGS && dclass != NO_REGS)
1206 || (GET_MODE (src)
1207 != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1209 *sec_mem_p = true;
1210 return false;
1212 if (! REG_P (dreg) || ! REG_P (sreg))
1213 return false;
1214 sri.prev_sri = NULL;
1215 sri.icode = CODE_FOR_nothing;
1216 sri.extra_cost = 0;
1217 secondary_class = NO_REGS;
1218 /* Set up hard register for a reload pseudo for hook
1219 secondary_reload because some targets just ignore unassigned
1220 pseudos in the hook. */
1221 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1223 dregno = REGNO (dreg);
1224 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1226 else
1227 dregno = -1;
1228 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1230 sregno = REGNO (sreg);
1231 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1233 else
1234 sregno = -1;
1235 if (sclass != NO_REGS)
1236 secondary_class
1237 = (enum reg_class) targetm.secondary_reload (false, dest,
1238 (reg_class_t) sclass,
1239 GET_MODE (src), &sri);
1240 if (sclass == NO_REGS
1241 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1242 && dclass != NO_REGS))
1244 enum reg_class old_sclass = secondary_class;
1245 secondary_reload_info old_sri = sri;
1247 sri.prev_sri = NULL;
1248 sri.icode = CODE_FOR_nothing;
1249 sri.extra_cost = 0;
1250 secondary_class
1251 = (enum reg_class) targetm.secondary_reload (true, src,
1252 (reg_class_t) dclass,
1253 GET_MODE (src), &sri);
1254 /* Check the target hook consistency. */
1255 lra_assert
1256 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1257 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1258 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1260 if (sregno >= 0)
1261 reg_renumber [sregno] = -1;
1262 if (dregno >= 0)
1263 reg_renumber [dregno] = -1;
1264 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1265 return false;
1266 *change_p = true;
1267 new_reg = NULL_RTX;
1268 if (secondary_class != NO_REGS)
1269 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1270 secondary_class,
1271 "secondary");
1272 start_sequence ();
1273 if (sri.icode == CODE_FOR_nothing)
1274 lra_emit_move (new_reg, src);
1275 else
1277 enum reg_class scratch_class;
1279 scratch_class = (reg_class_from_constraints
1280 (insn_data[sri.icode].operand[2].constraint));
1281 scratch_reg = (lra_create_new_reg_with_unique_value
1282 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1283 scratch_class, "scratch"));
1284 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1285 src, scratch_reg));
1287 before = get_insns ();
1288 end_sequence ();
1289 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1290 if (new_reg != NULL_RTX)
1291 SET_SRC (curr_insn_set) = new_reg;
1292 else
1294 if (lra_dump_file != NULL)
1296 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1297 dump_insn_slim (lra_dump_file, curr_insn);
1299 lra_set_insn_deleted (curr_insn);
1300 return true;
1302 return false;
1305 /* The following data describe the result of process_alt_operands.
1306 The data are used in curr_insn_transform to generate reloads. */
1308 /* The chosen reg classes which should be used for the corresponding
1309 operands. */
1310 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1311 /* True if the operand should be the same as another operand and that
1312 other operand does not need a reload. */
1313 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1314 /* True if the operand does not need a reload. */
1315 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1316 /* True if the operand can be offsetable memory. */
1317 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1318 /* The number of an operand to which given operand can be matched to. */
1319 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1320 /* The number of elements in the following array. */
1321 static int goal_alt_dont_inherit_ops_num;
1322 /* Numbers of operands whose reload pseudos should not be inherited. */
1323 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1324 /* True if the insn commutative operands should be swapped. */
1325 static bool goal_alt_swapped;
1326 /* The chosen insn alternative. */
1327 static int goal_alt_number;
1329 /* True if the corresponding operand is the result of an equivalence
1330 substitution. */
1331 static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1333 /* The following five variables are used to choose the best insn
1334 alternative. They reflect final characteristics of the best
1335 alternative. */
1337 /* Number of necessary reloads and overall cost reflecting the
1338 previous value and other unpleasantness of the best alternative. */
1339 static int best_losers, best_overall;
1340 /* Overall number hard registers used for reloads. For example, on
1341 some targets we need 2 general registers to reload DFmode and only
1342 one floating point register. */
1343 static int best_reload_nregs;
1344 /* Overall number reflecting distances of previous reloading the same
1345 value. The distances are counted from the current BB start. It is
1346 used to improve inheritance chances. */
1347 static int best_reload_sum;
1349 /* True if the current insn should have no correspondingly input or
1350 output reloads. */
1351 static bool no_input_reloads_p, no_output_reloads_p;
1353 /* True if we swapped the commutative operands in the current
1354 insn. */
1355 static int curr_swapped;
1357 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1358 register of class CL. Add any input reloads to list BEFORE. AFTER
1359 is nonnull if *LOC is an automodified value; handle that case by
1360 adding the required output reloads to list AFTER. Return true if
1361 the RTL was changed.
1363 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1364 register. Return false if the address register is correct. */
1365 static bool
1366 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1367 enum reg_class cl)
1369 int regno;
1370 enum reg_class rclass, new_class;
1371 rtx reg;
1372 rtx new_reg;
1373 machine_mode mode;
1374 bool subreg_p, before_p = false;
1376 subreg_p = GET_CODE (*loc) == SUBREG;
1377 if (subreg_p)
1379 reg = SUBREG_REG (*loc);
1380 mode = GET_MODE (reg);
1382 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1383 between two registers with different classes, but there normally will
1384 be "mov" which transfers element of vector register into the general
1385 register, and this normally will be a subreg which should be reloaded
1386 as a whole. This is particularly likely to be triggered when
1387 -fno-split-wide-types specified. */
1388 if (!REG_P (reg)
1389 || in_class_p (reg, cl, &new_class)
1390 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1391 loc = &SUBREG_REG (*loc);
1394 reg = *loc;
1395 mode = GET_MODE (reg);
1396 if (! REG_P (reg))
1398 if (check_only_p)
1399 return true;
1400 /* Always reload memory in an address even if the target supports
1401 such addresses. */
1402 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1403 before_p = true;
1405 else
1407 regno = REGNO (reg);
1408 rclass = get_reg_class (regno);
1409 if (! check_only_p
1410 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1412 if (lra_dump_file != NULL)
1414 fprintf (lra_dump_file,
1415 "Changing pseudo %d in address of insn %u on equiv ",
1416 REGNO (reg), INSN_UID (curr_insn));
1417 dump_value_slim (lra_dump_file, *loc, 1);
1418 fprintf (lra_dump_file, "\n");
1420 *loc = copy_rtx (*loc);
1422 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1424 if (check_only_p)
1425 return true;
1426 reg = *loc;
1427 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1428 mode, reg, cl, subreg_p, "address", &new_reg))
1429 before_p = true;
1431 else if (new_class != NO_REGS && rclass != new_class)
1433 if (check_only_p)
1434 return true;
1435 lra_change_class (regno, new_class, " Change to", true);
1436 return false;
1438 else
1439 return false;
1441 if (before_p)
1443 push_to_sequence (*before);
1444 lra_emit_move (new_reg, reg);
1445 *before = get_insns ();
1446 end_sequence ();
1448 *loc = new_reg;
1449 if (after != NULL)
1451 start_sequence ();
1452 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1453 emit_insn (*after);
1454 *after = get_insns ();
1455 end_sequence ();
1457 return true;
1460 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1461 the insn to be inserted before curr insn. AFTER returns the
1462 the insn to be inserted after curr insn. ORIGREG and NEWREG
1463 are the original reg and new reg for reload. */
1464 static void
1465 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1466 rtx newreg)
1468 if (before)
1470 push_to_sequence (*before);
1471 lra_emit_move (newreg, origreg);
1472 *before = get_insns ();
1473 end_sequence ();
1475 if (after)
1477 start_sequence ();
1478 lra_emit_move (origreg, newreg);
1479 emit_insn (*after);
1480 *after = get_insns ();
1481 end_sequence ();
1485 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1486 static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1488 /* Make reloads for subreg in operand NOP with internal subreg mode
1489 REG_MODE, add new reloads for further processing. Return true if
1490 any change was done. */
1491 static bool
1492 simplify_operand_subreg (int nop, machine_mode reg_mode)
1494 int hard_regno, inner_hard_regno;
1495 rtx_insn *before, *after;
1496 machine_mode mode, innermode;
1497 rtx reg, new_reg;
1498 rtx operand = *curr_id->operand_loc[nop];
1499 enum reg_class regclass;
1500 enum op_type type;
1502 before = after = NULL;
1504 if (GET_CODE (operand) != SUBREG)
1505 return false;
1507 mode = GET_MODE (operand);
1508 reg = SUBREG_REG (operand);
1509 innermode = GET_MODE (reg);
1510 type = curr_static_id->operand[nop].type;
1511 if (MEM_P (reg))
1513 const bool addr_was_valid
1514 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1515 alter_subreg (curr_id->operand_loc[nop], false);
1516 rtx subst = *curr_id->operand_loc[nop];
1517 lra_assert (MEM_P (subst));
1518 const bool addr_is_valid = valid_address_p (GET_MODE (subst),
1519 XEXP (subst, 0),
1520 MEM_ADDR_SPACE (subst));
1521 if (!addr_was_valid
1522 || addr_is_valid
1523 || ((get_constraint_type (lookup_constraint
1524 (curr_static_id->operand[nop].constraint))
1525 != CT_SPECIAL_MEMORY)
1526 /* We still can reload address and if the address is
1527 valid, we can remove subreg without reloading its
1528 inner memory. */
1529 && valid_address_p (GET_MODE (subst),
1530 regno_reg_rtx
1531 [ira_class_hard_regs
1532 [base_reg_class (GET_MODE (subst),
1533 MEM_ADDR_SPACE (subst),
1534 ADDRESS, SCRATCH)][0]],
1535 MEM_ADDR_SPACE (subst))))
1537 /* If we change the address for a paradoxical subreg of memory, the
1538 new address might violate the necessary alignment or the access
1539 might be slow; take this into consideration. We need not worry
1540 about accesses beyond allocated memory for paradoxical memory
1541 subregs as we don't substitute such equiv memory (see processing
1542 equivalences in function lra_constraints) and because for spilled
1543 pseudos we allocate stack memory enough for the biggest
1544 corresponding paradoxical subreg.
1546 However, do not blindly simplify a (subreg (mem ...)) for
1547 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1548 data into a register when the inner is narrower than outer or
1549 missing important data from memory when the inner is wider than
1550 outer. This rule only applies to modes that are no wider than
1551 a word.
1553 If valid memory becomes invalid after subreg elimination
1554 and address might be different we still have to reload
1555 memory.
1557 if ((! addr_was_valid
1558 || addr_is_valid
1559 || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode)))
1560 && !(maybe_ne (GET_MODE_PRECISION (mode),
1561 GET_MODE_PRECISION (innermode))
1562 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1563 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1564 && WORD_REGISTER_OPERATIONS)
1565 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1566 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1567 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1568 && targetm.slow_unaligned_access (innermode,
1569 MEM_ALIGN (reg)))))
1570 return true;
1572 *curr_id->operand_loc[nop] = operand;
1574 /* But if the address was not valid, we cannot reload the MEM without
1575 reloading the address first. */
1576 if (!addr_was_valid)
1577 process_address (nop, false, &before, &after);
1579 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1580 enum reg_class rclass
1581 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1582 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1583 reg, rclass, TRUE, "slow/invalid mem", &new_reg))
1585 bool insert_before, insert_after;
1586 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1588 insert_before = (type != OP_OUT
1589 || partial_subreg_p (mode, innermode));
1590 insert_after = type != OP_IN;
1591 insert_move_for_subreg (insert_before ? &before : NULL,
1592 insert_after ? &after : NULL,
1593 reg, new_reg);
1595 SUBREG_REG (operand) = new_reg;
1597 /* Convert to MODE. */
1598 reg = operand;
1599 rclass
1600 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1601 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1602 rclass, TRUE, "slow/invalid mem", &new_reg))
1604 bool insert_before, insert_after;
1605 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1607 insert_before = type != OP_OUT;
1608 insert_after = type != OP_IN;
1609 insert_move_for_subreg (insert_before ? &before : NULL,
1610 insert_after ? &after : NULL,
1611 reg, new_reg);
1613 *curr_id->operand_loc[nop] = new_reg;
1614 lra_process_new_insns (curr_insn, before, after,
1615 "Inserting slow/invalid mem reload");
1616 return true;
1619 /* If the address was valid and became invalid, prefer to reload
1620 the memory. Typical case is when the index scale should
1621 correspond the memory. */
1622 *curr_id->operand_loc[nop] = operand;
1623 /* Do not return false here as the MEM_P (reg) will be processed
1624 later in this function. */
1626 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1628 alter_subreg (curr_id->operand_loc[nop], false);
1629 return true;
1631 else if (CONSTANT_P (reg))
1633 /* Try to simplify subreg of constant. It is usually result of
1634 equivalence substitution. */
1635 if (innermode == VOIDmode
1636 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1637 innermode = curr_static_id->operand[nop].mode;
1638 if ((new_reg = simplify_subreg (mode, reg, innermode,
1639 SUBREG_BYTE (operand))) != NULL_RTX)
1641 *curr_id->operand_loc[nop] = new_reg;
1642 return true;
1645 /* Put constant into memory when we have mixed modes. It generates
1646 a better code in most cases as it does not need a secondary
1647 reload memory. It also prevents LRA looping when LRA is using
1648 secondary reload memory again and again. */
1649 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1650 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1652 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1653 alter_subreg (curr_id->operand_loc[nop], false);
1654 return true;
1656 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1657 if there may be a problem accessing OPERAND in the outer
1658 mode. */
1659 if ((REG_P (reg)
1660 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1661 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1662 /* Don't reload paradoxical subregs because we could be looping
1663 having repeatedly final regno out of hard regs range. */
1664 && (hard_regno_nregs (hard_regno, innermode)
1665 >= hard_regno_nregs (hard_regno, mode))
1666 && simplify_subreg_regno (hard_regno, innermode,
1667 SUBREG_BYTE (operand), mode) < 0
1668 /* Don't reload subreg for matching reload. It is actually
1669 valid subreg in LRA. */
1670 && ! LRA_SUBREG_P (operand))
1671 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1673 enum reg_class rclass;
1675 if (REG_P (reg))
1676 /* There is a big probability that we will get the same class
1677 for the new pseudo and we will get the same insn which
1678 means infinite looping. So spill the new pseudo. */
1679 rclass = NO_REGS;
1680 else
1681 /* The class will be defined later in curr_insn_transform. */
1682 rclass
1683 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1685 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1686 rclass, TRUE, "subreg reg", &new_reg))
1688 bool insert_before, insert_after;
1689 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1691 insert_before = (type != OP_OUT
1692 || read_modify_subreg_p (operand));
1693 insert_after = (type != OP_IN);
1694 insert_move_for_subreg (insert_before ? &before : NULL,
1695 insert_after ? &after : NULL,
1696 reg, new_reg);
1698 SUBREG_REG (operand) = new_reg;
1699 lra_process_new_insns (curr_insn, before, after,
1700 "Inserting subreg reload");
1701 return true;
1703 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1704 IRA allocates hardreg to the inner pseudo reg according to its mode
1705 instead of the outermode, so the size of the hardreg may not be enough
1706 to contain the outermode operand, in that case we may need to insert
1707 reload for the reg. For the following two types of paradoxical subreg,
1708 we need to insert reload:
1709 1. If the op_type is OP_IN, and the hardreg could not be paired with
1710 other hardreg to contain the outermode operand
1711 (checked by in_hard_reg_set_p), we need to insert the reload.
1712 2. If the op_type is OP_OUT or OP_INOUT.
1714 Here is a paradoxical subreg example showing how the reload is generated:
1716 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1717 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1719 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1720 here, if reg107 is assigned to hardreg R15, because R15 is the last
1721 hardreg, compiler cannot find another hardreg to pair with R15 to
1722 contain TImode data. So we insert a TImode reload reg180 for it.
1723 After reload is inserted:
1725 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1726 (reg:DI 107 [ __comp ])) -1
1727 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1728 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1730 Two reload hard registers will be allocated to reg180 to save TImode data
1731 in LRA_assign.
1733 For LRA pseudos this should normally be handled by the biggest_mode
1734 mechanism. However, it's possible for new uses of an LRA pseudo
1735 to be introduced after we've allocated it, such as when undoing
1736 inheritance, and the allocated register might not then be appropriate
1737 for the new uses. */
1738 else if (REG_P (reg)
1739 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1740 && paradoxical_subreg_p (operand)
1741 && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1742 && ((hard_regno
1743 = simplify_subreg_regno (inner_hard_regno, innermode,
1744 SUBREG_BYTE (operand), mode)) < 0
1745 || ((hard_regno_nregs (inner_hard_regno, innermode)
1746 < hard_regno_nregs (hard_regno, mode))
1747 && (regclass = lra_get_allocno_class (REGNO (reg)))
1748 && (type != OP_IN
1749 || !in_hard_reg_set_p (reg_class_contents[regclass],
1750 mode, hard_regno)
1751 || overlaps_hard_reg_set_p (lra_no_alloc_regs,
1752 mode, hard_regno)))))
1754 /* The class will be defined later in curr_insn_transform. */
1755 enum reg_class rclass
1756 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1758 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1759 rclass, TRUE, "paradoxical subreg", &new_reg))
1761 rtx subreg;
1762 bool insert_before, insert_after;
1764 PUT_MODE (new_reg, mode);
1765 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1766 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1768 insert_before = (type != OP_OUT);
1769 insert_after = (type != OP_IN);
1770 insert_move_for_subreg (insert_before ? &before : NULL,
1771 insert_after ? &after : NULL,
1772 reg, subreg);
1774 SUBREG_REG (operand) = new_reg;
1775 lra_process_new_insns (curr_insn, before, after,
1776 "Inserting paradoxical subreg reload");
1777 return true;
1779 return false;
1782 /* Return TRUE if X refers for a hard register from SET. */
1783 static bool
1784 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1786 int i, j, x_hard_regno;
1787 machine_mode mode;
1788 const char *fmt;
1789 enum rtx_code code;
1791 if (x == NULL_RTX)
1792 return false;
1793 code = GET_CODE (x);
1794 mode = GET_MODE (x);
1796 if (code == SUBREG)
1798 /* For all SUBREGs we want to check whether the full multi-register
1799 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1800 the inner register, for paradoxical SUBREGs this means the
1801 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1802 fine. Use the wider mode for all cases. */
1803 rtx subreg = SUBREG_REG (x);
1804 mode = wider_subreg_mode (x);
1805 if (mode == GET_MODE (subreg))
1807 x = subreg;
1808 code = GET_CODE (x);
1812 if (REG_P (x) || SUBREG_P (x))
1814 x_hard_regno = get_hard_regno (x, true);
1815 return (x_hard_regno >= 0
1816 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1818 if (MEM_P (x))
1820 struct address_info ad;
1822 decompose_mem_address (&ad, x);
1823 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1824 return true;
1825 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1826 return true;
1828 fmt = GET_RTX_FORMAT (code);
1829 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1831 if (fmt[i] == 'e')
1833 if (uses_hard_regs_p (XEXP (x, i), set))
1834 return true;
1836 else if (fmt[i] == 'E')
1838 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1839 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1840 return true;
1843 return false;
1846 /* Return true if OP is a spilled pseudo. */
1847 static inline bool
1848 spilled_pseudo_p (rtx op)
1850 return (REG_P (op)
1851 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1854 /* Return true if X is a general constant. */
1855 static inline bool
1856 general_constant_p (rtx x)
1858 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1861 static bool
1862 reg_in_class_p (rtx reg, enum reg_class cl)
1864 if (cl == NO_REGS)
1865 return get_reg_class (REGNO (reg)) == NO_REGS;
1866 return in_class_p (reg, cl, NULL);
1869 /* Return true if SET of RCLASS contains no hard regs which can be
1870 used in MODE. */
1871 static bool
1872 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1873 HARD_REG_SET &set,
1874 machine_mode mode)
1876 HARD_REG_SET temp;
1878 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1879 temp = set & ~lra_no_alloc_regs;
1880 return (hard_reg_set_subset_p
1881 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1885 /* Used to check validity info about small class input operands. It
1886 should be incremented at start of processing an insn
1887 alternative. */
1888 static unsigned int curr_small_class_check = 0;
1890 /* Update number of used inputs of class OP_CLASS for operand NOP
1891 of alternative NALT. Return true if we have more such class operands
1892 than the number of available regs. */
1893 static bool
1894 update_and_check_small_class_inputs (int nop, int nalt,
1895 enum reg_class op_class)
1897 static unsigned int small_class_check[LIM_REG_CLASSES];
1898 static int small_class_input_nums[LIM_REG_CLASSES];
1900 if (SMALL_REGISTER_CLASS_P (op_class)
1901 /* We are interesting in classes became small because of fixing
1902 some hard regs, e.g. by an user through GCC options. */
1903 && hard_reg_set_intersect_p (reg_class_contents[op_class],
1904 ira_no_alloc_regs)
1905 && (curr_static_id->operand[nop].type != OP_OUT
1906 || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt)))
1908 if (small_class_check[op_class] == curr_small_class_check)
1909 small_class_input_nums[op_class]++;
1910 else
1912 small_class_check[op_class] = curr_small_class_check;
1913 small_class_input_nums[op_class] = 1;
1915 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1916 return true;
1918 return false;
1921 /* Major function to choose the current insn alternative and what
1922 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1923 negative we should consider only this alternative. Return false if
1924 we cannot choose the alternative or find how to reload the
1925 operands. */
1926 static bool
1927 process_alt_operands (int only_alternative)
1929 bool ok_p = false;
1930 int nop, overall, nalt;
1931 int n_alternatives = curr_static_id->n_alternatives;
1932 int n_operands = curr_static_id->n_operands;
1933 /* LOSERS counts the operands that don't fit this alternative and
1934 would require loading. */
1935 int losers;
1936 int addr_losers;
1937 /* REJECT is a count of how undesirable this alternative says it is
1938 if any reloading is required. If the alternative matches exactly
1939 then REJECT is ignored, but otherwise it gets this much counted
1940 against it in addition to the reloading needed. */
1941 int reject;
1942 /* This is defined by '!' or '?' alternative constraint and added to
1943 reject. But in some cases it can be ignored. */
1944 int static_reject;
1945 int op_reject;
1946 /* The number of elements in the following array. */
1947 int early_clobbered_regs_num;
1948 /* Numbers of operands which are early clobber registers. */
1949 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1950 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1951 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1952 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1953 bool curr_alt_win[MAX_RECOG_OPERANDS];
1954 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1955 int curr_alt_matches[MAX_RECOG_OPERANDS];
1956 /* The number of elements in the following array. */
1957 int curr_alt_dont_inherit_ops_num;
1958 /* Numbers of operands whose reload pseudos should not be inherited. */
1959 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1960 rtx op;
1961 /* The register when the operand is a subreg of register, otherwise the
1962 operand itself. */
1963 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1964 /* The register if the operand is a register or subreg of register,
1965 otherwise NULL. */
1966 rtx operand_reg[MAX_RECOG_OPERANDS];
1967 int hard_regno[MAX_RECOG_OPERANDS];
1968 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1969 int reload_nregs, reload_sum;
1970 bool costly_p;
1971 enum reg_class cl;
1973 /* Calculate some data common for all alternatives to speed up the
1974 function. */
1975 for (nop = 0; nop < n_operands; nop++)
1977 rtx reg;
1979 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1980 /* The real hard regno of the operand after the allocation. */
1981 hard_regno[nop] = get_hard_regno (op, true);
1983 operand_reg[nop] = reg = op;
1984 biggest_mode[nop] = GET_MODE (op);
1985 if (GET_CODE (op) == SUBREG)
1987 biggest_mode[nop] = wider_subreg_mode (op);
1988 operand_reg[nop] = reg = SUBREG_REG (op);
1990 if (! REG_P (reg))
1991 operand_reg[nop] = NULL_RTX;
1992 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1993 || ((int) REGNO (reg)
1994 == lra_get_elimination_hard_regno (REGNO (reg))))
1995 no_subreg_reg_operand[nop] = reg;
1996 else
1997 operand_reg[nop] = no_subreg_reg_operand[nop]
1998 /* Just use natural mode for elimination result. It should
1999 be enough for extra constraints hooks. */
2000 = regno_reg_rtx[hard_regno[nop]];
2003 /* The constraints are made of several alternatives. Each operand's
2004 constraint looks like foo,bar,... with commas separating the
2005 alternatives. The first alternatives for all operands go
2006 together, the second alternatives go together, etc.
2008 First loop over alternatives. */
2009 alternative_mask preferred = curr_id->preferred_alternatives;
2010 if (only_alternative >= 0)
2011 preferred &= ALTERNATIVE_BIT (only_alternative);
2013 for (nalt = 0; nalt < n_alternatives; nalt++)
2015 /* Loop over operands for one constraint alternative. */
2016 if (!TEST_BIT (preferred, nalt))
2017 continue;
2019 bool matching_early_clobber[MAX_RECOG_OPERANDS];
2020 curr_small_class_check++;
2021 overall = losers = addr_losers = 0;
2022 static_reject = reject = reload_nregs = reload_sum = 0;
2023 for (nop = 0; nop < n_operands; nop++)
2025 int inc = (curr_static_id
2026 ->operand_alternative[nalt * n_operands + nop].reject);
2027 if (lra_dump_file != NULL && inc != 0)
2028 fprintf (lra_dump_file,
2029 " Staticly defined alt reject+=%d\n", inc);
2030 static_reject += inc;
2031 matching_early_clobber[nop] = 0;
2033 reject += static_reject;
2034 early_clobbered_regs_num = 0;
2036 for (nop = 0; nop < n_operands; nop++)
2038 const char *p;
2039 char *end;
2040 int len, c, m, i, opalt_num, this_alternative_matches;
2041 bool win, did_match, offmemok, early_clobber_p;
2042 /* false => this operand can be reloaded somehow for this
2043 alternative. */
2044 bool badop;
2045 /* true => this operand can be reloaded if the alternative
2046 allows regs. */
2047 bool winreg;
2048 /* True if a constant forced into memory would be OK for
2049 this operand. */
2050 bool constmemok;
2051 enum reg_class this_alternative, this_costly_alternative;
2052 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2053 bool this_alternative_match_win, this_alternative_win;
2054 bool this_alternative_offmemok;
2055 bool scratch_p;
2056 machine_mode mode;
2057 enum constraint_num cn;
2059 opalt_num = nalt * n_operands + nop;
2060 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2062 /* Fast track for no constraints at all. */
2063 curr_alt[nop] = NO_REGS;
2064 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2065 curr_alt_win[nop] = true;
2066 curr_alt_match_win[nop] = false;
2067 curr_alt_offmemok[nop] = false;
2068 curr_alt_matches[nop] = -1;
2069 continue;
2072 op = no_subreg_reg_operand[nop];
2073 mode = curr_operand_mode[nop];
2075 win = did_match = winreg = offmemok = constmemok = false;
2076 badop = true;
2078 early_clobber_p = false;
2079 p = curr_static_id->operand_alternative[opalt_num].constraint;
2081 this_costly_alternative = this_alternative = NO_REGS;
2082 /* We update set of possible hard regs besides its class
2083 because reg class might be inaccurate. For example,
2084 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2085 is translated in HI_REGS because classes are merged by
2086 pairs and there is no accurate intermediate class. */
2087 CLEAR_HARD_REG_SET (this_alternative_set);
2088 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2089 this_alternative_win = false;
2090 this_alternative_match_win = false;
2091 this_alternative_offmemok = false;
2092 this_alternative_matches = -1;
2094 /* An empty constraint should be excluded by the fast
2095 track. */
2096 lra_assert (*p != 0 && *p != ',');
2098 op_reject = 0;
2099 /* Scan this alternative's specs for this operand; set WIN
2100 if the operand fits any letter in this alternative.
2101 Otherwise, clear BADOP if this operand could fit some
2102 letter after reloads, or set WINREG if this operand could
2103 fit after reloads provided the constraint allows some
2104 registers. */
2105 costly_p = false;
2108 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2110 case '\0':
2111 len = 0;
2112 break;
2113 case ',':
2114 c = '\0';
2115 break;
2117 case '&':
2118 early_clobber_p = true;
2119 break;
2121 case '$':
2122 op_reject += LRA_MAX_REJECT;
2123 break;
2124 case '^':
2125 op_reject += LRA_LOSER_COST_FACTOR;
2126 break;
2128 case '#':
2129 /* Ignore rest of this alternative. */
2130 c = '\0';
2131 break;
2133 case '0': case '1': case '2': case '3': case '4':
2134 case '5': case '6': case '7': case '8': case '9':
2136 int m_hregno;
2137 bool match_p;
2139 m = strtoul (p, &end, 10);
2140 p = end;
2141 len = 0;
2142 lra_assert (nop > m);
2144 /* Reject matches if we don't know which operand is
2145 bigger. This situation would arguably be a bug in
2146 an .md pattern, but could also occur in a user asm. */
2147 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2148 GET_MODE_SIZE (biggest_mode[nop])))
2149 break;
2151 /* Don't match wrong asm insn operands for proper
2152 diagnostic later. */
2153 if (INSN_CODE (curr_insn) < 0
2154 && (curr_operand_mode[m] == BLKmode
2155 || curr_operand_mode[nop] == BLKmode)
2156 && curr_operand_mode[m] != curr_operand_mode[nop])
2157 break;
2159 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2160 /* We are supposed to match a previous operand.
2161 If we do, we win if that one did. If we do
2162 not, count both of the operands as losers.
2163 (This is too conservative, since most of the
2164 time only a single reload insn will be needed
2165 to make the two operands win. As a result,
2166 this alternative may be rejected when it is
2167 actually desirable.) */
2168 match_p = false;
2169 if (operands_match_p (*curr_id->operand_loc[nop],
2170 *curr_id->operand_loc[m], m_hregno))
2172 /* We should reject matching of an early
2173 clobber operand if the matching operand is
2174 not dying in the insn. */
2175 if (!TEST_BIT (curr_static_id->operand[m]
2176 .early_clobber_alts, nalt)
2177 || operand_reg[nop] == NULL_RTX
2178 || (find_regno_note (curr_insn, REG_DEAD,
2179 REGNO (op))
2180 || REGNO (op) == REGNO (operand_reg[m])))
2181 match_p = true;
2183 if (match_p)
2185 /* If we are matching a non-offsettable
2186 address where an offsettable address was
2187 expected, then we must reject this
2188 combination, because we can't reload
2189 it. */
2190 if (curr_alt_offmemok[m]
2191 && MEM_P (*curr_id->operand_loc[m])
2192 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2193 continue;
2195 else
2197 /* If the operands do not match and one
2198 operand is INOUT, we can not match them.
2199 Try other possibilities, e.g. other
2200 alternatives or commutative operand
2201 exchange. */
2202 if (curr_static_id->operand[nop].type == OP_INOUT
2203 || curr_static_id->operand[m].type == OP_INOUT)
2204 break;
2205 /* Operands don't match. If the operands are
2206 different user defined explicit hard
2207 registers, then we cannot make them match
2208 when one is early clobber operand. */
2209 if ((REG_P (*curr_id->operand_loc[nop])
2210 || SUBREG_P (*curr_id->operand_loc[nop]))
2211 && (REG_P (*curr_id->operand_loc[m])
2212 || SUBREG_P (*curr_id->operand_loc[m])))
2214 rtx nop_reg = *curr_id->operand_loc[nop];
2215 if (SUBREG_P (nop_reg))
2216 nop_reg = SUBREG_REG (nop_reg);
2217 rtx m_reg = *curr_id->operand_loc[m];
2218 if (SUBREG_P (m_reg))
2219 m_reg = SUBREG_REG (m_reg);
2221 if (REG_P (nop_reg)
2222 && HARD_REGISTER_P (nop_reg)
2223 && REG_USERVAR_P (nop_reg)
2224 && REG_P (m_reg)
2225 && HARD_REGISTER_P (m_reg)
2226 && REG_USERVAR_P (m_reg))
2228 int i;
2230 for (i = 0; i < early_clobbered_regs_num; i++)
2231 if (m == early_clobbered_nops[i])
2232 break;
2233 if (i < early_clobbered_regs_num
2234 || early_clobber_p)
2235 break;
2238 /* Both operands must allow a reload register,
2239 otherwise we cannot make them match. */
2240 if (curr_alt[m] == NO_REGS)
2241 break;
2242 /* Retroactively mark the operand we had to
2243 match as a loser, if it wasn't already and
2244 it wasn't matched to a register constraint
2245 (e.g it might be matched by memory). */
2246 if (curr_alt_win[m]
2247 && (operand_reg[m] == NULL_RTX
2248 || hard_regno[m] < 0))
2250 losers++;
2251 reload_nregs
2252 += (ira_reg_class_max_nregs[curr_alt[m]]
2253 [GET_MODE (*curr_id->operand_loc[m])]);
2256 /* Prefer matching earlyclobber alternative as
2257 it results in less hard regs required for
2258 the insn than a non-matching earlyclobber
2259 alternative. */
2260 if (TEST_BIT (curr_static_id->operand[m]
2261 .early_clobber_alts, nalt))
2263 if (lra_dump_file != NULL)
2264 fprintf
2265 (lra_dump_file,
2266 " %d Matching earlyclobber alt:"
2267 " reject--\n",
2268 nop);
2269 if (!matching_early_clobber[m])
2271 reject--;
2272 matching_early_clobber[m] = 1;
2275 /* Otherwise we prefer no matching
2276 alternatives because it gives more freedom
2277 in RA. */
2278 else if (operand_reg[nop] == NULL_RTX
2279 || (find_regno_note (curr_insn, REG_DEAD,
2280 REGNO (operand_reg[nop]))
2281 == NULL_RTX))
2283 if (lra_dump_file != NULL)
2284 fprintf
2285 (lra_dump_file,
2286 " %d Matching alt: reject+=2\n",
2287 nop);
2288 reject += 2;
2291 /* If we have to reload this operand and some
2292 previous operand also had to match the same
2293 thing as this operand, we don't know how to do
2294 that. */
2295 if (!match_p || !curr_alt_win[m])
2297 for (i = 0; i < nop; i++)
2298 if (curr_alt_matches[i] == m)
2299 break;
2300 if (i < nop)
2301 break;
2303 else
2304 did_match = true;
2306 this_alternative_matches = m;
2307 /* This can be fixed with reloads if the operand
2308 we are supposed to match can be fixed with
2309 reloads. */
2310 badop = false;
2311 this_alternative = curr_alt[m];
2312 this_alternative_set = curr_alt_set[m];
2313 winreg = this_alternative != NO_REGS;
2314 break;
2317 case 'g':
2318 if (MEM_P (op)
2319 || general_constant_p (op)
2320 || spilled_pseudo_p (op))
2321 win = true;
2322 cl = GENERAL_REGS;
2323 goto reg;
2325 default:
2326 cn = lookup_constraint (p);
2327 switch (get_constraint_type (cn))
2329 case CT_REGISTER:
2330 cl = reg_class_for_constraint (cn);
2331 if (cl != NO_REGS)
2332 goto reg;
2333 break;
2335 case CT_CONST_INT:
2336 if (CONST_INT_P (op)
2337 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2338 win = true;
2339 break;
2341 case CT_MEMORY:
2342 if (MEM_P (op)
2343 && satisfies_memory_constraint_p (op, cn))
2344 win = true;
2345 else if (spilled_pseudo_p (op))
2346 win = true;
2348 /* If we didn't already win, we can reload constants
2349 via force_const_mem or put the pseudo value into
2350 memory, or make other memory by reloading the
2351 address like for 'o'. */
2352 if (CONST_POOL_OK_P (mode, op)
2353 || MEM_P (op) || REG_P (op)
2354 /* We can restore the equiv insn by a
2355 reload. */
2356 || equiv_substition_p[nop])
2357 badop = false;
2358 constmemok = true;
2359 offmemok = true;
2360 break;
2362 case CT_ADDRESS:
2363 /* An asm operand with an address constraint
2364 that doesn't satisfy address_operand has
2365 is_address cleared, so that we don't try to
2366 make a non-address fit. */
2367 if (!curr_static_id->operand[nop].is_address)
2368 break;
2369 /* If we didn't already win, we can reload the address
2370 into a base register. */
2371 if (satisfies_address_constraint_p (op, cn))
2372 win = true;
2373 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2374 ADDRESS, SCRATCH);
2375 badop = false;
2376 goto reg;
2378 case CT_FIXED_FORM:
2379 if (constraint_satisfied_p (op, cn))
2380 win = true;
2381 break;
2383 case CT_SPECIAL_MEMORY:
2384 if (MEM_P (op)
2385 && satisfies_memory_constraint_p (op, cn))
2386 win = true;
2387 else if (spilled_pseudo_p (op))
2388 win = true;
2389 break;
2391 break;
2393 reg:
2394 if (mode == BLKmode)
2395 break;
2396 this_alternative = reg_class_subunion[this_alternative][cl];
2397 this_alternative_set |= reg_class_contents[cl];
2398 if (costly_p)
2400 this_costly_alternative
2401 = reg_class_subunion[this_costly_alternative][cl];
2402 this_costly_alternative_set |= reg_class_contents[cl];
2404 winreg = true;
2405 if (REG_P (op))
2407 if (hard_regno[nop] >= 0
2408 && in_hard_reg_set_p (this_alternative_set,
2409 mode, hard_regno[nop]))
2410 win = true;
2411 else if (hard_regno[nop] < 0
2412 && in_class_p (op, this_alternative, NULL))
2413 win = true;
2415 break;
2417 if (c != ' ' && c != '\t')
2418 costly_p = c == '*';
2420 while ((p += len), c);
2422 scratch_p = (operand_reg[nop] != NULL_RTX
2423 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2424 /* Record which operands fit this alternative. */
2425 if (win)
2427 this_alternative_win = true;
2428 if (operand_reg[nop] != NULL_RTX)
2430 if (hard_regno[nop] >= 0)
2432 if (in_hard_reg_set_p (this_costly_alternative_set,
2433 mode, hard_regno[nop]))
2435 if (lra_dump_file != NULL)
2436 fprintf (lra_dump_file,
2437 " %d Costly set: reject++\n",
2438 nop);
2439 reject++;
2442 else
2444 /* Prefer won reg to spilled pseudo under other
2445 equal conditions for possibe inheritance. */
2446 if (! scratch_p)
2448 if (lra_dump_file != NULL)
2449 fprintf
2450 (lra_dump_file,
2451 " %d Non pseudo reload: reject++\n",
2452 nop);
2453 reject++;
2455 if (in_class_p (operand_reg[nop],
2456 this_costly_alternative, NULL))
2458 if (lra_dump_file != NULL)
2459 fprintf
2460 (lra_dump_file,
2461 " %d Non pseudo costly reload:"
2462 " reject++\n",
2463 nop);
2464 reject++;
2467 /* We simulate the behavior of old reload here.
2468 Although scratches need hard registers and it
2469 might result in spilling other pseudos, no reload
2470 insns are generated for the scratches. So it
2471 might cost something but probably less than old
2472 reload pass believes. */
2473 if (scratch_p)
2475 if (lra_dump_file != NULL)
2476 fprintf (lra_dump_file,
2477 " %d Scratch win: reject+=2\n",
2478 nop);
2479 reject += 2;
2483 else if (did_match)
2484 this_alternative_match_win = true;
2485 else
2487 int const_to_mem = 0;
2488 bool no_regs_p;
2490 reject += op_reject;
2491 /* Never do output reload of stack pointer. It makes
2492 impossible to do elimination when SP is changed in
2493 RTL. */
2494 if (op == stack_pointer_rtx && ! frame_pointer_needed
2495 && curr_static_id->operand[nop].type != OP_IN)
2496 goto fail;
2498 /* If this alternative asks for a specific reg class, see if there
2499 is at least one allocatable register in that class. */
2500 no_regs_p
2501 = (this_alternative == NO_REGS
2502 || (hard_reg_set_subset_p
2503 (reg_class_contents[this_alternative],
2504 lra_no_alloc_regs)));
2506 /* For asms, verify that the class for this alternative is possible
2507 for the mode that is specified. */
2508 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2510 int i;
2511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2512 if (targetm.hard_regno_mode_ok (i, mode)
2513 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2514 mode, i))
2515 break;
2516 if (i == FIRST_PSEUDO_REGISTER)
2517 winreg = false;
2520 /* If this operand accepts a register, and if the
2521 register class has at least one allocatable register,
2522 then this operand can be reloaded. */
2523 if (winreg && !no_regs_p)
2524 badop = false;
2526 if (badop)
2528 if (lra_dump_file != NULL)
2529 fprintf (lra_dump_file,
2530 " alt=%d: Bad operand -- refuse\n",
2531 nalt);
2532 goto fail;
2535 if (this_alternative != NO_REGS)
2537 HARD_REG_SET available_regs
2538 = (reg_class_contents[this_alternative]
2539 & ~((ira_prohibited_class_mode_regs
2540 [this_alternative][mode])
2541 | lra_no_alloc_regs));
2542 if (hard_reg_set_empty_p (available_regs))
2544 /* There are no hard regs holding a value of given
2545 mode. */
2546 if (offmemok)
2548 this_alternative = NO_REGS;
2549 if (lra_dump_file != NULL)
2550 fprintf (lra_dump_file,
2551 " %d Using memory because of"
2552 " a bad mode: reject+=2\n",
2553 nop);
2554 reject += 2;
2556 else
2558 if (lra_dump_file != NULL)
2559 fprintf (lra_dump_file,
2560 " alt=%d: Wrong mode -- refuse\n",
2561 nalt);
2562 goto fail;
2567 /* If not assigned pseudo has a class which a subset of
2568 required reg class, it is a less costly alternative
2569 as the pseudo still can get a hard reg of necessary
2570 class. */
2571 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2572 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2573 && ira_class_subset_p[this_alternative][cl])
2575 if (lra_dump_file != NULL)
2576 fprintf
2577 (lra_dump_file,
2578 " %d Super set class reg: reject-=3\n", nop);
2579 reject -= 3;
2582 this_alternative_offmemok = offmemok;
2583 if (this_costly_alternative != NO_REGS)
2585 if (lra_dump_file != NULL)
2586 fprintf (lra_dump_file,
2587 " %d Costly loser: reject++\n", nop);
2588 reject++;
2590 /* If the operand is dying, has a matching constraint,
2591 and satisfies constraints of the matched operand
2592 which failed to satisfy the own constraints, most probably
2593 the reload for this operand will be gone. */
2594 if (this_alternative_matches >= 0
2595 && !curr_alt_win[this_alternative_matches]
2596 && REG_P (op)
2597 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2598 && (hard_regno[nop] >= 0
2599 ? in_hard_reg_set_p (this_alternative_set,
2600 mode, hard_regno[nop])
2601 : in_class_p (op, this_alternative, NULL)))
2603 if (lra_dump_file != NULL)
2604 fprintf
2605 (lra_dump_file,
2606 " %d Dying matched operand reload: reject++\n",
2607 nop);
2608 reject++;
2610 else
2612 /* Strict_low_part requires to reload the register
2613 not the sub-register. In this case we should
2614 check that a final reload hard reg can hold the
2615 value mode. */
2616 if (curr_static_id->operand[nop].strict_low
2617 && REG_P (op)
2618 && hard_regno[nop] < 0
2619 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2620 && ira_class_hard_regs_num[this_alternative] > 0
2621 && (!targetm.hard_regno_mode_ok
2622 (ira_class_hard_regs[this_alternative][0],
2623 GET_MODE (*curr_id->operand_loc[nop]))))
2625 if (lra_dump_file != NULL)
2626 fprintf
2627 (lra_dump_file,
2628 " alt=%d: Strict low subreg reload -- refuse\n",
2629 nalt);
2630 goto fail;
2632 losers++;
2634 if (operand_reg[nop] != NULL_RTX
2635 /* Output operands and matched input operands are
2636 not inherited. The following conditions do not
2637 exactly describe the previous statement but they
2638 are pretty close. */
2639 && curr_static_id->operand[nop].type != OP_OUT
2640 && (this_alternative_matches < 0
2641 || curr_static_id->operand[nop].type != OP_IN))
2643 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2644 (operand_reg[nop])]
2645 .last_reload);
2647 /* The value of reload_sum has sense only if we
2648 process insns in their order. It happens only on
2649 the first constraints sub-pass when we do most of
2650 reload work. */
2651 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2652 reload_sum += last_reload - bb_reload_num;
2654 /* If this is a constant that is reloaded into the
2655 desired class by copying it to memory first, count
2656 that as another reload. This is consistent with
2657 other code and is required to avoid choosing another
2658 alternative when the constant is moved into memory.
2659 Note that the test here is precisely the same as in
2660 the code below that calls force_const_mem. */
2661 if (CONST_POOL_OK_P (mode, op)
2662 && ((targetm.preferred_reload_class
2663 (op, this_alternative) == NO_REGS)
2664 || no_input_reloads_p))
2666 const_to_mem = 1;
2667 if (! no_regs_p)
2668 losers++;
2671 /* Alternative loses if it requires a type of reload not
2672 permitted for this insn. We can always reload
2673 objects with a REG_UNUSED note. */
2674 if ((curr_static_id->operand[nop].type != OP_IN
2675 && no_output_reloads_p
2676 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2677 || (curr_static_id->operand[nop].type != OP_OUT
2678 && no_input_reloads_p && ! const_to_mem)
2679 || (this_alternative_matches >= 0
2680 && (no_input_reloads_p
2681 || (no_output_reloads_p
2682 && (curr_static_id->operand
2683 [this_alternative_matches].type != OP_IN)
2684 && ! find_reg_note (curr_insn, REG_UNUSED,
2685 no_subreg_reg_operand
2686 [this_alternative_matches])))))
2688 if (lra_dump_file != NULL)
2689 fprintf
2690 (lra_dump_file,
2691 " alt=%d: No input/otput reload -- refuse\n",
2692 nalt);
2693 goto fail;
2696 /* Alternative loses if it required class pseudo cannot
2697 hold value of required mode. Such insns can be
2698 described by insn definitions with mode iterators. */
2699 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2700 && ! hard_reg_set_empty_p (this_alternative_set)
2701 /* It is common practice for constraints to use a
2702 class which does not have actually enough regs to
2703 hold the value (e.g. x86 AREG for mode requiring
2704 more one general reg). Therefore we have 2
2705 conditions to check that the reload pseudo cannot
2706 hold the mode value. */
2707 && (!targetm.hard_regno_mode_ok
2708 (ira_class_hard_regs[this_alternative][0],
2709 GET_MODE (*curr_id->operand_loc[nop])))
2710 /* The above condition is not enough as the first
2711 reg in ira_class_hard_regs can be not aligned for
2712 multi-words mode values. */
2713 && (prohibited_class_reg_set_mode_p
2714 (this_alternative, this_alternative_set,
2715 GET_MODE (*curr_id->operand_loc[nop]))))
2717 if (lra_dump_file != NULL)
2718 fprintf (lra_dump_file,
2719 " alt=%d: reload pseudo for op %d "
2720 "cannot hold the mode value -- refuse\n",
2721 nalt, nop);
2722 goto fail;
2725 /* Check strong discouragement of reload of non-constant
2726 into class THIS_ALTERNATIVE. */
2727 if (! CONSTANT_P (op) && ! no_regs_p
2728 && (targetm.preferred_reload_class
2729 (op, this_alternative) == NO_REGS
2730 || (curr_static_id->operand[nop].type == OP_OUT
2731 && (targetm.preferred_output_reload_class
2732 (op, this_alternative) == NO_REGS))))
2734 if (offmemok && REG_P (op))
2736 if (lra_dump_file != NULL)
2737 fprintf
2738 (lra_dump_file,
2739 " %d Spill pseudo into memory: reject+=3\n",
2740 nop);
2741 reject += 3;
2743 else
2745 if (lra_dump_file != NULL)
2746 fprintf
2747 (lra_dump_file,
2748 " %d Non-prefered reload: reject+=%d\n",
2749 nop, LRA_MAX_REJECT);
2750 reject += LRA_MAX_REJECT;
2754 if (! (MEM_P (op) && offmemok)
2755 && ! (const_to_mem && constmemok))
2757 /* We prefer to reload pseudos over reloading other
2758 things, since such reloads may be able to be
2759 eliminated later. So bump REJECT in other cases.
2760 Don't do this in the case where we are forcing a
2761 constant into memory and it will then win since
2762 we don't want to have a different alternative
2763 match then. */
2764 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2766 if (lra_dump_file != NULL)
2767 fprintf
2768 (lra_dump_file,
2769 " %d Non-pseudo reload: reject+=2\n",
2770 nop);
2771 reject += 2;
2774 if (! no_regs_p)
2775 reload_nregs
2776 += ira_reg_class_max_nregs[this_alternative][mode];
2778 if (SMALL_REGISTER_CLASS_P (this_alternative))
2780 if (lra_dump_file != NULL)
2781 fprintf
2782 (lra_dump_file,
2783 " %d Small class reload: reject+=%d\n",
2784 nop, LRA_LOSER_COST_FACTOR / 2);
2785 reject += LRA_LOSER_COST_FACTOR / 2;
2789 /* We are trying to spill pseudo into memory. It is
2790 usually more costly than moving to a hard register
2791 although it might takes the same number of
2792 reloads.
2794 Non-pseudo spill may happen also. Suppose a target allows both
2795 register and memory in the operand constraint alternatives,
2796 then it's typical that an eliminable register has a substition
2797 of "base + offset" which can either be reloaded by a simple
2798 "new_reg <= base + offset" which will match the register
2799 constraint, or a similar reg addition followed by further spill
2800 to and reload from memory which will match the memory
2801 constraint, but this memory spill will be much more costly
2802 usually.
2804 Code below increases the reject for both pseudo and non-pseudo
2805 spill. */
2806 if (no_regs_p
2807 && !(MEM_P (op) && offmemok)
2808 && !(REG_P (op) && hard_regno[nop] < 0))
2810 if (lra_dump_file != NULL)
2811 fprintf
2812 (lra_dump_file,
2813 " %d Spill %spseudo into memory: reject+=3\n",
2814 nop, REG_P (op) ? "" : "Non-");
2815 reject += 3;
2816 if (VECTOR_MODE_P (mode))
2818 /* Spilling vectors into memory is usually more
2819 costly as they contain big values. */
2820 if (lra_dump_file != NULL)
2821 fprintf
2822 (lra_dump_file,
2823 " %d Spill vector pseudo: reject+=2\n",
2824 nop);
2825 reject += 2;
2829 /* When we use an operand requiring memory in given
2830 alternative, the insn should write *and* read the
2831 value to/from memory it is costly in comparison with
2832 an insn alternative which does not use memory
2833 (e.g. register or immediate operand). We exclude
2834 memory operand for such case as we can satisfy the
2835 memory constraints by reloading address. */
2836 if (no_regs_p && offmemok && !MEM_P (op))
2838 if (lra_dump_file != NULL)
2839 fprintf
2840 (lra_dump_file,
2841 " Using memory insn operand %d: reject+=3\n",
2842 nop);
2843 reject += 3;
2846 /* If reload requires moving value through secondary
2847 memory, it will need one more insn at least. */
2848 if (this_alternative != NO_REGS
2849 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2850 && ((curr_static_id->operand[nop].type != OP_OUT
2851 && targetm.secondary_memory_needed (GET_MODE (op), cl,
2852 this_alternative))
2853 || (curr_static_id->operand[nop].type != OP_IN
2854 && (targetm.secondary_memory_needed
2855 (GET_MODE (op), this_alternative, cl)))))
2856 losers++;
2858 if (MEM_P (op) && offmemok)
2859 addr_losers++;
2860 else
2862 /* Input reloads can be inherited more often than
2863 output reloads can be removed, so penalize output
2864 reloads. */
2865 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2867 if (lra_dump_file != NULL)
2868 fprintf
2869 (lra_dump_file,
2870 " %d Non input pseudo reload: reject++\n",
2871 nop);
2872 reject++;
2875 if (curr_static_id->operand[nop].type == OP_INOUT)
2877 if (lra_dump_file != NULL)
2878 fprintf
2879 (lra_dump_file,
2880 " %d Input/Output reload: reject+=%d\n",
2881 nop, LRA_LOSER_COST_FACTOR);
2882 reject += LRA_LOSER_COST_FACTOR;
2887 if (early_clobber_p && ! scratch_p)
2889 if (lra_dump_file != NULL)
2890 fprintf (lra_dump_file,
2891 " %d Early clobber: reject++\n", nop);
2892 reject++;
2894 /* ??? We check early clobbers after processing all operands
2895 (see loop below) and there we update the costs more.
2896 Should we update the cost (may be approximately) here
2897 because of early clobber register reloads or it is a rare
2898 or non-important thing to be worth to do it. */
2899 overall = (losers * LRA_LOSER_COST_FACTOR + reject
2900 - (addr_losers == losers ? static_reject : 0));
2901 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2903 if (lra_dump_file != NULL)
2904 fprintf (lra_dump_file,
2905 " alt=%d,overall=%d,losers=%d -- refuse\n",
2906 nalt, overall, losers);
2907 goto fail;
2910 if (update_and_check_small_class_inputs (nop, nalt,
2911 this_alternative))
2913 if (lra_dump_file != NULL)
2914 fprintf (lra_dump_file,
2915 " alt=%d, not enough small class regs -- refuse\n",
2916 nalt);
2917 goto fail;
2919 curr_alt[nop] = this_alternative;
2920 curr_alt_set[nop] = this_alternative_set;
2921 curr_alt_win[nop] = this_alternative_win;
2922 curr_alt_match_win[nop] = this_alternative_match_win;
2923 curr_alt_offmemok[nop] = this_alternative_offmemok;
2924 curr_alt_matches[nop] = this_alternative_matches;
2926 if (this_alternative_matches >= 0
2927 && !did_match && !this_alternative_win)
2928 curr_alt_win[this_alternative_matches] = false;
2930 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2931 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2934 if (curr_insn_set != NULL_RTX && n_operands == 2
2935 /* Prevent processing non-move insns. */
2936 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2937 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2938 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2939 && REG_P (no_subreg_reg_operand[0])
2940 && REG_P (no_subreg_reg_operand[1])
2941 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2942 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2943 || (! curr_alt_win[0] && curr_alt_win[1]
2944 && REG_P (no_subreg_reg_operand[1])
2945 /* Check that we reload memory not the memory
2946 address. */
2947 && ! (curr_alt_offmemok[0]
2948 && MEM_P (no_subreg_reg_operand[0]))
2949 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2950 || (curr_alt_win[0] && ! curr_alt_win[1]
2951 && REG_P (no_subreg_reg_operand[0])
2952 /* Check that we reload memory not the memory
2953 address. */
2954 && ! (curr_alt_offmemok[1]
2955 && MEM_P (no_subreg_reg_operand[1]))
2956 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2957 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2958 no_subreg_reg_operand[1])
2959 || (targetm.preferred_reload_class
2960 (no_subreg_reg_operand[1],
2961 (enum reg_class) curr_alt[1]) != NO_REGS))
2962 /* If it is a result of recent elimination in move
2963 insn we can transform it into an add still by
2964 using this alternative. */
2965 && GET_CODE (no_subreg_reg_operand[1]) != PLUS
2966 /* Likewise if the source has been replaced with an
2967 equivalent value. This only happens once -- the reload
2968 will use the equivalent value instead of the register it
2969 replaces -- so there should be no danger of cycling. */
2970 && !equiv_substition_p[1])))
2972 /* We have a move insn and a new reload insn will be similar
2973 to the current insn. We should avoid such situation as
2974 it results in LRA cycling. */
2975 if (lra_dump_file != NULL)
2976 fprintf (lra_dump_file,
2977 " Cycle danger: overall += LRA_MAX_REJECT\n");
2978 overall += LRA_MAX_REJECT;
2980 ok_p = true;
2981 curr_alt_dont_inherit_ops_num = 0;
2982 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2984 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2985 HARD_REG_SET temp_set;
2987 i = early_clobbered_nops[nop];
2988 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2989 || hard_regno[i] < 0)
2990 continue;
2991 lra_assert (operand_reg[i] != NULL_RTX);
2992 clobbered_hard_regno = hard_regno[i];
2993 CLEAR_HARD_REG_SET (temp_set);
2994 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2995 first_conflict_j = last_conflict_j = -1;
2996 for (j = 0; j < n_operands; j++)
2997 if (j == i
2998 /* We don't want process insides of match_operator and
2999 match_parallel because otherwise we would process
3000 their operands once again generating a wrong
3001 code. */
3002 || curr_static_id->operand[j].is_operator)
3003 continue;
3004 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
3005 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
3006 continue;
3007 /* If we don't reload j-th operand, check conflicts. */
3008 else if ((curr_alt_win[j] || curr_alt_match_win[j])
3009 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
3011 if (first_conflict_j < 0)
3012 first_conflict_j = j;
3013 last_conflict_j = j;
3014 /* Both the earlyclobber operand and conflicting operand
3015 cannot both be user defined hard registers. */
3016 if (HARD_REGISTER_P (operand_reg[i])
3017 && REG_USERVAR_P (operand_reg[i])
3018 && operand_reg[j] != NULL_RTX
3019 && HARD_REGISTER_P (operand_reg[j])
3020 && REG_USERVAR_P (operand_reg[j]))
3021 fatal_insn ("unable to generate reloads for "
3022 "impossible constraints:", curr_insn);
3024 if (last_conflict_j < 0)
3025 continue;
3027 /* If an earlyclobber operand conflicts with another non-matching
3028 operand (ie, they have been assigned the same hard register),
3029 then it is better to reload the other operand, as there may
3030 exist yet another operand with a matching constraint associated
3031 with the earlyclobber operand. However, if one of the operands
3032 is an explicit use of a hard register, then we must reload the
3033 other non-hard register operand. */
3034 if (HARD_REGISTER_P (operand_reg[i])
3035 || (first_conflict_j == last_conflict_j
3036 && operand_reg[last_conflict_j] != NULL_RTX
3037 && !curr_alt_match_win[last_conflict_j]
3038 && !HARD_REGISTER_P (operand_reg[last_conflict_j])))
3040 curr_alt_win[last_conflict_j] = false;
3041 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
3042 = last_conflict_j;
3043 losers++;
3044 if (lra_dump_file != NULL)
3045 fprintf
3046 (lra_dump_file,
3047 " %d Conflict early clobber reload: reject--\n",
3050 else
3052 /* We need to reload early clobbered register and the
3053 matched registers. */
3054 for (j = 0; j < n_operands; j++)
3055 if (curr_alt_matches[j] == i)
3057 curr_alt_match_win[j] = false;
3058 losers++;
3059 overall += LRA_LOSER_COST_FACTOR;
3061 if (! curr_alt_match_win[i])
3062 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
3063 else
3065 /* Remember pseudos used for match reloads are never
3066 inherited. */
3067 lra_assert (curr_alt_matches[i] >= 0);
3068 curr_alt_win[curr_alt_matches[i]] = false;
3070 curr_alt_win[i] = curr_alt_match_win[i] = false;
3071 losers++;
3072 if (lra_dump_file != NULL)
3073 fprintf
3074 (lra_dump_file,
3075 " %d Matched conflict early clobber reloads: "
3076 "reject--\n",
3079 /* Early clobber was already reflected in REJECT. */
3080 if (!matching_early_clobber[i])
3082 lra_assert (reject > 0);
3083 reject--;
3084 matching_early_clobber[i] = 1;
3086 overall += LRA_LOSER_COST_FACTOR - 1;
3088 if (lra_dump_file != NULL)
3089 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3090 nalt, overall, losers, reload_nregs);
3092 /* If this alternative can be made to work by reloading, and it
3093 needs less reloading than the others checked so far, record
3094 it as the chosen goal for reloading. */
3095 if ((best_losers != 0 && losers == 0)
3096 || (((best_losers == 0 && losers == 0)
3097 || (best_losers != 0 && losers != 0))
3098 && (best_overall > overall
3099 || (best_overall == overall
3100 /* If the cost of the reloads is the same,
3101 prefer alternative which requires minimal
3102 number of reload regs. */
3103 && (reload_nregs < best_reload_nregs
3104 || (reload_nregs == best_reload_nregs
3105 && (best_reload_sum < reload_sum
3106 || (best_reload_sum == reload_sum
3107 && nalt < goal_alt_number))))))))
3109 for (nop = 0; nop < n_operands; nop++)
3111 goal_alt_win[nop] = curr_alt_win[nop];
3112 goal_alt_match_win[nop] = curr_alt_match_win[nop];
3113 goal_alt_matches[nop] = curr_alt_matches[nop];
3114 goal_alt[nop] = curr_alt[nop];
3115 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3117 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3118 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3119 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3120 goal_alt_swapped = curr_swapped;
3121 best_overall = overall;
3122 best_losers = losers;
3123 best_reload_nregs = reload_nregs;
3124 best_reload_sum = reload_sum;
3125 goal_alt_number = nalt;
3127 if (losers == 0)
3128 /* Everything is satisfied. Do not process alternatives
3129 anymore. */
3130 break;
3131 fail:
3134 return ok_p;
3137 /* Make reload base reg from address AD. */
3138 static rtx
3139 base_to_reg (struct address_info *ad)
3141 enum reg_class cl;
3142 int code = -1;
3143 rtx new_inner = NULL_RTX;
3144 rtx new_reg = NULL_RTX;
3145 rtx_insn *insn;
3146 rtx_insn *last_insn = get_last_insn();
3148 lra_assert (ad->disp == ad->disp_term);
3149 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3150 get_index_code (ad));
3151 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3152 cl, "base");
3153 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3154 ad->disp_term == NULL
3155 ? const0_rtx
3156 : *ad->disp_term);
3157 if (!valid_address_p (ad->mode, new_inner, ad->as))
3158 return NULL_RTX;
3159 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3160 code = recog_memoized (insn);
3161 if (code < 0)
3163 delete_insns_since (last_insn);
3164 return NULL_RTX;
3167 return new_inner;
3170 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3171 static rtx
3172 base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3174 enum reg_class cl;
3175 rtx new_reg;
3177 lra_assert (ad->base == ad->base_term);
3178 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3179 get_index_code (ad));
3180 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3181 cl, "base + disp");
3182 lra_emit_add (new_reg, *ad->base_term, disp);
3183 return new_reg;
3186 /* Make reload of index part of address AD. Return the new
3187 pseudo. */
3188 static rtx
3189 index_part_to_reg (struct address_info *ad)
3191 rtx new_reg;
3193 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3194 INDEX_REG_CLASS, "index term");
3195 expand_mult (GET_MODE (*ad->index), *ad->index_term,
3196 GEN_INT (get_index_scale (ad)), new_reg, 1);
3197 return new_reg;
3200 /* Return true if we can add a displacement to address AD, even if that
3201 makes the address invalid. The fix-up code requires any new address
3202 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3203 static bool
3204 can_add_disp_p (struct address_info *ad)
3206 return (!ad->autoinc_p
3207 && ad->segment == NULL
3208 && ad->base == ad->base_term
3209 && ad->disp == ad->disp_term);
3212 /* Make equiv substitution in address AD. Return true if a substitution
3213 was made. */
3214 static bool
3215 equiv_address_substitution (struct address_info *ad)
3217 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3218 poly_int64 disp;
3219 HOST_WIDE_INT scale;
3220 bool change_p;
3222 base_term = strip_subreg (ad->base_term);
3223 if (base_term == NULL)
3224 base_reg = new_base_reg = NULL_RTX;
3225 else
3227 base_reg = *base_term;
3228 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3230 index_term = strip_subreg (ad->index_term);
3231 if (index_term == NULL)
3232 index_reg = new_index_reg = NULL_RTX;
3233 else
3235 index_reg = *index_term;
3236 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3238 if (base_reg == new_base_reg && index_reg == new_index_reg)
3239 return false;
3240 disp = 0;
3241 change_p = false;
3242 if (lra_dump_file != NULL)
3244 fprintf (lra_dump_file, "Changing address in insn %d ",
3245 INSN_UID (curr_insn));
3246 dump_value_slim (lra_dump_file, *ad->outer, 1);
3248 if (base_reg != new_base_reg)
3250 poly_int64 offset;
3251 if (REG_P (new_base_reg))
3253 *base_term = new_base_reg;
3254 change_p = true;
3256 else if (GET_CODE (new_base_reg) == PLUS
3257 && REG_P (XEXP (new_base_reg, 0))
3258 && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3259 && can_add_disp_p (ad))
3261 disp += offset;
3262 *base_term = XEXP (new_base_reg, 0);
3263 change_p = true;
3265 if (ad->base_term2 != NULL)
3266 *ad->base_term2 = *ad->base_term;
3268 if (index_reg != new_index_reg)
3270 poly_int64 offset;
3271 if (REG_P (new_index_reg))
3273 *index_term = new_index_reg;
3274 change_p = true;
3276 else if (GET_CODE (new_index_reg) == PLUS
3277 && REG_P (XEXP (new_index_reg, 0))
3278 && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3279 && can_add_disp_p (ad)
3280 && (scale = get_index_scale (ad)))
3282 disp += offset * scale;
3283 *index_term = XEXP (new_index_reg, 0);
3284 change_p = true;
3287 if (maybe_ne (disp, 0))
3289 if (ad->disp != NULL)
3290 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3291 else
3293 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3294 update_address (ad);
3296 change_p = true;
3298 if (lra_dump_file != NULL)
3300 if (! change_p)
3301 fprintf (lra_dump_file, " -- no change\n");
3302 else
3304 fprintf (lra_dump_file, " on equiv ");
3305 dump_value_slim (lra_dump_file, *ad->outer, 1);
3306 fprintf (lra_dump_file, "\n");
3309 return change_p;
3312 /* Major function to make reloads for an address in operand NOP or
3313 check its correctness (If CHECK_ONLY_P is true). The supported
3314 cases are:
3316 1) an address that existed before LRA started, at which point it
3317 must have been valid. These addresses are subject to elimination
3318 and may have become invalid due to the elimination offset being out
3319 of range.
3321 2) an address created by forcing a constant to memory
3322 (force_const_to_mem). The initial form of these addresses might
3323 not be valid, and it is this function's job to make them valid.
3325 3) a frame address formed from a register and a (possibly zero)
3326 constant offset. As above, these addresses might not be valid and
3327 this function must make them so.
3329 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3330 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3331 address. Return true for any RTL change.
3333 The function is a helper function which does not produce all
3334 transformations (when CHECK_ONLY_P is false) which can be
3335 necessary. It does just basic steps. To do all necessary
3336 transformations use function process_address. */
3337 static bool
3338 process_address_1 (int nop, bool check_only_p,
3339 rtx_insn **before, rtx_insn **after)
3341 struct address_info ad;
3342 rtx new_reg;
3343 HOST_WIDE_INT scale;
3344 rtx op = *curr_id->operand_loc[nop];
3345 const char *constraint = curr_static_id->operand[nop].constraint;
3346 enum constraint_num cn = lookup_constraint (constraint);
3347 bool change_p = false;
3349 if (MEM_P (op)
3350 && GET_MODE (op) == BLKmode
3351 && GET_CODE (XEXP (op, 0)) == SCRATCH)
3352 return false;
3354 if (insn_extra_address_constraint (cn)
3355 /* When we find an asm operand with an address constraint that
3356 doesn't satisfy address_operand to begin with, we clear
3357 is_address, so that we don't try to make a non-address fit.
3358 If the asm statement got this far, it's because other
3359 constraints are available, and we'll use them, disregarding
3360 the unsatisfiable address ones. */
3361 && curr_static_id->operand[nop].is_address)
3362 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3363 /* Do not attempt to decompose arbitrary addresses generated by combine
3364 for asm operands with loose constraints, e.g 'X'. */
3365 else if (MEM_P (op)
3366 && !(INSN_CODE (curr_insn) < 0
3367 && get_constraint_type (cn) == CT_FIXED_FORM
3368 && constraint_satisfied_p (op, cn)))
3369 decompose_mem_address (&ad, op);
3370 else if (GET_CODE (op) == SUBREG
3371 && MEM_P (SUBREG_REG (op)))
3372 decompose_mem_address (&ad, SUBREG_REG (op));
3373 else
3374 return false;
3375 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3376 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3377 when INDEX_REG_CLASS is a single register class. */
3378 if (ad.base_term != NULL
3379 && ad.index_term != NULL
3380 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3381 && REG_P (*ad.base_term)
3382 && REG_P (*ad.index_term)
3383 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3384 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3386 std::swap (ad.base, ad.index);
3387 std::swap (ad.base_term, ad.index_term);
3389 if (! check_only_p)
3390 change_p = equiv_address_substitution (&ad);
3391 if (ad.base_term != NULL
3392 && (process_addr_reg
3393 (ad.base_term, check_only_p, before,
3394 (ad.autoinc_p
3395 && !(REG_P (*ad.base_term)
3396 && find_regno_note (curr_insn, REG_DEAD,
3397 REGNO (*ad.base_term)) != NULL_RTX)
3398 ? after : NULL),
3399 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3400 get_index_code (&ad)))))
3402 change_p = true;
3403 if (ad.base_term2 != NULL)
3404 *ad.base_term2 = *ad.base_term;
3406 if (ad.index_term != NULL
3407 && process_addr_reg (ad.index_term, check_only_p,
3408 before, NULL, INDEX_REG_CLASS))
3409 change_p = true;
3411 /* Target hooks sometimes don't treat extra-constraint addresses as
3412 legitimate address_operands, so handle them specially. */
3413 if (insn_extra_address_constraint (cn)
3414 && satisfies_address_constraint_p (&ad, cn))
3415 return change_p;
3417 if (check_only_p)
3418 return change_p;
3420 /* There are three cases where the shape of *AD.INNER may now be invalid:
3422 1) the original address was valid, but either elimination or
3423 equiv_address_substitution was applied and that made
3424 the address invalid.
3426 2) the address is an invalid symbolic address created by
3427 force_const_to_mem.
3429 3) the address is a frame address with an invalid offset.
3431 4) the address is a frame address with an invalid base.
3433 All these cases involve a non-autoinc address, so there is no
3434 point revalidating other types. */
3435 if (ad.autoinc_p || valid_address_p (op, &ad, cn))
3436 return change_p;
3438 /* Any index existed before LRA started, so we can assume that the
3439 presence and shape of the index is valid. */
3440 push_to_sequence (*before);
3441 lra_assert (ad.disp == ad.disp_term);
3442 if (ad.base == NULL)
3444 if (ad.index == NULL)
3446 rtx_insn *insn;
3447 rtx_insn *last = get_last_insn ();
3448 int code = -1;
3449 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3450 SCRATCH, SCRATCH);
3451 rtx addr = *ad.inner;
3453 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3454 if (HAVE_lo_sum)
3456 /* addr => lo_sum (new_base, addr), case (2) above. */
3457 insn = emit_insn (gen_rtx_SET
3458 (new_reg,
3459 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3460 code = recog_memoized (insn);
3461 if (code >= 0)
3463 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3464 if (!valid_address_p (op, &ad, cn))
3466 /* Try to put lo_sum into register. */
3467 insn = emit_insn (gen_rtx_SET
3468 (new_reg,
3469 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3470 code = recog_memoized (insn);
3471 if (code >= 0)
3473 *ad.inner = new_reg;
3474 if (!valid_address_p (op, &ad, cn))
3476 *ad.inner = addr;
3477 code = -1;
3483 if (code < 0)
3484 delete_insns_since (last);
3487 if (code < 0)
3489 /* addr => new_base, case (2) above. */
3490 lra_emit_move (new_reg, addr);
3492 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3493 insn != NULL_RTX;
3494 insn = NEXT_INSN (insn))
3495 if (recog_memoized (insn) < 0)
3496 break;
3497 if (insn != NULL_RTX)
3499 /* Do nothing if we cannot generate right insns.
3500 This is analogous to reload pass behavior. */
3501 delete_insns_since (last);
3502 end_sequence ();
3503 return false;
3505 *ad.inner = new_reg;
3508 else
3510 /* index * scale + disp => new base + index * scale,
3511 case (1) above. */
3512 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3513 GET_CODE (*ad.index));
3515 lra_assert (INDEX_REG_CLASS != NO_REGS);
3516 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3517 lra_emit_move (new_reg, *ad.disp);
3518 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3519 new_reg, *ad.index);
3522 else if (ad.index == NULL)
3524 int regno;
3525 enum reg_class cl;
3526 rtx set;
3527 rtx_insn *insns, *last_insn;
3528 /* Try to reload base into register only if the base is invalid
3529 for the address but with valid offset, case (4) above. */
3530 start_sequence ();
3531 new_reg = base_to_reg (&ad);
3533 /* base + disp => new base, cases (1) and (3) above. */
3534 /* Another option would be to reload the displacement into an
3535 index register. However, postreload has code to optimize
3536 address reloads that have the same base and different
3537 displacements, so reloading into an index register would
3538 not necessarily be a win. */
3539 if (new_reg == NULL_RTX)
3541 /* See if the target can split the displacement into a
3542 legitimate new displacement from a local anchor. */
3543 gcc_assert (ad.disp == ad.disp_term);
3544 poly_int64 orig_offset;
3545 rtx offset1, offset2;
3546 if (poly_int_rtx_p (*ad.disp, &orig_offset)
3547 && targetm.legitimize_address_displacement (&offset1, &offset2,
3548 orig_offset,
3549 ad.mode))
3551 new_reg = base_plus_disp_to_reg (&ad, offset1);
3552 new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2);
3554 else
3555 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3557 insns = get_insns ();
3558 last_insn = get_last_insn ();
3559 /* If we generated at least two insns, try last insn source as
3560 an address. If we succeed, we generate one less insn. */
3561 if (REG_P (new_reg)
3562 && last_insn != insns
3563 && (set = single_set (last_insn)) != NULL_RTX
3564 && GET_CODE (SET_SRC (set)) == PLUS
3565 && REG_P (XEXP (SET_SRC (set), 0))
3566 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3568 *ad.inner = SET_SRC (set);
3569 if (valid_address_p (op, &ad, cn))
3571 *ad.base_term = XEXP (SET_SRC (set), 0);
3572 *ad.disp_term = XEXP (SET_SRC (set), 1);
3573 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3574 get_index_code (&ad));
3575 regno = REGNO (*ad.base_term);
3576 if (regno >= FIRST_PSEUDO_REGISTER
3577 && cl != lra_get_allocno_class (regno))
3578 lra_change_class (regno, cl, " Change to", true);
3579 new_reg = SET_SRC (set);
3580 delete_insns_since (PREV_INSN (last_insn));
3583 end_sequence ();
3584 emit_insn (insns);
3585 *ad.inner = new_reg;
3587 else if (ad.disp_term != NULL)
3589 /* base + scale * index + disp => new base + scale * index,
3590 case (1) above. */
3591 gcc_assert (ad.disp == ad.disp_term);
3592 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3593 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3594 new_reg, *ad.index);
3596 else if ((scale = get_index_scale (&ad)) == 1)
3598 /* The last transformation to one reg will be made in
3599 curr_insn_transform function. */
3600 end_sequence ();
3601 return false;
3603 else if (scale != 0)
3605 /* base + scale * index => base + new_reg,
3606 case (1) above.
3607 Index part of address may become invalid. For example, we
3608 changed pseudo on the equivalent memory and a subreg of the
3609 pseudo onto the memory of different mode for which the scale is
3610 prohibitted. */
3611 new_reg = index_part_to_reg (&ad);
3612 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3613 *ad.base_term, new_reg);
3615 else
3617 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3618 SCRATCH, SCRATCH);
3619 rtx addr = *ad.inner;
3621 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3622 /* addr => new_base. */
3623 lra_emit_move (new_reg, addr);
3624 *ad.inner = new_reg;
3626 *before = get_insns ();
3627 end_sequence ();
3628 return true;
3631 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3632 Use process_address_1 as a helper function. Return true for any
3633 RTL changes.
3635 If CHECK_ONLY_P is true, just check address correctness. Return
3636 false if the address correct. */
3637 static bool
3638 process_address (int nop, bool check_only_p,
3639 rtx_insn **before, rtx_insn **after)
3641 bool res = false;
3643 while (process_address_1 (nop, check_only_p, before, after))
3645 if (check_only_p)
3646 return true;
3647 res = true;
3649 return res;
3652 /* Emit insns to reload VALUE into a new register. VALUE is an
3653 auto-increment or auto-decrement RTX whose operand is a register or
3654 memory location; so reloading involves incrementing that location.
3655 IN is either identical to VALUE, or some cheaper place to reload
3656 value being incremented/decremented from.
3658 INC_AMOUNT is the number to increment or decrement by (always
3659 positive and ignored for POST_MODIFY/PRE_MODIFY).
3661 Return pseudo containing the result. */
3662 static rtx
3663 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3665 /* REG or MEM to be copied and incremented. */
3666 rtx incloc = XEXP (value, 0);
3667 /* Nonzero if increment after copying. */
3668 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3669 || GET_CODE (value) == POST_MODIFY);
3670 rtx_insn *last;
3671 rtx inc;
3672 rtx_insn *add_insn;
3673 int code;
3674 rtx real_in = in == value ? incloc : in;
3675 rtx result;
3676 bool plus_p = true;
3678 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3680 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3681 || GET_CODE (XEXP (value, 1)) == MINUS);
3682 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3683 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3684 inc = XEXP (XEXP (value, 1), 1);
3686 else
3688 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3689 inc_amount = -inc_amount;
3691 inc = gen_int_mode (inc_amount, GET_MODE (value));
3694 if (! post && REG_P (incloc))
3695 result = incloc;
3696 else
3697 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3698 "INC/DEC result");
3700 if (real_in != result)
3702 /* First copy the location to the result register. */
3703 lra_assert (REG_P (result));
3704 emit_insn (gen_move_insn (result, real_in));
3707 /* We suppose that there are insns to add/sub with the constant
3708 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3709 old reload worked with this assumption. If the assumption
3710 becomes wrong, we should use approach in function
3711 base_plus_disp_to_reg. */
3712 if (in == value)
3714 /* See if we can directly increment INCLOC. */
3715 last = get_last_insn ();
3716 add_insn = emit_insn (plus_p
3717 ? gen_add2_insn (incloc, inc)
3718 : gen_sub2_insn (incloc, inc));
3720 code = recog_memoized (add_insn);
3721 if (code >= 0)
3723 if (! post && result != incloc)
3724 emit_insn (gen_move_insn (result, incloc));
3725 return result;
3727 delete_insns_since (last);
3730 /* If couldn't do the increment directly, must increment in RESULT.
3731 The way we do this depends on whether this is pre- or
3732 post-increment. For pre-increment, copy INCLOC to the reload
3733 register, increment it there, then save back. */
3734 if (! post)
3736 if (real_in != result)
3737 emit_insn (gen_move_insn (result, real_in));
3738 if (plus_p)
3739 emit_insn (gen_add2_insn (result, inc));
3740 else
3741 emit_insn (gen_sub2_insn (result, inc));
3742 if (result != incloc)
3743 emit_insn (gen_move_insn (incloc, result));
3745 else
3747 /* Post-increment.
3749 Because this might be a jump insn or a compare, and because
3750 RESULT may not be available after the insn in an input
3751 reload, we must do the incrementing before the insn being
3752 reloaded for.
3754 We have already copied IN to RESULT. Increment the copy in
3755 RESULT, save that back, then decrement RESULT so it has
3756 the original value. */
3757 if (plus_p)
3758 emit_insn (gen_add2_insn (result, inc));
3759 else
3760 emit_insn (gen_sub2_insn (result, inc));
3761 emit_insn (gen_move_insn (incloc, result));
3762 /* Restore non-modified value for the result. We prefer this
3763 way because it does not require an additional hard
3764 register. */
3765 if (plus_p)
3767 poly_int64 offset;
3768 if (poly_int_rtx_p (inc, &offset))
3769 emit_insn (gen_add2_insn (result,
3770 gen_int_mode (-offset,
3771 GET_MODE (result))));
3772 else
3773 emit_insn (gen_sub2_insn (result, inc));
3775 else
3776 emit_insn (gen_add2_insn (result, inc));
3778 return result;
3781 /* Return true if the current move insn does not need processing as we
3782 already know that it satisfies its constraints. */
3783 static bool
3784 simple_move_p (void)
3786 rtx dest, src;
3787 enum reg_class dclass, sclass;
3789 lra_assert (curr_insn_set != NULL_RTX);
3790 dest = SET_DEST (curr_insn_set);
3791 src = SET_SRC (curr_insn_set);
3793 /* If the instruction has multiple sets we need to process it even if it
3794 is single_set. This can happen if one or more of the SETs are dead.
3795 See PR73650. */
3796 if (multiple_sets (curr_insn))
3797 return false;
3799 return ((dclass = get_op_class (dest)) != NO_REGS
3800 && (sclass = get_op_class (src)) != NO_REGS
3801 /* The backend guarantees that register moves of cost 2
3802 never need reloads. */
3803 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3806 /* Swap operands NOP and NOP + 1. */
3807 static inline void
3808 swap_operands (int nop)
3810 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3811 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3812 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3813 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3814 /* Swap the duplicates too. */
3815 lra_update_dup (curr_id, nop);
3816 lra_update_dup (curr_id, nop + 1);
3819 /* Main entry point of the constraint code: search the body of the
3820 current insn to choose the best alternative. It is mimicking insn
3821 alternative cost calculation model of former reload pass. That is
3822 because machine descriptions were written to use this model. This
3823 model can be changed in future. Make commutative operand exchange
3824 if it is chosen.
3826 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3827 constraints. Return true if any change happened during function
3828 call.
3830 If CHECK_ONLY_P is true then don't do any transformation. Just
3831 check that the insn satisfies all constraints. If the insn does
3832 not satisfy any constraint, return true. */
3833 static bool
3834 curr_insn_transform (bool check_only_p)
3836 int i, j, k;
3837 int n_operands;
3838 int n_alternatives;
3839 int n_outputs;
3840 int commutative;
3841 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3842 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3843 signed char outputs[MAX_RECOG_OPERANDS + 1];
3844 rtx_insn *before, *after;
3845 bool alt_p = false;
3846 /* Flag that the insn has been changed through a transformation. */
3847 bool change_p;
3848 bool sec_mem_p;
3849 bool use_sec_mem_p;
3850 int max_regno_before;
3851 int reused_alternative_num;
3853 curr_insn_set = single_set (curr_insn);
3854 if (curr_insn_set != NULL_RTX && simple_move_p ())
3856 /* We assume that the corresponding insn alternative has no
3857 earlier clobbers. If it is not the case, don't define move
3858 cost equal to 2 for the corresponding register classes. */
3859 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT);
3860 return false;
3863 no_input_reloads_p = no_output_reloads_p = false;
3864 goal_alt_number = -1;
3865 change_p = sec_mem_p = false;
3866 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3867 reloads; neither are insns that SET cc0. Insns that use CC0 are
3868 not allowed to have any input reloads. */
3869 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3870 no_output_reloads_p = true;
3872 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3873 no_input_reloads_p = true;
3874 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3875 no_output_reloads_p = true;
3877 n_operands = curr_static_id->n_operands;
3878 n_alternatives = curr_static_id->n_alternatives;
3880 /* Just return "no reloads" if insn has no operands with
3881 constraints. */
3882 if (n_operands == 0 || n_alternatives == 0)
3883 return false;
3885 max_regno_before = max_reg_num ();
3887 for (i = 0; i < n_operands; i++)
3889 goal_alt_matched[i][0] = -1;
3890 goal_alt_matches[i] = -1;
3893 commutative = curr_static_id->commutative;
3895 /* Now see what we need for pseudos that didn't get hard regs or got
3896 the wrong kind of hard reg. For this, we must consider all the
3897 operands together against the register constraints. */
3899 best_losers = best_overall = INT_MAX;
3900 best_reload_sum = 0;
3902 curr_swapped = false;
3903 goal_alt_swapped = false;
3905 if (! check_only_p)
3906 /* Make equivalence substitution and memory subreg elimination
3907 before address processing because an address legitimacy can
3908 depend on memory mode. */
3909 for (i = 0; i < n_operands; i++)
3911 rtx op, subst, old;
3912 bool op_change_p = false;
3914 if (curr_static_id->operand[i].is_operator)
3915 continue;
3917 old = op = *curr_id->operand_loc[i];
3918 if (GET_CODE (old) == SUBREG)
3919 old = SUBREG_REG (old);
3920 subst = get_equiv_with_elimination (old, curr_insn);
3921 original_subreg_reg_mode[i] = VOIDmode;
3922 equiv_substition_p[i] = false;
3923 if (subst != old)
3925 equiv_substition_p[i] = true;
3926 subst = copy_rtx (subst);
3927 lra_assert (REG_P (old));
3928 if (GET_CODE (op) != SUBREG)
3929 *curr_id->operand_loc[i] = subst;
3930 else
3932 SUBREG_REG (op) = subst;
3933 if (GET_MODE (subst) == VOIDmode)
3934 original_subreg_reg_mode[i] = GET_MODE (old);
3936 if (lra_dump_file != NULL)
3938 fprintf (lra_dump_file,
3939 "Changing pseudo %d in operand %i of insn %u on equiv ",
3940 REGNO (old), i, INSN_UID (curr_insn));
3941 dump_value_slim (lra_dump_file, subst, 1);
3942 fprintf (lra_dump_file, "\n");
3944 op_change_p = change_p = true;
3946 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3948 change_p = true;
3949 lra_update_dup (curr_id, i);
3953 /* Reload address registers and displacements. We do it before
3954 finding an alternative because of memory constraints. */
3955 before = after = NULL;
3956 for (i = 0; i < n_operands; i++)
3957 if (! curr_static_id->operand[i].is_operator
3958 && process_address (i, check_only_p, &before, &after))
3960 if (check_only_p)
3961 return true;
3962 change_p = true;
3963 lra_update_dup (curr_id, i);
3966 if (change_p)
3967 /* If we've changed the instruction then any alternative that
3968 we chose previously may no longer be valid. */
3969 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT);
3971 if (! check_only_p && curr_insn_set != NULL_RTX
3972 && check_and_process_move (&change_p, &sec_mem_p))
3973 return change_p;
3975 try_swapped:
3977 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative;
3978 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3979 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3980 reused_alternative_num, INSN_UID (curr_insn));
3982 if (process_alt_operands (reused_alternative_num))
3983 alt_p = true;
3985 if (check_only_p)
3986 return ! alt_p || best_losers != 0;
3988 /* If insn is commutative (it's safe to exchange a certain pair of
3989 operands) then we need to try each alternative twice, the second
3990 time matching those two operands as if we had exchanged them. To
3991 do this, really exchange them in operands.
3993 If we have just tried the alternatives the second time, return
3994 operands to normal and drop through. */
3996 if (reused_alternative_num < 0 && commutative >= 0)
3998 curr_swapped = !curr_swapped;
3999 if (curr_swapped)
4001 swap_operands (commutative);
4002 goto try_swapped;
4004 else
4005 swap_operands (commutative);
4008 if (! alt_p && ! sec_mem_p)
4010 /* No alternative works with reloads?? */
4011 if (INSN_CODE (curr_insn) >= 0)
4012 fatal_insn ("unable to generate reloads for:", curr_insn);
4013 error_for_asm (curr_insn,
4014 "inconsistent operand constraints in an %<asm%>");
4015 lra_asm_error_p = true;
4016 /* Avoid further trouble with this insn. Don't generate use
4017 pattern here as we could use the insn SP offset. */
4018 lra_set_insn_deleted (curr_insn);
4019 return true;
4022 /* If the best alternative is with operands 1 and 2 swapped, swap
4023 them. Update the operand numbers of any reloads already
4024 pushed. */
4026 if (goal_alt_swapped)
4028 if (lra_dump_file != NULL)
4029 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
4030 INSN_UID (curr_insn));
4032 /* Swap the duplicates too. */
4033 swap_operands (commutative);
4034 change_p = true;
4037 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4038 too conservatively. So we use the secondary memory only if there
4039 is no any alternative without reloads. */
4040 use_sec_mem_p = false;
4041 if (! alt_p)
4042 use_sec_mem_p = true;
4043 else if (sec_mem_p)
4045 for (i = 0; i < n_operands; i++)
4046 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
4047 break;
4048 use_sec_mem_p = i < n_operands;
4051 if (use_sec_mem_p)
4053 int in = -1, out = -1;
4054 rtx new_reg, src, dest, rld;
4055 machine_mode sec_mode, rld_mode;
4057 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
4058 dest = SET_DEST (curr_insn_set);
4059 src = SET_SRC (curr_insn_set);
4060 for (i = 0; i < n_operands; i++)
4061 if (*curr_id->operand_loc[i] == dest)
4062 out = i;
4063 else if (*curr_id->operand_loc[i] == src)
4064 in = i;
4065 for (i = 0; i < curr_static_id->n_dups; i++)
4066 if (out < 0 && *curr_id->dup_loc[i] == dest)
4067 out = curr_static_id->dup_num[i];
4068 else if (in < 0 && *curr_id->dup_loc[i] == src)
4069 in = curr_static_id->dup_num[i];
4070 lra_assert (out >= 0 && in >= 0
4071 && curr_static_id->operand[out].type == OP_OUT
4072 && curr_static_id->operand[in].type == OP_IN);
4073 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
4074 rld_mode = GET_MODE (rld);
4075 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
4076 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
4077 NO_REGS, "secondary");
4078 /* If the mode is changed, it should be wider. */
4079 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
4080 if (sec_mode != rld_mode)
4082 /* If the target says specifically to use another mode for
4083 secondary memory moves we cannot reuse the original
4084 insn. */
4085 after = emit_spill_move (false, new_reg, dest);
4086 lra_process_new_insns (curr_insn, NULL, after,
4087 "Inserting the sec. move");
4088 /* We may have non null BEFORE here (e.g. after address
4089 processing. */
4090 push_to_sequence (before);
4091 before = emit_spill_move (true, new_reg, src);
4092 emit_insn (before);
4093 before = get_insns ();
4094 end_sequence ();
4095 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
4096 lra_set_insn_deleted (curr_insn);
4098 else if (dest == rld)
4100 *curr_id->operand_loc[out] = new_reg;
4101 lra_update_dup (curr_id, out);
4102 after = emit_spill_move (false, new_reg, dest);
4103 lra_process_new_insns (curr_insn, NULL, after,
4104 "Inserting the sec. move");
4106 else
4108 *curr_id->operand_loc[in] = new_reg;
4109 lra_update_dup (curr_id, in);
4110 /* See comments above. */
4111 push_to_sequence (before);
4112 before = emit_spill_move (true, new_reg, src);
4113 emit_insn (before);
4114 before = get_insns ();
4115 end_sequence ();
4116 lra_process_new_insns (curr_insn, before, NULL,
4117 "Inserting the sec. move");
4119 lra_update_insn_regno_info (curr_insn);
4120 return true;
4123 lra_assert (goal_alt_number >= 0);
4124 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4126 if (lra_dump_file != NULL)
4128 const char *p;
4130 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4131 goal_alt_number, INSN_UID (curr_insn));
4132 for (i = 0; i < n_operands; i++)
4134 p = (curr_static_id->operand_alternative
4135 [goal_alt_number * n_operands + i].constraint);
4136 if (*p == '\0')
4137 continue;
4138 fprintf (lra_dump_file, " (%d) ", i);
4139 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4140 fputc (*p, lra_dump_file);
4142 if (INSN_CODE (curr_insn) >= 0
4143 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4144 fprintf (lra_dump_file, " {%s}", p);
4145 if (maybe_ne (curr_id->sp_offset, 0))
4147 fprintf (lra_dump_file, " (sp_off=");
4148 print_dec (curr_id->sp_offset, lra_dump_file);
4149 fprintf (lra_dump_file, ")");
4151 fprintf (lra_dump_file, "\n");
4154 /* Right now, for any pair of operands I and J that are required to
4155 match, with J < I, goal_alt_matches[I] is J. Add I to
4156 goal_alt_matched[J]. */
4158 for (i = 0; i < n_operands; i++)
4159 if ((j = goal_alt_matches[i]) >= 0)
4161 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4163 /* We allow matching one output operand and several input
4164 operands. */
4165 lra_assert (k == 0
4166 || (curr_static_id->operand[j].type == OP_OUT
4167 && curr_static_id->operand[i].type == OP_IN
4168 && (curr_static_id->operand
4169 [goal_alt_matched[j][0]].type == OP_IN)));
4170 goal_alt_matched[j][k] = i;
4171 goal_alt_matched[j][k + 1] = -1;
4174 for (i = 0; i < n_operands; i++)
4175 goal_alt_win[i] |= goal_alt_match_win[i];
4177 /* Any constants that aren't allowed and can't be reloaded into
4178 registers are here changed into memory references. */
4179 for (i = 0; i < n_operands; i++)
4180 if (goal_alt_win[i])
4182 int regno;
4183 enum reg_class new_class;
4184 rtx reg = *curr_id->operand_loc[i];
4186 if (GET_CODE (reg) == SUBREG)
4187 reg = SUBREG_REG (reg);
4189 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4191 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4193 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4195 lra_assert (ok_p);
4196 lra_change_class (regno, new_class, " Change to", true);
4200 else
4202 const char *constraint;
4203 char c;
4204 rtx op = *curr_id->operand_loc[i];
4205 rtx subreg = NULL_RTX;
4206 machine_mode mode = curr_operand_mode[i];
4208 if (GET_CODE (op) == SUBREG)
4210 subreg = op;
4211 op = SUBREG_REG (op);
4212 mode = GET_MODE (op);
4215 if (CONST_POOL_OK_P (mode, op)
4216 && ((targetm.preferred_reload_class
4217 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4218 || no_input_reloads_p))
4220 rtx tem = force_const_mem (mode, op);
4222 change_p = true;
4223 if (subreg != NULL_RTX)
4224 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4226 *curr_id->operand_loc[i] = tem;
4227 lra_update_dup (curr_id, i);
4228 process_address (i, false, &before, &after);
4230 /* If the alternative accepts constant pool refs directly
4231 there will be no reload needed at all. */
4232 if (subreg != NULL_RTX)
4233 continue;
4234 /* Skip alternatives before the one requested. */
4235 constraint = (curr_static_id->operand_alternative
4236 [goal_alt_number * n_operands + i].constraint);
4237 for (;
4238 (c = *constraint) && c != ',' && c != '#';
4239 constraint += CONSTRAINT_LEN (c, constraint))
4241 enum constraint_num cn = lookup_constraint (constraint);
4242 if ((insn_extra_memory_constraint (cn)
4243 || insn_extra_special_memory_constraint (cn))
4244 && satisfies_memory_constraint_p (tem, cn))
4245 break;
4247 if (c == '\0' || c == ',' || c == '#')
4248 continue;
4250 goal_alt_win[i] = true;
4254 n_outputs = 0;
4255 outputs[0] = -1;
4256 for (i = 0; i < n_operands; i++)
4258 int regno;
4259 bool optional_p = false;
4260 rtx old, new_reg;
4261 rtx op = *curr_id->operand_loc[i];
4263 if (goal_alt_win[i])
4265 if (goal_alt[i] == NO_REGS
4266 && REG_P (op)
4267 /* When we assign NO_REGS it means that we will not
4268 assign a hard register to the scratch pseudo by
4269 assigment pass and the scratch pseudo will be
4270 spilled. Spilled scratch pseudos are transformed
4271 back to scratches at the LRA end. */
4272 && lra_former_scratch_operand_p (curr_insn, i)
4273 && lra_former_scratch_p (REGNO (op)))
4275 int regno = REGNO (op);
4276 lra_change_class (regno, NO_REGS, " Change to", true);
4277 if (lra_get_regno_hard_regno (regno) >= 0)
4278 /* We don't have to mark all insn affected by the
4279 spilled pseudo as there is only one such insn, the
4280 current one. */
4281 reg_renumber[regno] = -1;
4282 lra_assert (bitmap_single_bit_set_p
4283 (&lra_reg_info[REGNO (op)].insn_bitmap));
4285 /* We can do an optional reload. If the pseudo got a hard
4286 reg, we might improve the code through inheritance. If
4287 it does not get a hard register we coalesce memory/memory
4288 moves later. Ignore move insns to avoid cycling. */
4289 if (! lra_simple_p
4290 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4291 && goal_alt[i] != NO_REGS && REG_P (op)
4292 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4293 && regno < new_regno_start
4294 && ! lra_former_scratch_p (regno)
4295 && reg_renumber[regno] < 0
4296 /* Check that the optional reload pseudo will be able to
4297 hold given mode value. */
4298 && ! (prohibited_class_reg_set_mode_p
4299 (goal_alt[i], reg_class_contents[goal_alt[i]],
4300 PSEUDO_REGNO_MODE (regno)))
4301 && (curr_insn_set == NULL_RTX
4302 || !((REG_P (SET_SRC (curr_insn_set))
4303 || MEM_P (SET_SRC (curr_insn_set))
4304 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4305 && (REG_P (SET_DEST (curr_insn_set))
4306 || MEM_P (SET_DEST (curr_insn_set))
4307 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4308 optional_p = true;
4309 else if (goal_alt_matched[i][0] != -1
4310 && curr_static_id->operand[i].type == OP_OUT
4311 && (curr_static_id->operand_alternative
4312 [goal_alt_number * n_operands + i].earlyclobber)
4313 && REG_P (op))
4315 for (j = 0; goal_alt_matched[i][j] != -1; j++)
4317 rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]];
4319 if (REG_P (op2) && REGNO (op) != REGNO (op2))
4320 break;
4322 if (goal_alt_matched[i][j] != -1)
4324 /* Generate reloads for different output and matched
4325 input registers. This is the easiest way to avoid
4326 creation of non-existing register conflicts in
4327 lra-lives.c. */
4328 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4329 &after, TRUE);
4330 outputs[n_outputs++] = i;
4331 outputs[n_outputs] = -1;
4333 continue;
4335 else
4336 continue;
4339 /* Operands that match previous ones have already been handled. */
4340 if (goal_alt_matches[i] >= 0)
4341 continue;
4343 /* We should not have an operand with a non-offsettable address
4344 appearing where an offsettable address will do. It also may
4345 be a case when the address should be special in other words
4346 not a general one (e.g. it needs no index reg). */
4347 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4349 enum reg_class rclass;
4350 rtx *loc = &XEXP (op, 0);
4351 enum rtx_code code = GET_CODE (*loc);
4353 push_to_sequence (before);
4354 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4355 MEM, SCRATCH);
4356 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4357 new_reg = emit_inc (rclass, *loc, *loc,
4358 /* This value does not matter for MODIFY. */
4359 GET_MODE_SIZE (GET_MODE (op)));
4360 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4361 "offsetable address", &new_reg))
4363 rtx addr = *loc;
4364 enum rtx_code code = GET_CODE (addr);
4366 if (code == AND && CONST_INT_P (XEXP (addr, 1)))
4367 /* (and ... (const_int -X)) is used to align to X bytes. */
4368 addr = XEXP (*loc, 0);
4369 lra_emit_move (new_reg, addr);
4370 if (addr != *loc)
4371 emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1)));
4373 before = get_insns ();
4374 end_sequence ();
4375 *loc = new_reg;
4376 lra_update_dup (curr_id, i);
4378 else if (goal_alt_matched[i][0] == -1)
4380 machine_mode mode;
4381 rtx reg, *loc;
4382 int hard_regno;
4383 enum op_type type = curr_static_id->operand[i].type;
4385 loc = curr_id->operand_loc[i];
4386 mode = curr_operand_mode[i];
4387 if (GET_CODE (*loc) == SUBREG)
4389 reg = SUBREG_REG (*loc);
4390 poly_int64 byte = SUBREG_BYTE (*loc);
4391 if (REG_P (reg)
4392 /* Strict_low_part requires reloading the register and not
4393 just the subreg. Likewise for a strict subreg no wider
4394 than a word for WORD_REGISTER_OPERATIONS targets. */
4395 && (curr_static_id->operand[i].strict_low
4396 || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4397 && (hard_regno
4398 = get_try_hard_regno (REGNO (reg))) >= 0
4399 && (simplify_subreg_regno
4400 (hard_regno,
4401 GET_MODE (reg), byte, mode) < 0)
4402 && (goal_alt[i] == NO_REGS
4403 || (simplify_subreg_regno
4404 (ira_class_hard_regs[goal_alt[i]][0],
4405 GET_MODE (reg), byte, mode) >= 0)))
4406 || (partial_subreg_p (mode, GET_MODE (reg))
4407 && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4408 UNITS_PER_WORD)
4409 && WORD_REGISTER_OPERATIONS)))
4411 /* An OP_INOUT is required when reloading a subreg of a
4412 mode wider than a word to ensure that data beyond the
4413 word being reloaded is preserved. Also automatically
4414 ensure that strict_low_part reloads are made into
4415 OP_INOUT which should already be true from the backend
4416 constraints. */
4417 if (type == OP_OUT
4418 && (curr_static_id->operand[i].strict_low
4419 || read_modify_subreg_p (*loc)))
4420 type = OP_INOUT;
4421 loc = &SUBREG_REG (*loc);
4422 mode = GET_MODE (*loc);
4425 old = *loc;
4426 if (get_reload_reg (type, mode, old, goal_alt[i],
4427 loc != curr_id->operand_loc[i], "", &new_reg)
4428 && type != OP_OUT)
4430 push_to_sequence (before);
4431 lra_emit_move (new_reg, old);
4432 before = get_insns ();
4433 end_sequence ();
4435 *loc = new_reg;
4436 if (type != OP_IN
4437 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4439 start_sequence ();
4440 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4441 emit_insn (after);
4442 after = get_insns ();
4443 end_sequence ();
4444 *loc = new_reg;
4446 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4447 if (goal_alt_dont_inherit_ops[j] == i)
4449 lra_set_regno_unique_value (REGNO (new_reg));
4450 break;
4452 lra_update_dup (curr_id, i);
4454 else if (curr_static_id->operand[i].type == OP_IN
4455 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4456 == OP_OUT
4457 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4458 == OP_INOUT
4459 && (operands_match_p
4460 (*curr_id->operand_loc[i],
4461 *curr_id->operand_loc[goal_alt_matched[i][0]],
4462 -1)))))
4464 /* generate reloads for input and matched outputs. */
4465 match_inputs[0] = i;
4466 match_inputs[1] = -1;
4467 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4468 goal_alt[i], &before, &after,
4469 curr_static_id->operand_alternative
4470 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4471 .earlyclobber);
4473 else if ((curr_static_id->operand[i].type == OP_OUT
4474 || (curr_static_id->operand[i].type == OP_INOUT
4475 && (operands_match_p
4476 (*curr_id->operand_loc[i],
4477 *curr_id->operand_loc[goal_alt_matched[i][0]],
4478 -1))))
4479 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4480 == OP_IN))
4481 /* Generate reloads for output and matched inputs. */
4482 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4483 &after, curr_static_id->operand_alternative
4484 [goal_alt_number * n_operands + i].earlyclobber);
4485 else if (curr_static_id->operand[i].type == OP_IN
4486 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4487 == OP_IN))
4489 /* Generate reloads for matched inputs. */
4490 match_inputs[0] = i;
4491 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4492 match_inputs[j + 1] = k;
4493 match_inputs[j + 1] = -1;
4494 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4495 &after, false);
4497 else
4498 /* We must generate code in any case when function
4499 process_alt_operands decides that it is possible. */
4500 gcc_unreachable ();
4502 /* Memorise processed outputs so that output remaining to be processed
4503 can avoid using the same register value (see match_reload). */
4504 if (curr_static_id->operand[i].type == OP_OUT)
4506 outputs[n_outputs++] = i;
4507 outputs[n_outputs] = -1;
4510 if (optional_p)
4512 rtx reg = op;
4514 lra_assert (REG_P (reg));
4515 regno = REGNO (reg);
4516 op = *curr_id->operand_loc[i]; /* Substitution. */
4517 if (GET_CODE (op) == SUBREG)
4518 op = SUBREG_REG (op);
4519 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4520 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4521 lra_reg_info[REGNO (op)].restore_rtx = reg;
4522 if (lra_dump_file != NULL)
4523 fprintf (lra_dump_file,
4524 " Making reload reg %d for reg %d optional\n",
4525 REGNO (op), regno);
4528 if (before != NULL_RTX || after != NULL_RTX
4529 || max_regno_before != max_reg_num ())
4530 change_p = true;
4531 if (change_p)
4533 lra_update_operator_dups (curr_id);
4534 /* Something changes -- process the insn. */
4535 lra_update_insn_regno_info (curr_insn);
4537 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4538 return change_p;
4541 /* Return true if INSN satisfies all constraints. In other words, no
4542 reload insns are needed. */
4543 bool
4544 lra_constrain_insn (rtx_insn *insn)
4546 int saved_new_regno_start = new_regno_start;
4547 int saved_new_insn_uid_start = new_insn_uid_start;
4548 bool change_p;
4550 curr_insn = insn;
4551 curr_id = lra_get_insn_recog_data (curr_insn);
4552 curr_static_id = curr_id->insn_static_data;
4553 new_insn_uid_start = get_max_uid ();
4554 new_regno_start = max_reg_num ();
4555 change_p = curr_insn_transform (true);
4556 new_regno_start = saved_new_regno_start;
4557 new_insn_uid_start = saved_new_insn_uid_start;
4558 return ! change_p;
4561 /* Return true if X is in LIST. */
4562 static bool
4563 in_list_p (rtx x, rtx list)
4565 for (; list != NULL_RTX; list = XEXP (list, 1))
4566 if (XEXP (list, 0) == x)
4567 return true;
4568 return false;
4571 /* Return true if X contains an allocatable hard register (if
4572 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4573 static bool
4574 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4576 int i, j;
4577 const char *fmt;
4578 enum rtx_code code;
4580 code = GET_CODE (x);
4581 if (REG_P (x))
4583 int regno = REGNO (x);
4584 HARD_REG_SET alloc_regs;
4586 if (hard_reg_p)
4588 if (regno >= FIRST_PSEUDO_REGISTER)
4589 regno = lra_get_regno_hard_regno (regno);
4590 if (regno < 0)
4591 return false;
4592 alloc_regs = ~lra_no_alloc_regs;
4593 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4595 else
4597 if (regno < FIRST_PSEUDO_REGISTER)
4598 return false;
4599 if (! spilled_p)
4600 return true;
4601 return lra_get_regno_hard_regno (regno) < 0;
4604 fmt = GET_RTX_FORMAT (code);
4605 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4607 if (fmt[i] == 'e')
4609 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4610 return true;
4612 else if (fmt[i] == 'E')
4614 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4615 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4616 return true;
4619 return false;
4622 /* Process all regs in location *LOC and change them on equivalent
4623 substitution. Return true if any change was done. */
4624 static bool
4625 loc_equivalence_change_p (rtx *loc)
4627 rtx subst, reg, x = *loc;
4628 bool result = false;
4629 enum rtx_code code = GET_CODE (x);
4630 const char *fmt;
4631 int i, j;
4633 if (code == SUBREG)
4635 reg = SUBREG_REG (x);
4636 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4637 && GET_MODE (subst) == VOIDmode)
4639 /* We cannot reload debug location. Simplify subreg here
4640 while we know the inner mode. */
4641 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4642 GET_MODE (reg), SUBREG_BYTE (x));
4643 return true;
4646 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4648 *loc = subst;
4649 return true;
4652 /* Scan all the operand sub-expressions. */
4653 fmt = GET_RTX_FORMAT (code);
4654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4656 if (fmt[i] == 'e')
4657 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4658 else if (fmt[i] == 'E')
4659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4660 result
4661 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4663 return result;
4666 /* Similar to loc_equivalence_change_p, but for use as
4667 simplify_replace_fn_rtx callback. DATA is insn for which the
4668 elimination is done. If it null we don't do the elimination. */
4669 static rtx
4670 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4672 if (!REG_P (loc))
4673 return NULL_RTX;
4675 rtx subst = (data == NULL
4676 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4677 if (subst != loc)
4678 return subst;
4680 return NULL_RTX;
4683 /* Maximum number of generated reload insns per an insn. It is for
4684 preventing this pass cycling in a bug case. */
4685 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4687 /* The current iteration number of this LRA pass. */
4688 int lra_constraint_iter;
4690 /* True if we should during assignment sub-pass check assignment
4691 correctness for all pseudos and spill some of them to correct
4692 conflicts. It can be necessary when we substitute equiv which
4693 needs checking register allocation correctness because the
4694 equivalent value contains allocatable hard registers, or when we
4695 restore multi-register pseudo, or when we change the insn code and
4696 its operand became INOUT operand when it was IN one before. */
4697 bool check_and_force_assignment_correctness_p;
4699 /* Return true if REGNO is referenced in more than one block. */
4700 static bool
4701 multi_block_pseudo_p (int regno)
4703 basic_block bb = NULL;
4704 unsigned int uid;
4705 bitmap_iterator bi;
4707 if (regno < FIRST_PSEUDO_REGISTER)
4708 return false;
4710 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4711 if (bb == NULL)
4712 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4713 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4714 return true;
4715 return false;
4718 /* Return true if LIST contains a deleted insn. */
4719 static bool
4720 contains_deleted_insn_p (rtx_insn_list *list)
4722 for (; list != NULL_RTX; list = list->next ())
4723 if (NOTE_P (list->insn ())
4724 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4725 return true;
4726 return false;
4729 /* Return true if X contains a pseudo dying in INSN. */
4730 static bool
4731 dead_pseudo_p (rtx x, rtx_insn *insn)
4733 int i, j;
4734 const char *fmt;
4735 enum rtx_code code;
4737 if (REG_P (x))
4738 return (insn != NULL_RTX
4739 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4740 code = GET_CODE (x);
4741 fmt = GET_RTX_FORMAT (code);
4742 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4744 if (fmt[i] == 'e')
4746 if (dead_pseudo_p (XEXP (x, i), insn))
4747 return true;
4749 else if (fmt[i] == 'E')
4751 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4752 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4753 return true;
4756 return false;
4759 /* Return true if INSN contains a dying pseudo in INSN right hand
4760 side. */
4761 static bool
4762 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4764 rtx set = single_set (insn);
4766 gcc_assert (set != NULL);
4767 return dead_pseudo_p (SET_SRC (set), insn);
4770 /* Return true if any init insn of REGNO contains a dying pseudo in
4771 insn right hand side. */
4772 static bool
4773 init_insn_rhs_dead_pseudo_p (int regno)
4775 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4777 if (insns == NULL)
4778 return false;
4779 for (; insns != NULL_RTX; insns = insns->next ())
4780 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4781 return true;
4782 return false;
4785 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4786 reverse only if we have one init insn with given REGNO as a
4787 source. */
4788 static bool
4789 reverse_equiv_p (int regno)
4791 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4792 rtx set;
4794 if (insns == NULL)
4795 return false;
4796 if (! INSN_P (insns->insn ())
4797 || insns->next () != NULL)
4798 return false;
4799 if ((set = single_set (insns->insn ())) == NULL_RTX)
4800 return false;
4801 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4804 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4805 call this function only for non-reverse equivalence. */
4806 static bool
4807 contains_reloaded_insn_p (int regno)
4809 rtx set;
4810 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4812 for (; list != NULL; list = list->next ())
4813 if ((set = single_set (list->insn ())) == NULL_RTX
4814 || ! REG_P (SET_DEST (set))
4815 || (int) REGNO (SET_DEST (set)) != regno)
4816 return true;
4817 return false;
4820 /* Entry function of LRA constraint pass. Return true if the
4821 constraint pass did change the code. */
4822 bool
4823 lra_constraints (bool first_p)
4825 bool changed_p;
4826 int i, hard_regno, new_insns_num;
4827 unsigned int min_len, new_min_len, uid;
4828 rtx set, x, reg, dest_reg;
4829 basic_block last_bb;
4830 bitmap_iterator bi;
4832 lra_constraint_iter++;
4833 if (lra_dump_file != NULL)
4834 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4835 lra_constraint_iter);
4836 changed_p = false;
4837 if (pic_offset_table_rtx
4838 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4839 check_and_force_assignment_correctness_p = true;
4840 else if (first_p)
4841 /* On the first iteration we should check IRA assignment
4842 correctness. In rare cases, the assignments can be wrong as
4843 early clobbers operands are ignored in IRA or usages of
4844 paradoxical sub-registers are not taken into account by
4845 IRA. */
4846 check_and_force_assignment_correctness_p = true;
4847 new_insn_uid_start = get_max_uid ();
4848 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4849 /* Mark used hard regs for target stack size calulations. */
4850 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4851 if (lra_reg_info[i].nrefs != 0
4852 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4854 int j, nregs;
4856 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4857 for (j = 0; j < nregs; j++)
4858 df_set_regs_ever_live (hard_regno + j, true);
4860 /* Do elimination before the equivalence processing as we can spill
4861 some pseudos during elimination. */
4862 lra_eliminate (false, first_p);
4863 auto_bitmap equiv_insn_bitmap (&reg_obstack);
4864 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4865 if (lra_reg_info[i].nrefs != 0)
4867 ira_reg_equiv[i].profitable_p = true;
4868 reg = regno_reg_rtx[i];
4869 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4871 bool pseudo_p = contains_reg_p (x, false, false);
4873 /* After RTL transformation, we cannot guarantee that
4874 pseudo in the substitution was not reloaded which might
4875 make equivalence invalid. For example, in reverse
4876 equiv of p0
4878 p0 <- ...
4880 equiv_mem <- p0
4882 the memory address register was reloaded before the 2nd
4883 insn. */
4884 if ((! first_p && pseudo_p)
4885 /* We don't use DF for compilation speed sake. So it
4886 is problematic to update live info when we use an
4887 equivalence containing pseudos in more than one
4888 BB. */
4889 || (pseudo_p && multi_block_pseudo_p (i))
4890 /* If an init insn was deleted for some reason, cancel
4891 the equiv. We could update the equiv insns after
4892 transformations including an equiv insn deletion
4893 but it is not worthy as such cases are extremely
4894 rare. */
4895 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4896 /* If it is not a reverse equivalence, we check that a
4897 pseudo in rhs of the init insn is not dying in the
4898 insn. Otherwise, the live info at the beginning of
4899 the corresponding BB might be wrong after we
4900 removed the insn. When the equiv can be a
4901 constant, the right hand side of the init insn can
4902 be a pseudo. */
4903 || (! reverse_equiv_p (i)
4904 && (init_insn_rhs_dead_pseudo_p (i)
4905 /* If we reloaded the pseudo in an equivalence
4906 init insn, we cannot remove the equiv init
4907 insns and the init insns might write into
4908 const memory in this case. */
4909 || contains_reloaded_insn_p (i)))
4910 /* Prevent access beyond equivalent memory for
4911 paradoxical subregs. */
4912 || (MEM_P (x)
4913 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
4914 GET_MODE_SIZE (GET_MODE (x))))
4915 || (pic_offset_table_rtx
4916 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4917 && (targetm.preferred_reload_class
4918 (x, lra_get_allocno_class (i)) == NO_REGS))
4919 || contains_symbol_ref_p (x))))
4920 ira_reg_equiv[i].defined_p = false;
4921 if (contains_reg_p (x, false, true))
4922 ira_reg_equiv[i].profitable_p = false;
4923 if (get_equiv (reg) != reg)
4924 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4927 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4928 update_equiv (i);
4929 /* We should add all insns containing pseudos which should be
4930 substituted by their equivalences. */
4931 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
4932 lra_push_insn_by_uid (uid);
4933 min_len = lra_insn_stack_length ();
4934 new_insns_num = 0;
4935 last_bb = NULL;
4936 changed_p = false;
4937 while ((new_min_len = lra_insn_stack_length ()) != 0)
4939 curr_insn = lra_pop_insn ();
4940 --new_min_len;
4941 curr_bb = BLOCK_FOR_INSN (curr_insn);
4942 if (curr_bb != last_bb)
4944 last_bb = curr_bb;
4945 bb_reload_num = lra_curr_reload_num;
4947 if (min_len > new_min_len)
4949 min_len = new_min_len;
4950 new_insns_num = 0;
4952 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4953 internal_error
4954 ("maximum number of generated reload insns per insn achieved (%d)",
4955 MAX_RELOAD_INSNS_NUMBER);
4956 new_insns_num++;
4957 if (DEBUG_INSN_P (curr_insn))
4959 /* We need to check equivalence in debug insn and change
4960 pseudo to the equivalent value if necessary. */
4961 curr_id = lra_get_insn_recog_data (curr_insn);
4962 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
4964 rtx old = *curr_id->operand_loc[0];
4965 *curr_id->operand_loc[0]
4966 = simplify_replace_fn_rtx (old, NULL_RTX,
4967 loc_equivalence_callback, curr_insn);
4968 if (old != *curr_id->operand_loc[0])
4970 lra_update_insn_regno_info (curr_insn);
4971 changed_p = true;
4975 else if (INSN_P (curr_insn))
4977 if ((set = single_set (curr_insn)) != NULL_RTX)
4979 dest_reg = SET_DEST (set);
4980 /* The equivalence pseudo could be set up as SUBREG in a
4981 case when it is a call restore insn in a mode
4982 different from the pseudo mode. */
4983 if (GET_CODE (dest_reg) == SUBREG)
4984 dest_reg = SUBREG_REG (dest_reg);
4985 if ((REG_P (dest_reg)
4986 && (x = get_equiv (dest_reg)) != dest_reg
4987 /* Remove insns which set up a pseudo whose value
4988 cannot be changed. Such insns might be not in
4989 init_insns because we don't update equiv data
4990 during insn transformations.
4992 As an example, let suppose that a pseudo got
4993 hard register and on the 1st pass was not
4994 changed to equivalent constant. We generate an
4995 additional insn setting up the pseudo because of
4996 secondary memory movement. Then the pseudo is
4997 spilled and we use the equiv constant. In this
4998 case we should remove the additional insn and
4999 this insn is not init_insns list. */
5000 && (! MEM_P (x) || MEM_READONLY_P (x)
5001 /* Check that this is actually an insn setting
5002 up the equivalence. */
5003 || in_list_p (curr_insn,
5004 ira_reg_equiv
5005 [REGNO (dest_reg)].init_insns)))
5006 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
5007 && in_list_p (curr_insn,
5008 ira_reg_equiv
5009 [REGNO (SET_SRC (set))].init_insns)))
5011 /* This is equiv init insn of pseudo which did not get a
5012 hard register -- remove the insn. */
5013 if (lra_dump_file != NULL)
5015 fprintf (lra_dump_file,
5016 " Removing equiv init insn %i (freq=%d)\n",
5017 INSN_UID (curr_insn),
5018 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
5019 dump_insn_slim (lra_dump_file, curr_insn);
5021 if (contains_reg_p (x, true, false))
5022 check_and_force_assignment_correctness_p = true;
5023 lra_set_insn_deleted (curr_insn);
5024 continue;
5027 curr_id = lra_get_insn_recog_data (curr_insn);
5028 curr_static_id = curr_id->insn_static_data;
5029 init_curr_insn_input_reloads ();
5030 init_curr_operand_mode ();
5031 if (curr_insn_transform (false))
5032 changed_p = true;
5033 /* Check non-transformed insns too for equiv change as USE
5034 or CLOBBER don't need reloads but can contain pseudos
5035 being changed on their equivalences. */
5036 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
5037 && loc_equivalence_change_p (&PATTERN (curr_insn)))
5039 lra_update_insn_regno_info (curr_insn);
5040 changed_p = true;
5045 /* If we used a new hard regno, changed_p should be true because the
5046 hard reg is assigned to a new pseudo. */
5047 if (flag_checking && !changed_p)
5049 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
5050 if (lra_reg_info[i].nrefs != 0
5051 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
5053 int j, nregs = hard_regno_nregs (hard_regno,
5054 PSEUDO_REGNO_MODE (i));
5056 for (j = 0; j < nregs; j++)
5057 lra_assert (df_regs_ever_live_p (hard_regno + j));
5060 return changed_p;
5063 static void initiate_invariants (void);
5064 static void finish_invariants (void);
5066 /* Initiate the LRA constraint pass. It is done once per
5067 function. */
5068 void
5069 lra_constraints_init (void)
5071 initiate_invariants ();
5074 /* Finalize the LRA constraint pass. It is done once per
5075 function. */
5076 void
5077 lra_constraints_finish (void)
5079 finish_invariants ();
5084 /* Structure describes invariants for ineheritance. */
5085 struct lra_invariant
5087 /* The order number of the invariant. */
5088 int num;
5089 /* The invariant RTX. */
5090 rtx invariant_rtx;
5091 /* The origin insn of the invariant. */
5092 rtx_insn *insn;
5095 typedef lra_invariant invariant_t;
5096 typedef invariant_t *invariant_ptr_t;
5097 typedef const invariant_t *const_invariant_ptr_t;
5099 /* Pointer to the inheritance invariants. */
5100 static vec<invariant_ptr_t> invariants;
5102 /* Allocation pool for the invariants. */
5103 static object_allocator<lra_invariant> *invariants_pool;
5105 /* Hash table for the invariants. */
5106 static htab_t invariant_table;
5108 /* Hash function for INVARIANT. */
5109 static hashval_t
5110 invariant_hash (const void *invariant)
5112 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
5113 return lra_rtx_hash (inv);
5116 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5117 static int
5118 invariant_eq_p (const void *invariant1, const void *invariant2)
5120 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
5121 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
5123 return rtx_equal_p (inv1, inv2);
5126 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5127 invariant which is in the table. */
5128 static invariant_ptr_t
5129 insert_invariant (rtx invariant_rtx)
5131 void **entry_ptr;
5132 invariant_t invariant;
5133 invariant_ptr_t invariant_ptr;
5135 invariant.invariant_rtx = invariant_rtx;
5136 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5137 if (*entry_ptr == NULL)
5139 invariant_ptr = invariants_pool->allocate ();
5140 invariant_ptr->invariant_rtx = invariant_rtx;
5141 invariant_ptr->insn = NULL;
5142 invariants.safe_push (invariant_ptr);
5143 *entry_ptr = (void *) invariant_ptr;
5145 return (invariant_ptr_t) *entry_ptr;
5148 /* Initiate the invariant table. */
5149 static void
5150 initiate_invariants (void)
5152 invariants.create (100);
5153 invariants_pool
5154 = new object_allocator<lra_invariant> ("Inheritance invariants");
5155 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5158 /* Finish the invariant table. */
5159 static void
5160 finish_invariants (void)
5162 htab_delete (invariant_table);
5163 delete invariants_pool;
5164 invariants.release ();
5167 /* Make the invariant table empty. */
5168 static void
5169 clear_invariants (void)
5171 htab_empty (invariant_table);
5172 invariants_pool->release ();
5173 invariants.truncate (0);
5178 /* This page contains code to do inheritance/split
5179 transformations. */
5181 /* Number of reloads passed so far in current EBB. */
5182 static int reloads_num;
5184 /* Number of calls passed so far in current EBB. */
5185 static int calls_num;
5187 /* Index ID is the CALLS_NUM associated the last call we saw with
5188 ABI identifier ID. */
5189 static int last_call_for_abi[NUM_ABI_IDS];
5191 /* Which registers have been fully or partially clobbered by a call
5192 since they were last used. */
5193 static HARD_REG_SET full_and_partial_call_clobbers;
5195 /* Current reload pseudo check for validity of elements in
5196 USAGE_INSNS. */
5197 static int curr_usage_insns_check;
5199 /* Info about last usage of registers in EBB to do inheritance/split
5200 transformation. Inheritance transformation is done from a spilled
5201 pseudo and split transformations from a hard register or a pseudo
5202 assigned to a hard register. */
5203 struct usage_insns
5205 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5206 value INSNS is valid. The insns is chain of optional debug insns
5207 and a finishing non-debug insn using the corresponding reg. The
5208 value is also used to mark the registers which are set up in the
5209 current insn. The negated insn uid is used for this. */
5210 int check;
5211 /* Value of global reloads_num at the last insn in INSNS. */
5212 int reloads_num;
5213 /* Value of global reloads_nums at the last insn in INSNS. */
5214 int calls_num;
5215 /* It can be true only for splitting. And it means that the restore
5216 insn should be put after insn given by the following member. */
5217 bool after_p;
5218 /* Next insns in the current EBB which use the original reg and the
5219 original reg value is not changed between the current insn and
5220 the next insns. In order words, e.g. for inheritance, if we need
5221 to use the original reg value again in the next insns we can try
5222 to use the value in a hard register from a reload insn of the
5223 current insn. */
5224 rtx insns;
5227 /* Map: regno -> corresponding pseudo usage insns. */
5228 static struct usage_insns *usage_insns;
5230 static void
5231 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5233 usage_insns[regno].check = curr_usage_insns_check;
5234 usage_insns[regno].insns = insn;
5235 usage_insns[regno].reloads_num = reloads_num;
5236 usage_insns[regno].calls_num = calls_num;
5237 usage_insns[regno].after_p = after_p;
5238 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0)
5239 remove_from_hard_reg_set (&full_and_partial_call_clobbers,
5240 PSEUDO_REGNO_MODE (regno),
5241 reg_renumber[regno]);
5244 /* The function is used to form list REGNO usages which consists of
5245 optional debug insns finished by a non-debug insn using REGNO.
5246 RELOADS_NUM is current number of reload insns processed so far. */
5247 static void
5248 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5250 rtx next_usage_insns;
5252 if (usage_insns[regno].check == curr_usage_insns_check
5253 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5254 && DEBUG_INSN_P (insn))
5256 /* Check that we did not add the debug insn yet. */
5257 if (next_usage_insns != insn
5258 && (GET_CODE (next_usage_insns) != INSN_LIST
5259 || XEXP (next_usage_insns, 0) != insn))
5260 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5261 next_usage_insns);
5263 else if (NONDEBUG_INSN_P (insn))
5264 setup_next_usage_insn (regno, insn, reloads_num, false);
5265 else
5266 usage_insns[regno].check = 0;
5269 /* Return first non-debug insn in list USAGE_INSNS. */
5270 static rtx_insn *
5271 skip_usage_debug_insns (rtx usage_insns)
5273 rtx insn;
5275 /* Skip debug insns. */
5276 for (insn = usage_insns;
5277 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5278 insn = XEXP (insn, 1))
5280 return safe_as_a <rtx_insn *> (insn);
5283 /* Return true if we need secondary memory moves for insn in
5284 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5285 into the insn. */
5286 static bool
5287 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5288 rtx usage_insns ATTRIBUTE_UNUSED)
5290 rtx_insn *insn;
5291 rtx set, dest;
5292 enum reg_class cl;
5294 if (inher_cl == ALL_REGS
5295 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5296 return false;
5297 lra_assert (INSN_P (insn));
5298 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5299 return false;
5300 dest = SET_DEST (set);
5301 if (! REG_P (dest))
5302 return false;
5303 lra_assert (inher_cl != NO_REGS);
5304 cl = get_reg_class (REGNO (dest));
5305 return (cl != NO_REGS && cl != ALL_REGS
5306 && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5309 /* Registers involved in inheritance/split in the current EBB
5310 (inheritance/split pseudos and original registers). */
5311 static bitmap_head check_only_regs;
5313 /* Reload pseudos cannot be involded in invariant inheritance in the
5314 current EBB. */
5315 static bitmap_head invalid_invariant_regs;
5317 /* Do inheritance transformations for insn INSN, which defines (if
5318 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5319 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5320 form as the "insns" field of usage_insns. Return true if we
5321 succeed in such transformation.
5323 The transformations look like:
5325 p <- ... i <- ...
5326 ... p <- i (new insn)
5327 ... =>
5328 <- ... p ... <- ... i ...
5330 ... i <- p (new insn)
5331 <- ... p ... <- ... i ...
5332 ... =>
5333 <- ... p ... <- ... i ...
5334 where p is a spilled original pseudo and i is a new inheritance pseudo.
5337 The inheritance pseudo has the smallest class of two classes CL and
5338 class of ORIGINAL REGNO. */
5339 static bool
5340 inherit_reload_reg (bool def_p, int original_regno,
5341 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5343 if (optimize_function_for_size_p (cfun))
5344 return false;
5346 enum reg_class rclass = lra_get_allocno_class (original_regno);
5347 rtx original_reg = regno_reg_rtx[original_regno];
5348 rtx new_reg, usage_insn;
5349 rtx_insn *new_insns;
5351 lra_assert (! usage_insns[original_regno].after_p);
5352 if (lra_dump_file != NULL)
5353 fprintf (lra_dump_file,
5354 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5355 if (! ira_reg_classes_intersect_p[cl][rclass])
5357 if (lra_dump_file != NULL)
5359 fprintf (lra_dump_file,
5360 " Rejecting inheritance for %d "
5361 "because of disjoint classes %s and %s\n",
5362 original_regno, reg_class_names[cl],
5363 reg_class_names[rclass]);
5364 fprintf (lra_dump_file,
5365 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5367 return false;
5369 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5370 /* We don't use a subset of two classes because it can be
5371 NO_REGS. This transformation is still profitable in most
5372 cases even if the classes are not intersected as register
5373 move is probably cheaper than a memory load. */
5374 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5376 if (lra_dump_file != NULL)
5377 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5378 reg_class_names[cl], reg_class_names[rclass]);
5380 rclass = cl;
5382 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5384 /* Reject inheritance resulting in secondary memory moves.
5385 Otherwise, there is a danger in LRA cycling. Also such
5386 transformation will be unprofitable. */
5387 if (lra_dump_file != NULL)
5389 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5390 rtx set = single_set (insn);
5392 lra_assert (set != NULL_RTX);
5394 rtx dest = SET_DEST (set);
5396 lra_assert (REG_P (dest));
5397 fprintf (lra_dump_file,
5398 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5399 "as secondary mem is needed\n",
5400 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5401 original_regno, reg_class_names[rclass]);
5402 fprintf (lra_dump_file,
5403 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5405 return false;
5407 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5408 rclass, "inheritance");
5409 start_sequence ();
5410 if (def_p)
5411 lra_emit_move (original_reg, new_reg);
5412 else
5413 lra_emit_move (new_reg, original_reg);
5414 new_insns = get_insns ();
5415 end_sequence ();
5416 if (NEXT_INSN (new_insns) != NULL_RTX)
5418 if (lra_dump_file != NULL)
5420 fprintf (lra_dump_file,
5421 " Rejecting inheritance %d->%d "
5422 "as it results in 2 or more insns:\n",
5423 original_regno, REGNO (new_reg));
5424 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5425 fprintf (lra_dump_file,
5426 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5428 return false;
5430 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5431 lra_update_insn_regno_info (insn);
5432 if (! def_p)
5433 /* We now have a new usage insn for original regno. */
5434 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5435 if (lra_dump_file != NULL)
5436 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5437 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5438 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5439 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5440 bitmap_set_bit (&check_only_regs, original_regno);
5441 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5442 if (def_p)
5443 lra_process_new_insns (insn, NULL, new_insns,
5444 "Add original<-inheritance");
5445 else
5446 lra_process_new_insns (insn, new_insns, NULL,
5447 "Add inheritance<-original");
5448 while (next_usage_insns != NULL_RTX)
5450 if (GET_CODE (next_usage_insns) != INSN_LIST)
5452 usage_insn = next_usage_insns;
5453 lra_assert (NONDEBUG_INSN_P (usage_insn));
5454 next_usage_insns = NULL;
5456 else
5458 usage_insn = XEXP (next_usage_insns, 0);
5459 lra_assert (DEBUG_INSN_P (usage_insn));
5460 next_usage_insns = XEXP (next_usage_insns, 1);
5462 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5463 DEBUG_INSN_P (usage_insn));
5464 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5465 if (lra_dump_file != NULL)
5467 basic_block bb = BLOCK_FOR_INSN (usage_insn);
5468 fprintf (lra_dump_file,
5469 " Inheritance reuse change %d->%d (bb%d):\n",
5470 original_regno, REGNO (new_reg),
5471 bb ? bb->index : -1);
5472 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5475 if (lra_dump_file != NULL)
5476 fprintf (lra_dump_file,
5477 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5478 return true;
5481 /* Return true if we need a caller save/restore for pseudo REGNO which
5482 was assigned to a hard register. */
5483 static inline bool
5484 need_for_call_save_p (int regno)
5486 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5487 if (usage_insns[regno].calls_num < calls_num)
5489 unsigned int abis = 0;
5490 for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
5491 if (last_call_for_abi[i] > usage_insns[regno].calls_num)
5492 abis |= 1 << i;
5493 gcc_assert (abis);
5494 if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers,
5495 PSEUDO_REGNO_MODE (regno),
5496 reg_renumber[regno]))
5497 return true;
5499 return false;
5502 /* Global registers occurring in the current EBB. */
5503 static bitmap_head ebb_global_regs;
5505 /* Return true if we need a split for hard register REGNO or pseudo
5506 REGNO which was assigned to a hard register.
5507 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5508 used for reloads since the EBB end. It is an approximation of the
5509 used hard registers in the split range. The exact value would
5510 require expensive calculations. If we were aggressive with
5511 splitting because of the approximation, the split pseudo will save
5512 the same hard register assignment and will be removed in the undo
5513 pass. We still need the approximation because too aggressive
5514 splitting would result in too inaccurate cost calculation in the
5515 assignment pass because of too many generated moves which will be
5516 probably removed in the undo pass. */
5517 static inline bool
5518 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5520 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5522 lra_assert (hard_regno >= 0);
5523 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5524 /* Don't split eliminable hard registers, otherwise we can
5525 split hard registers like hard frame pointer, which
5526 lives on BB start/end according to DF-infrastructure,
5527 when there is a pseudo assigned to the register and
5528 living in the same BB. */
5529 && (regno >= FIRST_PSEUDO_REGISTER
5530 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5531 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5532 /* Don't split call clobbered hard regs living through
5533 calls, otherwise we might have a check problem in the
5534 assign sub-pass as in the most cases (exception is a
5535 situation when check_and_force_assignment_correctness_p value is
5536 true) the assign pass assumes that all pseudos living
5537 through calls are assigned to call saved hard regs. */
5538 && (regno >= FIRST_PSEUDO_REGISTER
5539 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno))
5540 /* We need at least 2 reloads to make pseudo splitting
5541 profitable. We should provide hard regno splitting in
5542 any case to solve 1st insn scheduling problem when
5543 moving hard register definition up might result in
5544 impossibility to find hard register for reload pseudo of
5545 small register class. */
5546 && (usage_insns[regno].reloads_num
5547 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5548 && (regno < FIRST_PSEUDO_REGISTER
5549 /* For short living pseudos, spilling + inheritance can
5550 be considered a substitution for splitting.
5551 Therefore we do not splitting for local pseudos. It
5552 decreases also aggressiveness of splitting. The
5553 minimal number of references is chosen taking into
5554 account that for 2 references splitting has no sense
5555 as we can just spill the pseudo. */
5556 || (regno >= FIRST_PSEUDO_REGISTER
5557 && lra_reg_info[regno].nrefs > 3
5558 && bitmap_bit_p (&ebb_global_regs, regno))))
5559 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5562 /* Return class for the split pseudo created from original pseudo with
5563 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5564 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5565 results in no secondary memory movements. */
5566 static enum reg_class
5567 choose_split_class (enum reg_class allocno_class,
5568 int hard_regno ATTRIBUTE_UNUSED,
5569 machine_mode mode ATTRIBUTE_UNUSED)
5571 int i;
5572 enum reg_class cl, best_cl = NO_REGS;
5573 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5574 = REGNO_REG_CLASS (hard_regno);
5576 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5577 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5578 return allocno_class;
5579 for (i = 0;
5580 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5581 i++)
5582 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5583 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5584 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5585 && (best_cl == NO_REGS
5586 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
5587 best_cl = cl;
5588 return best_cl;
5591 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5592 It only makes sense to call this function if NEW_REGNO is always
5593 equal to ORIGINAL_REGNO. */
5595 static void
5596 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5598 if (!ira_reg_equiv[original_regno].defined_p)
5599 return;
5601 ira_expand_reg_equiv ();
5602 ira_reg_equiv[new_regno].defined_p = true;
5603 if (ira_reg_equiv[original_regno].memory)
5604 ira_reg_equiv[new_regno].memory
5605 = copy_rtx (ira_reg_equiv[original_regno].memory);
5606 if (ira_reg_equiv[original_regno].constant)
5607 ira_reg_equiv[new_regno].constant
5608 = copy_rtx (ira_reg_equiv[original_regno].constant);
5609 if (ira_reg_equiv[original_regno].invariant)
5610 ira_reg_equiv[new_regno].invariant
5611 = copy_rtx (ira_reg_equiv[original_regno].invariant);
5614 /* Do split transformations for insn INSN, which defines or uses
5615 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5616 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5617 "insns" field of usage_insns. If TO is not NULL, we don't use
5618 usage_insns, we put restore insns after TO insn. It is a case when
5619 we call it from lra_split_hard_reg_for, outside the inheritance
5620 pass.
5622 The transformations look like:
5624 p <- ... p <- ...
5625 ... s <- p (new insn -- save)
5626 ... =>
5627 ... p <- s (new insn -- restore)
5628 <- ... p ... <- ... p ...
5630 <- ... p ... <- ... p ...
5631 ... s <- p (new insn -- save)
5632 ... =>
5633 ... p <- s (new insn -- restore)
5634 <- ... p ... <- ... p ...
5636 where p is an original pseudo got a hard register or a hard
5637 register and s is a new split pseudo. The save is put before INSN
5638 if BEFORE_P is true. Return true if we succeed in such
5639 transformation. */
5640 static bool
5641 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5642 rtx next_usage_insns, rtx_insn *to)
5644 enum reg_class rclass;
5645 rtx original_reg;
5646 int hard_regno, nregs;
5647 rtx new_reg, usage_insn;
5648 rtx_insn *restore, *save;
5649 bool after_p;
5650 bool call_save_p;
5651 machine_mode mode;
5653 if (original_regno < FIRST_PSEUDO_REGISTER)
5655 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5656 hard_regno = original_regno;
5657 call_save_p = false;
5658 nregs = 1;
5659 mode = lra_reg_info[hard_regno].biggest_mode;
5660 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5661 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5662 as part of a multi-word register. In that case, or if the biggest
5663 mode was larger than a register, just use the reg_rtx. Otherwise,
5664 limit the size to that of the biggest access in the function. */
5665 if (mode == VOIDmode
5666 || paradoxical_subreg_p (mode, reg_rtx_mode))
5668 original_reg = regno_reg_rtx[hard_regno];
5669 mode = reg_rtx_mode;
5671 else
5672 original_reg = gen_rtx_REG (mode, hard_regno);
5674 else
5676 mode = PSEUDO_REGNO_MODE (original_regno);
5677 hard_regno = reg_renumber[original_regno];
5678 nregs = hard_regno_nregs (hard_regno, mode);
5679 rclass = lra_get_allocno_class (original_regno);
5680 original_reg = regno_reg_rtx[original_regno];
5681 call_save_p = need_for_call_save_p (original_regno);
5683 lra_assert (hard_regno >= 0);
5684 if (lra_dump_file != NULL)
5685 fprintf (lra_dump_file,
5686 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5688 if (call_save_p)
5690 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5691 hard_regno_nregs (hard_regno, mode),
5692 mode);
5693 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5695 else
5697 rclass = choose_split_class (rclass, hard_regno, mode);
5698 if (rclass == NO_REGS)
5700 if (lra_dump_file != NULL)
5702 fprintf (lra_dump_file,
5703 " Rejecting split of %d(%s): "
5704 "no good reg class for %d(%s)\n",
5705 original_regno,
5706 reg_class_names[lra_get_allocno_class (original_regno)],
5707 hard_regno,
5708 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5709 fprintf
5710 (lra_dump_file,
5711 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5713 return false;
5715 /* Split_if_necessary can split hard registers used as part of a
5716 multi-register mode but splits each register individually. The
5717 mode used for each independent register may not be supported
5718 so reject the split. Splitting the wider mode should theoretically
5719 be possible but is not implemented. */
5720 if (!targetm.hard_regno_mode_ok (hard_regno, mode))
5722 if (lra_dump_file != NULL)
5724 fprintf (lra_dump_file,
5725 " Rejecting split of %d(%s): unsuitable mode %s\n",
5726 original_regno,
5727 reg_class_names[lra_get_allocno_class (original_regno)],
5728 GET_MODE_NAME (mode));
5729 fprintf
5730 (lra_dump_file,
5731 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5733 return false;
5735 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5736 reg_renumber[REGNO (new_reg)] = hard_regno;
5738 int new_regno = REGNO (new_reg);
5739 save = emit_spill_move (true, new_reg, original_reg);
5740 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5742 if (lra_dump_file != NULL)
5744 fprintf
5745 (lra_dump_file,
5746 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5747 original_regno, new_regno);
5748 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5749 fprintf (lra_dump_file,
5750 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5752 return false;
5754 restore = emit_spill_move (false, new_reg, original_reg);
5755 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5757 if (lra_dump_file != NULL)
5759 fprintf (lra_dump_file,
5760 " Rejecting split %d->%d "
5761 "resulting in > 2 restore insns:\n",
5762 original_regno, new_regno);
5763 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5764 fprintf (lra_dump_file,
5765 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5767 return false;
5769 /* Transfer equivalence information to the spill register, so that
5770 if we fail to allocate the spill register, we have the option of
5771 rematerializing the original value instead of spilling to the stack. */
5772 if (!HARD_REGISTER_NUM_P (original_regno)
5773 && mode == PSEUDO_REGNO_MODE (original_regno))
5774 lra_copy_reg_equiv (new_regno, original_regno);
5775 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
5776 bitmap_set_bit (&lra_split_regs, new_regno);
5777 if (to != NULL)
5779 lra_assert (next_usage_insns == NULL);
5780 usage_insn = to;
5781 after_p = TRUE;
5783 else
5785 /* We need check_only_regs only inside the inheritance pass. */
5786 bitmap_set_bit (&check_only_regs, new_regno);
5787 bitmap_set_bit (&check_only_regs, original_regno);
5788 after_p = usage_insns[original_regno].after_p;
5789 for (;;)
5791 if (GET_CODE (next_usage_insns) != INSN_LIST)
5793 usage_insn = next_usage_insns;
5794 break;
5796 usage_insn = XEXP (next_usage_insns, 0);
5797 lra_assert (DEBUG_INSN_P (usage_insn));
5798 next_usage_insns = XEXP (next_usage_insns, 1);
5799 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5800 true);
5801 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5802 if (lra_dump_file != NULL)
5804 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5805 original_regno, new_regno);
5806 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5810 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5811 lra_assert (usage_insn != insn || (after_p && before_p));
5812 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5813 after_p ? NULL : restore,
5814 after_p ? restore : NULL,
5815 call_save_p
5816 ? "Add reg<-save" : "Add reg<-split");
5817 lra_process_new_insns (insn, before_p ? save : NULL,
5818 before_p ? NULL : save,
5819 call_save_p
5820 ? "Add save<-reg" : "Add split<-reg");
5821 if (nregs > 1)
5822 /* If we are trying to split multi-register. We should check
5823 conflicts on the next assignment sub-pass. IRA can allocate on
5824 sub-register levels, LRA do this on pseudos level right now and
5825 this discrepancy may create allocation conflicts after
5826 splitting. */
5827 check_and_force_assignment_correctness_p = true;
5828 if (lra_dump_file != NULL)
5829 fprintf (lra_dump_file,
5830 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5831 return true;
5834 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5835 in the range [FROM, TO]. Return true if did a split. Otherwise,
5836 return false. */
5837 bool
5838 spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to)
5840 int i, hard_regno;
5841 int rclass_size;
5842 rtx_insn *insn;
5843 unsigned int uid;
5844 bitmap_iterator bi;
5845 HARD_REG_SET ignore;
5847 lra_assert (from != NULL && to != NULL);
5848 CLEAR_HARD_REG_SET (ignore);
5849 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
5851 lra_insn_recog_data_t id = lra_insn_recog_data[uid];
5852 struct lra_static_insn_data *static_id = id->insn_static_data;
5853 struct lra_insn_reg *reg;
5855 for (reg = id->regs; reg != NULL; reg = reg->next)
5856 if (reg->regno < FIRST_PSEUDO_REGISTER)
5857 SET_HARD_REG_BIT (ignore, reg->regno);
5858 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5859 SET_HARD_REG_BIT (ignore, reg->regno);
5861 rclass_size = ira_class_hard_regs_num[rclass];
5862 for (i = 0; i < rclass_size; i++)
5864 hard_regno = ira_class_hard_regs[rclass][i];
5865 if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
5866 || TEST_HARD_REG_BIT (ignore, hard_regno))
5867 continue;
5868 for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
5870 struct lra_static_insn_data *static_id;
5871 struct lra_insn_reg *reg;
5873 if (!INSN_P (insn))
5874 continue;
5875 if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap,
5876 INSN_UID (insn)))
5877 break;
5878 static_id = lra_get_insn_recog_data (insn)->insn_static_data;
5879 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5880 if (reg->regno == hard_regno)
5881 break;
5882 if (reg != NULL)
5883 break;
5885 if (insn != NEXT_INSN (to))
5886 continue;
5887 if (split_reg (TRUE, hard_regno, from, NULL, to))
5888 return true;
5890 return false;
5893 /* Recognize that we need a split transformation for insn INSN, which
5894 defines or uses REGNO in its insn biggest MODE (we use it only if
5895 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5896 hard registers which might be used for reloads since the EBB end.
5897 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5898 uid before starting INSN processing. Return true if we succeed in
5899 such transformation. */
5900 static bool
5901 split_if_necessary (int regno, machine_mode mode,
5902 HARD_REG_SET potential_reload_hard_regs,
5903 bool before_p, rtx_insn *insn, int max_uid)
5905 bool res = false;
5906 int i, nregs = 1;
5907 rtx next_usage_insns;
5909 if (regno < FIRST_PSEUDO_REGISTER)
5910 nregs = hard_regno_nregs (regno, mode);
5911 for (i = 0; i < nregs; i++)
5912 if (usage_insns[regno + i].check == curr_usage_insns_check
5913 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5914 /* To avoid processing the register twice or more. */
5915 && ((GET_CODE (next_usage_insns) != INSN_LIST
5916 && INSN_UID (next_usage_insns) < max_uid)
5917 || (GET_CODE (next_usage_insns) == INSN_LIST
5918 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5919 && need_for_split_p (potential_reload_hard_regs, regno + i)
5920 && split_reg (before_p, regno + i, insn, next_usage_insns, NULL))
5921 res = true;
5922 return res;
5925 /* Return TRUE if rtx X is considered as an invariant for
5926 inheritance. */
5927 static bool
5928 invariant_p (const_rtx x)
5930 machine_mode mode;
5931 const char *fmt;
5932 enum rtx_code code;
5933 int i, j;
5935 if (side_effects_p (x))
5936 return false;
5938 code = GET_CODE (x);
5939 mode = GET_MODE (x);
5940 if (code == SUBREG)
5942 x = SUBREG_REG (x);
5943 code = GET_CODE (x);
5944 mode = wider_subreg_mode (mode, GET_MODE (x));
5947 if (MEM_P (x))
5948 return false;
5950 if (REG_P (x))
5952 int i, nregs, regno = REGNO (x);
5954 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
5955 || TEST_HARD_REG_BIT (eliminable_regset, regno)
5956 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
5957 return false;
5958 nregs = hard_regno_nregs (regno, mode);
5959 for (i = 0; i < nregs; i++)
5960 if (! fixed_regs[regno + i]
5961 /* A hard register may be clobbered in the current insn
5962 but we can ignore this case because if the hard
5963 register is used it should be set somewhere after the
5964 clobber. */
5965 || bitmap_bit_p (&invalid_invariant_regs, regno + i))
5966 return false;
5968 fmt = GET_RTX_FORMAT (code);
5969 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5971 if (fmt[i] == 'e')
5973 if (! invariant_p (XEXP (x, i)))
5974 return false;
5976 else if (fmt[i] == 'E')
5978 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5979 if (! invariant_p (XVECEXP (x, i, j)))
5980 return false;
5983 return true;
5986 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5987 inheritance transformation (using dest_reg instead invariant in a
5988 subsequent insn). */
5989 static bool
5990 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
5992 invariant_ptr_t invariant_ptr;
5993 rtx_insn *insn, *new_insns;
5994 rtx insn_set, insn_reg, new_reg;
5995 int insn_regno;
5996 bool succ_p = false;
5997 int dst_regno = REGNO (dst_reg);
5998 machine_mode dst_mode = GET_MODE (dst_reg);
5999 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
6001 invariant_ptr = insert_invariant (invariant_rtx);
6002 if ((insn = invariant_ptr->insn) != NULL_RTX)
6004 /* We have a subsequent insn using the invariant. */
6005 insn_set = single_set (insn);
6006 lra_assert (insn_set != NULL);
6007 insn_reg = SET_DEST (insn_set);
6008 lra_assert (REG_P (insn_reg));
6009 insn_regno = REGNO (insn_reg);
6010 insn_reg_cl = lra_get_allocno_class (insn_regno);
6012 if (dst_mode == GET_MODE (insn_reg)
6013 /* We should consider only result move reg insns which are
6014 cheap. */
6015 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
6016 && targetm.register_move_cost (dst_mode, cl, cl) == 2)
6018 if (lra_dump_file != NULL)
6019 fprintf (lra_dump_file,
6020 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6021 new_reg = lra_create_new_reg (dst_mode, dst_reg,
6022 cl, "invariant inheritance");
6023 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
6024 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
6025 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
6026 start_sequence ();
6027 lra_emit_move (new_reg, dst_reg);
6028 new_insns = get_insns ();
6029 end_sequence ();
6030 lra_process_new_insns (curr_insn, NULL, new_insns,
6031 "Add invariant inheritance<-original");
6032 start_sequence ();
6033 lra_emit_move (SET_DEST (insn_set), new_reg);
6034 new_insns = get_insns ();
6035 end_sequence ();
6036 lra_process_new_insns (insn, NULL, new_insns,
6037 "Changing reload<-inheritance");
6038 lra_set_insn_deleted (insn);
6039 succ_p = true;
6040 if (lra_dump_file != NULL)
6042 fprintf (lra_dump_file,
6043 " Invariant inheritance reuse change %d (bb%d):\n",
6044 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
6045 dump_insn_slim (lra_dump_file, insn);
6046 fprintf (lra_dump_file,
6047 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6051 invariant_ptr->insn = curr_insn;
6052 return succ_p;
6055 /* Check only registers living at the current program point in the
6056 current EBB. */
6057 static bitmap_head live_regs;
6059 /* Update live info in EBB given by its HEAD and TAIL insns after
6060 inheritance/split transformation. The function removes dead moves
6061 too. */
6062 static void
6063 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
6065 unsigned int j;
6066 int i, regno;
6067 bool live_p;
6068 rtx_insn *prev_insn;
6069 rtx set;
6070 bool remove_p;
6071 basic_block last_bb, prev_bb, curr_bb;
6072 bitmap_iterator bi;
6073 struct lra_insn_reg *reg;
6074 edge e;
6075 edge_iterator ei;
6077 last_bb = BLOCK_FOR_INSN (tail);
6078 prev_bb = NULL;
6079 for (curr_insn = tail;
6080 curr_insn != PREV_INSN (head);
6081 curr_insn = prev_insn)
6083 prev_insn = PREV_INSN (curr_insn);
6084 /* We need to process empty blocks too. They contain
6085 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6086 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
6087 continue;
6088 curr_bb = BLOCK_FOR_INSN (curr_insn);
6089 if (curr_bb != prev_bb)
6091 if (prev_bb != NULL)
6093 /* Update df_get_live_in (prev_bb): */
6094 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
6095 if (bitmap_bit_p (&live_regs, j))
6096 bitmap_set_bit (df_get_live_in (prev_bb), j);
6097 else
6098 bitmap_clear_bit (df_get_live_in (prev_bb), j);
6100 if (curr_bb != last_bb)
6102 /* Update df_get_live_out (curr_bb): */
6103 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
6105 live_p = bitmap_bit_p (&live_regs, j);
6106 if (! live_p)
6107 FOR_EACH_EDGE (e, ei, curr_bb->succs)
6108 if (bitmap_bit_p (df_get_live_in (e->dest), j))
6110 live_p = true;
6111 break;
6113 if (live_p)
6114 bitmap_set_bit (df_get_live_out (curr_bb), j);
6115 else
6116 bitmap_clear_bit (df_get_live_out (curr_bb), j);
6119 prev_bb = curr_bb;
6120 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
6122 if (! NONDEBUG_INSN_P (curr_insn))
6123 continue;
6124 curr_id = lra_get_insn_recog_data (curr_insn);
6125 curr_static_id = curr_id->insn_static_data;
6126 remove_p = false;
6127 if ((set = single_set (curr_insn)) != NULL_RTX
6128 && REG_P (SET_DEST (set))
6129 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
6130 && SET_DEST (set) != pic_offset_table_rtx
6131 && bitmap_bit_p (&check_only_regs, regno)
6132 && ! bitmap_bit_p (&live_regs, regno))
6133 remove_p = true;
6134 /* See which defined values die here. */
6135 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6136 if (reg->type == OP_OUT && ! reg->subreg_p)
6137 bitmap_clear_bit (&live_regs, reg->regno);
6138 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6139 if (reg->type == OP_OUT && ! reg->subreg_p)
6140 bitmap_clear_bit (&live_regs, reg->regno);
6141 if (curr_id->arg_hard_regs != NULL)
6142 /* Make clobbered argument hard registers die. */
6143 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6144 if (regno >= FIRST_PSEUDO_REGISTER)
6145 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
6146 /* Mark each used value as live. */
6147 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6148 if (reg->type != OP_OUT
6149 && bitmap_bit_p (&check_only_regs, reg->regno))
6150 bitmap_set_bit (&live_regs, reg->regno);
6151 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6152 if (reg->type != OP_OUT
6153 && bitmap_bit_p (&check_only_regs, reg->regno))
6154 bitmap_set_bit (&live_regs, reg->regno);
6155 if (curr_id->arg_hard_regs != NULL)
6156 /* Make used argument hard registers live. */
6157 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6158 if (regno < FIRST_PSEUDO_REGISTER
6159 && bitmap_bit_p (&check_only_regs, regno))
6160 bitmap_set_bit (&live_regs, regno);
6161 /* It is quite important to remove dead move insns because it
6162 means removing dead store. We don't need to process them for
6163 constraints. */
6164 if (remove_p)
6166 if (lra_dump_file != NULL)
6168 fprintf (lra_dump_file, " Removing dead insn:\n ");
6169 dump_insn_slim (lra_dump_file, curr_insn);
6171 lra_set_insn_deleted (curr_insn);
6176 /* The structure describes info to do an inheritance for the current
6177 insn. We need to collect such info first before doing the
6178 transformations because the transformations change the insn
6179 internal representation. */
6180 struct to_inherit
6182 /* Original regno. */
6183 int regno;
6184 /* Subsequent insns which can inherit original reg value. */
6185 rtx insns;
6188 /* Array containing all info for doing inheritance from the current
6189 insn. */
6190 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
6192 /* Number elements in the previous array. */
6193 static int to_inherit_num;
6195 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6196 structure to_inherit. */
6197 static void
6198 add_to_inherit (int regno, rtx insns)
6200 int i;
6202 for (i = 0; i < to_inherit_num; i++)
6203 if (to_inherit[i].regno == regno)
6204 return;
6205 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
6206 to_inherit[to_inherit_num].regno = regno;
6207 to_inherit[to_inherit_num++].insns = insns;
6210 /* Return the last non-debug insn in basic block BB, or the block begin
6211 note if none. */
6212 static rtx_insn *
6213 get_last_insertion_point (basic_block bb)
6215 rtx_insn *insn;
6217 FOR_BB_INSNS_REVERSE (bb, insn)
6218 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
6219 return insn;
6220 gcc_unreachable ();
6223 /* Set up RES by registers living on edges FROM except the edge (FROM,
6224 TO) or by registers set up in a jump insn in BB FROM. */
6225 static void
6226 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
6228 rtx_insn *last;
6229 struct lra_insn_reg *reg;
6230 edge e;
6231 edge_iterator ei;
6233 lra_assert (to != NULL);
6234 bitmap_clear (res);
6235 FOR_EACH_EDGE (e, ei, from->succs)
6236 if (e->dest != to)
6237 bitmap_ior_into (res, df_get_live_in (e->dest));
6238 last = get_last_insertion_point (from);
6239 if (! JUMP_P (last))
6240 return;
6241 curr_id = lra_get_insn_recog_data (last);
6242 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6243 if (reg->type != OP_IN)
6244 bitmap_set_bit (res, reg->regno);
6247 /* Used as a temporary results of some bitmap calculations. */
6248 static bitmap_head temp_bitmap;
6250 /* We split for reloads of small class of hard regs. The following
6251 defines how many hard regs the class should have to be qualified as
6252 small. The code is mostly oriented to x86/x86-64 architecture
6253 where some insns need to use only specific register or pair of
6254 registers and these register can live in RTL explicitly, e.g. for
6255 parameter passing. */
6256 static const int max_small_class_regs_num = 2;
6258 /* Do inheritance/split transformations in EBB starting with HEAD and
6259 finishing on TAIL. We process EBB insns in the reverse order.
6260 Return true if we did any inheritance/split transformation in the
6261 EBB.
6263 We should avoid excessive splitting which results in worse code
6264 because of inaccurate cost calculations for spilling new split
6265 pseudos in such case. To achieve this we do splitting only if
6266 register pressure is high in given basic block and there are reload
6267 pseudos requiring hard registers. We could do more register
6268 pressure calculations at any given program point to avoid necessary
6269 splitting even more but it is to expensive and the current approach
6270 works well enough. */
6271 static bool
6272 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6274 int i, src_regno, dst_regno, nregs;
6275 bool change_p, succ_p, update_reloads_num_p;
6276 rtx_insn *prev_insn, *last_insn;
6277 rtx next_usage_insns, curr_set;
6278 enum reg_class cl;
6279 struct lra_insn_reg *reg;
6280 basic_block last_processed_bb, curr_bb = NULL;
6281 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6282 bitmap to_process;
6283 unsigned int j;
6284 bitmap_iterator bi;
6285 bool head_p, after_p;
6287 change_p = false;
6288 curr_usage_insns_check++;
6289 clear_invariants ();
6290 reloads_num = calls_num = 0;
6291 for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
6292 last_call_for_abi[i] = 0;
6293 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers);
6294 bitmap_clear (&check_only_regs);
6295 bitmap_clear (&invalid_invariant_regs);
6296 last_processed_bb = NULL;
6297 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6298 live_hard_regs = eliminable_regset | lra_no_alloc_regs;
6299 /* We don't process new insns generated in the loop. */
6300 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6302 prev_insn = PREV_INSN (curr_insn);
6303 if (BLOCK_FOR_INSN (curr_insn) != NULL)
6304 curr_bb = BLOCK_FOR_INSN (curr_insn);
6305 if (last_processed_bb != curr_bb)
6307 /* We are at the end of BB. Add qualified living
6308 pseudos for potential splitting. */
6309 to_process = df_get_live_out (curr_bb);
6310 if (last_processed_bb != NULL)
6312 /* We are somewhere in the middle of EBB. */
6313 get_live_on_other_edges (curr_bb, last_processed_bb,
6314 &temp_bitmap);
6315 to_process = &temp_bitmap;
6317 last_processed_bb = curr_bb;
6318 last_insn = get_last_insertion_point (curr_bb);
6319 after_p = (! JUMP_P (last_insn)
6320 && (! CALL_P (last_insn)
6321 || (find_reg_note (last_insn,
6322 REG_NORETURN, NULL_RTX) == NULL_RTX
6323 && ! SIBLING_CALL_P (last_insn))));
6324 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6325 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6327 if ((int) j >= lra_constraint_new_regno_start)
6328 break;
6329 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6331 if (j < FIRST_PSEUDO_REGISTER)
6332 SET_HARD_REG_BIT (live_hard_regs, j);
6333 else
6334 add_to_hard_reg_set (&live_hard_regs,
6335 PSEUDO_REGNO_MODE (j),
6336 reg_renumber[j]);
6337 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6341 src_regno = dst_regno = -1;
6342 curr_set = single_set (curr_insn);
6343 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6344 dst_regno = REGNO (SET_DEST (curr_set));
6345 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6346 src_regno = REGNO (SET_SRC (curr_set));
6347 update_reloads_num_p = true;
6348 if (src_regno < lra_constraint_new_regno_start
6349 && src_regno >= FIRST_PSEUDO_REGISTER
6350 && reg_renumber[src_regno] < 0
6351 && dst_regno >= lra_constraint_new_regno_start
6352 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6354 /* 'reload_pseudo <- original_pseudo'. */
6355 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6356 reloads_num++;
6357 update_reloads_num_p = false;
6358 succ_p = false;
6359 if (usage_insns[src_regno].check == curr_usage_insns_check
6360 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6361 succ_p = inherit_reload_reg (false, src_regno, cl,
6362 curr_insn, next_usage_insns);
6363 if (succ_p)
6364 change_p = true;
6365 else
6366 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6367 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6368 potential_reload_hard_regs |= reg_class_contents[cl];
6370 else if (src_regno < 0
6371 && dst_regno >= lra_constraint_new_regno_start
6372 && invariant_p (SET_SRC (curr_set))
6373 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6374 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6375 && ! bitmap_bit_p (&invalid_invariant_regs,
6376 ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6378 /* 'reload_pseudo <- invariant'. */
6379 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6380 reloads_num++;
6381 update_reloads_num_p = false;
6382 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6383 change_p = true;
6384 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6385 potential_reload_hard_regs |= reg_class_contents[cl];
6387 else if (src_regno >= lra_constraint_new_regno_start
6388 && dst_regno < lra_constraint_new_regno_start
6389 && dst_regno >= FIRST_PSEUDO_REGISTER
6390 && reg_renumber[dst_regno] < 0
6391 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6392 && usage_insns[dst_regno].check == curr_usage_insns_check
6393 && (next_usage_insns
6394 = usage_insns[dst_regno].insns) != NULL_RTX)
6396 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6397 reloads_num++;
6398 update_reloads_num_p = false;
6399 /* 'original_pseudo <- reload_pseudo'. */
6400 if (! JUMP_P (curr_insn)
6401 && inherit_reload_reg (true, dst_regno, cl,
6402 curr_insn, next_usage_insns))
6403 change_p = true;
6404 /* Invalidate. */
6405 usage_insns[dst_regno].check = 0;
6406 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6407 potential_reload_hard_regs |= reg_class_contents[cl];
6409 else if (INSN_P (curr_insn))
6411 int iter;
6412 int max_uid = get_max_uid ();
6414 curr_id = lra_get_insn_recog_data (curr_insn);
6415 curr_static_id = curr_id->insn_static_data;
6416 to_inherit_num = 0;
6417 /* Process insn definitions. */
6418 for (iter = 0; iter < 2; iter++)
6419 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6420 reg != NULL;
6421 reg = reg->next)
6422 if (reg->type != OP_IN
6423 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6425 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6426 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6427 && usage_insns[dst_regno].check == curr_usage_insns_check
6428 && (next_usage_insns
6429 = usage_insns[dst_regno].insns) != NULL_RTX)
6431 struct lra_insn_reg *r;
6433 for (r = curr_id->regs; r != NULL; r = r->next)
6434 if (r->type != OP_OUT && r->regno == dst_regno)
6435 break;
6436 /* Don't do inheritance if the pseudo is also
6437 used in the insn. */
6438 if (r == NULL)
6439 /* We cannot do inheritance right now
6440 because the current insn reg info (chain
6441 regs) can change after that. */
6442 add_to_inherit (dst_regno, next_usage_insns);
6444 /* We cannot process one reg twice here because of
6445 usage_insns invalidation. */
6446 if ((dst_regno < FIRST_PSEUDO_REGISTER
6447 || reg_renumber[dst_regno] >= 0)
6448 && ! reg->subreg_p && reg->type != OP_IN)
6450 HARD_REG_SET s;
6452 if (split_if_necessary (dst_regno, reg->biggest_mode,
6453 potential_reload_hard_regs,
6454 false, curr_insn, max_uid))
6455 change_p = true;
6456 CLEAR_HARD_REG_SET (s);
6457 if (dst_regno < FIRST_PSEUDO_REGISTER)
6458 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6459 else
6460 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6461 reg_renumber[dst_regno]);
6462 live_hard_regs &= ~s;
6463 potential_reload_hard_regs &= ~s;
6465 /* We should invalidate potential inheritance or
6466 splitting for the current insn usages to the next
6467 usage insns (see code below) as the output pseudo
6468 prevents this. */
6469 if ((dst_regno >= FIRST_PSEUDO_REGISTER
6470 && reg_renumber[dst_regno] < 0)
6471 || (reg->type == OP_OUT && ! reg->subreg_p
6472 && (dst_regno < FIRST_PSEUDO_REGISTER
6473 || reg_renumber[dst_regno] >= 0)))
6475 /* Invalidate and mark definitions. */
6476 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6477 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6478 else
6480 nregs = hard_regno_nregs (dst_regno,
6481 reg->biggest_mode);
6482 for (i = 0; i < nregs; i++)
6483 usage_insns[dst_regno + i].check
6484 = -(int) INSN_UID (curr_insn);
6488 /* Process clobbered call regs. */
6489 if (curr_id->arg_hard_regs != NULL)
6490 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6491 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6492 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6493 = -(int) INSN_UID (curr_insn);
6494 if (! JUMP_P (curr_insn))
6495 for (i = 0; i < to_inherit_num; i++)
6496 if (inherit_reload_reg (true, to_inherit[i].regno,
6497 ALL_REGS, curr_insn,
6498 to_inherit[i].insns))
6499 change_p = true;
6500 if (CALL_P (curr_insn))
6502 rtx cheap, pat, dest;
6503 rtx_insn *restore;
6504 int regno, hard_regno;
6506 calls_num++;
6507 function_abi callee_abi = insn_callee_abi (curr_insn);
6508 last_call_for_abi[callee_abi.id ()] = calls_num;
6509 full_and_partial_call_clobbers
6510 |= callee_abi.full_and_partial_reg_clobbers ();
6511 if ((cheap = find_reg_note (curr_insn,
6512 REG_RETURNED, NULL_RTX)) != NULL_RTX
6513 && ((cheap = XEXP (cheap, 0)), true)
6514 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6515 && (hard_regno = reg_renumber[regno]) >= 0
6516 && usage_insns[regno].check == curr_usage_insns_check
6517 /* If there are pending saves/restores, the
6518 optimization is not worth. */
6519 && usage_insns[regno].calls_num == calls_num - 1
6520 && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno))
6522 /* Restore the pseudo from the call result as
6523 REG_RETURNED note says that the pseudo value is
6524 in the call result and the pseudo is an argument
6525 of the call. */
6526 pat = PATTERN (curr_insn);
6527 if (GET_CODE (pat) == PARALLEL)
6528 pat = XVECEXP (pat, 0, 0);
6529 dest = SET_DEST (pat);
6530 /* For multiple return values dest is PARALLEL.
6531 Currently we handle only single return value case. */
6532 if (REG_P (dest))
6534 start_sequence ();
6535 emit_move_insn (cheap, copy_rtx (dest));
6536 restore = get_insns ();
6537 end_sequence ();
6538 lra_process_new_insns (curr_insn, NULL, restore,
6539 "Inserting call parameter restore");
6540 /* We don't need to save/restore of the pseudo from
6541 this call. */
6542 usage_insns[regno].calls_num = calls_num;
6543 remove_from_hard_reg_set
6544 (&full_and_partial_call_clobbers,
6545 GET_MODE (cheap), hard_regno);
6546 bitmap_set_bit (&check_only_regs, regno);
6550 to_inherit_num = 0;
6551 /* Process insn usages. */
6552 for (iter = 0; iter < 2; iter++)
6553 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6554 reg != NULL;
6555 reg = reg->next)
6556 if ((reg->type != OP_OUT
6557 || (reg->type == OP_OUT && reg->subreg_p))
6558 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6560 if (src_regno >= FIRST_PSEUDO_REGISTER
6561 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6563 if (usage_insns[src_regno].check == curr_usage_insns_check
6564 && (next_usage_insns
6565 = usage_insns[src_regno].insns) != NULL_RTX
6566 && NONDEBUG_INSN_P (curr_insn))
6567 add_to_inherit (src_regno, next_usage_insns);
6568 else if (usage_insns[src_regno].check
6569 != -(int) INSN_UID (curr_insn))
6570 /* Add usages but only if the reg is not set up
6571 in the same insn. */
6572 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6574 else if (src_regno < FIRST_PSEUDO_REGISTER
6575 || reg_renumber[src_regno] >= 0)
6577 bool before_p;
6578 rtx_insn *use_insn = curr_insn;
6580 before_p = (JUMP_P (curr_insn)
6581 || (CALL_P (curr_insn) && reg->type == OP_IN));
6582 if (NONDEBUG_INSN_P (curr_insn)
6583 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
6584 && split_if_necessary (src_regno, reg->biggest_mode,
6585 potential_reload_hard_regs,
6586 before_p, curr_insn, max_uid))
6588 if (reg->subreg_p)
6589 check_and_force_assignment_correctness_p = true;
6590 change_p = true;
6591 /* Invalidate. */
6592 usage_insns[src_regno].check = 0;
6593 if (before_p)
6594 use_insn = PREV_INSN (curr_insn);
6596 if (NONDEBUG_INSN_P (curr_insn))
6598 if (src_regno < FIRST_PSEUDO_REGISTER)
6599 add_to_hard_reg_set (&live_hard_regs,
6600 reg->biggest_mode, src_regno);
6601 else
6602 add_to_hard_reg_set (&live_hard_regs,
6603 PSEUDO_REGNO_MODE (src_regno),
6604 reg_renumber[src_regno]);
6606 if (src_regno >= FIRST_PSEUDO_REGISTER)
6607 add_next_usage_insn (src_regno, use_insn, reloads_num);
6608 else
6610 for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++)
6611 add_next_usage_insn (src_regno + i, use_insn, reloads_num);
6615 /* Process used call regs. */
6616 if (curr_id->arg_hard_regs != NULL)
6617 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6618 if (src_regno < FIRST_PSEUDO_REGISTER)
6620 SET_HARD_REG_BIT (live_hard_regs, src_regno);
6621 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6623 for (i = 0; i < to_inherit_num; i++)
6625 src_regno = to_inherit[i].regno;
6626 if (inherit_reload_reg (false, src_regno, ALL_REGS,
6627 curr_insn, to_inherit[i].insns))
6628 change_p = true;
6629 else
6630 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6633 if (update_reloads_num_p
6634 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
6636 int regno = -1;
6637 if ((REG_P (SET_DEST (curr_set))
6638 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
6639 && reg_renumber[regno] < 0
6640 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
6641 || (REG_P (SET_SRC (curr_set))
6642 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
6643 && reg_renumber[regno] < 0
6644 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
6646 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6647 reloads_num++;
6648 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6649 potential_reload_hard_regs |= reg_class_contents[cl];
6652 if (NONDEBUG_INSN_P (curr_insn))
6654 int regno;
6656 /* Invalidate invariants with changed regs. */
6657 curr_id = lra_get_insn_recog_data (curr_insn);
6658 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6659 if (reg->type != OP_IN)
6661 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6662 bitmap_set_bit (&invalid_invariant_regs,
6663 ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
6665 curr_static_id = curr_id->insn_static_data;
6666 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6667 if (reg->type != OP_IN)
6668 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6669 if (curr_id->arg_hard_regs != NULL)
6670 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6671 if (regno >= FIRST_PSEUDO_REGISTER)
6672 bitmap_set_bit (&invalid_invariant_regs,
6673 regno - FIRST_PSEUDO_REGISTER);
6675 /* We reached the start of the current basic block. */
6676 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
6677 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
6679 /* We reached the beginning of the current block -- do
6680 rest of spliting in the current BB. */
6681 to_process = df_get_live_in (curr_bb);
6682 if (BLOCK_FOR_INSN (head) != curr_bb)
6684 /* We are somewhere in the middle of EBB. */
6685 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
6686 curr_bb, &temp_bitmap);
6687 to_process = &temp_bitmap;
6689 head_p = true;
6690 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6692 if ((int) j >= lra_constraint_new_regno_start)
6693 break;
6694 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6695 && usage_insns[j].check == curr_usage_insns_check
6696 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
6698 if (need_for_split_p (potential_reload_hard_regs, j))
6700 if (lra_dump_file != NULL && head_p)
6702 fprintf (lra_dump_file,
6703 " ----------------------------------\n");
6704 head_p = false;
6706 if (split_reg (false, j, bb_note (curr_bb),
6707 next_usage_insns, NULL))
6708 change_p = true;
6710 usage_insns[j].check = 0;
6715 return change_p;
6718 /* This value affects EBB forming. If probability of edge from EBB to
6719 a BB is not greater than the following value, we don't add the BB
6720 to EBB. */
6721 #define EBB_PROBABILITY_CUTOFF \
6722 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
6724 /* Current number of inheritance/split iteration. */
6725 int lra_inheritance_iter;
6727 /* Entry function for inheritance/split pass. */
6728 void
6729 lra_inheritance (void)
6731 int i;
6732 basic_block bb, start_bb;
6733 edge e;
6735 lra_inheritance_iter++;
6736 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6737 return;
6738 timevar_push (TV_LRA_INHERITANCE);
6739 if (lra_dump_file != NULL)
6740 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
6741 lra_inheritance_iter);
6742 curr_usage_insns_check = 0;
6743 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
6744 for (i = 0; i < lra_constraint_new_regno_start; i++)
6745 usage_insns[i].check = 0;
6746 bitmap_initialize (&check_only_regs, &reg_obstack);
6747 bitmap_initialize (&invalid_invariant_regs, &reg_obstack);
6748 bitmap_initialize (&live_regs, &reg_obstack);
6749 bitmap_initialize (&temp_bitmap, &reg_obstack);
6750 bitmap_initialize (&ebb_global_regs, &reg_obstack);
6751 FOR_EACH_BB_FN (bb, cfun)
6753 start_bb = bb;
6754 if (lra_dump_file != NULL)
6755 fprintf (lra_dump_file, "EBB");
6756 /* Form a EBB starting with BB. */
6757 bitmap_clear (&ebb_global_regs);
6758 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
6759 for (;;)
6761 if (lra_dump_file != NULL)
6762 fprintf (lra_dump_file, " %d", bb->index);
6763 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
6764 || LABEL_P (BB_HEAD (bb->next_bb)))
6765 break;
6766 e = find_fallthru_edge (bb->succs);
6767 if (! e)
6768 break;
6769 if (e->probability.initialized_p ()
6770 && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
6771 break;
6772 bb = bb->next_bb;
6774 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
6775 if (lra_dump_file != NULL)
6776 fprintf (lra_dump_file, "\n");
6777 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
6778 /* Remember that the EBB head and tail can change in
6779 inherit_in_ebb. */
6780 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
6782 bitmap_release (&ebb_global_regs);
6783 bitmap_release (&temp_bitmap);
6784 bitmap_release (&live_regs);
6785 bitmap_release (&invalid_invariant_regs);
6786 bitmap_release (&check_only_regs);
6787 free (usage_insns);
6789 timevar_pop (TV_LRA_INHERITANCE);
6794 /* This page contains code to undo failed inheritance/split
6795 transformations. */
6797 /* Current number of iteration undoing inheritance/split. */
6798 int lra_undo_inheritance_iter;
6800 /* Fix BB live info LIVE after removing pseudos created on pass doing
6801 inheritance/split which are REMOVED_PSEUDOS. */
6802 static void
6803 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
6805 unsigned int regno;
6806 bitmap_iterator bi;
6808 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
6809 if (bitmap_clear_bit (live, regno)
6810 && REG_P (lra_reg_info[regno].restore_rtx))
6811 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
6814 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6815 number. */
6816 static int
6817 get_regno (rtx reg)
6819 if (GET_CODE (reg) == SUBREG)
6820 reg = SUBREG_REG (reg);
6821 if (REG_P (reg))
6822 return REGNO (reg);
6823 return -1;
6826 /* Delete a move INSN with destination reg DREGNO and a previous
6827 clobber insn with the same regno. The inheritance/split code can
6828 generate moves with preceding clobber and when we delete such moves
6829 we should delete the clobber insn too to keep the correct life
6830 info. */
6831 static void
6832 delete_move_and_clobber (rtx_insn *insn, int dregno)
6834 rtx_insn *prev_insn = PREV_INSN (insn);
6836 lra_set_insn_deleted (insn);
6837 lra_assert (dregno >= 0);
6838 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
6839 && GET_CODE (PATTERN (prev_insn)) == CLOBBER
6840 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
6841 lra_set_insn_deleted (prev_insn);
6844 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6845 return true if we did any change. The undo transformations for
6846 inheritance looks like
6847 i <- i2
6848 p <- i => p <- i2
6849 or removing
6850 p <- i, i <- p, and i <- i3
6851 where p is original pseudo from which inheritance pseudo i was
6852 created, i and i3 are removed inheritance pseudos, i2 is another
6853 not removed inheritance pseudo. All split pseudos or other
6854 occurrences of removed inheritance pseudos are changed on the
6855 corresponding original pseudos.
6857 The function also schedules insns changed and created during
6858 inheritance/split pass for processing by the subsequent constraint
6859 pass. */
6860 static bool
6861 remove_inheritance_pseudos (bitmap remove_pseudos)
6863 basic_block bb;
6864 int regno, sregno, prev_sregno, dregno;
6865 rtx restore_rtx;
6866 rtx set, prev_set;
6867 rtx_insn *prev_insn;
6868 bool change_p, done_p;
6870 change_p = ! bitmap_empty_p (remove_pseudos);
6871 /* We cannot finish the function right away if CHANGE_P is true
6872 because we need to marks insns affected by previous
6873 inheritance/split pass for processing by the subsequent
6874 constraint pass. */
6875 FOR_EACH_BB_FN (bb, cfun)
6877 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
6878 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
6879 FOR_BB_INSNS_REVERSE (bb, curr_insn)
6881 if (! INSN_P (curr_insn))
6882 continue;
6883 done_p = false;
6884 sregno = dregno = -1;
6885 if (change_p && NONDEBUG_INSN_P (curr_insn)
6886 && (set = single_set (curr_insn)) != NULL_RTX)
6888 dregno = get_regno (SET_DEST (set));
6889 sregno = get_regno (SET_SRC (set));
6892 if (sregno >= 0 && dregno >= 0)
6894 if (bitmap_bit_p (remove_pseudos, dregno)
6895 && ! REG_P (lra_reg_info[dregno].restore_rtx))
6897 /* invariant inheritance pseudo <- original pseudo */
6898 if (lra_dump_file != NULL)
6900 fprintf (lra_dump_file, " Removing invariant inheritance:\n");
6901 dump_insn_slim (lra_dump_file, curr_insn);
6902 fprintf (lra_dump_file, "\n");
6904 delete_move_and_clobber (curr_insn, dregno);
6905 done_p = true;
6907 else if (bitmap_bit_p (remove_pseudos, sregno)
6908 && ! REG_P (lra_reg_info[sregno].restore_rtx))
6910 /* reload pseudo <- invariant inheritance pseudo */
6911 start_sequence ();
6912 /* We cannot just change the source. It might be
6913 an insn different from the move. */
6914 emit_insn (lra_reg_info[sregno].restore_rtx);
6915 rtx_insn *new_insns = get_insns ();
6916 end_sequence ();
6917 lra_assert (single_set (new_insns) != NULL
6918 && SET_DEST (set) == SET_DEST (single_set (new_insns)));
6919 lra_process_new_insns (curr_insn, NULL, new_insns,
6920 "Changing reload<-invariant inheritance");
6921 delete_move_and_clobber (curr_insn, dregno);
6922 done_p = true;
6924 else if ((bitmap_bit_p (remove_pseudos, sregno)
6925 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
6926 || (bitmap_bit_p (remove_pseudos, dregno)
6927 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6928 && (get_regno (lra_reg_info[sregno].restore_rtx)
6929 == get_regno (lra_reg_info[dregno].restore_rtx)))))
6930 || (bitmap_bit_p (remove_pseudos, dregno)
6931 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
6932 /* One of the following cases:
6933 original <- removed inheritance pseudo
6934 removed inherit pseudo <- another removed inherit pseudo
6935 removed inherit pseudo <- original pseudo
6937 removed_split_pseudo <- original_reg
6938 original_reg <- removed_split_pseudo */
6940 if (lra_dump_file != NULL)
6942 fprintf (lra_dump_file, " Removing %s:\n",
6943 bitmap_bit_p (&lra_split_regs, sregno)
6944 || bitmap_bit_p (&lra_split_regs, dregno)
6945 ? "split" : "inheritance");
6946 dump_insn_slim (lra_dump_file, curr_insn);
6948 delete_move_and_clobber (curr_insn, dregno);
6949 done_p = true;
6951 else if (bitmap_bit_p (remove_pseudos, sregno)
6952 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6954 /* Search the following pattern:
6955 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6956 original_pseudo <- inherit_or_split_pseudo1
6957 where the 2nd insn is the current insn and
6958 inherit_or_split_pseudo2 is not removed. If it is found,
6959 change the current insn onto:
6960 original_pseudo <- inherit_or_split_pseudo2. */
6961 for (prev_insn = PREV_INSN (curr_insn);
6962 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6963 prev_insn = PREV_INSN (prev_insn))
6965 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6966 && (prev_set = single_set (prev_insn)) != NULL_RTX
6967 /* There should be no subregs in insn we are
6968 searching because only the original reg might
6969 be in subreg when we changed the mode of
6970 load/store for splitting. */
6971 && REG_P (SET_DEST (prev_set))
6972 && REG_P (SET_SRC (prev_set))
6973 && (int) REGNO (SET_DEST (prev_set)) == sregno
6974 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6975 >= FIRST_PSEUDO_REGISTER)
6976 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
6978 /* As we consider chain of inheritance or
6979 splitting described in above comment we should
6980 check that sregno and prev_sregno were
6981 inheritance/split pseudos created from the
6982 same original regno. */
6983 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6984 && (get_regno (lra_reg_info[sregno].restore_rtx)
6985 == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
6986 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6988 lra_assert (GET_MODE (SET_SRC (prev_set))
6989 == GET_MODE (regno_reg_rtx[sregno]));
6990 /* Although we have a single set, the insn can
6991 contain more one sregno register occurrence
6992 as a source. Change all occurrences. */
6993 lra_substitute_pseudo_within_insn (curr_insn, sregno,
6994 SET_SRC (prev_set),
6995 false);
6996 /* As we are finishing with processing the insn
6997 here, check the destination too as it might
6998 inheritance pseudo for another pseudo. */
6999 if (bitmap_bit_p (remove_pseudos, dregno)
7000 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
7001 && (restore_rtx
7002 = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
7004 if (GET_CODE (SET_DEST (set)) == SUBREG)
7005 SUBREG_REG (SET_DEST (set)) = restore_rtx;
7006 else
7007 SET_DEST (set) = restore_rtx;
7009 lra_push_insn_and_update_insn_regno_info (curr_insn);
7010 lra_set_used_insn_alternative_by_uid
7011 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
7012 done_p = true;
7013 if (lra_dump_file != NULL)
7015 fprintf (lra_dump_file, " Change reload insn:\n");
7016 dump_insn_slim (lra_dump_file, curr_insn);
7021 if (! done_p)
7023 struct lra_insn_reg *reg;
7024 bool restored_regs_p = false;
7025 bool kept_regs_p = false;
7027 curr_id = lra_get_insn_recog_data (curr_insn);
7028 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
7030 regno = reg->regno;
7031 restore_rtx = lra_reg_info[regno].restore_rtx;
7032 if (restore_rtx != NULL_RTX)
7034 if (change_p && bitmap_bit_p (remove_pseudos, regno))
7036 lra_substitute_pseudo_within_insn
7037 (curr_insn, regno, restore_rtx, false);
7038 restored_regs_p = true;
7040 else
7041 kept_regs_p = true;
7044 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
7046 /* The instruction has changed since the previous
7047 constraints pass. */
7048 lra_push_insn_and_update_insn_regno_info (curr_insn);
7049 lra_set_used_insn_alternative_by_uid
7050 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
7052 else if (restored_regs_p)
7053 /* The instruction has been restored to the form that
7054 it had during the previous constraints pass. */
7055 lra_update_insn_regno_info (curr_insn);
7056 if (restored_regs_p && lra_dump_file != NULL)
7058 fprintf (lra_dump_file, " Insn after restoring regs:\n");
7059 dump_insn_slim (lra_dump_file, curr_insn);
7064 return change_p;
7067 /* If optional reload pseudos failed to get a hard register or was not
7068 inherited, it is better to remove optional reloads. We do this
7069 transformation after undoing inheritance to figure out necessity to
7070 remove optional reloads easier. Return true if we do any
7071 change. */
7072 static bool
7073 undo_optional_reloads (void)
7075 bool change_p, keep_p;
7076 unsigned int regno, uid;
7077 bitmap_iterator bi, bi2;
7078 rtx_insn *insn;
7079 rtx set, src, dest;
7080 auto_bitmap removed_optional_reload_pseudos (&reg_obstack);
7082 bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
7083 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7085 keep_p = false;
7086 /* Keep optional reloads from previous subpasses. */
7087 if (lra_reg_info[regno].restore_rtx == NULL_RTX
7088 /* If the original pseudo changed its allocation, just
7089 removing the optional pseudo is dangerous as the original
7090 pseudo will have longer live range. */
7091 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
7092 keep_p = true;
7093 else if (reg_renumber[regno] >= 0)
7094 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
7096 insn = lra_insn_recog_data[uid]->insn;
7097 if ((set = single_set (insn)) == NULL_RTX)
7098 continue;
7099 src = SET_SRC (set);
7100 dest = SET_DEST (set);
7101 if (! REG_P (src) || ! REG_P (dest))
7102 continue;
7103 if (REGNO (dest) == regno
7104 /* Ignore insn for optional reloads itself. */
7105 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src)
7106 /* Check only inheritance on last inheritance pass. */
7107 && (int) REGNO (src) >= new_regno_start
7108 /* Check that the optional reload was inherited. */
7109 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
7111 keep_p = true;
7112 break;
7115 if (keep_p)
7117 bitmap_clear_bit (removed_optional_reload_pseudos, regno);
7118 if (lra_dump_file != NULL)
7119 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
7122 change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
7123 auto_bitmap insn_bitmap (&reg_obstack);
7124 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
7126 if (lra_dump_file != NULL)
7127 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
7128 bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
7129 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
7131 insn = lra_insn_recog_data[uid]->insn;
7132 if ((set = single_set (insn)) != NULL_RTX)
7134 src = SET_SRC (set);
7135 dest = SET_DEST (set);
7136 if (REG_P (src) && REG_P (dest)
7137 && ((REGNO (src) == regno
7138 && (REGNO (lra_reg_info[regno].restore_rtx)
7139 == REGNO (dest)))
7140 || (REGNO (dest) == regno
7141 && (REGNO (lra_reg_info[regno].restore_rtx)
7142 == REGNO (src)))))
7144 if (lra_dump_file != NULL)
7146 fprintf (lra_dump_file, " Deleting move %u\n",
7147 INSN_UID (insn));
7148 dump_insn_slim (lra_dump_file, insn);
7150 delete_move_and_clobber (insn, REGNO (dest));
7151 continue;
7153 /* We should not worry about generation memory-memory
7154 moves here as if the corresponding inheritance did
7155 not work (inheritance pseudo did not get a hard reg),
7156 we remove the inheritance pseudo and the optional
7157 reload. */
7159 lra_substitute_pseudo_within_insn
7160 (insn, regno, lra_reg_info[regno].restore_rtx, false);
7161 lra_update_insn_regno_info (insn);
7162 if (lra_dump_file != NULL)
7164 fprintf (lra_dump_file,
7165 " Restoring original insn:\n");
7166 dump_insn_slim (lra_dump_file, insn);
7170 /* Clear restore_regnos. */
7171 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7172 lra_reg_info[regno].restore_rtx = NULL_RTX;
7173 return change_p;
7176 /* Entry function for undoing inheritance/split transformation. Return true
7177 if we did any RTL change in this pass. */
7178 bool
7179 lra_undo_inheritance (void)
7181 unsigned int regno;
7182 int hard_regno;
7183 int n_all_inherit, n_inherit, n_all_split, n_split;
7184 rtx restore_rtx;
7185 bitmap_iterator bi;
7186 bool change_p;
7188 lra_undo_inheritance_iter++;
7189 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7190 return false;
7191 if (lra_dump_file != NULL)
7192 fprintf (lra_dump_file,
7193 "\n********** Undoing inheritance #%d: **********\n\n",
7194 lra_undo_inheritance_iter);
7195 auto_bitmap remove_pseudos (&reg_obstack);
7196 n_inherit = n_all_inherit = 0;
7197 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7198 if (lra_reg_info[regno].restore_rtx != NULL_RTX)
7200 n_all_inherit++;
7201 if (reg_renumber[regno] < 0
7202 /* If the original pseudo changed its allocation, just
7203 removing inheritance is dangerous as for changing
7204 allocation we used shorter live-ranges. */
7205 && (! REG_P (lra_reg_info[regno].restore_rtx)
7206 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
7207 bitmap_set_bit (remove_pseudos, regno);
7208 else
7209 n_inherit++;
7211 if (lra_dump_file != NULL && n_all_inherit != 0)
7212 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
7213 n_inherit, n_all_inherit,
7214 (double) n_inherit / n_all_inherit * 100);
7215 n_split = n_all_split = 0;
7216 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7217 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
7219 int restore_regno = REGNO (restore_rtx);
7221 n_all_split++;
7222 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
7223 ? reg_renumber[restore_regno] : restore_regno);
7224 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
7225 bitmap_set_bit (remove_pseudos, regno);
7226 else
7228 n_split++;
7229 if (lra_dump_file != NULL)
7230 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
7231 regno, restore_regno);
7234 if (lra_dump_file != NULL && n_all_split != 0)
7235 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
7236 n_split, n_all_split,
7237 (double) n_split / n_all_split * 100);
7238 change_p = remove_inheritance_pseudos (remove_pseudos);
7239 /* Clear restore_regnos. */
7240 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7241 lra_reg_info[regno].restore_rtx = NULL_RTX;
7242 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7243 lra_reg_info[regno].restore_rtx = NULL_RTX;
7244 change_p = undo_optional_reloads () || change_p;
7245 return change_p;