1 ;; Machine Description for Renesas RL78 processors
2 ;; Copyright (C) 2011 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; In this MD file, we define those insn patterns that involve
22 ;; registers, where such registers are virtual until allocated to a
23 ;; physical register. All of these insns need to be conditional on
24 ;; rl78_virt_insns_ok () being true.
26 ;; This tells the physical register allocator what method to use to
27 ;; allocate registers. Basically, this defines the template of the
28 ;; instruction - op1 is of the form "a = op(b)", op2 is "a = b op c"
31 (define_attr "valloc" "op1,op2,ro1,cmp,umul,macax"
34 ;;---------- Moving ------------------------
36 (define_insn "*movqi_virt"
37 [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,Wfr")
38 (match_operand 1 "general_operand" "vInt8JY,Wfr,vInt8J"))]
39 "rl78_virt_insns_ok ()"
41 [(set_attr "valloc" "op1")]
44 (define_insn "*movhi_virt"
45 [(set (match_operand:HI 0 "nonimmediate_operand" "=vYS,v,Wfr")
46 (match_operand:HI 1 "general_operand" "viYS,Wfr,v"))]
47 "rl78_virt_insns_ok ()"
49 [(set_attr "valloc" "op1")]
52 ;;---------- Conversions ------------------------
54 (define_insn "*zero_extendqihi2_virt"
55 [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vm")
56 (zero_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
57 "rl78_virt_insns_ok ()"
58 "v.zero_extend\t%0, %1"
59 [(set_attr "valloc" "op1")]
62 (define_insn "*extendqihi2_virt"
63 [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vm")
64 (sign_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
65 "rl78_virt_insns_ok ()"
66 "v.sign_extend\t%0, %1"
67 [(set_attr "valloc" "op1")]
70 ;;---------- Arithmetic ------------------------
72 (define_insn "*add<mode>3_virt"
73 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vY,S")
74 (plus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "viY,0")
75 (match_operand:QHI 2 "general_operand" "vim,i")))
77 "rl78_virt_insns_ok ()"
81 (define_insn "*sub<mode>3_virt"
82 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm,S")
83 (minus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim,0")
84 (match_operand:QHI 2 "general_operand" "vim,i")))
86 "rl78_virt_insns_ok ()"
90 (define_insn "*umulhi3_shift_virt"
91 [(set (match_operand:HI 0 "register_operand" "=vm")
92 (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "%vim")
93 (match_operand:HI 2 "rl78_24_operand" "Ni")))]
94 "rl78_virt_insns_ok ()"
96 [(set_attr "valloc" "umul")]
99 (define_insn "*umulqihi3_virt"
100 [(set (match_operand:HI 0 "register_operand" "=vm")
101 (mult:HI (zero_extend:HI (match_operand:QI 1 "rl78_nonfar_operand" "%vim"))
102 (zero_extend:HI (match_operand:QI 2 "general_operand" "vim"))))]
103 "rl78_virt_insns_ok ()"
105 [(set_attr "valloc" "umul")]
108 (define_insn "*andqi3_virt"
109 [(set (match_operand:QI 0 "rl78_nonfar_nonimm_operand" "=vm")
110 (and:QI (match_operand:QI 1 "rl78_nonfar_operand" "vim")
111 (match_operand:QI 2 "general_operand" "vim")))
113 "rl78_virt_insns_ok ()"
117 (define_insn "*iorqi3_virt"
118 [(set (match_operand:QI 0 "rl78_nonfar_nonimm_operand" "=vm")
119 (ior:QI (match_operand:QI 1 "rl78_nonfar_operand" "vim")
120 (match_operand:QI 2 "general_operand" "vim")))
122 "rl78_virt_insns_ok ()"
126 (define_insn "*xor3_virt"
127 [(set (match_operand:QI 0 "rl78_nonfar_nonimm_operand" "=v,vm,m")
128 (xor:QI (match_operand:QI 1 "rl78_nonfar_operand" "%0,vm,vm")
129 (match_operand 2 "general_operand" "i,vm,vim")))
131 "rl78_virt_insns_ok ()"
135 ;;---------- Shifts ------------------------
137 (define_insn "*ashl<mode>3_virt"
138 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm")
139 (ashift:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
140 (match_operand:QI 2 "general_operand" "vim")))
142 "rl78_virt_insns_ok ()"
146 (define_insn "*ashr<mode>3_virt"
147 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm")
148 (ashiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
149 (match_operand:QI 2 "general_operand" "vim")))
151 "rl78_virt_insns_ok ()"
155 (define_insn "*lshr<mode>3_virt"
156 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm")
157 (lshiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
158 (match_operand:QI 2 "general_operand" "vim")))
160 "rl78_virt_insns_ok ()"
165 (define_insn "*ashrsi3_virt"
166 [(set (match_operand:SI 0 "register_operand" "=v,v,v")
167 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,v,0")
168 (match_operand:SI 2 "immediate_operand" "M,K,i")))
173 movw\tax,%H1\;sarw\tax,1\;movw\t%H0,ax\;mov\ta,%Q1\;rorc\ta,1\;mov\t%Q0,a\;mov\ta,%q1\;rorc\ta,1\;mov\t%q0,a
174 mov\tb,%2\;1:\;movw\tax,%H1\;sarw\tax,1\;movw\t%H0,ax\;mov\ta,%Q1\;rorc\ta,1\;mov\t%Q0,a\;mov\ta,%q1\;rorc\ta,1\;mov\t%q0,a\;dec\tb\;bnz $1b"
175 [(set_attr "valloc" "macax")]
178 ;;---------- Branching ------------------------
180 (define_insn "*indirect_jump_virt"
182 (match_operand:HI 0 "nonimmediate_operand" "vm"))]
183 "rl78_virt_insns_ok ()"
185 [(set_attr "valloc" "ro1")]
188 (define_insn "*call_virt"
189 [(call (match_operand:HI 0 "memory_operand" "Wab,Wcv")
190 (match_operand 1 "" ""))]
191 "rl78_virt_insns_ok ()"
193 [(set_attr "valloc" "ro1")]
196 (define_insn "*call_value_virt"
197 [(set (match_operand 0 "register_operand" "=v,v")
198 (call (match_operand:HI 1 "memory_operand" "Wab,Wcv")
199 (match_operand 2 "" "")))]
200 "rl78_virt_insns_ok ()"
202 [(set_attr "valloc" "op1")]
205 (define_insn "*cbranchqi4_virt"
206 [(set (pc) (if_then_else
207 (match_operator 0 "rl78_cmp_operator_real"
208 [(match_operand:QI 1 "general_operand" "vim")
209 (match_operand:QI 2 "general_operand" "vim")])
210 (label_ref (match_operand 3 "" ""))
212 "rl78_virt_insns_ok ()"
213 "v.cmp\t%1, %2\\n\tv.b%c0\t%3"
214 [(set_attr "valloc" "cmp")]
217 (define_insn "*cbranchhi4_virt"
218 [(set (pc) (if_then_else
219 (match_operator 0 "rl78_cmp_operator_real"
220 [(match_operand:HI 1 "general_operand" "vim")
221 (match_operand:HI 2 "general_operand" "vim")])
222 (label_ref (match_operand 3 "" ""))
224 "rl78_virt_insns_ok ()"
225 "v.cmpw\t%1, %2\\n\tv.b%c0\t%3"
226 [(set_attr "valloc" "cmp")]
229 ;;---------- Peepholes ------------------------
232 [(set (match_operand:QI 0 "" "")
233 (match_operand:QI 1 "" ""))
234 (set (match_operand:QI 2 "" "")
235 (match_operand:QI 3 "" ""))]
236 "rl78_peep_movhi_p (operands)"
239 "rl78_setup_peep_movhi (operands);"
244 (match_operand:QI 1 "" ""))
245 (set (match_operand:QI 0 "" "")
248 (match_operand:QI 3 "" ""))
249 (set (match_operand:QI 2 "" "")
252 "rl78_peep_movhi_p (operands)"
253 [(set (reg:HI AX_REG)
258 "rl78_setup_peep_movhi (operands);"