gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #ifdef __STDC__
  79 #include <stdarg.h>
  80 #else
  81 #include <varargs.h>
  82 #endif
  83
  84 /* Must precede rtl.h for FFS.  */
  85 #include <stdio.h>
  86
  87 #include "rtl.h"
  88 #include "flags.h"
  89 #include "regs.h"
  90 #include "hard-reg-set.h"
  91 #include "expr.h"
  92 #include "basic-block.h"
  93 #include "insn-config.h"
  94 #include "insn-flags.h"
  95 #include "insn-codes.h"
  96 #include "insn-attr.h"
  97 #include "recog.h"
  98 #include "real.h"
  99
 100 /* It is not safe to use ordinary gen_lowpart in combine.
 101    Use gen_lowpart_for_combine instead.  See comments there.  */
 102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
 103
 104 /* Number of attempts to combine instructions in this function.  */
 105
 106 static int combine_attempts;
 107
 108 /* Number of attempts that got as far as substitution in this function.  */
 109
 110 static int combine_merges;
 111
 112 /* Number of instructions combined with added SETs in this function.  */
 113
 114 static int combine_extras;
 115
 116 /* Number of instructions combined in this function.  */
 117
 118 static int combine_successes;
 119
 120 /* Totals over entire compilation.  */
 121
 122 static int total_attempts, total_merges, total_extras, total_successes;
 123
 124 /* Define a default value for REVERSIBLE_CC_MODE.
 125    We can never assume that a condition code mode is safe to reverse unless
 126    the md tells us so.  */
 127 #ifndef REVERSIBLE_CC_MODE
 128 #define REVERSIBLE_CC_MODE(MODE) 0
 129 #endif
 130 \f
 131 /* Vector mapping INSN_UIDs to cuids.
 132    The cuids are like uids but increase monotonically always.
 133    Combine always uses cuids so that it can compare them.
 134    But actually renumbering the uids, which we used to do,
 135    proves to be a bad idea because it makes it hard to compare
 136    the dumps produced by earlier passes with those from later passes.  */
 137
 138 static int *uid_cuid;
 139 static int max_uid_cuid;
 140
 141 /* Get the cuid of an insn.  */
 142
 143 #define INSN_CUID(INSN) \
 144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 145
 146 /* Maximum register number, which is the size of the tables below.  */
 147
 148 static int combine_max_regno;
 149
 150 /* Record last point of death of (hard or pseudo) register n.  */
 151
 152 static rtx *reg_last_death;
 153
 154 /* Record last point of modification of (hard or pseudo) register n.  */
 155
 156 static rtx *reg_last_set;
 157
 158 /* Record the cuid of the last insn that invalidated memory
 159    (anything that writes memory, and subroutine calls, but not pushes).  */
 160
 161 static int mem_last_set;
 162
 163 /* Record the cuid of the last CALL_INSN
 164    so we can tell whether a potential combination crosses any calls.  */
 165
 166 static int last_call_cuid;
 167
 168 /* When `subst' is called, this is the insn that is being modified
 169    (by combining in a previous insn).  The PATTERN of this insn
 170    is still the old pattern partially modified and it should not be
 171    looked at, but this may be used to examine the successors of the insn
 172    to judge whether a simplification is valid.  */
 173
 174 static rtx subst_insn;
 175
 176 /* This is an insn that belongs before subst_insn, but is not currently
 177    on the insn chain.  */
 178
 179 static rtx subst_prev_insn;
 180
 181 /* This is the lowest CUID that `subst' is currently dealing with.
 182    get_last_value will not return a value if the register was set at or
 183    after this CUID.  If not for this mechanism, we could get confused if
 184    I2 or I1 in try_combine were an insn that used the old value of a register
 185    to obtain a new value.  In that case, we might erroneously get the
 186    new value of the register when we wanted the old one.  */
 187
 188 static int subst_low_cuid;
 189
 190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 191    must consider all these registers to be always live.  */
 192
 193 static HARD_REG_SET newpat_used_regs;
 194
 195 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 196    insn is the earlier than I2 or I3, combine should rescan starting at
 197    that location.  */
 198
 199 static rtx added_links_insn;
 200
 201 /* Basic block number of the block in which we are performing combines.  */
 202 static int this_basic_block;
 203 \f
 204 /* The next group of arrays allows the recording of the last value assigned
 205    to (hard or pseudo) register n.  We use this information to see if a
 206    operation being processed is redundant given a prior operation performed
 207    on the register.  For example, an `and' with a constant is redundant if
 208    all the zero bits are already known to be turned off.
 209
 210    We use an approach similar to that used by cse, but change it in the
 211    following ways:
 212
 213    (1) We do not want to reinitialize at each label.
 214    (2) It is useful, but not critical, to know the actual value assigned
 215        to a register.  Often just its form is helpful.
 216
 217    Therefore, we maintain the following arrays:
 218
 219    reg_last_set_value           the last value assigned
 220    reg_last_set_label           records the value of label_tick when the
 221                                 register was assigned
 222    reg_last_set_table_tick      records the value of label_tick when a
 223                                 value using the register is assigned
 224    reg_last_set_invalid         set to non-zero when it is not valid
 225                                 to use the value of this register in some
 226                                 register's value
 227
 228    To understand the usage of these tables, it is important to understand
 229    the distinction between the value in reg_last_set_value being valid
 230    and the register being validly contained in some other expression in the
 231    table.
 232
 233    Entry I in reg_last_set_value is valid if it is non-zero, and either
 234    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 235
 236    Register I may validly appear in any expression returned for the value
 237    of another register if reg_n_sets[i] is 1.  It may also appear in the
 238    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 239    reg_last_set_invalid[j] is zero.
 240
 241    If an expression is found in the table containing a register which may
 242    not validly appear in an expression, the register is replaced by
 243    something that won't match, (clobber (const_int 0)).
 244
 245    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 246    to and reg_last_set_table_tick[i] == label_tick.  */
 247
 248 /* Record last value assigned to (hard or pseudo) register n.  */
 249
 250 static rtx *reg_last_set_value;
 251
 252 /* Record the value of label_tick when the value for register n is placed in
 253    reg_last_set_value[n].  */
 254
 255 static int *reg_last_set_label;
 256
 257 /* Record the value of label_tick when an expression involving register n
 258    is placed in reg_last_set_value.  */
 259
 260 static int *reg_last_set_table_tick;
 261
 262 /* Set non-zero if references to register n in expressions should not be
 263    used.  */
 264
 265 static char *reg_last_set_invalid;
 266
 267 /* Incremented for each label.  */
 268
 269 static int label_tick;
 270
 271 /* Some registers that are set more than once and used in more than one
 272    basic block are nevertheless always set in similar ways.  For example,
 273    a QImode register may be loaded from memory in two places on a machine
 274    where byte loads zero extend.
 275
 276    We record in the following array what we know about the nonzero
 277    bits of a register, specifically which bits are known to be zero.
 278
 279    If an entry is zero, it means that we don't know anything special.  */
 280
 281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 282
 283 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 284    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 285
 286 static enum machine_mode nonzero_bits_mode;
 287
 288 /* Nonzero if we know that a register has some leading bits that are always
 289    equal to the sign bit.  */
 290
 291 static char *reg_sign_bit_copies;
 292
 293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 294    It is zero while computing them and after combine has completed.  This
 295    former test prevents propagating values based on previously set values,
 296    which can be incorrect if a variable is modified in a loop.  */
 297
 298 static int nonzero_sign_valid;
 299
 300 /* These arrays are maintained in parallel with reg_last_set_value
 301    and are used to store the mode in which the register was last set,
 302    the bits that were known to be zero when it was last set, and the
 303    number of sign bits copies it was known to have when it was last set.  */
 304
 305 static enum machine_mode *reg_last_set_mode;
 306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 307 static char *reg_last_set_sign_bit_copies;
 308 \f
 309 /* Record one modification to rtl structure
 310    to be undone by storing old_contents into *where.
 311    is_int is 1 if the contents are an int.  */
 312
 313 struct undo
 314 {
 315   struct undo *next;
 316   int is_int;
 317   union {rtx r; int i;} old_contents;
 318   union {rtx *r; int *i;} where;
 319 };
 320
 321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 322    num_undo says how many are currently recorded.
 323
 324    storage is nonzero if we must undo the allocation of new storage.
 325    The value of storage is what to pass to obfree.
 326
 327    other_insn is nonzero if we have modified some other insn in the process
 328    of working on subst_insn.  It must be verified too.
 329
 330    previous_undos is the value of undobuf.undos when we started processing
 331    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 332    from the previous expression.  Doing so can produce circular rtl
 333    structures.  */
 334
 335 struct undobuf
 336 {
 337   char *storage;
 338   struct undo *undos;
 339   struct undo *frees;
 340   struct undo *previous_undos;
 341   rtx other_insn;
 342 };
 343
 344 static struct undobuf undobuf;
 345
 346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 347    insn.  The substitution can be undone by undo_all.  If INTO is already
 348    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 349    also call SUBST, we have to compute it before we put anything into
 350    the undo table.  */
 351
 352 #define SUBST(INTO, NEWVAL)  \
 353  do { rtx _new = (NEWVAL);                                      \
 354       struct undo *_buf;                                        \
 355                                                                 \
 356       if (undobuf.frees)                                        \
 357         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 358       else                                                      \
 359         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 360                                                                 \
 361       _buf->is_int = 0;                                         \
 362       _buf->where.r = &INTO;                                    \
 363       _buf->old_contents.r = INTO;                              \
 364       INTO = _new;                                              \
 365       if (_buf->old_contents.r == INTO)                         \
 366         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 367       else                                                      \
 368         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 369     } while (0)
 370
 371 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 372    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 373    not safe.  */
 374
 375 #define SUBST_INT(INTO, NEWVAL)  \
 376  do { struct undo *_buf;                                        \
 377                                                                 \
 378       if (undobuf.frees)                                        \
 379         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 380       else                                                      \
 381         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 382                                                                 \
 383       _buf->is_int = 1;                                         \
 384       _buf->where.i = (int *) &INTO;                            \
 385       _buf->old_contents.i = INTO;                              \
 386       INTO = NEWVAL;                                            \
 387       if (_buf->old_contents.i == INTO)                         \
 388         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 389       else                                                      \
 390         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 391      } while (0)
 392
 393 /* Number of times the pseudo being substituted for
 394    was found and replaced.  */
 395
 396 static int n_occurrences;
 397
 398 static void init_reg_last_arrays        PROTO((void));
 399 static void setup_incoming_promotions   PROTO((void));
 400 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
 401 static int can_combine_p        PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
 402 static int combinable_i3pat     PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
 403 static rtx try_combine          PROTO((rtx, rtx, rtx));
 404 static void undo_all            PROTO((void));
 405 static rtx *find_split_point    PROTO((rtx *, rtx));
 406 static rtx subst                PROTO((rtx, rtx, rtx, int, int));
 407 static rtx simplify_rtx         PROTO((rtx, enum machine_mode, int, int));
 408 static rtx simplify_if_then_else  PROTO((rtx));
 409 static rtx simplify_set         PROTO((rtx));
 410 static rtx simplify_logical     PROTO((rtx, int));
 411 static rtx expand_compound_operation  PROTO((rtx));
 412 static rtx expand_field_assignment  PROTO((rtx));
 413 static rtx make_extraction      PROTO((enum machine_mode, rtx, int, rtx, int,
 414                                        int, int, int));
 415 static rtx extract_left_shift   PROTO((rtx, int));
 416 static rtx make_compound_operation  PROTO((rtx, enum rtx_code));
 417 static int get_pos_from_mask    PROTO((unsigned HOST_WIDE_INT, int *));
 418 static rtx force_to_mode        PROTO((rtx, enum machine_mode,
 419                                        unsigned HOST_WIDE_INT, rtx, int));
 420 static rtx if_then_else_cond    PROTO((rtx, rtx *, rtx *));
 421 static rtx known_cond           PROTO((rtx, enum rtx_code, rtx, rtx));
 422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
 423 static rtx make_field_assignment  PROTO((rtx));
 424 static rtx apply_distributive_law  PROTO((rtx));
 425 static rtx simplify_and_const_int  PROTO((rtx, enum machine_mode, rtx,
 426                                           unsigned HOST_WIDE_INT));
 427 static unsigned HOST_WIDE_INT nonzero_bits  PROTO((rtx, enum machine_mode));
 428 static int num_sign_bit_copies  PROTO((rtx, enum machine_mode));
 429 static int merge_outer_ops      PROTO((enum rtx_code *, HOST_WIDE_INT *,
 430                                        enum rtx_code, HOST_WIDE_INT,
 431                                        enum machine_mode, int *));
 432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
 433                                        rtx, int));
 434 static int recog_for_combine    PROTO((rtx *, rtx, rtx *, int *));
 435 static rtx gen_lowpart_for_combine  PROTO((enum machine_mode, rtx));
 436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
 437                                   ...));
 438 static rtx gen_binary           PROTO((enum rtx_code, enum machine_mode,
 439                                        rtx, rtx));
 440 static rtx gen_unary            PROTO((enum rtx_code, enum machine_mode,
 441                                        enum machine_mode, rtx));
 442 static enum rtx_code simplify_comparison  PROTO((enum rtx_code, rtx *, rtx *));
 443 static int reversible_comparison_p  PROTO((rtx));
 444 static void update_table_tick   PROTO((rtx));
 445 static void record_value_for_reg  PROTO((rtx, rtx, rtx));
 446 static void record_dead_and_set_regs_1  PROTO((rtx, rtx));
 447 static void record_dead_and_set_regs  PROTO((rtx));
 448 static int get_last_value_validate  PROTO((rtx *, int, int));
 449 static rtx get_last_value       PROTO((rtx));
 450 static int use_crosses_set_p    PROTO((rtx, int));
 451 static void reg_dead_at_p_1     PROTO((rtx, rtx));
 452 static int reg_dead_at_p        PROTO((rtx, rtx));
 453 static void move_deaths         PROTO((rtx, rtx, int, rtx, rtx *));
 454 static int reg_bitfield_target_p  PROTO((rtx, rtx));
 455 static void distribute_notes    PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 456 static void distribute_links    PROTO((rtx));
 457 static void mark_used_regs_combine PROTO((rtx));
 458 static int insn_cuid            PROTO((rtx));
 459 \f
 460 /* Main entry point for combiner.  F is the first insn of the function.
 461    NREGS is the first unused pseudo-reg number.  */
 462
 463 void
 464 combine_instructions (f, nregs)
 465      rtx f;
 466      int nregs;
 467 {
 468   register rtx insn, next, prev;
 469   register int i;
 470   register rtx links, nextlinks;
 471
 472   combine_attempts = 0;
 473   combine_merges = 0;
 474   combine_extras = 0;
 475   combine_successes = 0;
 476   undobuf.undos = undobuf.previous_undos = 0;
 477
 478   combine_max_regno = nregs;
 479
 480   reg_nonzero_bits
 481     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 482   reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
 483
 484   bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 485   bzero (reg_sign_bit_copies, nregs * sizeof (char));
 486
 487   reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
 488   reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
 489   reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
 490   reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
 491   reg_last_set_label = (int *) alloca (nregs * sizeof (int));
 492   reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
 493   reg_last_set_mode
 494     = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
 495   reg_last_set_nonzero_bits
 496     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 497   reg_last_set_sign_bit_copies
 498     = (char *) alloca (nregs * sizeof (char));
 499
 500   init_reg_last_arrays ();
 501
 502   init_recog_no_volatile ();
 503
 504   /* Compute maximum uid value so uid_cuid can be allocated.  */
 505
 506   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 507     if (INSN_UID (insn) > i)
 508       i = INSN_UID (insn);
 509
 510   uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
 511   max_uid_cuid = i;
 512
 513   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 514
 515   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 516      when, for example, we have j <<= 1 in a loop.  */
 517
 518   nonzero_sign_valid = 0;
 519
 520   /* Compute the mapping from uids to cuids.
 521      Cuids are numbers assigned to insns, like uids,
 522      except that cuids increase monotonically through the code.
 523
 524      Scan all SETs and see if we can deduce anything about what
 525      bits are known to be zero for some registers and how many copies
 526      of the sign bit are known to exist for those registers.
 527
 528      Also set any known values so that we can use it while searching
 529      for what bits are known to be set.  */
 530
 531   label_tick = 1;
 532
 533   /* We need to initialize it here, because record_dead_and_set_regs may call
 534      get_last_value.  */
 535   subst_prev_insn = NULL_RTX;
 536
 537   setup_incoming_promotions ();
 538
 539   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 540     {
 541       uid_cuid[INSN_UID (insn)] = ++i;
 542       subst_low_cuid = i;
 543       subst_insn = insn;
 544
 545       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 546         {
 547           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
 548           record_dead_and_set_regs (insn);
 549
 550 #ifdef AUTO_INC_DEC
 551           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 552             if (REG_NOTE_KIND (links) == REG_INC)
 553               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
 554 #endif
 555         }
 556
 557       if (GET_CODE (insn) == CODE_LABEL)
 558         label_tick++;
 559     }
 560
 561   nonzero_sign_valid = 1;
 562
 563   /* Now scan all the insns in forward order.  */
 564
 565   this_basic_block = -1;
 566   label_tick = 1;
 567   last_call_cuid = 0;
 568   mem_last_set = 0;
 569   init_reg_last_arrays ();
 570   setup_incoming_promotions ();
 571
 572   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 573     {
 574       next = 0;
 575
 576       /* If INSN starts a new basic block, update our basic block number.  */
 577       if (this_basic_block + 1 < n_basic_blocks
 578           && basic_block_head[this_basic_block + 1] == insn)
 579         this_basic_block++;
 580
 581       if (GET_CODE (insn) == CODE_LABEL)
 582         label_tick++;
 583
 584       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 585         {
 586           /* Try this insn with each insn it links back to.  */
 587
 588           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 589             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 590               goto retry;
 591
 592           /* Try each sequence of three linked insns ending with this one.  */
 593
 594           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 595             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 596                  nextlinks = XEXP (nextlinks, 1))
 597               if ((next = try_combine (insn, XEXP (links, 0),
 598                                        XEXP (nextlinks, 0))) != 0)
 599                 goto retry;
 600
 601 #ifdef HAVE_cc0
 602           /* Try to combine a jump insn that uses CC0
 603              with a preceding insn that sets CC0, and maybe with its
 604              logical predecessor as well.
 605              This is how we make decrement-and-branch insns.
 606              We need this special code because data flow connections
 607              via CC0 do not get entered in LOG_LINKS.  */
 608
 609           if (GET_CODE (insn) == JUMP_INSN
 610               && (prev = prev_nonnote_insn (insn)) != 0
 611               && GET_CODE (prev) == INSN
 612               && sets_cc0_p (PATTERN (prev)))
 613             {
 614               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 615                 goto retry;
 616
 617               for (nextlinks = LOG_LINKS (prev); nextlinks;
 618                    nextlinks = XEXP (nextlinks, 1))
 619                 if ((next = try_combine (insn, prev,
 620                                          XEXP (nextlinks, 0))) != 0)
 621                   goto retry;
 622             }
 623
 624           /* Do the same for an insn that explicitly references CC0.  */
 625           if (GET_CODE (insn) == INSN
 626               && (prev = prev_nonnote_insn (insn)) != 0
 627               && GET_CODE (prev) == INSN
 628               && sets_cc0_p (PATTERN (prev))
 629               && GET_CODE (PATTERN (insn)) == SET
 630               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 631             {
 632               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 633                 goto retry;
 634
 635               for (nextlinks = LOG_LINKS (prev); nextlinks;
 636                    nextlinks = XEXP (nextlinks, 1))
 637                 if ((next = try_combine (insn, prev,
 638                                          XEXP (nextlinks, 0))) != 0)
 639                   goto retry;
 640             }
 641
 642           /* Finally, see if any of the insns that this insn links to
 643              explicitly references CC0.  If so, try this insn, that insn,
 644              and its predecessor if it sets CC0.  */
 645           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 646             if (GET_CODE (XEXP (links, 0)) == INSN
 647                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 648                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 649                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 650                 && GET_CODE (prev) == INSN
 651                 && sets_cc0_p (PATTERN (prev))
 652                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 653               goto retry;
 654 #endif
 655
 656           /* Try combining an insn with two different insns whose results it
 657              uses.  */
 658           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 659             for (nextlinks = XEXP (links, 1); nextlinks;
 660                  nextlinks = XEXP (nextlinks, 1))
 661               if ((next = try_combine (insn, XEXP (links, 0),
 662                                        XEXP (nextlinks, 0))) != 0)
 663                 goto retry;
 664
 665           if (GET_CODE (insn) != NOTE)
 666             record_dead_and_set_regs (insn);
 667
 668         retry:
 669           ;
 670         }
 671     }
 672
 673   total_attempts += combine_attempts;
 674   total_merges += combine_merges;
 675   total_extras += combine_extras;
 676   total_successes += combine_successes;
 677
 678   nonzero_sign_valid = 0;
 679 }
 680
 681 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 682
 683 static void
 684 init_reg_last_arrays ()
 685 {
 686   int nregs = combine_max_regno;
 687
 688   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 689   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 690   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 691   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 692   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 693   bzero (reg_last_set_invalid, nregs * sizeof (char));
 694   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 695   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 696   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 697 }
 698 \f
 699 /* Set up any promoted values for incoming argument registers.  */
 700
 701 static void
 702 setup_incoming_promotions ()
 703 {
 704 #ifdef PROMOTE_FUNCTION_ARGS
 705   int regno;
 706   rtx reg;
 707   enum machine_mode mode;
 708   int unsignedp;
 709   rtx first = get_insns ();
 710
 711   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 712     if (FUNCTION_ARG_REGNO_P (regno)
 713         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 714       record_value_for_reg (reg, first,
 715                             gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
 716                                      GET_MODE (reg),
 717                                      gen_rtx (CLOBBER, mode, const0_rtx)));
 718 #endif
 719 }
 720 \f
 721 /* Called via note_stores.  If X is a pseudo that is narrower than
 722    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 723
 724    If we are setting only a portion of X and we can't figure out what
 725    portion, assume all bits will be used since we don't know what will
 726    be happening.
 727
 728    Similarly, set how many bits of X are known to be copies of the sign bit
 729    at all locations in the function.  This is the smallest number implied
 730    by any set of X.  */
 731
 732 static void
 733 set_nonzero_bits_and_sign_copies (x, set)
 734      rtx x;
 735      rtx set;
 736 {
 737   int num;
 738
 739   if (GET_CODE (x) == REG
 740       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 741       /* If this register is undefined at the start of the file, we can't
 742          say what its contents were.  */
 743       && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
 744             & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
 745       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 746     {
 747       if (set == 0 || GET_CODE (set) == CLOBBER)
 748         {
 749           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 750           reg_sign_bit_copies[REGNO (x)] = 1;
 751           return;
 752         }
 753
 754       /* If this is a complex assignment, see if we can convert it into a
 755          simple assignment.  */
 756       set = expand_field_assignment (set);
 757
 758       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 759          set what we know about X.  */
 760
 761       if (SET_DEST (set) == x
 762           || (GET_CODE (SET_DEST (set)) == SUBREG
 763               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 764                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 765               && SUBREG_REG (SET_DEST (set)) == x))
 766         {
 767           rtx src = SET_SRC (set);
 768
 769 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 770           /* If X is narrower than a word and SRC is a non-negative
 771              constant that would appear negative in the mode of X,
 772              sign-extend it for use in reg_nonzero_bits because some
 773              machines (maybe most) will actually do the sign-extension
 774              and this is the conservative approach.
 775
 776              ??? For 2.5, try to tighten up the MD files in this regard
 777              instead of this kludge.  */
 778
 779           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 780               && GET_CODE (src) == CONST_INT
 781               && INTVAL (src) > 0
 782               && 0 != (INTVAL (src)
 783                        & ((HOST_WIDE_INT) 1
 784                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 785             src = GEN_INT (INTVAL (src)
 786                            | ((HOST_WIDE_INT) (-1)
 787                               << GET_MODE_BITSIZE (GET_MODE (x))));
 788 #endif
 789
 790           reg_nonzero_bits[REGNO (x)]
 791             |= nonzero_bits (src, nonzero_bits_mode);
 792           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 793           if (reg_sign_bit_copies[REGNO (x)] == 0
 794               || reg_sign_bit_copies[REGNO (x)] > num)
 795             reg_sign_bit_copies[REGNO (x)] = num;
 796         }
 797       else
 798         {
 799           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 800           reg_sign_bit_copies[REGNO (x)] = 1;
 801         }
 802     }
 803 }
 804 \f
 805 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 806    insns that were previously combined into I3 or that will be combined
 807    into the merger of INSN and I3.
 808
 809    Return 0 if the combination is not allowed for any reason.
 810
 811    If the combination is allowed, *PDEST will be set to the single
 812    destination of INSN and *PSRC to the single source, and this function
 813    will return 1.  */
 814
 815 static int
 816 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 817      rtx insn;
 818      rtx i3;
 819      rtx pred, succ;
 820      rtx *pdest, *psrc;
 821 {
 822   int i;
 823   rtx set = 0, src, dest;
 824   rtx p, link;
 825   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 826                               && next_active_insn (succ) == i3)
 827                       : next_active_insn (insn) == i3);
 828
 829   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 830      or a PARALLEL consisting of such a SET and CLOBBERs.
 831
 832      If INSN has CLOBBER parallel parts, ignore them for our processing.
 833      By definition, these happen during the execution of the insn.  When it
 834      is merged with another insn, all bets are off.  If they are, in fact,
 835      needed and aren't also supplied in I3, they may be added by
 836      recog_for_combine.  Otherwise, it won't match.
 837
 838      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 839      note.
 840
 841      Get the source and destination of INSN.  If more than one, can't
 842      combine.  */
 843
 844   if (GET_CODE (PATTERN (insn)) == SET)
 845     set = PATTERN (insn);
 846   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 847            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 848     {
 849       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 850         {
 851           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 852
 853           switch (GET_CODE (elt))
 854             {
 855               /* We can ignore CLOBBERs.  */
 856             case CLOBBER:
 857               break;
 858
 859             case SET:
 860               /* Ignore SETs whose result isn't used but not those that
 861                  have side-effects.  */
 862               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 863                   && ! side_effects_p (elt))
 864                 break;
 865
 866               /* If we have already found a SET, this is a second one and
 867                  so we cannot combine with this insn.  */
 868               if (set)
 869                 return 0;
 870
 871               set = elt;
 872               break;
 873
 874             default:
 875               /* Anything else means we can't combine.  */
 876               return 0;
 877             }
 878         }
 879
 880       if (set == 0
 881           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 882              so don't do anything with it.  */
 883           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
 884         return 0;
 885     }
 886   else
 887     return 0;
 888
 889   if (set == 0)
 890     return 0;
 891
 892   set = expand_field_assignment (set);
 893   src = SET_SRC (set), dest = SET_DEST (set);
 894
 895   /* Don't eliminate a store in the stack pointer.  */
 896   if (dest == stack_pointer_rtx
 897       /* If we couldn't eliminate a field assignment, we can't combine.  */
 898       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
 899       /* Don't combine with an insn that sets a register to itself if it has
 900          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
 901       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
 902       /* Can't merge a function call.  */
 903       || GET_CODE (src) == CALL
 904       /* Don't eliminate a function call argument.  */
 905       || (GET_CODE (i3) == CALL_INSN
 906           && (find_reg_fusage (i3, USE, dest)
 907               || (GET_CODE (dest) == REG
 908                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
 909                   && global_regs[REGNO (dest)])))
 910       /* Don't substitute into an incremented register.  */
 911       || FIND_REG_INC_NOTE (i3, dest)
 912       || (succ && FIND_REG_INC_NOTE (succ, dest))
 913       /* Don't combine the end of a libcall into anything.  */
 914       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
 915       /* Make sure that DEST is not used after SUCC but before I3.  */
 916       || (succ && ! all_adjacent
 917           && reg_used_between_p (dest, succ, i3))
 918       /* Make sure that the value that is to be substituted for the register
 919          does not use any registers whose values alter in between.  However,
 920          If the insns are adjacent, a use can't cross a set even though we
 921          think it might (this can happen for a sequence of insns each setting
 922          the same destination; reg_last_set of that register might point to
 923          a NOTE).  If INSN has a REG_EQUIV note, the register is always
 924          equivalent to the memory so the substitution is valid even if there
 925          are intervening stores.  Also, don't move a volatile asm or
 926          UNSPEC_VOLATILE across any other insns.  */
 927       || (! all_adjacent
 928           && (((GET_CODE (src) != MEM
 929                 || ! find_reg_note (insn, REG_EQUIV, src))
 930                && use_crosses_set_p (src, INSN_CUID (insn)))
 931               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
 932               || GET_CODE (src) == UNSPEC_VOLATILE))
 933       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
 934          better register allocation by not doing the combine.  */
 935       || find_reg_note (i3, REG_NO_CONFLICT, dest)
 936       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
 937       /* Don't combine across a CALL_INSN, because that would possibly
 938          change whether the life span of some REGs crosses calls or not,
 939          and it is a pain to update that information.
 940          Exception: if source is a constant, moving it later can't hurt.
 941          Accept that special case, because it helps -fforce-addr a lot.  */
 942       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
 943     return 0;
 944
 945   /* DEST must either be a REG or CC0.  */
 946   if (GET_CODE (dest) == REG)
 947     {
 948       /* If register alignment is being enforced for multi-word items in all
 949          cases except for parameters, it is possible to have a register copy
 950          insn referencing a hard register that is not allowed to contain the
 951          mode being copied and which would not be valid as an operand of most
 952          insns.  Eliminate this problem by not combining with such an insn.
 953
 954          Also, on some machines we don't want to extend the life of a hard
 955          register.
 956
 957          This is the same test done in can_combine except that we don't test
 958          if SRC is a CALL operation to permit a hard register with
 959          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
 960          into account.  */
 961
 962       if (GET_CODE (src) == REG
 963           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
 964                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
 965               /* Don't extend the life of a hard register unless it is
 966                  user variable (if we have few registers) or it can't
 967                  fit into the desired register (meaning something special
 968                  is going on).
 969                  Also avoid substituting a return register into I3, because
 970                  reload can't handle a conflict with constraints of other
 971                  inputs.  */
 972               || (REGNO (src) < FIRST_PSEUDO_REGISTER
 973                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
 974 #ifdef SMALL_REGISTER_CLASSES
 975                       || (SMALL_REGISTER_CLASSES
 976                           && ((! all_adjacent && ! REG_USERVAR_P (src))
 977                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
 978                                   && ! REG_USERVAR_P (src))))
 979 #endif
 980                       ))))
 981         return 0;
 982     }
 983   else if (GET_CODE (dest) != CC0)
 984     return 0;
 985
 986   /* Don't substitute for a register intended as a clobberable operand.
 987      Similarly, don't substitute an expression containing a register that
 988      will be clobbered in I3.  */
 989   if (GET_CODE (PATTERN (i3)) == PARALLEL)
 990     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
 991       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
 992           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
 993                                        src)
 994               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
 995         return 0;
 996
 997   /* If INSN contains anything volatile, or is an `asm' (whether volatile
 998      or not), reject, unless nothing volatile comes between it and I3,
 999      with the exception of SUCC.  */
1000
1001   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1002     for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1003       if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1004           && p != succ && volatile_refs_p (PATTERN (p)))
1005         return 0;
1006
1007   /* If there are any volatile insns between INSN and I3, reject, because
1008      they might affect machine state.  */
1009
1010   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1011     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1012         && p != succ && volatile_insn_p (PATTERN (p)))
1013       return 0;
1014
1015   /* If INSN or I2 contains an autoincrement or autodecrement,
1016      make sure that register is not used between there and I3,
1017      and not already used in I3 either.
1018      Also insist that I3 not be a jump; if it were one
1019      and the incremented register were spilled, we would lose.  */
1020
1021 #ifdef AUTO_INC_DEC
1022   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1023     if (REG_NOTE_KIND (link) == REG_INC
1024         && (GET_CODE (i3) == JUMP_INSN
1025             || reg_used_between_p (XEXP (link, 0), insn, i3)
1026             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1027       return 0;
1028 #endif
1029
1030 #ifdef HAVE_cc0
1031   /* Don't combine an insn that follows a CC0-setting insn.
1032      An insn that uses CC0 must not be separated from the one that sets it.
1033      We do, however, allow I2 to follow a CC0-setting insn if that insn
1034      is passed as I1; in that case it will be deleted also.
1035      We also allow combining in this case if all the insns are adjacent
1036      because that would leave the two CC0 insns adjacent as well.
1037      It would be more logical to test whether CC0 occurs inside I1 or I2,
1038      but that would be much slower, and this ought to be equivalent.  */
1039
1040   p = prev_nonnote_insn (insn);
1041   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1042       && ! all_adjacent)
1043     return 0;
1044 #endif
1045
1046   /* If we get here, we have passed all the tests and the combination is
1047      to be allowed.  */
1048
1049   *pdest = dest;
1050   *psrc = src;
1051
1052   return 1;
1053 }
1054 \f
1055 /* LOC is the location within I3 that contains its pattern or the component
1056    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1057
1058    One problem is if I3 modifies its output, as opposed to replacing it
1059    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1060    so would produce an insn that is not equivalent to the original insns.
1061
1062    Consider:
1063
1064          (set (reg:DI 101) (reg:DI 100))
1065          (set (subreg:SI (reg:DI 101) 0) <foo>)
1066
1067    This is NOT equivalent to:
1068
1069          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1070                     (set (reg:DI 101) (reg:DI 100))])
1071
1072    Not only does this modify 100 (in which case it might still be valid
1073    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1074
1075    We can also run into a problem if I2 sets a register that I1
1076    uses and I1 gets directly substituted into I3 (not via I2).  In that
1077    case, we would be getting the wrong value of I2DEST into I3, so we
1078    must reject the combination.  This case occurs when I2 and I1 both
1079    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1080    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1081    of a SET must prevent combination from occurring.
1082
1083    On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1084    if the destination of a SET is a hard register that isn't a user
1085    variable.
1086
1087    Before doing the above check, we first try to expand a field assignment
1088    into a set of logical operations.
1089
1090    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1091    we place a register that is both set and used within I3.  If more than one
1092    such register is detected, we fail.
1093
1094    Return 1 if the combination is valid, zero otherwise.  */
1095
1096 static int
1097 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1098      rtx i3;
1099      rtx *loc;
1100      rtx i2dest;
1101      rtx i1dest;
1102      int i1_not_in_src;
1103      rtx *pi3dest_killed;
1104 {
1105   rtx x = *loc;
1106
1107   if (GET_CODE (x) == SET)
1108     {
1109       rtx set = expand_field_assignment (x);
1110       rtx dest = SET_DEST (set);
1111       rtx src = SET_SRC (set);
1112       rtx inner_dest = dest, inner_src = src;
1113
1114       SUBST (*loc, set);
1115
1116       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1117              || GET_CODE (inner_dest) == SUBREG
1118              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1119         inner_dest = XEXP (inner_dest, 0);
1120
1121   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1122      was added.  */
1123 #if 0
1124       while (GET_CODE (inner_src) == STRICT_LOW_PART
1125              || GET_CODE (inner_src) == SUBREG
1126              || GET_CODE (inner_src) == ZERO_EXTRACT)
1127         inner_src = XEXP (inner_src, 0);
1128
1129       /* If it is better that two different modes keep two different pseudos,
1130          avoid combining them.  This avoids producing the following pattern
1131          on a 386:
1132           (set (subreg:SI (reg/v:QI 21) 0)
1133                (lshiftrt:SI (reg/v:SI 20)
1134                    (const_int 24)))
1135          If that were made, reload could not handle the pair of
1136          reg 20/21, since it would try to get any GENERAL_REGS
1137          but some of them don't handle QImode.  */
1138
1139       if (rtx_equal_p (inner_src, i2dest)
1140           && GET_CODE (inner_dest) == REG
1141           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1142         return 0;
1143 #endif
1144
1145       /* Check for the case where I3 modifies its output, as
1146          discussed above.  */
1147       if ((inner_dest != dest
1148            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1149                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1150           /* This is the same test done in can_combine_p except that we
1151              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1152              CALL operation.
1153              Moreover, we can't test all_adjacent; we don't have to, since
1154              this instruction will stay in place, thus we are not considering
1155              to increase the lifetime of INNER_DEST.  */
1156           || (GET_CODE (inner_dest) == REG
1157               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1158               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1159                                         GET_MODE (inner_dest))
1160 #ifdef SMALL_REGISTER_CLASSES
1161                  || (SMALL_REGISTER_CLASSES
1162                      && GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)
1163                      && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))
1164 #endif
1165                   ))
1166           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1167         return 0;
1168
1169       /* If DEST is used in I3, it is being killed in this insn,
1170          so record that for later.
1171          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1172          STACK_POINTER_REGNUM, since these are always considered to be
1173          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1174       if (pi3dest_killed && GET_CODE (dest) == REG
1175           && reg_referenced_p (dest, PATTERN (i3))
1176           && REGNO (dest) != FRAME_POINTER_REGNUM
1177 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1178           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1179 #endif
1180 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1181           && (REGNO (dest) != ARG_POINTER_REGNUM
1182               || ! fixed_regs [REGNO (dest)])
1183 #endif
1184           && REGNO (dest) != STACK_POINTER_REGNUM)
1185         {
1186           if (*pi3dest_killed)
1187             return 0;
1188
1189           *pi3dest_killed = dest;
1190         }
1191     }
1192
1193   else if (GET_CODE (x) == PARALLEL)
1194     {
1195       int i;
1196
1197       for (i = 0; i < XVECLEN (x, 0); i++)
1198         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1199                                 i1_not_in_src, pi3dest_killed))
1200           return 0;
1201     }
1202
1203   return 1;
1204 }
1205 \f
1206 /* Try to combine the insns I1 and I2 into I3.
1207    Here I1 and I2 appear earlier than I3.
1208    I1 can be zero; then we combine just I2 into I3.
1209
1210    It we are combining three insns and the resulting insn is not recognized,
1211    try splitting it into two insns.  If that happens, I2 and I3 are retained
1212    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1213    are pseudo-deleted.
1214
1215    Return 0 if the combination does not work.  Then nothing is changed.
1216    If we did the combination, return the insn at which combine should
1217    resume scanning.  */
1218
1219 static rtx
1220 try_combine (i3, i2, i1)
1221      register rtx i3, i2, i1;
1222 {
1223   /* New patterns for I3 and I3, respectively.  */
1224   rtx newpat, newi2pat = 0;
1225   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1226   int added_sets_1, added_sets_2;
1227   /* Total number of SETs to put into I3.  */
1228   int total_sets;
1229   /* Nonzero is I2's body now appears in I3.  */
1230   int i2_is_used;
1231   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1232   int insn_code_number, i2_code_number, other_code_number;
1233   /* Contains I3 if the destination of I3 is used in its source, which means
1234      that the old life of I3 is being killed.  If that usage is placed into
1235      I2 and not in I3, a REG_DEAD note must be made.  */
1236   rtx i3dest_killed = 0;
1237   /* SET_DEST and SET_SRC of I2 and I1.  */
1238   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1239   /* PATTERN (I2), or a copy of it in certain cases.  */
1240   rtx i2pat;
1241   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1242   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1243   int i1_feeds_i3 = 0;
1244   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1245   rtx new_i3_notes, new_i2_notes;
1246   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1247   int i3_subst_into_i2 = 0;
1248   /* Notes that I1, I2 or I3 is a MULT operation.  */
1249   int have_mult = 0;
1250   /* Number of clobbers of SCRATCH we had to add.  */
1251   int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1252
1253   int maxreg;
1254   rtx temp;
1255   register rtx link;
1256   int i;
1257
1258   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1259      This can occur when flow deletes an insn that it has merged into an
1260      auto-increment address.  We also can't do anything if I3 has a
1261      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1262      libcall.  */
1263
1264   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1265       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1266       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1267       || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1268     return 0;
1269
1270   combine_attempts++;
1271
1272   undobuf.undos = undobuf.previous_undos = 0;
1273   undobuf.other_insn = 0;
1274
1275   /* Save the current high-water-mark so we can free storage if we didn't
1276      accept this combination.  */
1277   undobuf.storage = (char *) oballoc (0);
1278
1279   /* Reset the hard register usage information.  */
1280   CLEAR_HARD_REG_SET (newpat_used_regs);
1281
1282   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1283      code below, set I1 to be the earlier of the two insns.  */
1284   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1285     temp = i1, i1 = i2, i2 = temp;
1286
1287   added_links_insn = 0;
1288
1289   /* First check for one important special-case that the code below will
1290      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1291      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1292      we may be able to replace that destination with the destination of I3.
1293      This occurs in the common code where we compute both a quotient and
1294      remainder into a structure, in which case we want to do the computation
1295      directly into the structure to avoid register-register copies.
1296
1297      We make very conservative checks below and only try to handle the
1298      most common cases of this.  For example, we only handle the case
1299      where I2 and I3 are adjacent to avoid making difficult register
1300      usage tests.  */
1301
1302   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1303       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1304       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1305 #ifdef SMALL_REGISTER_CLASSES
1306       && (! SMALL_REGISTER_CLASSES
1307           || GET_CODE (SET_DEST (PATTERN (i3))) != REG
1308           || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1309           || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1310 #endif
1311       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1312       && GET_CODE (PATTERN (i2)) == PARALLEL
1313       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1314       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1315          below would need to check what is inside (and reg_overlap_mentioned_p
1316          doesn't support those codes anyway).  Don't allow those destinations;
1317          the resulting insn isn't likely to be recognized anyway.  */
1318       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1319       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1320       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1321                                     SET_DEST (PATTERN (i3)))
1322       && next_real_insn (i2) == i3)
1323     {
1324       rtx p2 = PATTERN (i2);
1325
1326       /* Make sure that the destination of I3,
1327          which we are going to substitute into one output of I2,
1328          is not used within another output of I2.  We must avoid making this:
1329          (parallel [(set (mem (reg 69)) ...)
1330                     (set (reg 69) ...)])
1331          which is not well-defined as to order of actions.
1332          (Besides, reload can't handle output reloads for this.)
1333
1334          The problem can also happen if the dest of I3 is a memory ref,
1335          if another dest in I2 is an indirect memory ref.  */
1336       for (i = 0; i < XVECLEN (p2, 0); i++)
1337         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1338              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1339             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1340                                         SET_DEST (XVECEXP (p2, 0, i))))
1341           break;
1342
1343       if (i == XVECLEN (p2, 0))
1344         for (i = 0; i < XVECLEN (p2, 0); i++)
1345           if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1346             {
1347               combine_merges++;
1348
1349               subst_insn = i3;
1350               subst_low_cuid = INSN_CUID (i2);
1351
1352               added_sets_2 = added_sets_1 = 0;
1353               i2dest = SET_SRC (PATTERN (i3));
1354
1355               /* Replace the dest in I2 with our dest and make the resulting
1356                  insn the new pattern for I3.  Then skip to where we
1357                  validate the pattern.  Everything was set up above.  */
1358               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1359                      SET_DEST (PATTERN (i3)));
1360
1361               newpat = p2;
1362               i3_subst_into_i2 = 1;
1363               goto validate_replacement;
1364             }
1365     }
1366
1367 #ifndef HAVE_cc0
1368   /* If we have no I1 and I2 looks like:
1369         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1370                    (set Y OP)])
1371      make up a dummy I1 that is
1372         (set Y OP)
1373      and change I2 to be
1374         (set (reg:CC X) (compare:CC Y (const_int 0)))
1375
1376      (We can ignore any trailing CLOBBERs.)
1377
1378      This undoes a previous combination and allows us to match a branch-and-
1379      decrement insn.  */
1380
1381   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1382       && XVECLEN (PATTERN (i2), 0) >= 2
1383       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1384       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1385           == MODE_CC)
1386       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1387       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1388       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1389       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1390       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1391                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1392     {
1393       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1394         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1395           break;
1396
1397       if (i == 1)
1398         {
1399           /* We make I1 with the same INSN_UID as I2.  This gives it
1400              the same INSN_CUID for value tracking.  Our fake I1 will
1401              never appear in the insn stream so giving it the same INSN_UID
1402              as I2 will not cause a problem.  */
1403
1404           subst_prev_insn = i1
1405             = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1406                        XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1407
1408           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1409           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1410                  SET_DEST (PATTERN (i1)));
1411         }
1412     }
1413 #endif
1414
1415   /* Verify that I2 and I1 are valid for combining.  */
1416   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1417       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1418     {
1419       undo_all ();
1420       return 0;
1421     }
1422
1423   /* Record whether I2DEST is used in I2SRC and similarly for the other
1424      cases.  Knowing this will help in register status updating below.  */
1425   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1426   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1427   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1428
1429   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1430      in I2SRC.  */
1431   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1432
1433   /* Ensure that I3's pattern can be the destination of combines.  */
1434   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1435                           i1 && i2dest_in_i1src && i1_feeds_i3,
1436                           &i3dest_killed))
1437     {
1438       undo_all ();
1439       return 0;
1440     }
1441
1442   /* See if any of the insns is a MULT operation.  Unless one is, we will
1443      reject a combination that is, since it must be slower.  Be conservative
1444      here.  */
1445   if (GET_CODE (i2src) == MULT
1446       || (i1 != 0 && GET_CODE (i1src) == MULT)
1447       || (GET_CODE (PATTERN (i3)) == SET
1448           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1449     have_mult = 1;
1450
1451   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1452      We used to do this EXCEPT in one case: I3 has a post-inc in an
1453      output operand.  However, that exception can give rise to insns like
1454         mov r3,(r3)+
1455      which is a famous insn on the PDP-11 where the value of r3 used as the
1456      source was model-dependent.  Avoid this sort of thing.  */
1457
1458 #if 0
1459   if (!(GET_CODE (PATTERN (i3)) == SET
1460         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1461         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1462         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1463             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1464     /* It's not the exception.  */
1465 #endif
1466 #ifdef AUTO_INC_DEC
1467     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1468       if (REG_NOTE_KIND (link) == REG_INC
1469           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1470               || (i1 != 0
1471                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1472         {
1473           undo_all ();
1474           return 0;
1475         }
1476 #endif
1477
1478   /* See if the SETs in I1 or I2 need to be kept around in the merged
1479      instruction: whenever the value set there is still needed past I3.
1480      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1481
1482      For the SET in I1, we have two cases:  If I1 and I2 independently
1483      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1484      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1485      in I1 needs to be kept around unless I1DEST dies or is set in either
1486      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1487      I1DEST.  If so, we know I1 feeds into I2.  */
1488
1489   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1490
1491   added_sets_1
1492     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1493                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1494
1495   /* If the set in I2 needs to be kept around, we must make a copy of
1496      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1497      PATTERN (I2), we are only substituting for the original I1DEST, not into
1498      an already-substituted copy.  This also prevents making self-referential
1499      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1500      I2DEST.  */
1501
1502   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1503            ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1504            : PATTERN (i2));
1505
1506   if (added_sets_2)
1507     i2pat = copy_rtx (i2pat);
1508
1509   combine_merges++;
1510
1511   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1512
1513   maxreg = max_reg_num ();
1514
1515   subst_insn = i3;
1516
1517   /* It is possible that the source of I2 or I1 may be performing an
1518      unneeded operation, such as a ZERO_EXTEND of something that is known
1519      to have the high part zero.  Handle that case by letting subst look at
1520      the innermost one of them.
1521
1522      Another way to do this would be to have a function that tries to
1523      simplify a single insn instead of merging two or more insns.  We don't
1524      do this because of the potential of infinite loops and because
1525      of the potential extra memory required.  However, doing it the way
1526      we are is a bit of a kludge and doesn't catch all cases.
1527
1528      But only do this if -fexpensive-optimizations since it slows things down
1529      and doesn't usually win.  */
1530
1531   if (flag_expensive_optimizations)
1532     {
1533       /* Pass pc_rtx so no substitutions are done, just simplifications.
1534          The cases that we are interested in here do not involve the few
1535          cases were is_replaced is checked.  */
1536       if (i1)
1537         {
1538           subst_low_cuid = INSN_CUID (i1);
1539           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1540         }
1541       else
1542         {
1543           subst_low_cuid = INSN_CUID (i2);
1544           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1545         }
1546
1547       undobuf.previous_undos = undobuf.undos;
1548     }
1549
1550 #ifndef HAVE_cc0
1551   /* Many machines that don't use CC0 have insns that can both perform an
1552      arithmetic operation and set the condition code.  These operations will
1553      be represented as a PARALLEL with the first element of the vector
1554      being a COMPARE of an arithmetic operation with the constant zero.
1555      The second element of the vector will set some pseudo to the result
1556      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1557      match such a pattern and so will generate an extra insn.   Here we test
1558      for this case, where both the comparison and the operation result are
1559      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1560      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1561
1562   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1563       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1564       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1565       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1566     {
1567       rtx *cc_use;
1568       enum machine_mode compare_mode;
1569
1570       newpat = PATTERN (i3);
1571       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1572
1573       i2_is_used = 1;
1574
1575 #ifdef EXTRA_CC_MODES
1576       /* See if a COMPARE with the operand we substituted in should be done
1577          with the mode that is currently being used.  If not, do the same
1578          processing we do in `subst' for a SET; namely, if the destination
1579          is used only once, try to replace it with a register of the proper
1580          mode and also replace the COMPARE.  */
1581       if (undobuf.other_insn == 0
1582           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1583                                         &undobuf.other_insn))
1584           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1585                                               i2src, const0_rtx))
1586               != GET_MODE (SET_DEST (newpat))))
1587         {
1588           int regno = REGNO (SET_DEST (newpat));
1589           rtx new_dest = gen_rtx (REG, compare_mode, regno);
1590
1591           if (regno < FIRST_PSEUDO_REGISTER
1592               || (reg_n_sets[regno] == 1 && ! added_sets_2
1593                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1594             {
1595               if (regno >= FIRST_PSEUDO_REGISTER)
1596                 SUBST (regno_reg_rtx[regno], new_dest);
1597
1598               SUBST (SET_DEST (newpat), new_dest);
1599               SUBST (XEXP (*cc_use, 0), new_dest);
1600               SUBST (SET_SRC (newpat),
1601                      gen_rtx_combine (COMPARE, compare_mode,
1602                                       i2src, const0_rtx));
1603             }
1604           else
1605             undobuf.other_insn = 0;
1606         }
1607 #endif
1608     }
1609   else
1610 #endif
1611     {
1612       n_occurrences = 0;                /* `subst' counts here */
1613
1614       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1615          need to make a unique copy of I2SRC each time we substitute it
1616          to avoid self-referential rtl.  */
1617
1618       subst_low_cuid = INSN_CUID (i2);
1619       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1620                       ! i1_feeds_i3 && i1dest_in_i1src);
1621       undobuf.previous_undos = undobuf.undos;
1622
1623       /* Record whether i2's body now appears within i3's body.  */
1624       i2_is_used = n_occurrences;
1625     }
1626
1627   /* If we already got a failure, don't try to do more.  Otherwise,
1628      try to substitute in I1 if we have it.  */
1629
1630   if (i1 && GET_CODE (newpat) != CLOBBER)
1631     {
1632       /* Before we can do this substitution, we must redo the test done
1633          above (see detailed comments there) that ensures  that I1DEST
1634          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1635
1636       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1637                               0, NULL_PTR))
1638         {
1639           undo_all ();
1640           return 0;
1641         }
1642
1643       n_occurrences = 0;
1644       subst_low_cuid = INSN_CUID (i1);
1645       newpat = subst (newpat, i1dest, i1src, 0, 0);
1646       undobuf.previous_undos = undobuf.undos;
1647     }
1648
1649   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1650      to count all the ways that I2SRC and I1SRC can be used.  */
1651   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1652        && i2_is_used + added_sets_2 > 1)
1653       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1654           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1655               > 1))
1656       /* Fail if we tried to make a new register (we used to abort, but there's
1657          really no reason to).  */
1658       || max_reg_num () != maxreg
1659       /* Fail if we couldn't do something and have a CLOBBER.  */
1660       || GET_CODE (newpat) == CLOBBER
1661       /* Fail if this new pattern is a MULT and we didn't have one before
1662          at the outer level.  */
1663       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1664           && ! have_mult))
1665     {
1666       undo_all ();
1667       return 0;
1668     }
1669
1670   /* If the actions of the earlier insns must be kept
1671      in addition to substituting them into the latest one,
1672      we must make a new PARALLEL for the latest insn
1673      to hold additional the SETs.  */
1674
1675   if (added_sets_1 || added_sets_2)
1676     {
1677       combine_extras++;
1678
1679       if (GET_CODE (newpat) == PARALLEL)
1680         {
1681           rtvec old = XVEC (newpat, 0);
1682           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1683           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1684           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1685                  sizeof (old->elem[0]) * old->num_elem);
1686         }
1687       else
1688         {
1689           rtx old = newpat;
1690           total_sets = 1 + added_sets_1 + added_sets_2;
1691           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1692           XVECEXP (newpat, 0, 0) = old;
1693         }
1694
1695      if (added_sets_1)
1696        XVECEXP (newpat, 0, --total_sets)
1697          = (GET_CODE (PATTERN (i1)) == PARALLEL
1698             ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1699
1700      if (added_sets_2)
1701         {
1702           /* If there is no I1, use I2's body as is.  We used to also not do
1703              the subst call below if I2 was substituted into I3,
1704              but that could lose a simplification.  */
1705           if (i1 == 0)
1706             XVECEXP (newpat, 0, --total_sets) = i2pat;
1707           else
1708             /* See comment where i2pat is assigned.  */
1709             XVECEXP (newpat, 0, --total_sets)
1710               = subst (i2pat, i1dest, i1src, 0, 0);
1711         }
1712     }
1713
1714   /* We come here when we are replacing a destination in I2 with the
1715      destination of I3.  */
1716  validate_replacement:
1717
1718   /* Note which hard regs this insn has as inputs.  */
1719   mark_used_regs_combine (newpat);
1720
1721   /* Is the result of combination a valid instruction?  */
1722   insn_code_number
1723     = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1724
1725   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1726      the second SET's destination is a register that is unused.  In that case,
1727      we just need the first SET.   This can occur when simplifying a divmod
1728      insn.  We *must* test for this case here because the code below that
1729      splits two independent SETs doesn't handle this case correctly when it
1730      updates the register status.  Also check the case where the first
1731      SET's destination is unused.  That would not cause incorrect code, but
1732      does cause an unneeded insn to remain.  */
1733
1734   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1735       && XVECLEN (newpat, 0) == 2
1736       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1737       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1738       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1739       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1740       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1741       && asm_noperands (newpat) < 0)
1742     {
1743       newpat = XVECEXP (newpat, 0, 0);
1744       insn_code_number
1745         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1746     }
1747
1748   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1749            && XVECLEN (newpat, 0) == 2
1750            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1751            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1752            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1753            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1754            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1755            && asm_noperands (newpat) < 0)
1756     {
1757       newpat = XVECEXP (newpat, 0, 1);
1758       insn_code_number
1759         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1760     }
1761
1762   /* If we were combining three insns and the result is a simple SET
1763      with no ASM_OPERANDS that wasn't recognized, try to split it into two
1764      insns.  There are two ways to do this.  It can be split using a
1765      machine-specific method (like when you have an addition of a large
1766      constant) or by combine in the function find_split_point.  */
1767
1768   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1769       && asm_noperands (newpat) < 0)
1770     {
1771       rtx m_split, *split;
1772       rtx ni2dest = i2dest;
1773
1774       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
1775          use I2DEST as a scratch register will help.  In the latter case,
1776          convert I2DEST to the mode of the source of NEWPAT if we can.  */
1777
1778       m_split = split_insns (newpat, i3);
1779
1780       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1781          inputs of NEWPAT.  */
1782
1783       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1784          possible to try that as a scratch reg.  This would require adding
1785          more code to make it work though.  */
1786
1787       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1788         {
1789           /* If I2DEST is a hard register or the only use of a pseudo,
1790              we can change its mode.  */
1791           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1792               && GET_MODE (SET_DEST (newpat)) != VOIDmode
1793               && GET_CODE (i2dest) == REG
1794               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1795                   || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1796                       && ! REG_USERVAR_P (i2dest))))
1797             ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1798                                REGNO (i2dest));
1799
1800           m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1801                                           gen_rtvec (2, newpat,
1802                                                      gen_rtx (CLOBBER,
1803                                                               VOIDmode,
1804                                                               ni2dest))),
1805                                  i3);
1806         }
1807
1808       if (m_split && GET_CODE (m_split) == SEQUENCE
1809           && XVECLEN (m_split, 0) == 2
1810           && (next_real_insn (i2) == i3
1811               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1812                                       INSN_CUID (i2))))
1813         {
1814           rtx i2set, i3set;
1815           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1816           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1817
1818           i3set = single_set (XVECEXP (m_split, 0, 1));
1819           i2set = single_set (XVECEXP (m_split, 0, 0));
1820
1821           /* In case we changed the mode of I2DEST, replace it in the
1822              pseudo-register table here.  We can't do it above in case this
1823              code doesn't get executed and we do a split the other way.  */
1824
1825           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1826             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1827
1828           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1829                                               &i2_scratches);
1830
1831           /* If I2 or I3 has multiple SETs, we won't know how to track
1832              register status, so don't use these insns.  If I2's destination
1833              is used between I2 and I3, we also can't use these insns.  */
1834
1835           if (i2_code_number >= 0 && i2set && i3set
1836               && (next_real_insn (i2) == i3
1837                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1838             insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1839                                                   &i3_scratches);
1840           if (insn_code_number >= 0)
1841             newpat = newi3pat;
1842
1843           /* It is possible that both insns now set the destination of I3.
1844              If so, we must show an extra use of it.  */
1845
1846           if (insn_code_number >= 0)
1847             {
1848               rtx new_i3_dest = SET_DEST (i3set);
1849               rtx new_i2_dest = SET_DEST (i2set);
1850
1851               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1852                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1853                      || GET_CODE (new_i3_dest) == SUBREG)
1854                 new_i3_dest = XEXP (new_i3_dest, 0);
1855
1856               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1857                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1858                      || GET_CODE (new_i2_dest) == SUBREG)
1859                 new_i2_dest = XEXP (new_i2_dest, 0);
1860
1861               if (GET_CODE (new_i3_dest) == REG
1862                   && GET_CODE (new_i2_dest) == REG
1863                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1864                 reg_n_sets[REGNO (new_i2_dest)]++;
1865             }
1866         }
1867
1868       /* If we can split it and use I2DEST, go ahead and see if that
1869          helps things be recognized.  Verify that none of the registers
1870          are set between I2 and I3.  */
1871       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1872 #ifdef HAVE_cc0
1873           && GET_CODE (i2dest) == REG
1874 #endif
1875           /* We need I2DEST in the proper mode.  If it is a hard register
1876              or the only use of a pseudo, we can change its mode.  */
1877           && (GET_MODE (*split) == GET_MODE (i2dest)
1878               || GET_MODE (*split) == VOIDmode
1879               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1880               || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1881                   && ! REG_USERVAR_P (i2dest)))
1882           && (next_real_insn (i2) == i3
1883               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1884           /* We can't overwrite I2DEST if its value is still used by
1885              NEWPAT.  */
1886           && ! reg_referenced_p (i2dest, newpat))
1887         {
1888           rtx newdest = i2dest;
1889           enum rtx_code split_code = GET_CODE (*split);
1890           enum machine_mode split_mode = GET_MODE (*split);
1891
1892           /* Get NEWDEST as a register in the proper mode.  We have already
1893              validated that we can do this.  */
1894           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1895             {
1896               newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1897
1898               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1899                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1900             }
1901
1902           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1903              an ASHIFT.  This can occur if it was inside a PLUS and hence
1904              appeared to be a memory address.  This is a kludge.  */
1905           if (split_code == MULT
1906               && GET_CODE (XEXP (*split, 1)) == CONST_INT
1907               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1908             {
1909               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1910                                               XEXP (*split, 0), GEN_INT (i)));
1911               /* Update split_code because we may not have a multiply
1912                  anymore.  */
1913               split_code = GET_CODE (*split);
1914             }
1915
1916 #ifdef INSN_SCHEDULING
1917           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1918              be written as a ZERO_EXTEND.  */
1919           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1920             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1921                                             XEXP (*split, 0)));
1922 #endif
1923
1924           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1925           SUBST (*split, newdest);
1926           i2_code_number
1927             = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1928
1929           /* If the split point was a MULT and we didn't have one before,
1930              don't use one now.  */
1931           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1932             insn_code_number
1933               = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1934         }
1935     }
1936
1937   /* Check for a case where we loaded from memory in a narrow mode and
1938      then sign extended it, but we need both registers.  In that case,
1939      we have a PARALLEL with both loads from the same memory location.
1940      We can split this into a load from memory followed by a register-register
1941      copy.  This saves at least one insn, more if register allocation can
1942      eliminate the copy.
1943
1944      We cannot do this if the destination of the second assignment is
1945      a register that we have already assumed is zero-extended.  Similarly
1946      for a SUBREG of such a register.  */
1947
1948   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1949            && GET_CODE (newpat) == PARALLEL
1950            && XVECLEN (newpat, 0) == 2
1951            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1952            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1953            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1954            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1955                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1956            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1957                                    INSN_CUID (i2))
1958            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1959            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1960            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1961                  (GET_CODE (temp) == REG
1962                   && reg_nonzero_bits[REGNO (temp)] != 0
1963                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1964                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1965                   && (reg_nonzero_bits[REGNO (temp)]
1966                       != GET_MODE_MASK (word_mode))))
1967            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1968                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1969                      (GET_CODE (temp) == REG
1970                       && reg_nonzero_bits[REGNO (temp)] != 0
1971                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1972                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1973                       && (reg_nonzero_bits[REGNO (temp)]
1974                           != GET_MODE_MASK (word_mode)))))
1975            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1976                                          SET_SRC (XVECEXP (newpat, 0, 1)))
1977            && ! find_reg_note (i3, REG_UNUSED,
1978                                SET_DEST (XVECEXP (newpat, 0, 0))))
1979     {
1980       rtx ni2dest;
1981
1982       newi2pat = XVECEXP (newpat, 0, 0);
1983       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1984       newpat = XVECEXP (newpat, 0, 1);
1985       SUBST (SET_SRC (newpat),
1986              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1987       i2_code_number
1988         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1989
1990       if (i2_code_number >= 0)
1991         insn_code_number
1992           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1993
1994       if (insn_code_number >= 0)
1995         {
1996           rtx insn;
1997           rtx link;
1998
1999           /* If we will be able to accept this, we have made a change to the
2000              destination of I3.  This can invalidate a LOG_LINKS pointing
2001              to I3.  No other part of combine.c makes such a transformation.
2002
2003              The new I3 will have a destination that was previously the
2004              destination of I1 or I2 and which was used in i2 or I3.  Call
2005              distribute_links to make a LOG_LINK from the next use of
2006              that destination.  */
2007
2008           PATTERN (i3) = newpat;
2009           distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2010
2011           /* I3 now uses what used to be its destination and which is
2012              now I2's destination.  That means we need a LOG_LINK from
2013              I3 to I2.  But we used to have one, so we still will.
2014
2015              However, some later insn might be using I2's dest and have
2016              a LOG_LINK pointing at I3.  We must remove this link.
2017              The simplest way to remove the link is to point it at I1,
2018              which we know will be a NOTE.  */
2019
2020           for (insn = NEXT_INSN (i3);
2021                insn && (this_basic_block == n_basic_blocks - 1
2022                         || insn != basic_block_head[this_basic_block + 1]);
2023                insn = NEXT_INSN (insn))
2024             {
2025               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2026                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2027                 {
2028                   for (link = LOG_LINKS (insn); link;
2029                        link = XEXP (link, 1))
2030                     if (XEXP (link, 0) == i3)
2031                       XEXP (link, 0) = i1;
2032
2033                   break;
2034                 }
2035             }
2036         }
2037     }
2038
2039   /* Similarly, check for a case where we have a PARALLEL of two independent
2040      SETs but we started with three insns.  In this case, we can do the sets
2041      as two separate insns.  This case occurs when some SET allows two
2042      other insns to combine, but the destination of that SET is still live.  */
2043
2044   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2045            && GET_CODE (newpat) == PARALLEL
2046            && XVECLEN (newpat, 0) == 2
2047            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2048            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2049            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2050            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2051            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2052            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2053            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2054                                    INSN_CUID (i2))
2055            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2056            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2057            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2058            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2059                                   XVECEXP (newpat, 0, 0))
2060            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2061                                   XVECEXP (newpat, 0, 1)))
2062     {
2063       newi2pat = XVECEXP (newpat, 0, 1);
2064       newpat = XVECEXP (newpat, 0, 0);
2065
2066       i2_code_number
2067         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2068
2069       if (i2_code_number >= 0)
2070         insn_code_number
2071           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2072     }
2073
2074   /* If it still isn't recognized, fail and change things back the way they
2075      were.  */
2076   if ((insn_code_number < 0
2077        /* Is the result a reasonable ASM_OPERANDS?  */
2078        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2079     {
2080       undo_all ();
2081       return 0;
2082     }
2083
2084   /* If we had to change another insn, make sure it is valid also.  */
2085   if (undobuf.other_insn)
2086     {
2087       rtx other_pat = PATTERN (undobuf.other_insn);
2088       rtx new_other_notes;
2089       rtx note, next;
2090
2091       CLEAR_HARD_REG_SET (newpat_used_regs);
2092
2093       other_code_number
2094         = recog_for_combine (&other_pat, undobuf.other_insn,
2095                              &new_other_notes, &other_scratches);
2096
2097       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2098         {
2099           undo_all ();
2100           return 0;
2101         }
2102
2103       PATTERN (undobuf.other_insn) = other_pat;
2104
2105       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2106          are still valid.  Then add any non-duplicate notes added by
2107          recog_for_combine.  */
2108       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2109         {
2110           next = XEXP (note, 1);
2111
2112           if (REG_NOTE_KIND (note) == REG_UNUSED
2113               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2114             {
2115               if (GET_CODE (XEXP (note, 0)) == REG)
2116                 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2117
2118               remove_note (undobuf.other_insn, note);
2119             }
2120         }
2121
2122       for (note = new_other_notes; note; note = XEXP (note, 1))
2123         if (GET_CODE (XEXP (note, 0)) == REG)
2124           reg_n_deaths[REGNO (XEXP (note, 0))]++;
2125
2126       distribute_notes (new_other_notes, undobuf.other_insn,
2127                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2128     }
2129
2130   /* We now know that we can do this combination.  Merge the insns and
2131      update the status of registers and LOG_LINKS.  */
2132
2133   {
2134     rtx i3notes, i2notes, i1notes = 0;
2135     rtx i3links, i2links, i1links = 0;
2136     rtx midnotes = 0;
2137     register int regno;
2138     /* Compute which registers we expect to eliminate.  */
2139     rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2140                    ? 0 : i2dest);
2141     rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2142
2143     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2144        clear them.  */
2145     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2146     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2147     if (i1)
2148       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2149
2150     /* Ensure that we do not have something that should not be shared but
2151        occurs multiple times in the new insns.  Check this by first
2152        resetting all the `used' flags and then copying anything is shared.  */
2153
2154     reset_used_flags (i3notes);
2155     reset_used_flags (i2notes);
2156     reset_used_flags (i1notes);
2157     reset_used_flags (newpat);
2158     reset_used_flags (newi2pat);
2159     if (undobuf.other_insn)
2160       reset_used_flags (PATTERN (undobuf.other_insn));
2161
2162     i3notes = copy_rtx_if_shared (i3notes);
2163     i2notes = copy_rtx_if_shared (i2notes);
2164     i1notes = copy_rtx_if_shared (i1notes);
2165     newpat = copy_rtx_if_shared (newpat);
2166     newi2pat = copy_rtx_if_shared (newi2pat);
2167     if (undobuf.other_insn)
2168       reset_used_flags (PATTERN (undobuf.other_insn));
2169
2170     INSN_CODE (i3) = insn_code_number;
2171     PATTERN (i3) = newpat;
2172     if (undobuf.other_insn)
2173       INSN_CODE (undobuf.other_insn) = other_code_number;
2174
2175     /* We had one special case above where I2 had more than one set and
2176        we replaced a destination of one of those sets with the destination
2177        of I3.  In that case, we have to update LOG_LINKS of insns later
2178        in this basic block.  Note that this (expensive) case is rare.
2179
2180        Also, in this case, we must pretend that all REG_NOTEs for I2
2181        actually came from I3, so that REG_UNUSED notes from I2 will be
2182        properly handled.  */
2183
2184     if (i3_subst_into_i2)
2185       {
2186         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2187           if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2188               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2189               && ! find_reg_note (i2, REG_UNUSED,
2190                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2191             for (temp = NEXT_INSN (i2);
2192                  temp && (this_basic_block == n_basic_blocks - 1
2193                           || basic_block_head[this_basic_block] != temp);
2194                  temp = NEXT_INSN (temp))
2195               if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2196                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2197                   if (XEXP (link, 0) == i2)
2198                     XEXP (link, 0) = i3;
2199
2200         if (i3notes)
2201           {
2202             rtx link = i3notes;
2203             while (XEXP (link, 1))
2204               link = XEXP (link, 1);
2205             XEXP (link, 1) = i2notes;
2206           }
2207         else
2208           i3notes = i2notes;
2209         i2notes = 0;
2210       }
2211
2212     LOG_LINKS (i3) = 0;
2213     REG_NOTES (i3) = 0;
2214     LOG_LINKS (i2) = 0;
2215     REG_NOTES (i2) = 0;
2216
2217     if (newi2pat)
2218       {
2219         INSN_CODE (i2) = i2_code_number;
2220         PATTERN (i2) = newi2pat;
2221       }
2222     else
2223       {
2224         PUT_CODE (i2, NOTE);
2225         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2226         NOTE_SOURCE_FILE (i2) = 0;
2227       }
2228
2229     if (i1)
2230       {
2231         LOG_LINKS (i1) = 0;
2232         REG_NOTES (i1) = 0;
2233         PUT_CODE (i1, NOTE);
2234         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2235         NOTE_SOURCE_FILE (i1) = 0;
2236       }
2237
2238     /* Get death notes for everything that is now used in either I3 or
2239        I2 and used to die in a previous insn.  If we built two new
2240        patterns, move from I1 to I2 then I2 to I3 so that we get the
2241        proper movement on registers that I2 modifies.  */
2242
2243     if (newi2pat)
2244       {
2245         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2246         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2247       }
2248     else
2249       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2250                    i3, &midnotes);
2251
2252     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2253     if (i3notes)
2254       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2255                         elim_i2, elim_i1);
2256     if (i2notes)
2257       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2258                         elim_i2, elim_i1);
2259     if (i1notes)
2260       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2261                         elim_i2, elim_i1);
2262     if (midnotes)
2263       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2264                         elim_i2, elim_i1);
2265
2266     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2267        know these are REG_UNUSED and want them to go to the desired insn,
2268        so we always pass it as i3.  We have not counted the notes in
2269        reg_n_deaths yet, so we need to do so now.  */
2270
2271     if (newi2pat && new_i2_notes)
2272       {
2273         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2274           if (GET_CODE (XEXP (temp, 0)) == REG)
2275             reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2276
2277         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2278       }
2279
2280     if (new_i3_notes)
2281       {
2282         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2283           if (GET_CODE (XEXP (temp, 0)) == REG)
2284             reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2285
2286         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2287       }
2288
2289     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2290        put a REG_DEAD note for it somewhere.  Similarly for I2 and I1.
2291        Show an additional death due to the REG_DEAD note we make here.  If
2292        we discard it in distribute_notes, we will decrement it again.  */
2293
2294     if (i3dest_killed)
2295       {
2296         if (GET_CODE (i3dest_killed) == REG)
2297           reg_n_deaths[REGNO (i3dest_killed)]++;
2298
2299         distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2300                                    NULL_RTX),
2301                           NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2302                           NULL_RTX, NULL_RTX);
2303       }
2304
2305     /* For I2 and I1, we have to be careful.  If NEWI2PAT exists and sets
2306        I2DEST or I1DEST, the death must be somewhere before I2, not I3.  If
2307        we passed I3 in that case, it might delete I2.  */
2308
2309     if (i2dest_in_i2src)
2310       {
2311         if (GET_CODE (i2dest) == REG)
2312           reg_n_deaths[REGNO (i2dest)]++;
2313
2314         if (newi2pat && reg_set_p (i2dest, newi2pat))
2315           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2316                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2317         else
2318           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2319                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2320                             NULL_RTX, NULL_RTX);
2321       }
2322
2323     if (i1dest_in_i1src)
2324       {
2325         if (GET_CODE (i1dest) == REG)
2326           reg_n_deaths[REGNO (i1dest)]++;
2327
2328         if (newi2pat && reg_set_p (i1dest, newi2pat))
2329           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2330                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2331         else
2332           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2333                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2334                             NULL_RTX, NULL_RTX);
2335       }
2336
2337     distribute_links (i3links);
2338     distribute_links (i2links);
2339     distribute_links (i1links);
2340
2341     if (GET_CODE (i2dest) == REG)
2342       {
2343         rtx link;
2344         rtx i2_insn = 0, i2_val = 0, set;
2345
2346         /* The insn that used to set this register doesn't exist, and
2347            this life of the register may not exist either.  See if one of
2348            I3's links points to an insn that sets I2DEST.  If it does,
2349            that is now the last known value for I2DEST. If we don't update
2350            this and I2 set the register to a value that depended on its old
2351            contents, we will get confused.  If this insn is used, thing
2352            will be set correctly in combine_instructions.  */
2353
2354         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2355           if ((set = single_set (XEXP (link, 0))) != 0
2356               && rtx_equal_p (i2dest, SET_DEST (set)))
2357             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2358
2359         record_value_for_reg (i2dest, i2_insn, i2_val);
2360
2361         /* If the reg formerly set in I2 died only once and that was in I3,
2362            zero its use count so it won't make `reload' do any work.  */
2363         if (! added_sets_2
2364             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2365             && ! i2dest_in_i2src)
2366           {
2367             regno = REGNO (i2dest);
2368             reg_n_sets[regno]--;
2369             if (reg_n_sets[regno] == 0
2370                 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2371                       & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2372               reg_n_refs[regno] = 0;
2373           }
2374       }
2375
2376     if (i1 && GET_CODE (i1dest) == REG)
2377       {
2378         rtx link;
2379         rtx i1_insn = 0, i1_val = 0, set;
2380
2381         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2382           if ((set = single_set (XEXP (link, 0))) != 0
2383               && rtx_equal_p (i1dest, SET_DEST (set)))
2384             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2385
2386         record_value_for_reg (i1dest, i1_insn, i1_val);
2387
2388         regno = REGNO (i1dest);
2389         if (! added_sets_1 && ! i1dest_in_i1src)
2390           {
2391             reg_n_sets[regno]--;
2392             if (reg_n_sets[regno] == 0
2393                 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2394                       & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2395               reg_n_refs[regno] = 0;
2396           }
2397       }
2398
2399     /* Update reg_nonzero_bits et al for any changes that may have been made
2400        to this insn.  */
2401
2402     note_stores (newpat, set_nonzero_bits_and_sign_copies);
2403     if (newi2pat)
2404       note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2405
2406     /* If we added any (clobber (scratch)), add them to the max for a
2407        block.  This is a very pessimistic calculation, since we might
2408        have had them already and this might not be the worst block, but
2409        it's not worth doing any better.  */
2410     max_scratch += i3_scratches + i2_scratches + other_scratches;
2411
2412     /* If I3 is now an unconditional jump, ensure that it has a
2413        BARRIER following it since it may have initially been a
2414        conditional jump.  It may also be the last nonnote insn.  */
2415
2416     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2417         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2418             || GET_CODE (temp) != BARRIER))
2419       emit_barrier_after (i3);
2420   }
2421
2422   combine_successes++;
2423
2424   /* Clear this here, so that subsequent get_last_value calls are not
2425      affected.  */
2426   subst_prev_insn = NULL_RTX;
2427
2428   if (added_links_insn
2429       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2430       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2431     return added_links_insn;
2432   else
2433     return newi2pat ? i2 : i3;
2434 }
2435 \f
2436 /* Undo all the modifications recorded in undobuf.  */
2437
2438 static void
2439 undo_all ()
2440 {
2441   struct undo *undo, *next;
2442
2443   for (undo = undobuf.undos; undo; undo = next)
2444     {
2445       next = undo->next;
2446       if (undo->is_int)
2447         *undo->where.i = undo->old_contents.i;
2448       else
2449         *undo->where.r = undo->old_contents.r;
2450
2451       undo->next = undobuf.frees;
2452       undobuf.frees = undo;
2453     }
2454
2455   obfree (undobuf.storage);
2456   undobuf.undos = undobuf.previous_undos = 0;
2457
2458   /* Clear this here, so that subsequent get_last_value calls are not
2459      affected.  */
2460   subst_prev_insn = NULL_RTX;
2461 }
2462 \f
2463 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2464    where we have an arithmetic expression and return that point.  LOC will
2465    be inside INSN.
2466
2467    try_combine will call this function to see if an insn can be split into
2468    two insns.  */
2469
2470 static rtx *
2471 find_split_point (loc, insn)
2472      rtx *loc;
2473      rtx insn;
2474 {
2475   rtx x = *loc;
2476   enum rtx_code code = GET_CODE (x);
2477   rtx *split;
2478   int len = 0, pos, unsignedp;
2479   rtx inner;
2480
2481   /* First special-case some codes.  */
2482   switch (code)
2483     {
2484     case SUBREG:
2485 #ifdef INSN_SCHEDULING
2486       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2487          point.  */
2488       if (GET_CODE (SUBREG_REG (x)) == MEM)
2489         return loc;
2490 #endif
2491       return find_split_point (&SUBREG_REG (x), insn);
2492
2493     case MEM:
2494 #ifdef HAVE_lo_sum
2495       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2496          using LO_SUM and HIGH.  */
2497       if (GET_CODE (XEXP (x, 0)) == CONST
2498           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2499         {
2500           SUBST (XEXP (x, 0),
2501                  gen_rtx_combine (LO_SUM, Pmode,
2502                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2503                                   XEXP (x, 0)));
2504           return &XEXP (XEXP (x, 0), 0);
2505         }
2506 #endif
2507
2508       /* If we have a PLUS whose second operand is a constant and the
2509          address is not valid, perhaps will can split it up using
2510          the machine-specific way to split large constants.  We use
2511          the first pseudo-reg (one of the virtual regs) as a placeholder;
2512          it will not remain in the result.  */
2513       if (GET_CODE (XEXP (x, 0)) == PLUS
2514           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2515           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2516         {
2517           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2518           rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2519                                  subst_insn);
2520
2521           /* This should have produced two insns, each of which sets our
2522              placeholder.  If the source of the second is a valid address,
2523              we can make put both sources together and make a split point
2524              in the middle.  */
2525
2526           if (seq && XVECLEN (seq, 0) == 2
2527               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2528               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2529               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2530               && ! reg_mentioned_p (reg,
2531                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2532               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2533               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2534               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2535               && memory_address_p (GET_MODE (x),
2536                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2537             {
2538               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2539               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2540
2541               /* Replace the placeholder in SRC2 with SRC1.  If we can
2542                  find where in SRC2 it was placed, that can become our
2543                  split point and we can replace this address with SRC2.
2544                  Just try two obvious places.  */
2545
2546               src2 = replace_rtx (src2, reg, src1);
2547               split = 0;
2548               if (XEXP (src2, 0) == src1)
2549                 split = &XEXP (src2, 0);
2550               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2551                        && XEXP (XEXP (src2, 0), 0) == src1)
2552                 split = &XEXP (XEXP (src2, 0), 0);
2553
2554               if (split)
2555                 {
2556                   SUBST (XEXP (x, 0), src2);
2557                   return split;
2558                 }
2559             }
2560
2561           /* If that didn't work, perhaps the first operand is complex and
2562              needs to be computed separately, so make a split point there.
2563              This will occur on machines that just support REG + CONST
2564              and have a constant moved through some previous computation.  */
2565
2566           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2567                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2568                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2569                              == 'o')))
2570             return &XEXP (XEXP (x, 0), 0);
2571         }
2572       break;
2573
2574     case SET:
2575 #ifdef HAVE_cc0
2576       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2577          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2578          we need to put the operand into a register.  So split at that
2579          point.  */
2580
2581       if (SET_DEST (x) == cc0_rtx
2582           && GET_CODE (SET_SRC (x)) != COMPARE
2583           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2584           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2585           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2586                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2587         return &SET_SRC (x);
2588 #endif
2589
2590       /* See if we can split SET_SRC as it stands.  */
2591       split = find_split_point (&SET_SRC (x), insn);
2592       if (split && split != &SET_SRC (x))
2593         return split;
2594
2595       /* See if we can split SET_DEST as it stands.  */
2596       split = find_split_point (&SET_DEST (x), insn);
2597       if (split && split != &SET_DEST (x))
2598         return split;
2599
2600       /* See if this is a bitfield assignment with everything constant.  If
2601          so, this is an IOR of an AND, so split it into that.  */
2602       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2603           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2604               <= HOST_BITS_PER_WIDE_INT)
2605           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2606           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2607           && GET_CODE (SET_SRC (x)) == CONST_INT
2608           && ((INTVAL (XEXP (SET_DEST (x), 1))
2609               + INTVAL (XEXP (SET_DEST (x), 2)))
2610               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2611           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2612         {
2613           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2614           int len = INTVAL (XEXP (SET_DEST (x), 1));
2615           int src = INTVAL (SET_SRC (x));
2616           rtx dest = XEXP (SET_DEST (x), 0);
2617           enum machine_mode mode = GET_MODE (dest);
2618           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2619
2620           if (BITS_BIG_ENDIAN)
2621             pos = GET_MODE_BITSIZE (mode) - len - pos;
2622
2623           if (src == mask)
2624             SUBST (SET_SRC (x),
2625                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2626           else
2627             SUBST (SET_SRC (x),
2628                    gen_binary (IOR, mode,
2629                                gen_binary (AND, mode, dest,
2630                                            GEN_INT (~ (mask << pos)
2631                                                     & GET_MODE_MASK (mode))),
2632                                GEN_INT (src << pos)));
2633
2634           SUBST (SET_DEST (x), dest);
2635
2636           split = find_split_point (&SET_SRC (x), insn);
2637           if (split && split != &SET_SRC (x))
2638             return split;
2639         }
2640
2641       /* Otherwise, see if this is an operation that we can split into two.
2642          If so, try to split that.  */
2643       code = GET_CODE (SET_SRC (x));
2644
2645       switch (code)
2646         {
2647         case AND:
2648           /* If we are AND'ing with a large constant that is only a single
2649              bit and the result is only being used in a context where we
2650              need to know if it is zero or non-zero, replace it with a bit
2651              extraction.  This will avoid the large constant, which might
2652              have taken more than one insn to make.  If the constant were
2653              not a valid argument to the AND but took only one insn to make,
2654              this is no worse, but if it took more than one insn, it will
2655              be better.  */
2656
2657           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2658               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2659               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2660               && GET_CODE (SET_DEST (x)) == REG
2661               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2662               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2663               && XEXP (*split, 0) == SET_DEST (x)
2664               && XEXP (*split, 1) == const0_rtx)
2665             {
2666               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2667                                                 XEXP (SET_SRC (x), 0),
2668                                                 pos, NULL_RTX, 1, 1, 0, 0);
2669               if (extraction != 0)
2670                 {
2671                   SUBST (SET_SRC (x), extraction);
2672                   return find_split_point (loc, insn);
2673                 }
2674             }
2675           break;
2676
2677         case NE:
2678           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2679              is known to be on, this can be converted into a NEG of a shift. */
2680           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2681               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2682               && 1 <= (pos = exact_log2
2683                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2684                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2685             {
2686               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2687
2688               SUBST (SET_SRC (x),
2689                      gen_rtx_combine (NEG, mode,
2690                                       gen_rtx_combine (LSHIFTRT, mode,
2691                                                        XEXP (SET_SRC (x), 0),
2692                                                        GEN_INT (pos))));
2693
2694               split = find_split_point (&SET_SRC (x), insn);
2695               if (split && split != &SET_SRC (x))
2696                 return split;
2697             }
2698           break;
2699
2700         case SIGN_EXTEND:
2701           inner = XEXP (SET_SRC (x), 0);
2702
2703           /* We can't optimize if either mode is a partial integer
2704              mode as we don't know how many bits are significant
2705              in those modes.  */
2706           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2707               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2708             break;
2709
2710           pos = 0;
2711           len = GET_MODE_BITSIZE (GET_MODE (inner));
2712           unsignedp = 0;
2713           break;
2714
2715         case SIGN_EXTRACT:
2716         case ZERO_EXTRACT:
2717           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2718               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2719             {
2720               inner = XEXP (SET_SRC (x), 0);
2721               len = INTVAL (XEXP (SET_SRC (x), 1));
2722               pos = INTVAL (XEXP (SET_SRC (x), 2));
2723
2724               if (BITS_BIG_ENDIAN)
2725                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2726               unsignedp = (code == ZERO_EXTRACT);
2727             }
2728           break;
2729         }
2730
2731       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2732         {
2733           enum machine_mode mode = GET_MODE (SET_SRC (x));
2734
2735           /* For unsigned, we have a choice of a shift followed by an
2736              AND or two shifts.  Use two shifts for field sizes where the
2737              constant might be too large.  We assume here that we can
2738              always at least get 8-bit constants in an AND insn, which is
2739              true for every current RISC.  */
2740
2741           if (unsignedp && len <= 8)
2742             {
2743               SUBST (SET_SRC (x),
2744                      gen_rtx_combine
2745                      (AND, mode,
2746                       gen_rtx_combine (LSHIFTRT, mode,
2747                                        gen_lowpart_for_combine (mode, inner),
2748                                        GEN_INT (pos)),
2749                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2750
2751               split = find_split_point (&SET_SRC (x), insn);
2752               if (split && split != &SET_SRC (x))
2753                 return split;
2754             }
2755           else
2756             {
2757               SUBST (SET_SRC (x),
2758                      gen_rtx_combine
2759                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2760                       gen_rtx_combine (ASHIFT, mode,
2761                                        gen_lowpart_for_combine (mode, inner),
2762                                        GEN_INT (GET_MODE_BITSIZE (mode)
2763                                                 - len - pos)),
2764                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2765
2766               split = find_split_point (&SET_SRC (x), insn);
2767               if (split && split != &SET_SRC (x))
2768                 return split;
2769             }
2770         }
2771
2772       /* See if this is a simple operation with a constant as the second
2773          operand.  It might be that this constant is out of range and hence
2774          could be used as a split point.  */
2775       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2776            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2777            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2778           && CONSTANT_P (XEXP (SET_SRC (x), 1))
2779           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2780               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2781                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2782                       == 'o'))))
2783         return &XEXP (SET_SRC (x), 1);
2784
2785       /* Finally, see if this is a simple operation with its first operand
2786          not in a register.  The operation might require this operand in a
2787          register, so return it as a split point.  We can always do this
2788          because if the first operand were another operation, we would have
2789          already found it as a split point.  */
2790       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2791            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2792            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2793            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2794           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2795         return &XEXP (SET_SRC (x), 0);
2796
2797       return 0;
2798
2799     case AND:
2800     case IOR:
2801       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2802          it is better to write this as (not (ior A B)) so we can split it.
2803          Similarly for IOR.  */
2804       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2805         {
2806           SUBST (*loc,
2807                  gen_rtx_combine (NOT, GET_MODE (x),
2808                                   gen_rtx_combine (code == IOR ? AND : IOR,
2809                                                    GET_MODE (x),
2810                                                    XEXP (XEXP (x, 0), 0),
2811                                                    XEXP (XEXP (x, 1), 0))));
2812           return find_split_point (loc, insn);
2813         }
2814
2815       /* Many RISC machines have a large set of logical insns.  If the
2816          second operand is a NOT, put it first so we will try to split the
2817          other operand first.  */
2818       if (GET_CODE (XEXP (x, 1)) == NOT)
2819         {
2820           rtx tem = XEXP (x, 0);
2821           SUBST (XEXP (x, 0), XEXP (x, 1));
2822           SUBST (XEXP (x, 1), tem);
2823         }
2824       break;
2825     }
2826
2827   /* Otherwise, select our actions depending on our rtx class.  */
2828   switch (GET_RTX_CLASS (code))
2829     {
2830     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
2831     case '3':
2832       split = find_split_point (&XEXP (x, 2), insn);
2833       if (split)
2834         return split;
2835       /* ... fall through ...  */
2836     case '2':
2837     case 'c':
2838     case '<':
2839       split = find_split_point (&XEXP (x, 1), insn);
2840       if (split)
2841         return split;
2842       /* ... fall through ...  */
2843     case '1':
2844       /* Some machines have (and (shift ...) ...) insns.  If X is not
2845          an AND, but XEXP (X, 0) is, use it as our split point.  */
2846       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2847         return &XEXP (x, 0);
2848
2849       split = find_split_point (&XEXP (x, 0), insn);
2850       if (split)
2851         return split;
2852       return loc;
2853     }
2854
2855   /* Otherwise, we don't have a split point.  */
2856   return 0;
2857 }
2858 \f
2859 /* Throughout X, replace FROM with TO, and return the result.
2860    The result is TO if X is FROM;
2861    otherwise the result is X, but its contents may have been modified.
2862    If they were modified, a record was made in undobuf so that
2863    undo_all will (among other things) return X to its original state.
2864
2865    If the number of changes necessary is too much to record to undo,
2866    the excess changes are not made, so the result is invalid.
2867    The changes already made can still be undone.
2868    undobuf.num_undo is incremented for such changes, so by testing that
2869    the caller can tell whether the result is valid.
2870
2871    `n_occurrences' is incremented each time FROM is replaced.
2872
2873    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2874
2875    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
2876    by copying if `n_occurrences' is non-zero.  */
2877
2878 static rtx
2879 subst (x, from, to, in_dest, unique_copy)
2880      register rtx x, from, to;
2881      int in_dest;
2882      int unique_copy;
2883 {
2884   register enum rtx_code code = GET_CODE (x);
2885   enum machine_mode op0_mode = VOIDmode;
2886   register char *fmt;
2887   register int len, i;
2888   rtx new;
2889
2890 /* Two expressions are equal if they are identical copies of a shared
2891    RTX or if they are both registers with the same register number
2892    and mode.  */
2893
2894 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
2895   ((X) == (Y)                                           \
2896    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
2897        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2898
2899   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2900     {
2901       n_occurrences++;
2902       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2903     }
2904
2905   /* If X and FROM are the same register but different modes, they will
2906      not have been seen as equal above.  However, flow.c will make a
2907      LOG_LINKS entry for that case.  If we do nothing, we will try to
2908      rerecognize our original insn and, when it succeeds, we will
2909      delete the feeding insn, which is incorrect.
2910
2911      So force this insn not to match in this (rare) case.  */
2912   if (! in_dest && code == REG && GET_CODE (from) == REG
2913       && REGNO (x) == REGNO (from))
2914     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2915
2916   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2917      of which may contain things that can be combined.  */
2918   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2919     return x;
2920
2921   /* It is possible to have a subexpression appear twice in the insn.
2922      Suppose that FROM is a register that appears within TO.
2923      Then, after that subexpression has been scanned once by `subst',
2924      the second time it is scanned, TO may be found.  If we were
2925      to scan TO here, we would find FROM within it and create a
2926      self-referent rtl structure which is completely wrong.  */
2927   if (COMBINE_RTX_EQUAL_P (x, to))
2928     return to;
2929
2930   len = GET_RTX_LENGTH (code);
2931   fmt = GET_RTX_FORMAT (code);
2932
2933   /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2934      set up to skip this common case.  All other cases where we want to
2935      suppress replacing something inside a SET_SRC are handled via the
2936      IN_DEST operand.  */
2937   if (code == SET
2938       && (GET_CODE (SET_DEST (x)) == REG
2939         || GET_CODE (SET_DEST (x)) == CC0
2940         || GET_CODE (SET_DEST (x)) == PC))
2941     fmt = "ie";
2942
2943   /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2944      constant.  */
2945   if (fmt[0] == 'e')
2946     op0_mode = GET_MODE (XEXP (x, 0));
2947
2948   for (i = 0; i < len; i++)
2949     {
2950       if (fmt[i] == 'E')
2951         {
2952           register int j;
2953           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2954             {
2955               if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2956                 {
2957                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2958                   n_occurrences++;
2959                 }
2960               else
2961                 {
2962                   new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2963
2964                   /* If this substitution failed, this whole thing fails.  */
2965                   if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2966                     return new;
2967                 }
2968
2969               SUBST (XVECEXP (x, i, j), new);
2970             }
2971         }
2972       else if (fmt[i] == 'e')
2973         {
2974           if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2975             {
2976               /* In general, don't install a subreg involving two modes not
2977                  tieable.  It can worsen register allocation, and can even
2978                  make invalid reload insns, since the reg inside may need to
2979                  be copied from in the outside mode, and that may be invalid
2980                  if it is an fp reg copied in integer mode.
2981
2982                  We allow two exceptions to this: It is valid if it is inside
2983                  another SUBREG and the mode of that SUBREG and the mode of
2984                  the inside of TO is tieable and it is valid if X is a SET
2985                  that copies FROM to CC0.  */
2986               if (GET_CODE (to) == SUBREG
2987                   && ! MODES_TIEABLE_P (GET_MODE (to),
2988                                         GET_MODE (SUBREG_REG (to)))
2989                   && ! (code == SUBREG
2990                         && MODES_TIEABLE_P (GET_MODE (x),
2991                                             GET_MODE (SUBREG_REG (to))))
2992 #ifdef HAVE_cc0
2993                   && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2994 #endif
2995                   )
2996                 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2997
2998               new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2999               n_occurrences++;
3000             }
3001           else
3002             /* If we are in a SET_DEST, suppress most cases unless we
3003                have gone inside a MEM, in which case we want to
3004                simplify the address.  We assume here that things that
3005                are actually part of the destination have their inner
3006                parts in the first expression.  This is true for SUBREG,
3007                STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3008                things aside from REG and MEM that should appear in a
3009                SET_DEST.  */
3010             new = subst (XEXP (x, i), from, to,
3011                          (((in_dest
3012                             && (code == SUBREG || code == STRICT_LOW_PART
3013                                 || code == ZERO_EXTRACT))
3014                            || code == SET)
3015                           && i == 0), unique_copy);
3016
3017           /* If we found that we will have to reject this combination,
3018              indicate that by returning the CLOBBER ourselves, rather than
3019              an expression containing it.  This will speed things up as
3020              well as prevent accidents where two CLOBBERs are considered
3021              to be equal, thus producing an incorrect simplification.  */
3022
3023           if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3024             return new;
3025
3026           SUBST (XEXP (x, i), new);
3027         }
3028     }
3029
3030   /* Try to simplify X.  If the simplification changed the code, it is likely
3031      that further simplification will help, so loop, but limit the number
3032      of repetitions that will be performed.  */
3033
3034   for (i = 0; i < 4; i++)
3035     {
3036       /* If X is sufficiently simple, don't bother trying to do anything
3037          with it.  */
3038       if (code != CONST_INT && code != REG && code != CLOBBER)
3039         x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3040
3041       if (GET_CODE (x) == code)
3042         break;
3043
3044       code = GET_CODE (x);
3045
3046       /* We no longer know the original mode of operand 0 since we
3047          have changed the form of X)  */
3048       op0_mode = VOIDmode;
3049     }
3050
3051   return x;
3052 }
3053 \f
3054 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3055    outer level; call `subst' to simplify recursively.  Return the new
3056    expression.
3057
3058    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3059    will be the iteration even if an expression with a code different from
3060    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3061
3062 static rtx
3063 simplify_rtx (x, op0_mode, last, in_dest)
3064      rtx x;
3065      enum machine_mode op0_mode;
3066      int last;
3067      int in_dest;
3068 {
3069   enum rtx_code code = GET_CODE (x);
3070   enum machine_mode mode = GET_MODE (x);
3071   rtx temp;
3072   int i;
3073
3074   /* If this is a commutative operation, put a constant last and a complex
3075      expression first.  We don't need to do this for comparisons here.  */
3076   if (GET_RTX_CLASS (code) == 'c'
3077       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3078           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3079               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3080           || (GET_CODE (XEXP (x, 0)) == SUBREG
3081               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3082               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3083     {
3084       temp = XEXP (x, 0);
3085       SUBST (XEXP (x, 0), XEXP (x, 1));
3086       SUBST (XEXP (x, 1), temp);
3087     }
3088
3089   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3090      sign extension of a PLUS with a constant, reverse the order of the sign
3091      extension and the addition. Note that this not the same as the original
3092      code, but overflow is undefined for signed values.  Also note that the
3093      PLUS will have been partially moved "inside" the sign-extension, so that
3094      the first operand of X will really look like:
3095          (ashiftrt (plus (ashift A C4) C5) C4).
3096      We convert this to
3097          (plus (ashiftrt (ashift A C4) C2) C4)
3098      and replace the first operand of X with that expression.  Later parts
3099      of this function may simplify the expression further.
3100
3101      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3102      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3103      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3104
3105      We do this to simplify address expressions.  */
3106
3107   if ((code == PLUS || code == MINUS || code == MULT)
3108       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3109       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3110       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3111       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3112       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3113       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3114       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3115       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3116                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3117                                             XEXP (XEXP (x, 0), 1))) != 0)
3118     {
3119       rtx new
3120         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3121                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3122                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3123
3124       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3125                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3126
3127       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3128     }
3129
3130   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3131      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3132      things.  Check for cases where both arms are testing the same
3133      condition.
3134
3135      Don't do anything if all operands are very simple.  */
3136
3137   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3138         || GET_RTX_CLASS (code) == '<')
3139        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3140             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3141                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3142                       == 'o')))
3143            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3144                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3145                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3146                          == 'o')))))
3147       || (GET_RTX_CLASS (code) == '1'
3148           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3149                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3150                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3151                          == 'o'))))))
3152     {
3153       rtx cond, true, false;
3154
3155       cond = if_then_else_cond (x, &true, &false);
3156       if (cond != 0
3157           /* If everything is a comparison, what we have is highly unlikely
3158              to be simpler, so don't use it.  */
3159           && ! (GET_RTX_CLASS (code) == '<'
3160                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3161                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3162         {
3163           rtx cop1 = const0_rtx;
3164           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3165
3166           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3167             return x;
3168
3169           /* Simplify the alternative arms; this may collapse the true and
3170              false arms to store-flag values.  */
3171           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3172           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3173
3174           /* Restarting if we generate a store-flag expression will cause
3175              us to loop.  Just drop through in this case.  */
3176
3177           /* If the result values are STORE_FLAG_VALUE and zero, we can
3178              just make the comparison operation.  */
3179           if (true == const_true_rtx && false == const0_rtx)
3180             x = gen_binary (cond_code, mode, cond, cop1);
3181           else if (true == const0_rtx && false == const_true_rtx)
3182             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3183
3184           /* Likewise, we can make the negate of a comparison operation
3185              if the result values are - STORE_FLAG_VALUE and zero.  */
3186           else if (GET_CODE (true) == CONST_INT
3187                    && INTVAL (true) == - STORE_FLAG_VALUE
3188                    && false == const0_rtx)
3189             x = gen_unary (NEG, mode, mode,
3190                            gen_binary (cond_code, mode, cond, cop1));
3191           else if (GET_CODE (false) == CONST_INT
3192                    && INTVAL (false) == - STORE_FLAG_VALUE
3193                    && true == const0_rtx)
3194             x = gen_unary (NEG, mode, mode,
3195                            gen_binary (reverse_condition (cond_code),
3196                                        mode, cond, cop1));
3197           else
3198             return gen_rtx (IF_THEN_ELSE, mode,
3199                             gen_binary (cond_code, VOIDmode, cond, cop1),
3200                             true, false);
3201
3202           code = GET_CODE (x);
3203           op0_mode = VOIDmode;
3204         }
3205     }
3206
3207   /* Try to fold this expression in case we have constants that weren't
3208      present before.  */
3209   temp = 0;
3210   switch (GET_RTX_CLASS (code))
3211     {
3212     case '1':
3213       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3214       break;
3215     case '<':
3216       temp = simplify_relational_operation (code, op0_mode,
3217                                             XEXP (x, 0), XEXP (x, 1));
3218 #ifdef FLOAT_STORE_FLAG_VALUE
3219       if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3220         temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3221                 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3222 #endif
3223       break;
3224     case 'c':
3225     case '2':
3226       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3227       break;
3228     case 'b':
3229     case '3':
3230       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3231                                          XEXP (x, 1), XEXP (x, 2));
3232       break;
3233     }
3234
3235   if (temp)
3236     x = temp, code = GET_CODE (temp);
3237
3238   /* First see if we can apply the inverse distributive law.  */
3239   if (code == PLUS || code == MINUS
3240       || code == AND || code == IOR || code == XOR)
3241     {
3242       x = apply_distributive_law (x);
3243       code = GET_CODE (x);
3244     }
3245
3246   /* If CODE is an associative operation not otherwise handled, see if we
3247      can associate some operands.  This can win if they are constants or
3248      if they are logically related (i.e. (a & b) & a.  */
3249   if ((code == PLUS || code == MINUS
3250        || code == MULT || code == AND || code == IOR || code == XOR
3251        || code == DIV || code == UDIV
3252        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3253       && INTEGRAL_MODE_P (mode))
3254     {
3255       if (GET_CODE (XEXP (x, 0)) == code)
3256         {
3257           rtx other = XEXP (XEXP (x, 0), 0);
3258           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3259           rtx inner_op1 = XEXP (x, 1);
3260           rtx inner;
3261
3262           /* Make sure we pass the constant operand if any as the second
3263              one if this is a commutative operation.  */
3264           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3265             {
3266               rtx tem = inner_op0;
3267               inner_op0 = inner_op1;
3268               inner_op1 = tem;
3269             }
3270           inner = simplify_binary_operation (code == MINUS ? PLUS
3271                                              : code == DIV ? MULT
3272                                              : code == UDIV ? MULT
3273                                              : code,
3274                                              mode, inner_op0, inner_op1);
3275
3276           /* For commutative operations, try the other pair if that one
3277              didn't simplify.  */
3278           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3279             {
3280               other = XEXP (XEXP (x, 0), 1);
3281               inner = simplify_binary_operation (code, mode,
3282                                                  XEXP (XEXP (x, 0), 0),
3283                                                  XEXP (x, 1));
3284             }
3285
3286           if (inner)
3287             return gen_binary (code, mode, other, inner);
3288         }
3289     }
3290
3291   /* A little bit of algebraic simplification here.  */
3292   switch (code)
3293     {
3294     case MEM:
3295       /* Ensure that our address has any ASHIFTs converted to MULT in case
3296          address-recognizing predicates are called later.  */
3297       temp = make_compound_operation (XEXP (x, 0), MEM);
3298       SUBST (XEXP (x, 0), temp);
3299       break;
3300
3301     case SUBREG:
3302       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3303          is paradoxical.  If we can't do that safely, then it becomes
3304          something nonsensical so that this combination won't take place.  */
3305
3306       if (GET_CODE (SUBREG_REG (x)) == MEM
3307           && (GET_MODE_SIZE (mode)
3308               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3309         {
3310           rtx inner = SUBREG_REG (x);
3311           int endian_offset = 0;
3312           /* Don't change the mode of the MEM
3313              if that would change the meaning of the address.  */
3314           if (MEM_VOLATILE_P (SUBREG_REG (x))
3315               || mode_dependent_address_p (XEXP (inner, 0)))
3316             return gen_rtx (CLOBBER, mode, const0_rtx);
3317
3318           if (BYTES_BIG_ENDIAN)
3319             {
3320               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3321                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3322               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3323                 endian_offset -= (UNITS_PER_WORD
3324                                   - GET_MODE_SIZE (GET_MODE (inner)));
3325             }
3326           /* Note if the plus_constant doesn't make a valid address
3327              then this combination won't be accepted.  */
3328           x = gen_rtx (MEM, mode,
3329                        plus_constant (XEXP (inner, 0),
3330                                       (SUBREG_WORD (x) * UNITS_PER_WORD
3331                                        + endian_offset)));
3332           MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3333           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3334           MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3335           return x;
3336         }
3337
3338       /* If we are in a SET_DEST, these other cases can't apply.  */
3339       if (in_dest)
3340         return x;
3341
3342       /* Changing mode twice with SUBREG => just change it once,
3343          or not at all if changing back to starting mode.  */
3344       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3345         {
3346           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3347               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3348             return SUBREG_REG (SUBREG_REG (x));
3349
3350           SUBST_INT (SUBREG_WORD (x),
3351                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3352           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3353         }
3354
3355       /* SUBREG of a hard register => just change the register number
3356          and/or mode.  If the hard register is not valid in that mode,
3357          suppress this combination.  If the hard register is the stack,
3358          frame, or argument pointer, leave this as a SUBREG.  */
3359
3360       if (GET_CODE (SUBREG_REG (x)) == REG
3361           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3362           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3363 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3364           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3365 #endif
3366 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3367           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3368 #endif
3369           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3370         {
3371           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3372                                   mode))
3373             return gen_rtx (REG, mode,
3374                             REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3375           else
3376             return gen_rtx (CLOBBER, mode, const0_rtx);
3377         }
3378
3379       /* For a constant, try to pick up the part we want.  Handle a full
3380          word and low-order part.  Only do this if we are narrowing
3381          the constant; if it is being widened, we have no idea what
3382          the extra bits will have been set to.  */
3383
3384       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3385           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3386           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3387           && GET_MODE_CLASS (mode) == MODE_INT)
3388         {
3389           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3390                                   0, op0_mode);
3391           if (temp)
3392             return temp;
3393         }
3394
3395       /* If we want a subreg of a constant, at offset 0,
3396          take the low bits.  On a little-endian machine, that's
3397          always valid.  On a big-endian machine, it's valid
3398          only if the constant's mode fits in one word.   Note that we
3399          cannot use subreg_lowpart_p since we SUBREG_REG may be VOIDmode.  */
3400       if (CONSTANT_P (SUBREG_REG (x))
3401           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3402               || ! WORDS_BIG_ENDIAN)
3403               ? SUBREG_WORD (x) == 0
3404               : (SUBREG_WORD (x)
3405                  == ((GET_MODE_SIZE (op0_mode)
3406                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3407                      / UNITS_PER_WORD)))
3408           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3409           && (! WORDS_BIG_ENDIAN
3410               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3411         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3412
3413       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3414          since we are saying that the high bits don't matter.  */
3415       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3416           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3417         return SUBREG_REG (x);
3418
3419       /* Note that we cannot do any narrowing for non-constants since
3420          we might have been counting on using the fact that some bits were
3421          zero.  We now do this in the SET.  */
3422
3423       break;
3424
3425     case NOT:
3426       /* (not (plus X -1)) can become (neg X).  */
3427       if (GET_CODE (XEXP (x, 0)) == PLUS
3428           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3429         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3430
3431       /* Similarly, (not (neg X)) is (plus X -1).  */
3432       if (GET_CODE (XEXP (x, 0)) == NEG)
3433         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3434                                 constm1_rtx);
3435
3436       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3437       if (GET_CODE (XEXP (x, 0)) == XOR
3438           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3439           && (temp = simplify_unary_operation (NOT, mode,
3440                                                XEXP (XEXP (x, 0), 1),
3441                                                mode)) != 0)
3442         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3443
3444       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3445          other than 1, but that is not valid.  We could do a similar
3446          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3447          but this doesn't seem common enough to bother with.  */
3448       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3449           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3450         return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3451                         XEXP (XEXP (x, 0), 1));
3452
3453       if (GET_CODE (XEXP (x, 0)) == SUBREG
3454           && subreg_lowpart_p (XEXP (x, 0))
3455           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3456               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3457           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3458           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3459         {
3460           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3461
3462           x = gen_rtx (ROTATE, inner_mode,
3463                        gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3464                        XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3465           return gen_lowpart_for_combine (mode, x);
3466         }
3467
3468       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3469          reversing the comparison code if valid.  */
3470       if (STORE_FLAG_VALUE == -1
3471           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3472           && reversible_comparison_p (XEXP (x, 0)))
3473         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3474                                 mode, XEXP (XEXP (x, 0), 0),
3475                                 XEXP (XEXP (x, 0), 1));
3476
3477       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3478          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3479          perform the above simplification.  */
3480
3481       if (STORE_FLAG_VALUE == -1
3482           && XEXP (x, 1) == const1_rtx
3483           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3484           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3485           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3486         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3487
3488       /* Apply De Morgan's laws to reduce number of patterns for machines
3489          with negating logical insns (and-not, nand, etc.).  If result has
3490          only one NOT, put it first, since that is how the patterns are
3491          coded.  */
3492
3493       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3494         {
3495          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3496
3497          if (GET_CODE (in1) == NOT)
3498            in1 = XEXP (in1, 0);
3499          else
3500            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3501
3502          if (GET_CODE (in2) == NOT)
3503            in2 = XEXP (in2, 0);
3504          else if (GET_CODE (in2) == CONST_INT
3505                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3506            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3507          else
3508            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3509
3510          if (GET_CODE (in2) == NOT)
3511            {
3512              rtx tem = in2;
3513              in2 = in1; in1 = tem;
3514            }
3515
3516          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3517                                  mode, in1, in2);
3518        }
3519       break;
3520
3521     case NEG:
3522       /* (neg (plus X 1)) can become (not X).  */
3523       if (GET_CODE (XEXP (x, 0)) == PLUS
3524           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3525         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3526
3527       /* Similarly, (neg (not X)) is (plus X 1).  */
3528       if (GET_CODE (XEXP (x, 0)) == NOT)
3529         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3530
3531       /* (neg (minus X Y)) can become (minus Y X).  */
3532       if (GET_CODE (XEXP (x, 0)) == MINUS
3533           && (! FLOAT_MODE_P (mode)
3534               /* x-y != -(y-x) with IEEE floating point.  */
3535               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3536               || flag_fast_math))
3537         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3538                            XEXP (XEXP (x, 0), 0));
3539
3540       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3541       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3542           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3543         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3544
3545       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3546          if we can then eliminate the NEG (e.g.,
3547          if the operand is a constant).  */
3548
3549       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3550         {
3551           temp = simplify_unary_operation (NEG, mode,
3552                                            XEXP (XEXP (x, 0), 0), mode);
3553           if (temp)
3554             {
3555               SUBST (XEXP (XEXP (x, 0), 0), temp);
3556               return XEXP (x, 0);
3557             }
3558         }
3559
3560       temp = expand_compound_operation (XEXP (x, 0));
3561
3562       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3563          replaced by (lshiftrt X C).  This will convert
3564          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3565
3566       if (GET_CODE (temp) == ASHIFTRT
3567           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3568           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3569         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3570                                      INTVAL (XEXP (temp, 1)));
3571
3572       /* If X has only a single bit that might be nonzero, say, bit I, convert
3573          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3574          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3575          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3576          or a SUBREG of one since we'd be making the expression more
3577          complex if it was just a register.  */
3578
3579       if (GET_CODE (temp) != REG
3580           && ! (GET_CODE (temp) == SUBREG
3581                 && GET_CODE (SUBREG_REG (temp)) == REG)
3582           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3583         {
3584           rtx temp1 = simplify_shift_const
3585             (NULL_RTX, ASHIFTRT, mode,
3586              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3587                                    GET_MODE_BITSIZE (mode) - 1 - i),
3588              GET_MODE_BITSIZE (mode) - 1 - i);
3589
3590           /* If all we did was surround TEMP with the two shifts, we
3591              haven't improved anything, so don't use it.  Otherwise,
3592              we are better off with TEMP1.  */
3593           if (GET_CODE (temp1) != ASHIFTRT
3594               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3595               || XEXP (XEXP (temp1, 0), 0) != temp)
3596             return temp1;
3597         }
3598       break;
3599
3600     case TRUNCATE:
3601       /* We can't handle truncation to a partial integer mode here
3602          because we don't know the real bitsize of the partial
3603          integer mode.  */
3604       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3605         break;
3606
3607       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3608         SUBST (XEXP (x, 0),
3609                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3610                               GET_MODE_MASK (mode), NULL_RTX, 0));
3611
3612       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3613       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3614            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3615           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3616         return XEXP (XEXP (x, 0), 0);
3617
3618       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3619          (OP:SI foo:SI) if OP is NEG or ABS.  */
3620       if ((GET_CODE (XEXP (x, 0)) == ABS
3621            || GET_CODE (XEXP (x, 0)) == NEG)
3622           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3623               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3624           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3625         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3626                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3627
3628       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3629          (truncate:SI x).  */
3630       if (GET_CODE (XEXP (x, 0)) == SUBREG
3631           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3632           && subreg_lowpart_p (XEXP (x, 0)))
3633         return SUBREG_REG (XEXP (x, 0));
3634
3635       /* If we know that the value is already truncated, we can
3636          replace the TRUNCATE with a SUBREG.  */
3637       if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3638           && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3639               &~ GET_MODE_MASK (mode)) == 0)
3640         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3641
3642       /* A truncate of a comparison can be replaced with a subreg if
3643          STORE_FLAG_VALUE permits.  This is like the previous test,
3644          but it works even if the comparison is done in a mode larger
3645          than HOST_BITS_PER_WIDE_INT.  */
3646       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3647           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3648           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3649         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3650
3651       /* Similarly, a truncate of a register whose value is a
3652          comparison can be replaced with a subreg if STORE_FLAG_VALUE
3653          permits.  */
3654       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3655           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3656           && (temp = get_last_value (XEXP (x, 0)))
3657           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3658         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3659
3660       break;
3661
3662     case FLOAT_TRUNCATE:
3663       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
3664       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3665           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3666         return XEXP (XEXP (x, 0), 0);
3667
3668       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3669          (OP:SF foo:SF) if OP is NEG or ABS.  */
3670       if ((GET_CODE (XEXP (x, 0)) == ABS
3671            || GET_CODE (XEXP (x, 0)) == NEG)
3672           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3673           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3674         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3675                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3676
3677       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3678          is (float_truncate:SF x).  */
3679       if (GET_CODE (XEXP (x, 0)) == SUBREG
3680           && subreg_lowpart_p (XEXP (x, 0))
3681           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3682         return SUBREG_REG (XEXP (x, 0));
3683       break;
3684
3685 #ifdef HAVE_cc0
3686     case COMPARE:
3687       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3688          using cc0, in which case we want to leave it as a COMPARE
3689          so we can distinguish it from a register-register-copy.  */
3690       if (XEXP (x, 1) == const0_rtx)
3691         return XEXP (x, 0);
3692
3693       /* In IEEE floating point, x-0 is not the same as x.  */
3694       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3695            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3696            || flag_fast_math)
3697           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3698         return XEXP (x, 0);
3699       break;
3700 #endif
3701
3702     case CONST:
3703       /* (const (const X)) can become (const X).  Do it this way rather than
3704          returning the inner CONST since CONST can be shared with a
3705          REG_EQUAL note.  */
3706       if (GET_CODE (XEXP (x, 0)) == CONST)
3707         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3708       break;
3709
3710 #ifdef HAVE_lo_sum
3711     case LO_SUM:
3712       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
3713          can add in an offset.  find_split_point will split this address up
3714          again if it doesn't match.  */
3715       if (GET_CODE (XEXP (x, 0)) == HIGH
3716           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3717         return XEXP (x, 1);
3718       break;
3719 #endif
3720
3721     case PLUS:
3722       /* If we have (plus (plus (A const) B)), associate it so that CONST is
3723          outermost.  That's because that's the way indexed addresses are
3724          supposed to appear.  This code used to check many more cases, but
3725          they are now checked elsewhere.  */
3726       if (GET_CODE (XEXP (x, 0)) == PLUS
3727           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3728         return gen_binary (PLUS, mode,
3729                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3730                                        XEXP (x, 1)),
3731                            XEXP (XEXP (x, 0), 1));
3732
3733       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3734          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3735          bit-field and can be replaced by either a sign_extend or a
3736          sign_extract.  The `and' may be a zero_extend.  */
3737       if (GET_CODE (XEXP (x, 0)) == XOR
3738           && GET_CODE (XEXP (x, 1)) == CONST_INT
3739           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3740           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3741           && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3742           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3743           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3744                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3745                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3746                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3747               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3748                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3749                       == i + 1))))
3750         return simplify_shift_const
3751           (NULL_RTX, ASHIFTRT, mode,
3752            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3753                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
3754                                  GET_MODE_BITSIZE (mode) - (i + 1)),
3755            GET_MODE_BITSIZE (mode) - (i + 1));
3756
3757       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3758          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3759          is 1.  This produces better code than the alternative immediately
3760          below.  */
3761       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3762           && reversible_comparison_p (XEXP (x, 0))
3763           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3764               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3765         return
3766           gen_unary (NEG, mode, mode,
3767                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3768                                  mode, XEXP (XEXP (x, 0), 0),
3769                                  XEXP (XEXP (x, 0), 1)));
3770
3771       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3772          can become (ashiftrt (ashift (xor x 1) C) C) where C is
3773          the bitsize of the mode - 1.  This allows simplification of
3774          "a = (b & 8) == 0;"  */
3775       if (XEXP (x, 1) == constm1_rtx
3776           && GET_CODE (XEXP (x, 0)) != REG
3777           && ! (GET_CODE (XEXP (x,0)) == SUBREG
3778                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3779           && nonzero_bits (XEXP (x, 0), mode) == 1)
3780         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3781            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3782                                  gen_rtx_combine (XOR, mode,
3783                                                   XEXP (x, 0), const1_rtx),
3784                                  GET_MODE_BITSIZE (mode) - 1),
3785            GET_MODE_BITSIZE (mode) - 1);
3786
3787       /* If we are adding two things that have no bits in common, convert
3788          the addition into an IOR.  This will often be further simplified,
3789          for example in cases like ((a & 1) + (a & 2)), which can
3790          become a & 3.  */
3791
3792       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3793           && (nonzero_bits (XEXP (x, 0), mode)
3794               & nonzero_bits (XEXP (x, 1), mode)) == 0)
3795         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3796       break;
3797
3798     case MINUS:
3799       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3800          by reversing the comparison code if valid.  */
3801       if (STORE_FLAG_VALUE == 1
3802           && XEXP (x, 0) == const1_rtx
3803           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3804           && reversible_comparison_p (XEXP (x, 1)))
3805         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3806                            mode, XEXP (XEXP (x, 1), 0),
3807                                 XEXP (XEXP (x, 1), 1));
3808
3809       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3810          (and <foo> (const_int pow2-1))  */
3811       if (GET_CODE (XEXP (x, 1)) == AND
3812           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3813           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3814           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3815         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3816                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3817
3818       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3819          integers.  */
3820       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3821         return gen_binary (MINUS, mode,
3822                            gen_binary (MINUS, mode, XEXP (x, 0),
3823                                        XEXP (XEXP (x, 1), 0)),
3824                            XEXP (XEXP (x, 1), 1));
3825       break;
3826
3827     case MULT:
3828       /* If we have (mult (plus A B) C), apply the distributive law and then
3829          the inverse distributive law to see if things simplify.  This
3830          occurs mostly in addresses, often when unrolling loops.  */
3831
3832       if (GET_CODE (XEXP (x, 0)) == PLUS)
3833         {
3834           x = apply_distributive_law
3835             (gen_binary (PLUS, mode,
3836                          gen_binary (MULT, mode,
3837                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3838                          gen_binary (MULT, mode,
3839                                      XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3840
3841           if (GET_CODE (x) != MULT)
3842             return x;
3843         }
3844       break;
3845
3846     case UDIV:
3847       /* If this is a divide by a power of two, treat it as a shift if
3848          its first operand is a shift.  */
3849       if (GET_CODE (XEXP (x, 1)) == CONST_INT
3850           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3851           && (GET_CODE (XEXP (x, 0)) == ASHIFT
3852               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3853               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3854               || GET_CODE (XEXP (x, 0)) == ROTATE
3855               || GET_CODE (XEXP (x, 0)) == ROTATERT))
3856         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3857       break;
3858
3859     case EQ:  case NE:
3860     case GT:  case GTU:  case GE:  case GEU:
3861     case LT:  case LTU:  case LE:  case LEU:
3862       /* If the first operand is a condition code, we can't do anything
3863          with it.  */
3864       if (GET_CODE (XEXP (x, 0)) == COMPARE
3865           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3866 #ifdef HAVE_cc0
3867               && XEXP (x, 0) != cc0_rtx
3868 #endif
3869                ))
3870         {
3871           rtx op0 = XEXP (x, 0);
3872           rtx op1 = XEXP (x, 1);
3873           enum rtx_code new_code;
3874
3875           if (GET_CODE (op0) == COMPARE)
3876             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3877
3878           /* Simplify our comparison, if possible.  */
3879           new_code = simplify_comparison (code, &op0, &op1);
3880
3881           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3882              if only the low-order bit is possibly nonzero in X (such as when
3883              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
3884              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
3885              known to be either 0 or -1, NE becomes a NEG and EQ becomes
3886              (plus X 1).
3887
3888              Remove any ZERO_EXTRACT we made when thinking this was a
3889              comparison.  It may now be simpler to use, e.g., an AND.  If a
3890              ZERO_EXTRACT is indeed appropriate, it will be placed back by
3891              the call to make_compound_operation in the SET case.  */
3892
3893           if (STORE_FLAG_VALUE == 1
3894               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3895               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3896             return gen_lowpart_for_combine (mode,
3897                                             expand_compound_operation (op0));
3898
3899           else if (STORE_FLAG_VALUE == 1
3900                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3901                    && op1 == const0_rtx
3902                    && (num_sign_bit_copies (op0, mode)
3903                        == GET_MODE_BITSIZE (mode)))
3904             {
3905               op0 = expand_compound_operation (op0);
3906               return gen_unary (NEG, mode, mode,
3907                                 gen_lowpart_for_combine (mode, op0));
3908             }
3909
3910           else if (STORE_FLAG_VALUE == 1
3911                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3912                    && op1 == const0_rtx
3913                    && nonzero_bits (op0, mode) == 1)
3914             {
3915               op0 = expand_compound_operation (op0);
3916               return gen_binary (XOR, mode,
3917                                  gen_lowpart_for_combine (mode, op0),
3918                                  const1_rtx);
3919             }
3920
3921           else if (STORE_FLAG_VALUE == 1
3922                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3923                    && op1 == const0_rtx
3924                    && (num_sign_bit_copies (op0, mode)
3925                        == GET_MODE_BITSIZE (mode)))
3926             {
3927               op0 = expand_compound_operation (op0);
3928               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3929             }
3930
3931           /* If STORE_FLAG_VALUE is -1, we have cases similar to
3932              those above.  */
3933           if (STORE_FLAG_VALUE == -1
3934               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3935               && op1 == const0_rtx
3936               && (num_sign_bit_copies (op0, mode)
3937                   == GET_MODE_BITSIZE (mode)))
3938             return gen_lowpart_for_combine (mode,
3939                                             expand_compound_operation (op0));
3940
3941           else if (STORE_FLAG_VALUE == -1
3942                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3943                    && op1 == const0_rtx
3944                    && nonzero_bits (op0, mode) == 1)
3945             {
3946               op0 = expand_compound_operation (op0);
3947               return gen_unary (NEG, mode, mode,
3948                                 gen_lowpart_for_combine (mode, op0));
3949             }
3950
3951           else if (STORE_FLAG_VALUE == -1
3952                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3953                    && op1 == const0_rtx
3954                    && (num_sign_bit_copies (op0, mode)
3955                        == GET_MODE_BITSIZE (mode)))
3956             {
3957               op0 = expand_compound_operation (op0);
3958               return gen_unary (NOT, mode, mode,
3959                                 gen_lowpart_for_combine (mode, op0));
3960             }
3961
3962           /* If X is 0/1, (eq X 0) is X-1.  */
3963           else if (STORE_FLAG_VALUE == -1
3964                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3965                    && op1 == const0_rtx
3966                    && nonzero_bits (op0, mode) == 1)
3967             {
3968               op0 = expand_compound_operation (op0);
3969               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3970             }
3971
3972           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3973              one bit that might be nonzero, we can convert (ne x 0) to
3974              (ashift x c) where C puts the bit in the sign bit.  Remove any
3975              AND with STORE_FLAG_VALUE when we are done, since we are only
3976              going to test the sign bit.  */
3977           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3978               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3979               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
3980                   == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3981               && op1 == const0_rtx
3982               && mode == GET_MODE (op0)
3983               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3984             {
3985               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3986                                         expand_compound_operation (op0),
3987                                         GET_MODE_BITSIZE (mode) - 1 - i);
3988               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3989                 return XEXP (x, 0);
3990               else
3991                 return x;
3992             }
3993
3994           /* If the code changed, return a whole new comparison.  */
3995           if (new_code != code)
3996             return gen_rtx_combine (new_code, mode, op0, op1);
3997
3998           /* Otherwise, keep this operation, but maybe change its operands.
3999              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4000           SUBST (XEXP (x, 0), op0);
4001           SUBST (XEXP (x, 1), op1);
4002         }
4003       break;
4004
4005     case IF_THEN_ELSE:
4006       return simplify_if_then_else (x);
4007
4008     case ZERO_EXTRACT:
4009     case SIGN_EXTRACT:
4010     case ZERO_EXTEND:
4011     case SIGN_EXTEND:
4012       /* If we are processing SET_DEST, we are done.  */
4013       if (in_dest)
4014         return x;
4015
4016       return expand_compound_operation (x);
4017
4018     case SET:
4019       return simplify_set (x);
4020
4021     case AND:
4022     case IOR:
4023     case XOR:
4024       return simplify_logical (x, last);
4025
4026     case ABS:
4027       /* (abs (neg <foo>)) -> (abs <foo>) */
4028       if (GET_CODE (XEXP (x, 0)) == NEG)
4029         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4030
4031       /* If operand is something known to be positive, ignore the ABS.  */
4032       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4033           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4034                <= HOST_BITS_PER_WIDE_INT)
4035               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4036                    & ((HOST_WIDE_INT) 1
4037                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4038                   == 0)))
4039         return XEXP (x, 0);
4040
4041
4042       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4043       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4044         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4045
4046       break;
4047
4048     case FFS:
4049       /* (ffs (*_extend <X>)) = (ffs <X>) */
4050       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4051           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4052         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4053       break;
4054
4055     case FLOAT:
4056       /* (float (sign_extend <X>)) = (float <X>).  */
4057       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4058         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4059       break;
4060
4061     case ASHIFT:
4062     case LSHIFTRT:
4063     case ASHIFTRT:
4064     case ROTATE:
4065     case ROTATERT:
4066       /* If this is a shift by a constant amount, simplify it.  */
4067       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4068         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4069                                      INTVAL (XEXP (x, 1)));
4070
4071 #ifdef SHIFT_COUNT_TRUNCATED
4072       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4073         SUBST (XEXP (x, 1),
4074                force_to_mode (XEXP (x, 1), GET_MODE (x),
4075                               ((HOST_WIDE_INT) 1
4076                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4077                               - 1,
4078                               NULL_RTX, 0));
4079 #endif
4080
4081       break;
4082     }
4083
4084   return x;
4085 }
4086 \f
4087 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4088
4089 static rtx
4090 simplify_if_then_else (x)
4091      rtx x;
4092 {
4093   enum machine_mode mode = GET_MODE (x);
4094   rtx cond = XEXP (x, 0);
4095   rtx true = XEXP (x, 1);
4096   rtx false = XEXP (x, 2);
4097   enum rtx_code true_code = GET_CODE (cond);
4098   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4099   rtx temp;
4100   int i;
4101
4102   /* Simplify storing of the truth value.  */
4103   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4104     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4105
4106   /* Also when the truth value has to be reversed.  */
4107   if (comparison_p && reversible_comparison_p (cond)
4108       && true == const0_rtx && false == const_true_rtx)
4109     return gen_binary (reverse_condition (true_code),
4110                        mode, XEXP (cond, 0), XEXP (cond, 1));
4111
4112   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4113      in it is being compared against certain values.  Get the true and false
4114      comparisons and see if that says anything about the value of each arm.  */
4115
4116   if (comparison_p && reversible_comparison_p (cond)
4117       && GET_CODE (XEXP (cond, 0)) == REG)
4118     {
4119       HOST_WIDE_INT nzb;
4120       rtx from = XEXP (cond, 0);
4121       enum rtx_code false_code = reverse_condition (true_code);
4122       rtx true_val = XEXP (cond, 1);
4123       rtx false_val = true_val;
4124       int swapped = 0;
4125
4126       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4127
4128       if (false_code == EQ)
4129         {
4130           swapped = 1, true_code = EQ, false_code = NE;
4131           temp = true, true = false, false = temp;
4132         }
4133
4134       /* If we are comparing against zero and the expression being tested has
4135          only a single bit that might be nonzero, that is its value when it is
4136          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4137
4138       if (true_code == EQ && true_val == const0_rtx
4139           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4140         false_code = EQ, false_val = GEN_INT (nzb);
4141       else if (true_code == EQ && true_val == const0_rtx
4142                && (num_sign_bit_copies (from, GET_MODE (from))
4143                    == GET_MODE_BITSIZE (GET_MODE (from))))
4144         false_code = EQ, false_val = constm1_rtx;
4145
4146       /* Now simplify an arm if we know the value of the register in the
4147          branch and it is used in the arm.  Be careful due to the potential
4148          of locally-shared RTL.  */
4149
4150       if (reg_mentioned_p (from, true))
4151         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4152                       pc_rtx, pc_rtx, 0, 0);
4153       if (reg_mentioned_p (from, false))
4154         false = subst (known_cond (copy_rtx (false), false_code,
4155                                    from, false_val),
4156                        pc_rtx, pc_rtx, 0, 0);
4157
4158       SUBST (XEXP (x, 1), swapped ? false : true);
4159       SUBST (XEXP (x, 2), swapped ? true : false);
4160
4161       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4162     }
4163
4164   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4165      reversed, do so to avoid needing two sets of patterns for
4166      subtract-and-branch insns.  Similarly if we have a constant in the true
4167      arm, the false arm is the same as the first operand of the comparison, or
4168      the false arm is more complicated than the true arm.  */
4169
4170   if (comparison_p && reversible_comparison_p (cond)
4171       && (true == pc_rtx
4172           || (CONSTANT_P (true)
4173               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4174           || true == const0_rtx
4175           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4176               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4177           || (GET_CODE (true) == SUBREG
4178               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4179               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4180           || reg_mentioned_p (true, false)
4181           || rtx_equal_p (false, XEXP (cond, 0))))
4182     {
4183       true_code = reverse_condition (true_code);
4184       SUBST (XEXP (x, 0),
4185              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4186                          XEXP (cond, 1)));
4187
4188       SUBST (XEXP (x, 1), false);
4189       SUBST (XEXP (x, 2), true);
4190
4191       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4192
4193       /* It is possible that the conditional has been simplified out.  */
4194       true_code = GET_CODE (cond);
4195       comparison_p = GET_RTX_CLASS (true_code) == '<';
4196     }
4197
4198   /* If the two arms are identical, we don't need the comparison.  */
4199
4200   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4201     return true;
4202
4203   /* Convert a == b ? b : a to "a".  */
4204   if (true_code == EQ && ! side_effects_p (cond)
4205       && rtx_equal_p (XEXP (cond, 0), false)
4206       && rtx_equal_p (XEXP (cond, 1), true))
4207     return false;
4208   else if (true_code == NE && ! side_effects_p (cond)
4209            && rtx_equal_p (XEXP (cond, 0), true)
4210            && rtx_equal_p (XEXP (cond, 1), false))
4211     return true;
4212
4213   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4214
4215   if (GET_MODE_CLASS (mode) == MODE_INT
4216       && GET_CODE (false) == NEG
4217       && rtx_equal_p (true, XEXP (false, 0))
4218       && comparison_p
4219       && rtx_equal_p (true, XEXP (cond, 0))
4220       && ! side_effects_p (true))
4221     switch (true_code)
4222       {
4223       case GT:
4224       case GE:
4225         return gen_unary (ABS, mode, mode, true);
4226       case LT:
4227       case LE:
4228         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4229       }
4230
4231   /* Look for MIN or MAX.  */
4232
4233   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4234       && comparison_p
4235       && rtx_equal_p (XEXP (cond, 0), true)
4236       && rtx_equal_p (XEXP (cond, 1), false)
4237       && ! side_effects_p (cond))
4238     switch (true_code)
4239       {
4240       case GE:
4241       case GT:
4242         return gen_binary (SMAX, mode, true, false);
4243       case LE:
4244       case LT:
4245         return gen_binary (SMIN, mode, true, false);
4246       case GEU:
4247       case GTU:
4248         return gen_binary (UMAX, mode, true, false);
4249       case LEU:
4250       case LTU:
4251         return gen_binary (UMIN, mode, true, false);
4252       }
4253
4254   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4255      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4256      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4257      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4258      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4259      neither 1 or -1, but it isn't worth checking for.  */
4260
4261   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4262       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4263     {
4264       rtx t = make_compound_operation (true, SET);
4265       rtx f = make_compound_operation (false, SET);
4266       rtx cond_op0 = XEXP (cond, 0);
4267       rtx cond_op1 = XEXP (cond, 1);
4268       enum rtx_code op, extend_op = NIL;
4269       enum machine_mode m = mode;
4270       rtx z = 0, c1;
4271
4272       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4273            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4274            || GET_CODE (t) == ASHIFT
4275            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4276           && rtx_equal_p (XEXP (t, 0), f))
4277         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4278
4279       /* If an identity-zero op is commutative, check whether there
4280          would be a match if we swapped the operands.  */
4281       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4282                 || GET_CODE (t) == XOR)
4283                && rtx_equal_p (XEXP (t, 1), f))
4284         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4285       else if (GET_CODE (t) == SIGN_EXTEND
4286                && (GET_CODE (XEXP (t, 0)) == PLUS
4287                    || GET_CODE (XEXP (t, 0)) == MINUS
4288                    || GET_CODE (XEXP (t, 0)) == IOR
4289                    || GET_CODE (XEXP (t, 0)) == XOR
4290                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4291                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4292                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4293                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4294                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4295                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4296                && (num_sign_bit_copies (f, GET_MODE (f))
4297                    > (GET_MODE_BITSIZE (mode)
4298                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4299         {
4300           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4301           extend_op = SIGN_EXTEND;
4302           m = GET_MODE (XEXP (t, 0));
4303         }
4304       else if (GET_CODE (t) == SIGN_EXTEND
4305                && (GET_CODE (XEXP (t, 0)) == PLUS
4306                    || GET_CODE (XEXP (t, 0)) == IOR
4307                    || GET_CODE (XEXP (t, 0)) == XOR)
4308                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4309                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4310                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4311                && (num_sign_bit_copies (f, GET_MODE (f))
4312                    > (GET_MODE_BITSIZE (mode)
4313                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4314         {
4315           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4316           extend_op = SIGN_EXTEND;
4317           m = GET_MODE (XEXP (t, 0));
4318         }
4319       else if (GET_CODE (t) == ZERO_EXTEND
4320                && (GET_CODE (XEXP (t, 0)) == PLUS
4321                    || GET_CODE (XEXP (t, 0)) == MINUS
4322                    || GET_CODE (XEXP (t, 0)) == IOR
4323                    || GET_CODE (XEXP (t, 0)) == XOR
4324                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4325                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4326                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4327                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4328                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4329                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4330                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4331                && ((nonzero_bits (f, GET_MODE (f))
4332                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4333                    == 0))
4334         {
4335           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4336           extend_op = ZERO_EXTEND;
4337           m = GET_MODE (XEXP (t, 0));
4338         }
4339       else if (GET_CODE (t) == ZERO_EXTEND
4340                && (GET_CODE (XEXP (t, 0)) == PLUS
4341                    || GET_CODE (XEXP (t, 0)) == IOR
4342                    || GET_CODE (XEXP (t, 0)) == XOR)
4343                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4344                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4345                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4346                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4347                && ((nonzero_bits (f, GET_MODE (f))
4348                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4349                    == 0))
4350         {
4351           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4352           extend_op = ZERO_EXTEND;
4353           m = GET_MODE (XEXP (t, 0));
4354         }
4355
4356       if (z)
4357         {
4358           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4359                         pc_rtx, pc_rtx, 0, 0);
4360           temp = gen_binary (MULT, m, temp,
4361                              gen_binary (MULT, m, c1, const_true_rtx));
4362           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4363           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4364
4365           if (extend_op != NIL)
4366             temp = gen_unary (extend_op, mode, m, temp);
4367
4368           return temp;
4369         }
4370     }
4371
4372   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4373      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4374      negation of a single bit, we can convert this operation to a shift.  We
4375      can actually do this more generally, but it doesn't seem worth it.  */
4376
4377   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4378       && false == const0_rtx && GET_CODE (true) == CONST_INT
4379       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4380            && (i = exact_log2 (INTVAL (true))) >= 0)
4381           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4382                == GET_MODE_BITSIZE (mode))
4383               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4384     return
4385       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4386                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4387
4388   return x;
4389 }
4390 \f
4391 /* Simplify X, a SET expression.  Return the new expression.  */
4392
4393 static rtx
4394 simplify_set (x)
4395      rtx x;
4396 {
4397   rtx src = SET_SRC (x);
4398   rtx dest = SET_DEST (x);
4399   enum machine_mode mode
4400     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4401   rtx other_insn;
4402   rtx *cc_use;
4403
4404   /* (set (pc) (return)) gets written as (return).  */
4405   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4406     return src;
4407
4408   /* Now that we know for sure which bits of SRC we are using, see if we can
4409      simplify the expression for the object knowing that we only need the
4410      low-order bits.  */
4411
4412   if (GET_MODE_CLASS (mode) == MODE_INT)
4413     src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4414
4415   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4416      the comparison result and try to simplify it unless we already have used
4417      undobuf.other_insn.  */
4418   if ((GET_CODE (src) == COMPARE
4419 #ifdef HAVE_cc0
4420        || dest == cc0_rtx
4421 #endif
4422        )
4423       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4424       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4425       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4426       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4427     {
4428       enum rtx_code old_code = GET_CODE (*cc_use);
4429       enum rtx_code new_code;
4430       rtx op0, op1;
4431       int other_changed = 0;
4432       enum machine_mode compare_mode = GET_MODE (dest);
4433
4434       if (GET_CODE (src) == COMPARE)
4435         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4436       else
4437         op0 = src, op1 = const0_rtx;
4438
4439       /* Simplify our comparison, if possible.  */
4440       new_code = simplify_comparison (old_code, &op0, &op1);
4441
4442 #ifdef EXTRA_CC_MODES
4443       /* If this machine has CC modes other than CCmode, check to see if we
4444          need to use a different CC mode here.  */
4445       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4446 #endif /* EXTRA_CC_MODES */
4447
4448 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4449       /* If the mode changed, we have to change SET_DEST, the mode in the
4450          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4451          a hard register, just build new versions with the proper mode.  If it
4452          is a pseudo, we lose unless it is only time we set the pseudo, in
4453          which case we can safely change its mode.  */
4454       if (compare_mode != GET_MODE (dest))
4455         {
4456           int regno = REGNO (dest);
4457           rtx new_dest = gen_rtx (REG, compare_mode, regno);
4458
4459           if (regno < FIRST_PSEUDO_REGISTER
4460               || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4461             {
4462               if (regno >= FIRST_PSEUDO_REGISTER)
4463                 SUBST (regno_reg_rtx[regno], new_dest);
4464
4465               SUBST (SET_DEST (x), new_dest);
4466               SUBST (XEXP (*cc_use, 0), new_dest);
4467               other_changed = 1;
4468
4469               dest = new_dest;
4470             }
4471         }
4472 #endif
4473
4474       /* If the code changed, we have to build a new comparison in
4475          undobuf.other_insn.  */
4476       if (new_code != old_code)
4477         {
4478           unsigned HOST_WIDE_INT mask;
4479
4480           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4481                                            dest, const0_rtx));
4482
4483           /* If the only change we made was to change an EQ into an NE or
4484              vice versa, OP0 has only one bit that might be nonzero, and OP1
4485              is zero, check if changing the user of the condition code will
4486              produce a valid insn.  If it won't, we can keep the original code
4487              in that insn by surrounding our operation with an XOR.  */
4488
4489           if (((old_code == NE && new_code == EQ)
4490                || (old_code == EQ && new_code == NE))
4491               && ! other_changed && op1 == const0_rtx
4492               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4493               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4494             {
4495               rtx pat = PATTERN (other_insn), note = 0;
4496               int scratches;
4497
4498               if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
4499                    && ! check_asm_operands (pat)))
4500                 {
4501                   PUT_CODE (*cc_use, old_code);
4502                   other_insn = 0;
4503
4504                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4505                 }
4506             }
4507
4508           other_changed = 1;
4509         }
4510
4511       if (other_changed)
4512         undobuf.other_insn = other_insn;
4513
4514 #ifdef HAVE_cc0
4515       /* If we are now comparing against zero, change our source if
4516          needed.  If we do not use cc0, we always have a COMPARE.  */
4517       if (op1 == const0_rtx && dest == cc0_rtx)
4518         {
4519           SUBST (SET_SRC (x), op0);
4520           src = op0;
4521         }
4522       else
4523 #endif
4524
4525       /* Otherwise, if we didn't previously have a COMPARE in the
4526          correct mode, we need one.  */
4527       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4528         {
4529           SUBST (SET_SRC (x),
4530                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4531           src = SET_SRC (x);
4532         }
4533       else
4534         {
4535           /* Otherwise, update the COMPARE if needed.  */
4536           SUBST (XEXP (src, 0), op0);
4537           SUBST (XEXP (src, 1), op1);
4538         }
4539     }
4540   else
4541     {
4542       /* Get SET_SRC in a form where we have placed back any
4543          compound expressions.  Then do the checks below.  */
4544       src = make_compound_operation (src, SET);
4545       SUBST (SET_SRC (x), src);
4546     }
4547
4548   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4549      and X being a REG or (subreg (reg)), we may be able to convert this to
4550      (set (subreg:m2 x) (op)).
4551
4552      We can always do this if M1 is narrower than M2 because that means that
4553      we only care about the low bits of the result.
4554
4555      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4556      perform a narrower operation that requested since the high-order bits will
4557      be undefined.  On machine where it is defined, this transformation is safe
4558      as long as M1 and M2 have the same number of words.  */
4559
4560   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4561       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4562       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4563            / UNITS_PER_WORD)
4564           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4565                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4566 #ifndef WORD_REGISTER_OPERATIONS
4567       && (GET_MODE_SIZE (GET_MODE (src))
4568           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4569 #endif
4570 #ifdef CLASS_CANNOT_CHANGE_SIZE
4571       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4572             && (TEST_HARD_REG_BIT
4573                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4574                  REGNO (dest)))
4575             && (GET_MODE_SIZE (GET_MODE (src))
4576                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4577 #endif
4578       && (GET_CODE (dest) == REG
4579           || (GET_CODE (dest) == SUBREG
4580               && GET_CODE (SUBREG_REG (dest)) == REG)))
4581     {
4582       SUBST (SET_DEST (x),
4583              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4584                                       dest));
4585       SUBST (SET_SRC (x), SUBREG_REG (src));
4586
4587       src = SET_SRC (x), dest = SET_DEST (x);
4588     }
4589
4590 #ifdef LOAD_EXTEND_OP
4591   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4592      would require a paradoxical subreg.  Replace the subreg with a
4593      zero_extend to avoid the reload that would otherwise be required.  */
4594
4595   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4596       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4597       && SUBREG_WORD (src) == 0
4598       && (GET_MODE_SIZE (GET_MODE (src))
4599           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4600       && GET_CODE (SUBREG_REG (src)) == MEM)
4601     {
4602       SUBST (SET_SRC (x),
4603              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4604                               GET_MODE (src), XEXP (src, 0)));
4605
4606       src = SET_SRC (x);
4607     }
4608 #endif
4609
4610   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4611      are comparing an item known to be 0 or -1 against 0, use a logical
4612      operation instead. Check for one of the arms being an IOR of the other
4613      arm with some value.  We compute three terms to be IOR'ed together.  In
4614      practice, at most two will be nonzero.  Then we do the IOR's.  */
4615
4616   if (GET_CODE (dest) != PC
4617       && GET_CODE (src) == IF_THEN_ELSE
4618       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4619       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4620       && XEXP (XEXP (src, 0), 1) == const0_rtx
4621       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4622 #ifdef HAVE_conditional_move
4623       && ! can_conditionally_move_p (GET_MODE (src))
4624 #endif
4625       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4626                                GET_MODE (XEXP (XEXP (src, 0), 0)))
4627           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4628       && ! side_effects_p (src))
4629     {
4630       rtx true = (GET_CODE (XEXP (src, 0)) == NE
4631                       ? XEXP (src, 1) : XEXP (src, 2));
4632       rtx false = (GET_CODE (XEXP (src, 0)) == NE
4633                    ? XEXP (src, 2) : XEXP (src, 1));
4634       rtx term1 = const0_rtx, term2, term3;
4635
4636       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4637         term1 = false, true = XEXP (true, 1), false = const0_rtx;
4638       else if (GET_CODE (true) == IOR
4639                && rtx_equal_p (XEXP (true, 1), false))
4640         term1 = false, true = XEXP (true, 0), false = const0_rtx;
4641       else if (GET_CODE (false) == IOR
4642                && rtx_equal_p (XEXP (false, 0), true))
4643         term1 = true, false = XEXP (false, 1), true = const0_rtx;
4644       else if (GET_CODE (false) == IOR
4645                && rtx_equal_p (XEXP (false, 1), true))
4646         term1 = true, false = XEXP (false, 0), true = const0_rtx;
4647
4648       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4649       term3 = gen_binary (AND, GET_MODE (src),
4650                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4651                                      XEXP (XEXP (src, 0), 0)),
4652                           false);
4653
4654       SUBST (SET_SRC (x),
4655              gen_binary (IOR, GET_MODE (src),
4656                          gen_binary (IOR, GET_MODE (src), term1, term2),
4657                          term3));
4658
4659       src = SET_SRC (x);
4660     }
4661
4662   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4663      whole thing fail.  */
4664   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4665     return src;
4666   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4667     return dest;
4668   else
4669     /* Convert this into a field assignment operation, if possible.  */
4670     return make_field_assignment (x);
4671 }
4672 \f
4673 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4674    result.  LAST is nonzero if this is the last retry.  */
4675
4676 static rtx
4677 simplify_logical (x, last)
4678      rtx x;
4679      int last;
4680 {
4681   enum machine_mode mode = GET_MODE (x);
4682   rtx op0 = XEXP (x, 0);
4683   rtx op1 = XEXP (x, 1);
4684
4685   switch (GET_CODE (x))
4686     {
4687     case AND:
4688       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4689          insn (and may simplify more).  */
4690       if (GET_CODE (op0) == XOR
4691           && rtx_equal_p (XEXP (op0, 0), op1)
4692           && ! side_effects_p (op1))
4693         x = gen_binary (AND, mode,
4694                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4695
4696       if (GET_CODE (op0) == XOR
4697           && rtx_equal_p (XEXP (op0, 1), op1)
4698           && ! side_effects_p (op1))
4699         x = gen_binary (AND, mode,
4700                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4701
4702       /* Similarly for (~ (A ^ B)) & A.  */
4703       if (GET_CODE (op0) == NOT
4704           && GET_CODE (XEXP (op0, 0)) == XOR
4705           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4706           && ! side_effects_p (op1))
4707         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4708
4709       if (GET_CODE (op0) == NOT
4710           && GET_CODE (XEXP (op0, 0)) == XOR
4711           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4712           && ! side_effects_p (op1))
4713         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4714
4715       if (GET_CODE (op1) == CONST_INT)
4716         {
4717           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4718
4719           /* If we have (ior (and (X C1) C2)) and the next restart would be
4720              the last, simplify this by making C1 as small as possible
4721              and then exit.  */
4722           if (last
4723               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4724               && GET_CODE (XEXP (op0, 1)) == CONST_INT
4725               && GET_CODE (op1) == CONST_INT)
4726             return gen_binary (IOR, mode,
4727                                gen_binary (AND, mode, XEXP (op0, 0),
4728                                            GEN_INT (INTVAL (XEXP (op0, 1))
4729                                                     & ~ INTVAL (op1))), op1);
4730
4731           if (GET_CODE (x) != AND)
4732             return x;
4733
4734           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4735               || GET_RTX_CLASS (GET_CODE (x)) == '2')
4736             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4737         }
4738
4739       /* Convert (A | B) & A to A.  */
4740       if (GET_CODE (op0) == IOR
4741           && (rtx_equal_p (XEXP (op0, 0), op1)
4742               || rtx_equal_p (XEXP (op0, 1), op1))
4743           && ! side_effects_p (XEXP (op0, 0))
4744           && ! side_effects_p (XEXP (op0, 1)))
4745         return op1;
4746
4747       /* In the following group of tests (and those in case IOR below),
4748          we start with some combination of logical operations and apply
4749          the distributive law followed by the inverse distributive law.
4750          Most of the time, this results in no change.  However, if some of
4751          the operands are the same or inverses of each other, simplifications
4752          will result.
4753
4754          For example, (and (ior A B) (not B)) can occur as the result of
4755          expanding a bit field assignment.  When we apply the distributive
4756          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4757          which then simplifies to (and (A (not B))).
4758
4759          If we have (and (ior A B) C), apply the distributive law and then
4760          the inverse distributive law to see if things simplify.  */
4761
4762       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4763         {
4764           x = apply_distributive_law
4765             (gen_binary (GET_CODE (op0), mode,
4766                          gen_binary (AND, mode, XEXP (op0, 0), op1),
4767                          gen_binary (AND, mode, XEXP (op0, 1), op1)));
4768           if (GET_CODE (x) != AND)
4769             return x;
4770         }
4771
4772       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4773         return apply_distributive_law
4774           (gen_binary (GET_CODE (op1), mode,
4775                        gen_binary (AND, mode, XEXP (op1, 0), op0),
4776                        gen_binary (AND, mode, XEXP (op1, 1), op0)));
4777
4778       /* Similarly, taking advantage of the fact that
4779          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
4780
4781       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4782         return apply_distributive_law
4783           (gen_binary (XOR, mode,
4784                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4785                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4786
4787       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4788         return apply_distributive_law
4789           (gen_binary (XOR, mode,
4790                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4791                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4792       break;
4793
4794     case IOR:
4795       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
4796       if (GET_CODE (op1) == CONST_INT
4797           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4798           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4799         return op1;
4800
4801       /* Convert (A & B) | A to A.  */
4802       if (GET_CODE (op0) == AND
4803           && (rtx_equal_p (XEXP (op0, 0), op1)
4804               || rtx_equal_p (XEXP (op0, 1), op1))
4805           && ! side_effects_p (XEXP (op0, 0))
4806           && ! side_effects_p (XEXP (op0, 1)))
4807         return op1;
4808
4809       /* If we have (ior (and A B) C), apply the distributive law and then
4810          the inverse distributive law to see if things simplify.  */
4811
4812       if (GET_CODE (op0) == AND)
4813         {
4814           x = apply_distributive_law
4815             (gen_binary (AND, mode,
4816                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
4817                          gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4818
4819           if (GET_CODE (x) != IOR)
4820             return x;
4821         }
4822
4823       if (GET_CODE (op1) == AND)
4824         {
4825           x = apply_distributive_law
4826             (gen_binary (AND, mode,
4827                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
4828                          gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4829
4830           if (GET_CODE (x) != IOR)
4831             return x;
4832         }
4833
4834       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4835          mode size to (rotate A CX).  */
4836
4837       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4838            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4839           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4840           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4841           && GET_CODE (XEXP (op1, 1)) == CONST_INT
4842           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4843               == GET_MODE_BITSIZE (mode)))
4844         return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4845                         (GET_CODE (op0) == ASHIFT
4846                          ? XEXP (op0, 1) : XEXP (op1, 1)));
4847
4848       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4849          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
4850          does not affect any of the bits in OP1, it can really be done
4851          as a PLUS and we can associate.  We do this by seeing if OP1
4852          can be safely shifted left C bits.  */
4853       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4854           && GET_CODE (XEXP (op0, 0)) == PLUS
4855           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4856           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4857           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4858         {
4859           int count = INTVAL (XEXP (op0, 1));
4860           HOST_WIDE_INT mask = INTVAL (op1) << count;
4861
4862           if (mask >> count == INTVAL (op1)
4863               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4864             {
4865               SUBST (XEXP (XEXP (op0, 0), 1),
4866                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4867               return op0;
4868             }
4869         }
4870       break;
4871
4872     case XOR:
4873       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4874          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4875          (NOT y).  */
4876       {
4877         int num_negated = 0;
4878
4879         if (GET_CODE (op0) == NOT)
4880           num_negated++, op0 = XEXP (op0, 0);
4881         if (GET_CODE (op1) == NOT)
4882           num_negated++, op1 = XEXP (op1, 0);
4883
4884         if (num_negated == 2)
4885           {
4886             SUBST (XEXP (x, 0), op0);
4887             SUBST (XEXP (x, 1), op1);
4888           }
4889         else if (num_negated == 1)
4890           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4891       }
4892
4893       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
4894          correspond to a machine insn or result in further simplifications
4895          if B is a constant.  */
4896
4897       if (GET_CODE (op0) == AND
4898           && rtx_equal_p (XEXP (op0, 1), op1)
4899           && ! side_effects_p (op1))
4900         return gen_binary (AND, mode,
4901                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4902                            op1);
4903
4904       else if (GET_CODE (op0) == AND
4905                && rtx_equal_p (XEXP (op0, 0), op1)
4906                && ! side_effects_p (op1))
4907         return gen_binary (AND, mode,
4908                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4909                            op1);
4910
4911       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4912          comparison if STORE_FLAG_VALUE is 1.  */
4913       if (STORE_FLAG_VALUE == 1
4914           && op1 == const1_rtx
4915           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4916           && reversible_comparison_p (op0))
4917         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4918                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4919
4920       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4921          is (lt foo (const_int 0)), so we can perform the above
4922          simplification if STORE_FLAG_VALUE is 1.  */
4923
4924       if (STORE_FLAG_VALUE == 1
4925           && op1 == const1_rtx
4926           && GET_CODE (op0) == LSHIFTRT
4927           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4928           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4929         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4930
4931       /* (xor (comparison foo bar) (const_int sign-bit))
4932          when STORE_FLAG_VALUE is the sign bit.  */
4933       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4934           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4935               == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4936           && op1 == const_true_rtx
4937           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4938           && reversible_comparison_p (op0))
4939         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4940                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4941       break;
4942     }
4943
4944   return x;
4945 }
4946 \f
4947 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4948    operations" because they can be replaced with two more basic operations.
4949    ZERO_EXTEND is also considered "compound" because it can be replaced with
4950    an AND operation, which is simpler, though only one operation.
4951
4952    The function expand_compound_operation is called with an rtx expression
4953    and will convert it to the appropriate shifts and AND operations,
4954    simplifying at each stage.
4955
4956    The function make_compound_operation is called to convert an expression
4957    consisting of shifts and ANDs into the equivalent compound expression.
4958    It is the inverse of this function, loosely speaking.  */
4959
4960 static rtx
4961 expand_compound_operation (x)
4962      rtx x;
4963 {
4964   int pos = 0, len;
4965   int unsignedp = 0;
4966   int modewidth;
4967   rtx tem;
4968
4969   switch (GET_CODE (x))
4970     {
4971     case ZERO_EXTEND:
4972       unsignedp = 1;
4973     case SIGN_EXTEND:
4974       /* We can't necessarily use a const_int for a multiword mode;
4975          it depends on implicitly extending the value.
4976          Since we don't know the right way to extend it,
4977          we can't tell whether the implicit way is right.
4978
4979          Even for a mode that is no wider than a const_int,
4980          we can't win, because we need to sign extend one of its bits through
4981          the rest of it, and we don't know which bit.  */
4982       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4983         return x;
4984
4985       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4986          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
4987          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4988          reloaded. If not for that, MEM's would very rarely be safe.
4989
4990          Reject MODEs bigger than a word, because we might not be able
4991          to reference a two-register group starting with an arbitrary register
4992          (and currently gen_lowpart might crash for a SUBREG).  */
4993
4994       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4995         return x;
4996
4997       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4998       /* If the inner object has VOIDmode (the only way this can happen
4999          is if it is a ASM_OPERANDS), we can't do anything since we don't
5000          know how much masking to do.  */
5001       if (len == 0)
5002         return x;
5003
5004       break;
5005
5006     case ZERO_EXTRACT:
5007       unsignedp = 1;
5008     case SIGN_EXTRACT:
5009       /* If the operand is a CLOBBER, just return it.  */
5010       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5011         return XEXP (x, 0);
5012
5013       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5014           || GET_CODE (XEXP (x, 2)) != CONST_INT
5015           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5016         return x;
5017
5018       len = INTVAL (XEXP (x, 1));
5019       pos = INTVAL (XEXP (x, 2));
5020
5021       /* If this goes outside the object being extracted, replace the object
5022          with a (use (mem ...)) construct that only combine understands
5023          and is used only for this purpose.  */
5024       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5025         SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5026
5027       if (BITS_BIG_ENDIAN)
5028         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5029
5030       break;
5031
5032     default:
5033       return x;
5034     }
5035
5036   /* We can optimize some special cases of ZERO_EXTEND.  */
5037   if (GET_CODE (x) == ZERO_EXTEND)
5038     {
5039       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5040          know that the last value didn't have any inappropriate bits
5041          set.  */
5042       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5043           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5044           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5045           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5046               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5047         return XEXP (XEXP (x, 0), 0);
5048
5049       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5050       if (GET_CODE (XEXP (x, 0)) == SUBREG
5051           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5052           && subreg_lowpart_p (XEXP (x, 0))
5053           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5054           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5055               & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5056         return SUBREG_REG (XEXP (x, 0));
5057
5058       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5059          is a comparison and STORE_FLAG_VALUE permits.  This is like
5060          the first case, but it works even when GET_MODE (x) is larger
5061          than HOST_WIDE_INT.  */
5062       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5063           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5064           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5065           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5066               <= HOST_BITS_PER_WIDE_INT)
5067           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5068               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5069         return XEXP (XEXP (x, 0), 0);
5070
5071       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5072       if (GET_CODE (XEXP (x, 0)) == SUBREG
5073           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5074           && subreg_lowpart_p (XEXP (x, 0))
5075           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5076           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5077               <= HOST_BITS_PER_WIDE_INT)
5078           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5079               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5080         return SUBREG_REG (XEXP (x, 0));
5081
5082       /* If sign extension is cheaper than zero extension, then use it
5083          if we know that no extraneous bits are set, and that the high
5084          bit is not set.  */
5085       if (flag_expensive_optimizations
5086           && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5087                && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5088                     & ~ (((unsigned HOST_WIDE_INT)
5089                           GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5090                          >> 1))
5091                    == 0))
5092               || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5093                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5094                       <= HOST_BITS_PER_WIDE_INT)
5095                   && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5096                        & ~ (((unsigned HOST_WIDE_INT)
5097                              GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5098                             >> 1))
5099                       == 0))))
5100         {
5101           rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5102
5103           if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5104             return expand_compound_operation (temp);
5105         }
5106     }
5107
5108   /* If we reach here, we want to return a pair of shifts.  The inner
5109      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5110      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5111      logical depending on the value of UNSIGNEDP.
5112
5113      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5114      converted into an AND of a shift.
5115
5116      We must check for the case where the left shift would have a negative
5117      count.  This can happen in a case like (x >> 31) & 255 on machines
5118      that can't shift by a constant.  On those machines, we would first
5119      combine the shift with the AND to produce a variable-position
5120      extraction.  Then the constant of 31 would be substituted in to produce
5121      a such a position.  */
5122
5123   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5124   if (modewidth >= pos - len)
5125     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5126                                 GET_MODE (x),
5127                                 simplify_shift_const (NULL_RTX, ASHIFT,
5128                                                       GET_MODE (x),
5129                                                       XEXP (x, 0),
5130                                                       modewidth - pos - len),
5131                                 modewidth - len);
5132
5133   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5134     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5135                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5136                                                         GET_MODE (x),
5137                                                         XEXP (x, 0), pos),
5138                                   ((HOST_WIDE_INT) 1 << len) - 1);
5139   else
5140     /* Any other cases we can't handle.  */
5141     return x;
5142
5143
5144   /* If we couldn't do this for some reason, return the original
5145      expression.  */
5146   if (GET_CODE (tem) == CLOBBER)
5147     return x;
5148
5149   return tem;
5150 }
5151 \f
5152 /* X is a SET which contains an assignment of one object into
5153    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5154    or certain SUBREGS). If possible, convert it into a series of
5155    logical operations.
5156
5157    We half-heartedly support variable positions, but do not at all
5158    support variable lengths.  */
5159
5160 static rtx
5161 expand_field_assignment (x)
5162      rtx x;
5163 {
5164   rtx inner;
5165   rtx pos;                      /* Always counts from low bit.  */
5166   int len;
5167   rtx mask;
5168   enum machine_mode compute_mode;
5169
5170   /* Loop until we find something we can't simplify.  */
5171   while (1)
5172     {
5173       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5174           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5175         {
5176           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5177           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5178           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5179         }
5180       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5181                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5182         {
5183           inner = XEXP (SET_DEST (x), 0);
5184           len = INTVAL (XEXP (SET_DEST (x), 1));
5185           pos = XEXP (SET_DEST (x), 2);
5186
5187           /* If the position is constant and spans the width of INNER,
5188              surround INNER  with a USE to indicate this.  */
5189           if (GET_CODE (pos) == CONST_INT
5190               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5191             inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5192
5193           if (BITS_BIG_ENDIAN)
5194             {
5195               if (GET_CODE (pos) == CONST_INT)
5196                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5197                                - INTVAL (pos));
5198               else if (GET_CODE (pos) == MINUS
5199                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5200                        && (INTVAL (XEXP (pos, 1))
5201                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5202                 /* If position is ADJUST - X, new position is X.  */
5203                 pos = XEXP (pos, 0);
5204               else
5205                 pos = gen_binary (MINUS, GET_MODE (pos),
5206                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5207                                            - len),
5208                                   pos);
5209             }
5210         }
5211
5212       /* A SUBREG between two modes that occupy the same numbers of words
5213          can be done by moving the SUBREG to the source.  */
5214       else if (GET_CODE (SET_DEST (x)) == SUBREG
5215                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5216                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5217                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5218                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5219         {
5220           x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5221                        gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5222                                                 SET_SRC (x)));
5223           continue;
5224         }
5225       else
5226         break;
5227
5228       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5229         inner = SUBREG_REG (inner);
5230
5231       compute_mode = GET_MODE (inner);
5232
5233       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5234       if (len < HOST_BITS_PER_WIDE_INT)
5235         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5236       else
5237         break;
5238
5239       /* Now compute the equivalent expression.  Make a copy of INNER
5240          for the SET_DEST in case it is a MEM into which we will substitute;
5241          we don't want shared RTL in that case.  */
5242       x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5243                    gen_binary (IOR, compute_mode,
5244                                gen_binary (AND, compute_mode,
5245                                            gen_unary (NOT, compute_mode,
5246                                                       compute_mode,
5247                                                       gen_binary (ASHIFT,
5248                                                                   compute_mode,
5249                                                                   mask, pos)),
5250                                            inner),
5251                                gen_binary (ASHIFT, compute_mode,
5252                                            gen_binary (AND, compute_mode,
5253                                                        gen_lowpart_for_combine
5254                                                        (compute_mode,
5255                                                         SET_SRC (x)),
5256                                                        mask),
5257                                            pos)));
5258     }
5259
5260   return x;
5261 }
5262 \f
5263 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5264    it is an RTX that represents a variable starting position; otherwise,
5265    POS is the (constant) starting bit position (counted from the LSB).
5266
5267    INNER may be a USE.  This will occur when we started with a bitfield
5268    that went outside the boundary of the object in memory, which is
5269    allowed on most machines.  To isolate this case, we produce a USE
5270    whose mode is wide enough and surround the MEM with it.  The only
5271    code that understands the USE is this routine.  If it is not removed,
5272    it will cause the resulting insn not to match.
5273
5274    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5275    signed reference.
5276
5277    IN_DEST is non-zero if this is a reference in the destination of a
5278    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5279    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5280    be used.
5281
5282    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5283    ZERO_EXTRACT should be built even for bits starting at bit 0.
5284
5285    MODE is the desired mode of the result (if IN_DEST == 0).
5286
5287    The result is an RTX for the extraction or NULL_RTX if the target
5288    can't handle it.  */
5289
5290 static rtx
5291 make_extraction (mode, inner, pos, pos_rtx, len,
5292                  unsignedp, in_dest, in_compare)
5293      enum machine_mode mode;
5294      rtx inner;
5295      int pos;
5296      rtx pos_rtx;
5297      int len;
5298      int unsignedp;
5299      int in_dest, in_compare;
5300 {
5301   /* This mode describes the size of the storage area
5302      to fetch the overall value from.  Within that, we
5303      ignore the POS lowest bits, etc.  */
5304   enum machine_mode is_mode = GET_MODE (inner);
5305   enum machine_mode inner_mode;
5306   enum machine_mode wanted_inner_mode = byte_mode;
5307   enum machine_mode wanted_inner_reg_mode = word_mode;
5308   enum machine_mode pos_mode = word_mode;
5309   enum machine_mode extraction_mode = word_mode;
5310   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5311   int spans_byte = 0;
5312   rtx new = 0;
5313   rtx orig_pos_rtx = pos_rtx;
5314   int orig_pos;
5315
5316   /* Get some information about INNER and get the innermost object.  */
5317   if (GET_CODE (inner) == USE)
5318     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5319     /* We don't need to adjust the position because we set up the USE
5320        to pretend that it was a full-word object.  */
5321     spans_byte = 1, inner = XEXP (inner, 0);
5322   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5323     {
5324       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5325          consider just the QI as the memory to extract from.
5326          The subreg adds or removes high bits; its mode is
5327          irrelevant to the meaning of this extraction,
5328          since POS and LEN count from the lsb.  */
5329       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5330         is_mode = GET_MODE (SUBREG_REG (inner));
5331       inner = SUBREG_REG (inner);
5332     }
5333
5334   inner_mode = GET_MODE (inner);
5335
5336   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5337     pos = INTVAL (pos_rtx), pos_rtx = 0;
5338
5339   /* See if this can be done without an extraction.  We never can if the
5340      width of the field is not the same as that of some integer mode. For
5341      registers, we can only avoid the extraction if the position is at the
5342      low-order bit and this is either not in the destination or we have the
5343      appropriate STRICT_LOW_PART operation available.
5344
5345      For MEM, we can avoid an extract if the field starts on an appropriate
5346      boundary and we can change the mode of the memory reference.  However,
5347      we cannot directly access the MEM if we have a USE and the underlying
5348      MEM is not TMODE.  This combination means that MEM was being used in a
5349      context where bits outside its mode were being referenced; that is only
5350      valid in bit-field insns.  */
5351
5352   if (tmode != BLKmode
5353       && ! (spans_byte && inner_mode != tmode)
5354       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5355            && GET_CODE (inner) != MEM
5356            && (! in_dest
5357                || (GET_CODE (inner) == REG
5358                    && (movstrict_optab->handlers[(int) tmode].insn_code
5359                        != CODE_FOR_nothing))))
5360           || (GET_CODE (inner) == MEM && pos_rtx == 0
5361               && (pos
5362                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5363                      : BITS_PER_UNIT)) == 0
5364               /* We can't do this if we are widening INNER_MODE (it
5365                  may not be aligned, for one thing).  */
5366               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5367               && (inner_mode == tmode
5368                   || (! mode_dependent_address_p (XEXP (inner, 0))
5369                       && ! MEM_VOLATILE_P (inner))))))
5370     {
5371       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5372          field.  If the original and current mode are the same, we need not
5373          adjust the offset.  Otherwise, we do if bytes big endian.
5374
5375          If INNER is not a MEM, get a piece consisting of just the field
5376          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5377
5378       if (GET_CODE (inner) == MEM)
5379         {
5380           int offset;
5381           /* POS counts from lsb, but make OFFSET count in memory order.  */
5382           if (BYTES_BIG_ENDIAN)
5383             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5384           else
5385             offset = pos / BITS_PER_UNIT;
5386
5387           new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5388           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5389           MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5390           MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5391         }
5392       else if (GET_CODE (inner) == REG)
5393         {
5394           /* We can't call gen_lowpart_for_combine here since we always want
5395              a SUBREG and it would sometimes return a new hard register.  */
5396           if (tmode != inner_mode)
5397             new = gen_rtx (SUBREG, tmode, inner,
5398                            (WORDS_BIG_ENDIAN
5399                             && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5400                             ? (((GET_MODE_SIZE (inner_mode)
5401                                  - GET_MODE_SIZE (tmode))
5402                                 / UNITS_PER_WORD)
5403                                - pos / BITS_PER_WORD)
5404                             : pos / BITS_PER_WORD));
5405           else
5406             new = inner;
5407         }
5408       else
5409         new = force_to_mode (inner, tmode,
5410                              len >= HOST_BITS_PER_WIDE_INT
5411                              ? GET_MODE_MASK (tmode)
5412                              : ((HOST_WIDE_INT) 1 << len) - 1,
5413                              NULL_RTX, 0);
5414
5415       /* If this extraction is going into the destination of a SET,
5416          make a STRICT_LOW_PART unless we made a MEM.  */
5417
5418       if (in_dest)
5419         return (GET_CODE (new) == MEM ? new
5420                 : (GET_CODE (new) != SUBREG
5421                    ? gen_rtx (CLOBBER, tmode, const0_rtx)
5422                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5423
5424       /* Otherwise, sign- or zero-extend unless we already are in the
5425          proper mode.  */
5426
5427       return (mode == tmode ? new
5428               : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5429                                  mode, new));
5430     }
5431
5432   /* Unless this is a COMPARE or we have a funny memory reference,
5433      don't do anything with zero-extending field extracts starting at
5434      the low-order bit since they are simple AND operations.  */
5435   if (pos_rtx == 0 && pos == 0 && ! in_dest
5436       && ! in_compare && ! spans_byte && unsignedp)
5437     return 0;
5438
5439   /* Unless we are allowed to span bytes, reject this if we would be
5440      spanning bytes or if the position is not a constant and the length
5441      is not 1.  In all other cases, we would only be going outside
5442      out object in cases when an original shift would have been
5443      undefined.  */
5444   if (! spans_byte
5445       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5446           || (pos_rtx != 0 && len != 1)))
5447     return 0;
5448
5449   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5450      and the mode for the result.  */
5451 #ifdef HAVE_insv
5452   if (in_dest)
5453     {
5454       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5455       pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5456       extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5457     }
5458 #endif
5459
5460 #ifdef HAVE_extzv
5461   if (! in_dest && unsignedp)
5462     {
5463       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5464       pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5465       extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5466     }
5467 #endif
5468
5469 #ifdef HAVE_extv
5470   if (! in_dest && ! unsignedp)
5471     {
5472       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5473       pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5474       extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5475     }
5476 #endif
5477
5478   /* Never narrow an object, since that might not be safe.  */
5479
5480   if (mode != VOIDmode
5481       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5482     extraction_mode = mode;
5483
5484   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5485       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5486     pos_mode = GET_MODE (pos_rtx);
5487
5488   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5489      if we have to change the mode of memory and cannot, the desired mode is
5490      EXTRACTION_MODE.  */
5491   if (GET_CODE (inner) != MEM)
5492     wanted_inner_mode = wanted_inner_reg_mode;
5493   else if (inner_mode != wanted_inner_mode
5494            && (mode_dependent_address_p (XEXP (inner, 0))
5495                || MEM_VOLATILE_P (inner)))
5496     wanted_inner_mode = extraction_mode;
5497
5498   orig_pos = pos;
5499
5500   if (BITS_BIG_ENDIAN)
5501     {
5502       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5503          BITS_BIG_ENDIAN style.  If position is constant, compute new
5504          position.  Otherwise, build subtraction.
5505          Note that POS is relative to the mode of the original argument.
5506          If it's a MEM we need to recompute POS relative to that.
5507          However, if we're extracting from (or inserting into) a register,
5508          we want to recompute POS relative to wanted_inner_mode.  */
5509       int width = (GET_CODE (inner) == MEM
5510                    ? GET_MODE_BITSIZE (is_mode)
5511                    : GET_MODE_BITSIZE (wanted_inner_mode));
5512
5513       if (pos_rtx == 0)
5514         pos = width - len - pos;
5515       else
5516         pos_rtx
5517           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5518                              GEN_INT (width - len), pos_rtx);
5519       /* POS may be less than 0 now, but we check for that below.
5520          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
5521     }
5522
5523   /* If INNER has a wider mode, make it smaller.  If this is a constant
5524      extract, try to adjust the byte to point to the byte containing
5525      the value.  */
5526   if (wanted_inner_mode != VOIDmode
5527       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5528       && ((GET_CODE (inner) == MEM
5529            && (inner_mode == wanted_inner_mode
5530                || (! mode_dependent_address_p (XEXP (inner, 0))
5531                    && ! MEM_VOLATILE_P (inner))))))
5532     {
5533       int offset = 0;
5534
5535       /* The computations below will be correct if the machine is big
5536          endian in both bits and bytes or little endian in bits and bytes.
5537          If it is mixed, we must adjust.  */
5538
5539       /* If bytes are big endian and we had a paradoxical SUBREG, we must
5540          adjust OFFSET to compensate.  */
5541       if (BYTES_BIG_ENDIAN
5542           && ! spans_byte
5543           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5544         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5545
5546       /* If this is a constant position, we can move to the desired byte.  */
5547       if (pos_rtx == 0)
5548         {
5549           offset += pos / BITS_PER_UNIT;
5550           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5551         }
5552
5553       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5554           && ! spans_byte
5555           && is_mode != wanted_inner_mode)
5556         offset = (GET_MODE_SIZE (is_mode)
5557                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
5558
5559       if (offset != 0 || inner_mode != wanted_inner_mode)
5560         {
5561           rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5562                                 plus_constant (XEXP (inner, 0), offset));
5563           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5564           MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5565           MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5566           inner = newmem;
5567         }
5568     }
5569
5570   /* If INNER is not memory, we can always get it into the proper mode.  If we
5571      are changing its mode, POS must be a constant and smaller than the size
5572      of the new mode.  */
5573   else if (GET_CODE (inner) != MEM)
5574     {
5575       if (GET_MODE (inner) != wanted_inner_mode
5576           && (pos_rtx != 0
5577               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5578         return 0;
5579
5580       inner = force_to_mode (inner, wanted_inner_mode,
5581                              pos_rtx
5582                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5583                              ? GET_MODE_MASK (wanted_inner_mode)
5584                              : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5585                              NULL_RTX, 0);
5586     }
5587
5588   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
5589      have to zero extend.  Otherwise, we can just use a SUBREG.  */
5590   if (pos_rtx != 0
5591       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5592     pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5593   else if (pos_rtx != 0
5594            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5595     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5596
5597   /* Make POS_RTX unless we already have it and it is correct.  If we don't
5598      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5599      be a CONST_INT.  */
5600   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5601     pos_rtx = orig_pos_rtx;
5602
5603   else if (pos_rtx == 0)
5604     pos_rtx = GEN_INT (pos);
5605
5606   /* Make the required operation.  See if we can use existing rtx.  */
5607   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5608                          extraction_mode, inner, GEN_INT (len), pos_rtx);
5609   if (! in_dest)
5610     new = gen_lowpart_for_combine (mode, new);
5611
5612   return new;
5613 }
5614 \f
5615 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5616    with any other operations in X.  Return X without that shift if so.  */
5617
5618 static rtx
5619 extract_left_shift (x, count)
5620      rtx x;
5621      int count;
5622 {
5623   enum rtx_code code = GET_CODE (x);
5624   enum machine_mode mode = GET_MODE (x);
5625   rtx tem;
5626
5627   switch (code)
5628     {
5629     case ASHIFT:
5630       /* This is the shift itself.  If it is wide enough, we will return
5631          either the value being shifted if the shift count is equal to
5632          COUNT or a shift for the difference.  */
5633       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5634           && INTVAL (XEXP (x, 1)) >= count)
5635         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5636                                      INTVAL (XEXP (x, 1)) - count);
5637       break;
5638
5639     case NEG:  case NOT:
5640       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5641         return gen_unary (code, mode, mode, tem);
5642
5643       break;
5644
5645     case PLUS:  case IOR:  case XOR:  case AND:
5646       /* If we can safely shift this constant and we find the inner shift,
5647          make a new operation.  */
5648       if (GET_CODE (XEXP (x,1)) == CONST_INT
5649           && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5650           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5651         return gen_binary (code, mode, tem,
5652                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5653
5654       break;
5655     }
5656
5657   return 0;
5658 }
5659 \f
5660 /* Look at the expression rooted at X.  Look for expressions
5661    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5662    Form these expressions.
5663
5664    Return the new rtx, usually just X.
5665
5666    Also, for machines like the Vax that don't have logical shift insns,
5667    try to convert logical to arithmetic shift operations in cases where
5668    they are equivalent.  This undoes the canonicalizations to logical
5669    shifts done elsewhere.
5670
5671    We try, as much as possible, to re-use rtl expressions to save memory.
5672
5673    IN_CODE says what kind of expression we are processing.  Normally, it is
5674    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
5675    being kludges), it is MEM.  When processing the arguments of a comparison
5676    or a COMPARE against zero, it is COMPARE.  */
5677
5678 static rtx
5679 make_compound_operation (x, in_code)
5680      rtx x;
5681      enum rtx_code in_code;
5682 {
5683   enum rtx_code code = GET_CODE (x);
5684   enum machine_mode mode = GET_MODE (x);
5685   int mode_width = GET_MODE_BITSIZE (mode);
5686   rtx rhs, lhs;
5687   enum rtx_code next_code;
5688   int i;
5689   rtx new = 0;
5690   rtx tem;
5691   char *fmt;
5692
5693   /* Select the code to be used in recursive calls.  Once we are inside an
5694      address, we stay there.  If we have a comparison, set to COMPARE,
5695      but once inside, go back to our default of SET.  */
5696
5697   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5698                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5699                   && XEXP (x, 1) == const0_rtx) ? COMPARE
5700                : in_code == COMPARE ? SET : in_code);
5701
5702   /* Process depending on the code of this operation.  If NEW is set
5703      non-zero, it will be returned.  */
5704
5705   switch (code)
5706     {
5707     case ASHIFT:
5708       /* Convert shifts by constants into multiplications if inside
5709          an address.  */
5710       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5711           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5712           && INTVAL (XEXP (x, 1)) >= 0)
5713         {
5714           new = make_compound_operation (XEXP (x, 0), next_code);
5715           new = gen_rtx_combine (MULT, mode, new,
5716                                  GEN_INT ((HOST_WIDE_INT) 1
5717                                           << INTVAL (XEXP (x, 1))));
5718         }
5719       break;
5720
5721     case AND:
5722       /* If the second operand is not a constant, we can't do anything
5723          with it.  */
5724       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5725         break;
5726
5727       /* If the constant is a power of two minus one and the first operand
5728          is a logical right shift, make an extraction.  */
5729       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5730           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5731         {
5732           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5733           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5734                                  0, in_code == COMPARE);
5735         }
5736
5737       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
5738       else if (GET_CODE (XEXP (x, 0)) == SUBREG
5739                && subreg_lowpart_p (XEXP (x, 0))
5740                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5741                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5742         {
5743           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5744                                          next_code);
5745           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5746                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5747                                  0, in_code == COMPARE);
5748         }
5749       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
5750       else if ((GET_CODE (XEXP (x, 0)) == XOR
5751                 || GET_CODE (XEXP (x, 0)) == IOR)
5752                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5753                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5754                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5755         {
5756           /* Apply the distributive law, and then try to make extractions.  */
5757           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5758                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5759                                           XEXP (x, 1)),
5760                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5761                                           XEXP (x, 1)));
5762           new = make_compound_operation (new, in_code);
5763         }
5764
5765       /* If we are have (and (rotate X C) M) and C is larger than the number
5766          of bits in M, this is an extraction.  */
5767
5768       else if (GET_CODE (XEXP (x, 0)) == ROTATE
5769                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5770                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5771                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5772         {
5773           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5774           new = make_extraction (mode, new,
5775                                  (GET_MODE_BITSIZE (mode)
5776                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
5777                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
5778         }
5779
5780       /* On machines without logical shifts, if the operand of the AND is
5781          a logical shift and our mask turns off all the propagated sign
5782          bits, we can replace the logical shift with an arithmetic shift.  */
5783       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5784                && (lshr_optab->handlers[(int) mode].insn_code
5785                    == CODE_FOR_nothing)
5786                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5787                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5788                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5789                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5790                && mode_width <= HOST_BITS_PER_WIDE_INT)
5791         {
5792           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5793
5794           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5795           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5796             SUBST (XEXP (x, 0),
5797                    gen_rtx_combine (ASHIFTRT, mode,
5798                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
5799                                                              next_code),
5800                                     XEXP (XEXP (x, 0), 1)));
5801         }
5802
5803       /* If the constant is one less than a power of two, this might be
5804          representable by an extraction even if no shift is present.
5805          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5806          we are in a COMPARE.  */
5807       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5808         new = make_extraction (mode,
5809                                make_compound_operation (XEXP (x, 0),
5810                                                         next_code),
5811                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5812
5813       /* If we are in a comparison and this is an AND with a power of two,
5814          convert this into the appropriate bit extract.  */
5815       else if (in_code == COMPARE
5816                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5817         new = make_extraction (mode,
5818                                make_compound_operation (XEXP (x, 0),
5819                                                         next_code),
5820                                i, NULL_RTX, 1, 1, 0, 1);
5821
5822       break;
5823
5824     case LSHIFTRT:
5825       /* If the sign bit is known to be zero, replace this with an
5826          arithmetic shift.  */
5827       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5828           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5829           && mode_width <= HOST_BITS_PER_WIDE_INT
5830           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5831         {
5832           new = gen_rtx_combine (ASHIFTRT, mode,
5833                                  make_compound_operation (XEXP (x, 0),
5834                                                           next_code),
5835                                  XEXP (x, 1));
5836           break;
5837         }
5838
5839       /* ... fall through ...  */
5840
5841     case ASHIFTRT:
5842       lhs = XEXP (x, 0);
5843       rhs = XEXP (x, 1);
5844
5845       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5846          this is a SIGN_EXTRACT.  */
5847       if (GET_CODE (rhs) == CONST_INT
5848           && GET_CODE (lhs) == ASHIFT
5849           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5850           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5851         {
5852           new = make_compound_operation (XEXP (lhs, 0), next_code);
5853           new = make_extraction (mode, new,
5854                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5855                                  NULL_RTX, mode_width - INTVAL (rhs),
5856                                  code == LSHIFTRT, 0, in_code == COMPARE);
5857         }
5858
5859       /* See if we have operations between an ASHIFTRT and an ASHIFT.
5860          If so, try to merge the shifts into a SIGN_EXTEND.  We could
5861          also do this for some cases of SIGN_EXTRACT, but it doesn't
5862          seem worth the effort; the case checked for occurs on Alpha.  */
5863
5864       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5865           && ! (GET_CODE (lhs) == SUBREG
5866                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5867           && GET_CODE (rhs) == CONST_INT
5868           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5869           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5870         new = make_extraction (mode, make_compound_operation (new, next_code),
5871                                0, NULL_RTX, mode_width - INTVAL (rhs),
5872                                code == LSHIFTRT, 0, in_code == COMPARE);
5873
5874       break;
5875
5876     case SUBREG:
5877       /* Call ourselves recursively on the inner expression.  If we are
5878          narrowing the object and it has a different RTL code from
5879          what it originally did, do this SUBREG as a force_to_mode.  */
5880
5881       tem = make_compound_operation (SUBREG_REG (x), in_code);
5882       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5883           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5884           && subreg_lowpart_p (x))
5885         {
5886           rtx newer = force_to_mode (tem, mode,
5887                                      GET_MODE_MASK (mode), NULL_RTX, 0);
5888
5889           /* If we have something other than a SUBREG, we might have
5890              done an expansion, so rerun outselves.  */
5891           if (GET_CODE (newer) != SUBREG)
5892             newer = make_compound_operation (newer, in_code);
5893
5894           return newer;
5895         }
5896     }
5897
5898   if (new)
5899     {
5900       x = gen_lowpart_for_combine (mode, new);
5901       code = GET_CODE (x);
5902     }
5903
5904   /* Now recursively process each operand of this operation.  */
5905   fmt = GET_RTX_FORMAT (code);
5906   for (i = 0; i < GET_RTX_LENGTH (code); i++)
5907     if (fmt[i] == 'e')
5908       {
5909         new = make_compound_operation (XEXP (x, i), next_code);
5910         SUBST (XEXP (x, i), new);
5911       }
5912
5913   return x;
5914 }
5915 \f
5916 /* Given M see if it is a value that would select a field of bits
5917     within an item, but not the entire word.  Return -1 if not.
5918     Otherwise, return the starting position of the field, where 0 is the
5919     low-order bit.
5920
5921    *PLEN is set to the length of the field.  */
5922
5923 static int
5924 get_pos_from_mask (m, plen)
5925      unsigned HOST_WIDE_INT m;
5926      int *plen;
5927 {
5928   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
5929   int pos = exact_log2 (m & - m);
5930
5931   if (pos < 0)
5932     return -1;
5933
5934   /* Now shift off the low-order zero bits and see if we have a power of
5935      two minus 1.  */
5936   *plen = exact_log2 ((m >> pos) + 1);
5937
5938   if (*plen <= 0)
5939     return -1;
5940
5941   return pos;
5942 }
5943 \f
5944 /* See if X can be simplified knowing that we will only refer to it in
5945    MODE and will only refer to those bits that are nonzero in MASK.
5946    If other bits are being computed or if masking operations are done
5947    that select a superset of the bits in MASK, they can sometimes be
5948    ignored.
5949
5950    Return a possibly simplified expression, but always convert X to
5951    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
5952
5953    Also, if REG is non-zero and X is a register equal in value to REG,
5954    replace X with REG.
5955
5956    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5957    are all off in X.  This is used when X will be complemented, by either
5958    NOT, NEG, or XOR.  */
5959
5960 static rtx
5961 force_to_mode (x, mode, mask, reg, just_select)
5962      rtx x;
5963      enum machine_mode mode;
5964      unsigned HOST_WIDE_INT mask;
5965      rtx reg;
5966      int just_select;
5967 {
5968   enum rtx_code code = GET_CODE (x);
5969   int next_select = just_select || code == XOR || code == NOT || code == NEG;
5970   enum machine_mode op_mode;
5971   unsigned HOST_WIDE_INT fuller_mask, nonzero;
5972   rtx op0, op1, temp;
5973
5974   /* If this is a CALL, don't do anything.  Some of the code below
5975      will do the wrong thing since the mode of a CALL is VOIDmode.  */
5976   if (code == CALL)
5977     return x;
5978
5979   /* We want to perform the operation is its present mode unless we know
5980      that the operation is valid in MODE, in which case we do the operation
5981      in MODE.  */
5982   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5983               && code_to_optab[(int) code] != 0
5984               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5985                   != CODE_FOR_nothing))
5986              ? mode : GET_MODE (x));
5987
5988   /* It is not valid to do a right-shift in a narrower mode
5989      than the one it came in with.  */
5990   if ((code == LSHIFTRT || code == ASHIFTRT)
5991       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5992     op_mode = GET_MODE (x);
5993
5994   /* Truncate MASK to fit OP_MODE.  */
5995   if (op_mode)
5996     mask &= GET_MODE_MASK (op_mode);
5997
5998   /* When we have an arithmetic operation, or a shift whose count we
5999      do not know, we need to assume that all bit the up to the highest-order
6000      bit in MASK will be needed.  This is how we form such a mask.  */
6001   if (op_mode)
6002     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6003                    ? GET_MODE_MASK (op_mode)
6004                    : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6005   else
6006     fuller_mask = ~ (HOST_WIDE_INT) 0;
6007
6008   /* Determine what bits of X are guaranteed to be (non)zero.  */
6009   nonzero = nonzero_bits (x, mode);
6010
6011   /* If none of the bits in X are needed, return a zero.  */
6012   if (! just_select && (nonzero & mask) == 0)
6013     return const0_rtx;
6014
6015   /* If X is a CONST_INT, return a new one.  Do this here since the
6016      test below will fail.  */
6017   if (GET_CODE (x) == CONST_INT)
6018     {
6019       HOST_WIDE_INT cval = INTVAL (x) & mask;
6020       int width = GET_MODE_BITSIZE (mode);
6021
6022       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6023          number, sign extend it.  */
6024       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6025           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6026         cval |= (HOST_WIDE_INT) -1 << width;
6027
6028       return GEN_INT (cval);
6029     }
6030
6031   /* If X is narrower than MODE and we want all the bits in X's mode, just
6032      get X in the proper mode.  */
6033   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6034       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6035     return gen_lowpart_for_combine (mode, x);
6036
6037   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6038      MASK are already known to be zero in X, we need not do anything.  */
6039   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6040     return x;
6041
6042   switch (code)
6043     {
6044     case CLOBBER:
6045       /* If X is a (clobber (const_int)), return it since we know we are
6046          generating something that won't match.  */
6047       return x;
6048
6049     case USE:
6050       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6051          spanned the boundary of the MEM.  If we are now masking so it is
6052          within that boundary, we don't need the USE any more.  */
6053       if (! BITS_BIG_ENDIAN
6054           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6055         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6056       break;
6057
6058     case SIGN_EXTEND:
6059     case ZERO_EXTEND:
6060     case ZERO_EXTRACT:
6061     case SIGN_EXTRACT:
6062       x = expand_compound_operation (x);
6063       if (GET_CODE (x) != code)
6064         return force_to_mode (x, mode, mask, reg, next_select);
6065       break;
6066
6067     case REG:
6068       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6069                        || rtx_equal_p (reg, get_last_value (x))))
6070         x = reg;
6071       break;
6072
6073     case SUBREG:
6074       if (subreg_lowpart_p (x)
6075           /* We can ignore the effect of this SUBREG if it narrows the mode or
6076              if the constant masks to zero all the bits the mode doesn't
6077              have.  */
6078           && ((GET_MODE_SIZE (GET_MODE (x))
6079                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6080               || (0 == (mask
6081                         & GET_MODE_MASK (GET_MODE (x))
6082                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6083         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6084       break;
6085
6086     case AND:
6087       /* If this is an AND with a constant, convert it into an AND
6088          whose constant is the AND of that constant with MASK.  If it
6089          remains an AND of MASK, delete it since it is redundant.  */
6090
6091       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6092         {
6093           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6094                                       mask & INTVAL (XEXP (x, 1)));
6095
6096           /* If X is still an AND, see if it is an AND with a mask that
6097              is just some low-order bits.  If so, and it is MASK, we don't
6098              need it.  */
6099
6100           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6101               && INTVAL (XEXP (x, 1)) == mask)
6102             x = XEXP (x, 0);
6103
6104           /* If it remains an AND, try making another AND with the bits
6105              in the mode mask that aren't in MASK turned on.  If the
6106              constant in the AND is wide enough, this might make a
6107              cheaper constant.  */
6108
6109           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6110               && GET_MODE_MASK (GET_MODE (x)) != mask
6111               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6112             {
6113               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6114                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6115               int width = GET_MODE_BITSIZE (GET_MODE (x));
6116               rtx y;
6117
6118               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6119                  number, sign extend it.  */
6120               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6121                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6122                 cval |= (HOST_WIDE_INT) -1 << width;
6123
6124               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6125               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6126                 x = y;
6127             }
6128
6129           break;
6130         }
6131
6132       goto binop;
6133
6134     case PLUS:
6135       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6136          low-order bits (as in an alignment operation) and FOO is already
6137          aligned to that boundary, mask C1 to that boundary as well.
6138          This may eliminate that PLUS and, later, the AND.  */
6139
6140       {
6141         int width = GET_MODE_BITSIZE (mode);
6142         unsigned HOST_WIDE_INT smask = mask;
6143
6144         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6145            number, sign extend it.  */
6146
6147         if (width < HOST_BITS_PER_WIDE_INT
6148             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6149           smask |= (HOST_WIDE_INT) -1 << width;
6150
6151         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6152             && exact_log2 (- smask) >= 0
6153             && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6154             && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6155           return force_to_mode (plus_constant (XEXP (x, 0),
6156                                                INTVAL (XEXP (x, 1)) & mask),
6157                                 mode, mask, reg, next_select);
6158       }
6159
6160       /* ... fall through ...  */
6161
6162     case MINUS:
6163     case MULT:
6164       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6165          most significant bit in MASK since carries from those bits will
6166          affect the bits we are interested in.  */
6167       mask = fuller_mask;
6168       goto binop;
6169
6170     case IOR:
6171     case XOR:
6172       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6173          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6174          operation which may be a bitfield extraction.  Ensure that the
6175          constant we form is not wider than the mode of X.  */
6176
6177       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6178           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6179           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6180           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6181           && GET_CODE (XEXP (x, 1)) == CONST_INT
6182           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6183                + floor_log2 (INTVAL (XEXP (x, 1))))
6184               < GET_MODE_BITSIZE (GET_MODE (x)))
6185           && (INTVAL (XEXP (x, 1))
6186               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6187         {
6188           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6189                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6190           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6191                              XEXP (XEXP (x, 0), 0), temp);
6192           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6193                           XEXP (XEXP (x, 0), 1));
6194           return force_to_mode (x, mode, mask, reg, next_select);
6195         }
6196
6197     binop:
6198       /* For most binary operations, just propagate into the operation and
6199          change the mode if we have an operation of that mode.   */
6200
6201       op0 = gen_lowpart_for_combine (op_mode,
6202                                      force_to_mode (XEXP (x, 0), mode, mask,
6203                                                     reg, next_select));
6204       op1 = gen_lowpart_for_combine (op_mode,
6205                                      force_to_mode (XEXP (x, 1), mode, mask,
6206                                                     reg, next_select));
6207
6208       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6209          MASK since OP1 might have been sign-extended but we never want
6210          to turn on extra bits, since combine might have previously relied
6211          on them being off.  */
6212       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6213           && (INTVAL (op1) & mask) != 0)
6214         op1 = GEN_INT (INTVAL (op1) & mask);
6215
6216       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6217         x = gen_binary (code, op_mode, op0, op1);
6218       break;
6219
6220     case ASHIFT:
6221       /* For left shifts, do the same, but just for the first operand.
6222          However, we cannot do anything with shifts where we cannot
6223          guarantee that the counts are smaller than the size of the mode
6224          because such a count will have a different meaning in a
6225          wider mode.  */
6226
6227       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6228              && INTVAL (XEXP (x, 1)) >= 0
6229              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6230           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6231                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6232                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6233         break;
6234
6235       /* If the shift count is a constant and we can do arithmetic in
6236          the mode of the shift, refine which bits we need.  Otherwise, use the
6237          conservative form of the mask.  */
6238       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6239           && INTVAL (XEXP (x, 1)) >= 0
6240           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6241           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6242         mask >>= INTVAL (XEXP (x, 1));
6243       else
6244         mask = fuller_mask;
6245
6246       op0 = gen_lowpart_for_combine (op_mode,
6247                                      force_to_mode (XEXP (x, 0), op_mode,
6248                                                     mask, reg, next_select));
6249
6250       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6251         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6252       break;
6253
6254     case LSHIFTRT:
6255       /* Here we can only do something if the shift count is a constant,
6256          this shift constant is valid for the host, and we can do arithmetic
6257          in OP_MODE.  */
6258
6259       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6260           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6261           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6262         {
6263           rtx inner = XEXP (x, 0);
6264
6265           /* Select the mask of the bits we need for the shift operand.  */
6266           mask <<= INTVAL (XEXP (x, 1));
6267
6268           /* We can only change the mode of the shift if we can do arithmetic
6269              in the mode of the shift and MASK is no wider than the width of
6270              OP_MODE.  */
6271           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6272               || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6273             op_mode = GET_MODE (x);
6274
6275           inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6276
6277           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6278             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6279         }
6280
6281       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6282          shift and AND produces only copies of the sign bit (C2 is one less
6283          than a power of two), we can do this with just a shift.  */
6284
6285       if (GET_CODE (x) == LSHIFTRT
6286           && GET_CODE (XEXP (x, 1)) == CONST_INT
6287           && ((INTVAL (XEXP (x, 1))
6288                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6289               >= GET_MODE_BITSIZE (GET_MODE (x)))
6290           && exact_log2 (mask + 1) >= 0
6291           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6292               >= exact_log2 (mask + 1)))
6293         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6294                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6295                                  - exact_log2 (mask + 1)));
6296       break;
6297
6298     case ASHIFTRT:
6299       /* If we are just looking for the sign bit, we don't need this shift at
6300          all, even if it has a variable count.  */
6301       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6302           && (mask == ((HOST_WIDE_INT) 1
6303                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6304         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6305
6306       /* If this is a shift by a constant, get a mask that contains those bits
6307          that are not copies of the sign bit.  We then have two cases:  If
6308          MASK only includes those bits, this can be a logical shift, which may
6309          allow simplifications.  If MASK is a single-bit field not within
6310          those bits, we are requesting a copy of the sign bit and hence can
6311          shift the sign bit to the appropriate location.  */
6312
6313       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6314           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6315         {
6316           int i = -1;
6317
6318           /* If the considered data is wider then HOST_WIDE_INT, we can't
6319              represent a mask for all its bits in a single scalar.
6320              But we only care about the lower bits, so calculate these.  */
6321
6322           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6323             {
6324               nonzero = ~ (HOST_WIDE_INT) 0;
6325
6326               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6327                  is the number of bits a full-width mask would have set.
6328                  We need only shift if these are fewer than nonzero can
6329                  hold.  If not, we must keep all bits set in nonzero.  */
6330
6331               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6332                   < HOST_BITS_PER_WIDE_INT)
6333                 nonzero >>= INTVAL (XEXP (x, 1))
6334                             + HOST_BITS_PER_WIDE_INT
6335                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6336             }
6337           else
6338             {
6339               nonzero = GET_MODE_MASK (GET_MODE (x));
6340               nonzero >>= INTVAL (XEXP (x, 1));
6341             }
6342
6343           if ((mask & ~ nonzero) == 0
6344               || (i = exact_log2 (mask)) >= 0)
6345             {
6346               x = simplify_shift_const
6347                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6348                  i < 0 ? INTVAL (XEXP (x, 1))
6349                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6350
6351               if (GET_CODE (x) != ASHIFTRT)
6352                 return force_to_mode (x, mode, mask, reg, next_select);
6353             }
6354         }
6355
6356       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6357          even if the shift count isn't a constant.  */
6358       if (mask == 1)
6359         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6360
6361       /* If this is a sign-extension operation that just affects bits
6362          we don't care about, remove it.  Be sure the call above returned
6363          something that is still a shift.  */
6364
6365       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6366           && GET_CODE (XEXP (x, 1)) == CONST_INT
6367           && INTVAL (XEXP (x, 1)) >= 0
6368           && (INTVAL (XEXP (x, 1))
6369               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6370           && GET_CODE (XEXP (x, 0)) == ASHIFT
6371           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6372           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6373         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6374                               reg, next_select);
6375
6376       break;
6377
6378     case ROTATE:
6379     case ROTATERT:
6380       /* If the shift count is constant and we can do computations
6381          in the mode of X, compute where the bits we care about are.
6382          Otherwise, we can't do anything.  Don't change the mode of
6383          the shift or propagate MODE into the shift, though.  */
6384       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6385           && INTVAL (XEXP (x, 1)) >= 0)
6386         {
6387           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6388                                             GET_MODE (x), GEN_INT (mask),
6389                                             XEXP (x, 1));
6390           if (temp && GET_CODE(temp) == CONST_INT)
6391             SUBST (XEXP (x, 0),
6392                    force_to_mode (XEXP (x, 0), GET_MODE (x),
6393                                   INTVAL (temp), reg, next_select));
6394         }
6395       break;
6396
6397     case NEG:
6398       /* If we just want the low-order bit, the NEG isn't needed since it
6399          won't change the low-order bit.    */
6400       if (mask == 1)
6401         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6402
6403       /* We need any bits less significant than the most significant bit in
6404          MASK since carries from those bits will affect the bits we are
6405          interested in.  */
6406       mask = fuller_mask;
6407       goto unop;
6408
6409     case NOT:
6410       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6411          same as the XOR case above.  Ensure that the constant we form is not
6412          wider than the mode of X.  */
6413
6414       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6415           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6416           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6417           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6418               < GET_MODE_BITSIZE (GET_MODE (x)))
6419           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6420         {
6421           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6422           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6423           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6424
6425           return force_to_mode (x, mode, mask, reg, next_select);
6426         }
6427
6428       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6429          use the full mask inside the NOT.  */
6430       mask = fuller_mask;
6431
6432     unop:
6433       op0 = gen_lowpart_for_combine (op_mode,
6434                                      force_to_mode (XEXP (x, 0), mode, mask,
6435                                                     reg, next_select));
6436       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6437         x = gen_unary (code, op_mode, op_mode, op0);
6438       break;
6439
6440     case NE:
6441       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6442          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6443          which is equal to STORE_FLAG_VALUE.  */
6444       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6445           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6446           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6447         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6448
6449       break;
6450
6451     case IF_THEN_ELSE:
6452       /* We have no way of knowing if the IF_THEN_ELSE can itself be
6453          written in a narrower mode.  We play it safe and do not do so.  */
6454
6455       SUBST (XEXP (x, 1),
6456              gen_lowpart_for_combine (GET_MODE (x),
6457                                       force_to_mode (XEXP (x, 1), mode,
6458                                                      mask, reg, next_select)));
6459       SUBST (XEXP (x, 2),
6460              gen_lowpart_for_combine (GET_MODE (x),
6461                                       force_to_mode (XEXP (x, 2), mode,
6462                                                      mask, reg,next_select)));
6463       break;
6464     }
6465
6466   /* Ensure we return a value of the proper mode.  */
6467   return gen_lowpart_for_combine (mode, x);
6468 }
6469 \f
6470 /* Return nonzero if X is an expression that has one of two values depending on
6471    whether some other value is zero or nonzero.  In that case, we return the
6472    value that is being tested, *PTRUE is set to the value if the rtx being
6473    returned has a nonzero value, and *PFALSE is set to the other alternative.
6474
6475    If we return zero, we set *PTRUE and *PFALSE to X.  */
6476
6477 static rtx
6478 if_then_else_cond (x, ptrue, pfalse)
6479      rtx x;
6480      rtx *ptrue, *pfalse;
6481 {
6482   enum machine_mode mode = GET_MODE (x);
6483   enum rtx_code code = GET_CODE (x);
6484   int size = GET_MODE_BITSIZE (mode);
6485   rtx cond0, cond1, true0, true1, false0, false1;
6486   unsigned HOST_WIDE_INT nz;
6487
6488   /* If this is a unary operation whose operand has one of two values, apply
6489      our opcode to compute those values.  */
6490   if (GET_RTX_CLASS (code) == '1'
6491       && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6492     {
6493       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6494       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6495       return cond0;
6496     }
6497
6498   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6499      make can't possibly match and would suppress other optimizations.  */
6500   else if (code == COMPARE)
6501     ;
6502
6503   /* If this is a binary operation, see if either side has only one of two
6504      values.  If either one does or if both do and they are conditional on
6505      the same value, compute the new true and false values.  */
6506   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6507            || GET_RTX_CLASS (code) == '<')
6508     {
6509       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6510       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6511
6512       if ((cond0 != 0 || cond1 != 0)
6513           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6514         {
6515           *ptrue = gen_binary (code, mode, true0, true1);
6516           *pfalse = gen_binary (code, mode, false0, false1);
6517           return cond0 ? cond0 : cond1;
6518         }
6519
6520       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6521          operands is zero when the other is non-zero, and vice-versa,
6522          and STORE_FLAG_VALUE is 1 or -1.  */
6523
6524       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6525           && (code == PLUS || code == IOR || code == XOR || code == MINUS
6526            || code == UMAX)
6527           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6528         {
6529           rtx op0 = XEXP (XEXP (x, 0), 1);
6530           rtx op1 = XEXP (XEXP (x, 1), 1);
6531
6532           cond0 = XEXP (XEXP (x, 0), 0);
6533           cond1 = XEXP (XEXP (x, 1), 0);
6534
6535           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6536               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6537               && reversible_comparison_p (cond1)
6538               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6539                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6540                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6541                   || ((swap_condition (GET_CODE (cond0))
6542                        == reverse_condition (GET_CODE (cond1)))
6543                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6544                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6545               && ! side_effects_p (x))
6546             {
6547               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6548               *pfalse = gen_binary (MULT, mode,
6549                                     (code == MINUS
6550                                      ? gen_unary (NEG, mode, mode, op1) : op1),
6551                                     const_true_rtx);
6552               return cond0;
6553             }
6554         }
6555
6556       /* Similarly for MULT, AND and UMIN, execpt that for these the result
6557          is always zero.  */
6558       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6559           && (code == MULT || code == AND || code == UMIN)
6560           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6561         {
6562           cond0 = XEXP (XEXP (x, 0), 0);
6563           cond1 = XEXP (XEXP (x, 1), 0);
6564
6565           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6566               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6567               && reversible_comparison_p (cond1)
6568               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6569                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6570                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6571                   || ((swap_condition (GET_CODE (cond0))
6572                        == reverse_condition (GET_CODE (cond1)))
6573                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6574                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6575               && ! side_effects_p (x))
6576             {
6577               *ptrue = *pfalse = const0_rtx;
6578               return cond0;
6579             }
6580         }
6581     }
6582
6583   else if (code == IF_THEN_ELSE)
6584     {
6585       /* If we have IF_THEN_ELSE already, extract the condition and
6586          canonicalize it if it is NE or EQ.  */
6587       cond0 = XEXP (x, 0);
6588       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6589       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6590         return XEXP (cond0, 0);
6591       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6592         {
6593           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6594           return XEXP (cond0, 0);
6595         }
6596       else
6597         return cond0;
6598     }
6599
6600   /* If X is a normal SUBREG with both inner and outer modes integral,
6601      we can narrow both the true and false values of the inner expression,
6602      if there is a condition.  */
6603   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6604            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6605            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6606            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6607                                                &true0, &false0)))
6608     {
6609       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6610       *pfalse
6611         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6612
6613       return cond0;
6614     }
6615
6616   /* If X is a constant, this isn't special and will cause confusions
6617      if we treat it as such.  Likewise if it is equivalent to a constant.  */
6618   else if (CONSTANT_P (x)
6619            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6620     ;
6621
6622   /* If X is known to be either 0 or -1, those are the true and
6623      false values when testing X.  */
6624   else if (num_sign_bit_copies (x, mode) == size)
6625     {
6626       *ptrue = constm1_rtx, *pfalse = const0_rtx;
6627       return x;
6628     }
6629
6630   /* Likewise for 0 or a single bit.  */
6631   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6632     {
6633       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6634       return x;
6635     }
6636
6637   /* Otherwise fail; show no condition with true and false values the same.  */
6638   *ptrue = *pfalse = x;
6639   return 0;
6640 }
6641 \f
6642 /* Return the value of expression X given the fact that condition COND
6643    is known to be true when applied to REG as its first operand and VAL
6644    as its second.  X is known to not be shared and so can be modified in
6645    place.
6646
6647    We only handle the simplest cases, and specifically those cases that
6648    arise with IF_THEN_ELSE expressions.  */
6649
6650 static rtx
6651 known_cond (x, cond, reg, val)
6652      rtx x;
6653      enum rtx_code cond;
6654      rtx reg, val;
6655 {
6656   enum rtx_code code = GET_CODE (x);
6657   rtx temp;
6658   char *fmt;
6659   int i, j;
6660
6661   if (side_effects_p (x))
6662     return x;
6663
6664   if (cond == EQ && rtx_equal_p (x, reg))
6665     return val;
6666
6667   /* If X is (abs REG) and we know something about REG's relationship
6668      with zero, we may be able to simplify this.  */
6669
6670   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6671     switch (cond)
6672       {
6673       case GE:  case GT:  case EQ:
6674         return XEXP (x, 0);
6675       case LT:  case LE:
6676         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6677                           XEXP (x, 0));
6678       }
6679
6680   /* The only other cases we handle are MIN, MAX, and comparisons if the
6681      operands are the same as REG and VAL.  */
6682
6683   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6684     {
6685       if (rtx_equal_p (XEXP (x, 0), val))
6686         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6687
6688       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6689         {
6690           if (GET_RTX_CLASS (code) == '<')
6691             return (comparison_dominates_p (cond, code) ? const_true_rtx
6692                     : (comparison_dominates_p (cond,
6693                                                reverse_condition (code))
6694                        ? const0_rtx : x));
6695
6696           else if (code == SMAX || code == SMIN
6697                    || code == UMIN || code == UMAX)
6698             {
6699               int unsignedp = (code == UMIN || code == UMAX);
6700
6701               if (code == SMAX || code == UMAX)
6702                 cond = reverse_condition (cond);
6703
6704               switch (cond)
6705                 {
6706                 case GE:   case GT:
6707                   return unsignedp ? x : XEXP (x, 1);
6708                 case LE:   case LT:
6709                   return unsignedp ? x : XEXP (x, 0);
6710                 case GEU:  case GTU:
6711                   return unsignedp ? XEXP (x, 1) : x;
6712                 case LEU:  case LTU:
6713                   return unsignedp ? XEXP (x, 0) : x;
6714                 }
6715             }
6716         }
6717     }
6718
6719   fmt = GET_RTX_FORMAT (code);
6720   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6721     {
6722       if (fmt[i] == 'e')
6723         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6724       else if (fmt[i] == 'E')
6725         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6726           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6727                                                 cond, reg, val));
6728     }
6729
6730   return x;
6731 }
6732 \f
6733 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6734    assignment as a field assignment.  */
6735
6736 static int
6737 rtx_equal_for_field_assignment_p (x, y)
6738      rtx x;
6739      rtx y;
6740 {
6741   rtx last_x, last_y;
6742
6743   if (x == y || rtx_equal_p (x, y))
6744     return 1;
6745
6746   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6747     return 0;
6748
6749   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6750      Note that all SUBREGs of MEM are paradoxical; otherwise they
6751      would have been rewritten.  */
6752   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6753       && GET_CODE (SUBREG_REG (y)) == MEM
6754       && rtx_equal_p (SUBREG_REG (y),
6755                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6756     return 1;
6757
6758   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6759       && GET_CODE (SUBREG_REG (x)) == MEM
6760       && rtx_equal_p (SUBREG_REG (x),
6761                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6762     return 1;
6763
6764   last_x = get_last_value (x);
6765   last_y = get_last_value (y);
6766
6767   return ((last_x != 0
6768            && GET_CODE (last_x) != CLOBBER
6769            && rtx_equal_for_field_assignment_p (last_x, y))
6770           || (last_y != 0
6771               && GET_CODE (last_y) != CLOBBER
6772               && rtx_equal_for_field_assignment_p (x, last_y))
6773           || (last_x != 0 && last_y != 0
6774               && GET_CODE (last_x) != CLOBBER
6775               && GET_CODE (last_y) != CLOBBER
6776               && rtx_equal_for_field_assignment_p (last_x, last_y)));
6777 }
6778 \f
6779 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6780    Return that assignment if so.
6781
6782    We only handle the most common cases.  */
6783
6784 static rtx
6785 make_field_assignment (x)
6786      rtx x;
6787 {
6788   rtx dest = SET_DEST (x);
6789   rtx src = SET_SRC (x);
6790   rtx assign;
6791   rtx rhs, lhs;
6792   HOST_WIDE_INT c1;
6793   int pos, len;
6794   rtx other;
6795   enum machine_mode mode;
6796
6797   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6798      a clear of a one-bit field.  We will have changed it to
6799      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
6800      for a SUBREG.  */
6801
6802   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6803       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6804       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6805       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6806     {
6807       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6808                                 1, 1, 1, 0);
6809       if (assign != 0)
6810         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6811       return x;
6812     }
6813
6814   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6815            && subreg_lowpart_p (XEXP (src, 0))
6816            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6817                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6818            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6819            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6820            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6821     {
6822       assign = make_extraction (VOIDmode, dest, 0,
6823                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6824                                 1, 1, 1, 0);
6825       if (assign != 0)
6826         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6827       return x;
6828     }
6829
6830   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6831      one-bit field.  */
6832   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6833            && XEXP (XEXP (src, 0), 0) == const1_rtx
6834            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6835     {
6836       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6837                                 1, 1, 1, 0);
6838       if (assign != 0)
6839         return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6840       return x;
6841     }
6842
6843   /* The other case we handle is assignments into a constant-position
6844      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
6845      a mask that has all one bits except for a group of zero bits and
6846      OTHER is known to have zeros where C1 has ones, this is such an
6847      assignment.  Compute the position and length from C1.  Shift OTHER
6848      to the appropriate position, force it to the required mode, and
6849      make the extraction.  Check for the AND in both operands.  */
6850
6851   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6852     return x;
6853
6854   rhs = expand_compound_operation (XEXP (src, 0));
6855   lhs = expand_compound_operation (XEXP (src, 1));
6856
6857   if (GET_CODE (rhs) == AND
6858       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6859       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6860     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6861   else if (GET_CODE (lhs) == AND
6862            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6863            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6864     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6865   else
6866     return x;
6867
6868   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6869   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6870       || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6871           && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6872     return x;
6873
6874   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6875   if (assign == 0)
6876     return x;
6877
6878   /* The mode to use for the source is the mode of the assignment, or of
6879      what is inside a possible STRICT_LOW_PART.  */
6880   mode = (GET_CODE (assign) == STRICT_LOW_PART
6881           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6882
6883   /* Shift OTHER right POS places and make it the source, restricting it
6884      to the proper length and mode.  */
6885
6886   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6887                                              GET_MODE (src), other, pos),
6888                        mode,
6889                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6890                        ? GET_MODE_MASK (mode)
6891                        : ((HOST_WIDE_INT) 1 << len) - 1,
6892                        dest, 0);
6893
6894   return gen_rtx_combine (SET, VOIDmode, assign, src);
6895 }
6896 \f
6897 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6898    if so.  */
6899
6900 static rtx
6901 apply_distributive_law (x)
6902      rtx x;
6903 {
6904   enum rtx_code code = GET_CODE (x);
6905   rtx lhs, rhs, other;
6906   rtx tem;
6907   enum rtx_code inner_code;
6908
6909   /* Distributivity is not true for floating point.
6910      It can change the value.  So don't do it.
6911      -- rms and moshier@world.std.com.  */
6912   if (FLOAT_MODE_P (GET_MODE (x)))
6913     return x;
6914
6915   /* The outer operation can only be one of the following:  */
6916   if (code != IOR && code != AND && code != XOR
6917       && code != PLUS && code != MINUS)
6918     return x;
6919
6920   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6921
6922   /* If either operand is a primitive we can't do anything, so get out
6923      fast.  */
6924   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6925       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6926     return x;
6927
6928   lhs = expand_compound_operation (lhs);
6929   rhs = expand_compound_operation (rhs);
6930   inner_code = GET_CODE (lhs);
6931   if (inner_code != GET_CODE (rhs))
6932     return x;
6933
6934   /* See if the inner and outer operations distribute.  */
6935   switch (inner_code)
6936     {
6937     case LSHIFTRT:
6938     case ASHIFTRT:
6939     case AND:
6940     case IOR:
6941       /* These all distribute except over PLUS.  */
6942       if (code == PLUS || code == MINUS)
6943         return x;
6944       break;
6945
6946     case MULT:
6947       if (code != PLUS && code != MINUS)
6948         return x;
6949       break;
6950
6951     case ASHIFT:
6952       /* This is also a multiply, so it distributes over everything.  */
6953       break;
6954
6955     case SUBREG:
6956       /* Non-paradoxical SUBREGs distributes over all operations, provided
6957          the inner modes and word numbers are the same, this is an extraction
6958          of a low-order part, we don't convert an fp operation to int or
6959          vice versa, and we would not be converting a single-word
6960          operation into a multi-word operation.  The latter test is not
6961          required, but it prevents generating unneeded multi-word operations.
6962          Some of the previous tests are redundant given the latter test, but
6963          are retained because they are required for correctness.
6964
6965          We produce the result slightly differently in this case.  */
6966
6967       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6968           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6969           || ! subreg_lowpart_p (lhs)
6970           || (GET_MODE_CLASS (GET_MODE (lhs))
6971               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6972           || (GET_MODE_SIZE (GET_MODE (lhs))
6973               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6974           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6975         return x;
6976
6977       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6978                         SUBREG_REG (lhs), SUBREG_REG (rhs));
6979       return gen_lowpart_for_combine (GET_MODE (x), tem);
6980
6981     default:
6982       return x;
6983     }
6984
6985   /* Set LHS and RHS to the inner operands (A and B in the example
6986      above) and set OTHER to the common operand (C in the example).
6987      These is only one way to do this unless the inner operation is
6988      commutative.  */
6989   if (GET_RTX_CLASS (inner_code) == 'c'
6990       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6991     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6992   else if (GET_RTX_CLASS (inner_code) == 'c'
6993            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6994     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6995   else if (GET_RTX_CLASS (inner_code) == 'c'
6996            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6997     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6998   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6999     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7000   else
7001     return x;
7002
7003   /* Form the new inner operation, seeing if it simplifies first.  */
7004   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7005
7006   /* There is one exception to the general way of distributing:
7007      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7008   if (code == XOR && inner_code == IOR)
7009     {
7010       inner_code = AND;
7011       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7012     }
7013
7014   /* We may be able to continuing distributing the result, so call
7015      ourselves recursively on the inner operation before forming the
7016      outer operation, which we return.  */
7017   return gen_binary (inner_code, GET_MODE (x),
7018                      apply_distributive_law (tem), other);
7019 }
7020 \f
7021 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7022    in MODE.
7023
7024    Return an equivalent form, if different from X.  Otherwise, return X.  If
7025    X is zero, we are to always construct the equivalent form.  */
7026
7027 static rtx
7028 simplify_and_const_int (x, mode, varop, constop)
7029      rtx x;
7030      enum machine_mode mode;
7031      rtx varop;
7032      unsigned HOST_WIDE_INT constop;
7033 {
7034   unsigned HOST_WIDE_INT nonzero;
7035   int width = GET_MODE_BITSIZE (mode);
7036   int i;
7037
7038   /* Simplify VAROP knowing that we will be only looking at some of the
7039      bits in it.  */
7040   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7041
7042   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7043      CONST_INT, we are done.  */
7044   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7045     return varop;
7046
7047   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7048      a call to nonzero_bits, here we don't care about bits outside
7049      MODE.  */
7050
7051   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7052
7053   /* If this would be an entire word for the target, but is not for
7054      the host, then sign-extend on the host so that the number will look
7055      the same way on the host that it would on the target.
7056
7057      For example, when building a 64 bit alpha hosted 32 bit sparc
7058      targeted compiler, then we want the 32 bit unsigned value -1 to be
7059      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7060      The later confuses the sparc backend.  */
7061
7062   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7063       && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7064     nonzero |= ((HOST_WIDE_INT) (-1) << width);
7065
7066   /* Turn off all bits in the constant that are known to already be zero.
7067      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7068      which is tested below.  */
7069
7070   constop &= nonzero;
7071
7072   /* If we don't have any bits left, return zero.  */
7073   if (constop == 0)
7074     return const0_rtx;
7075
7076   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7077      a power of two, we can replace this with a ASHIFT.  */
7078   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7079       && (i = exact_log2 (constop)) >= 0)
7080     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7081
7082   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7083      or XOR, then try to apply the distributive law.  This may eliminate
7084      operations if either branch can be simplified because of the AND.
7085      It may also make some cases more complex, but those cases probably
7086      won't match a pattern either with or without this.  */
7087
7088   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7089     return
7090       gen_lowpart_for_combine
7091         (mode,
7092          apply_distributive_law
7093          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7094                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7095                                               XEXP (varop, 0), constop),
7096                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7097                                               XEXP (varop, 1), constop))));
7098
7099   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7100      if we already had one (just check for the simplest cases).  */
7101   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7102       && GET_MODE (XEXP (x, 0)) == mode
7103       && SUBREG_REG (XEXP (x, 0)) == varop)
7104     varop = XEXP (x, 0);
7105   else
7106     varop = gen_lowpart_for_combine (mode, varop);
7107
7108   /* If we can't make the SUBREG, try to return what we were given.  */
7109   if (GET_CODE (varop) == CLOBBER)
7110     return x ? x : varop;
7111
7112   /* If we are only masking insignificant bits, return VAROP.  */
7113   if (constop == nonzero)
7114     x = varop;
7115
7116   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7117   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7118     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7119
7120   else
7121     {
7122       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7123           || INTVAL (XEXP (x, 1)) != constop)
7124         SUBST (XEXP (x, 1), GEN_INT (constop));
7125
7126       SUBST (XEXP (x, 0), varop);
7127     }
7128
7129   return x;
7130 }
7131 \f
7132 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7133    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7134    is less useful.  We can't allow both, because that results in exponential
7135    run time recusion.  There is a nullstone testcase that triggered
7136    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7137 #define num_sign_bit_copies()
7138
7139 /* Given an expression, X, compute which bits in X can be non-zero.
7140    We don't care about bits outside of those defined in MODE.
7141
7142    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7143    a shift, AND, or zero_extract, we can do better.  */
7144
7145 static unsigned HOST_WIDE_INT
7146 nonzero_bits (x, mode)
7147      rtx x;
7148      enum machine_mode mode;
7149 {
7150   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7151   unsigned HOST_WIDE_INT inner_nz;
7152   enum rtx_code code;
7153   int mode_width = GET_MODE_BITSIZE (mode);
7154   rtx tem;
7155
7156   /* For floating-point values, assume all bits are needed.  */
7157   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7158     return nonzero;
7159
7160   /* If X is wider than MODE, use its mode instead.  */
7161   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7162     {
7163       mode = GET_MODE (x);
7164       nonzero = GET_MODE_MASK (mode);
7165       mode_width = GET_MODE_BITSIZE (mode);
7166     }
7167
7168   if (mode_width > HOST_BITS_PER_WIDE_INT)
7169     /* Our only callers in this case look for single bit values.  So
7170        just return the mode mask.  Those tests will then be false.  */
7171     return nonzero;
7172
7173 #ifndef WORD_REGISTER_OPERATIONS
7174   /* If MODE is wider than X, but both are a single word for both the host
7175      and target machines, we can compute this from which bits of the
7176      object might be nonzero in its own mode, taking into account the fact
7177      that on many CISC machines, accessing an object in a wider mode
7178      causes the high-order bits to become undefined.  So they are
7179      not known to be zero.  */
7180
7181   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7182       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7183       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7184       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7185     {
7186       nonzero &= nonzero_bits (x, GET_MODE (x));
7187       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7188       return nonzero;
7189     }
7190 #endif
7191
7192   code = GET_CODE (x);
7193   switch (code)
7194     {
7195     case REG:
7196 #ifdef POINTERS_EXTEND_UNSIGNED
7197       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7198          all the bits above ptr_mode are known to be zero.  */
7199       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7200           && REGNO_POINTER_FLAG (REGNO (x)))
7201         nonzero &= GET_MODE_MASK (ptr_mode);
7202 #endif
7203
7204 #ifdef STACK_BOUNDARY
7205       /* If this is the stack pointer, we may know something about its
7206          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7207          stack to be momentarily aligned only to that amount, so we pick
7208          the least alignment.  */
7209
7210       /* We can't check for arg_pointer_rtx here, because it is not
7211          guaranteed to have as much alignment as the stack pointer.
7212          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7213          alignment but the argument pointer has only 64 bit alignment.  */
7214
7215       if (x == stack_pointer_rtx || x == frame_pointer_rtx
7216           || x == hard_frame_pointer_rtx
7217           || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7218               && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7219         {
7220           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7221
7222 #ifdef PUSH_ROUNDING
7223           if (REGNO (x) == STACK_POINTER_REGNUM)
7224             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7225 #endif
7226
7227           /* We must return here, otherwise we may get a worse result from
7228              one of the choices below.  There is nothing useful below as
7229              far as the stack pointer is concerned.  */
7230           return nonzero &= ~ (sp_alignment - 1);
7231         }
7232 #endif
7233
7234       /* If X is a register whose nonzero bits value is current, use it.
7235          Otherwise, if X is a register whose value we can find, use that
7236          value.  Otherwise, use the previously-computed global nonzero bits
7237          for this register.  */
7238
7239       if (reg_last_set_value[REGNO (x)] != 0
7240           && reg_last_set_mode[REGNO (x)] == mode
7241           && (reg_n_sets[REGNO (x)] == 1
7242               || reg_last_set_label[REGNO (x)] == label_tick)
7243           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7244         return reg_last_set_nonzero_bits[REGNO (x)];
7245
7246       tem = get_last_value (x);
7247
7248       if (tem)
7249         {
7250 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7251           /* If X is narrower than MODE and TEM is a non-negative
7252              constant that would appear negative in the mode of X,
7253              sign-extend it for use in reg_nonzero_bits because some
7254              machines (maybe most) will actually do the sign-extension
7255              and this is the conservative approach.
7256
7257              ??? For 2.5, try to tighten up the MD files in this regard
7258              instead of this kludge.  */
7259
7260           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7261               && GET_CODE (tem) == CONST_INT
7262               && INTVAL (tem) > 0
7263               && 0 != (INTVAL (tem)
7264                        & ((HOST_WIDE_INT) 1
7265                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7266             tem = GEN_INT (INTVAL (tem)
7267                            | ((HOST_WIDE_INT) (-1)
7268                               << GET_MODE_BITSIZE (GET_MODE (x))));
7269 #endif
7270           return nonzero_bits (tem, mode);
7271         }
7272       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7273         return reg_nonzero_bits[REGNO (x)] & nonzero;
7274       else
7275         return nonzero;
7276
7277     case CONST_INT:
7278 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7279       /* If X is negative in MODE, sign-extend the value.  */
7280       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7281           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7282         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7283 #endif
7284
7285       return INTVAL (x);
7286
7287     case MEM:
7288 #ifdef LOAD_EXTEND_OP
7289       /* In many, if not most, RISC machines, reading a byte from memory
7290          zeros the rest of the register.  Noticing that fact saves a lot
7291          of extra zero-extends.  */
7292       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7293         nonzero &= GET_MODE_MASK (GET_MODE (x));
7294 #endif
7295       break;
7296
7297     case EQ:  case NE:
7298     case GT:  case GTU:
7299     case LT:  case LTU:
7300     case GE:  case GEU:
7301     case LE:  case LEU:
7302
7303       /* If this produces an integer result, we know which bits are set.
7304          Code here used to clear bits outside the mode of X, but that is
7305          now done above.  */
7306
7307       if (GET_MODE_CLASS (mode) == MODE_INT
7308           && mode_width <= HOST_BITS_PER_WIDE_INT)
7309         nonzero = STORE_FLAG_VALUE;
7310       break;
7311
7312     case NEG:
7313 #if 0
7314       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7315          and num_sign_bit_copies.  */
7316       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7317           == GET_MODE_BITSIZE (GET_MODE (x)))
7318         nonzero = 1;
7319 #endif
7320
7321       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7322         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7323       break;
7324
7325     case ABS:
7326 #if 0
7327       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7328          and num_sign_bit_copies.  */
7329       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7330           == GET_MODE_BITSIZE (GET_MODE (x)))
7331         nonzero = 1;
7332 #endif
7333       break;
7334
7335     case TRUNCATE:
7336       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7337       break;
7338
7339     case ZERO_EXTEND:
7340       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7341       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7342         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7343       break;
7344
7345     case SIGN_EXTEND:
7346       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7347          Otherwise, show all the bits in the outer mode but not the inner
7348          may be non-zero.  */
7349       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7350       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7351         {
7352           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7353           if (inner_nz &
7354               (((HOST_WIDE_INT) 1
7355                 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7356             inner_nz |= (GET_MODE_MASK (mode)
7357                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7358         }
7359
7360       nonzero &= inner_nz;
7361       break;
7362
7363     case AND:
7364       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7365                   & nonzero_bits (XEXP (x, 1), mode));
7366       break;
7367
7368     case XOR:   case IOR:
7369     case UMIN:  case UMAX:  case SMIN:  case SMAX:
7370       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7371                   | nonzero_bits (XEXP (x, 1), mode));
7372       break;
7373
7374     case PLUS:  case MINUS:
7375     case MULT:
7376     case DIV:   case UDIV:
7377     case MOD:   case UMOD:
7378       /* We can apply the rules of arithmetic to compute the number of
7379          high- and low-order zero bits of these operations.  We start by
7380          computing the width (position of the highest-order non-zero bit)
7381          and the number of low-order zero bits for each value.  */
7382       {
7383         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7384         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7385         int width0 = floor_log2 (nz0) + 1;
7386         int width1 = floor_log2 (nz1) + 1;
7387         int low0 = floor_log2 (nz0 & -nz0);
7388         int low1 = floor_log2 (nz1 & -nz1);
7389         HOST_WIDE_INT op0_maybe_minusp
7390           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7391         HOST_WIDE_INT op1_maybe_minusp
7392           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7393         int result_width = mode_width;
7394         int result_low = 0;
7395
7396         switch (code)
7397           {
7398           case PLUS:
7399             result_width = MAX (width0, width1) + 1;
7400             result_low = MIN (low0, low1);
7401             break;
7402           case MINUS:
7403             result_low = MIN (low0, low1);
7404             break;
7405           case MULT:
7406             result_width = width0 + width1;
7407             result_low = low0 + low1;
7408             break;
7409           case DIV:
7410             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7411               result_width = width0;
7412             break;
7413           case UDIV:
7414             result_width = width0;
7415             break;
7416           case MOD:
7417             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7418               result_width = MIN (width0, width1);
7419             result_low = MIN (low0, low1);
7420             break;
7421           case UMOD:
7422             result_width = MIN (width0, width1);
7423             result_low = MIN (low0, low1);
7424             break;
7425           }
7426
7427         if (result_width < mode_width)
7428           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7429
7430         if (result_low > 0)
7431           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7432       }
7433       break;
7434
7435     case ZERO_EXTRACT:
7436       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7437           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7438         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7439       break;
7440
7441     case SUBREG:
7442       /* If this is a SUBREG formed for a promoted variable that has
7443          been zero-extended, we know that at least the high-order bits
7444          are zero, though others might be too.  */
7445
7446       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7447         nonzero = (GET_MODE_MASK (GET_MODE (x))
7448                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7449
7450       /* If the inner mode is a single word for both the host and target
7451          machines, we can compute this from which bits of the inner
7452          object might be nonzero.  */
7453       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7454           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7455               <= HOST_BITS_PER_WIDE_INT))
7456         {
7457           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7458
7459 #ifndef WORD_REGISTER_OPERATIONS
7460           /* On many CISC machines, accessing an object in a wider mode
7461              causes the high-order bits to become undefined.  So they are
7462              not known to be zero.  */
7463           if (GET_MODE_SIZE (GET_MODE (x))
7464               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7465             nonzero |= (GET_MODE_MASK (GET_MODE (x))
7466                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7467 #endif
7468         }
7469       break;
7470
7471     case ASHIFTRT:
7472     case LSHIFTRT:
7473     case ASHIFT:
7474     case ROTATE:
7475       /* The nonzero bits are in two classes: any bits within MODE
7476          that aren't in GET_MODE (x) are always significant.  The rest of the
7477          nonzero bits are those that are significant in the operand of
7478          the shift when shifted the appropriate number of bits.  This
7479          shows that high-order bits are cleared by the right shift and
7480          low-order bits by left shifts.  */
7481       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7482           && INTVAL (XEXP (x, 1)) >= 0
7483           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7484         {
7485           enum machine_mode inner_mode = GET_MODE (x);
7486           int width = GET_MODE_BITSIZE (inner_mode);
7487           int count = INTVAL (XEXP (x, 1));
7488           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7489           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7490           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7491           unsigned HOST_WIDE_INT outer = 0;
7492
7493           if (mode_width > width)
7494             outer = (op_nonzero & nonzero & ~ mode_mask);
7495
7496           if (code == LSHIFTRT)
7497             inner >>= count;
7498           else if (code == ASHIFTRT)
7499             {
7500               inner >>= count;
7501
7502               /* If the sign bit may have been nonzero before the shift, we
7503                  need to mark all the places it could have been copied to
7504                  by the shift as possibly nonzero.  */
7505               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7506                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7507             }
7508           else if (code == ASHIFT)
7509             inner <<= count;
7510           else
7511             inner = ((inner << (count % width)
7512                       | (inner >> (width - (count % width)))) & mode_mask);
7513
7514           nonzero &= (outer | inner);
7515         }
7516       break;
7517
7518     case FFS:
7519       /* This is at most the number of bits in the mode.  */
7520       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7521       break;
7522
7523     case IF_THEN_ELSE:
7524       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7525                   | nonzero_bits (XEXP (x, 2), mode));
7526       break;
7527     }
7528
7529   return nonzero;
7530 }
7531
7532 /* See the macro definition above.  */
7533 #undef num_sign_bit_copies
7534 \f
7535 /* Return the number of bits at the high-order end of X that are known to
7536    be equal to the sign bit.  X will be used in mode MODE; if MODE is
7537    VOIDmode, X will be used in its own mode.  The returned value  will always
7538    be between 1 and the number of bits in MODE.  */
7539
7540 static int
7541 num_sign_bit_copies (x, mode)
7542      rtx x;
7543      enum machine_mode mode;
7544 {
7545   enum rtx_code code = GET_CODE (x);
7546   int bitwidth;
7547   int num0, num1, result;
7548   unsigned HOST_WIDE_INT nonzero;
7549   rtx tem;
7550
7551   /* If we weren't given a mode, use the mode of X.  If the mode is still
7552      VOIDmode, we don't know anything.  Likewise if one of the modes is
7553      floating-point.  */
7554
7555   if (mode == VOIDmode)
7556     mode = GET_MODE (x);
7557
7558   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7559     return 1;
7560
7561   bitwidth = GET_MODE_BITSIZE (mode);
7562
7563   /* For a smaller object, just ignore the high bits.  */
7564   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7565     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7566                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7567
7568 #ifndef WORD_REGISTER_OPERATIONS
7569   /* If this machine does not do all register operations on the entire
7570      register and MODE is wider than the mode of X, we can say nothing
7571      at all about the high-order bits.  */
7572   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7573     return 1;
7574 #endif
7575
7576   switch (code)
7577     {
7578     case REG:
7579
7580 #ifdef POINTERS_EXTEND_UNSIGNED
7581       /* If pointers extend signed and this is a pointer in Pmode, say that
7582          all the bits above ptr_mode are known to be sign bit copies.  */
7583       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7584           && REGNO_POINTER_FLAG (REGNO (x)))
7585         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7586 #endif
7587
7588       if (reg_last_set_value[REGNO (x)] != 0
7589           && reg_last_set_mode[REGNO (x)] == mode
7590           && (reg_n_sets[REGNO (x)] == 1
7591               || reg_last_set_label[REGNO (x)] == label_tick)
7592           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7593         return reg_last_set_sign_bit_copies[REGNO (x)];
7594
7595       tem =  get_last_value (x);
7596       if (tem != 0)
7597         return num_sign_bit_copies (tem, mode);
7598
7599       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7600         return reg_sign_bit_copies[REGNO (x)];
7601       break;
7602
7603     case MEM:
7604 #ifdef LOAD_EXTEND_OP
7605       /* Some RISC machines sign-extend all loads of smaller than a word.  */
7606       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7607         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7608 #endif
7609       break;
7610
7611     case CONST_INT:
7612       /* If the constant is negative, take its 1's complement and remask.
7613          Then see how many zero bits we have.  */
7614       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7615       if (bitwidth <= HOST_BITS_PER_WIDE_INT
7616           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7617         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7618
7619       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7620
7621     case SUBREG:
7622       /* If this is a SUBREG for a promoted object that is sign-extended
7623          and we are looking at it in a wider mode, we know that at least the
7624          high-order bits are known to be sign bit copies.  */
7625
7626       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7627         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7628                     num_sign_bit_copies (SUBREG_REG (x), mode));
7629
7630       /* For a smaller object, just ignore the high bits.  */
7631       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7632         {
7633           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7634           return MAX (1, (num0
7635                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7636                              - bitwidth)));
7637         }
7638
7639 #ifdef WORD_REGISTER_OPERATIONS
7640 #ifdef LOAD_EXTEND_OP
7641       /* For paradoxical SUBREGs on machines where all register operations
7642          affect the entire register, just look inside.  Note that we are
7643          passing MODE to the recursive call, so the number of sign bit copies
7644          will remain relative to that mode, not the inner mode.  */
7645
7646       /* This works only if loads sign extend.  Otherwise, if we get a
7647          reload for the inner part, it may be loaded from the stack, and
7648          then we lose all sign bit copies that existed before the store
7649          to the stack.  */
7650
7651       if ((GET_MODE_SIZE (GET_MODE (x))
7652            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7653           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7654         return num_sign_bit_copies (SUBREG_REG (x), mode);
7655 #endif
7656 #endif
7657       break;
7658
7659     case SIGN_EXTRACT:
7660       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7661         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7662       break;
7663
7664     case SIGN_EXTEND:
7665       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7666               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7667
7668     case TRUNCATE:
7669       /* For a smaller object, just ignore the high bits.  */
7670       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7671       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7672                               - bitwidth)));
7673
7674     case NOT:
7675       return num_sign_bit_copies (XEXP (x, 0), mode);
7676
7677     case ROTATE:       case ROTATERT:
7678       /* If we are rotating left by a number of bits less than the number
7679          of sign bit copies, we can just subtract that amount from the
7680          number.  */
7681       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7682           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7683         {
7684           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7685           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7686                                  : bitwidth - INTVAL (XEXP (x, 1))));
7687         }
7688       break;
7689
7690     case NEG:
7691       /* In general, this subtracts one sign bit copy.  But if the value
7692          is known to be positive, the number of sign bit copies is the
7693          same as that of the input.  Finally, if the input has just one bit
7694          that might be nonzero, all the bits are copies of the sign bit.  */
7695       nonzero = nonzero_bits (XEXP (x, 0), mode);
7696       if (nonzero == 1)
7697         return bitwidth;
7698
7699       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7700       if (num0 > 1
7701           && bitwidth <= HOST_BITS_PER_WIDE_INT
7702           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7703         num0--;
7704
7705       return num0;
7706
7707     case IOR:   case AND:   case XOR:
7708     case SMIN:  case SMAX:  case UMIN:  case UMAX:
7709       /* Logical operations will preserve the number of sign-bit copies.
7710          MIN and MAX operations always return one of the operands.  */
7711       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7712       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7713       return MIN (num0, num1);
7714
7715     case PLUS:  case MINUS:
7716       /* For addition and subtraction, we can have a 1-bit carry.  However,
7717          if we are subtracting 1 from a positive number, there will not
7718          be such a carry.  Furthermore, if the positive number is known to
7719          be 0 or 1, we know the result is either -1 or 0.  */
7720
7721       if (code == PLUS && XEXP (x, 1) == constm1_rtx
7722           && bitwidth <= HOST_BITS_PER_WIDE_INT)
7723         {
7724           nonzero = nonzero_bits (XEXP (x, 0), mode);
7725           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7726             return (nonzero == 1 || nonzero == 0 ? bitwidth
7727                     : bitwidth - floor_log2 (nonzero) - 1);
7728         }
7729
7730       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7731       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7732       return MAX (1, MIN (num0, num1) - 1);
7733
7734     case MULT:
7735       /* The number of bits of the product is the sum of the number of
7736          bits of both terms.  However, unless one of the terms if known
7737          to be positive, we must allow for an additional bit since negating
7738          a negative number can remove one sign bit copy.  */
7739
7740       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7741       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7742
7743       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7744       if (result > 0
7745           && bitwidth <= HOST_BITS_PER_WIDE_INT
7746           && ((nonzero_bits (XEXP (x, 0), mode)
7747                & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7748           && ((nonzero_bits (XEXP (x, 1), mode)
7749               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7750         result--;
7751
7752       return MAX (1, result);
7753
7754     case UDIV:
7755       /* The result must be <= the first operand.  */
7756       return num_sign_bit_copies (XEXP (x, 0), mode);
7757
7758     case UMOD:
7759       /* The result must be <= the scond operand.  */
7760       return num_sign_bit_copies (XEXP (x, 1), mode);
7761
7762     case DIV:
7763       /* Similar to unsigned division, except that we have to worry about
7764          the case where the divisor is negative, in which case we have
7765          to add 1.  */
7766       result = num_sign_bit_copies (XEXP (x, 0), mode);
7767       if (result > 1
7768           && bitwidth <= HOST_BITS_PER_WIDE_INT
7769           && (nonzero_bits (XEXP (x, 1), mode)
7770               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7771         result --;
7772
7773       return result;
7774
7775     case MOD:
7776       result = num_sign_bit_copies (XEXP (x, 1), mode);
7777       if (result > 1
7778           && bitwidth <= HOST_BITS_PER_WIDE_INT
7779           && (nonzero_bits (XEXP (x, 1), mode)
7780               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7781         result --;
7782
7783       return result;
7784
7785     case ASHIFTRT:
7786       /* Shifts by a constant add to the number of bits equal to the
7787          sign bit.  */
7788       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7789       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7790           && INTVAL (XEXP (x, 1)) > 0)
7791         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7792
7793       return num0;
7794
7795     case ASHIFT:
7796       /* Left shifts destroy copies.  */
7797       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7798           || INTVAL (XEXP (x, 1)) < 0
7799           || INTVAL (XEXP (x, 1)) >= bitwidth)
7800         return 1;
7801
7802       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7803       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7804
7805     case IF_THEN_ELSE:
7806       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7807       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7808       return MIN (num0, num1);
7809
7810     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
7811     case GEU: case GTU: case LEU: case LTU:
7812       if (STORE_FLAG_VALUE == -1)
7813         return bitwidth;
7814     }
7815
7816   /* If we haven't been able to figure it out by one of the above rules,
7817      see if some of the high-order bits are known to be zero.  If so,
7818      count those bits and return one less than that amount.  If we can't
7819      safely compute the mask for this mode, always return BITWIDTH.  */
7820
7821   if (bitwidth > HOST_BITS_PER_WIDE_INT)
7822     return 1;
7823
7824   nonzero = nonzero_bits (x, mode);
7825   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7826           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7827 }
7828 \f
7829 /* Return the number of "extended" bits there are in X, when interpreted
7830    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
7831    unsigned quantities, this is the number of high-order zero bits.
7832    For signed quantities, this is the number of copies of the sign bit
7833    minus 1.  In both case, this function returns the number of "spare"
7834    bits.  For example, if two quantities for which this function returns
7835    at least 1 are added, the addition is known not to overflow.
7836
7837    This function will always return 0 unless called during combine, which
7838    implies that it must be called from a define_split.  */
7839
7840 int
7841 extended_count (x, mode, unsignedp)
7842      rtx x;
7843      enum machine_mode mode;
7844      int unsignedp;
7845 {
7846   if (nonzero_sign_valid == 0)
7847     return 0;
7848
7849   return (unsignedp
7850           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7851              && (GET_MODE_BITSIZE (mode) - 1
7852                  - floor_log2 (nonzero_bits (x, mode))))
7853           : num_sign_bit_copies (x, mode) - 1);
7854 }
7855 \f
7856 /* This function is called from `simplify_shift_const' to merge two
7857    outer operations.  Specifically, we have already found that we need
7858    to perform operation *POP0 with constant *PCONST0 at the outermost
7859    position.  We would now like to also perform OP1 with constant CONST1
7860    (with *POP0 being done last).
7861
7862    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7863    the resulting operation.  *PCOMP_P is set to 1 if we would need to
7864    complement the innermost operand, otherwise it is unchanged.
7865
7866    MODE is the mode in which the operation will be done.  No bits outside
7867    the width of this mode matter.  It is assumed that the width of this mode
7868    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7869
7870    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
7871    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
7872    result is simply *PCONST0.
7873
7874    If the resulting operation cannot be expressed as one operation, we
7875    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
7876
7877 static int
7878 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7879      enum rtx_code *pop0;
7880      HOST_WIDE_INT *pconst0;
7881      enum rtx_code op1;
7882      HOST_WIDE_INT const1;
7883      enum machine_mode mode;
7884      int *pcomp_p;
7885 {
7886   enum rtx_code op0 = *pop0;
7887   HOST_WIDE_INT const0 = *pconst0;
7888   int width = GET_MODE_BITSIZE (mode);
7889
7890   const0 &= GET_MODE_MASK (mode);
7891   const1 &= GET_MODE_MASK (mode);
7892
7893   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
7894   if (op0 == AND)
7895     const1 &= const0;
7896
7897   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
7898      if OP0 is SET.  */
7899
7900   if (op1 == NIL || op0 == SET)
7901     return 1;
7902
7903   else if (op0 == NIL)
7904     op0 = op1, const0 = const1;
7905
7906   else if (op0 == op1)
7907     {
7908       switch (op0)
7909         {
7910         case AND:
7911           const0 &= const1;
7912           break;
7913         case IOR:
7914           const0 |= const1;
7915           break;
7916         case XOR:
7917           const0 ^= const1;
7918           break;
7919         case PLUS:
7920           const0 += const1;
7921           break;
7922         case NEG:
7923           op0 = NIL;
7924           break;
7925         }
7926     }
7927
7928   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
7929   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7930     return 0;
7931
7932   /* If the two constants aren't the same, we can't do anything.  The
7933      remaining six cases can all be done.  */
7934   else if (const0 != const1)
7935     return 0;
7936
7937   else
7938     switch (op0)
7939       {
7940       case IOR:
7941         if (op1 == AND)
7942           /* (a & b) | b == b */
7943           op0 = SET;
7944         else /* op1 == XOR */
7945           /* (a ^ b) | b == a | b */
7946           ;
7947         break;
7948
7949       case XOR:
7950         if (op1 == AND)
7951           /* (a & b) ^ b == (~a) & b */
7952           op0 = AND, *pcomp_p = 1;
7953         else /* op1 == IOR */
7954           /* (a | b) ^ b == a & ~b */
7955           op0 = AND, *pconst0 = ~ const0;
7956         break;
7957
7958       case AND:
7959         if (op1 == IOR)
7960           /* (a | b) & b == b */
7961         op0 = SET;
7962         else /* op1 == XOR */
7963           /* (a ^ b) & b) == (~a) & b */
7964           *pcomp_p = 1;
7965         break;
7966       }
7967
7968   /* Check for NO-OP cases.  */
7969   const0 &= GET_MODE_MASK (mode);
7970   if (const0 == 0
7971       && (op0 == IOR || op0 == XOR || op0 == PLUS))
7972     op0 = NIL;
7973   else if (const0 == 0 && op0 == AND)
7974     op0 = SET;
7975   else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7976     op0 = NIL;
7977
7978   /* If this would be an entire word for the target, but is not for
7979      the host, then sign-extend on the host so that the number will look
7980      the same way on the host that it would on the target.
7981
7982      For example, when building a 64 bit alpha hosted 32 bit sparc
7983      targeted compiler, then we want the 32 bit unsigned value -1 to be
7984      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7985      The later confuses the sparc backend.  */
7986
7987   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7988       && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7989     const0 |= ((HOST_WIDE_INT) (-1) << width);
7990
7991   *pop0 = op0;
7992   *pconst0 = const0;
7993
7994   return 1;
7995 }
7996 \f
7997 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
7998    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
7999    that we started with.
8000
8001    The shift is normally computed in the widest mode we find in VAROP, as
8002    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8003    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8004
8005 static rtx
8006 simplify_shift_const (x, code, result_mode, varop, count)
8007      rtx x;
8008      enum rtx_code code;
8009      enum machine_mode result_mode;
8010      rtx varop;
8011      int count;
8012 {
8013   enum rtx_code orig_code = code;
8014   int orig_count = count;
8015   enum machine_mode mode = result_mode;
8016   enum machine_mode shift_mode, tmode;
8017   int mode_words
8018     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8019   /* We form (outer_op (code varop count) (outer_const)).  */
8020   enum rtx_code outer_op = NIL;
8021   HOST_WIDE_INT outer_const = 0;
8022   rtx const_rtx;
8023   int complement_p = 0;
8024   rtx new;
8025
8026   /* If we were given an invalid count, don't do anything except exactly
8027      what was requested.  */
8028
8029   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8030     {
8031       if (x)
8032         return x;
8033
8034       return gen_rtx (code, mode, varop, GEN_INT (count));
8035     }
8036
8037   /* Unless one of the branches of the `if' in this loop does a `continue',
8038      we will `break' the loop after the `if'.  */
8039
8040   while (count != 0)
8041     {
8042       /* If we have an operand of (clobber (const_int 0)), just return that
8043          value.  */
8044       if (GET_CODE (varop) == CLOBBER)
8045         return varop;
8046
8047       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8048          here would cause an infinite loop.  */
8049       if (complement_p)
8050         break;
8051
8052       /* Convert ROTATERT to ROTATE.  */
8053       if (code == ROTATERT)
8054         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8055
8056       /* We need to determine what mode we will do the shift in.  If the
8057          shift is a right shift or a ROTATE, we must always do it in the mode
8058          it was originally done in.  Otherwise, we can do it in MODE, the
8059          widest mode encountered.  */
8060       shift_mode
8061         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8062            ? result_mode : mode);
8063
8064       /* Handle cases where the count is greater than the size of the mode
8065          minus 1.  For ASHIFT, use the size minus one as the count (this can
8066          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8067          take the count modulo the size.  For other shifts, the result is
8068          zero.
8069
8070          Since these shifts are being produced by the compiler by combining
8071          multiple operations, each of which are defined, we know what the
8072          result is supposed to be.  */
8073
8074       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8075         {
8076           if (code == ASHIFTRT)
8077             count = GET_MODE_BITSIZE (shift_mode) - 1;
8078           else if (code == ROTATE || code == ROTATERT)
8079             count %= GET_MODE_BITSIZE (shift_mode);
8080           else
8081             {
8082               /* We can't simply return zero because there may be an
8083                  outer op.  */
8084               varop = const0_rtx;
8085               count = 0;
8086               break;
8087             }
8088         }
8089
8090       /* Negative counts are invalid and should not have been made (a
8091          programmer-specified negative count should have been handled
8092          above).  */
8093       else if (count < 0)
8094         abort ();
8095
8096       /* An arithmetic right shift of a quantity known to be -1 or 0
8097          is a no-op.  */
8098       if (code == ASHIFTRT
8099           && (num_sign_bit_copies (varop, shift_mode)
8100               == GET_MODE_BITSIZE (shift_mode)))
8101         {
8102           count = 0;
8103           break;
8104         }
8105
8106       /* If we are doing an arithmetic right shift and discarding all but
8107          the sign bit copies, this is equivalent to doing a shift by the
8108          bitsize minus one.  Convert it into that shift because it will often
8109          allow other simplifications.  */
8110
8111       if (code == ASHIFTRT
8112           && (count + num_sign_bit_copies (varop, shift_mode)
8113               >= GET_MODE_BITSIZE (shift_mode)))
8114         count = GET_MODE_BITSIZE (shift_mode) - 1;
8115
8116       /* We simplify the tests below and elsewhere by converting
8117          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8118          `make_compound_operation' will convert it to a ASHIFTRT for
8119          those machines (such as Vax) that don't have a LSHIFTRT.  */
8120       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8121           && code == ASHIFTRT
8122           && ((nonzero_bits (varop, shift_mode)
8123                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8124               == 0))
8125         code = LSHIFTRT;
8126
8127       switch (GET_CODE (varop))
8128         {
8129         case SIGN_EXTEND:
8130         case ZERO_EXTEND:
8131         case SIGN_EXTRACT:
8132         case ZERO_EXTRACT:
8133           new = expand_compound_operation (varop);
8134           if (new != varop)
8135             {
8136               varop = new;
8137               continue;
8138             }
8139           break;
8140
8141         case MEM:
8142           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8143              minus the width of a smaller mode, we can do this with a
8144              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8145           if ((code == ASHIFTRT || code == LSHIFTRT)
8146               && ! mode_dependent_address_p (XEXP (varop, 0))
8147               && ! MEM_VOLATILE_P (varop)
8148               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8149                                          MODE_INT, 1)) != BLKmode)
8150             {
8151               if (BYTES_BIG_ENDIAN)
8152                 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8153               else
8154                 new = gen_rtx (MEM, tmode,
8155                                plus_constant (XEXP (varop, 0),
8156                                               count / BITS_PER_UNIT));
8157               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8158               MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8159               MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8160               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8161                                        : ZERO_EXTEND, mode, new);
8162               count = 0;
8163               continue;
8164             }
8165           break;
8166
8167         case USE:
8168           /* Similar to the case above, except that we can only do this if
8169              the resulting mode is the same as that of the underlying
8170              MEM and adjust the address depending on the *bits* endianness
8171              because of the way that bit-field extract insns are defined.  */
8172           if ((code == ASHIFTRT || code == LSHIFTRT)
8173               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8174                                          MODE_INT, 1)) != BLKmode
8175               && tmode == GET_MODE (XEXP (varop, 0)))
8176             {
8177               if (BITS_BIG_ENDIAN)
8178                 new = XEXP (varop, 0);
8179               else
8180                 {
8181                   new = copy_rtx (XEXP (varop, 0));
8182                   SUBST (XEXP (new, 0),
8183                          plus_constant (XEXP (new, 0),
8184                                         count / BITS_PER_UNIT));
8185                 }
8186
8187               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8188                                        : ZERO_EXTEND, mode, new);
8189               count = 0;
8190               continue;
8191             }
8192           break;
8193
8194         case SUBREG:
8195           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8196              the same number of words as what we've seen so far.  Then store
8197              the widest mode in MODE.  */
8198           if (subreg_lowpart_p (varop)
8199               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8200                   > GET_MODE_SIZE (GET_MODE (varop)))
8201               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8202                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8203                   == mode_words))
8204             {
8205               varop = SUBREG_REG (varop);
8206               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8207                 mode = GET_MODE (varop);
8208               continue;
8209             }
8210           break;
8211
8212         case MULT:
8213           /* Some machines use MULT instead of ASHIFT because MULT
8214              is cheaper.  But it is still better on those machines to
8215              merge two shifts into one.  */
8216           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8217               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8218             {
8219               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8220                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8221               continue;
8222             }
8223           break;
8224
8225         case UDIV:
8226           /* Similar, for when divides are cheaper.  */
8227           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8228               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8229             {
8230               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8231                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8232               continue;
8233             }
8234           break;
8235
8236         case ASHIFTRT:
8237           /* If we are extracting just the sign bit of an arithmetic right
8238              shift, that shift is not needed.  */
8239           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8240             {
8241               varop = XEXP (varop, 0);
8242               continue;
8243             }
8244
8245           /* ... fall through ...  */
8246
8247         case LSHIFTRT:
8248         case ASHIFT:
8249         case ROTATE:
8250           /* Here we have two nested shifts.  The result is usually the
8251              AND of a new shift with a mask.  We compute the result below.  */
8252           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8253               && INTVAL (XEXP (varop, 1)) >= 0
8254               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8255               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8256               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8257             {
8258               enum rtx_code first_code = GET_CODE (varop);
8259               int first_count = INTVAL (XEXP (varop, 1));
8260               unsigned HOST_WIDE_INT mask;
8261               rtx mask_rtx;
8262
8263               /* We have one common special case.  We can't do any merging if
8264                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8265                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8266                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8267                  we can convert it to
8268                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8269                  This simplifies certain SIGN_EXTEND operations.  */
8270               if (code == ASHIFT && first_code == ASHIFTRT
8271                   && (GET_MODE_BITSIZE (result_mode)
8272                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8273                 {
8274                   /* C3 has the low-order C1 bits zero.  */
8275
8276                   mask = (GET_MODE_MASK (mode)
8277                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8278
8279                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8280                                                   XEXP (varop, 0), mask);
8281                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8282                                                 varop, count);
8283                   count = first_count;
8284                   code = ASHIFTRT;
8285                   continue;
8286                 }
8287
8288               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8289                  than C1 high-order bits equal to the sign bit, we can convert
8290                  this to either an ASHIFT or a ASHIFTRT depending on the
8291                  two counts.
8292
8293                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8294
8295               if (code == ASHIFTRT && first_code == ASHIFT
8296                   && GET_MODE (varop) == shift_mode
8297                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8298                       > first_count))
8299                 {
8300                   count -= first_count;
8301                   if (count < 0)
8302                     count = - count, code = ASHIFT;
8303                   varop = XEXP (varop, 0);
8304                   continue;
8305                 }
8306
8307               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8308                  we can only do this if FIRST_CODE is also ASHIFTRT.
8309
8310                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8311                  ASHIFTRT.
8312
8313                  If the mode of this shift is not the mode of the outer shift,
8314                  we can't do this if either shift is a right shift or ROTATE.
8315
8316                  Finally, we can't do any of these if the mode is too wide
8317                  unless the codes are the same.
8318
8319                  Handle the case where the shift codes are the same
8320                  first.  */
8321
8322               if (code == first_code)
8323                 {
8324                   if (GET_MODE (varop) != result_mode
8325                       && (code == ASHIFTRT || code == LSHIFTRT
8326                           || code == ROTATE))
8327                     break;
8328
8329                   count += first_count;
8330                   varop = XEXP (varop, 0);
8331                   continue;
8332                 }
8333
8334               if (code == ASHIFTRT
8335                   || (code == ROTATE && first_code == ASHIFTRT)
8336                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8337                   || (GET_MODE (varop) != result_mode
8338                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8339                           || first_code == ROTATE
8340                           || code == ROTATE)))
8341                 break;
8342
8343               /* To compute the mask to apply after the shift, shift the
8344                  nonzero bits of the inner shift the same way the
8345                  outer shift will.  */
8346
8347               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8348
8349               mask_rtx
8350                 = simplify_binary_operation (code, result_mode, mask_rtx,
8351                                              GEN_INT (count));
8352
8353               /* Give up if we can't compute an outer operation to use.  */
8354               if (mask_rtx == 0
8355                   || GET_CODE (mask_rtx) != CONST_INT
8356                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8357                                         INTVAL (mask_rtx),
8358                                         result_mode, &complement_p))
8359                 break;
8360
8361               /* If the shifts are in the same direction, we add the
8362                  counts.  Otherwise, we subtract them.  */
8363               if ((code == ASHIFTRT || code == LSHIFTRT)
8364                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8365                 count += first_count;
8366               else
8367                 count -= first_count;
8368
8369               /* If COUNT is positive, the new shift is usually CODE,
8370                  except for the two exceptions below, in which case it is
8371                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8372                  always be used  */
8373               if (count > 0
8374                   && ((first_code == ROTATE && code == ASHIFT)
8375                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8376                 code = first_code;
8377               else if (count < 0)
8378                 code = first_code, count = - count;
8379
8380               varop = XEXP (varop, 0);
8381               continue;
8382             }
8383
8384           /* If we have (A << B << C) for any shift, we can convert this to
8385              (A << C << B).  This wins if A is a constant.  Only try this if
8386              B is not a constant.  */
8387
8388           else if (GET_CODE (varop) == code
8389                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
8390                    && 0 != (new
8391                             = simplify_binary_operation (code, mode,
8392                                                          XEXP (varop, 0),
8393                                                          GEN_INT (count))))
8394             {
8395               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8396               count = 0;
8397               continue;
8398             }
8399           break;
8400
8401         case NOT:
8402           /* Make this fit the case below.  */
8403           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8404                                    GEN_INT (GET_MODE_MASK (mode)));
8405           continue;
8406
8407         case IOR:
8408         case AND:
8409         case XOR:
8410           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8411              with C the size of VAROP - 1 and the shift is logical if
8412              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8413              we have an (le X 0) operation.   If we have an arithmetic shift
8414              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8415              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8416
8417           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8418               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8419               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8420               && (code == LSHIFTRT || code == ASHIFTRT)
8421               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8422               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8423             {
8424               count = 0;
8425               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8426                                        const0_rtx);
8427
8428               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8429                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8430
8431               continue;
8432             }
8433
8434           /* If we have (shift (logical)), move the logical to the outside
8435              to allow it to possibly combine with another logical and the
8436              shift to combine with another shift.  This also canonicalizes to
8437              what a ZERO_EXTRACT looks like.  Also, some machines have
8438              (and (shift)) insns.  */
8439
8440           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8441               && (new = simplify_binary_operation (code, result_mode,
8442                                                    XEXP (varop, 1),
8443                                                    GEN_INT (count))) != 0
8444               && GET_CODE(new) == CONST_INT
8445               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8446                                   INTVAL (new), result_mode, &complement_p))
8447             {
8448               varop = XEXP (varop, 0);
8449               continue;
8450             }
8451
8452           /* If we can't do that, try to simplify the shift in each arm of the
8453              logical expression, make a new logical expression, and apply
8454              the inverse distributive law.  */
8455           {
8456             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8457                                             XEXP (varop, 0), count);
8458             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8459                                             XEXP (varop, 1), count);
8460
8461             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8462             varop = apply_distributive_law (varop);
8463
8464             count = 0;
8465           }
8466           break;
8467
8468         case EQ:
8469           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8470              says that the sign bit can be tested, FOO has mode MODE, C is
8471              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8472              that may be nonzero.  */
8473           if (code == LSHIFTRT
8474               && XEXP (varop, 1) == const0_rtx
8475               && GET_MODE (XEXP (varop, 0)) == result_mode
8476               && count == GET_MODE_BITSIZE (result_mode) - 1
8477               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8478               && ((STORE_FLAG_VALUE
8479                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8480               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8481               && merge_outer_ops (&outer_op, &outer_const, XOR,
8482                                   (HOST_WIDE_INT) 1, result_mode,
8483                                   &complement_p))
8484             {
8485               varop = XEXP (varop, 0);
8486               count = 0;
8487               continue;
8488             }
8489           break;
8490
8491         case NEG:
8492           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8493              than the number of bits in the mode is equivalent to A.  */
8494           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8495               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8496             {
8497               varop = XEXP (varop, 0);
8498               count = 0;
8499               continue;
8500             }
8501
8502           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8503              NEG outside to allow shifts to combine.  */
8504           if (code == ASHIFT
8505               && merge_outer_ops (&outer_op, &outer_const, NEG,
8506                                   (HOST_WIDE_INT) 0, result_mode,
8507                                   &complement_p))
8508             {
8509               varop = XEXP (varop, 0);
8510               continue;
8511             }
8512           break;
8513
8514         case PLUS:
8515           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8516              is one less than the number of bits in the mode is
8517              equivalent to (xor A 1).  */
8518           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8519               && XEXP (varop, 1) == constm1_rtx
8520               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8521               && merge_outer_ops (&outer_op, &outer_const, XOR,
8522                                   (HOST_WIDE_INT) 1, result_mode,
8523                                   &complement_p))
8524             {
8525               count = 0;
8526               varop = XEXP (varop, 0);
8527               continue;
8528             }
8529
8530           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8531              that might be nonzero in BAR are those being shifted out and those
8532              bits are known zero in FOO, we can replace the PLUS with FOO.
8533              Similarly in the other operand order.  This code occurs when
8534              we are computing the size of a variable-size array.  */
8535
8536           if ((code == ASHIFTRT || code == LSHIFTRT)
8537               && count < HOST_BITS_PER_WIDE_INT
8538               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8539               && (nonzero_bits (XEXP (varop, 1), result_mode)
8540                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8541             {
8542               varop = XEXP (varop, 0);
8543               continue;
8544             }
8545           else if ((code == ASHIFTRT || code == LSHIFTRT)
8546                    && count < HOST_BITS_PER_WIDE_INT
8547                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8548                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8549                             >> count)
8550                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8551                             & nonzero_bits (XEXP (varop, 1),
8552                                                  result_mode)))
8553             {
8554               varop = XEXP (varop, 1);
8555               continue;
8556             }
8557
8558           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
8559           if (code == ASHIFT
8560               && GET_CODE (XEXP (varop, 1)) == CONST_INT
8561               && (new = simplify_binary_operation (ASHIFT, result_mode,
8562                                                    XEXP (varop, 1),
8563                                                    GEN_INT (count))) != 0
8564               && GET_CODE(new) == CONST_INT
8565               && merge_outer_ops (&outer_op, &outer_const, PLUS,
8566                                   INTVAL (new), result_mode, &complement_p))
8567             {
8568               varop = XEXP (varop, 0);
8569               continue;
8570             }
8571           break;
8572
8573         case MINUS:
8574           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8575              with C the size of VAROP - 1 and the shift is logical if
8576              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8577              we have a (gt X 0) operation.  If the shift is arithmetic with
8578              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8579              we have a (neg (gt X 0)) operation.  */
8580
8581           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8582               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8583               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8584               && (code == LSHIFTRT || code == ASHIFTRT)
8585               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8586               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8587               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8588             {
8589               count = 0;
8590               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8591                                        const0_rtx);
8592
8593               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8594                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8595
8596               continue;
8597             }
8598           break;
8599         }
8600
8601       break;
8602     }
8603
8604   /* We need to determine what mode to do the shift in.  If the shift is
8605      a right shift or ROTATE, we must always do it in the mode it was
8606      originally done in.  Otherwise, we can do it in MODE, the widest mode
8607      encountered.  The code we care about is that of the shift that will
8608      actually be done, not the shift that was originally requested.  */
8609   shift_mode
8610     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8611        ? result_mode : mode);
8612
8613   /* We have now finished analyzing the shift.  The result should be
8614      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
8615      OUTER_OP is non-NIL, it is an operation that needs to be applied
8616      to the result of the shift.  OUTER_CONST is the relevant constant,
8617      but we must turn off all bits turned off in the shift.
8618
8619      If we were passed a value for X, see if we can use any pieces of
8620      it.  If not, make new rtx.  */
8621
8622   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8623       && GET_CODE (XEXP (x, 1)) == CONST_INT
8624       && INTVAL (XEXP (x, 1)) == count)
8625     const_rtx = XEXP (x, 1);
8626   else
8627     const_rtx = GEN_INT (count);
8628
8629   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8630       && GET_MODE (XEXP (x, 0)) == shift_mode
8631       && SUBREG_REG (XEXP (x, 0)) == varop)
8632     varop = XEXP (x, 0);
8633   else if (GET_MODE (varop) != shift_mode)
8634     varop = gen_lowpart_for_combine (shift_mode, varop);
8635
8636   /* If we can't make the SUBREG, try to return what we were given.  */
8637   if (GET_CODE (varop) == CLOBBER)
8638     return x ? x : varop;
8639
8640   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8641   if (new != 0)
8642     x = new;
8643   else
8644     {
8645       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8646         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8647
8648       SUBST (XEXP (x, 0), varop);
8649       SUBST (XEXP (x, 1), const_rtx);
8650     }
8651
8652   /* If we have an outer operation and we just made a shift, it is
8653      possible that we could have simplified the shift were it not
8654      for the outer operation.  So try to do the simplification
8655      recursively.  */
8656
8657   if (outer_op != NIL && GET_CODE (x) == code
8658       && GET_CODE (XEXP (x, 1)) == CONST_INT)
8659     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8660                               INTVAL (XEXP (x, 1)));
8661
8662   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8663      turn off all the bits that the shift would have turned off.  */
8664   if (orig_code == LSHIFTRT && result_mode != shift_mode)
8665     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8666                                 GET_MODE_MASK (result_mode) >> orig_count);
8667
8668   /* Do the remainder of the processing in RESULT_MODE.  */
8669   x = gen_lowpart_for_combine (result_mode, x);
8670
8671   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8672      operation.  */
8673   if (complement_p)
8674     x = gen_unary (NOT, result_mode, result_mode, x);
8675
8676   if (outer_op != NIL)
8677     {
8678       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8679         {
8680           int width = GET_MODE_BITSIZE (result_mode);
8681
8682           outer_const &= GET_MODE_MASK (result_mode);
8683
8684           /* If this would be an entire word for the target, but is not for
8685              the host, then sign-extend on the host so that the number will
8686              look the same way on the host that it would on the target.
8687
8688              For example, when building a 64 bit alpha hosted 32 bit sparc
8689              targeted compiler, then we want the 32 bit unsigned value -1 to be
8690              represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8691              The later confuses the sparc backend.  */
8692
8693           if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8694               && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8695             outer_const |= ((HOST_WIDE_INT) (-1) << width);
8696         }
8697
8698       if (outer_op == AND)
8699         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8700       else if (outer_op == SET)
8701         /* This means that we have determined that the result is
8702            equivalent to a constant.  This should be rare.  */
8703         x = GEN_INT (outer_const);
8704       else if (GET_RTX_CLASS (outer_op) == '1')
8705         x = gen_unary (outer_op, result_mode, result_mode, x);
8706       else
8707         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8708     }
8709
8710   return x;
8711 }
8712 \f
8713 /* Like recog, but we receive the address of a pointer to a new pattern.
8714    We try to match the rtx that the pointer points to.
8715    If that fails, we may try to modify or replace the pattern,
8716    storing the replacement into the same pointer object.
8717
8718    Modifications include deletion or addition of CLOBBERs.
8719
8720    PNOTES is a pointer to a location where any REG_UNUSED notes added for
8721    the CLOBBERs are placed.
8722
8723    PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8724    we had to add.
8725
8726    The value is the final insn code from the pattern ultimately matched,
8727    or -1.  */
8728
8729 static int
8730 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8731      rtx *pnewpat;
8732      rtx insn;
8733      rtx *pnotes;
8734      int *padded_scratches;
8735 {
8736   register rtx pat = *pnewpat;
8737   int insn_code_number;
8738   int num_clobbers_to_add = 0;
8739   int i;
8740   rtx notes = 0;
8741
8742   *padded_scratches = 0;
8743
8744   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8745      we use to indicate that something didn't match.  If we find such a
8746      thing, force rejection.  */
8747   if (GET_CODE (pat) == PARALLEL)
8748     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8749       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8750           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8751         return -1;
8752
8753   /* Is the result of combination a valid instruction?  */
8754   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8755
8756   /* If it isn't, there is the possibility that we previously had an insn
8757      that clobbered some register as a side effect, but the combined
8758      insn doesn't need to do that.  So try once more without the clobbers
8759      unless this represents an ASM insn.  */
8760
8761   if (insn_code_number < 0 && ! check_asm_operands (pat)
8762       && GET_CODE (pat) == PARALLEL)
8763     {
8764       int pos;
8765
8766       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8767         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8768           {
8769             if (i != pos)
8770               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8771             pos++;
8772           }
8773
8774       SUBST_INT (XVECLEN (pat, 0), pos);
8775
8776       if (pos == 1)
8777         pat = XVECEXP (pat, 0, 0);
8778
8779       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8780     }
8781
8782   /* If we had any clobbers to add, make a new pattern than contains
8783      them.  Then check to make sure that all of them are dead.  */
8784   if (num_clobbers_to_add)
8785     {
8786       rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8787                             gen_rtvec (GET_CODE (pat) == PARALLEL
8788                                        ? XVECLEN (pat, 0) + num_clobbers_to_add
8789                                        : num_clobbers_to_add + 1));
8790
8791       if (GET_CODE (pat) == PARALLEL)
8792         for (i = 0; i < XVECLEN (pat, 0); i++)
8793           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8794       else
8795         XVECEXP (newpat, 0, 0) = pat;
8796
8797       add_clobbers (newpat, insn_code_number);
8798
8799       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8800            i < XVECLEN (newpat, 0); i++)
8801         {
8802           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8803               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8804             return -1;
8805           else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8806             (*padded_scratches)++;
8807           notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8808                            XEXP (XVECEXP (newpat, 0, i), 0), notes);
8809         }
8810       pat = newpat;
8811     }
8812
8813   *pnewpat = pat;
8814   *pnotes = notes;
8815
8816   return insn_code_number;
8817 }
8818 \f
8819 /* Like gen_lowpart but for use by combine.  In combine it is not possible
8820    to create any new pseudoregs.  However, it is safe to create
8821    invalid memory addresses, because combine will try to recognize
8822    them and all they will do is make the combine attempt fail.
8823
8824    If for some reason this cannot do its job, an rtx
8825    (clobber (const_int 0)) is returned.
8826    An insn containing that will not be recognized.  */
8827
8828 #undef gen_lowpart
8829
8830 static rtx
8831 gen_lowpart_for_combine (mode, x)
8832      enum machine_mode mode;
8833      register rtx x;
8834 {
8835   rtx result;
8836
8837   if (GET_MODE (x) == mode)
8838     return x;
8839
8840   /* We can only support MODE being wider than a word if X is a
8841      constant integer or has a mode the same size.  */
8842
8843   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8844       && ! ((GET_MODE (x) == VOIDmode
8845              && (GET_CODE (x) == CONST_INT
8846                  || GET_CODE (x) == CONST_DOUBLE))
8847             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8848     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8849
8850   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
8851      won't know what to do.  So we will strip off the SUBREG here and
8852      process normally.  */
8853   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8854     {
8855       x = SUBREG_REG (x);
8856       if (GET_MODE (x) == mode)
8857         return x;
8858     }
8859
8860   result = gen_lowpart_common (mode, x);
8861   if (result != 0
8862       && GET_CODE (result) == SUBREG
8863       && GET_CODE (SUBREG_REG (result)) == REG
8864       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8865       && (GET_MODE_SIZE (GET_MODE (result))
8866           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8867     reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
8868
8869   if (result)
8870     return result;
8871
8872   if (GET_CODE (x) == MEM)
8873     {
8874       register int offset = 0;
8875       rtx new;
8876
8877       /* Refuse to work on a volatile memory ref or one with a mode-dependent
8878          address.  */
8879       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8880         return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8881
8882       /* If we want to refer to something bigger than the original memref,
8883          generate a perverse subreg instead.  That will force a reload
8884          of the original memref X.  */
8885       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8886         return gen_rtx (SUBREG, mode, x, 0);
8887
8888       if (WORDS_BIG_ENDIAN)
8889         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8890                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8891       if (BYTES_BIG_ENDIAN)
8892         {
8893           /* Adjust the address so that the address-after-the-data is
8894              unchanged.  */
8895           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8896                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8897         }
8898       new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8899       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8900       MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8901       MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8902       return new;
8903     }
8904
8905   /* If X is a comparison operator, rewrite it in a new mode.  This
8906      probably won't match, but may allow further simplifications.  */
8907   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8908     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8909
8910   /* If we couldn't simplify X any other way, just enclose it in a
8911      SUBREG.  Normally, this SUBREG won't match, but some patterns may
8912      include an explicit SUBREG or we may simplify it further in combine.  */
8913   else
8914     {
8915       int word = 0;
8916
8917       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8918         word = ((GET_MODE_SIZE (GET_MODE (x))
8919                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8920                 / UNITS_PER_WORD);
8921       return gen_rtx (SUBREG, mode, x, word);
8922     }
8923 }
8924 \f
8925 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
8926    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8927
8928    If the identical expression was previously in the insn (in the undobuf),
8929    it will be returned.  Only if it is not found will a new expression
8930    be made.  */
8931
8932 /*VARARGS2*/
8933 static rtx
8934 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8935 {
8936 #ifndef __STDC__
8937   enum rtx_code code;
8938   enum machine_mode mode;
8939 #endif
8940   va_list p;
8941   int n_args;
8942   rtx args[3];
8943   int i, j;
8944   char *fmt;
8945   rtx rt;
8946   struct undo *undo;
8947
8948   VA_START (p, mode);
8949
8950 #ifndef __STDC__
8951   code = va_arg (p, enum rtx_code);
8952   mode = va_arg (p, enum machine_mode);
8953 #endif
8954
8955   n_args = GET_RTX_LENGTH (code);
8956   fmt = GET_RTX_FORMAT (code);
8957
8958   if (n_args == 0 || n_args > 3)
8959     abort ();
8960
8961   /* Get each arg and verify that it is supposed to be an expression.  */
8962   for (j = 0; j < n_args; j++)
8963     {
8964       if (*fmt++ != 'e')
8965         abort ();
8966
8967       args[j] = va_arg (p, rtx);
8968     }
8969
8970   /* See if this is in undobuf.  Be sure we don't use objects that came
8971      from another insn; this could produce circular rtl structures.  */
8972
8973   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8974     if (!undo->is_int
8975         && GET_CODE (undo->old_contents.r) == code
8976         && GET_MODE (undo->old_contents.r) == mode)
8977       {
8978         for (j = 0; j < n_args; j++)
8979           if (XEXP (undo->old_contents.r, j) != args[j])
8980             break;
8981
8982         if (j == n_args)
8983           return undo->old_contents.r;
8984       }
8985
8986   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
8987      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
8988   rt = rtx_alloc (code);
8989   PUT_MODE (rt, mode);
8990   XEXP (rt, 0) = args[0];
8991   if (n_args > 1)
8992     {
8993       XEXP (rt, 1) = args[1];
8994       if (n_args > 2)
8995         XEXP (rt, 2) = args[2];
8996     }
8997   return rt;
8998 }
8999
9000 /* These routines make binary and unary operations by first seeing if they
9001    fold; if not, a new expression is allocated.  */
9002
9003 static rtx
9004 gen_binary (code, mode, op0, op1)
9005      enum rtx_code code;
9006      enum machine_mode mode;
9007      rtx op0, op1;
9008 {
9009   rtx result;
9010   rtx tem;
9011
9012   if (GET_RTX_CLASS (code) == 'c'
9013       && (GET_CODE (op0) == CONST_INT
9014           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9015     tem = op0, op0 = op1, op1 = tem;
9016
9017   if (GET_RTX_CLASS (code) == '<')
9018     {
9019       enum machine_mode op_mode = GET_MODE (op0);
9020
9021       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9022          just (REL_OP X Y).  */
9023       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9024         {
9025           op1 = XEXP (op0, 1);
9026           op0 = XEXP (op0, 0);
9027           op_mode = GET_MODE (op0);
9028         }
9029
9030       if (op_mode == VOIDmode)
9031         op_mode = GET_MODE (op1);
9032       result = simplify_relational_operation (code, op_mode, op0, op1);
9033     }
9034   else
9035     result = simplify_binary_operation (code, mode, op0, op1);
9036
9037   if (result)
9038     return result;
9039
9040   /* Put complex operands first and constants second.  */
9041   if (GET_RTX_CLASS (code) == 'c'
9042       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9043           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9044               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9045           || (GET_CODE (op0) == SUBREG
9046               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9047               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9048     return gen_rtx_combine (code, mode, op1, op0);
9049
9050   return gen_rtx_combine (code, mode, op0, op1);
9051 }
9052
9053 static rtx
9054 gen_unary (code, mode, op0_mode, op0)
9055      enum rtx_code code;
9056      enum machine_mode mode, op0_mode;
9057      rtx op0;
9058 {
9059   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9060
9061   if (result)
9062     return result;
9063
9064   return gen_rtx_combine (code, mode, op0);
9065 }
9066 \f
9067 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9068    comparison code that will be tested.
9069
9070    The result is a possibly different comparison code to use.  *POP0 and
9071    *POP1 may be updated.
9072
9073    It is possible that we might detect that a comparison is either always
9074    true or always false.  However, we do not perform general constant
9075    folding in combine, so this knowledge isn't useful.  Such tautologies
9076    should have been detected earlier.  Hence we ignore all such cases.  */
9077
9078 static enum rtx_code
9079 simplify_comparison (code, pop0, pop1)
9080      enum rtx_code code;
9081      rtx *pop0;
9082      rtx *pop1;
9083 {
9084   rtx op0 = *pop0;
9085   rtx op1 = *pop1;
9086   rtx tem, tem1;
9087   int i;
9088   enum machine_mode mode, tmode;
9089
9090   /* Try a few ways of applying the same transformation to both operands.  */
9091   while (1)
9092     {
9093 #ifndef WORD_REGISTER_OPERATIONS
9094       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9095          so check specially.  */
9096       if (code != GTU && code != GEU && code != LTU && code != LEU
9097           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9098           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9099           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9100           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9101           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9102           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9103               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9104           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9105           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9106           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9107           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9108           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9109           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9110           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9111           && (INTVAL (XEXP (op0, 1))
9112               == (GET_MODE_BITSIZE (GET_MODE (op0))
9113                   - (GET_MODE_BITSIZE
9114                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9115         {
9116           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9117           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9118         }
9119 #endif
9120
9121       /* If both operands are the same constant shift, see if we can ignore the
9122          shift.  We can if the shift is a rotate or if the bits shifted out of
9123          this shift are known to be zero for both inputs and if the type of
9124          comparison is compatible with the shift.  */
9125       if (GET_CODE (op0) == GET_CODE (op1)
9126           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9127           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9128               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9129                   && (code != GT && code != LT && code != GE && code != LE))
9130               || (GET_CODE (op0) == ASHIFTRT
9131                   && (code != GTU && code != LTU
9132                       && code != GEU && code != GEU)))
9133           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9134           && INTVAL (XEXP (op0, 1)) >= 0
9135           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9136           && XEXP (op0, 1) == XEXP (op1, 1))
9137         {
9138           enum machine_mode mode = GET_MODE (op0);
9139           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9140           int shift_count = INTVAL (XEXP (op0, 1));
9141
9142           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9143             mask &= (mask >> shift_count) << shift_count;
9144           else if (GET_CODE (op0) == ASHIFT)
9145             mask = (mask & (mask << shift_count)) >> shift_count;
9146
9147           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9148               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9149             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9150           else
9151             break;
9152         }
9153
9154       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9155          SUBREGs are of the same mode, and, in both cases, the AND would
9156          be redundant if the comparison was done in the narrower mode,
9157          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9158          and the operand's possibly nonzero bits are 0xffffff01; in that case
9159          if we only care about QImode, we don't need the AND).  This case
9160          occurs if the output mode of an scc insn is not SImode and
9161          STORE_FLAG_VALUE == 1 (e.g., the 386).
9162
9163          Similarly, check for a case where the AND's are ZERO_EXTEND
9164          operations from some narrower mode even though a SUBREG is not
9165          present.  */
9166
9167       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9168                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9169                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9170         {
9171           rtx inner_op0 = XEXP (op0, 0);
9172           rtx inner_op1 = XEXP (op1, 0);
9173           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9174           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9175           int changed = 0;
9176
9177           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9178               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9179                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9180               && (GET_MODE (SUBREG_REG (inner_op0))
9181                   == GET_MODE (SUBREG_REG (inner_op1)))
9182               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9183                   <= HOST_BITS_PER_WIDE_INT)
9184               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9185                                              GET_MODE (SUBREG_REG (op0)))))
9186               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9187                                              GET_MODE (SUBREG_REG (inner_op1))))))
9188             {
9189               op0 = SUBREG_REG (inner_op0);
9190               op1 = SUBREG_REG (inner_op1);
9191
9192               /* The resulting comparison is always unsigned since we masked
9193                  off the original sign bit.  */
9194               code = unsigned_condition (code);
9195
9196               changed = 1;
9197             }
9198
9199           else if (c0 == c1)
9200             for (tmode = GET_CLASS_NARROWEST_MODE
9201                  (GET_MODE_CLASS (GET_MODE (op0)));
9202                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9203               if (c0 == GET_MODE_MASK (tmode))
9204                 {
9205                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9206                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9207                   code = unsigned_condition (code);
9208                   changed = 1;
9209                   break;
9210                 }
9211
9212           if (! changed)
9213             break;
9214         }
9215
9216       /* If both operands are NOT, we can strip off the outer operation
9217          and adjust the comparison code for swapped operands; similarly for
9218          NEG, except that this must be an equality comparison.  */
9219       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9220                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9221                    && (code == EQ || code == NE)))
9222         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9223
9224       else
9225         break;
9226     }
9227
9228   /* If the first operand is a constant, swap the operands and adjust the
9229      comparison code appropriately, but don't do this if the second operand
9230      is already a constant integer.  */
9231   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9232     {
9233       tem = op0, op0 = op1, op1 = tem;
9234       code = swap_condition (code);
9235     }
9236
9237   /* We now enter a loop during which we will try to simplify the comparison.
9238      For the most part, we only are concerned with comparisons with zero,
9239      but some things may really be comparisons with zero but not start
9240      out looking that way.  */
9241
9242   while (GET_CODE (op1) == CONST_INT)
9243     {
9244       enum machine_mode mode = GET_MODE (op0);
9245       int mode_width = GET_MODE_BITSIZE (mode);
9246       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9247       int equality_comparison_p;
9248       int sign_bit_comparison_p;
9249       int unsigned_comparison_p;
9250       HOST_WIDE_INT const_op;
9251
9252       /* We only want to handle integral modes.  This catches VOIDmode,
9253          CCmode, and the floating-point modes.  An exception is that we
9254          can handle VOIDmode if OP0 is a COMPARE or a comparison
9255          operation.  */
9256
9257       if (GET_MODE_CLASS (mode) != MODE_INT
9258           && ! (mode == VOIDmode
9259                 && (GET_CODE (op0) == COMPARE
9260                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9261         break;
9262
9263       /* Get the constant we are comparing against and turn off all bits
9264          not on in our mode.  */
9265       const_op = INTVAL (op1);
9266       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9267         const_op &= mask;
9268
9269       /* If we are comparing against a constant power of two and the value
9270          being compared can only have that single bit nonzero (e.g., it was
9271          `and'ed with that bit), we can replace this with a comparison
9272          with zero.  */
9273       if (const_op
9274           && (code == EQ || code == NE || code == GE || code == GEU
9275               || code == LT || code == LTU)
9276           && mode_width <= HOST_BITS_PER_WIDE_INT
9277           && exact_log2 (const_op) >= 0
9278           && nonzero_bits (op0, mode) == const_op)
9279         {
9280           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9281           op1 = const0_rtx, const_op = 0;
9282         }
9283
9284       /* Similarly, if we are comparing a value known to be either -1 or
9285          0 with -1, change it to the opposite comparison against zero.  */
9286
9287       if (const_op == -1
9288           && (code == EQ || code == NE || code == GT || code == LE
9289               || code == GEU || code == LTU)
9290           && num_sign_bit_copies (op0, mode) == mode_width)
9291         {
9292           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9293           op1 = const0_rtx, const_op = 0;
9294         }
9295
9296       /* Do some canonicalizations based on the comparison code.  We prefer
9297          comparisons against zero and then prefer equality comparisons.
9298          If we can reduce the size of a constant, we will do that too.  */
9299
9300       switch (code)
9301         {
9302         case LT:
9303           /* < C is equivalent to <= (C - 1) */
9304           if (const_op > 0)
9305             {
9306               const_op -= 1;
9307               op1 = GEN_INT (const_op);
9308               code = LE;
9309               /* ... fall through to LE case below.  */
9310             }
9311           else
9312             break;
9313
9314         case LE:
9315           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9316           if (const_op < 0)
9317             {
9318               const_op += 1;
9319               op1 = GEN_INT (const_op);
9320               code = LT;
9321             }
9322
9323           /* If we are doing a <= 0 comparison on a value known to have
9324              a zero sign bit, we can replace this with == 0.  */
9325           else if (const_op == 0
9326                    && mode_width <= HOST_BITS_PER_WIDE_INT
9327                    && (nonzero_bits (op0, mode)
9328                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9329             code = EQ;
9330           break;
9331
9332         case GE:
9333           /* >= C is equivalent to > (C - 1).  */
9334           if (const_op > 0)
9335             {
9336               const_op -= 1;
9337               op1 = GEN_INT (const_op);
9338               code = GT;
9339               /* ... fall through to GT below.  */
9340             }
9341           else
9342             break;
9343
9344         case GT:
9345           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9346           if (const_op < 0)
9347             {
9348               const_op += 1;
9349               op1 = GEN_INT (const_op);
9350               code = GE;
9351             }
9352
9353           /* If we are doing a > 0 comparison on a value known to have
9354              a zero sign bit, we can replace this with != 0.  */
9355           else if (const_op == 0
9356                    && mode_width <= HOST_BITS_PER_WIDE_INT
9357                    && (nonzero_bits (op0, mode)
9358                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9359             code = NE;
9360           break;
9361
9362         case LTU:
9363           /* < C is equivalent to <= (C - 1).  */
9364           if (const_op > 0)
9365             {
9366               const_op -= 1;
9367               op1 = GEN_INT (const_op);
9368               code = LEU;
9369               /* ... fall through ...  */
9370             }
9371
9372           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9373           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9374                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9375             {
9376               const_op = 0, op1 = const0_rtx;
9377               code = GE;
9378               break;
9379             }
9380           else
9381             break;
9382
9383         case LEU:
9384           /* unsigned <= 0 is equivalent to == 0 */
9385           if (const_op == 0)
9386             code = EQ;
9387
9388           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9389           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9390                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9391             {
9392               const_op = 0, op1 = const0_rtx;
9393               code = GE;
9394             }
9395           break;
9396
9397         case GEU:
9398           /* >= C is equivalent to < (C - 1).  */
9399           if (const_op > 1)
9400             {
9401               const_op -= 1;
9402               op1 = GEN_INT (const_op);
9403               code = GTU;
9404               /* ... fall through ...  */
9405             }
9406
9407           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9408           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9409                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9410             {
9411               const_op = 0, op1 = const0_rtx;
9412               code = LT;
9413               break;
9414             }
9415           else
9416             break;
9417
9418         case GTU:
9419           /* unsigned > 0 is equivalent to != 0 */
9420           if (const_op == 0)
9421             code = NE;
9422
9423           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9424           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9425                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9426             {
9427               const_op = 0, op1 = const0_rtx;
9428               code = LT;
9429             }
9430           break;
9431         }
9432
9433       /* Compute some predicates to simplify code below.  */
9434
9435       equality_comparison_p = (code == EQ || code == NE);
9436       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9437       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9438                                || code == LEU);
9439
9440       /* If this is a sign bit comparison and we can do arithmetic in
9441          MODE, say that we will only be needing the sign bit of OP0.  */
9442       if (sign_bit_comparison_p
9443           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9444         op0 = force_to_mode (op0, mode,
9445                              ((HOST_WIDE_INT) 1
9446                               << (GET_MODE_BITSIZE (mode) - 1)),
9447                              NULL_RTX, 0);
9448
9449       /* Now try cases based on the opcode of OP0.  If none of the cases
9450          does a "continue", we exit this loop immediately after the
9451          switch.  */
9452
9453       switch (GET_CODE (op0))
9454         {
9455         case ZERO_EXTRACT:
9456           /* If we are extracting a single bit from a variable position in
9457              a constant that has only a single bit set and are comparing it
9458              with zero, we can convert this into an equality comparison
9459              between the position and the location of the single bit.  */
9460
9461           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9462               && XEXP (op0, 1) == const1_rtx
9463               && equality_comparison_p && const_op == 0
9464               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9465             {
9466               if (BITS_BIG_ENDIAN)
9467 #ifdef HAVE_extzv
9468                 i = (GET_MODE_BITSIZE
9469                      (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9470 #else
9471                 i = BITS_PER_WORD - 1 - i;
9472 #endif
9473
9474               op0 = XEXP (op0, 2);
9475               op1 = GEN_INT (i);
9476               const_op = i;
9477
9478               /* Result is nonzero iff shift count is equal to I.  */
9479               code = reverse_condition (code);
9480               continue;
9481             }
9482
9483           /* ... fall through ...  */
9484
9485         case SIGN_EXTRACT:
9486           tem = expand_compound_operation (op0);
9487           if (tem != op0)
9488             {
9489               op0 = tem;
9490               continue;
9491             }
9492           break;
9493
9494         case NOT:
9495           /* If testing for equality, we can take the NOT of the constant.  */
9496           if (equality_comparison_p
9497               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9498             {
9499               op0 = XEXP (op0, 0);
9500               op1 = tem;
9501               continue;
9502             }
9503
9504           /* If just looking at the sign bit, reverse the sense of the
9505              comparison.  */
9506           if (sign_bit_comparison_p)
9507             {
9508               op0 = XEXP (op0, 0);
9509               code = (code == GE ? LT : GE);
9510               continue;
9511             }
9512           break;
9513
9514         case NEG:
9515           /* If testing for equality, we can take the NEG of the constant.  */
9516           if (equality_comparison_p
9517               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9518             {
9519               op0 = XEXP (op0, 0);
9520               op1 = tem;
9521               continue;
9522             }
9523
9524           /* The remaining cases only apply to comparisons with zero.  */
9525           if (const_op != 0)
9526             break;
9527
9528           /* When X is ABS or is known positive,
9529              (neg X) is < 0 if and only if X != 0.  */
9530
9531           if (sign_bit_comparison_p
9532               && (GET_CODE (XEXP (op0, 0)) == ABS
9533                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9534                       && (nonzero_bits (XEXP (op0, 0), mode)
9535                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9536             {
9537               op0 = XEXP (op0, 0);
9538               code = (code == LT ? NE : EQ);
9539               continue;
9540             }
9541
9542           /* If we have NEG of something whose two high-order bits are the
9543              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9544           if (num_sign_bit_copies (op0, mode) >= 2)
9545             {
9546               op0 = XEXP (op0, 0);
9547               code = swap_condition (code);
9548               continue;
9549             }
9550           break;
9551
9552         case ROTATE:
9553           /* If we are testing equality and our count is a constant, we
9554              can perform the inverse operation on our RHS.  */
9555           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9556               && (tem = simplify_binary_operation (ROTATERT, mode,
9557                                                    op1, XEXP (op0, 1))) != 0)
9558             {
9559               op0 = XEXP (op0, 0);
9560               op1 = tem;
9561               continue;
9562             }
9563
9564           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9565              a particular bit.  Convert it to an AND of a constant of that
9566              bit.  This will be converted into a ZERO_EXTRACT.  */
9567           if (const_op == 0 && sign_bit_comparison_p
9568               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9569               && mode_width <= HOST_BITS_PER_WIDE_INT)
9570             {
9571               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9572                                             ((HOST_WIDE_INT) 1
9573                                              << (mode_width - 1
9574                                                  - INTVAL (XEXP (op0, 1)))));
9575               code = (code == LT ? NE : EQ);
9576               continue;
9577             }
9578
9579           /* ... fall through ...  */
9580
9581         case ABS:
9582           /* ABS is ignorable inside an equality comparison with zero.  */
9583           if (const_op == 0 && equality_comparison_p)
9584             {
9585               op0 = XEXP (op0, 0);
9586               continue;
9587             }
9588           break;
9589
9590
9591         case SIGN_EXTEND:
9592           /* Can simplify (compare (zero/sign_extend FOO) CONST)
9593              to (compare FOO CONST) if CONST fits in FOO's mode and we
9594              are either testing inequality or have an unsigned comparison
9595              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
9596           if (! unsigned_comparison_p
9597               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9598                   <= HOST_BITS_PER_WIDE_INT)
9599               && ((unsigned HOST_WIDE_INT) const_op
9600                   < (((HOST_WIDE_INT) 1
9601                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9602             {
9603               op0 = XEXP (op0, 0);
9604               continue;
9605             }
9606           break;
9607
9608         case SUBREG:
9609           /* Check for the case where we are comparing A - C1 with C2,
9610              both constants are smaller than 1/2 the maximum positive
9611              value in MODE, and the comparison is equality or unsigned.
9612              In that case, if A is either zero-extended to MODE or has
9613              sufficient sign bits so that the high-order bit in MODE
9614              is a copy of the sign in the inner mode, we can prove that it is
9615              safe to do the operation in the wider mode.  This simplifies
9616              many range checks.  */
9617
9618           if (mode_width <= HOST_BITS_PER_WIDE_INT
9619               && subreg_lowpart_p (op0)
9620               && GET_CODE (SUBREG_REG (op0)) == PLUS
9621               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9622               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9623               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9624                   < GET_MODE_MASK (mode) / 2)
9625               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9626               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9627                                       GET_MODE (SUBREG_REG (op0)))
9628                         & ~ GET_MODE_MASK (mode))
9629                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9630                                            GET_MODE (SUBREG_REG (op0)))
9631                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9632                          - GET_MODE_BITSIZE (mode)))))
9633             {
9634               op0 = SUBREG_REG (op0);
9635               continue;
9636             }
9637
9638           /* If the inner mode is narrower and we are extracting the low part,
9639              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
9640           if (subreg_lowpart_p (op0)
9641               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9642             /* Fall through */ ;
9643           else
9644             break;
9645
9646           /* ... fall through ...  */
9647
9648         case ZERO_EXTEND:
9649           if ((unsigned_comparison_p || equality_comparison_p)
9650               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9651                   <= HOST_BITS_PER_WIDE_INT)
9652               && ((unsigned HOST_WIDE_INT) const_op
9653                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9654             {
9655               op0 = XEXP (op0, 0);
9656               continue;
9657             }
9658           break;
9659
9660         case PLUS:
9661           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
9662              this for equality comparisons due to pathological cases involving
9663              overflows.  */
9664           if (equality_comparison_p
9665               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9666                                                         op1, XEXP (op0, 1))))
9667             {
9668               op0 = XEXP (op0, 0);
9669               op1 = tem;
9670               continue;
9671             }
9672
9673           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
9674           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9675               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9676             {
9677               op0 = XEXP (XEXP (op0, 0), 0);
9678               code = (code == LT ? EQ : NE);
9679               continue;
9680             }
9681           break;
9682
9683         case MINUS:
9684           /* (eq (minus A B) C) -> (eq A (plus B C)) or
9685              (eq B (minus A C)), whichever simplifies.  We can only do
9686              this for equality comparisons due to pathological cases involving
9687              overflows.  */
9688           if (equality_comparison_p
9689               && 0 != (tem = simplify_binary_operation (PLUS, mode,
9690                                                         XEXP (op0, 1), op1)))
9691             {
9692               op0 = XEXP (op0, 0);
9693               op1 = tem;
9694               continue;
9695             }
9696
9697           if (equality_comparison_p
9698               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9699                                                         XEXP (op0, 0), op1)))
9700             {
9701               op0 = XEXP (op0, 1);
9702               op1 = tem;
9703               continue;
9704             }
9705
9706           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9707              of bits in X minus 1, is one iff X > 0.  */
9708           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9709               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9710               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9711               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9712             {
9713               op0 = XEXP (op0, 1);
9714               code = (code == GE ? LE : GT);
9715               continue;
9716             }
9717           break;
9718
9719         case XOR:
9720           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
9721              if C is zero or B is a constant.  */
9722           if (equality_comparison_p
9723               && 0 != (tem = simplify_binary_operation (XOR, mode,
9724                                                         XEXP (op0, 1), op1)))
9725             {
9726               op0 = XEXP (op0, 0);
9727               op1 = tem;
9728               continue;
9729             }
9730           break;
9731
9732         case EQ:  case NE:
9733         case LT:  case LTU:  case LE:  case LEU:
9734         case GT:  case GTU:  case GE:  case GEU:
9735           /* We can't do anything if OP0 is a condition code value, rather
9736              than an actual data value.  */
9737           if (const_op != 0
9738 #ifdef HAVE_cc0
9739               || XEXP (op0, 0) == cc0_rtx
9740 #endif
9741               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9742             break;
9743
9744           /* Get the two operands being compared.  */
9745           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9746             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9747           else
9748             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9749
9750           /* Check for the cases where we simply want the result of the
9751              earlier test or the opposite of that result.  */
9752           if (code == NE
9753               || (code == EQ && reversible_comparison_p (op0))
9754               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9755                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9756                   && (STORE_FLAG_VALUE
9757                       & (((HOST_WIDE_INT) 1
9758                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9759                   && (code == LT
9760                       || (code == GE && reversible_comparison_p (op0)))))
9761             {
9762               code = (code == LT || code == NE
9763                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9764               op0 = tem, op1 = tem1;
9765               continue;
9766             }
9767           break;
9768
9769         case IOR:
9770           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9771              iff X <= 0.  */
9772           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9773               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9774               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9775             {
9776               op0 = XEXP (op0, 1);
9777               code = (code == GE ? GT : LE);
9778               continue;
9779             }
9780           break;
9781
9782         case AND:
9783           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
9784              will be converted to a ZERO_EXTRACT later.  */
9785           if (const_op == 0 && equality_comparison_p
9786               && GET_CODE (XEXP (op0, 0)) == ASHIFT
9787               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9788             {
9789               op0 = simplify_and_const_int
9790                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9791                                              XEXP (op0, 1),
9792                                              XEXP (XEXP (op0, 0), 1)),
9793                  (HOST_WIDE_INT) 1);
9794               continue;
9795             }
9796
9797           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9798              zero and X is a comparison and C1 and C2 describe only bits set
9799              in STORE_FLAG_VALUE, we can compare with X.  */
9800           if (const_op == 0 && equality_comparison_p
9801               && mode_width <= HOST_BITS_PER_WIDE_INT
9802               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9803               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9804               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9805               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9806               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9807             {
9808               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9809                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
9810               if ((~ STORE_FLAG_VALUE & mask) == 0
9811                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9812                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9813                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9814                 {
9815                   op0 = XEXP (XEXP (op0, 0), 0);
9816                   continue;
9817                 }
9818             }
9819
9820           /* If we are doing an equality comparison of an AND of a bit equal
9821              to the sign bit, replace this with a LT or GE comparison of
9822              the underlying value.  */
9823           if (equality_comparison_p
9824               && const_op == 0
9825               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9826               && mode_width <= HOST_BITS_PER_WIDE_INT
9827               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9828                   == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9829             {
9830               op0 = XEXP (op0, 0);
9831               code = (code == EQ ? GE : LT);
9832               continue;
9833             }
9834
9835           /* If this AND operation is really a ZERO_EXTEND from a narrower
9836              mode, the constant fits within that mode, and this is either an
9837              equality or unsigned comparison, try to do this comparison in
9838              the narrower mode.  */
9839           if ((equality_comparison_p || unsigned_comparison_p)
9840               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9841               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9842                                    & GET_MODE_MASK (mode))
9843                                   + 1)) >= 0
9844               && const_op >> i == 0
9845               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9846             {
9847               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9848               continue;
9849             }
9850           break;
9851
9852         case ASHIFT:
9853           /* If we have (compare (ashift FOO N) (const_int C)) and
9854              the high order N bits of FOO (N+1 if an inequality comparison)
9855              are known to be zero, we can do this by comparing FOO with C
9856              shifted right N bits so long as the low-order N bits of C are
9857              zero.  */
9858           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9859               && INTVAL (XEXP (op0, 1)) >= 0
9860               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9861                   < HOST_BITS_PER_WIDE_INT)
9862               && ((const_op
9863                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9864               && mode_width <= HOST_BITS_PER_WIDE_INT
9865               && (nonzero_bits (XEXP (op0, 0), mode)
9866                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
9867                                 + ! equality_comparison_p))) == 0)
9868             {
9869               const_op >>= INTVAL (XEXP (op0, 1));
9870               op1 = GEN_INT (const_op);
9871               op0 = XEXP (op0, 0);
9872               continue;
9873             }
9874
9875           /* If we are doing a sign bit comparison, it means we are testing
9876              a particular bit.  Convert it to the appropriate AND.  */
9877           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9878               && mode_width <= HOST_BITS_PER_WIDE_INT)
9879             {
9880               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9881                                             ((HOST_WIDE_INT) 1
9882                                              << (mode_width - 1
9883                                                  - INTVAL (XEXP (op0, 1)))));
9884               code = (code == LT ? NE : EQ);
9885               continue;
9886             }
9887
9888           /* If this an equality comparison with zero and we are shifting
9889              the low bit to the sign bit, we can convert this to an AND of the
9890              low-order bit.  */
9891           if (const_op == 0 && equality_comparison_p
9892               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9893               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9894             {
9895               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9896                                             (HOST_WIDE_INT) 1);
9897               continue;
9898             }
9899           break;
9900
9901         case ASHIFTRT:
9902           /* If this is an equality comparison with zero, we can do this
9903              as a logical shift, which might be much simpler.  */
9904           if (equality_comparison_p && const_op == 0
9905               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9906             {
9907               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9908                                           XEXP (op0, 0),
9909                                           INTVAL (XEXP (op0, 1)));
9910               continue;
9911             }
9912
9913           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9914              do the comparison in a narrower mode.  */
9915           if (! unsigned_comparison_p
9916               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9917               && GET_CODE (XEXP (op0, 0)) == ASHIFT
9918               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9919               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9920                                          MODE_INT, 1)) != BLKmode
9921               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9922                   || ((unsigned HOST_WIDE_INT) - const_op
9923                       <= GET_MODE_MASK (tmode))))
9924             {
9925               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9926               continue;
9927             }
9928
9929           /* ... fall through ...  */
9930         case LSHIFTRT:
9931           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9932              the low order N bits of FOO are known to be zero, we can do this
9933              by comparing FOO with C shifted left N bits so long as no
9934              overflow occurs.  */
9935           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9936               && INTVAL (XEXP (op0, 1)) >= 0
9937               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9938               && mode_width <= HOST_BITS_PER_WIDE_INT
9939               && (nonzero_bits (XEXP (op0, 0), mode)
9940                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9941               && (const_op == 0
9942                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9943                       < mode_width)))
9944             {
9945               const_op <<= INTVAL (XEXP (op0, 1));
9946               op1 = GEN_INT (const_op);
9947               op0 = XEXP (op0, 0);
9948               continue;
9949             }
9950
9951           /* If we are using this shift to extract just the sign bit, we
9952              can replace this with an LT or GE comparison.  */
9953           if (const_op == 0
9954               && (equality_comparison_p || sign_bit_comparison_p)
9955               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9956               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9957             {
9958               op0 = XEXP (op0, 0);
9959               code = (code == NE || code == GT ? LT : GE);
9960               continue;
9961             }
9962           break;
9963         }
9964
9965       break;
9966     }
9967
9968   /* Now make any compound operations involved in this comparison.  Then,
9969      check for an outmost SUBREG on OP0 that isn't doing anything or is
9970      paradoxical.  The latter case can only occur when it is known that the
9971      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
9972      We can never remove a SUBREG for a non-equality comparison because the
9973      sign bit is in a different place in the underlying object.  */
9974
9975   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9976   op1 = make_compound_operation (op1, SET);
9977
9978   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9979       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9980       && (code == NE || code == EQ)
9981       && ((GET_MODE_SIZE (GET_MODE (op0))
9982            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9983     {
9984       op0 = SUBREG_REG (op0);
9985       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9986     }
9987
9988   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9989            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9990            && (code == NE || code == EQ)
9991            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9992                <= HOST_BITS_PER_WIDE_INT)
9993            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9994                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9995            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9996                                               op1),
9997                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9998                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9999     op0 = SUBREG_REG (op0), op1 = tem;
10000
10001   /* We now do the opposite procedure: Some machines don't have compare
10002      insns in all modes.  If OP0's mode is an integer mode smaller than a
10003      word and we can't do a compare in that mode, see if there is a larger
10004      mode for which we can do the compare.  There are a number of cases in
10005      which we can use the wider mode.  */
10006
10007   mode = GET_MODE (op0);
10008   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10009       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10010       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10011     for (tmode = GET_MODE_WIDER_MODE (mode);
10012          (tmode != VOIDmode
10013           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10014          tmode = GET_MODE_WIDER_MODE (tmode))
10015       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10016         {
10017           /* If the only nonzero bits in OP0 and OP1 are those in the
10018              narrower mode and this is an equality or unsigned comparison,
10019              we can use the wider mode.  Similarly for sign-extended
10020              values, in which case it is true for all comparisons.  */
10021           if (((code == EQ || code == NE
10022                 || code == GEU || code == GTU || code == LEU || code == LTU)
10023                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10024                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10025               || ((num_sign_bit_copies (op0, tmode)
10026                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10027                   && (num_sign_bit_copies (op1, tmode)
10028                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10029             {
10030               op0 = gen_lowpart_for_combine (tmode, op0);
10031               op1 = gen_lowpart_for_combine (tmode, op1);
10032               break;
10033             }
10034
10035           /* If this is a test for negative, we can make an explicit
10036              test of the sign bit.  */
10037
10038           if (op1 == const0_rtx && (code == LT || code == GE)
10039               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10040             {
10041               op0 = gen_binary (AND, tmode,
10042                                 gen_lowpart_for_combine (tmode, op0),
10043                                 GEN_INT ((HOST_WIDE_INT) 1
10044                                          << (GET_MODE_BITSIZE (mode) - 1)));
10045               code = (code == LT) ? NE : EQ;
10046               break;
10047             }
10048         }
10049
10050 #ifdef CANONICALIZE_COMPARISON
10051   /* If this machine only supports a subset of valid comparisons, see if we
10052      can convert an unsupported one into a supported one.  */
10053   CANONICALIZE_COMPARISON (code, op0, op1);
10054 #endif
10055
10056   *pop0 = op0;
10057   *pop1 = op1;
10058
10059   return code;
10060 }
10061 \f
10062 /* Return 1 if we know that X, a comparison operation, is not operating
10063    on a floating-point value or is EQ or NE, meaning that we can safely
10064    reverse it.  */
10065
10066 static int
10067 reversible_comparison_p (x)
10068      rtx x;
10069 {
10070   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10071       || flag_fast_math
10072       || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10073     return 1;
10074
10075   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10076     {
10077     case MODE_INT:
10078     case MODE_PARTIAL_INT:
10079     case MODE_COMPLEX_INT:
10080       return 1;
10081
10082     case MODE_CC:
10083       /* If the mode of the condition codes tells us that this is safe,
10084          we need look no further.  */
10085       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10086         return 1;
10087
10088       /* Otherwise try and find where the condition codes were last set and
10089          use that.  */
10090       x = get_last_value (XEXP (x, 0));
10091       return (x && GET_CODE (x) == COMPARE
10092               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10093     }
10094
10095   return 0;
10096 }
10097 \f
10098 /* Utility function for following routine.  Called when X is part of a value
10099    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10100    for each register mentioned.  Similar to mention_regs in cse.c  */
10101
10102 static void
10103 update_table_tick (x)
10104      rtx x;
10105 {
10106   register enum rtx_code code = GET_CODE (x);
10107   register char *fmt = GET_RTX_FORMAT (code);
10108   register int i;
10109
10110   if (code == REG)
10111     {
10112       int regno = REGNO (x);
10113       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10114                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10115
10116       for (i = regno; i < endregno; i++)
10117         reg_last_set_table_tick[i] = label_tick;
10118
10119       return;
10120     }
10121
10122   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10123     /* Note that we can't have an "E" in values stored; see
10124        get_last_value_validate.  */
10125     if (fmt[i] == 'e')
10126       update_table_tick (XEXP (x, i));
10127 }
10128
10129 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10130    are saying that the register is clobbered and we no longer know its
10131    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10132    with VALUE also zero and is used to invalidate the register.  */
10133
10134 static void
10135 record_value_for_reg (reg, insn, value)
10136      rtx reg;
10137      rtx insn;
10138      rtx value;
10139 {
10140   int regno = REGNO (reg);
10141   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10142                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10143   int i;
10144
10145   /* If VALUE contains REG and we have a previous value for REG, substitute
10146      the previous value.  */
10147   if (value && insn && reg_overlap_mentioned_p (reg, value))
10148     {
10149       rtx tem;
10150
10151       /* Set things up so get_last_value is allowed to see anything set up to
10152          our insn.  */
10153       subst_low_cuid = INSN_CUID (insn);
10154       tem = get_last_value (reg);
10155
10156       if (tem)
10157         value = replace_rtx (copy_rtx (value), reg, tem);
10158     }
10159
10160   /* For each register modified, show we don't know its value, that
10161      we don't know about its bitwise content, that its value has been
10162      updated, and that we don't know the location of the death of the
10163      register.  */
10164   for (i = regno; i < endregno; i ++)
10165     {
10166       if (insn)
10167         reg_last_set[i] = insn;
10168       reg_last_set_value[i] = 0;
10169       reg_last_set_mode[i] = 0;
10170       reg_last_set_nonzero_bits[i] = 0;
10171       reg_last_set_sign_bit_copies[i] = 0;
10172       reg_last_death[i] = 0;
10173     }
10174
10175   /* Mark registers that are being referenced in this value.  */
10176   if (value)
10177     update_table_tick (value);
10178
10179   /* Now update the status of each register being set.
10180      If someone is using this register in this block, set this register
10181      to invalid since we will get confused between the two lives in this
10182      basic block.  This makes using this register always invalid.  In cse, we
10183      scan the table to invalidate all entries using this register, but this
10184      is too much work for us.  */
10185
10186   for (i = regno; i < endregno; i++)
10187     {
10188       reg_last_set_label[i] = label_tick;
10189       if (value && reg_last_set_table_tick[i] == label_tick)
10190         reg_last_set_invalid[i] = 1;
10191       else
10192         reg_last_set_invalid[i] = 0;
10193     }
10194
10195   /* The value being assigned might refer to X (like in "x++;").  In that
10196      case, we must replace it with (clobber (const_int 0)) to prevent
10197      infinite loops.  */
10198   if (value && ! get_last_value_validate (&value,
10199                                           reg_last_set_label[regno], 0))
10200     {
10201       value = copy_rtx (value);
10202       if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
10203         value = 0;
10204     }
10205
10206   /* For the main register being modified, update the value, the mode, the
10207      nonzero bits, and the number of sign bit copies.  */
10208
10209   reg_last_set_value[regno] = value;
10210
10211   if (value)
10212     {
10213       subst_low_cuid = INSN_CUID (insn);
10214       reg_last_set_mode[regno] = GET_MODE (reg);
10215       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10216       reg_last_set_sign_bit_copies[regno]
10217         = num_sign_bit_copies (value, GET_MODE (reg));
10218     }
10219 }
10220
10221 /* Used for communication between the following two routines.  */
10222 static rtx record_dead_insn;
10223
10224 /* Called via note_stores from record_dead_and_set_regs to handle one
10225    SET or CLOBBER in an insn.  */
10226
10227 static void
10228 record_dead_and_set_regs_1 (dest, setter)
10229      rtx dest, setter;
10230 {
10231   if (GET_CODE (dest) == SUBREG)
10232     dest = SUBREG_REG (dest);
10233
10234   if (GET_CODE (dest) == REG)
10235     {
10236       /* If we are setting the whole register, we know its value.  Otherwise
10237          show that we don't know the value.  We can handle SUBREG in
10238          some cases.  */
10239       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10240         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10241       else if (GET_CODE (setter) == SET
10242                && GET_CODE (SET_DEST (setter)) == SUBREG
10243                && SUBREG_REG (SET_DEST (setter)) == dest
10244                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10245                && subreg_lowpart_p (SET_DEST (setter)))
10246         record_value_for_reg (dest, record_dead_insn,
10247                               gen_lowpart_for_combine (GET_MODE (dest),
10248                                                        SET_SRC (setter)));
10249       else
10250         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10251     }
10252   else if (GET_CODE (dest) == MEM
10253            /* Ignore pushes, they clobber nothing.  */
10254            && ! push_operand (dest, GET_MODE (dest)))
10255     mem_last_set = INSN_CUID (record_dead_insn);
10256 }
10257
10258 /* Update the records of when each REG was most recently set or killed
10259    for the things done by INSN.  This is the last thing done in processing
10260    INSN in the combiner loop.
10261
10262    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10263    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10264    and also the similar information mem_last_set (which insn most recently
10265    modified memory) and last_call_cuid (which insn was the most recent
10266    subroutine call).  */
10267
10268 static void
10269 record_dead_and_set_regs (insn)
10270      rtx insn;
10271 {
10272   register rtx link;
10273   int i;
10274
10275   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10276     {
10277       if (REG_NOTE_KIND (link) == REG_DEAD
10278           && GET_CODE (XEXP (link, 0)) == REG)
10279         {
10280           int regno = REGNO (XEXP (link, 0));
10281           int endregno
10282             = regno + (regno < FIRST_PSEUDO_REGISTER
10283                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10284                        : 1);
10285
10286           for (i = regno; i < endregno; i++)
10287             reg_last_death[i] = insn;
10288         }
10289       else if (REG_NOTE_KIND (link) == REG_INC)
10290         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10291     }
10292
10293   if (GET_CODE (insn) == CALL_INSN)
10294     {
10295       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10296         if (call_used_regs[i])
10297           {
10298             reg_last_set_value[i] = 0;
10299             reg_last_set_mode[i] = 0;
10300             reg_last_set_nonzero_bits[i] = 0;
10301             reg_last_set_sign_bit_copies[i] = 0;
10302             reg_last_death[i] = 0;
10303           }
10304
10305       last_call_cuid = mem_last_set = INSN_CUID (insn);
10306     }
10307
10308   record_dead_insn = insn;
10309   note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10310 }
10311 \f
10312 /* Utility routine for the following function.  Verify that all the registers
10313    mentioned in *LOC are valid when *LOC was part of a value set when
10314    label_tick == TICK.  Return 0 if some are not.
10315
10316    If REPLACE is non-zero, replace the invalid reference with
10317    (clobber (const_int 0)) and return 1.  This replacement is useful because
10318    we often can get useful information about the form of a value (e.g., if
10319    it was produced by a shift that always produces -1 or 0) even though
10320    we don't know exactly what registers it was produced from.  */
10321
10322 static int
10323 get_last_value_validate (loc, tick, replace)
10324      rtx *loc;
10325      int tick;
10326      int replace;
10327 {
10328   rtx x = *loc;
10329   char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10330   int len = GET_RTX_LENGTH (GET_CODE (x));
10331   int i;
10332
10333   if (GET_CODE (x) == REG)
10334     {
10335       int regno = REGNO (x);
10336       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10337                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10338       int j;
10339
10340       for (j = regno; j < endregno; j++)
10341         if (reg_last_set_invalid[j]
10342             /* If this is a pseudo-register that was only set once, it is
10343                always valid.  */
10344             || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10345                 && reg_last_set_label[j] > tick))
10346           {
10347             if (replace)
10348               *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10349             return replace;
10350           }
10351
10352       return 1;
10353     }
10354
10355   for (i = 0; i < len; i++)
10356     if ((fmt[i] == 'e'
10357          && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10358         /* Don't bother with these.  They shouldn't occur anyway.  */
10359         || fmt[i] == 'E')
10360       return 0;
10361
10362   /* If we haven't found a reason for it to be invalid, it is valid.  */
10363   return 1;
10364 }
10365
10366 /* Get the last value assigned to X, if known.  Some registers
10367    in the value may be replaced with (clobber (const_int 0)) if their value
10368    is known longer known reliably.  */
10369
10370 static rtx
10371 get_last_value (x)
10372      rtx x;
10373 {
10374   int regno;
10375   rtx value;
10376
10377   /* If this is a non-paradoxical SUBREG, get the value of its operand and
10378      then convert it to the desired mode.  If this is a paradoxical SUBREG,
10379      we cannot predict what values the "extra" bits might have.  */
10380   if (GET_CODE (x) == SUBREG
10381       && subreg_lowpart_p (x)
10382       && (GET_MODE_SIZE (GET_MODE (x))
10383           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10384       && (value = get_last_value (SUBREG_REG (x))) != 0)
10385     return gen_lowpart_for_combine (GET_MODE (x), value);
10386
10387   if (GET_CODE (x) != REG)
10388     return 0;
10389
10390   regno = REGNO (x);
10391   value = reg_last_set_value[regno];
10392
10393   /* If we don't have a value or if it isn't for this basic block,
10394      return 0.  */
10395
10396   if (value == 0
10397       || (reg_n_sets[regno] != 1
10398           && reg_last_set_label[regno] != label_tick))
10399     return 0;
10400
10401   /* If the value was set in a later insn than the ones we are processing,
10402      we can't use it even if the register was only set once, but make a quick
10403      check to see if the previous insn set it to something.  This is commonly
10404      the case when the same pseudo is used by repeated insns.
10405
10406      This does not work if there exists an instruction which is temporarily
10407      not on the insn chain.  */
10408
10409   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10410     {
10411       rtx insn, set;
10412
10413       /* We can not do anything useful in this case, because there is
10414          an instruction which is not on the insn chain.  */
10415       if (subst_prev_insn)
10416         return 0;
10417
10418       /* Skip over USE insns.  They are not useful here, and they may have
10419          been made by combine, in which case they do not have a INSN_CUID
10420          value.  We can't use prev_real_insn, because that would incorrectly
10421          take us backwards across labels.  Skip over BARRIERs also, since
10422          they could have been made by combine.  If we see one, we must be
10423          optimizing dead code, so it doesn't matter what we do.  */
10424       for (insn = prev_nonnote_insn (subst_insn);
10425            insn && ((GET_CODE (insn) == INSN
10426                      && GET_CODE (PATTERN (insn)) == USE)
10427                     || GET_CODE (insn) == BARRIER
10428                     || INSN_CUID (insn) >= subst_low_cuid);
10429            insn = prev_nonnote_insn (insn))
10430         ;
10431
10432       if (insn
10433           && (set = single_set (insn)) != 0
10434           && rtx_equal_p (SET_DEST (set), x))
10435         {
10436           value = SET_SRC (set);
10437
10438           /* Make sure that VALUE doesn't reference X.  Replace any
10439              explicit references with a CLOBBER.  If there are any remaining
10440              references (rare), don't use the value.  */
10441
10442           if (reg_mentioned_p (x, value))
10443             value = replace_rtx (copy_rtx (value), x,
10444                                  gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10445
10446           if (reg_overlap_mentioned_p (x, value))
10447             return 0;
10448         }
10449       else
10450         return 0;
10451     }
10452
10453   /* If the value has all its registers valid, return it.  */
10454   if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10455     return value;
10456
10457   /* Otherwise, make a copy and replace any invalid register with
10458      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
10459
10460   value = copy_rtx (value);
10461   if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10462     return value;
10463
10464   return 0;
10465 }
10466 \f
10467 /* Return nonzero if expression X refers to a REG or to memory
10468    that is set in an instruction more recent than FROM_CUID.  */
10469
10470 static int
10471 use_crosses_set_p (x, from_cuid)
10472      register rtx x;
10473      int from_cuid;
10474 {
10475   register char *fmt;
10476   register int i;
10477   register enum rtx_code code = GET_CODE (x);
10478
10479   if (code == REG)
10480     {
10481       register int regno = REGNO (x);
10482       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10483                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10484
10485 #ifdef PUSH_ROUNDING
10486       /* Don't allow uses of the stack pointer to be moved,
10487          because we don't know whether the move crosses a push insn.  */
10488       if (regno == STACK_POINTER_REGNUM)
10489         return 1;
10490 #endif
10491       for (;regno < endreg; regno++)
10492         if (reg_last_set[regno]
10493             && INSN_CUID (reg_last_set[regno]) > from_cuid)
10494           return 1;
10495       return 0;
10496     }
10497
10498   if (code == MEM && mem_last_set > from_cuid)
10499     return 1;
10500
10501   fmt = GET_RTX_FORMAT (code);
10502
10503   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10504     {
10505       if (fmt[i] == 'E')
10506         {
10507           register int j;
10508           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10509             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10510               return 1;
10511         }
10512       else if (fmt[i] == 'e'
10513                && use_crosses_set_p (XEXP (x, i), from_cuid))
10514         return 1;
10515     }
10516   return 0;
10517 }
10518 \f
10519 /* Define three variables used for communication between the following
10520    routines.  */
10521
10522 static int reg_dead_regno, reg_dead_endregno;
10523 static int reg_dead_flag;
10524
10525 /* Function called via note_stores from reg_dead_at_p.
10526
10527    If DEST is within [reg_dead_regno, reg_dead_endregno), set
10528    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
10529
10530 static void
10531 reg_dead_at_p_1 (dest, x)
10532      rtx dest;
10533      rtx x;
10534 {
10535   int regno, endregno;
10536
10537   if (GET_CODE (dest) != REG)
10538     return;
10539
10540   regno = REGNO (dest);
10541   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10542                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10543
10544   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10545     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10546 }
10547
10548 /* Return non-zero if REG is known to be dead at INSN.
10549
10550    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
10551    referencing REG, it is dead.  If we hit a SET referencing REG, it is
10552    live.  Otherwise, see if it is live or dead at the start of the basic
10553    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
10554    must be assumed to be always live.  */
10555
10556 static int
10557 reg_dead_at_p (reg, insn)
10558      rtx reg;
10559      rtx insn;
10560 {
10561   int block, i;
10562
10563   /* Set variables for reg_dead_at_p_1.  */
10564   reg_dead_regno = REGNO (reg);
10565   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10566                                         ? HARD_REGNO_NREGS (reg_dead_regno,
10567                                                             GET_MODE (reg))
10568                                         : 1);
10569
10570   reg_dead_flag = 0;
10571
10572   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
10573   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10574     {
10575       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10576         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10577           return 0;
10578     }
10579
10580   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10581      beginning of function.  */
10582   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10583        insn = prev_nonnote_insn (insn))
10584     {
10585       note_stores (PATTERN (insn), reg_dead_at_p_1);
10586       if (reg_dead_flag)
10587         return reg_dead_flag == 1 ? 1 : 0;
10588
10589       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10590         return 1;
10591     }
10592
10593   /* Get the basic block number that we were in.  */
10594   if (insn == 0)
10595     block = 0;
10596   else
10597     {
10598       for (block = 0; block < n_basic_blocks; block++)
10599         if (insn == basic_block_head[block])
10600           break;
10601
10602       if (block == n_basic_blocks)
10603         return 0;
10604     }
10605
10606   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10607     if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10608         & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
10609       return 0;
10610
10611   return 1;
10612 }
10613 \f
10614 /* Note hard registers in X that are used.  This code is similar to
10615    that in flow.c, but much simpler since we don't care about pseudos.  */
10616
10617 static void
10618 mark_used_regs_combine (x)
10619      rtx x;
10620 {
10621   register RTX_CODE code = GET_CODE (x);
10622   register int regno;
10623   int i;
10624
10625   switch (code)
10626     {
10627     case LABEL_REF:
10628     case SYMBOL_REF:
10629     case CONST_INT:
10630     case CONST:
10631     case CONST_DOUBLE:
10632     case PC:
10633     case ADDR_VEC:
10634     case ADDR_DIFF_VEC:
10635     case ASM_INPUT:
10636 #ifdef HAVE_cc0
10637     /* CC0 must die in the insn after it is set, so we don't need to take
10638        special note of it here.  */
10639     case CC0:
10640 #endif
10641       return;
10642
10643     case CLOBBER:
10644       /* If we are clobbering a MEM, mark any hard registers inside the
10645          address as used.  */
10646       if (GET_CODE (XEXP (x, 0)) == MEM)
10647         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10648       return;
10649
10650     case REG:
10651       regno = REGNO (x);
10652       /* A hard reg in a wide mode may really be multiple registers.
10653          If so, mark all of them just like the first.  */
10654       if (regno < FIRST_PSEUDO_REGISTER)
10655         {
10656           /* None of this applies to the stack, frame or arg pointers */
10657           if (regno == STACK_POINTER_REGNUM
10658 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10659               || regno == HARD_FRAME_POINTER_REGNUM
10660 #endif
10661 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10662               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10663 #endif
10664               || regno == FRAME_POINTER_REGNUM)
10665             return;
10666
10667           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10668           while (i-- > 0)
10669             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10670         }
10671       return;
10672
10673     case SET:
10674       {
10675         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10676            the address.  */
10677         register rtx testreg = SET_DEST (x);
10678
10679         while (GET_CODE (testreg) == SUBREG
10680                || GET_CODE (testreg) == ZERO_EXTRACT
10681                || GET_CODE (testreg) == SIGN_EXTRACT
10682                || GET_CODE (testreg) == STRICT_LOW_PART)
10683           testreg = XEXP (testreg, 0);
10684
10685         if (GET_CODE (testreg) == MEM)
10686           mark_used_regs_combine (XEXP (testreg, 0));
10687
10688         mark_used_regs_combine (SET_SRC (x));
10689         return;
10690       }
10691     }
10692
10693   /* Recursively scan the operands of this expression.  */
10694
10695   {
10696     register char *fmt = GET_RTX_FORMAT (code);
10697
10698     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10699       {
10700         if (fmt[i] == 'e')
10701           mark_used_regs_combine (XEXP (x, i));
10702         else if (fmt[i] == 'E')
10703           {
10704             register int j;
10705
10706             for (j = 0; j < XVECLEN (x, i); j++)
10707               mark_used_regs_combine (XVECEXP (x, i, j));
10708           }
10709       }
10710   }
10711 }
10712
10713 \f
10714 /* Remove register number REGNO from the dead registers list of INSN.
10715
10716    Return the note used to record the death, if there was one.  */
10717
10718 rtx
10719 remove_death (regno, insn)
10720      int regno;
10721      rtx insn;
10722 {
10723   register rtx note = find_regno_note (insn, REG_DEAD, regno);
10724
10725   if (note)
10726     {
10727       reg_n_deaths[regno]--;
10728       remove_note (insn, note);
10729     }
10730
10731   return note;
10732 }
10733
10734 /* For each register (hardware or pseudo) used within expression X, if its
10735    death is in an instruction with cuid between FROM_CUID (inclusive) and
10736    TO_INSN (exclusive), put a REG_DEAD note for that register in the
10737    list headed by PNOTES.
10738
10739    That said, don't move registers killed by maybe_kill_insn.
10740
10741    This is done when X is being merged by combination into TO_INSN.  These
10742    notes will then be distributed as needed.  */
10743
10744 static void
10745 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10746      rtx x;
10747      rtx maybe_kill_insn;
10748      int from_cuid;
10749      rtx to_insn;
10750      rtx *pnotes;
10751 {
10752   register char *fmt;
10753   register int len, i;
10754   register enum rtx_code code = GET_CODE (x);
10755
10756   if (code == REG)
10757     {
10758       register int regno = REGNO (x);
10759       register rtx where_dead = reg_last_death[regno];
10760       register rtx before_dead, after_dead;
10761
10762       /* Don't move the register if it gets killed in between from and to */
10763       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10764           && !reg_referenced_p (x, maybe_kill_insn))
10765         return;
10766
10767       /* WHERE_DEAD could be a USE insn made by combine, so first we
10768          make sure that we have insns with valid INSN_CUID values.  */
10769       before_dead = where_dead;
10770       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10771         before_dead = PREV_INSN (before_dead);
10772       after_dead = where_dead;
10773       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10774         after_dead = NEXT_INSN (after_dead);
10775
10776       if (before_dead && after_dead
10777           && INSN_CUID (before_dead) >= from_cuid
10778           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10779               || (where_dead != after_dead
10780                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10781         {
10782           rtx note = remove_death (regno, where_dead);
10783
10784           /* It is possible for the call above to return 0.  This can occur
10785              when reg_last_death points to I2 or I1 that we combined with.
10786              In that case make a new note.
10787
10788              We must also check for the case where X is a hard register
10789              and NOTE is a death note for a range of hard registers
10790              including X.  In that case, we must put REG_DEAD notes for
10791              the remaining registers in place of NOTE.  */
10792
10793           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10794               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10795                   != GET_MODE_SIZE (GET_MODE (x))))
10796             {
10797               int deadregno = REGNO (XEXP (note, 0));
10798               int deadend
10799                 = (deadregno + HARD_REGNO_NREGS (deadregno,
10800                                                  GET_MODE (XEXP (note, 0))));
10801               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10802               int i;
10803
10804               for (i = deadregno; i < deadend; i++)
10805                 if (i < regno || i >= ourend)
10806                   REG_NOTES (where_dead)
10807                     = gen_rtx (EXPR_LIST, REG_DEAD,
10808                                gen_rtx (REG, reg_raw_mode[i], i),
10809                                REG_NOTES (where_dead));
10810             }
10811           /* If we didn't find any note, and we have a multi-reg hard
10812              register, then to be safe we must check for REG_DEAD notes
10813              for each register other than the first.  They could have
10814              their own REG_DEAD notes lying around.  */
10815           else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
10816                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10817             {
10818               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10819               int i;
10820               rtx oldnotes = 0;
10821
10822               for (i = regno + 1; i < ourend; i++)
10823                 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10824                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10825             }
10826
10827           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10828             {
10829               XEXP (note, 1) = *pnotes;
10830               *pnotes = note;
10831             }
10832           else
10833             *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10834
10835           reg_n_deaths[regno]++;
10836         }
10837
10838       return;
10839     }
10840
10841   else if (GET_CODE (x) == SET)
10842     {
10843       rtx dest = SET_DEST (x);
10844
10845       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10846
10847       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10848          that accesses one word of a multi-word item, some
10849          piece of everything register in the expression is used by
10850          this insn, so remove any old death.  */
10851
10852       if (GET_CODE (dest) == ZERO_EXTRACT
10853           || GET_CODE (dest) == STRICT_LOW_PART
10854           || (GET_CODE (dest) == SUBREG
10855               && (((GET_MODE_SIZE (GET_MODE (dest))
10856                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10857                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10858                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10859         {
10860           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10861           return;
10862         }
10863
10864       /* If this is some other SUBREG, we know it replaces the entire
10865          value, so use that as the destination.  */
10866       if (GET_CODE (dest) == SUBREG)
10867         dest = SUBREG_REG (dest);
10868
10869       /* If this is a MEM, adjust deaths of anything used in the address.
10870          For a REG (the only other possibility), the entire value is
10871          being replaced so the old value is not used in this insn.  */
10872
10873       if (GET_CODE (dest) == MEM)
10874         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10875                      to_insn, pnotes);
10876       return;
10877     }
10878
10879   else if (GET_CODE (x) == CLOBBER)
10880     return;
10881
10882   len = GET_RTX_LENGTH (code);
10883   fmt = GET_RTX_FORMAT (code);
10884
10885   for (i = 0; i < len; i++)
10886     {
10887       if (fmt[i] == 'E')
10888         {
10889           register int j;
10890           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10891             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10892                          to_insn, pnotes);
10893         }
10894       else if (fmt[i] == 'e')
10895         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10896     }
10897 }
10898 \f
10899 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10900    pattern of an insn.  X must be a REG.  */
10901
10902 static int
10903 reg_bitfield_target_p (x, body)
10904      rtx x;
10905      rtx body;
10906 {
10907   int i;
10908
10909   if (GET_CODE (body) == SET)
10910     {
10911       rtx dest = SET_DEST (body);
10912       rtx target;
10913       int regno, tregno, endregno, endtregno;
10914
10915       if (GET_CODE (dest) == ZERO_EXTRACT)
10916         target = XEXP (dest, 0);
10917       else if (GET_CODE (dest) == STRICT_LOW_PART)
10918         target = SUBREG_REG (XEXP (dest, 0));
10919       else
10920         return 0;
10921
10922       if (GET_CODE (target) == SUBREG)
10923         target = SUBREG_REG (target);
10924
10925       if (GET_CODE (target) != REG)
10926         return 0;
10927
10928       tregno = REGNO (target), regno = REGNO (x);
10929       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10930         return target == x;
10931
10932       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10933       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10934
10935       return endregno > tregno && regno < endtregno;
10936     }
10937
10938   else if (GET_CODE (body) == PARALLEL)
10939     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10940       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10941         return 1;
10942
10943   return 0;
10944 }
10945 \f
10946 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10947    as appropriate.  I3 and I2 are the insns resulting from the combination
10948    insns including FROM (I2 may be zero).
10949
10950    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10951    not need REG_DEAD notes because they are being substituted for.  This
10952    saves searching in the most common cases.
10953
10954    Each note in the list is either ignored or placed on some insns, depending
10955    on the type of note.  */
10956
10957 static void
10958 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10959      rtx notes;
10960      rtx from_insn;
10961      rtx i3, i2;
10962      rtx elim_i2, elim_i1;
10963 {
10964   rtx note, next_note;
10965   rtx tem;
10966
10967   for (note = notes; note; note = next_note)
10968     {
10969       rtx place = 0, place2 = 0;
10970
10971       /* If this NOTE references a pseudo register, ensure it references
10972          the latest copy of that register.  */
10973       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10974           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10975         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10976
10977       next_note = XEXP (note, 1);
10978       switch (REG_NOTE_KIND (note))
10979         {
10980         case REG_UNUSED:
10981           /* Any clobbers for i3 may still exist, and so we must process
10982              REG_UNUSED notes from that insn.
10983
10984              Any clobbers from i2 or i1 can only exist if they were added by
10985              recog_for_combine.  In that case, recog_for_combine created the
10986              necessary REG_UNUSED notes.  Trying to keep any original
10987              REG_UNUSED notes from these insns can cause incorrect output
10988              if it is for the same register as the original i3 dest.
10989              In that case, we will notice that the register is set in i3,
10990              and then add a REG_UNUSED note for the destination of i3, which
10991              is wrong.  However, it is possible to have REG_UNUSED notes from
10992              i2 or i1 for register which were both used and clobbered, so
10993              we keep notes from i2 or i1 if they will turn into REG_DEAD
10994              notes.  */
10995
10996           /* If this register is set or clobbered in I3, put the note there
10997              unless there is one already.  */
10998           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10999             {
11000               if (from_insn != i3)
11001                 break;
11002
11003               if (! (GET_CODE (XEXP (note, 0)) == REG
11004                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11005                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11006                 place = i3;
11007             }
11008           /* Otherwise, if this register is used by I3, then this register
11009              now dies here, so we must put a REG_DEAD note here unless there
11010              is one already.  */
11011           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11012                    && ! (GET_CODE (XEXP (note, 0)) == REG
11013                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11014                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11015             {
11016               PUT_REG_NOTE_KIND (note, REG_DEAD);
11017               place = i3;
11018             }
11019           break;
11020
11021         case REG_EQUAL:
11022         case REG_EQUIV:
11023         case REG_NONNEG:
11024           /* These notes say something about results of an insn.  We can
11025              only support them if they used to be on I3 in which case they
11026              remain on I3.  Otherwise they are ignored.
11027
11028              If the note refers to an expression that is not a constant, we
11029              must also ignore the note since we cannot tell whether the
11030              equivalence is still true.  It might be possible to do
11031              slightly better than this (we only have a problem if I2DEST
11032              or I1DEST is present in the expression), but it doesn't
11033              seem worth the trouble.  */
11034
11035           if (from_insn == i3
11036               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11037             place = i3;
11038           break;
11039
11040         case REG_INC:
11041         case REG_NO_CONFLICT:
11042         case REG_LABEL:
11043           /* These notes say something about how a register is used.  They must
11044              be present on any use of the register in I2 or I3.  */
11045           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11046             place = i3;
11047
11048           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11049             {
11050               if (place)
11051                 place2 = i2;
11052               else
11053                 place = i2;
11054             }
11055           break;
11056
11057         case REG_WAS_0:
11058           /* It is too much trouble to try to see if this note is still
11059              correct in all situations.  It is better to simply delete it.  */
11060           break;
11061
11062         case REG_RETVAL:
11063           /* If the insn previously containing this note still exists,
11064              put it back where it was.  Otherwise move it to the previous
11065              insn.  Adjust the corresponding REG_LIBCALL note.  */
11066           if (GET_CODE (from_insn) != NOTE)
11067             place = from_insn;
11068           else
11069             {
11070               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11071               place = prev_real_insn (from_insn);
11072               if (tem && place)
11073                 XEXP (tem, 0) = place;
11074             }
11075           break;
11076
11077         case REG_LIBCALL:
11078           /* This is handled similarly to REG_RETVAL.  */
11079           if (GET_CODE (from_insn) != NOTE)
11080             place = from_insn;
11081           else
11082             {
11083               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11084               place = next_real_insn (from_insn);
11085               if (tem && place)
11086                 XEXP (tem, 0) = place;
11087             }
11088           break;
11089
11090         case REG_DEAD:
11091           /* If the register is used as an input in I3, it dies there.
11092              Similarly for I2, if it is non-zero and adjacent to I3.
11093
11094              If the register is not used as an input in either I3 or I2
11095              and it is not one of the registers we were supposed to eliminate,
11096              there are two possibilities.  We might have a non-adjacent I2
11097              or we might have somehow eliminated an additional register
11098              from a computation.  For example, we might have had A & B where
11099              we discover that B will always be zero.  In this case we will
11100              eliminate the reference to A.
11101
11102              In both cases, we must search to see if we can find a previous
11103              use of A and put the death note there.  */
11104
11105           if (from_insn
11106               && GET_CODE (from_insn) == CALL_INSN
11107               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11108             place = from_insn;
11109           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11110             place = i3;
11111           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11112                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11113             place = i2;
11114
11115           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11116             break;
11117
11118           /* If the register is used in both I2 and I3 and it dies in I3,
11119              we might have added another reference to it.  If reg_n_refs
11120              was 2, bump it to 3.  This has to be correct since the
11121              register must have been set somewhere.  The reason this is
11122              done is because local-alloc.c treats 2 references as a
11123              special case.  */
11124
11125           if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11126               && reg_n_refs[REGNO (XEXP (note, 0))]== 2
11127               && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11128             reg_n_refs[REGNO (XEXP (note, 0))] = 3;
11129
11130           if (place == 0)
11131             {
11132               for (tem = prev_nonnote_insn (i3);
11133                    place == 0 && tem
11134                    && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11135                    tem = prev_nonnote_insn (tem))
11136                 {
11137                   /* If the register is being set at TEM, see if that is all
11138                      TEM is doing.  If so, delete TEM.  Otherwise, make this
11139                      into a REG_UNUSED note instead.  */
11140                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11141                     {
11142                       rtx set = single_set (tem);
11143
11144                       /* Verify that it was the set, and not a clobber that
11145                          modified the register.  */
11146
11147                       if (set != 0 && ! side_effects_p (SET_SRC (set))
11148                           && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11149                               || (GET_CODE (SET_DEST (set)) == SUBREG
11150                                   && rtx_equal_p (XEXP (note, 0),
11151                                                   XEXP (SET_DEST (set), 0)))))
11152                         {
11153                           /* Move the notes and links of TEM elsewhere.
11154                              This might delete other dead insns recursively.
11155                              First set the pattern to something that won't use
11156                              any register.  */
11157
11158                           PATTERN (tem) = pc_rtx;
11159
11160                           distribute_notes (REG_NOTES (tem), tem, tem,
11161                                             NULL_RTX, NULL_RTX, NULL_RTX);
11162                           distribute_links (LOG_LINKS (tem));
11163
11164                           PUT_CODE (tem, NOTE);
11165                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11166                           NOTE_SOURCE_FILE (tem) = 0;
11167                         }
11168                       else
11169                         {
11170                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
11171
11172                           /*  If there isn't already a REG_UNUSED note, put one
11173                               here.  */
11174                           if (! find_regno_note (tem, REG_UNUSED,
11175                                                  REGNO (XEXP (note, 0))))
11176                             place = tem;
11177                           break;
11178                       }
11179                   }
11180                 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11181                          || (GET_CODE (tem) == CALL_INSN
11182                              && find_reg_fusage (tem, USE, XEXP (note, 0))))
11183                   {
11184                     place = tem;
11185
11186                     /* If we are doing a 3->2 combination, and we have a
11187                        register which formerly died in i3 and was not used
11188                        by i2, which now no longer dies in i3 and is used in
11189                        i2 but does not die in i2, and place is between i2
11190                        and i3, then we may need to move a link from place to
11191                        i2.  */
11192                     if (i2 && INSN_UID (place) <= max_uid_cuid
11193                         && INSN_CUID (place) > INSN_CUID (i2)
11194                         && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11195                         && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11196                       {
11197                         rtx links = LOG_LINKS (place);
11198                         LOG_LINKS (place) = 0;
11199                         distribute_links (links);
11200                       }
11201                     break;
11202                   }
11203                 }
11204
11205               /* If we haven't found an insn for the death note and it
11206                  is still a REG_DEAD note, but we have hit a CODE_LABEL,
11207                  insert a USE insn for the register at that label and
11208                  put the death node there.  This prevents problems with
11209                  call-state tracking in caller-save.c.  */
11210               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11211                 {
11212                   place
11213                     = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11214                                        tem);
11215
11216                   /* If this insn was emitted between blocks, then update
11217                      basic_block_head of the current block to include it.  */
11218                   if (basic_block_end[this_basic_block - 1] == tem)
11219                     basic_block_head[this_basic_block] = place;
11220                 }
11221             }
11222
11223           /* If the register is set or already dead at PLACE, we needn't do
11224              anything with this note if it is still a REG_DEAD note.
11225
11226              Note that we cannot use just `dead_or_set_p' here since we can
11227              convert an assignment to a register into a bit-field assignment.
11228              Therefore, we must also omit the note if the register is the
11229              target of a bitfield assignment.  */
11230
11231           if (place && REG_NOTE_KIND (note) == REG_DEAD)
11232             {
11233               int regno = REGNO (XEXP (note, 0));
11234
11235               if (dead_or_set_p (place, XEXP (note, 0))
11236                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11237                 {
11238                   /* Unless the register previously died in PLACE, clear
11239                      reg_last_death.  [I no longer understand why this is
11240                      being done.] */
11241                   if (reg_last_death[regno] != place)
11242                     reg_last_death[regno] = 0;
11243                   place = 0;
11244                 }
11245               else
11246                 reg_last_death[regno] = place;
11247
11248               /* If this is a death note for a hard reg that is occupying
11249                  multiple registers, ensure that we are still using all
11250                  parts of the object.  If we find a piece of the object
11251                  that is unused, we must add a USE for that piece before
11252                  PLACE and put the appropriate REG_DEAD note on it.
11253
11254                  An alternative would be to put a REG_UNUSED for the pieces
11255                  on the insn that set the register, but that can't be done if
11256                  it is not in the same block.  It is simpler, though less
11257                  efficient, to add the USE insns.  */
11258
11259               if (place && regno < FIRST_PSEUDO_REGISTER
11260                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11261                 {
11262                   int endregno
11263                     = regno + HARD_REGNO_NREGS (regno,
11264                                                 GET_MODE (XEXP (note, 0)));
11265                   int all_used = 1;
11266                   int i;
11267
11268                   for (i = regno; i < endregno; i++)
11269                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11270                         && ! find_regno_fusage (place, USE, i))
11271                       {
11272                         rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11273                         rtx p;
11274
11275                         /* See if we already placed a USE note for this
11276                            register in front of PLACE.  */
11277                         for (p = place;
11278                              GET_CODE (PREV_INSN (p)) == INSN
11279                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11280                              p = PREV_INSN (p))
11281                           if (rtx_equal_p (piece,
11282                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
11283                             {
11284                               p = 0;
11285                               break;
11286                             }
11287
11288                         if (p)
11289                           {
11290                             rtx use_insn
11291                               = emit_insn_before (gen_rtx (USE, VOIDmode,
11292                                                            piece),
11293                                                   p);
11294                             REG_NOTES (use_insn)
11295                               = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11296                                          REG_NOTES (use_insn));
11297                           }
11298
11299                         all_used = 0;
11300                       }
11301
11302                   /* Check for the case where the register dying partially
11303                      overlaps the register set by this insn.  */
11304                   if (all_used)
11305                     for (i = regno; i < endregno; i++)
11306                       if (dead_or_set_regno_p (place, i))
11307                           {
11308                             all_used = 0;
11309                             break;
11310                           }
11311
11312                   if (! all_used)
11313                     {
11314                       /* Put only REG_DEAD notes for pieces that are
11315                          still used and that are not already dead or set.  */
11316
11317                       for (i = regno; i < endregno; i++)
11318                         {
11319                           rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11320
11321                           if ((reg_referenced_p (piece, PATTERN (place))
11322                                || (GET_CODE (place) == CALL_INSN
11323                                    && find_reg_fusage (place, USE, piece)))
11324                               && ! dead_or_set_p (place, piece)
11325                               && ! reg_bitfield_target_p (piece,
11326                                                           PATTERN (place)))
11327                             REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11328                                                          piece,
11329                                                          REG_NOTES (place));
11330                         }
11331
11332                       place = 0;
11333                     }
11334                 }
11335             }
11336           break;
11337
11338         default:
11339           /* Any other notes should not be present at this point in the
11340              compilation.  */
11341           abort ();
11342         }
11343
11344       if (place)
11345         {
11346           XEXP (note, 1) = REG_NOTES (place);
11347           REG_NOTES (place) = note;
11348         }
11349       else if ((REG_NOTE_KIND (note) == REG_DEAD
11350                 || REG_NOTE_KIND (note) == REG_UNUSED)
11351                && GET_CODE (XEXP (note, 0)) == REG)
11352         reg_n_deaths[REGNO (XEXP (note, 0))]--;
11353
11354       if (place2)
11355         {
11356           if ((REG_NOTE_KIND (note) == REG_DEAD
11357                || REG_NOTE_KIND (note) == REG_UNUSED)
11358               && GET_CODE (XEXP (note, 0)) == REG)
11359             reg_n_deaths[REGNO (XEXP (note, 0))]++;
11360
11361           REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11362                                         XEXP (note, 0), REG_NOTES (place2));
11363         }
11364     }
11365 }
11366 \f
11367 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11368    I3, I2, and I1 to new locations.  This is also called in one case to
11369    add a link pointing at I3 when I3's destination is changed.  */
11370
11371 static void
11372 distribute_links (links)
11373      rtx links;
11374 {
11375   rtx link, next_link;
11376
11377   for (link = links; link; link = next_link)
11378     {
11379       rtx place = 0;
11380       rtx insn;
11381       rtx set, reg;
11382
11383       next_link = XEXP (link, 1);
11384
11385       /* If the insn that this link points to is a NOTE or isn't a single
11386          set, ignore it.  In the latter case, it isn't clear what we
11387          can do other than ignore the link, since we can't tell which
11388          register it was for.  Such links wouldn't be used by combine
11389          anyway.
11390
11391          It is not possible for the destination of the target of the link to
11392          have been changed by combine.  The only potential of this is if we
11393          replace I3, I2, and I1 by I3 and I2.  But in that case the
11394          destination of I2 also remains unchanged.  */
11395
11396       if (GET_CODE (XEXP (link, 0)) == NOTE
11397           || (set = single_set (XEXP (link, 0))) == 0)
11398         continue;
11399
11400       reg = SET_DEST (set);
11401       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11402              || GET_CODE (reg) == SIGN_EXTRACT
11403              || GET_CODE (reg) == STRICT_LOW_PART)
11404         reg = XEXP (reg, 0);
11405
11406       /* A LOG_LINK is defined as being placed on the first insn that uses
11407          a register and points to the insn that sets the register.  Start
11408          searching at the next insn after the target of the link and stop
11409          when we reach a set of the register or the end of the basic block.
11410
11411          Note that this correctly handles the link that used to point from
11412          I3 to I2.  Also note that not much searching is typically done here
11413          since most links don't point very far away.  */
11414
11415       for (insn = NEXT_INSN (XEXP (link, 0));
11416            (insn && (this_basic_block == n_basic_blocks - 1
11417                      || basic_block_head[this_basic_block + 1] != insn));
11418            insn = NEXT_INSN (insn))
11419         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11420             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11421           {
11422             if (reg_referenced_p (reg, PATTERN (insn)))
11423               place = insn;
11424             break;
11425           }
11426         else if (GET_CODE (insn) == CALL_INSN
11427               && find_reg_fusage (insn, USE, reg))
11428           {
11429             place = insn;
11430             break;
11431           }
11432
11433       /* If we found a place to put the link, place it there unless there
11434          is already a link to the same insn as LINK at that point.  */
11435
11436       if (place)
11437         {
11438           rtx link2;
11439
11440           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11441             if (XEXP (link2, 0) == XEXP (link, 0))
11442               break;
11443
11444           if (link2 == 0)
11445             {
11446               XEXP (link, 1) = LOG_LINKS (place);
11447               LOG_LINKS (place) = link;
11448
11449               /* Set added_links_insn to the earliest insn we added a
11450                  link to.  */
11451               if (added_links_insn == 0
11452                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
11453                 added_links_insn = place;
11454             }
11455         }
11456     }
11457 }
11458 \f
11459 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
11460
11461 static int
11462 insn_cuid (insn)
11463      rtx insn;
11464 {
11465   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11466          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11467     insn = NEXT_INSN (insn);
11468
11469   if (INSN_UID (insn) > max_uid_cuid)
11470     abort ();
11471
11472   return INSN_CUID (insn);
11473 }
11474 \f
11475 void
11476 dump_combine_stats (file)
11477      FILE *file;
11478 {
11479   fprintf
11480     (file,
11481      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11482      combine_attempts, combine_merges, combine_extras, combine_successes);
11483 }
11484
11485 void
11486 dump_combine_total_stats (file)
11487      FILE *file;
11488 {
11489   fprintf
11490     (file,
11491      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11492      total_attempts, total_merges, total_extras, total_successes);
11493 }