1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
35 #include "diagnostic-core.h"
39 /* Simplification and canonicalization of RTL. */
41 /* Much code operates on (low, high) pairs; the low value is an
42 unsigned wide int, the high value a signed wide int. We
43 occasionally need to sign extend from low to high as if low were a
45 #define HWI_SIGN_EXTEND(low) \
46 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
48 static rtx
neg_const_int (enum machine_mode
, const_rtx
);
49 static bool plus_minus_operand_p (const_rtx
);
50 static bool simplify_plus_minus_op_data_cmp (rtx
, rtx
);
51 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
52 static rtx
simplify_immed_subreg (enum machine_mode
, rtx
, enum machine_mode
,
54 static rtx
simplify_associative_operation (enum rtx_code
, enum machine_mode
,
56 static rtx
simplify_relational_operation_1 (enum rtx_code
, enum machine_mode
,
57 enum machine_mode
, rtx
, rtx
);
58 static rtx
simplify_unary_operation_1 (enum rtx_code
, enum machine_mode
, rtx
);
59 static rtx
simplify_binary_operation_1 (enum rtx_code
, enum machine_mode
,
62 /* Negate a CONST_INT rtx, truncating (because a conversion from a
63 maximally negative number can overflow). */
65 neg_const_int (enum machine_mode mode
, const_rtx i
)
67 return gen_int_mode (-(unsigned HOST_WIDE_INT
) INTVAL (i
), mode
);
70 /* Test whether expression, X, is an immediate constant that represents
71 the most significant bit of machine mode MODE. */
74 mode_signbit_p (enum machine_mode mode
, const_rtx x
)
76 unsigned HOST_WIDE_INT val
;
79 if (GET_MODE_CLASS (mode
) != MODE_INT
)
82 width
= GET_MODE_PRECISION (mode
);
86 if (width
<= HOST_BITS_PER_WIDE_INT
89 else if (width
<= HOST_BITS_PER_DOUBLE_INT
90 && CONST_DOUBLE_AS_INT_P (x
)
91 && CONST_DOUBLE_LOW (x
) == 0)
93 val
= CONST_DOUBLE_HIGH (x
);
94 width
-= HOST_BITS_PER_WIDE_INT
;
97 /* FIXME: We don't yet have a representation for wider modes. */
100 if (width
< HOST_BITS_PER_WIDE_INT
)
101 val
&= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
102 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
105 /* Test whether VAL is equal to the most significant bit of mode MODE
106 (after masking with the mode mask of MODE). Returns false if the
107 precision of MODE is too large to handle. */
110 val_signbit_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
114 if (GET_MODE_CLASS (mode
) != MODE_INT
)
117 width
= GET_MODE_PRECISION (mode
);
118 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
121 val
&= GET_MODE_MASK (mode
);
122 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
125 /* Test whether the most significant bit of mode MODE is set in VAL.
126 Returns false if the precision of MODE is too large to handle. */
128 val_signbit_known_set_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
132 if (GET_MODE_CLASS (mode
) != MODE_INT
)
135 width
= GET_MODE_PRECISION (mode
);
136 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
139 val
&= (unsigned HOST_WIDE_INT
) 1 << (width
- 1);
143 /* Test whether the most significant bit of mode MODE is clear in VAL.
144 Returns false if the precision of MODE is too large to handle. */
146 val_signbit_known_clear_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
150 if (GET_MODE_CLASS (mode
) != MODE_INT
)
153 width
= GET_MODE_PRECISION (mode
);
154 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
157 val
&= (unsigned HOST_WIDE_INT
) 1 << (width
- 1);
161 /* Make a binary operation by properly ordering the operands and
162 seeing if the expression folds. */
165 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
170 /* If this simplifies, do it. */
171 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
175 /* Put complex operands first and constants second if commutative. */
176 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
177 && swap_commutative_operands_p (op0
, op1
))
178 tem
= op0
, op0
= op1
, op1
= tem
;
180 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
183 /* If X is a MEM referencing the constant pool, return the real value.
184 Otherwise return X. */
186 avoid_constant_pool_reference (rtx x
)
189 enum machine_mode cmode
;
190 HOST_WIDE_INT offset
= 0;
192 switch (GET_CODE (x
))
198 /* Handle float extensions of constant pool references. */
200 c
= avoid_constant_pool_reference (tmp
);
201 if (c
!= tmp
&& CONST_DOUBLE_AS_FLOAT_P (c
))
205 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
206 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
214 if (GET_MODE (x
) == BLKmode
)
219 /* Call target hook to avoid the effects of -fpic etc.... */
220 addr
= targetm
.delegitimize_address (addr
);
222 /* Split the address into a base and integer offset. */
223 if (GET_CODE (addr
) == CONST
224 && GET_CODE (XEXP (addr
, 0)) == PLUS
225 && CONST_INT_P (XEXP (XEXP (addr
, 0), 1)))
227 offset
= INTVAL (XEXP (XEXP (addr
, 0), 1));
228 addr
= XEXP (XEXP (addr
, 0), 0);
231 if (GET_CODE (addr
) == LO_SUM
)
232 addr
= XEXP (addr
, 1);
234 /* If this is a constant pool reference, we can turn it into its
235 constant and hope that simplifications happen. */
236 if (GET_CODE (addr
) == SYMBOL_REF
237 && CONSTANT_POOL_ADDRESS_P (addr
))
239 c
= get_pool_constant (addr
);
240 cmode
= get_pool_mode (addr
);
242 /* If we're accessing the constant in a different mode than it was
243 originally stored, attempt to fix that up via subreg simplifications.
244 If that fails we have no choice but to return the original memory. */
245 if ((offset
!= 0 || cmode
!= GET_MODE (x
))
246 && offset
>= 0 && offset
< GET_MODE_SIZE (cmode
))
248 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
249 if (tem
&& CONSTANT_P (tem
))
259 /* Simplify a MEM based on its attributes. This is the default
260 delegitimize_address target hook, and it's recommended that every
261 overrider call it. */
264 delegitimize_mem_from_attrs (rtx x
)
266 /* MEMs without MEM_OFFSETs may have been offset, so we can't just
267 use their base addresses as equivalent. */
270 && MEM_OFFSET_KNOWN_P (x
))
272 tree decl
= MEM_EXPR (x
);
273 enum machine_mode mode
= GET_MODE (x
);
274 HOST_WIDE_INT offset
= 0;
276 switch (TREE_CODE (decl
))
286 case ARRAY_RANGE_REF
:
291 case VIEW_CONVERT_EXPR
:
293 HOST_WIDE_INT bitsize
, bitpos
;
295 int unsignedp
, volatilep
= 0;
297 decl
= get_inner_reference (decl
, &bitsize
, &bitpos
, &toffset
,
298 &mode
, &unsignedp
, &volatilep
, false);
299 if (bitsize
!= GET_MODE_BITSIZE (mode
)
300 || (bitpos
% BITS_PER_UNIT
)
301 || (toffset
&& !host_integerp (toffset
, 0)))
305 offset
+= bitpos
/ BITS_PER_UNIT
;
307 offset
+= TREE_INT_CST_LOW (toffset
);
314 && mode
== GET_MODE (x
)
315 && TREE_CODE (decl
) == VAR_DECL
316 && (TREE_STATIC (decl
)
317 || DECL_THREAD_LOCAL_P (decl
))
318 && DECL_RTL_SET_P (decl
)
319 && MEM_P (DECL_RTL (decl
)))
323 offset
+= MEM_OFFSET (x
);
325 newx
= DECL_RTL (decl
);
329 rtx n
= XEXP (newx
, 0), o
= XEXP (x
, 0);
331 /* Avoid creating a new MEM needlessly if we already had
332 the same address. We do if there's no OFFSET and the
333 old address X is identical to NEWX, or if X is of the
334 form (plus NEWX OFFSET), or the NEWX is of the form
335 (plus Y (const_int Z)) and X is that with the offset
336 added: (plus Y (const_int Z+OFFSET)). */
338 || (GET_CODE (o
) == PLUS
339 && GET_CODE (XEXP (o
, 1)) == CONST_INT
340 && (offset
== INTVAL (XEXP (o
, 1))
341 || (GET_CODE (n
) == PLUS
342 && GET_CODE (XEXP (n
, 1)) == CONST_INT
343 && (INTVAL (XEXP (n
, 1)) + offset
344 == INTVAL (XEXP (o
, 1)))
345 && (n
= XEXP (n
, 0))))
346 && (o
= XEXP (o
, 0))))
347 && rtx_equal_p (o
, n
)))
348 x
= adjust_address_nv (newx
, mode
, offset
);
350 else if (GET_MODE (x
) == GET_MODE (newx
)
359 /* Make a unary operation by first seeing if it folds and otherwise making
360 the specified operation. */
363 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
364 enum machine_mode op_mode
)
368 /* If this simplifies, use it. */
369 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
372 return gen_rtx_fmt_e (code
, mode
, op
);
375 /* Likewise for ternary operations. */
378 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
379 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
383 /* If this simplifies, use it. */
384 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
388 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
391 /* Likewise, for relational operations.
392 CMP_MODE specifies mode comparison is done in. */
395 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
396 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
400 if (0 != (tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
404 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
407 /* If FN is NULL, replace all occurrences of OLD_RTX in X with copy_rtx (DATA)
408 and simplify the result. If FN is non-NULL, call this callback on each
409 X, if it returns non-NULL, replace X with its return value and simplify the
413 simplify_replace_fn_rtx (rtx x
, const_rtx old_rtx
,
414 rtx (*fn
) (rtx
, const_rtx
, void *), void *data
)
416 enum rtx_code code
= GET_CODE (x
);
417 enum machine_mode mode
= GET_MODE (x
);
418 enum machine_mode op_mode
;
420 rtx op0
, op1
, op2
, newx
, op
;
424 if (__builtin_expect (fn
!= NULL
, 0))
426 newx
= fn (x
, old_rtx
, data
);
430 else if (rtx_equal_p (x
, old_rtx
))
431 return copy_rtx ((rtx
) data
);
433 switch (GET_RTX_CLASS (code
))
437 op_mode
= GET_MODE (op0
);
438 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
439 if (op0
== XEXP (x
, 0))
441 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
445 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
446 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
447 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
449 return simplify_gen_binary (code
, mode
, op0
, op1
);
452 case RTX_COMM_COMPARE
:
455 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
456 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
457 op1
= simplify_replace_fn_rtx (op1
, old_rtx
, fn
, data
);
458 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
460 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
463 case RTX_BITFIELD_OPS
:
465 op_mode
= GET_MODE (op0
);
466 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
467 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
468 op2
= simplify_replace_fn_rtx (XEXP (x
, 2), old_rtx
, fn
, data
);
469 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
471 if (op_mode
== VOIDmode
)
472 op_mode
= GET_MODE (op0
);
473 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
478 op0
= simplify_replace_fn_rtx (SUBREG_REG (x
), old_rtx
, fn
, data
);
479 if (op0
== SUBREG_REG (x
))
481 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
482 GET_MODE (SUBREG_REG (x
)),
484 return op0
? op0
: x
;
491 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
492 if (op0
== XEXP (x
, 0))
494 return replace_equiv_address_nv (x
, op0
);
496 else if (code
== LO_SUM
)
498 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
499 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
501 /* (lo_sum (high x) x) -> x */
502 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
505 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
507 return gen_rtx_LO_SUM (mode
, op0
, op1
);
516 fmt
= GET_RTX_FORMAT (code
);
517 for (i
= 0; fmt
[i
]; i
++)
522 newvec
= XVEC (newx
, i
);
523 for (j
= 0; j
< GET_NUM_ELEM (vec
); j
++)
525 op
= simplify_replace_fn_rtx (RTVEC_ELT (vec
, j
),
527 if (op
!= RTVEC_ELT (vec
, j
))
531 newvec
= shallow_copy_rtvec (vec
);
533 newx
= shallow_copy_rtx (x
);
534 XVEC (newx
, i
) = newvec
;
536 RTVEC_ELT (newvec
, j
) = op
;
544 op
= simplify_replace_fn_rtx (XEXP (x
, i
), old_rtx
, fn
, data
);
545 if (op
!= XEXP (x
, i
))
548 newx
= shallow_copy_rtx (x
);
557 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
558 resulting RTX. Return a new RTX which is as simplified as possible. */
561 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
563 return simplify_replace_fn_rtx (x
, old_rtx
, 0, new_rtx
);
566 /* Try to simplify a MODE truncation of OP, which has OP_MODE.
567 Only handle cases where the truncated value is inherently an rvalue.
569 RTL provides two ways of truncating a value:
571 1. a lowpart subreg. This form is only a truncation when both
572 the outer and inner modes (here MODE and OP_MODE respectively)
573 are scalar integers, and only then when the subreg is used as
576 It is only valid to form such truncating subregs if the
577 truncation requires no action by the target. The onus for
578 proving this is on the creator of the subreg -- e.g. the
579 caller to simplify_subreg or simplify_gen_subreg -- and typically
580 involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
582 2. a TRUNCATE. This form handles both scalar and compound integers.
584 The first form is preferred where valid. However, the TRUNCATE
585 handling in simplify_unary_operation turns the second form into the
586 first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
587 so it is generally safe to form rvalue truncations using:
589 simplify_gen_unary (TRUNCATE, ...)
591 and leave simplify_unary_operation to work out which representation
594 Because of the proof requirements on (1), simplify_truncation must
595 also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
596 regardless of whether the outer truncation came from a SUBREG or a
597 TRUNCATE. For example, if the caller has proven that an SImode
602 is a no-op and can be represented as a subreg, it does not follow
603 that SImode truncations of X and Y are also no-ops. On a target
604 like 64-bit MIPS that requires SImode values to be stored in
605 sign-extended form, an SImode truncation of:
607 (and:DI (reg:DI X) (const_int 63))
609 is trivially a no-op because only the lower 6 bits can be set.
610 However, X is still an arbitrary 64-bit number and so we cannot
611 assume that truncating it too is a no-op. */
614 simplify_truncation (enum machine_mode mode
, rtx op
,
615 enum machine_mode op_mode
)
617 unsigned int precision
= GET_MODE_UNIT_PRECISION (mode
);
618 unsigned int op_precision
= GET_MODE_UNIT_PRECISION (op_mode
);
619 gcc_assert (precision
<= op_precision
);
621 /* Optimize truncations of zero and sign extended values. */
622 if (GET_CODE (op
) == ZERO_EXTEND
623 || GET_CODE (op
) == SIGN_EXTEND
)
625 /* There are three possibilities. If MODE is the same as the
626 origmode, we can omit both the extension and the subreg.
627 If MODE is not larger than the origmode, we can apply the
628 truncation without the extension. Finally, if the outermode
629 is larger than the origmode, we can just extend to the appropriate
631 enum machine_mode origmode
= GET_MODE (XEXP (op
, 0));
632 if (mode
== origmode
)
634 else if (precision
<= GET_MODE_UNIT_PRECISION (origmode
))
635 return simplify_gen_unary (TRUNCATE
, mode
,
636 XEXP (op
, 0), origmode
);
638 return simplify_gen_unary (GET_CODE (op
), mode
,
639 XEXP (op
, 0), origmode
);
642 /* If the machine can perform operations in the truncated mode, distribute
643 the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
644 (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
646 #ifdef WORD_REGISTER_OPERATIONS
647 && precision
>= BITS_PER_WORD
649 && (GET_CODE (op
) == PLUS
650 || GET_CODE (op
) == MINUS
651 || GET_CODE (op
) == MULT
))
653 rtx op0
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0), op_mode
);
656 rtx op1
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 1), op_mode
);
658 return simplify_gen_binary (GET_CODE (op
), mode
, op0
, op1
);
662 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
663 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
664 the outer subreg is effectively a truncation to the original mode. */
665 if ((GET_CODE (op
) == LSHIFTRT
666 || GET_CODE (op
) == ASHIFTRT
)
667 /* Ensure that OP_MODE is at least twice as wide as MODE
668 to avoid the possibility that an outer LSHIFTRT shifts by more
669 than the sign extension's sign_bit_copies and introduces zeros
670 into the high bits of the result. */
671 && 2 * precision
<= op_precision
672 && CONST_INT_P (XEXP (op
, 1))
673 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
674 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
675 && UINTVAL (XEXP (op
, 1)) < precision
)
676 return simplify_gen_binary (ASHIFTRT
, mode
,
677 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
679 /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
680 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
681 the outer subreg is effectively a truncation to the original mode. */
682 if ((GET_CODE (op
) == LSHIFTRT
683 || GET_CODE (op
) == ASHIFTRT
)
684 && CONST_INT_P (XEXP (op
, 1))
685 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
686 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
687 && UINTVAL (XEXP (op
, 1)) < precision
)
688 return simplify_gen_binary (LSHIFTRT
, mode
,
689 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
691 /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
692 to (ashift:QI (x:QI) C), where C is a suitable small constant and
693 the outer subreg is effectively a truncation to the original mode. */
694 if (GET_CODE (op
) == ASHIFT
695 && CONST_INT_P (XEXP (op
, 1))
696 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
697 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
698 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
699 && UINTVAL (XEXP (op
, 1)) < precision
)
700 return simplify_gen_binary (ASHIFT
, mode
,
701 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
703 /* Recognize a word extraction from a multi-word subreg. */
704 if ((GET_CODE (op
) == LSHIFTRT
705 || GET_CODE (op
) == ASHIFTRT
)
706 && SCALAR_INT_MODE_P (mode
)
707 && SCALAR_INT_MODE_P (op_mode
)
708 && precision
>= BITS_PER_WORD
709 && 2 * precision
<= op_precision
710 && CONST_INT_P (XEXP (op
, 1))
711 && (INTVAL (XEXP (op
, 1)) & (precision
- 1)) == 0
712 && UINTVAL (XEXP (op
, 1)) < op_precision
)
714 int byte
= subreg_lowpart_offset (mode
, op_mode
);
715 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
716 return simplify_gen_subreg (mode
, XEXP (op
, 0), op_mode
,
718 ? byte
- shifted_bytes
719 : byte
+ shifted_bytes
));
722 /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
723 and try replacing the TRUNCATE and shift with it. Don't do this
724 if the MEM has a mode-dependent address. */
725 if ((GET_CODE (op
) == LSHIFTRT
726 || GET_CODE (op
) == ASHIFTRT
)
727 && SCALAR_INT_MODE_P (op_mode
)
728 && MEM_P (XEXP (op
, 0))
729 && CONST_INT_P (XEXP (op
, 1))
730 && (INTVAL (XEXP (op
, 1)) % GET_MODE_BITSIZE (mode
)) == 0
731 && INTVAL (XEXP (op
, 1)) > 0
732 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (op_mode
)
733 && ! mode_dependent_address_p (XEXP (XEXP (op
, 0), 0),
734 MEM_ADDR_SPACE (XEXP (op
, 0)))
735 && ! MEM_VOLATILE_P (XEXP (op
, 0))
736 && (GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
737 || WORDS_BIG_ENDIAN
== BYTES_BIG_ENDIAN
))
739 int byte
= subreg_lowpart_offset (mode
, op_mode
);
740 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
741 return adjust_address_nv (XEXP (op
, 0), mode
,
743 ? byte
- shifted_bytes
744 : byte
+ shifted_bytes
));
747 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
748 (OP:SI foo:SI) if OP is NEG or ABS. */
749 if ((GET_CODE (op
) == ABS
750 || GET_CODE (op
) == NEG
)
751 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
752 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
753 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
754 return simplify_gen_unary (GET_CODE (op
), mode
,
755 XEXP (XEXP (op
, 0), 0), mode
);
757 /* (truncate:A (subreg:B (truncate:C X) 0)) is
759 if (GET_CODE (op
) == SUBREG
760 && SCALAR_INT_MODE_P (mode
)
761 && SCALAR_INT_MODE_P (op_mode
)
762 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op
)))
763 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
764 && subreg_lowpart_p (op
))
766 rtx inner
= XEXP (SUBREG_REG (op
), 0);
767 if (GET_MODE_PRECISION (mode
)
768 <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
))))
769 return simplify_gen_unary (TRUNCATE
, mode
, inner
, GET_MODE (inner
));
771 /* If subreg above is paradoxical and C is narrower
772 than A, return (subreg:A (truncate:C X) 0). */
773 return simplify_gen_subreg (mode
, SUBREG_REG (op
),
774 GET_MODE (SUBREG_REG (op
)), 0);
777 /* (truncate:A (truncate:B X)) is (truncate:A X). */
778 if (GET_CODE (op
) == TRUNCATE
)
779 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0),
780 GET_MODE (XEXP (op
, 0)));
785 /* Try to simplify a unary operation CODE whose output mode is to be
786 MODE with input operand OP whose mode was originally OP_MODE.
787 Return zero if no simplification can be made. */
789 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
790 rtx op
, enum machine_mode op_mode
)
794 trueop
= avoid_constant_pool_reference (op
);
796 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
800 return simplify_unary_operation_1 (code
, mode
, op
);
803 /* Perform some simplifications we can do even if the operands
806 simplify_unary_operation_1 (enum rtx_code code
, enum machine_mode mode
, rtx op
)
808 enum rtx_code reversed
;
814 /* (not (not X)) == X. */
815 if (GET_CODE (op
) == NOT
)
818 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
819 comparison is all ones. */
820 if (COMPARISON_P (op
)
821 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
822 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
)) != UNKNOWN
))
823 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
824 XEXP (op
, 0), XEXP (op
, 1));
826 /* (not (plus X -1)) can become (neg X). */
827 if (GET_CODE (op
) == PLUS
828 && XEXP (op
, 1) == constm1_rtx
)
829 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
831 /* Similarly, (not (neg X)) is (plus X -1). */
832 if (GET_CODE (op
) == NEG
)
833 return plus_constant (mode
, XEXP (op
, 0), -1);
835 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
836 if (GET_CODE (op
) == XOR
837 && CONST_INT_P (XEXP (op
, 1))
838 && (temp
= simplify_unary_operation (NOT
, mode
,
839 XEXP (op
, 1), mode
)) != 0)
840 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
842 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
843 if (GET_CODE (op
) == PLUS
844 && CONST_INT_P (XEXP (op
, 1))
845 && mode_signbit_p (mode
, XEXP (op
, 1))
846 && (temp
= simplify_unary_operation (NOT
, mode
,
847 XEXP (op
, 1), mode
)) != 0)
848 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
851 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
852 operands other than 1, but that is not valid. We could do a
853 similar simplification for (not (lshiftrt C X)) where C is
854 just the sign bit, but this doesn't seem common enough to
856 if (GET_CODE (op
) == ASHIFT
857 && XEXP (op
, 0) == const1_rtx
)
859 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
860 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
863 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
864 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
865 so we can perform the above simplification. */
867 if (STORE_FLAG_VALUE
== -1
868 && GET_CODE (op
) == ASHIFTRT
869 && GET_CODE (XEXP (op
, 1))
870 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
871 return simplify_gen_relational (GE
, mode
, VOIDmode
,
872 XEXP (op
, 0), const0_rtx
);
875 if (GET_CODE (op
) == SUBREG
876 && subreg_lowpart_p (op
)
877 && (GET_MODE_SIZE (GET_MODE (op
))
878 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
879 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
880 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
882 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
885 x
= gen_rtx_ROTATE (inner_mode
,
886 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
888 XEXP (SUBREG_REG (op
), 1));
889 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
894 /* Apply De Morgan's laws to reduce number of patterns for machines
895 with negating logical insns (and-not, nand, etc.). If result has
896 only one NOT, put it first, since that is how the patterns are
899 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
901 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
902 enum machine_mode op_mode
;
904 op_mode
= GET_MODE (in1
);
905 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
907 op_mode
= GET_MODE (in2
);
908 if (op_mode
== VOIDmode
)
910 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
912 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
915 in2
= in1
; in1
= tem
;
918 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
924 /* (neg (neg X)) == X. */
925 if (GET_CODE (op
) == NEG
)
928 /* (neg (plus X 1)) can become (not X). */
929 if (GET_CODE (op
) == PLUS
930 && XEXP (op
, 1) == const1_rtx
)
931 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
933 /* Similarly, (neg (not X)) is (plus X 1). */
934 if (GET_CODE (op
) == NOT
)
935 return plus_constant (mode
, XEXP (op
, 0), 1);
937 /* (neg (minus X Y)) can become (minus Y X). This transformation
938 isn't safe for modes with signed zeros, since if X and Y are
939 both +0, (minus Y X) is the same as (minus X Y). If the
940 rounding mode is towards +infinity (or -infinity) then the two
941 expressions will be rounded differently. */
942 if (GET_CODE (op
) == MINUS
943 && !HONOR_SIGNED_ZEROS (mode
)
944 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
945 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
947 if (GET_CODE (op
) == PLUS
948 && !HONOR_SIGNED_ZEROS (mode
)
949 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
951 /* (neg (plus A C)) is simplified to (minus -C A). */
952 if (CONST_SCALAR_INT_P (XEXP (op
, 1))
953 || CONST_DOUBLE_AS_FLOAT_P (XEXP (op
, 1)))
955 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
957 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
960 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
961 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
962 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
965 /* (neg (mult A B)) becomes (mult A (neg B)).
966 This works even for floating-point values. */
967 if (GET_CODE (op
) == MULT
968 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
970 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 1), mode
);
971 return simplify_gen_binary (MULT
, mode
, XEXP (op
, 0), temp
);
974 /* NEG commutes with ASHIFT since it is multiplication. Only do
975 this if we can then eliminate the NEG (e.g., if the operand
977 if (GET_CODE (op
) == ASHIFT
)
979 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
981 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
984 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
985 C is equal to the width of MODE minus 1. */
986 if (GET_CODE (op
) == ASHIFTRT
987 && CONST_INT_P (XEXP (op
, 1))
988 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
989 return simplify_gen_binary (LSHIFTRT
, mode
,
990 XEXP (op
, 0), XEXP (op
, 1));
992 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
993 C is equal to the width of MODE minus 1. */
994 if (GET_CODE (op
) == LSHIFTRT
995 && CONST_INT_P (XEXP (op
, 1))
996 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
997 return simplify_gen_binary (ASHIFTRT
, mode
,
998 XEXP (op
, 0), XEXP (op
, 1));
1000 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
1001 if (GET_CODE (op
) == XOR
1002 && XEXP (op
, 1) == const1_rtx
1003 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
1004 return plus_constant (mode
, XEXP (op
, 0), -1);
1006 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
1007 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
1008 if (GET_CODE (op
) == LT
1009 && XEXP (op
, 1) == const0_rtx
1010 && SCALAR_INT_MODE_P (GET_MODE (XEXP (op
, 0))))
1012 enum machine_mode inner
= GET_MODE (XEXP (op
, 0));
1013 int isize
= GET_MODE_PRECISION (inner
);
1014 if (STORE_FLAG_VALUE
== 1)
1016 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
1017 GEN_INT (isize
- 1));
1020 if (GET_MODE_PRECISION (mode
) > isize
)
1021 return simplify_gen_unary (SIGN_EXTEND
, mode
, temp
, inner
);
1022 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
1024 else if (STORE_FLAG_VALUE
== -1)
1026 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
1027 GEN_INT (isize
- 1));
1030 if (GET_MODE_PRECISION (mode
) > isize
)
1031 return simplify_gen_unary (ZERO_EXTEND
, mode
, temp
, inner
);
1032 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
1038 /* Don't optimize (lshiftrt (mult ...)) as it would interfere
1039 with the umulXi3_highpart patterns. */
1040 if (GET_CODE (op
) == LSHIFTRT
1041 && GET_CODE (XEXP (op
, 0)) == MULT
)
1044 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
1046 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1048 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1052 /* We can't handle truncation to a partial integer mode here
1053 because we don't know the real bitsize of the partial
1058 if (GET_MODE (op
) != VOIDmode
)
1060 temp
= simplify_truncation (mode
, op
, GET_MODE (op
));
1065 /* If we know that the value is already truncated, we can
1066 replace the TRUNCATE with a SUBREG. */
1067 if (GET_MODE_NUNITS (mode
) == 1
1068 && (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
))
1069 || truncated_to_mode (mode
, op
)))
1071 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1076 /* A truncate of a comparison can be replaced with a subreg if
1077 STORE_FLAG_VALUE permits. This is like the previous test,
1078 but it works even if the comparison is done in a mode larger
1079 than HOST_BITS_PER_WIDE_INT. */
1080 if (HWI_COMPUTABLE_MODE_P (mode
)
1081 && COMPARISON_P (op
)
1082 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
1084 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1089 /* A truncate of a memory is just loading the low part of the memory
1090 if we are not changing the meaning of the address. */
1091 if (GET_CODE (op
) == MEM
1092 && !VECTOR_MODE_P (mode
)
1093 && !MEM_VOLATILE_P (op
)
1094 && !mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
)))
1096 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1103 case FLOAT_TRUNCATE
:
1104 if (DECIMAL_FLOAT_MODE_P (mode
))
1107 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
1108 if (GET_CODE (op
) == FLOAT_EXTEND
1109 && GET_MODE (XEXP (op
, 0)) == mode
)
1110 return XEXP (op
, 0);
1112 /* (float_truncate:SF (float_truncate:DF foo:XF))
1113 = (float_truncate:SF foo:XF).
1114 This may eliminate double rounding, so it is unsafe.
1116 (float_truncate:SF (float_extend:XF foo:DF))
1117 = (float_truncate:SF foo:DF).
1119 (float_truncate:DF (float_extend:XF foo:SF))
1120 = (float_extend:SF foo:DF). */
1121 if ((GET_CODE (op
) == FLOAT_TRUNCATE
1122 && flag_unsafe_math_optimizations
)
1123 || GET_CODE (op
) == FLOAT_EXTEND
)
1124 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (op
,
1126 > GET_MODE_SIZE (mode
)
1127 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
1129 XEXP (op
, 0), mode
);
1131 /* (float_truncate (float x)) is (float x) */
1132 if (GET_CODE (op
) == FLOAT
1133 && (flag_unsafe_math_optimizations
1134 || (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1135 && ((unsigned)significand_size (GET_MODE (op
))
1136 >= (GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))
1137 - num_sign_bit_copies (XEXP (op
, 0),
1138 GET_MODE (XEXP (op
, 0))))))))
1139 return simplify_gen_unary (FLOAT
, mode
,
1141 GET_MODE (XEXP (op
, 0)));
1143 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
1144 (OP:SF foo:SF) if OP is NEG or ABS. */
1145 if ((GET_CODE (op
) == ABS
1146 || GET_CODE (op
) == NEG
)
1147 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
1148 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
1149 return simplify_gen_unary (GET_CODE (op
), mode
,
1150 XEXP (XEXP (op
, 0), 0), mode
);
1152 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
1153 is (float_truncate:SF x). */
1154 if (GET_CODE (op
) == SUBREG
1155 && subreg_lowpart_p (op
)
1156 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
1157 return SUBREG_REG (op
);
1161 if (DECIMAL_FLOAT_MODE_P (mode
))
1164 /* (float_extend (float_extend x)) is (float_extend x)
1166 (float_extend (float x)) is (float x) assuming that double
1167 rounding can't happen.
1169 if (GET_CODE (op
) == FLOAT_EXTEND
1170 || (GET_CODE (op
) == FLOAT
1171 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1172 && ((unsigned)significand_size (GET_MODE (op
))
1173 >= (GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))
1174 - num_sign_bit_copies (XEXP (op
, 0),
1175 GET_MODE (XEXP (op
, 0)))))))
1176 return simplify_gen_unary (GET_CODE (op
), mode
,
1178 GET_MODE (XEXP (op
, 0)));
1183 /* (abs (neg <foo>)) -> (abs <foo>) */
1184 if (GET_CODE (op
) == NEG
)
1185 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
1186 GET_MODE (XEXP (op
, 0)));
1188 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
1190 if (GET_MODE (op
) == VOIDmode
)
1193 /* If operand is something known to be positive, ignore the ABS. */
1194 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
1195 || val_signbit_known_clear_p (GET_MODE (op
),
1196 nonzero_bits (op
, GET_MODE (op
))))
1199 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1200 if (num_sign_bit_copies (op
, mode
) == GET_MODE_PRECISION (mode
))
1201 return gen_rtx_NEG (mode
, op
);
1206 /* (ffs (*_extend <X>)) = (ffs <X>) */
1207 if (GET_CODE (op
) == SIGN_EXTEND
1208 || GET_CODE (op
) == ZERO_EXTEND
)
1209 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
1210 GET_MODE (XEXP (op
, 0)));
1214 switch (GET_CODE (op
))
1218 /* (popcount (zero_extend <X>)) = (popcount <X>) */
1219 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1220 GET_MODE (XEXP (op
, 0)));
1224 /* Rotations don't affect popcount. */
1225 if (!side_effects_p (XEXP (op
, 1)))
1226 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1227 GET_MODE (XEXP (op
, 0)));
1236 switch (GET_CODE (op
))
1242 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1243 GET_MODE (XEXP (op
, 0)));
1247 /* Rotations don't affect parity. */
1248 if (!side_effects_p (XEXP (op
, 1)))
1249 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1250 GET_MODE (XEXP (op
, 0)));
1259 /* (bswap (bswap x)) -> x. */
1260 if (GET_CODE (op
) == BSWAP
)
1261 return XEXP (op
, 0);
1265 /* (float (sign_extend <X>)) = (float <X>). */
1266 if (GET_CODE (op
) == SIGN_EXTEND
)
1267 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
1268 GET_MODE (XEXP (op
, 0)));
1272 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1273 becomes just the MINUS if its mode is MODE. This allows
1274 folding switch statements on machines using casesi (such as
1276 if (GET_CODE (op
) == TRUNCATE
1277 && GET_MODE (XEXP (op
, 0)) == mode
1278 && GET_CODE (XEXP (op
, 0)) == MINUS
1279 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1280 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1281 return XEXP (op
, 0);
1283 /* Extending a widening multiplication should be canonicalized to
1284 a wider widening multiplication. */
1285 if (GET_CODE (op
) == MULT
)
1287 rtx lhs
= XEXP (op
, 0);
1288 rtx rhs
= XEXP (op
, 1);
1289 enum rtx_code lcode
= GET_CODE (lhs
);
1290 enum rtx_code rcode
= GET_CODE (rhs
);
1292 /* Widening multiplies usually extend both operands, but sometimes
1293 they use a shift to extract a portion of a register. */
1294 if ((lcode
== SIGN_EXTEND
1295 || (lcode
== ASHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1296 && (rcode
== SIGN_EXTEND
1297 || (rcode
== ASHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1299 enum machine_mode lmode
= GET_MODE (lhs
);
1300 enum machine_mode rmode
= GET_MODE (rhs
);
1303 if (lcode
== ASHIFTRT
)
1304 /* Number of bits not shifted off the end. */
1305 bits
= GET_MODE_PRECISION (lmode
) - INTVAL (XEXP (lhs
, 1));
1306 else /* lcode == SIGN_EXTEND */
1307 /* Size of inner mode. */
1308 bits
= GET_MODE_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1310 if (rcode
== ASHIFTRT
)
1311 bits
+= GET_MODE_PRECISION (rmode
) - INTVAL (XEXP (rhs
, 1));
1312 else /* rcode == SIGN_EXTEND */
1313 bits
+= GET_MODE_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1315 /* We can only widen multiplies if the result is mathematiclly
1316 equivalent. I.e. if overflow was impossible. */
1317 if (bits
<= GET_MODE_PRECISION (GET_MODE (op
)))
1318 return simplify_gen_binary
1320 simplify_gen_unary (SIGN_EXTEND
, mode
, lhs
, lmode
),
1321 simplify_gen_unary (SIGN_EXTEND
, mode
, rhs
, rmode
));
1325 /* Check for a sign extension of a subreg of a promoted
1326 variable, where the promotion is sign-extended, and the
1327 target mode is the same as the variable's promotion. */
1328 if (GET_CODE (op
) == SUBREG
1329 && SUBREG_PROMOTED_VAR_P (op
)
1330 && ! SUBREG_PROMOTED_UNSIGNED_P (op
)
1331 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (XEXP (op
, 0))))
1333 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1338 /* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
1339 (sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1340 if (GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
)
1342 gcc_assert (GET_MODE_BITSIZE (mode
)
1343 > GET_MODE_BITSIZE (GET_MODE (op
)));
1344 return simplify_gen_unary (GET_CODE (op
), mode
, XEXP (op
, 0),
1345 GET_MODE (XEXP (op
, 0)));
1348 /* (sign_extend:M (ashiftrt:N (ashift <X> (const_int I)) (const_int I)))
1349 is (sign_extend:M (subreg:O <X>)) if there is mode with
1350 GET_MODE_BITSIZE (N) - I bits.
1351 (sign_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1352 is similarly (zero_extend:M (subreg:O <X>)). */
1353 if ((GET_CODE (op
) == ASHIFTRT
|| GET_CODE (op
) == LSHIFTRT
)
1354 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1355 && CONST_INT_P (XEXP (op
, 1))
1356 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1357 && GET_MODE_BITSIZE (GET_MODE (op
)) > INTVAL (XEXP (op
, 1)))
1359 enum machine_mode tmode
1360 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op
))
1361 - INTVAL (XEXP (op
, 1)), MODE_INT
, 1);
1362 gcc_assert (GET_MODE_BITSIZE (mode
)
1363 > GET_MODE_BITSIZE (GET_MODE (op
)));
1364 if (tmode
!= BLKmode
)
1367 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1369 return simplify_gen_unary (GET_CODE (op
) == ASHIFTRT
1370 ? SIGN_EXTEND
: ZERO_EXTEND
,
1371 mode
, inner
, tmode
);
1375 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1376 /* As we do not know which address space the pointer is referring to,
1377 we can do this only if the target does not support different pointer
1378 or address modes depending on the address space. */
1379 if (target_default_pointer_address_modes_p ()
1380 && ! POINTERS_EXTEND_UNSIGNED
1381 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1383 || (GET_CODE (op
) == SUBREG
1384 && REG_P (SUBREG_REG (op
))
1385 && REG_POINTER (SUBREG_REG (op
))
1386 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1387 return convert_memory_address (Pmode
, op
);
1392 /* Check for a zero extension of a subreg of a promoted
1393 variable, where the promotion is zero-extended, and the
1394 target mode is the same as the variable's promotion. */
1395 if (GET_CODE (op
) == SUBREG
1396 && SUBREG_PROMOTED_VAR_P (op
)
1397 && SUBREG_PROMOTED_UNSIGNED_P (op
) > 0
1398 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (XEXP (op
, 0))))
1400 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1405 /* Extending a widening multiplication should be canonicalized to
1406 a wider widening multiplication. */
1407 if (GET_CODE (op
) == MULT
)
1409 rtx lhs
= XEXP (op
, 0);
1410 rtx rhs
= XEXP (op
, 1);
1411 enum rtx_code lcode
= GET_CODE (lhs
);
1412 enum rtx_code rcode
= GET_CODE (rhs
);
1414 /* Widening multiplies usually extend both operands, but sometimes
1415 they use a shift to extract a portion of a register. */
1416 if ((lcode
== ZERO_EXTEND
1417 || (lcode
== LSHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1418 && (rcode
== ZERO_EXTEND
1419 || (rcode
== LSHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1421 enum machine_mode lmode
= GET_MODE (lhs
);
1422 enum machine_mode rmode
= GET_MODE (rhs
);
1425 if (lcode
== LSHIFTRT
)
1426 /* Number of bits not shifted off the end. */
1427 bits
= GET_MODE_PRECISION (lmode
) - INTVAL (XEXP (lhs
, 1));
1428 else /* lcode == ZERO_EXTEND */
1429 /* Size of inner mode. */
1430 bits
= GET_MODE_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1432 if (rcode
== LSHIFTRT
)
1433 bits
+= GET_MODE_PRECISION (rmode
) - INTVAL (XEXP (rhs
, 1));
1434 else /* rcode == ZERO_EXTEND */
1435 bits
+= GET_MODE_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1437 /* We can only widen multiplies if the result is mathematiclly
1438 equivalent. I.e. if overflow was impossible. */
1439 if (bits
<= GET_MODE_PRECISION (GET_MODE (op
)))
1440 return simplify_gen_binary
1442 simplify_gen_unary (ZERO_EXTEND
, mode
, lhs
, lmode
),
1443 simplify_gen_unary (ZERO_EXTEND
, mode
, rhs
, rmode
));
1447 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1448 if (GET_CODE (op
) == ZERO_EXTEND
)
1449 return simplify_gen_unary (ZERO_EXTEND
, mode
, XEXP (op
, 0),
1450 GET_MODE (XEXP (op
, 0)));
1452 /* (zero_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1453 is (zero_extend:M (subreg:O <X>)) if there is mode with
1454 GET_MODE_BITSIZE (N) - I bits. */
1455 if (GET_CODE (op
) == LSHIFTRT
1456 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1457 && CONST_INT_P (XEXP (op
, 1))
1458 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1459 && GET_MODE_BITSIZE (GET_MODE (op
)) > INTVAL (XEXP (op
, 1)))
1461 enum machine_mode tmode
1462 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op
))
1463 - INTVAL (XEXP (op
, 1)), MODE_INT
, 1);
1464 if (tmode
!= BLKmode
)
1467 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1469 return simplify_gen_unary (ZERO_EXTEND
, mode
, inner
, tmode
);
1473 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1474 /* As we do not know which address space the pointer is referring to,
1475 we can do this only if the target does not support different pointer
1476 or address modes depending on the address space. */
1477 if (target_default_pointer_address_modes_p ()
1478 && POINTERS_EXTEND_UNSIGNED
> 0
1479 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1481 || (GET_CODE (op
) == SUBREG
1482 && REG_P (SUBREG_REG (op
))
1483 && REG_POINTER (SUBREG_REG (op
))
1484 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1485 return convert_memory_address (Pmode
, op
);
1496 /* Try to compute the value of a unary operation CODE whose output mode is to
1497 be MODE with input operand OP whose mode was originally OP_MODE.
1498 Return zero if the value cannot be computed. */
1500 simplify_const_unary_operation (enum rtx_code code
, enum machine_mode mode
,
1501 rtx op
, enum machine_mode op_mode
)
1503 unsigned int width
= GET_MODE_PRECISION (mode
);
1504 unsigned int op_width
= GET_MODE_PRECISION (op_mode
);
1506 if (code
== VEC_DUPLICATE
)
1508 gcc_assert (VECTOR_MODE_P (mode
));
1509 if (GET_MODE (op
) != VOIDmode
)
1511 if (!VECTOR_MODE_P (GET_MODE (op
)))
1512 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
1514 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
1517 if (CONST_SCALAR_INT_P (op
) || CONST_DOUBLE_AS_FLOAT_P (op
)
1518 || GET_CODE (op
) == CONST_VECTOR
)
1520 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1521 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1522 rtvec v
= rtvec_alloc (n_elts
);
1525 if (GET_CODE (op
) != CONST_VECTOR
)
1526 for (i
= 0; i
< n_elts
; i
++)
1527 RTVEC_ELT (v
, i
) = op
;
1530 enum machine_mode inmode
= GET_MODE (op
);
1531 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
1532 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
1534 gcc_assert (in_n_elts
< n_elts
);
1535 gcc_assert ((n_elts
% in_n_elts
) == 0);
1536 for (i
= 0; i
< n_elts
; i
++)
1537 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op
, i
% in_n_elts
);
1539 return gen_rtx_CONST_VECTOR (mode
, v
);
1543 if (VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
1545 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1546 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1547 enum machine_mode opmode
= GET_MODE (op
);
1548 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
1549 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
1550 rtvec v
= rtvec_alloc (n_elts
);
1553 gcc_assert (op_n_elts
== n_elts
);
1554 for (i
= 0; i
< n_elts
; i
++)
1556 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1557 CONST_VECTOR_ELT (op
, i
),
1558 GET_MODE_INNER (opmode
));
1561 RTVEC_ELT (v
, i
) = x
;
1563 return gen_rtx_CONST_VECTOR (mode
, v
);
1566 /* The order of these tests is critical so that, for example, we don't
1567 check the wrong mode (input vs. output) for a conversion operation,
1568 such as FIX. At some point, this should be simplified. */
1570 if (code
== FLOAT
&& CONST_SCALAR_INT_P (op
))
1572 HOST_WIDE_INT hv
, lv
;
1575 if (CONST_INT_P (op
))
1576 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
1578 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
1580 REAL_VALUE_FROM_INT (d
, lv
, hv
, mode
);
1581 d
= real_value_truncate (mode
, d
);
1582 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1584 else if (code
== UNSIGNED_FLOAT
&& CONST_SCALAR_INT_P (op
))
1586 HOST_WIDE_INT hv
, lv
;
1589 if (CONST_INT_P (op
))
1590 lv
= INTVAL (op
), hv
= HWI_SIGN_EXTEND (lv
);
1592 lv
= CONST_DOUBLE_LOW (op
), hv
= CONST_DOUBLE_HIGH (op
);
1594 if (op_mode
== VOIDmode
1595 || GET_MODE_PRECISION (op_mode
) > HOST_BITS_PER_DOUBLE_INT
)
1596 /* We should never get a negative number. */
1597 gcc_assert (hv
>= 0);
1598 else if (GET_MODE_PRECISION (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
1599 hv
= 0, lv
&= GET_MODE_MASK (op_mode
);
1601 REAL_VALUE_FROM_UNSIGNED_INT (d
, lv
, hv
, mode
);
1602 d
= real_value_truncate (mode
, d
);
1603 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1606 if (CONST_INT_P (op
)
1607 && width
<= HOST_BITS_PER_WIDE_INT
&& width
> 0)
1609 HOST_WIDE_INT arg0
= INTVAL (op
);
1623 val
= (arg0
>= 0 ? arg0
: - arg0
);
1627 arg0
&= GET_MODE_MASK (mode
);
1628 val
= ffs_hwi (arg0
);
1632 arg0
&= GET_MODE_MASK (mode
);
1633 if (arg0
== 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1636 val
= GET_MODE_PRECISION (mode
) - floor_log2 (arg0
) - 1;
1640 arg0
&= GET_MODE_MASK (mode
);
1642 val
= GET_MODE_PRECISION (mode
) - 1;
1644 val
= GET_MODE_PRECISION (mode
) - floor_log2 (arg0
) - 2;
1646 val
= GET_MODE_PRECISION (mode
) - floor_log2 (~arg0
) - 2;
1650 arg0
&= GET_MODE_MASK (mode
);
1653 /* Even if the value at zero is undefined, we have to come
1654 up with some replacement. Seems good enough. */
1655 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
))
1656 val
= GET_MODE_PRECISION (mode
);
1659 val
= ctz_hwi (arg0
);
1663 arg0
&= GET_MODE_MASK (mode
);
1666 val
++, arg0
&= arg0
- 1;
1670 arg0
&= GET_MODE_MASK (mode
);
1673 val
++, arg0
&= arg0
- 1;
1682 for (s
= 0; s
< width
; s
+= 8)
1684 unsigned int d
= width
- s
- 8;
1685 unsigned HOST_WIDE_INT byte
;
1686 byte
= (arg0
>> s
) & 0xff;
1697 /* When zero-extending a CONST_INT, we need to know its
1699 gcc_assert (op_mode
!= VOIDmode
);
1700 if (op_width
== HOST_BITS_PER_WIDE_INT
)
1702 /* If we were really extending the mode,
1703 we would have to distinguish between zero-extension
1704 and sign-extension. */
1705 gcc_assert (width
== op_width
);
1708 else if (GET_MODE_BITSIZE (op_mode
) < HOST_BITS_PER_WIDE_INT
)
1709 val
= arg0
& GET_MODE_MASK (op_mode
);
1715 if (op_mode
== VOIDmode
)
1717 op_width
= GET_MODE_PRECISION (op_mode
);
1718 if (op_width
== HOST_BITS_PER_WIDE_INT
)
1720 /* If we were really extending the mode,
1721 we would have to distinguish between zero-extension
1722 and sign-extension. */
1723 gcc_assert (width
== op_width
);
1726 else if (op_width
< HOST_BITS_PER_WIDE_INT
)
1728 val
= arg0
& GET_MODE_MASK (op_mode
);
1729 if (val_signbit_known_set_p (op_mode
, val
))
1730 val
|= ~GET_MODE_MASK (op_mode
);
1738 case FLOAT_TRUNCATE
:
1750 return gen_int_mode (val
, mode
);
1753 /* We can do some operations on integer CONST_DOUBLEs. Also allow
1754 for a DImode operation on a CONST_INT. */
1755 else if (width
<= HOST_BITS_PER_DOUBLE_INT
1756 && (CONST_DOUBLE_AS_INT_P (op
) || CONST_INT_P (op
)))
1758 double_int first
, value
;
1760 if (CONST_DOUBLE_AS_INT_P (op
))
1761 first
= double_int::from_pair (CONST_DOUBLE_HIGH (op
),
1762 CONST_DOUBLE_LOW (op
));
1764 first
= double_int::from_shwi (INTVAL (op
));
1777 if (first
.is_negative ())
1786 value
.low
= ffs_hwi (first
.low
);
1787 else if (first
.high
!= 0)
1788 value
.low
= HOST_BITS_PER_WIDE_INT
+ ffs_hwi (first
.high
);
1795 if (first
.high
!= 0)
1796 value
.low
= GET_MODE_PRECISION (mode
) - floor_log2 (first
.high
) - 1
1797 - HOST_BITS_PER_WIDE_INT
;
1798 else if (first
.low
!= 0)
1799 value
.low
= GET_MODE_PRECISION (mode
) - floor_log2 (first
.low
) - 1;
1800 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode
, value
.low
))
1801 value
.low
= GET_MODE_PRECISION (mode
);
1807 value
.low
= ctz_hwi (first
.low
);
1808 else if (first
.high
!= 0)
1809 value
.low
= HOST_BITS_PER_WIDE_INT
+ ctz_hwi (first
.high
);
1810 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode
, value
.low
))
1811 value
.low
= GET_MODE_PRECISION (mode
);
1815 value
= double_int_zero
;
1819 first
.low
&= first
.low
- 1;
1824 first
.high
&= first
.high
- 1;
1829 value
= double_int_zero
;
1833 first
.low
&= first
.low
- 1;
1838 first
.high
&= first
.high
- 1;
1847 value
= double_int_zero
;
1848 for (s
= 0; s
< width
; s
+= 8)
1850 unsigned int d
= width
- s
- 8;
1851 unsigned HOST_WIDE_INT byte
;
1853 if (s
< HOST_BITS_PER_WIDE_INT
)
1854 byte
= (first
.low
>> s
) & 0xff;
1856 byte
= (first
.high
>> (s
- HOST_BITS_PER_WIDE_INT
)) & 0xff;
1858 if (d
< HOST_BITS_PER_WIDE_INT
)
1859 value
.low
|= byte
<< d
;
1861 value
.high
|= byte
<< (d
- HOST_BITS_PER_WIDE_INT
);
1867 /* This is just a change-of-mode, so do nothing. */
1872 gcc_assert (op_mode
!= VOIDmode
);
1874 if (op_width
> HOST_BITS_PER_WIDE_INT
)
1877 value
= double_int::from_uhwi (first
.low
& GET_MODE_MASK (op_mode
));
1881 if (op_mode
== VOIDmode
1882 || op_width
> HOST_BITS_PER_WIDE_INT
)
1886 value
.low
= first
.low
& GET_MODE_MASK (op_mode
);
1887 if (val_signbit_known_set_p (op_mode
, value
.low
))
1888 value
.low
|= ~GET_MODE_MASK (op_mode
);
1890 value
.high
= HWI_SIGN_EXTEND (value
.low
);
1901 return immed_double_int_const (value
, mode
);
1904 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1905 && SCALAR_FLOAT_MODE_P (mode
)
1906 && SCALAR_FLOAT_MODE_P (GET_MODE (op
)))
1908 REAL_VALUE_TYPE d
, t
;
1909 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
1914 if (HONOR_SNANS (mode
) && real_isnan (&d
))
1916 real_sqrt (&t
, mode
, &d
);
1920 d
= real_value_abs (&d
);
1923 d
= real_value_negate (&d
);
1925 case FLOAT_TRUNCATE
:
1926 d
= real_value_truncate (mode
, d
);
1929 /* All this does is change the mode, unless changing
1931 if (GET_MODE_CLASS (mode
) != GET_MODE_CLASS (GET_MODE (op
)))
1932 real_convert (&d
, mode
, &d
);
1935 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1942 real_to_target (tmp
, &d
, GET_MODE (op
));
1943 for (i
= 0; i
< 4; i
++)
1945 real_from_target (&d
, tmp
, mode
);
1951 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1954 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1955 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1956 && GET_MODE_CLASS (mode
) == MODE_INT
1957 && width
<= HOST_BITS_PER_DOUBLE_INT
&& width
> 0)
1959 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
1960 operators are intentionally left unspecified (to ease implementation
1961 by target backends), for consistency, this routine implements the
1962 same semantics for constant folding as used by the middle-end. */
1964 /* This was formerly used only for non-IEEE float.
1965 eggert@twinsun.com says it is safe for IEEE also. */
1966 HOST_WIDE_INT xh
, xl
, th
, tl
;
1967 REAL_VALUE_TYPE x
, t
;
1968 REAL_VALUE_FROM_CONST_DOUBLE (x
, op
);
1972 if (REAL_VALUE_ISNAN (x
))
1975 /* Test against the signed upper bound. */
1976 if (width
> HOST_BITS_PER_WIDE_INT
)
1978 th
= ((unsigned HOST_WIDE_INT
) 1
1979 << (width
- HOST_BITS_PER_WIDE_INT
- 1)) - 1;
1985 tl
= ((unsigned HOST_WIDE_INT
) 1 << (width
- 1)) - 1;
1987 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
1988 if (REAL_VALUES_LESS (t
, x
))
1995 /* Test against the signed lower bound. */
1996 if (width
> HOST_BITS_PER_WIDE_INT
)
1998 th
= (unsigned HOST_WIDE_INT
) (-1)
1999 << (width
- HOST_BITS_PER_WIDE_INT
- 1);
2005 tl
= (unsigned HOST_WIDE_INT
) (-1) << (width
- 1);
2007 real_from_integer (&t
, VOIDmode
, tl
, th
, 0);
2008 if (REAL_VALUES_LESS (x
, t
))
2014 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
2018 if (REAL_VALUE_ISNAN (x
) || REAL_VALUE_NEGATIVE (x
))
2021 /* Test against the unsigned upper bound. */
2022 if (width
== HOST_BITS_PER_DOUBLE_INT
)
2027 else if (width
>= HOST_BITS_PER_WIDE_INT
)
2029 th
= ((unsigned HOST_WIDE_INT
) 1
2030 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2036 tl
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2038 real_from_integer (&t
, VOIDmode
, tl
, th
, 1);
2039 if (REAL_VALUES_LESS (t
, x
))
2046 REAL_VALUE_TO_INT (&xl
, &xh
, x
);
2052 return immed_double_const (xl
, xh
, mode
);
2058 /* Subroutine of simplify_binary_operation to simplify a commutative,
2059 associative binary operation CODE with result mode MODE, operating
2060 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
2061 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2062 canonicalization is possible. */
2065 simplify_associative_operation (enum rtx_code code
, enum machine_mode mode
,
2070 /* Linearize the operator to the left. */
2071 if (GET_CODE (op1
) == code
)
2073 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
2074 if (GET_CODE (op0
) == code
)
2076 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
2077 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
2080 /* "a op (b op c)" becomes "(b op c) op a". */
2081 if (! swap_commutative_operands_p (op1
, op0
))
2082 return simplify_gen_binary (code
, mode
, op1
, op0
);
2089 if (GET_CODE (op0
) == code
)
2091 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
2092 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
2094 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
2095 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2098 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
2099 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
2101 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
2103 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
2104 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
2106 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2113 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
2114 and OP1. Return 0 if no simplification is possible.
2116 Don't use this for relational operations such as EQ or LT.
2117 Use simplify_relational_operation instead. */
2119 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
2122 rtx trueop0
, trueop1
;
2125 /* Relational operations don't work here. We must know the mode
2126 of the operands in order to do the comparison correctly.
2127 Assuming a full word can give incorrect results.
2128 Consider comparing 128 with -128 in QImode. */
2129 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
2130 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
2132 /* Make sure the constant is second. */
2133 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
2134 && swap_commutative_operands_p (op0
, op1
))
2136 tem
= op0
, op0
= op1
, op1
= tem
;
2139 trueop0
= avoid_constant_pool_reference (op0
);
2140 trueop1
= avoid_constant_pool_reference (op1
);
2142 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
2145 return simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
2148 /* Subroutine of simplify_binary_operation. Simplify a binary operation
2149 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
2150 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
2151 actual constants. */
2154 simplify_binary_operation_1 (enum rtx_code code
, enum machine_mode mode
,
2155 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
2157 rtx tem
, reversed
, opleft
, opright
;
2159 unsigned int width
= GET_MODE_PRECISION (mode
);
2161 /* Even if we can't compute a constant result,
2162 there are some cases worth simplifying. */
2167 /* Maybe simplify x + 0 to x. The two expressions are equivalent
2168 when x is NaN, infinite, or finite and nonzero. They aren't
2169 when x is -0 and the rounding mode is not towards -infinity,
2170 since (-0) + 0 is then 0. */
2171 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
2174 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
2175 transformations are safe even for IEEE. */
2176 if (GET_CODE (op0
) == NEG
)
2177 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
2178 else if (GET_CODE (op1
) == NEG
)
2179 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
2181 /* (~a) + 1 -> -a */
2182 if (INTEGRAL_MODE_P (mode
)
2183 && GET_CODE (op0
) == NOT
2184 && trueop1
== const1_rtx
)
2185 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
2187 /* Handle both-operands-constant cases. We can only add
2188 CONST_INTs to constants since the sum of relocatable symbols
2189 can't be handled by most assemblers. Don't add CONST_INT
2190 to CONST_INT since overflow won't be computed properly if wider
2191 than HOST_BITS_PER_WIDE_INT. */
2193 if ((GET_CODE (op0
) == CONST
2194 || GET_CODE (op0
) == SYMBOL_REF
2195 || GET_CODE (op0
) == LABEL_REF
)
2196 && CONST_INT_P (op1
))
2197 return plus_constant (mode
, op0
, INTVAL (op1
));
2198 else if ((GET_CODE (op1
) == CONST
2199 || GET_CODE (op1
) == SYMBOL_REF
2200 || GET_CODE (op1
) == LABEL_REF
)
2201 && CONST_INT_P (op0
))
2202 return plus_constant (mode
, op1
, INTVAL (op0
));
2204 /* See if this is something like X * C - X or vice versa or
2205 if the multiplication is written as a shift. If so, we can
2206 distribute and make a new multiply, shift, or maybe just
2207 have X (if C is 2 in the example above). But don't make
2208 something more expensive than we had before. */
2210 if (SCALAR_INT_MODE_P (mode
))
2212 double_int coeff0
, coeff1
;
2213 rtx lhs
= op0
, rhs
= op1
;
2215 coeff0
= double_int_one
;
2216 coeff1
= double_int_one
;
2218 if (GET_CODE (lhs
) == NEG
)
2220 coeff0
= double_int_minus_one
;
2221 lhs
= XEXP (lhs
, 0);
2223 else if (GET_CODE (lhs
) == MULT
2224 && CONST_INT_P (XEXP (lhs
, 1)))
2226 coeff0
= double_int::from_shwi (INTVAL (XEXP (lhs
, 1)));
2227 lhs
= XEXP (lhs
, 0);
2229 else if (GET_CODE (lhs
) == ASHIFT
2230 && CONST_INT_P (XEXP (lhs
, 1))
2231 && INTVAL (XEXP (lhs
, 1)) >= 0
2232 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
2234 coeff0
= double_int_zero
.set_bit (INTVAL (XEXP (lhs
, 1)));
2235 lhs
= XEXP (lhs
, 0);
2238 if (GET_CODE (rhs
) == NEG
)
2240 coeff1
= double_int_minus_one
;
2241 rhs
= XEXP (rhs
, 0);
2243 else if (GET_CODE (rhs
) == MULT
2244 && CONST_INT_P (XEXP (rhs
, 1)))
2246 coeff1
= double_int::from_shwi (INTVAL (XEXP (rhs
, 1)));
2247 rhs
= XEXP (rhs
, 0);
2249 else if (GET_CODE (rhs
) == ASHIFT
2250 && CONST_INT_P (XEXP (rhs
, 1))
2251 && INTVAL (XEXP (rhs
, 1)) >= 0
2252 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
2254 coeff1
= double_int_zero
.set_bit (INTVAL (XEXP (rhs
, 1)));
2255 rhs
= XEXP (rhs
, 0);
2258 if (rtx_equal_p (lhs
, rhs
))
2260 rtx orig
= gen_rtx_PLUS (mode
, op0
, op1
);
2263 bool speed
= optimize_function_for_speed_p (cfun
);
2265 val
= coeff0
+ coeff1
;
2266 coeff
= immed_double_int_const (val
, mode
);
2268 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
2269 return set_src_cost (tem
, speed
) <= set_src_cost (orig
, speed
)
2274 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
2275 if (CONST_SCALAR_INT_P (op1
)
2276 && GET_CODE (op0
) == XOR
2277 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2278 && mode_signbit_p (mode
, op1
))
2279 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2280 simplify_gen_binary (XOR
, mode
, op1
,
2283 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
2284 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2285 && GET_CODE (op0
) == MULT
2286 && GET_CODE (XEXP (op0
, 0)) == NEG
)
2290 in1
= XEXP (XEXP (op0
, 0), 0);
2291 in2
= XEXP (op0
, 1);
2292 return simplify_gen_binary (MINUS
, mode
, op1
,
2293 simplify_gen_binary (MULT
, mode
,
2297 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
2298 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
2300 if (COMPARISON_P (op0
)
2301 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
2302 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
2303 && (reversed
= reversed_comparison (op0
, mode
)))
2305 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
2307 /* If one of the operands is a PLUS or a MINUS, see if we can
2308 simplify this by the associative law.
2309 Don't use the associative law for floating point.
2310 The inaccuracy makes it nonassociative,
2311 and subtle programs can break if operations are associated. */
2313 if (INTEGRAL_MODE_P (mode
)
2314 && (plus_minus_operand_p (op0
)
2315 || plus_minus_operand_p (op1
))
2316 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2319 /* Reassociate floating point addition only when the user
2320 specifies associative math operations. */
2321 if (FLOAT_MODE_P (mode
)
2322 && flag_associative_math
)
2324 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2331 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
2332 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
2333 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
2334 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
2336 rtx xop00
= XEXP (op0
, 0);
2337 rtx xop10
= XEXP (op1
, 0);
2340 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
2342 if (REG_P (xop00
) && REG_P (xop10
)
2343 && GET_MODE (xop00
) == GET_MODE (xop10
)
2344 && REGNO (xop00
) == REGNO (xop10
)
2345 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
2346 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
2353 /* We can't assume x-x is 0 even with non-IEEE floating point,
2354 but since it is zero except in very strange circumstances, we
2355 will treat it as zero with -ffinite-math-only. */
2356 if (rtx_equal_p (trueop0
, trueop1
)
2357 && ! side_effects_p (op0
)
2358 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
2359 return CONST0_RTX (mode
);
2361 /* Change subtraction from zero into negation. (0 - x) is the
2362 same as -x when x is NaN, infinite, or finite and nonzero.
2363 But if the mode has signed zeros, and does not round towards
2364 -infinity, then 0 - 0 is 0, not -0. */
2365 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
2366 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
2368 /* (-1 - a) is ~a. */
2369 if (trueop0
== constm1_rtx
)
2370 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
2372 /* Subtracting 0 has no effect unless the mode has signed zeros
2373 and supports rounding towards -infinity. In such a case,
2375 if (!(HONOR_SIGNED_ZEROS (mode
)
2376 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2377 && trueop1
== CONST0_RTX (mode
))
2380 /* See if this is something like X * C - X or vice versa or
2381 if the multiplication is written as a shift. If so, we can
2382 distribute and make a new multiply, shift, or maybe just
2383 have X (if C is 2 in the example above). But don't make
2384 something more expensive than we had before. */
2386 if (SCALAR_INT_MODE_P (mode
))
2388 double_int coeff0
, negcoeff1
;
2389 rtx lhs
= op0
, rhs
= op1
;
2391 coeff0
= double_int_one
;
2392 negcoeff1
= double_int_minus_one
;
2394 if (GET_CODE (lhs
) == NEG
)
2396 coeff0
= double_int_minus_one
;
2397 lhs
= XEXP (lhs
, 0);
2399 else if (GET_CODE (lhs
) == MULT
2400 && CONST_INT_P (XEXP (lhs
, 1)))
2402 coeff0
= double_int::from_shwi (INTVAL (XEXP (lhs
, 1)));
2403 lhs
= XEXP (lhs
, 0);
2405 else if (GET_CODE (lhs
) == ASHIFT
2406 && CONST_INT_P (XEXP (lhs
, 1))
2407 && INTVAL (XEXP (lhs
, 1)) >= 0
2408 && INTVAL (XEXP (lhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
2410 coeff0
= double_int_zero
.set_bit (INTVAL (XEXP (lhs
, 1)));
2411 lhs
= XEXP (lhs
, 0);
2414 if (GET_CODE (rhs
) == NEG
)
2416 negcoeff1
= double_int_one
;
2417 rhs
= XEXP (rhs
, 0);
2419 else if (GET_CODE (rhs
) == MULT
2420 && CONST_INT_P (XEXP (rhs
, 1)))
2422 negcoeff1
= double_int::from_shwi (-INTVAL (XEXP (rhs
, 1)));
2423 rhs
= XEXP (rhs
, 0);
2425 else if (GET_CODE (rhs
) == ASHIFT
2426 && CONST_INT_P (XEXP (rhs
, 1))
2427 && INTVAL (XEXP (rhs
, 1)) >= 0
2428 && INTVAL (XEXP (rhs
, 1)) < HOST_BITS_PER_WIDE_INT
)
2430 negcoeff1
= double_int_zero
.set_bit (INTVAL (XEXP (rhs
, 1)));
2431 negcoeff1
= -negcoeff1
;
2432 rhs
= XEXP (rhs
, 0);
2435 if (rtx_equal_p (lhs
, rhs
))
2437 rtx orig
= gen_rtx_MINUS (mode
, op0
, op1
);
2440 bool speed
= optimize_function_for_speed_p (cfun
);
2442 val
= coeff0
+ negcoeff1
;
2443 coeff
= immed_double_int_const (val
, mode
);
2445 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
2446 return set_src_cost (tem
, speed
) <= set_src_cost (orig
, speed
)
2451 /* (a - (-b)) -> (a + b). True even for IEEE. */
2452 if (GET_CODE (op1
) == NEG
)
2453 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
2455 /* (-x - c) may be simplified as (-c - x). */
2456 if (GET_CODE (op0
) == NEG
2457 && (CONST_SCALAR_INT_P (op1
) || CONST_DOUBLE_AS_FLOAT_P (op1
)))
2459 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2461 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
2464 /* Don't let a relocatable value get a negative coeff. */
2465 if (CONST_INT_P (op1
) && GET_MODE (op0
) != VOIDmode
)
2466 return simplify_gen_binary (PLUS
, mode
,
2468 neg_const_int (mode
, op1
));
2470 /* (x - (x & y)) -> (x & ~y) */
2471 if (INTEGRAL_MODE_P (mode
) && GET_CODE (op1
) == AND
)
2473 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
2475 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
2476 GET_MODE (XEXP (op1
, 1)));
2477 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2479 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
2481 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
2482 GET_MODE (XEXP (op1
, 0)));
2483 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2487 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
2488 by reversing the comparison code if valid. */
2489 if (STORE_FLAG_VALUE
== 1
2490 && trueop0
== const1_rtx
2491 && COMPARISON_P (op1
)
2492 && (reversed
= reversed_comparison (op1
, mode
)))
2495 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
2496 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2497 && GET_CODE (op1
) == MULT
2498 && GET_CODE (XEXP (op1
, 0)) == NEG
)
2502 in1
= XEXP (XEXP (op1
, 0), 0);
2503 in2
= XEXP (op1
, 1);
2504 return simplify_gen_binary (PLUS
, mode
,
2505 simplify_gen_binary (MULT
, mode
,
2510 /* Canonicalize (minus (neg A) (mult B C)) to
2511 (minus (mult (neg B) C) A). */
2512 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2513 && GET_CODE (op1
) == MULT
2514 && GET_CODE (op0
) == NEG
)
2518 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
2519 in2
= XEXP (op1
, 1);
2520 return simplify_gen_binary (MINUS
, mode
,
2521 simplify_gen_binary (MULT
, mode
,
2526 /* If one of the operands is a PLUS or a MINUS, see if we can
2527 simplify this by the associative law. This will, for example,
2528 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
2529 Don't use the associative law for floating point.
2530 The inaccuracy makes it nonassociative,
2531 and subtle programs can break if operations are associated. */
2533 if (INTEGRAL_MODE_P (mode
)
2534 && (plus_minus_operand_p (op0
)
2535 || plus_minus_operand_p (op1
))
2536 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2541 if (trueop1
== constm1_rtx
)
2542 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2544 if (GET_CODE (op0
) == NEG
)
2546 rtx temp
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2547 /* If op1 is a MULT as well and simplify_unary_operation
2548 just moved the NEG to the second operand, simplify_gen_binary
2549 below could through simplify_associative_operation move
2550 the NEG around again and recurse endlessly. */
2552 && GET_CODE (op1
) == MULT
2553 && GET_CODE (temp
) == MULT
2554 && XEXP (op1
, 0) == XEXP (temp
, 0)
2555 && GET_CODE (XEXP (temp
, 1)) == NEG
2556 && XEXP (op1
, 1) == XEXP (XEXP (temp
, 1), 0))
2559 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), temp
);
2561 if (GET_CODE (op1
) == NEG
)
2563 rtx temp
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
2564 /* If op0 is a MULT as well and simplify_unary_operation
2565 just moved the NEG to the second operand, simplify_gen_binary
2566 below could through simplify_associative_operation move
2567 the NEG around again and recurse endlessly. */
2569 && GET_CODE (op0
) == MULT
2570 && GET_CODE (temp
) == MULT
2571 && XEXP (op0
, 0) == XEXP (temp
, 0)
2572 && GET_CODE (XEXP (temp
, 1)) == NEG
2573 && XEXP (op0
, 1) == XEXP (XEXP (temp
, 1), 0))
2576 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op1
, 0));
2579 /* Maybe simplify x * 0 to 0. The reduction is not valid if
2580 x is NaN, since x * 0 is then also NaN. Nor is it valid
2581 when the mode has signed zeros, since multiplying a negative
2582 number by 0 will give -0, not 0. */
2583 if (!HONOR_NANS (mode
)
2584 && !HONOR_SIGNED_ZEROS (mode
)
2585 && trueop1
== CONST0_RTX (mode
)
2586 && ! side_effects_p (op0
))
2589 /* In IEEE floating point, x*1 is not equivalent to x for
2591 if (!HONOR_SNANS (mode
)
2592 && trueop1
== CONST1_RTX (mode
))
2595 /* Convert multiply by constant power of two into shift unless
2596 we are still generating RTL. This test is a kludge. */
2597 if (CONST_INT_P (trueop1
)
2598 && (val
= exact_log2 (UINTVAL (trueop1
))) >= 0
2599 /* If the mode is larger than the host word size, and the
2600 uppermost bit is set, then this isn't a power of two due
2601 to implicit sign extension. */
2602 && (width
<= HOST_BITS_PER_WIDE_INT
2603 || val
!= HOST_BITS_PER_WIDE_INT
- 1))
2604 return simplify_gen_binary (ASHIFT
, mode
, op0
, GEN_INT (val
));
2606 /* Likewise for multipliers wider than a word. */
2607 if (CONST_DOUBLE_AS_INT_P (trueop1
)
2608 && GET_MODE (op0
) == mode
2609 && CONST_DOUBLE_LOW (trueop1
) == 0
2610 && (val
= exact_log2 (CONST_DOUBLE_HIGH (trueop1
))) >= 0
2611 && (val
< HOST_BITS_PER_DOUBLE_INT
- 1
2612 || GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_DOUBLE_INT
))
2613 return simplify_gen_binary (ASHIFT
, mode
, op0
,
2614 GEN_INT (val
+ HOST_BITS_PER_WIDE_INT
));
2616 /* x*2 is x+x and x*(-1) is -x */
2617 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
2618 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2619 && !DECIMAL_FLOAT_MODE_P (GET_MODE (trueop1
))
2620 && GET_MODE (op0
) == mode
)
2623 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2625 if (REAL_VALUES_EQUAL (d
, dconst2
))
2626 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2628 if (!HONOR_SNANS (mode
)
2629 && REAL_VALUES_EQUAL (d
, dconstm1
))
2630 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2633 /* Optimize -x * -x as x * x. */
2634 if (FLOAT_MODE_P (mode
)
2635 && GET_CODE (op0
) == NEG
2636 && GET_CODE (op1
) == NEG
2637 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2638 && !side_effects_p (XEXP (op0
, 0)))
2639 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2641 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2642 if (SCALAR_FLOAT_MODE_P (mode
)
2643 && GET_CODE (op0
) == ABS
2644 && GET_CODE (op1
) == ABS
2645 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2646 && !side_effects_p (XEXP (op0
, 0)))
2647 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2649 /* Reassociate multiplication, but for floating point MULTs
2650 only when the user specifies unsafe math optimizations. */
2651 if (! FLOAT_MODE_P (mode
)
2652 || flag_unsafe_math_optimizations
)
2654 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2661 if (trueop1
== CONST0_RTX (mode
))
2663 if (INTEGRAL_MODE_P (mode
)
2664 && trueop1
== CONSTM1_RTX (mode
)
2665 && !side_effects_p (op0
))
2667 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2669 /* A | (~A) -> -1 */
2670 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2671 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2672 && ! side_effects_p (op0
)
2673 && SCALAR_INT_MODE_P (mode
))
2676 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
2677 if (CONST_INT_P (op1
)
2678 && HWI_COMPUTABLE_MODE_P (mode
)
2679 && (nonzero_bits (op0
, mode
) & ~UINTVAL (op1
)) == 0
2680 && !side_effects_p (op0
))
2683 /* Canonicalize (X & C1) | C2. */
2684 if (GET_CODE (op0
) == AND
2685 && CONST_INT_P (trueop1
)
2686 && CONST_INT_P (XEXP (op0
, 1)))
2688 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
2689 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
2690 HOST_WIDE_INT c2
= INTVAL (trueop1
);
2692 /* If (C1&C2) == C1, then (X&C1)|C2 becomes X. */
2694 && !side_effects_p (XEXP (op0
, 0)))
2697 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
2698 if (((c1
|c2
) & mask
) == mask
)
2699 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
2701 /* Minimize the number of bits set in C1, i.e. C1 := C1 & ~C2. */
2702 if (((c1
& ~c2
) & mask
) != (c1
& mask
))
2704 tem
= simplify_gen_binary (AND
, mode
, XEXP (op0
, 0),
2705 gen_int_mode (c1
& ~c2
, mode
));
2706 return simplify_gen_binary (IOR
, mode
, tem
, op1
);
2710 /* Convert (A & B) | A to A. */
2711 if (GET_CODE (op0
) == AND
2712 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2713 || rtx_equal_p (XEXP (op0
, 1), op1
))
2714 && ! side_effects_p (XEXP (op0
, 0))
2715 && ! side_effects_p (XEXP (op0
, 1)))
2718 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
2719 mode size to (rotate A CX). */
2721 if (GET_CODE (op1
) == ASHIFT
2722 || GET_CODE (op1
) == SUBREG
)
2733 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
2734 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
2735 && CONST_INT_P (XEXP (opleft
, 1))
2736 && CONST_INT_P (XEXP (opright
, 1))
2737 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
2738 == GET_MODE_PRECISION (mode
)))
2739 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
2741 /* Same, but for ashift that has been "simplified" to a wider mode
2742 by simplify_shift_const. */
2744 if (GET_CODE (opleft
) == SUBREG
2745 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
2746 && GET_CODE (opright
) == LSHIFTRT
2747 && GET_CODE (XEXP (opright
, 0)) == SUBREG
2748 && GET_MODE (opleft
) == GET_MODE (XEXP (opright
, 0))
2749 && SUBREG_BYTE (opleft
) == SUBREG_BYTE (XEXP (opright
, 0))
2750 && (GET_MODE_SIZE (GET_MODE (opleft
))
2751 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (opleft
))))
2752 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
2753 SUBREG_REG (XEXP (opright
, 0)))
2754 && CONST_INT_P (XEXP (SUBREG_REG (opleft
), 1))
2755 && CONST_INT_P (XEXP (opright
, 1))
2756 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1)) + INTVAL (XEXP (opright
, 1))
2757 == GET_MODE_PRECISION (mode
)))
2758 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0),
2759 XEXP (SUBREG_REG (opleft
), 1));
2761 /* If we have (ior (and (X C1) C2)), simplify this by making
2762 C1 as small as possible if C1 actually changes. */
2763 if (CONST_INT_P (op1
)
2764 && (HWI_COMPUTABLE_MODE_P (mode
)
2765 || INTVAL (op1
) > 0)
2766 && GET_CODE (op0
) == AND
2767 && CONST_INT_P (XEXP (op0
, 1))
2768 && CONST_INT_P (op1
)
2769 && (UINTVAL (XEXP (op0
, 1)) & UINTVAL (op1
)) != 0)
2770 return simplify_gen_binary (IOR
, mode
,
2772 (AND
, mode
, XEXP (op0
, 0),
2773 GEN_INT (UINTVAL (XEXP (op0
, 1))
2777 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
2778 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
2779 the PLUS does not affect any of the bits in OP1: then we can do
2780 the IOR as a PLUS and we can associate. This is valid if OP1
2781 can be safely shifted left C bits. */
2782 if (CONST_INT_P (trueop1
) && GET_CODE (op0
) == ASHIFTRT
2783 && GET_CODE (XEXP (op0
, 0)) == PLUS
2784 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
2785 && CONST_INT_P (XEXP (op0
, 1))
2786 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
2788 int count
= INTVAL (XEXP (op0
, 1));
2789 HOST_WIDE_INT mask
= INTVAL (trueop1
) << count
;
2791 if (mask
>> count
== INTVAL (trueop1
)
2792 && trunc_int_for_mode (mask
, mode
) == mask
2793 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
2794 return simplify_gen_binary (ASHIFTRT
, mode
,
2795 plus_constant (mode
, XEXP (op0
, 0),
2800 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2806 if (trueop1
== CONST0_RTX (mode
))
2808 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
2809 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
2810 if (rtx_equal_p (trueop0
, trueop1
)
2811 && ! side_effects_p (op0
)
2812 && GET_MODE_CLASS (mode
) != MODE_CC
)
2813 return CONST0_RTX (mode
);
2815 /* Canonicalize XOR of the most significant bit to PLUS. */
2816 if (CONST_SCALAR_INT_P (op1
)
2817 && mode_signbit_p (mode
, op1
))
2818 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
2819 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
2820 if (CONST_SCALAR_INT_P (op1
)
2821 && GET_CODE (op0
) == PLUS
2822 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2823 && mode_signbit_p (mode
, XEXP (op0
, 1)))
2824 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2825 simplify_gen_binary (XOR
, mode
, op1
,
2828 /* If we are XORing two things that have no bits in common,
2829 convert them into an IOR. This helps to detect rotation encoded
2830 using those methods and possibly other simplifications. */
2832 if (HWI_COMPUTABLE_MODE_P (mode
)
2833 && (nonzero_bits (op0
, mode
)
2834 & nonzero_bits (op1
, mode
)) == 0)
2835 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
2837 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
2838 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
2841 int num_negated
= 0;
2843 if (GET_CODE (op0
) == NOT
)
2844 num_negated
++, op0
= XEXP (op0
, 0);
2845 if (GET_CODE (op1
) == NOT
)
2846 num_negated
++, op1
= XEXP (op1
, 0);
2848 if (num_negated
== 2)
2849 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
2850 else if (num_negated
== 1)
2851 return simplify_gen_unary (NOT
, mode
,
2852 simplify_gen_binary (XOR
, mode
, op0
, op1
),
2856 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
2857 correspond to a machine insn or result in further simplifications
2858 if B is a constant. */
2860 if (GET_CODE (op0
) == AND
2861 && rtx_equal_p (XEXP (op0
, 1), op1
)
2862 && ! side_effects_p (op1
))
2863 return simplify_gen_binary (AND
, mode
,
2864 simplify_gen_unary (NOT
, mode
,
2865 XEXP (op0
, 0), mode
),
2868 else if (GET_CODE (op0
) == AND
2869 && rtx_equal_p (XEXP (op0
, 0), op1
)
2870 && ! side_effects_p (op1
))
2871 return simplify_gen_binary (AND
, mode
,
2872 simplify_gen_unary (NOT
, mode
,
2873 XEXP (op0
, 1), mode
),
2876 /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
2877 we can transform like this:
2878 (A&B)^C == ~(A&B)&C | ~C&(A&B)
2879 == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
2880 == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
2881 Attempt a few simplifications when B and C are both constants. */
2882 if (GET_CODE (op0
) == AND
2883 && CONST_INT_P (op1
)
2884 && CONST_INT_P (XEXP (op0
, 1)))
2886 rtx a
= XEXP (op0
, 0);
2887 rtx b
= XEXP (op0
, 1);
2889 HOST_WIDE_INT bval
= INTVAL (b
);
2890 HOST_WIDE_INT cval
= INTVAL (c
);
2893 = simplify_binary_operation (AND
, mode
,
2894 simplify_gen_unary (NOT
, mode
, a
, mode
),
2896 if ((~cval
& bval
) == 0)
2898 /* Try to simplify ~A&C | ~B&C. */
2899 if (na_c
!= NULL_RTX
)
2900 return simplify_gen_binary (IOR
, mode
, na_c
,
2901 GEN_INT (~bval
& cval
));
2905 /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
2906 if (na_c
== const0_rtx
)
2908 rtx a_nc_b
= simplify_gen_binary (AND
, mode
, a
,
2909 GEN_INT (~cval
& bval
));
2910 return simplify_gen_binary (IOR
, mode
, a_nc_b
,
2911 GEN_INT (~bval
& cval
));
2916 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
2917 comparison if STORE_FLAG_VALUE is 1. */
2918 if (STORE_FLAG_VALUE
== 1
2919 && trueop1
== const1_rtx
2920 && COMPARISON_P (op0
)
2921 && (reversed
= reversed_comparison (op0
, mode
)))
2924 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
2925 is (lt foo (const_int 0)), so we can perform the above
2926 simplification if STORE_FLAG_VALUE is 1. */
2928 if (STORE_FLAG_VALUE
== 1
2929 && trueop1
== const1_rtx
2930 && GET_CODE (op0
) == LSHIFTRT
2931 && CONST_INT_P (XEXP (op0
, 1))
2932 && INTVAL (XEXP (op0
, 1)) == GET_MODE_PRECISION (mode
) - 1)
2933 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
2935 /* (xor (comparison foo bar) (const_int sign-bit))
2936 when STORE_FLAG_VALUE is the sign bit. */
2937 if (val_signbit_p (mode
, STORE_FLAG_VALUE
)
2938 && trueop1
== const_true_rtx
2939 && COMPARISON_P (op0
)
2940 && (reversed
= reversed_comparison (op0
, mode
)))
2943 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2949 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2951 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
2953 if (HWI_COMPUTABLE_MODE_P (mode
))
2955 HOST_WIDE_INT nzop0
= nonzero_bits (trueop0
, mode
);
2956 HOST_WIDE_INT nzop1
;
2957 if (CONST_INT_P (trueop1
))
2959 HOST_WIDE_INT val1
= INTVAL (trueop1
);
2960 /* If we are turning off bits already known off in OP0, we need
2962 if ((nzop0
& ~val1
) == 0)
2965 nzop1
= nonzero_bits (trueop1
, mode
);
2966 /* If we are clearing all the nonzero bits, the result is zero. */
2967 if ((nzop1
& nzop0
) == 0
2968 && !side_effects_p (op0
) && !side_effects_p (op1
))
2969 return CONST0_RTX (mode
);
2971 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
2972 && GET_MODE_CLASS (mode
) != MODE_CC
)
2975 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2976 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2977 && ! side_effects_p (op0
)
2978 && GET_MODE_CLASS (mode
) != MODE_CC
)
2979 return CONST0_RTX (mode
);
2981 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
2982 there are no nonzero bits of C outside of X's mode. */
2983 if ((GET_CODE (op0
) == SIGN_EXTEND
2984 || GET_CODE (op0
) == ZERO_EXTEND
)
2985 && CONST_INT_P (trueop1
)
2986 && HWI_COMPUTABLE_MODE_P (mode
)
2987 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
2988 & UINTVAL (trueop1
)) == 0)
2990 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2991 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
2992 gen_int_mode (INTVAL (trueop1
),
2994 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
2997 /* Transform (and (truncate X) C) into (truncate (and X C)). This way
2998 we might be able to further simplify the AND with X and potentially
2999 remove the truncation altogether. */
3000 if (GET_CODE (op0
) == TRUNCATE
&& CONST_INT_P (trueop1
))
3002 rtx x
= XEXP (op0
, 0);
3003 enum machine_mode xmode
= GET_MODE (x
);
3004 tem
= simplify_gen_binary (AND
, xmode
, x
,
3005 gen_int_mode (INTVAL (trueop1
), xmode
));
3006 return simplify_gen_unary (TRUNCATE
, mode
, tem
, xmode
);
3009 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
3010 if (GET_CODE (op0
) == IOR
3011 && CONST_INT_P (trueop1
)
3012 && CONST_INT_P (XEXP (op0
, 1)))
3014 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
3015 return simplify_gen_binary (IOR
, mode
,
3016 simplify_gen_binary (AND
, mode
,
3017 XEXP (op0
, 0), op1
),
3018 gen_int_mode (tmp
, mode
));
3021 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
3022 insn (and may simplify more). */
3023 if (GET_CODE (op0
) == XOR
3024 && rtx_equal_p (XEXP (op0
, 0), op1
)
3025 && ! side_effects_p (op1
))
3026 return simplify_gen_binary (AND
, mode
,
3027 simplify_gen_unary (NOT
, mode
,
3028 XEXP (op0
, 1), mode
),
3031 if (GET_CODE (op0
) == XOR
3032 && rtx_equal_p (XEXP (op0
, 1), op1
)
3033 && ! side_effects_p (op1
))
3034 return simplify_gen_binary (AND
, mode
,
3035 simplify_gen_unary (NOT
, mode
,
3036 XEXP (op0
, 0), mode
),
3039 /* Similarly for (~(A ^ B)) & A. */
3040 if (GET_CODE (op0
) == NOT
3041 && GET_CODE (XEXP (op0
, 0)) == XOR
3042 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
3043 && ! side_effects_p (op1
))
3044 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
3046 if (GET_CODE (op0
) == NOT
3047 && GET_CODE (XEXP (op0
, 0)) == XOR
3048 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
3049 && ! side_effects_p (op1
))
3050 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
3052 /* Convert (A | B) & A to A. */
3053 if (GET_CODE (op0
) == IOR
3054 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3055 || rtx_equal_p (XEXP (op0
, 1), op1
))
3056 && ! side_effects_p (XEXP (op0
, 0))
3057 && ! side_effects_p (XEXP (op0
, 1)))
3060 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
3061 ((A & N) + B) & M -> (A + B) & M
3062 Similarly if (N & M) == 0,
3063 ((A | N) + B) & M -> (A + B) & M
3064 and for - instead of + and/or ^ instead of |.
3065 Also, if (N & M) == 0, then
3066 (A +- N) & M -> A & M. */
3067 if (CONST_INT_P (trueop1
)
3068 && HWI_COMPUTABLE_MODE_P (mode
)
3069 && ~UINTVAL (trueop1
)
3070 && (UINTVAL (trueop1
) & (UINTVAL (trueop1
) + 1)) == 0
3071 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
3076 pmop
[0] = XEXP (op0
, 0);
3077 pmop
[1] = XEXP (op0
, 1);
3079 if (CONST_INT_P (pmop
[1])
3080 && (UINTVAL (pmop
[1]) & UINTVAL (trueop1
)) == 0)
3081 return simplify_gen_binary (AND
, mode
, pmop
[0], op1
);
3083 for (which
= 0; which
< 2; which
++)
3086 switch (GET_CODE (tem
))
3089 if (CONST_INT_P (XEXP (tem
, 1))
3090 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
))
3091 == UINTVAL (trueop1
))
3092 pmop
[which
] = XEXP (tem
, 0);
3096 if (CONST_INT_P (XEXP (tem
, 1))
3097 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
)) == 0)
3098 pmop
[which
] = XEXP (tem
, 0);
3105 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
3107 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
3109 return simplify_gen_binary (code
, mode
, tem
, op1
);
3113 /* (and X (ior (not X) Y) -> (and X Y) */
3114 if (GET_CODE (op1
) == IOR
3115 && GET_CODE (XEXP (op1
, 0)) == NOT
3116 && op0
== XEXP (XEXP (op1
, 0), 0))
3117 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
3119 /* (and (ior (not X) Y) X) -> (and X Y) */
3120 if (GET_CODE (op0
) == IOR
3121 && GET_CODE (XEXP (op0
, 0)) == NOT
3122 && op1
== XEXP (XEXP (op0
, 0), 0))
3123 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
3125 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3131 /* 0/x is 0 (or x&0 if x has side-effects). */
3132 if (trueop0
== CONST0_RTX (mode
))
3134 if (side_effects_p (op1
))
3135 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3139 if (trueop1
== CONST1_RTX (mode
))
3141 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3145 /* Convert divide by power of two into shift. */
3146 if (CONST_INT_P (trueop1
)
3147 && (val
= exact_log2 (UINTVAL (trueop1
))) > 0)
3148 return simplify_gen_binary (LSHIFTRT
, mode
, op0
, GEN_INT (val
));
3152 /* Handle floating point and integers separately. */
3153 if (SCALAR_FLOAT_MODE_P (mode
))
3155 /* Maybe change 0.0 / x to 0.0. This transformation isn't
3156 safe for modes with NaNs, since 0.0 / 0.0 will then be
3157 NaN rather than 0.0. Nor is it safe for modes with signed
3158 zeros, since dividing 0 by a negative number gives -0.0 */
3159 if (trueop0
== CONST0_RTX (mode
)
3160 && !HONOR_NANS (mode
)
3161 && !HONOR_SIGNED_ZEROS (mode
)
3162 && ! side_effects_p (op1
))
3165 if (trueop1
== CONST1_RTX (mode
)
3166 && !HONOR_SNANS (mode
))
3169 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
3170 && trueop1
!= CONST0_RTX (mode
))
3173 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
3176 if (REAL_VALUES_EQUAL (d
, dconstm1
)
3177 && !HONOR_SNANS (mode
))
3178 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
3180 /* Change FP division by a constant into multiplication.
3181 Only do this with -freciprocal-math. */
3182 if (flag_reciprocal_math
3183 && !REAL_VALUES_EQUAL (d
, dconst0
))
3185 REAL_ARITHMETIC (d
, RDIV_EXPR
, dconst1
, d
);
3186 tem
= CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
3187 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
3191 else if (SCALAR_INT_MODE_P (mode
))
3193 /* 0/x is 0 (or x&0 if x has side-effects). */
3194 if (trueop0
== CONST0_RTX (mode
)
3195 && !cfun
->can_throw_non_call_exceptions
)
3197 if (side_effects_p (op1
))
3198 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3202 if (trueop1
== CONST1_RTX (mode
))
3204 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3209 if (trueop1
== constm1_rtx
)
3211 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3213 return simplify_gen_unary (NEG
, mode
, x
, mode
);
3219 /* 0%x is 0 (or x&0 if x has side-effects). */
3220 if (trueop0
== CONST0_RTX (mode
))
3222 if (side_effects_p (op1
))
3223 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3226 /* x%1 is 0 (of x&0 if x has side-effects). */
3227 if (trueop1
== CONST1_RTX (mode
))
3229 if (side_effects_p (op0
))
3230 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3231 return CONST0_RTX (mode
);
3233 /* Implement modulus by power of two as AND. */
3234 if (CONST_INT_P (trueop1
)
3235 && exact_log2 (UINTVAL (trueop1
)) > 0)
3236 return simplify_gen_binary (AND
, mode
, op0
,
3237 GEN_INT (INTVAL (op1
) - 1));
3241 /* 0%x is 0 (or x&0 if x has side-effects). */
3242 if (trueop0
== CONST0_RTX (mode
))
3244 if (side_effects_p (op1
))
3245 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3248 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
3249 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
3251 if (side_effects_p (op0
))
3252 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3253 return CONST0_RTX (mode
);
3260 if (trueop1
== CONST0_RTX (mode
))
3262 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3264 /* Rotating ~0 always results in ~0. */
3265 if (CONST_INT_P (trueop0
) && width
<= HOST_BITS_PER_WIDE_INT
3266 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
3267 && ! side_effects_p (op1
))
3270 if (SHIFT_COUNT_TRUNCATED
&& CONST_INT_P (op1
))
3272 val
= INTVAL (op1
) & (GET_MODE_BITSIZE (mode
) - 1);
3273 if (val
!= INTVAL (op1
))
3274 return simplify_gen_binary (code
, mode
, op0
, GEN_INT (val
));
3281 if (trueop1
== CONST0_RTX (mode
))
3283 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3285 goto canonicalize_shift
;
3288 if (trueop1
== CONST0_RTX (mode
))
3290 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3292 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
3293 if (GET_CODE (op0
) == CLZ
3294 && CONST_INT_P (trueop1
)
3295 && STORE_FLAG_VALUE
== 1
3296 && INTVAL (trueop1
) < (HOST_WIDE_INT
)width
)
3298 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
3299 unsigned HOST_WIDE_INT zero_val
= 0;
3301 if (CLZ_DEFINED_VALUE_AT_ZERO (imode
, zero_val
)
3302 && zero_val
== GET_MODE_PRECISION (imode
)
3303 && INTVAL (trueop1
) == exact_log2 (zero_val
))
3304 return simplify_gen_relational (EQ
, mode
, imode
,
3305 XEXP (op0
, 0), const0_rtx
);
3307 goto canonicalize_shift
;
3310 if (width
<= HOST_BITS_PER_WIDE_INT
3311 && mode_signbit_p (mode
, trueop1
)
3312 && ! side_effects_p (op0
))
3314 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3316 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3322 if (width
<= HOST_BITS_PER_WIDE_INT
3323 && CONST_INT_P (trueop1
)
3324 && (UINTVAL (trueop1
) == GET_MODE_MASK (mode
) >> 1)
3325 && ! side_effects_p (op0
))
3327 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3329 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3335 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3337 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3339 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3345 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
3347 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3349 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3362 /* ??? There are simplifications that can be done. */
3366 if (!VECTOR_MODE_P (mode
))
3368 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3369 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
3370 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3371 gcc_assert (XVECLEN (trueop1
, 0) == 1);
3372 gcc_assert (CONST_INT_P (XVECEXP (trueop1
, 0, 0)));
3374 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3375 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
3378 /* Extract a scalar element from a nested VEC_SELECT expression
3379 (with optional nested VEC_CONCAT expression). Some targets
3380 (i386) extract scalar element from a vector using chain of
3381 nested VEC_SELECT expressions. When input operand is a memory
3382 operand, this operation can be simplified to a simple scalar
3383 load from an offseted memory address. */
3384 if (GET_CODE (trueop0
) == VEC_SELECT
)
3386 rtx op0
= XEXP (trueop0
, 0);
3387 rtx op1
= XEXP (trueop0
, 1);
3389 enum machine_mode opmode
= GET_MODE (op0
);
3390 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
3391 int n_elts
= GET_MODE_SIZE (opmode
) / elt_size
;
3393 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
3399 gcc_assert (GET_CODE (op1
) == PARALLEL
);
3400 gcc_assert (i
< n_elts
);
3402 /* Select element, pointed by nested selector. */
3403 elem
= INTVAL (XVECEXP (op1
, 0, i
));
3405 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
3406 if (GET_CODE (op0
) == VEC_CONCAT
)
3408 rtx op00
= XEXP (op0
, 0);
3409 rtx op01
= XEXP (op0
, 1);
3411 enum machine_mode mode00
, mode01
;
3412 int n_elts00
, n_elts01
;
3414 mode00
= GET_MODE (op00
);
3415 mode01
= GET_MODE (op01
);
3417 /* Find out number of elements of each operand. */
3418 if (VECTOR_MODE_P (mode00
))
3420 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode00
));
3421 n_elts00
= GET_MODE_SIZE (mode00
) / elt_size
;
3426 if (VECTOR_MODE_P (mode01
))
3428 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode01
));
3429 n_elts01
= GET_MODE_SIZE (mode01
) / elt_size
;
3434 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
3436 /* Select correct operand of VEC_CONCAT
3437 and adjust selector. */
3438 if (elem
< n_elts01
)
3449 vec
= rtvec_alloc (1);
3450 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
3452 tmp
= gen_rtx_fmt_ee (code
, mode
,
3453 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
3456 if (GET_CODE (trueop0
) == VEC_DUPLICATE
3457 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
3458 return XEXP (trueop0
, 0);
3462 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3463 gcc_assert (GET_MODE_INNER (mode
)
3464 == GET_MODE_INNER (GET_MODE (trueop0
)));
3465 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3467 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3469 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
3470 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
3471 rtvec v
= rtvec_alloc (n_elts
);
3474 gcc_assert (XVECLEN (trueop1
, 0) == (int) n_elts
);
3475 for (i
= 0; i
< n_elts
; i
++)
3477 rtx x
= XVECEXP (trueop1
, 0, i
);
3479 gcc_assert (CONST_INT_P (x
));
3480 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
3484 return gen_rtx_CONST_VECTOR (mode
, v
);
3487 /* Recognize the identity. */
3488 if (GET_MODE (trueop0
) == mode
)
3490 bool maybe_ident
= true;
3491 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
3493 rtx j
= XVECEXP (trueop1
, 0, i
);
3494 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
3496 maybe_ident
= false;
3504 /* If we build {a,b} then permute it, build the result directly. */
3505 if (XVECLEN (trueop1
, 0) == 2
3506 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3507 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3508 && GET_CODE (trueop0
) == VEC_CONCAT
3509 && GET_CODE (XEXP (trueop0
, 0)) == VEC_CONCAT
3510 && GET_MODE (XEXP (trueop0
, 0)) == mode
3511 && GET_CODE (XEXP (trueop0
, 1)) == VEC_CONCAT
3512 && GET_MODE (XEXP (trueop0
, 1)) == mode
)
3514 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3515 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3518 gcc_assert (i0
< 4 && i1
< 4);
3519 subop0
= XEXP (XEXP (trueop0
, i0
/ 2), i0
% 2);
3520 subop1
= XEXP (XEXP (trueop0
, i1
/ 2), i1
% 2);
3522 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
3525 if (XVECLEN (trueop1
, 0) == 2
3526 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3527 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3528 && GET_CODE (trueop0
) == VEC_CONCAT
3529 && GET_MODE (trueop0
) == mode
)
3531 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3532 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3535 gcc_assert (i0
< 2 && i1
< 2);
3536 subop0
= XEXP (trueop0
, i0
);
3537 subop1
= XEXP (trueop0
, i1
);
3539 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
3543 if (XVECLEN (trueop1
, 0) == 1
3544 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3545 && GET_CODE (trueop0
) == VEC_CONCAT
)
3548 int offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
3550 /* Try to find the element in the VEC_CONCAT. */
3551 while (GET_MODE (vec
) != mode
3552 && GET_CODE (vec
) == VEC_CONCAT
)
3554 HOST_WIDE_INT vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
3555 if (offset
< vec_size
)
3556 vec
= XEXP (vec
, 0);
3560 vec
= XEXP (vec
, 1);
3562 vec
= avoid_constant_pool_reference (vec
);
3565 if (GET_MODE (vec
) == mode
)
3572 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
3573 ? GET_MODE (trueop0
)
3574 : GET_MODE_INNER (mode
));
3575 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
3576 ? GET_MODE (trueop1
)
3577 : GET_MODE_INNER (mode
));
3579 gcc_assert (VECTOR_MODE_P (mode
));
3580 gcc_assert (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
3581 == GET_MODE_SIZE (mode
));
3583 if (VECTOR_MODE_P (op0_mode
))
3584 gcc_assert (GET_MODE_INNER (mode
)
3585 == GET_MODE_INNER (op0_mode
));
3587 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
3589 if (VECTOR_MODE_P (op1_mode
))
3590 gcc_assert (GET_MODE_INNER (mode
)
3591 == GET_MODE_INNER (op1_mode
));
3593 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
3595 if ((GET_CODE (trueop0
) == CONST_VECTOR
3596 || CONST_SCALAR_INT_P (trueop0
)
3597 || CONST_DOUBLE_AS_FLOAT_P (trueop0
))
3598 && (GET_CODE (trueop1
) == CONST_VECTOR
3599 || CONST_SCALAR_INT_P (trueop1
)
3600 || CONST_DOUBLE_AS_FLOAT_P (trueop1
)))
3602 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
3603 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
3604 rtvec v
= rtvec_alloc (n_elts
);
3606 unsigned in_n_elts
= 1;
3608 if (VECTOR_MODE_P (op0_mode
))
3609 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
3610 for (i
= 0; i
< n_elts
; i
++)
3614 if (!VECTOR_MODE_P (op0_mode
))
3615 RTVEC_ELT (v
, i
) = trueop0
;
3617 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
3621 if (!VECTOR_MODE_P (op1_mode
))
3622 RTVEC_ELT (v
, i
) = trueop1
;
3624 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
3629 return gen_rtx_CONST_VECTOR (mode
, v
);
3632 /* Try to merge VEC_SELECTs from the same vector into a single one. */
3633 if (GET_CODE (trueop0
) == VEC_SELECT
3634 && GET_CODE (trueop1
) == VEC_SELECT
3635 && rtx_equal_p (XEXP (trueop0
, 0), XEXP (trueop1
, 0)))
3637 rtx par0
= XEXP (trueop0
, 1);
3638 rtx par1
= XEXP (trueop1
, 1);
3639 int len0
= XVECLEN (par0
, 0);
3640 int len1
= XVECLEN (par1
, 0);
3641 rtvec vec
= rtvec_alloc (len0
+ len1
);
3642 for (int i
= 0; i
< len0
; i
++)
3643 RTVEC_ELT (vec
, i
) = XVECEXP (par0
, 0, i
);
3644 for (int i
= 0; i
< len1
; i
++)
3645 RTVEC_ELT (vec
, len0
+ i
) = XVECEXP (par1
, 0, i
);
3646 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (trueop0
, 0),
3647 gen_rtx_PARALLEL (VOIDmode
, vec
));
3660 simplify_const_binary_operation (enum rtx_code code
, enum machine_mode mode
,
3663 HOST_WIDE_INT arg0
, arg1
, arg0s
, arg1s
;
3665 unsigned int width
= GET_MODE_PRECISION (mode
);
3667 if (VECTOR_MODE_P (mode
)
3668 && code
!= VEC_CONCAT
3669 && GET_CODE (op0
) == CONST_VECTOR
3670 && GET_CODE (op1
) == CONST_VECTOR
)
3672 unsigned n_elts
= GET_MODE_NUNITS (mode
);
3673 enum machine_mode op0mode
= GET_MODE (op0
);
3674 unsigned op0_n_elts
= GET_MODE_NUNITS (op0mode
);
3675 enum machine_mode op1mode
= GET_MODE (op1
);
3676 unsigned op1_n_elts
= GET_MODE_NUNITS (op1mode
);
3677 rtvec v
= rtvec_alloc (n_elts
);
3680 gcc_assert (op0_n_elts
== n_elts
);
3681 gcc_assert (op1_n_elts
== n_elts
);
3682 for (i
= 0; i
< n_elts
; i
++)
3684 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
3685 CONST_VECTOR_ELT (op0
, i
),
3686 CONST_VECTOR_ELT (op1
, i
));
3689 RTVEC_ELT (v
, i
) = x
;
3692 return gen_rtx_CONST_VECTOR (mode
, v
);
3695 if (VECTOR_MODE_P (mode
)
3696 && code
== VEC_CONCAT
3697 && (CONST_SCALAR_INT_P (op0
)
3698 || GET_CODE (op0
) == CONST_FIXED
3699 || CONST_DOUBLE_AS_FLOAT_P (op0
))
3700 && (CONST_SCALAR_INT_P (op1
)
3701 || CONST_DOUBLE_AS_FLOAT_P (op1
)
3702 || GET_CODE (op1
) == CONST_FIXED
))
3704 unsigned n_elts
= GET_MODE_NUNITS (mode
);
3705 rtvec v
= rtvec_alloc (n_elts
);
3707 gcc_assert (n_elts
>= 2);
3710 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
3711 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
3713 RTVEC_ELT (v
, 0) = op0
;
3714 RTVEC_ELT (v
, 1) = op1
;
3718 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
));
3719 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
));
3722 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
3723 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
3724 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
3726 for (i
= 0; i
< op0_n_elts
; ++i
)
3727 RTVEC_ELT (v
, i
) = XVECEXP (op0
, 0, i
);
3728 for (i
= 0; i
< op1_n_elts
; ++i
)
3729 RTVEC_ELT (v
, op0_n_elts
+i
) = XVECEXP (op1
, 0, i
);
3732 return gen_rtx_CONST_VECTOR (mode
, v
);
3735 if (SCALAR_FLOAT_MODE_P (mode
)
3736 && CONST_DOUBLE_AS_FLOAT_P (op0
)
3737 && CONST_DOUBLE_AS_FLOAT_P (op1
)
3738 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
3749 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
3751 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
3753 for (i
= 0; i
< 4; i
++)
3770 real_from_target (&r
, tmp0
, mode
);
3771 return CONST_DOUBLE_FROM_REAL_VALUE (r
, mode
);
3775 REAL_VALUE_TYPE f0
, f1
, value
, result
;
3778 REAL_VALUE_FROM_CONST_DOUBLE (f0
, op0
);
3779 REAL_VALUE_FROM_CONST_DOUBLE (f1
, op1
);
3780 real_convert (&f0
, mode
, &f0
);
3781 real_convert (&f1
, mode
, &f1
);
3783 if (HONOR_SNANS (mode
)
3784 && (REAL_VALUE_ISNAN (f0
) || REAL_VALUE_ISNAN (f1
)))
3788 && REAL_VALUES_EQUAL (f1
, dconst0
)
3789 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
3792 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3793 && flag_trapping_math
3794 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
3796 int s0
= REAL_VALUE_NEGATIVE (f0
);
3797 int s1
= REAL_VALUE_NEGATIVE (f1
);
3802 /* Inf + -Inf = NaN plus exception. */
3807 /* Inf - Inf = NaN plus exception. */
3812 /* Inf / Inf = NaN plus exception. */
3819 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3820 && flag_trapping_math
3821 && ((REAL_VALUE_ISINF (f0
) && REAL_VALUES_EQUAL (f1
, dconst0
))
3822 || (REAL_VALUE_ISINF (f1
)
3823 && REAL_VALUES_EQUAL (f0
, dconst0
))))
3824 /* Inf * 0 = NaN plus exception. */
3827 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
3829 real_convert (&result
, mode
, &value
);
3831 /* Don't constant fold this floating point operation if
3832 the result has overflowed and flag_trapping_math. */
3834 if (flag_trapping_math
3835 && MODE_HAS_INFINITIES (mode
)
3836 && REAL_VALUE_ISINF (result
)
3837 && !REAL_VALUE_ISINF (f0
)
3838 && !REAL_VALUE_ISINF (f1
))
3839 /* Overflow plus exception. */
3842 /* Don't constant fold this floating point operation if the
3843 result may dependent upon the run-time rounding mode and
3844 flag_rounding_math is set, or if GCC's software emulation
3845 is unable to accurately represent the result. */
3847 if ((flag_rounding_math
3848 || (MODE_COMPOSITE_P (mode
) && !flag_unsafe_math_optimizations
))
3849 && (inexact
|| !real_identical (&result
, &value
)))
3852 return CONST_DOUBLE_FROM_REAL_VALUE (result
, mode
);
3856 /* We can fold some multi-word operations. */
3857 if (GET_MODE_CLASS (mode
) == MODE_INT
3858 && width
== HOST_BITS_PER_DOUBLE_INT
3859 && (CONST_DOUBLE_AS_INT_P (op0
) || CONST_INT_P (op0
))
3860 && (CONST_DOUBLE_AS_INT_P (op1
) || CONST_INT_P (op1
)))
3862 double_int o0
, o1
, res
, tmp
;
3865 o0
= rtx_to_double_int (op0
);
3866 o1
= rtx_to_double_int (op1
);
3871 /* A - B == A + (-B). */
3874 /* Fall through.... */
3885 res
= o0
.divmod_with_overflow (o1
, false, TRUNC_DIV_EXPR
,
3892 tmp
= o0
.divmod_with_overflow (o1
, false, TRUNC_DIV_EXPR
,
3899 res
= o0
.divmod_with_overflow (o1
, true, TRUNC_DIV_EXPR
,
3906 tmp
= o0
.divmod_with_overflow (o1
, true, TRUNC_DIV_EXPR
,
3940 case LSHIFTRT
: case ASHIFTRT
:
3942 case ROTATE
: case ROTATERT
:
3944 unsigned HOST_WIDE_INT cnt
;
3946 if (SHIFT_COUNT_TRUNCATED
)
3949 o1
.low
&= GET_MODE_PRECISION (mode
) - 1;
3952 if (!o1
.fits_uhwi ()
3953 || o1
.to_uhwi () >= GET_MODE_PRECISION (mode
))
3956 cnt
= o1
.to_uhwi ();
3957 unsigned short prec
= GET_MODE_PRECISION (mode
);
3959 if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
3960 res
= o0
.rshift (cnt
, prec
, code
== ASHIFTRT
);
3961 else if (code
== ASHIFT
)
3962 res
= o0
.alshift (cnt
, prec
);
3963 else if (code
== ROTATE
)
3964 res
= o0
.lrotate (cnt
, prec
);
3965 else /* code == ROTATERT */
3966 res
= o0
.rrotate (cnt
, prec
);
3974 return immed_double_int_const (res
, mode
);
3977 if (CONST_INT_P (op0
) && CONST_INT_P (op1
)
3978 && width
<= HOST_BITS_PER_WIDE_INT
&& width
!= 0)
3980 /* Get the integer argument values in two forms:
3981 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
3983 arg0
= INTVAL (op0
);
3984 arg1
= INTVAL (op1
);
3986 if (width
< HOST_BITS_PER_WIDE_INT
)
3988 arg0
&= GET_MODE_MASK (mode
);
3989 arg1
&= GET_MODE_MASK (mode
);
3992 if (val_signbit_known_set_p (mode
, arg0s
))
3993 arg0s
|= ~GET_MODE_MASK (mode
);
3996 if (val_signbit_known_set_p (mode
, arg1s
))
3997 arg1s
|= ~GET_MODE_MASK (mode
);
4005 /* Compute the value of the arithmetic. */
4010 val
= arg0s
+ arg1s
;
4014 val
= arg0s
- arg1s
;
4018 val
= arg0s
* arg1s
;
4023 || ((unsigned HOST_WIDE_INT
) arg0s
4024 == (unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
4027 val
= arg0s
/ arg1s
;
4032 || ((unsigned HOST_WIDE_INT
) arg0s
4033 == (unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
4036 val
= arg0s
% arg1s
;
4041 || ((unsigned HOST_WIDE_INT
) arg0s
4042 == (unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
4045 val
= (unsigned HOST_WIDE_INT
) arg0
/ arg1
;
4050 || ((unsigned HOST_WIDE_INT
) arg0s
4051 == (unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)
4054 val
= (unsigned HOST_WIDE_INT
) arg0
% arg1
;
4072 /* Truncate the shift if SHIFT_COUNT_TRUNCATED, otherwise make sure
4073 the value is in range. We can't return any old value for
4074 out-of-range arguments because either the middle-end (via
4075 shift_truncation_mask) or the back-end might be relying on
4076 target-specific knowledge. Nor can we rely on
4077 shift_truncation_mask, since the shift might not be part of an
4078 ashlM3, lshrM3 or ashrM3 instruction. */
4079 if (SHIFT_COUNT_TRUNCATED
)
4080 arg1
= (unsigned HOST_WIDE_INT
) arg1
% width
;
4081 else if (arg1
< 0 || arg1
>= GET_MODE_BITSIZE (mode
))
4084 val
= (code
== ASHIFT
4085 ? ((unsigned HOST_WIDE_INT
) arg0
) << arg1
4086 : ((unsigned HOST_WIDE_INT
) arg0
) >> arg1
);
4088 /* Sign-extend the result for arithmetic right shifts. */
4089 if (code
== ASHIFTRT
&& arg0s
< 0 && arg1
> 0)
4090 val
|= ((unsigned HOST_WIDE_INT
) (-1)) << (width
- arg1
);
4098 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << (width
- arg1
))
4099 | (((unsigned HOST_WIDE_INT
) arg0
) >> arg1
));
4107 val
= ((((unsigned HOST_WIDE_INT
) arg0
) << arg1
)
4108 | (((unsigned HOST_WIDE_INT
) arg0
) >> (width
- arg1
)));
4112 /* Do nothing here. */
4116 val
= arg0s
<= arg1s
? arg0s
: arg1s
;
4120 val
= ((unsigned HOST_WIDE_INT
) arg0
4121 <= (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
4125 val
= arg0s
> arg1s
? arg0s
: arg1s
;
4129 val
= ((unsigned HOST_WIDE_INT
) arg0
4130 > (unsigned HOST_WIDE_INT
) arg1
? arg0
: arg1
);
4143 /* ??? There are simplifications that can be done. */
4150 return gen_int_mode (val
, mode
);
4158 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
4161 Rather than test for specific case, we do this by a brute-force method
4162 and do all possible simplifications until no more changes occur. Then
4163 we rebuild the operation. */
4165 struct simplify_plus_minus_op_data
4172 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
4176 result
= (commutative_operand_precedence (y
)
4177 - commutative_operand_precedence (x
));
4181 /* Group together equal REGs to do more simplification. */
4182 if (REG_P (x
) && REG_P (y
))
4183 return REGNO (x
) > REGNO (y
);
4189 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
4192 struct simplify_plus_minus_op_data ops
[8];
4194 int n_ops
= 2, input_ops
= 2;
4195 int changed
, n_constants
= 0, canonicalized
= 0;
4198 memset (ops
, 0, sizeof ops
);
4200 /* Set up the two operands and then expand them until nothing has been
4201 changed. If we run out of room in our array, give up; this should
4202 almost never happen. */
4207 ops
[1].neg
= (code
== MINUS
);
4213 for (i
= 0; i
< n_ops
; i
++)
4215 rtx this_op
= ops
[i
].op
;
4216 int this_neg
= ops
[i
].neg
;
4217 enum rtx_code this_code
= GET_CODE (this_op
);
4226 ops
[n_ops
].op
= XEXP (this_op
, 1);
4227 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
4230 ops
[i
].op
= XEXP (this_op
, 0);
4233 canonicalized
|= this_neg
;
4237 ops
[i
].op
= XEXP (this_op
, 0);
4238 ops
[i
].neg
= ! this_neg
;
4245 && GET_CODE (XEXP (this_op
, 0)) == PLUS
4246 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
4247 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
4249 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
4250 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
4251 ops
[n_ops
].neg
= this_neg
;
4259 /* ~a -> (-a - 1) */
4262 ops
[n_ops
].op
= CONSTM1_RTX (mode
);
4263 ops
[n_ops
++].neg
= this_neg
;
4264 ops
[i
].op
= XEXP (this_op
, 0);
4265 ops
[i
].neg
= !this_neg
;
4275 ops
[i
].op
= neg_const_int (mode
, this_op
);
4289 if (n_constants
> 1)
4292 gcc_assert (n_ops
>= 2);
4294 /* If we only have two operands, we can avoid the loops. */
4297 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
4300 /* Get the two operands. Be careful with the order, especially for
4301 the cases where code == MINUS. */
4302 if (ops
[0].neg
&& ops
[1].neg
)
4304 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
4307 else if (ops
[0].neg
)
4318 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
4321 /* Now simplify each pair of operands until nothing changes. */
4324 /* Insertion sort is good enough for an eight-element array. */
4325 for (i
= 1; i
< n_ops
; i
++)
4327 struct simplify_plus_minus_op_data save
;
4329 if (!simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
))
4335 ops
[j
+ 1] = ops
[j
];
4336 while (j
-- && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
));
4341 for (i
= n_ops
- 1; i
> 0; i
--)
4342 for (j
= i
- 1; j
>= 0; j
--)
4344 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
4345 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
4347 if (lhs
!= 0 && rhs
!= 0)
4349 enum rtx_code ncode
= PLUS
;
4355 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
4357 else if (swap_commutative_operands_p (lhs
, rhs
))
4358 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
4360 if ((GET_CODE (lhs
) == CONST
|| CONST_INT_P (lhs
))
4361 && (GET_CODE (rhs
) == CONST
|| CONST_INT_P (rhs
)))
4363 rtx tem_lhs
, tem_rhs
;
4365 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
4366 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
4367 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
, tem_rhs
);
4369 if (tem
&& !CONSTANT_P (tem
))
4370 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
4373 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
4375 /* Reject "simplifications" that just wrap the two
4376 arguments in a CONST. Failure to do so can result
4377 in infinite recursion with simplify_binary_operation
4378 when it calls us to simplify CONST operations. */
4380 && ! (GET_CODE (tem
) == CONST
4381 && GET_CODE (XEXP (tem
, 0)) == ncode
4382 && XEXP (XEXP (tem
, 0), 0) == lhs
4383 && XEXP (XEXP (tem
, 0), 1) == rhs
))
4386 if (GET_CODE (tem
) == NEG
)
4387 tem
= XEXP (tem
, 0), lneg
= !lneg
;
4388 if (CONST_INT_P (tem
) && lneg
)
4389 tem
= neg_const_int (mode
, tem
), lneg
= 0;
4393 ops
[j
].op
= NULL_RTX
;
4400 /* If nothing changed, fail. */
4404 /* Pack all the operands to the lower-numbered entries. */
4405 for (i
= 0, j
= 0; j
< n_ops
; j
++)
4415 /* Create (minus -C X) instead of (neg (const (plus X C))). */
4417 && CONST_INT_P (ops
[1].op
)
4418 && CONSTANT_P (ops
[0].op
)
4420 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
4422 /* We suppressed creation of trivial CONST expressions in the
4423 combination loop to avoid recursion. Create one manually now.
4424 The combination loop should have ensured that there is exactly
4425 one CONST_INT, and the sort will have ensured that it is last
4426 in the array and that any other constant will be next-to-last. */
4429 && CONST_INT_P (ops
[n_ops
- 1].op
)
4430 && CONSTANT_P (ops
[n_ops
- 2].op
))
4432 rtx value
= ops
[n_ops
- 1].op
;
4433 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
4434 value
= neg_const_int (mode
, value
);
4435 ops
[n_ops
- 2].op
= plus_constant (mode
, ops
[n_ops
- 2].op
,
4440 /* Put a non-negated operand first, if possible. */
4442 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
4445 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
4454 /* Now make the result by performing the requested operations. */
4456 for (i
= 1; i
< n_ops
; i
++)
4457 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
4458 mode
, result
, ops
[i
].op
);
4463 /* Check whether an operand is suitable for calling simplify_plus_minus. */
4465 plus_minus_operand_p (const_rtx x
)
4467 return GET_CODE (x
) == PLUS
4468 || GET_CODE (x
) == MINUS
4469 || (GET_CODE (x
) == CONST
4470 && GET_CODE (XEXP (x
, 0)) == PLUS
4471 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
4472 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
4475 /* Like simplify_binary_operation except used for relational operators.
4476 MODE is the mode of the result. If MODE is VOIDmode, both operands must
4477 not also be VOIDmode.
4479 CMP_MODE specifies in which mode the comparison is done in, so it is
4480 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
4481 the operands or, if both are VOIDmode, the operands are compared in
4482 "infinite precision". */
4484 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
4485 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
4487 rtx tem
, trueop0
, trueop1
;
4489 if (cmp_mode
== VOIDmode
)
4490 cmp_mode
= GET_MODE (op0
);
4491 if (cmp_mode
== VOIDmode
)
4492 cmp_mode
= GET_MODE (op1
);
4494 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
4497 if (SCALAR_FLOAT_MODE_P (mode
))
4499 if (tem
== const0_rtx
)
4500 return CONST0_RTX (mode
);
4501 #ifdef FLOAT_STORE_FLAG_VALUE
4503 REAL_VALUE_TYPE val
;
4504 val
= FLOAT_STORE_FLAG_VALUE (mode
);
4505 return CONST_DOUBLE_FROM_REAL_VALUE (val
, mode
);
4511 if (VECTOR_MODE_P (mode
))
4513 if (tem
== const0_rtx
)
4514 return CONST0_RTX (mode
);
4515 #ifdef VECTOR_STORE_FLAG_VALUE
4520 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
4521 if (val
== NULL_RTX
)
4523 if (val
== const1_rtx
)
4524 return CONST1_RTX (mode
);
4526 units
= GET_MODE_NUNITS (mode
);
4527 v
= rtvec_alloc (units
);
4528 for (i
= 0; i
< units
; i
++)
4529 RTVEC_ELT (v
, i
) = val
;
4530 return gen_rtx_raw_CONST_VECTOR (mode
, v
);
4540 /* For the following tests, ensure const0_rtx is op1. */
4541 if (swap_commutative_operands_p (op0
, op1
)
4542 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
4543 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
4545 /* If op0 is a compare, extract the comparison arguments from it. */
4546 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
4547 return simplify_gen_relational (code
, mode
, VOIDmode
,
4548 XEXP (op0
, 0), XEXP (op0
, 1));
4550 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
4554 trueop0
= avoid_constant_pool_reference (op0
);
4555 trueop1
= avoid_constant_pool_reference (op1
);
4556 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
4560 /* This part of simplify_relational_operation is only used when CMP_MODE
4561 is not in class MODE_CC (i.e. it is a real comparison).
4563 MODE is the mode of the result, while CMP_MODE specifies in which
4564 mode the comparison is done in, so it is the mode of the operands. */
4567 simplify_relational_operation_1 (enum rtx_code code
, enum machine_mode mode
,
4568 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
4570 enum rtx_code op0code
= GET_CODE (op0
);
4572 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
4574 /* If op0 is a comparison, extract the comparison arguments
4578 if (GET_MODE (op0
) == mode
)
4579 return simplify_rtx (op0
);
4581 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
4582 XEXP (op0
, 0), XEXP (op0
, 1));
4584 else if (code
== EQ
)
4586 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL_RTX
);
4587 if (new_code
!= UNKNOWN
)
4588 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
4589 XEXP (op0
, 0), XEXP (op0
, 1));
4593 /* (LTU/GEU (PLUS a C) C), where C is constant, can be simplified to
4594 (GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
4595 if ((code
== LTU
|| code
== GEU
)
4596 && GET_CODE (op0
) == PLUS
4597 && CONST_INT_P (XEXP (op0
, 1))
4598 && (rtx_equal_p (op1
, XEXP (op0
, 0))
4599 || rtx_equal_p (op1
, XEXP (op0
, 1)))
4600 /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
4601 && XEXP (op0
, 1) != const0_rtx
)
4604 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
4605 return simplify_gen_relational ((code
== LTU
? GEU
: LTU
), mode
,
4606 cmp_mode
, XEXP (op0
, 0), new_cmp
);
4609 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
4610 if ((code
== LTU
|| code
== GEU
)
4611 && GET_CODE (op0
) == PLUS
4612 && rtx_equal_p (op1
, XEXP (op0
, 1))
4613 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
4614 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
4615 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
,
4616 copy_rtx (XEXP (op0
, 0)));
4618 if (op1
== const0_rtx
)
4620 /* Canonicalize (GTU x 0) as (NE x 0). */
4622 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
4623 /* Canonicalize (LEU x 0) as (EQ x 0). */
4625 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
4627 else if (op1
== const1_rtx
)
4632 /* Canonicalize (GE x 1) as (GT x 0). */
4633 return simplify_gen_relational (GT
, mode
, cmp_mode
,
4636 /* Canonicalize (GEU x 1) as (NE x 0). */
4637 return simplify_gen_relational (NE
, mode
, cmp_mode
,
4640 /* Canonicalize (LT x 1) as (LE x 0). */
4641 return simplify_gen_relational (LE
, mode
, cmp_mode
,
4644 /* Canonicalize (LTU x 1) as (EQ x 0). */
4645 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
4651 else if (op1
== constm1_rtx
)
4653 /* Canonicalize (LE x -1) as (LT x 0). */
4655 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
4656 /* Canonicalize (GT x -1) as (GE x 0). */
4658 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
4661 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
4662 if ((code
== EQ
|| code
== NE
)
4663 && (op0code
== PLUS
|| op0code
== MINUS
)
4665 && CONSTANT_P (XEXP (op0
, 1))
4666 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
4668 rtx x
= XEXP (op0
, 0);
4669 rtx c
= XEXP (op0
, 1);
4670 enum rtx_code invcode
= op0code
== PLUS
? MINUS
: PLUS
;
4671 rtx tem
= simplify_gen_binary (invcode
, cmp_mode
, op1
, c
);
4673 /* Detect an infinite recursive condition, where we oscillate at this
4674 simplification case between:
4675 A + B == C <---> C - B == A,
4676 where A, B, and C are all constants with non-simplifiable expressions,
4677 usually SYMBOL_REFs. */
4678 if (GET_CODE (tem
) == invcode
4680 && rtx_equal_p (c
, XEXP (tem
, 1)))
4683 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, tem
);
4686 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
4687 the same as (zero_extract:SI FOO (const_int 1) BAR). */
4689 && op1
== const0_rtx
4690 && GET_MODE_CLASS (mode
) == MODE_INT
4691 && cmp_mode
!= VOIDmode
4692 /* ??? Work-around BImode bugs in the ia64 backend. */
4694 && cmp_mode
!= BImode
4695 && nonzero_bits (op0
, cmp_mode
) == 1
4696 && STORE_FLAG_VALUE
== 1)
4697 return GET_MODE_SIZE (mode
) > GET_MODE_SIZE (cmp_mode
)
4698 ? simplify_gen_unary (ZERO_EXTEND
, mode
, op0
, cmp_mode
)
4699 : lowpart_subreg (mode
, op0
, cmp_mode
);
4701 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
4702 if ((code
== EQ
|| code
== NE
)
4703 && op1
== const0_rtx
4705 return simplify_gen_relational (code
, mode
, cmp_mode
,
4706 XEXP (op0
, 0), XEXP (op0
, 1));
4708 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
4709 if ((code
== EQ
|| code
== NE
)
4711 && rtx_equal_p (XEXP (op0
, 0), op1
)
4712 && !side_effects_p (XEXP (op0
, 0)))
4713 return simplify_gen_relational (code
, mode
, cmp_mode
,
4714 XEXP (op0
, 1), const0_rtx
);
4716 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
4717 if ((code
== EQ
|| code
== NE
)
4719 && rtx_equal_p (XEXP (op0
, 1), op1
)
4720 && !side_effects_p (XEXP (op0
, 1)))
4721 return simplify_gen_relational (code
, mode
, cmp_mode
,
4722 XEXP (op0
, 0), const0_rtx
);
4724 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
4725 if ((code
== EQ
|| code
== NE
)
4727 && CONST_SCALAR_INT_P (op1
)
4728 && CONST_SCALAR_INT_P (XEXP (op0
, 1)))
4729 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
4730 simplify_gen_binary (XOR
, cmp_mode
,
4731 XEXP (op0
, 1), op1
));
4733 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
4739 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
4740 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
4741 XEXP (op0
, 0), const0_rtx
);
4746 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
4747 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
4748 XEXP (op0
, 0), const0_rtx
);
4767 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
4768 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
4769 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
4770 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
4771 For floating-point comparisons, assume that the operands were ordered. */
4774 comparison_result (enum rtx_code code
, int known_results
)
4780 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
4783 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
4787 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
4790 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
4794 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
4797 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
4800 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
4802 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
4805 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
4807 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
4810 return const_true_rtx
;
4818 /* Check if the given comparison (done in the given MODE) is actually a
4819 tautology or a contradiction.
4820 If no simplification is possible, this function returns zero.
4821 Otherwise, it returns either const_true_rtx or const0_rtx. */
4824 simplify_const_relational_operation (enum rtx_code code
,
4825 enum machine_mode mode
,
4832 gcc_assert (mode
!= VOIDmode
4833 || (GET_MODE (op0
) == VOIDmode
4834 && GET_MODE (op1
) == VOIDmode
));
4836 /* If op0 is a compare, extract the comparison arguments from it. */
4837 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
4839 op1
= XEXP (op0
, 1);
4840 op0
= XEXP (op0
, 0);
4842 if (GET_MODE (op0
) != VOIDmode
)
4843 mode
= GET_MODE (op0
);
4844 else if (GET_MODE (op1
) != VOIDmode
)
4845 mode
= GET_MODE (op1
);
4850 /* We can't simplify MODE_CC values since we don't know what the
4851 actual comparison is. */
4852 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
4855 /* Make sure the constant is second. */
4856 if (swap_commutative_operands_p (op0
, op1
))
4858 tem
= op0
, op0
= op1
, op1
= tem
;
4859 code
= swap_condition (code
);
4862 trueop0
= avoid_constant_pool_reference (op0
);
4863 trueop1
= avoid_constant_pool_reference (op1
);
4865 /* For integer comparisons of A and B maybe we can simplify A - B and can
4866 then simplify a comparison of that with zero. If A and B are both either
4867 a register or a CONST_INT, this can't help; testing for these cases will
4868 prevent infinite recursion here and speed things up.
4870 We can only do this for EQ and NE comparisons as otherwise we may
4871 lose or introduce overflow which we cannot disregard as undefined as
4872 we do not know the signedness of the operation on either the left or
4873 the right hand side of the comparison. */
4875 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
4876 && (code
== EQ
|| code
== NE
)
4877 && ! ((REG_P (op0
) || CONST_INT_P (trueop0
))
4878 && (REG_P (op1
) || CONST_INT_P (trueop1
)))
4879 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
4880 /* We cannot do this if tem is a nonzero address. */
4881 && ! nonzero_address_p (tem
))
4882 return simplify_const_relational_operation (signed_condition (code
),
4883 mode
, tem
, const0_rtx
);
4885 if (! HONOR_NANS (mode
) && code
== ORDERED
)
4886 return const_true_rtx
;
4888 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
4891 /* For modes without NaNs, if the two operands are equal, we know the
4892 result except if they have side-effects. Even with NaNs we know
4893 the result of unordered comparisons and, if signaling NaNs are
4894 irrelevant, also the result of LT/GT/LTGT. */
4895 if ((! HONOR_NANS (GET_MODE (trueop0
))
4896 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
4897 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
4898 && ! HONOR_SNANS (GET_MODE (trueop0
))))
4899 && rtx_equal_p (trueop0
, trueop1
)
4900 && ! side_effects_p (trueop0
))
4901 return comparison_result (code
, CMP_EQ
);
4903 /* If the operands are floating-point constants, see if we can fold
4905 if (CONST_DOUBLE_AS_FLOAT_P (trueop0
)
4906 && CONST_DOUBLE_AS_FLOAT_P (trueop1
)
4907 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
4909 REAL_VALUE_TYPE d0
, d1
;
4911 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
4912 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
4914 /* Comparisons are unordered iff at least one of the values is NaN. */
4915 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
4925 return const_true_rtx
;
4938 return comparison_result (code
,
4939 (REAL_VALUES_EQUAL (d0
, d1
) ? CMP_EQ
:
4940 REAL_VALUES_LESS (d0
, d1
) ? CMP_LT
: CMP_GT
));
4943 /* Otherwise, see if the operands are both integers. */
4944 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
4945 && (CONST_DOUBLE_AS_INT_P (trueop0
) || CONST_INT_P (trueop0
))
4946 && (CONST_DOUBLE_AS_INT_P (trueop1
) || CONST_INT_P (trueop1
)))
4948 int width
= GET_MODE_PRECISION (mode
);
4949 HOST_WIDE_INT l0s
, h0s
, l1s
, h1s
;
4950 unsigned HOST_WIDE_INT l0u
, h0u
, l1u
, h1u
;
4952 /* Get the two words comprising each integer constant. */
4953 if (CONST_DOUBLE_AS_INT_P (trueop0
))
4955 l0u
= l0s
= CONST_DOUBLE_LOW (trueop0
);
4956 h0u
= h0s
= CONST_DOUBLE_HIGH (trueop0
);
4960 l0u
= l0s
= INTVAL (trueop0
);
4961 h0u
= h0s
= HWI_SIGN_EXTEND (l0s
);
4964 if (CONST_DOUBLE_AS_INT_P (trueop1
))
4966 l1u
= l1s
= CONST_DOUBLE_LOW (trueop1
);
4967 h1u
= h1s
= CONST_DOUBLE_HIGH (trueop1
);
4971 l1u
= l1s
= INTVAL (trueop1
);
4972 h1u
= h1s
= HWI_SIGN_EXTEND (l1s
);
4975 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
4976 we have to sign or zero-extend the values. */
4977 if (width
!= 0 && width
< HOST_BITS_PER_WIDE_INT
)
4979 l0u
&= GET_MODE_MASK (mode
);
4980 l1u
&= GET_MODE_MASK (mode
);
4982 if (val_signbit_known_set_p (mode
, l0s
))
4983 l0s
|= ~GET_MODE_MASK (mode
);
4985 if (val_signbit_known_set_p (mode
, l1s
))
4986 l1s
|= ~GET_MODE_MASK (mode
);
4988 if (width
!= 0 && width
<= HOST_BITS_PER_WIDE_INT
)
4989 h0u
= h1u
= 0, h0s
= HWI_SIGN_EXTEND (l0s
), h1s
= HWI_SIGN_EXTEND (l1s
);
4991 if (h0u
== h1u
&& l0u
== l1u
)
4992 return comparison_result (code
, CMP_EQ
);
4996 cr
= (h0s
< h1s
|| (h0s
== h1s
&& l0u
< l1u
)) ? CMP_LT
: CMP_GT
;
4997 cr
|= (h0u
< h1u
|| (h0u
== h1u
&& l0u
< l1u
)) ? CMP_LTU
: CMP_GTU
;
4998 return comparison_result (code
, cr
);
5002 /* Optimize comparisons with upper and lower bounds. */
5003 if (HWI_COMPUTABLE_MODE_P (mode
)
5004 && CONST_INT_P (trueop1
))
5007 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, mode
);
5008 HOST_WIDE_INT val
= INTVAL (trueop1
);
5009 HOST_WIDE_INT mmin
, mmax
;
5019 /* Get a reduced range if the sign bit is zero. */
5020 if (nonzero
<= (GET_MODE_MASK (mode
) >> 1))
5027 rtx mmin_rtx
, mmax_rtx
;
5028 get_mode_bounds (mode
, sign
, mode
, &mmin_rtx
, &mmax_rtx
);
5030 mmin
= INTVAL (mmin_rtx
);
5031 mmax
= INTVAL (mmax_rtx
);
5034 unsigned int sign_copies
= num_sign_bit_copies (trueop0
, mode
);
5036 mmin
>>= (sign_copies
- 1);
5037 mmax
>>= (sign_copies
- 1);
5043 /* x >= y is always true for y <= mmin, always false for y > mmax. */
5045 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5046 return const_true_rtx
;
5047 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5052 return const_true_rtx
;
5057 /* x <= y is always true for y >= mmax, always false for y < mmin. */
5059 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5060 return const_true_rtx
;
5061 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5066 return const_true_rtx
;
5072 /* x == y is always false for y out of range. */
5073 if (val
< mmin
|| val
> mmax
)
5077 /* x > y is always false for y >= mmax, always true for y < mmin. */
5079 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5081 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5082 return const_true_rtx
;
5088 return const_true_rtx
;
5091 /* x < y is always false for y <= mmin, always true for y > mmax. */
5093 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5095 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5096 return const_true_rtx
;
5102 return const_true_rtx
;
5106 /* x != y is always true for y out of range. */
5107 if (val
< mmin
|| val
> mmax
)
5108 return const_true_rtx
;
5116 /* Optimize integer comparisons with zero. */
5117 if (trueop1
== const0_rtx
)
5119 /* Some addresses are known to be nonzero. We don't know
5120 their sign, but equality comparisons are known. */
5121 if (nonzero_address_p (trueop0
))
5123 if (code
== EQ
|| code
== LEU
)
5125 if (code
== NE
|| code
== GTU
)
5126 return const_true_rtx
;
5129 /* See if the first operand is an IOR with a constant. If so, we
5130 may be able to determine the result of this comparison. */
5131 if (GET_CODE (op0
) == IOR
)
5133 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
5134 if (CONST_INT_P (inner_const
) && inner_const
!= const0_rtx
)
5136 int sign_bitnum
= GET_MODE_PRECISION (mode
) - 1;
5137 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
5138 && (UINTVAL (inner_const
)
5139 & ((unsigned HOST_WIDE_INT
) 1
5149 return const_true_rtx
;
5153 return const_true_rtx
;
5167 /* Optimize comparison of ABS with zero. */
5168 if (trueop1
== CONST0_RTX (mode
)
5169 && (GET_CODE (trueop0
) == ABS
5170 || (GET_CODE (trueop0
) == FLOAT_EXTEND
5171 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
5176 /* Optimize abs(x) < 0.0. */
5177 if (!HONOR_SNANS (mode
)
5178 && (!INTEGRAL_MODE_P (mode
)
5179 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
5181 if (INTEGRAL_MODE_P (mode
)
5182 && (issue_strict_overflow_warning
5183 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
5184 warning (OPT_Wstrict_overflow
,
5185 ("assuming signed overflow does not occur when "
5186 "assuming abs (x) < 0 is false"));
5192 /* Optimize abs(x) >= 0.0. */
5193 if (!HONOR_NANS (mode
)
5194 && (!INTEGRAL_MODE_P (mode
)
5195 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
5197 if (INTEGRAL_MODE_P (mode
)
5198 && (issue_strict_overflow_warning
5199 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
5200 warning (OPT_Wstrict_overflow
,
5201 ("assuming signed overflow does not occur when "
5202 "assuming abs (x) >= 0 is true"));
5203 return const_true_rtx
;
5208 /* Optimize ! (abs(x) < 0.0). */
5209 return const_true_rtx
;
5219 /* Simplify CODE, an operation with result mode MODE and three operands,
5220 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
5221 a constant. Return 0 if no simplifications is possible. */
5224 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
5225 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
5228 unsigned int width
= GET_MODE_PRECISION (mode
);
5229 bool any_change
= false;
5232 /* VOIDmode means "infinite" precision. */
5234 width
= HOST_BITS_PER_WIDE_INT
;
5239 /* Simplify negations around the multiplication. */
5240 /* -a * -b + c => a * b + c. */
5241 if (GET_CODE (op0
) == NEG
)
5243 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
5245 op1
= tem
, op0
= XEXP (op0
, 0), any_change
= true;
5247 else if (GET_CODE (op1
) == NEG
)
5249 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
5251 op0
= tem
, op1
= XEXP (op1
, 0), any_change
= true;
5254 /* Canonicalize the two multiplication operands. */
5255 /* a * -b + c => -b * a + c. */
5256 if (swap_commutative_operands_p (op0
, op1
))
5257 tem
= op0
, op0
= op1
, op1
= tem
, any_change
= true;
5260 return gen_rtx_FMA (mode
, op0
, op1
, op2
);
5265 if (CONST_INT_P (op0
)
5266 && CONST_INT_P (op1
)
5267 && CONST_INT_P (op2
)
5268 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
5269 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
5271 /* Extracting a bit-field from a constant */
5272 unsigned HOST_WIDE_INT val
= UINTVAL (op0
);
5273 HOST_WIDE_INT op1val
= INTVAL (op1
);
5274 HOST_WIDE_INT op2val
= INTVAL (op2
);
5275 if (BITS_BIG_ENDIAN
)
5276 val
>>= GET_MODE_PRECISION (op0_mode
) - op2val
- op1val
;
5280 if (HOST_BITS_PER_WIDE_INT
!= op1val
)
5282 /* First zero-extend. */
5283 val
&= ((unsigned HOST_WIDE_INT
) 1 << op1val
) - 1;
5284 /* If desired, propagate sign bit. */
5285 if (code
== SIGN_EXTRACT
5286 && (val
& ((unsigned HOST_WIDE_INT
) 1 << (op1val
- 1)))
5288 val
|= ~ (((unsigned HOST_WIDE_INT
) 1 << op1val
) - 1);
5291 return gen_int_mode (val
, mode
);
5296 if (CONST_INT_P (op0
))
5297 return op0
!= const0_rtx
? op1
: op2
;
5299 /* Convert c ? a : a into "a". */
5300 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
5303 /* Convert a != b ? a : b into "a". */
5304 if (GET_CODE (op0
) == NE
5305 && ! side_effects_p (op0
)
5306 && ! HONOR_NANS (mode
)
5307 && ! HONOR_SIGNED_ZEROS (mode
)
5308 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
5309 && rtx_equal_p (XEXP (op0
, 1), op2
))
5310 || (rtx_equal_p (XEXP (op0
, 0), op2
)
5311 && rtx_equal_p (XEXP (op0
, 1), op1
))))
5314 /* Convert a == b ? a : b into "b". */
5315 if (GET_CODE (op0
) == EQ
5316 && ! side_effects_p (op0
)
5317 && ! HONOR_NANS (mode
)
5318 && ! HONOR_SIGNED_ZEROS (mode
)
5319 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
5320 && rtx_equal_p (XEXP (op0
, 1), op2
))
5321 || (rtx_equal_p (XEXP (op0
, 0), op2
)
5322 && rtx_equal_p (XEXP (op0
, 1), op1
))))
5325 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
5327 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
5328 ? GET_MODE (XEXP (op0
, 1))
5329 : GET_MODE (XEXP (op0
, 0)));
5332 /* Look for happy constants in op1 and op2. */
5333 if (CONST_INT_P (op1
) && CONST_INT_P (op2
))
5335 HOST_WIDE_INT t
= INTVAL (op1
);
5336 HOST_WIDE_INT f
= INTVAL (op2
);
5338 if (t
== STORE_FLAG_VALUE
&& f
== 0)
5339 code
= GET_CODE (op0
);
5340 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
5343 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
5351 return simplify_gen_relational (code
, mode
, cmp_mode
,
5352 XEXP (op0
, 0), XEXP (op0
, 1));
5355 if (cmp_mode
== VOIDmode
)
5356 cmp_mode
= op0_mode
;
5357 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
5358 cmp_mode
, XEXP (op0
, 0),
5361 /* See if any simplifications were possible. */
5364 if (CONST_INT_P (temp
))
5365 return temp
== const0_rtx
? op2
: op1
;
5367 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
5373 gcc_assert (GET_MODE (op0
) == mode
);
5374 gcc_assert (GET_MODE (op1
) == mode
);
5375 gcc_assert (VECTOR_MODE_P (mode
));
5376 op2
= avoid_constant_pool_reference (op2
);
5377 if (CONST_INT_P (op2
))
5379 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
5380 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
5381 int mask
= (1 << n_elts
) - 1;
5383 if (!(INTVAL (op2
) & mask
))
5385 if ((INTVAL (op2
) & mask
) == mask
)
5388 op0
= avoid_constant_pool_reference (op0
);
5389 op1
= avoid_constant_pool_reference (op1
);
5390 if (GET_CODE (op0
) == CONST_VECTOR
5391 && GET_CODE (op1
) == CONST_VECTOR
)
5393 rtvec v
= rtvec_alloc (n_elts
);
5396 for (i
= 0; i
< n_elts
; i
++)
5397 RTVEC_ELT (v
, i
) = (INTVAL (op2
) & (1 << i
)
5398 ? CONST_VECTOR_ELT (op0
, i
)
5399 : CONST_VECTOR_ELT (op1
, i
));
5400 return gen_rtx_CONST_VECTOR (mode
, v
);
5412 /* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_FIXED
5414 returning another CONST_INT or CONST_DOUBLE or CONST_FIXED or CONST_VECTOR.
5416 Works by unpacking OP into a collection of 8-bit values
5417 represented as a little-endian array of 'unsigned char', selecting by BYTE,
5418 and then repacking them again for OUTERMODE. */
5421 simplify_immed_subreg (enum machine_mode outermode
, rtx op
,
5422 enum machine_mode innermode
, unsigned int byte
)
5424 /* We support up to 512-bit values (for V8DFmode). */
5428 value_mask
= (1 << value_bit
) - 1
5430 unsigned char value
[max_bitsize
/ value_bit
];
5439 rtvec result_v
= NULL
;
5440 enum mode_class outer_class
;
5441 enum machine_mode outer_submode
;
5443 /* Some ports misuse CCmode. */
5444 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& CONST_INT_P (op
))
5447 /* We have no way to represent a complex constant at the rtl level. */
5448 if (COMPLEX_MODE_P (outermode
))
5451 /* Unpack the value. */
5453 if (GET_CODE (op
) == CONST_VECTOR
)
5455 num_elem
= CONST_VECTOR_NUNITS (op
);
5456 elems
= &CONST_VECTOR_ELT (op
, 0);
5457 elem_bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (innermode
));
5463 elem_bitsize
= max_bitsize
;
5465 /* If this asserts, it is too complicated; reducing value_bit may help. */
5466 gcc_assert (BITS_PER_UNIT
% value_bit
== 0);
5467 /* I don't know how to handle endianness of sub-units. */
5468 gcc_assert (elem_bitsize
% BITS_PER_UNIT
== 0);
5470 for (elem
= 0; elem
< num_elem
; elem
++)
5473 rtx el
= elems
[elem
];
5475 /* Vectors are kept in target memory order. (This is probably
5478 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
5479 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
5481 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5482 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5483 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
5484 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5485 vp
= value
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
5488 switch (GET_CODE (el
))
5492 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
5494 *vp
++ = INTVAL (el
) >> i
;
5495 /* CONST_INTs are always logically sign-extended. */
5496 for (; i
< elem_bitsize
; i
+= value_bit
)
5497 *vp
++ = INTVAL (el
) < 0 ? -1 : 0;
5501 if (GET_MODE (el
) == VOIDmode
)
5503 unsigned char extend
= 0;
5504 /* If this triggers, someone should have generated a
5505 CONST_INT instead. */
5506 gcc_assert (elem_bitsize
> HOST_BITS_PER_WIDE_INT
);
5508 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
5509 *vp
++ = CONST_DOUBLE_LOW (el
) >> i
;
5510 while (i
< HOST_BITS_PER_DOUBLE_INT
&& i
< elem_bitsize
)
5513 = CONST_DOUBLE_HIGH (el
) >> (i
- HOST_BITS_PER_WIDE_INT
);
5517 if (CONST_DOUBLE_HIGH (el
) >> (HOST_BITS_PER_WIDE_INT
- 1))
5519 for (; i
< elem_bitsize
; i
+= value_bit
)
5524 long tmp
[max_bitsize
/ 32];
5525 int bitsize
= GET_MODE_BITSIZE (GET_MODE (el
));
5527 gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (el
)));
5528 gcc_assert (bitsize
<= elem_bitsize
);
5529 gcc_assert (bitsize
% value_bit
== 0);
5531 real_to_target (tmp
, CONST_DOUBLE_REAL_VALUE (el
),
5534 /* real_to_target produces its result in words affected by
5535 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
5536 and use WORDS_BIG_ENDIAN instead; see the documentation
5537 of SUBREG in rtl.texi. */
5538 for (i
= 0; i
< bitsize
; i
+= value_bit
)
5541 if (WORDS_BIG_ENDIAN
)
5542 ibase
= bitsize
- 1 - i
;
5545 *vp
++ = tmp
[ibase
/ 32] >> i
% 32;
5548 /* It shouldn't matter what's done here, so fill it with
5550 for (; i
< elem_bitsize
; i
+= value_bit
)
5556 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
5558 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
5559 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
5563 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
5564 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
5565 for (; i
< HOST_BITS_PER_DOUBLE_INT
&& i
< elem_bitsize
;
5567 *vp
++ = CONST_FIXED_VALUE_HIGH (el
)
5568 >> (i
- HOST_BITS_PER_WIDE_INT
);
5569 for (; i
< elem_bitsize
; i
+= value_bit
)
5579 /* Now, pick the right byte to start with. */
5580 /* Renumber BYTE so that the least-significant byte is byte 0. A special
5581 case is paradoxical SUBREGs, which shouldn't be adjusted since they
5582 will already have offset 0. */
5583 if (GET_MODE_SIZE (innermode
) >= GET_MODE_SIZE (outermode
))
5585 unsigned ibyte
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
)
5587 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5588 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5589 byte
= (subword_byte
% UNITS_PER_WORD
5590 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5593 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
5594 so if it's become negative it will instead be very large.) */
5595 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
5597 /* Convert from bytes to chunks of size value_bit. */
5598 value_start
= byte
* (BITS_PER_UNIT
/ value_bit
);
5600 /* Re-pack the value. */
5602 if (VECTOR_MODE_P (outermode
))
5604 num_elem
= GET_MODE_NUNITS (outermode
);
5605 result_v
= rtvec_alloc (num_elem
);
5606 elems
= &RTVEC_ELT (result_v
, 0);
5607 outer_submode
= GET_MODE_INNER (outermode
);
5613 outer_submode
= outermode
;
5616 outer_class
= GET_MODE_CLASS (outer_submode
);
5617 elem_bitsize
= GET_MODE_BITSIZE (outer_submode
);
5619 gcc_assert (elem_bitsize
% value_bit
== 0);
5620 gcc_assert (elem_bitsize
+ value_start
* value_bit
<= max_bitsize
);
5622 for (elem
= 0; elem
< num_elem
; elem
++)
5626 /* Vectors are stored in target memory order. (This is probably
5629 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
5630 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
5632 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5633 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5634 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
5635 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5636 vp
= value
+ value_start
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
5639 switch (outer_class
)
5642 case MODE_PARTIAL_INT
:
5644 unsigned HOST_WIDE_INT hi
= 0, lo
= 0;
5647 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
5649 lo
|= (unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
5650 for (; i
< elem_bitsize
; i
+= value_bit
)
5651 hi
|= (unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
)
5652 << (i
- HOST_BITS_PER_WIDE_INT
);
5654 /* immed_double_const doesn't call trunc_int_for_mode. I don't
5656 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
5657 elems
[elem
] = gen_int_mode (lo
, outer_submode
);
5658 else if (elem_bitsize
<= HOST_BITS_PER_DOUBLE_INT
)
5659 elems
[elem
] = immed_double_const (lo
, hi
, outer_submode
);
5666 case MODE_DECIMAL_FLOAT
:
5669 long tmp
[max_bitsize
/ 32];
5671 /* real_from_target wants its input in words affected by
5672 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
5673 and use WORDS_BIG_ENDIAN instead; see the documentation
5674 of SUBREG in rtl.texi. */
5675 for (i
= 0; i
< max_bitsize
/ 32; i
++)
5677 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
5680 if (WORDS_BIG_ENDIAN
)
5681 ibase
= elem_bitsize
- 1 - i
;
5684 tmp
[ibase
/ 32] |= (*vp
++ & value_mask
) << i
% 32;
5687 real_from_target (&r
, tmp
, outer_submode
);
5688 elems
[elem
] = CONST_DOUBLE_FROM_REAL_VALUE (r
, outer_submode
);
5700 f
.mode
= outer_submode
;
5703 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
5705 f
.data
.low
|= (unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
5706 for (; i
< elem_bitsize
; i
+= value_bit
)
5707 f
.data
.high
|= ((unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
)
5708 << (i
- HOST_BITS_PER_WIDE_INT
));
5710 elems
[elem
] = CONST_FIXED_FROM_FIXED_VALUE (f
, outer_submode
);
5718 if (VECTOR_MODE_P (outermode
))
5719 return gen_rtx_CONST_VECTOR (outermode
, result_v
);
5724 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
5725 Return 0 if no simplifications are possible. */
5727 simplify_subreg (enum machine_mode outermode
, rtx op
,
5728 enum machine_mode innermode
, unsigned int byte
)
5730 /* Little bit of sanity checking. */
5731 gcc_assert (innermode
!= VOIDmode
);
5732 gcc_assert (outermode
!= VOIDmode
);
5733 gcc_assert (innermode
!= BLKmode
);
5734 gcc_assert (outermode
!= BLKmode
);
5736 gcc_assert (GET_MODE (op
) == innermode
5737 || GET_MODE (op
) == VOIDmode
);
5739 if ((byte
% GET_MODE_SIZE (outermode
)) != 0)
5742 if (byte
>= GET_MODE_SIZE (innermode
))
5745 if (outermode
== innermode
&& !byte
)
5748 if (CONST_SCALAR_INT_P (op
)
5749 || CONST_DOUBLE_AS_FLOAT_P (op
)
5750 || GET_CODE (op
) == CONST_FIXED
5751 || GET_CODE (op
) == CONST_VECTOR
)
5752 return simplify_immed_subreg (outermode
, op
, innermode
, byte
);
5754 /* Changing mode twice with SUBREG => just change it once,
5755 or not at all if changing back op starting mode. */
5756 if (GET_CODE (op
) == SUBREG
)
5758 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
5759 int final_offset
= byte
+ SUBREG_BYTE (op
);
5762 if (outermode
== innermostmode
5763 && byte
== 0 && SUBREG_BYTE (op
) == 0)
5764 return SUBREG_REG (op
);
5766 /* The SUBREG_BYTE represents offset, as if the value were stored
5767 in memory. Irritating exception is paradoxical subreg, where
5768 we define SUBREG_BYTE to be 0. On big endian machines, this
5769 value should be negative. For a moment, undo this exception. */
5770 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
5772 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
5773 if (WORDS_BIG_ENDIAN
)
5774 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5775 if (BYTES_BIG_ENDIAN
)
5776 final_offset
+= difference
% UNITS_PER_WORD
;
5778 if (SUBREG_BYTE (op
) == 0
5779 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
5781 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
5782 if (WORDS_BIG_ENDIAN
)
5783 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5784 if (BYTES_BIG_ENDIAN
)
5785 final_offset
+= difference
% UNITS_PER_WORD
;
5788 /* See whether resulting subreg will be paradoxical. */
5789 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
5791 /* In nonparadoxical subregs we can't handle negative offsets. */
5792 if (final_offset
< 0)
5794 /* Bail out in case resulting subreg would be incorrect. */
5795 if (final_offset
% GET_MODE_SIZE (outermode
)
5796 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
5802 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
5804 /* In paradoxical subreg, see if we are still looking on lower part.
5805 If so, our SUBREG_BYTE will be 0. */
5806 if (WORDS_BIG_ENDIAN
)
5807 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5808 if (BYTES_BIG_ENDIAN
)
5809 offset
+= difference
% UNITS_PER_WORD
;
5810 if (offset
== final_offset
)
5816 /* Recurse for further possible simplifications. */
5817 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
5821 if (validate_subreg (outermode
, innermostmode
,
5822 SUBREG_REG (op
), final_offset
))
5824 newx
= gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
5825 if (SUBREG_PROMOTED_VAR_P (op
)
5826 && SUBREG_PROMOTED_UNSIGNED_P (op
) >= 0
5827 && GET_MODE_CLASS (outermode
) == MODE_INT
5828 && IN_RANGE (GET_MODE_SIZE (outermode
),
5829 GET_MODE_SIZE (innermode
),
5830 GET_MODE_SIZE (innermostmode
))
5831 && subreg_lowpart_p (newx
))
5833 SUBREG_PROMOTED_VAR_P (newx
) = 1;
5834 SUBREG_PROMOTED_UNSIGNED_SET
5835 (newx
, SUBREG_PROMOTED_UNSIGNED_P (op
));
5842 /* SUBREG of a hard register => just change the register number
5843 and/or mode. If the hard register is not valid in that mode,
5844 suppress this simplification. If the hard register is the stack,
5845 frame, or argument pointer, leave this as a SUBREG. */
5847 if (REG_P (op
) && HARD_REGISTER_P (op
))
5849 unsigned int regno
, final_regno
;
5852 final_regno
= simplify_subreg_regno (regno
, innermode
, byte
, outermode
);
5853 if (HARD_REGISTER_NUM_P (final_regno
))
5856 int final_offset
= byte
;
5858 /* Adjust offset for paradoxical subregs. */
5860 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
5862 int difference
= (GET_MODE_SIZE (innermode
)
5863 - GET_MODE_SIZE (outermode
));
5864 if (WORDS_BIG_ENDIAN
)
5865 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5866 if (BYTES_BIG_ENDIAN
)
5867 final_offset
+= difference
% UNITS_PER_WORD
;
5870 x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, final_offset
);
5872 /* Propagate original regno. We don't have any way to specify
5873 the offset inside original regno, so do so only for lowpart.
5874 The information is used only by alias analysis that can not
5875 grog partial register anyway. */
5877 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
5878 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
5883 /* If we have a SUBREG of a register that we are replacing and we are
5884 replacing it with a MEM, make a new MEM and try replacing the
5885 SUBREG with it. Don't do this if the MEM has a mode-dependent address
5886 or if we would be widening it. */
5889 && ! mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
))
5890 /* Allow splitting of volatile memory references in case we don't
5891 have instruction to move the whole thing. */
5892 && (! MEM_VOLATILE_P (op
)
5893 || ! have_insn_for (SET
, innermode
))
5894 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
5895 return adjust_address_nv (op
, outermode
, byte
);
5897 /* Handle complex values represented as CONCAT
5898 of real and imaginary part. */
5899 if (GET_CODE (op
) == CONCAT
)
5901 unsigned int part_size
, final_offset
;
5904 part_size
= GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)));
5905 if (byte
< part_size
)
5907 part
= XEXP (op
, 0);
5908 final_offset
= byte
;
5912 part
= XEXP (op
, 1);
5913 final_offset
= byte
- part_size
;
5916 if (final_offset
+ GET_MODE_SIZE (outermode
) > part_size
)
5919 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
5922 if (validate_subreg (outermode
, GET_MODE (part
), part
, final_offset
))
5923 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
5927 /* A SUBREG resulting from a zero extension may fold to zero if
5928 it extracts higher bits that the ZERO_EXTEND's source bits. */
5929 if (GET_CODE (op
) == ZERO_EXTEND
&& SCALAR_INT_MODE_P (innermode
))
5931 unsigned int bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
5932 if (bitpos
>= GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0))))
5933 return CONST0_RTX (outermode
);
5936 if (SCALAR_INT_MODE_P (outermode
)
5937 && SCALAR_INT_MODE_P (innermode
)
5938 && GET_MODE_PRECISION (outermode
) < GET_MODE_PRECISION (innermode
)
5939 && byte
== subreg_lowpart_offset (outermode
, innermode
))
5941 rtx tem
= simplify_truncation (outermode
, op
, innermode
);
5949 /* Make a SUBREG operation or equivalent if it folds. */
5952 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
5953 enum machine_mode innermode
, unsigned int byte
)
5957 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
5961 if (GET_CODE (op
) == SUBREG
5962 || GET_CODE (op
) == CONCAT
5963 || GET_MODE (op
) == VOIDmode
)
5966 if (validate_subreg (outermode
, innermode
, op
, byte
))
5967 return gen_rtx_SUBREG (outermode
, op
, byte
);
5972 /* Simplify X, an rtx expression.
5974 Return the simplified expression or NULL if no simplifications
5977 This is the preferred entry point into the simplification routines;
5978 however, we still allow passes to call the more specific routines.
5980 Right now GCC has three (yes, three) major bodies of RTL simplification
5981 code that need to be unified.
5983 1. fold_rtx in cse.c. This code uses various CSE specific
5984 information to aid in RTL simplification.
5986 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
5987 it uses combine specific information to aid in RTL
5990 3. The routines in this file.
5993 Long term we want to only have one body of simplification code; to
5994 get to that state I recommend the following steps:
5996 1. Pour over fold_rtx & simplify_rtx and move any simplifications
5997 which are not pass dependent state into these routines.
5999 2. As code is moved by #1, change fold_rtx & simplify_rtx to
6000 use this routine whenever possible.
6002 3. Allow for pass dependent state to be provided to these
6003 routines and add simplifications based on the pass dependent
6004 state. Remove code from cse.c & combine.c that becomes
6007 It will take time, but ultimately the compiler will be easier to
6008 maintain and improve. It's totally silly that when we add a
6009 simplification that it needs to be added to 4 places (3 for RTL
6010 simplification and 1 for tree simplification. */
6013 simplify_rtx (const_rtx x
)
6015 const enum rtx_code code
= GET_CODE (x
);
6016 const enum machine_mode mode
= GET_MODE (x
);
6018 switch (GET_RTX_CLASS (code
))
6021 return simplify_unary_operation (code
, mode
,
6022 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
6023 case RTX_COMM_ARITH
:
6024 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
6025 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
6027 /* Fall through.... */
6030 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6033 case RTX_BITFIELD_OPS
:
6034 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
6035 XEXP (x
, 0), XEXP (x
, 1),
6039 case RTX_COMM_COMPARE
:
6040 return simplify_relational_operation (code
, mode
,
6041 ((GET_MODE (XEXP (x
, 0))
6043 ? GET_MODE (XEXP (x
, 0))
6044 : GET_MODE (XEXP (x
, 1))),
6050 return simplify_subreg (mode
, SUBREG_REG (x
),
6051 GET_MODE (SUBREG_REG (x
)),
6058 /* Convert (lo_sum (high FOO) FOO) to FOO. */
6059 if (GET_CODE (XEXP (x
, 0)) == HIGH
6060 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))