1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
27 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
37 #include "stringpool.h"
40 #include "stor-layout.h"
49 #include "target-def.h"
50 #include "basic-block.h"
55 #include "diagnostic.h"
58 #include "tree-pass.h"
60 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* True if bit BIT is set in VALUE. */
75 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
77 /* Classifies an address.
80 A natural register + offset address. The register satisfies
81 riscv_valid_base_register_p and the offset is a const_arith_operand.
84 A LO_SUM rtx. The first operand is a valid base register and
85 the second operand is a symbolic address.
88 A signed 16-bit constant address.
91 A constant symbolic address. */
92 enum riscv_address_type
{
99 /* Information about a function's frame layout. */
100 struct GTY(()) riscv_frame_info
{
101 /* The size of the frame in bytes. */
102 HOST_WIDE_INT total_size
;
104 /* Bit X is set if the function saves or restores GPR X. */
107 /* Likewise FPR X. */
110 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
111 unsigned save_libcall_adjustment
;
113 /* Offsets of fixed-point and floating-point save areas from frame bottom */
114 HOST_WIDE_INT gp_sp_offset
;
115 HOST_WIDE_INT fp_sp_offset
;
117 /* Offset of virtual frame pointer from stack pointer/frame bottom */
118 HOST_WIDE_INT frame_pointer_offset
;
120 /* Offset of hard frame pointer from stack pointer/frame bottom */
121 HOST_WIDE_INT hard_frame_pointer_offset
;
123 /* The offset of arg_pointer_rtx from the bottom of the frame. */
124 HOST_WIDE_INT arg_pointer_offset
;
127 enum riscv_privilege_levels
{
128 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
131 struct GTY(()) machine_function
{
132 /* The number of extra stack bytes taken up by register varargs.
133 This area is allocated by the callee at the very top of the frame. */
136 /* True if current function is a naked function. */
139 /* True if current function is an interrupt function. */
140 bool interrupt_handler_p
;
141 /* For an interrupt handler, indicates the privilege level. */
142 enum riscv_privilege_levels interrupt_mode
;
144 /* True if attributes on current function have been checked. */
145 bool attributes_checked_p
;
147 /* The current frame information, calculated by riscv_compute_frame_info. */
148 struct riscv_frame_info frame
;
151 /* Information about a single argument. */
152 struct riscv_arg_info
{
153 /* True if the argument is at least partially passed on the stack. */
156 /* The number of integer registers allocated to this argument. */
157 unsigned int num_gprs
;
159 /* The offset of the first register used, provided num_gprs is nonzero.
160 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
161 unsigned int gpr_offset
;
163 /* The number of floating-point registers allocated to this argument. */
164 unsigned int num_fprs
;
166 /* The offset of the first register used, provided num_fprs is nonzero. */
167 unsigned int fpr_offset
;
170 /* Information about an address described by riscv_address_type.
176 REG is the base register and OFFSET is the constant offset.
179 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
180 is the type of symbol it references.
183 SYMBOL_TYPE is the type of symbol that the address references. */
184 struct riscv_address_info
{
185 enum riscv_address_type type
;
188 enum riscv_symbol_type symbol_type
;
191 /* One stage in a constant building sequence. These sequences have
195 A = A CODE[1] VALUE[1]
196 A = A CODE[2] VALUE[2]
199 where A is an accumulator, each CODE[i] is a binary rtl operation
200 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
201 struct riscv_integer_op
{
203 unsigned HOST_WIDE_INT value
;
206 /* The largest number of operations needed to load an integer constant.
207 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
208 #define RISCV_MAX_INTEGER_OPS 8
210 /* Costs of various operations on the different architectures. */
212 struct riscv_tune_info
214 unsigned short fp_add
[2];
215 unsigned short fp_mul
[2];
216 unsigned short fp_div
[2];
217 unsigned short int_mul
[2];
218 unsigned short int_div
[2];
219 unsigned short issue_rate
;
220 unsigned short branch_cost
;
221 unsigned short memory_cost
;
222 bool slow_unaligned_access
;
225 /* Information about one CPU we know about. */
226 struct riscv_cpu_info
{
227 /* This CPU's canonical name. */
230 /* Which automaton to use for tuning. */
231 enum riscv_microarchitecture_type microarchitecture
;
233 /* Tuning parameters for this CPU. */
234 const struct riscv_tune_info
*tune_info
;
237 /* Global variables for machine-dependent things. */
239 /* Whether unaligned accesses execute very slowly. */
240 bool riscv_slow_unaligned_access_p
;
242 /* Stack alignment to assume/maintain. */
243 unsigned riscv_stack_boundary
;
245 /* If non-zero, this is an offset to be added to SP to redefine the CFA
246 when restoring the FP register from the stack. Only valid when generating
248 static int epilogue_cfa_sp_offset
;
250 /* Which tuning parameters to use. */
251 static const struct riscv_tune_info
*tune_info
;
253 /* Which automaton to use for tuning. */
254 enum riscv_microarchitecture_type riscv_microarchitecture
;
256 /* Index R is the smallest register class that contains register R. */
257 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
258 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
259 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
260 JALR_REGS
, JALR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
261 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
262 SIBCALL_REGS
, SIBCALL_REGS
, JALR_REGS
, JALR_REGS
,
263 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
264 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
265 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
266 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
267 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
268 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
269 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
270 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
271 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
272 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
273 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
274 FRAME_REGS
, FRAME_REGS
,
277 /* Costs to use when optimizing for rocket. */
278 static const struct riscv_tune_info rocket_tune_info
= {
279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
280 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
281 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
282 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
283 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
287 true, /* slow_unaligned_access */
290 /* Costs to use when optimizing for Sifive 7 Series. */
291 static const struct riscv_tune_info sifive_7_tune_info
= {
292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
293 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
294 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
295 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
296 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
300 true, /* slow_unaligned_access */
303 /* Costs to use when optimizing for size. */
304 static const struct riscv_tune_info optimize_size_tune_info
= {
305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
309 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
313 false, /* slow_unaligned_access */
316 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
317 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
319 /* Defining target-specific uses of __attribute__. */
320 static const struct attribute_spec riscv_attribute_table
[] =
322 /* Syntax: { name, min_len, max_len, decl_required, type_required,
323 function_type_required, affects_type_identity, handler,
326 /* The attribute telling no prologue/epilogue. */
327 { "naked", 0, 0, true, false, false, false,
328 riscv_handle_fndecl_attribute
, NULL
},
329 /* This attribute generates prologue/epilogue for interrupt handlers. */
330 { "interrupt", 0, 1, false, true, true, false,
331 riscv_handle_type_attribute
, NULL
},
333 /* The last attribute spec is set to be NULL. */
334 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
337 /* Order for the CLOBBERs/USEs of gpr_save. */
338 static const unsigned gpr_save_reg_order
[] = {
339 INVALID_REGNUM
, T0_REGNUM
, T1_REGNUM
, RETURN_ADDR_REGNUM
,
340 S0_REGNUM
, S1_REGNUM
, S2_REGNUM
, S3_REGNUM
, S4_REGNUM
,
341 S5_REGNUM
, S6_REGNUM
, S7_REGNUM
, S8_REGNUM
, S9_REGNUM
,
342 S10_REGNUM
, S11_REGNUM
345 /* A table describing all the processors GCC knows about. */
346 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
347 { "rocket", generic
, &rocket_tune_info
},
348 { "sifive-3-series", generic
, &rocket_tune_info
},
349 { "sifive-5-series", generic
, &rocket_tune_info
},
350 { "sifive-7-series", sifive_7
, &sifive_7_tune_info
},
351 { "size", generic
, &optimize_size_tune_info
},
354 /* Return the riscv_cpu_info entry for the given name string. */
356 static const struct riscv_cpu_info
*
357 riscv_parse_cpu (const char *cpu_string
)
359 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
360 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
361 return riscv_cpu_info_table
+ i
;
363 error ("unknown cpu %qs for %<-mtune%>", cpu_string
);
364 return riscv_cpu_info_table
;
367 /* Helper function for riscv_build_integer; arguments are as for
368 riscv_build_integer. */
371 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
372 HOST_WIDE_INT value
, machine_mode mode
)
374 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
375 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
376 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
378 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
380 /* Simply ADDI or LUI. */
381 codes
[0].code
= UNKNOWN
;
382 codes
[0].value
= value
;
386 /* End with ADDI. When constructing HImode constants, do not generate any
387 intermediate value that is not itself a valid HImode constant. The
388 XORI case below will handle those remaining HImode constants. */
391 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
393 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
396 alt_codes
[alt_cost
-1].code
= PLUS
;
397 alt_codes
[alt_cost
-1].value
= low_part
;
398 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
404 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
406 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
409 alt_codes
[alt_cost
-1].code
= XOR
;
410 alt_codes
[alt_cost
-1].value
= low_part
;
411 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
416 /* Eliminate trailing zeros and end with SLLI. */
417 if (cost
> 2 && (value
& 1) == 0)
419 int shift
= ctz_hwi (value
);
420 unsigned HOST_WIDE_INT x
= value
;
421 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
423 /* Don't eliminate the lower 12 bits if LUI might apply. */
424 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
425 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
427 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
430 alt_codes
[alt_cost
-1].code
= ASHIFT
;
431 alt_codes
[alt_cost
-1].value
= shift
;
432 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
437 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
441 /* Fill CODES with a sequence of rtl operations to load VALUE.
442 Return the number of operations needed. */
445 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
448 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
450 /* Eliminate leading zeros and end with SRLI. */
451 if (value
> 0 && cost
> 2)
453 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
454 int alt_cost
, shift
= clz_hwi (value
);
455 HOST_WIDE_INT shifted_val
;
457 /* Try filling trailing bits with 1s. */
458 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
459 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
462 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
463 alt_codes
[alt_cost
-1].value
= shift
;
464 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
468 /* Try filling trailing bits with 0s. */
469 shifted_val
= value
<< shift
;
470 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
473 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
474 alt_codes
[alt_cost
-1].value
= shift
;
475 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
483 /* Return the cost of constructing VAL in the event that a scratch
484 register is available. */
487 riscv_split_integer_cost (HOST_WIDE_INT val
)
490 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
491 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
492 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
494 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
496 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
501 /* Return the cost of constructing the integer constant VAL. */
504 riscv_integer_cost (HOST_WIDE_INT val
)
506 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
507 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
508 riscv_split_integer_cost (val
));
511 /* Try to split a 64b integer into 32b parts, then reassemble. */
514 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
516 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
517 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
518 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
520 riscv_move_integer (hi
, hi
, hival
, mode
, FALSE
);
521 riscv_move_integer (lo
, lo
, loval
, mode
, FALSE
);
523 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
524 hi
= force_reg (mode
, hi
);
526 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
529 /* Return true if X is a thread-local symbol. */
532 riscv_tls_symbol_p (const_rtx x
)
534 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
537 /* Return true if symbol X binds locally. */
540 riscv_symbol_binds_local_p (const_rtx x
)
542 if (SYMBOL_REF_P (x
))
543 return (SYMBOL_REF_DECL (x
)
544 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
545 : SYMBOL_REF_LOCAL_P (x
));
550 /* Return the method that should be used to access SYMBOL_REF or
553 static enum riscv_symbol_type
554 riscv_classify_symbol (const_rtx x
)
556 if (riscv_tls_symbol_p (x
))
559 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
560 return SYMBOL_GOT_DISP
;
562 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
565 /* Classify the base of symbolic expression X. */
567 enum riscv_symbol_type
568 riscv_classify_symbolic_expression (rtx x
)
572 split_const (x
, &x
, &offset
);
573 if (UNSPEC_ADDRESS_P (x
))
574 return UNSPEC_ADDRESS_TYPE (x
);
576 return riscv_classify_symbol (x
);
579 /* Return true if X is a symbolic constant. If it is, store the type of
580 the symbol in *SYMBOL_TYPE. */
583 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
587 split_const (x
, &x
, &offset
);
588 if (UNSPEC_ADDRESS_P (x
))
590 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
591 x
= UNSPEC_ADDRESS (x
);
593 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
594 *symbol_type
= riscv_classify_symbol (x
);
598 if (offset
== const0_rtx
)
601 /* Nonzero offsets are only valid for references that don't use the GOT. */
602 switch (*symbol_type
)
604 case SYMBOL_ABSOLUTE
:
607 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
608 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
615 /* Returns the number of instructions necessary to reference a symbol. */
617 static int riscv_symbol_insns (enum riscv_symbol_type type
)
621 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
622 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
623 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
624 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
625 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
626 default: gcc_unreachable ();
630 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
633 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
635 return riscv_const_insns (x
) > 0;
638 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
641 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
643 enum riscv_symbol_type type
;
646 /* There is no assembler syntax for expressing an address-sized
648 if (GET_CODE (x
) == HIGH
)
651 split_const (x
, &base
, &offset
);
652 if (riscv_symbolic_constant_p (base
, &type
))
654 /* As an optimization, don't spill symbolic constants that are as
655 cheap to rematerialize as to access in the constant pool. */
656 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
659 /* As an optimization, avoid needlessly generate dynamic relocations. */
664 /* TLS symbols must be computed by riscv_legitimize_move. */
665 if (tls_referenced_p (x
))
671 /* Return true if register REGNO is a valid base register for mode MODE.
672 STRICT_P is true if REG_OK_STRICT is in effect. */
675 riscv_regno_mode_ok_for_base_p (int regno
,
676 machine_mode mode ATTRIBUTE_UNUSED
,
679 if (!HARD_REGISTER_NUM_P (regno
))
683 regno
= reg_renumber
[regno
];
686 /* These fake registers will be eliminated to either the stack or
687 hard frame pointer, both of which are usually valid base registers.
688 Reload deals with the cases where the eliminated form isn't valid. */
689 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
692 return GP_REG_P (regno
);
695 /* Return true if X is a valid base register for mode MODE.
696 STRICT_P is true if REG_OK_STRICT is in effect. */
699 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
701 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
705 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
708 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
709 can address a value of mode MODE. */
712 riscv_valid_offset_p (rtx x
, machine_mode mode
)
714 /* Check that X is a signed 12-bit number. */
715 if (!const_arith_operand (x
, Pmode
))
718 /* We may need to split multiword moves, so make sure that every word
720 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
721 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
727 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
730 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
732 if (symbol_type
== SYMBOL_TLS_LE
)
735 if (!TARGET_EXPLICIT_RELOCS
)
738 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
741 /* Return true if a LO_SUM can address a value of mode MODE when the
742 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
743 is used when the mode is BLKmode. */
746 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
,
751 /* Check that symbols of type SYMBOL_TYPE can be used to access values
753 if (riscv_symbol_insns (sym_type
) == 0)
756 /* Check that there is a known low-part relocation. */
757 if (!riscv_split_symbol_type (sym_type
))
760 /* We can't tell size or alignment when we have BLKmode, so try extracing a
761 decl from the symbol if possible. */
766 /* Extract the symbol from the LO_SUM operand, if any. */
767 split_const (x
, &x
, &offset
);
769 /* Might be a CODE_LABEL. We can compute align but not size for that,
770 so don't bother trying to handle it. */
771 if (!SYMBOL_REF_P (x
))
774 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
775 align
= (SYMBOL_REF_DECL (x
)
776 ? DECL_ALIGN (SYMBOL_REF_DECL (x
))
778 size
= (SYMBOL_REF_DECL (x
) && DECL_SIZE (SYMBOL_REF_DECL (x
))
779 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x
)))
784 align
= GET_MODE_ALIGNMENT (mode
);
785 size
= GET_MODE_BITSIZE (mode
);
788 /* We may need to split multiword moves, so make sure that each word
789 can be accessed without inducing a carry. */
790 if (size
> BITS_PER_WORD
791 && (!TARGET_STRICT_ALIGN
|| size
> align
))
797 /* Return true if X is a valid address for machine mode MODE. If it is,
798 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
802 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
803 machine_mode mode
, bool strict_p
)
805 switch (GET_CODE (x
))
809 info
->type
= ADDRESS_REG
;
811 info
->offset
= const0_rtx
;
812 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
815 info
->type
= ADDRESS_REG
;
816 info
->reg
= XEXP (x
, 0);
817 info
->offset
= XEXP (x
, 1);
818 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
819 && riscv_valid_offset_p (info
->offset
, mode
));
822 info
->type
= ADDRESS_LO_SUM
;
823 info
->reg
= XEXP (x
, 0);
824 info
->offset
= XEXP (x
, 1);
825 /* We have to trust the creator of the LO_SUM to do something vaguely
826 sane. Target-independent code that creates a LO_SUM should also
827 create and verify the matching HIGH. Target-independent code that
828 adds an offset to a LO_SUM must prove that the offset will not
829 induce a carry. Failure to do either of these things would be
830 a bug, and we are not required to check for it here. The RISC-V
831 backend itself should only create LO_SUMs for valid symbolic
832 constants, with the high part being either a HIGH or a copy
835 = riscv_classify_symbolic_expression (info
->offset
);
836 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
837 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
, info
->offset
));
840 /* Small-integer addresses don't occur very often, but they
841 are legitimate if x0 is a valid base register. */
842 info
->type
= ADDRESS_CONST_INT
;
843 return SMALL_OPERAND (INTVAL (x
));
850 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
853 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
855 struct riscv_address_info addr
;
857 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
860 /* Return true if hard reg REGNO can be used in compressed instructions. */
863 riscv_compressed_reg_p (int regno
)
865 /* x8-x15/f8-f15 are compressible registers. */
866 return (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
867 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)));
870 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
873 riscv_compressed_lw_offset_p (rtx x
)
875 return (CONST_INT_P (x
)
876 && (INTVAL (x
) & 3) == 0
877 && IN_RANGE (INTVAL (x
), 0, CSW_MAX_OFFSET
));
880 /* Return true if load/store from/to address x can be compressed. */
883 riscv_compressed_lw_address_p (rtx x
)
885 struct riscv_address_info addr
;
886 bool result
= riscv_classify_address (&addr
, x
, GET_MODE (x
),
889 /* Before reload, assuming all load/stores of valid addresses get compressed
890 gives better code size than checking if the address is reg + small_offset
892 if (result
&& !reload_completed
)
895 /* Return false if address is not compressed_reg + small_offset. */
897 || addr
.type
!= ADDRESS_REG
898 || (!riscv_compressed_reg_p (REGNO (addr
.reg
))
899 && addr
.reg
!= stack_pointer_rtx
)
900 || !riscv_compressed_lw_offset_p (addr
.offset
))
906 /* Return the number of instructions needed to load or store a value
907 of mode MODE at address X. Return 0 if X isn't valid for MODE.
908 Assume that multiword moves may need to be split into word moves
909 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
913 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
915 struct riscv_address_info addr
= {};
918 if (!riscv_classify_address (&addr
, x
, mode
, false))
920 /* This could be a pattern from the pic.md file. In which case we want
921 this address to always have a cost of 3 to make it as expensive as the
922 most expensive symbol. This prevents constant propagation from
923 preferring symbols over register plus offset. */
927 /* BLKmode is used for single unaligned loads and stores and should
928 not count as a multiword mode. */
929 if (mode
!= BLKmode
&& might_split_p
)
930 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
932 if (addr
.type
== ADDRESS_LO_SUM
)
933 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
938 /* Return the number of instructions needed to load constant X.
939 Return 0 if X isn't a valid constant. */
942 riscv_const_insns (rtx x
)
944 enum riscv_symbol_type symbol_type
;
947 switch (GET_CODE (x
))
950 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
951 || !riscv_split_symbol_type (symbol_type
))
954 /* This is simply an LUI. */
959 int cost
= riscv_integer_cost (INTVAL (x
));
960 /* Force complicated constants to memory. */
961 return cost
< 4 ? cost
: 0;
966 /* We can use x0 to load floating-point zero. */
967 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
970 /* See if we can refer to X directly. */
971 if (riscv_symbolic_constant_p (x
, &symbol_type
))
972 return riscv_symbol_insns (symbol_type
);
974 /* Otherwise try splitting the constant into a base and offset. */
975 split_const (x
, &x
, &offset
);
978 int n
= riscv_const_insns (x
);
980 return n
+ riscv_integer_cost (INTVAL (offset
));
986 return riscv_symbol_insns (riscv_classify_symbol (x
));
993 /* X is a doubleword constant that can be handled by splitting it into
994 two words and loading each word separately. Return the number of
995 instructions required to do this. */
998 riscv_split_const_insns (rtx x
)
1000 unsigned int low
, high
;
1002 low
= riscv_const_insns (riscv_subword (x
, false));
1003 high
= riscv_const_insns (riscv_subword (x
, true));
1004 gcc_assert (low
> 0 && high
> 0);
1008 /* Return the number of instructions needed to implement INSN,
1009 given that it loads from or stores to MEM. */
1012 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
1018 gcc_assert (MEM_P (mem
));
1019 mode
= GET_MODE (mem
);
1021 /* Try to prove that INSN does not need to be split. */
1022 might_split_p
= true;
1023 if (GET_MODE_BITSIZE (mode
) <= 32)
1024 might_split_p
= false;
1025 else if (GET_MODE_BITSIZE (mode
) == 64)
1027 set
= single_set (insn
);
1028 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
1029 might_split_p
= false;
1032 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
1035 /* Emit a move from SRC to DEST. Assume that the move expanders can
1036 handle all moves if !can_create_pseudo_p (). The distinction is
1037 important because, unlike emit_move_insn, the move expanders know
1038 how to force Pmode objects into the constant pool even when the
1039 constant pool address is not itself legitimate. */
1042 riscv_emit_move (rtx dest
, rtx src
)
1044 return (can_create_pseudo_p ()
1045 ? emit_move_insn (dest
, src
)
1046 : emit_move_insn_1 (dest
, src
));
1049 /* Emit an instruction of the form (set TARGET SRC). */
1052 riscv_emit_set (rtx target
, rtx src
)
1054 emit_insn (gen_rtx_SET (target
, src
));
1058 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1061 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
1063 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
1066 /* Compute (CODE X Y) and store the result in a new register
1067 of mode MODE. Return that new register. */
1070 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
1072 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
1075 /* Copy VALUE to a register and return that register. If new pseudos
1076 are allowed, copy it into a new register, otherwise use DEST. */
1079 riscv_force_temporary (rtx dest
, rtx value
, bool in_splitter
)
1081 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1082 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1083 combine undo buffer. */
1084 if (can_create_pseudo_p () && !in_splitter
)
1085 return force_reg (Pmode
, value
);
1088 riscv_emit_move (dest
, value
);
1093 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1094 then add CONST_INT OFFSET to the result. */
1097 riscv_unspec_address_offset (rtx base
, rtx offset
,
1098 enum riscv_symbol_type symbol_type
)
1100 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1101 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1102 if (offset
!= const0_rtx
)
1103 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1104 return gen_rtx_CONST (Pmode
, base
);
1107 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1108 type SYMBOL_TYPE. */
1111 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
1115 split_const (address
, &base
, &offset
);
1116 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
1119 /* If OP is an UNSPEC address, return the address to which it refers,
1120 otherwise return OP itself. */
1123 riscv_strip_unspec_address (rtx op
)
1127 split_const (op
, &base
, &offset
);
1128 if (UNSPEC_ADDRESS_P (base
))
1129 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1133 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1134 high part to BASE and return the result. Just return BASE otherwise.
1135 TEMP is as for riscv_force_temporary.
1137 The returned expression can be used as the first operand to a LO_SUM. */
1140 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1142 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1143 return riscv_force_temporary (temp
, addr
, FALSE
);
1146 /* Load an entry from the GOT for a TLS GD access. */
1148 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1150 if (Pmode
== DImode
)
1151 return gen_got_load_tls_gddi (dest
, sym
);
1153 return gen_got_load_tls_gdsi (dest
, sym
);
1156 /* Load an entry from the GOT for a TLS IE access. */
1158 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1160 if (Pmode
== DImode
)
1161 return gen_got_load_tls_iedi (dest
, sym
);
1163 return gen_got_load_tls_iesi (dest
, sym
);
1166 /* Add in the thread pointer for a TLS LE access. */
1168 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1170 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1171 if (Pmode
== DImode
)
1172 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1174 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1177 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1178 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1179 constant in that context and can be split into high and low parts.
1180 If so, and if LOW_OUT is nonnull, emit the high part and store the
1181 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1183 TEMP is as for riscv_force_temporary and is used to load the high
1184 part into a register.
1186 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1187 a legitimize SET_SRC for an .md pattern, otherwise the low part
1188 is guaranteed to be a legitimate address for mode MODE. */
1191 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
,
1194 enum riscv_symbol_type symbol_type
;
1196 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1197 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1198 || riscv_symbol_insns (symbol_type
) == 0
1199 || !riscv_split_symbol_type (symbol_type
))
1203 switch (symbol_type
)
1205 case SYMBOL_ABSOLUTE
:
1207 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1208 high
= riscv_force_temporary (temp
, high
, in_splitter
);
1209 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1215 static unsigned seqno
;
1219 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1220 gcc_assert ((size_t) bytes
< sizeof (buf
));
1222 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1223 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1224 /* ??? Ugly hack to make weak symbols work. May need to change the
1225 RTL for the auipc and/or low patterns to get a better fix for
1227 if (! nonzero_address_p (addr
))
1228 SYMBOL_REF_WEAK (label
) = 1;
1231 temp
= gen_reg_rtx (Pmode
);
1233 if (Pmode
== DImode
)
1234 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1236 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1238 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1251 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1252 riscv_force_temporary; it is only needed when OFFSET is not a
1256 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1258 if (!SMALL_OPERAND (offset
))
1262 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1263 The addition inside the macro CONST_HIGH_PART may cause an
1264 overflow, so we need to force a sign-extension check. */
1265 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1266 offset
= CONST_LOW_PART (offset
);
1267 high
= riscv_force_temporary (temp
, high
, FALSE
);
1268 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
),
1271 return plus_constant (Pmode
, reg
, offset
);
1274 /* The __tls_get_attr symbol. */
1275 static GTY(()) rtx riscv_tls_symbol
;
1277 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1278 the TLS symbol we are referencing and TYPE is the symbol type to use
1279 (either global dynamic or local dynamic). RESULT is an RTX for the
1280 return value location. */
1283 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1285 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1288 if (!riscv_tls_symbol
)
1289 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1290 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1294 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1295 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1296 RTL_CONST_CALL_P (insn
) = 1;
1297 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1298 insn
= get_insns ();
1305 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1306 its address. The return value will be both a valid address and a valid
1307 SET_SRC (either a REG or a LO_SUM). */
1310 riscv_legitimize_tls_address (rtx loc
)
1313 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1316 /* TLS copy relocs are now deprecated and should not be used. */
1317 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1319 model
= TLS_MODEL_LOCAL_EXEC
;
1324 case TLS_MODEL_LOCAL_DYNAMIC
:
1325 /* Rely on section anchors for the optimization that LDM TLS
1326 provides. The anchor's address is loaded with GD TLS. */
1327 case TLS_MODEL_GLOBAL_DYNAMIC
:
1328 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1329 dest
= gen_reg_rtx (Pmode
);
1330 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1333 case TLS_MODEL_INITIAL_EXEC
:
1334 /* la.tls.ie; tp-relative add */
1335 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1336 tmp
= gen_reg_rtx (Pmode
);
1337 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1338 dest
= gen_reg_rtx (Pmode
);
1339 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1342 case TLS_MODEL_LOCAL_EXEC
:
1343 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1344 dest
= gen_reg_rtx (Pmode
);
1345 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1346 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1347 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1356 /* If X is not a valid address for mode MODE, force it into a register. */
1359 riscv_force_address (rtx x
, machine_mode mode
)
1361 if (!riscv_legitimate_address_p (mode
, x
, false))
1362 x
= force_reg (Pmode
, x
);
1366 /* Modify base + offset so that offset fits within a compressed load/store insn
1367 and the excess is added to base. */
1370 riscv_shorten_lw_offset (rtx base
, HOST_WIDE_INT offset
)
1373 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
1375 high
= GEN_INT (offset
& ~CSW_MAX_OFFSET
);
1376 offset
&= CSW_MAX_OFFSET
;
1377 if (!SMALL_OPERAND (INTVAL (high
)))
1378 high
= force_reg (Pmode
, high
);
1379 base
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, high
, base
));
1380 addr
= plus_constant (Pmode
, base
, offset
);
1384 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1385 be legitimized in a way that the generic machinery might not expect,
1386 return a new address, otherwise return NULL. MODE is the mode of
1387 the memory being accessed. */
1390 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1395 if (riscv_tls_symbol_p (x
))
1396 return riscv_legitimize_tls_address (x
);
1398 /* See if the address can split into a high part and a LO_SUM. */
1399 if (riscv_split_symbol (NULL
, x
, mode
, &addr
, FALSE
))
1400 return riscv_force_address (addr
, mode
);
1402 /* Handle BASE + OFFSET. */
1403 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1404 && INTVAL (XEXP (x
, 1)) != 0)
1406 rtx base
= XEXP (x
, 0);
1407 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1409 if (!riscv_valid_base_register_p (base
, mode
, false))
1410 base
= copy_to_mode_reg (Pmode
, base
);
1411 if (optimize_function_for_size_p (cfun
)
1412 && (strcmp (current_pass
->name
, "shorten_memrefs") == 0)
1414 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
1415 possible compressed load/store. */
1416 addr
= riscv_shorten_lw_offset (base
, offset
);
1418 addr
= riscv_add_offset (NULL
, base
, offset
);
1419 return riscv_force_address (addr
, mode
);
1425 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
1426 is the original src mode before promotion. */
1429 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
,
1430 machine_mode orig_mode
, bool in_splitter
)
1432 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1437 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1438 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1439 combine undo buffer. */
1440 bool can_create_pseudo
= can_create_pseudo_p () && ! in_splitter
;
1442 mode
= GET_MODE (dest
);
1443 /* We use the original mode for the riscv_build_integer call, because HImode
1444 values are given special treatment. */
1445 num_ops
= riscv_build_integer (codes
, value
, orig_mode
);
1447 if (can_create_pseudo
&& num_ops
> 2 /* not a simple constant */
1448 && num_ops
>= riscv_split_integer_cost (value
))
1449 x
= riscv_split_integer (value
, mode
);
1452 /* Apply each binary operation to X. */
1453 x
= GEN_INT (codes
[0].value
);
1455 for (i
= 1; i
< num_ops
; i
++)
1457 if (!can_create_pseudo
)
1458 x
= riscv_emit_set (temp
, x
);
1460 x
= force_reg (mode
, x
);
1462 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1466 riscv_emit_set (dest
, x
);
1469 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1470 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1474 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1478 /* Split moves of big integers into smaller pieces. */
1479 if (splittable_const_int_operand (src
, mode
))
1481 riscv_move_integer (dest
, dest
, INTVAL (src
), mode
, FALSE
);
1485 /* Split moves of symbolic constants into high/low pairs. */
1486 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
, FALSE
))
1488 riscv_emit_set (dest
, src
);
1492 /* Generate the appropriate access sequences for TLS symbols. */
1493 if (riscv_tls_symbol_p (src
))
1495 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1499 /* If we have (const (plus symbol offset)), and that expression cannot
1500 be forced into memory, load the symbol first and add in the offset. Also
1501 prefer to do this even if the constant _can_ be forced into memory, as it
1502 usually produces better code. */
1503 split_const (src
, &base
, &offset
);
1504 if (offset
!= const0_rtx
1505 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1507 base
= riscv_force_temporary (dest
, base
, FALSE
);
1508 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1512 src
= force_const_mem (mode
, src
);
1514 /* When using explicit relocs, constant pool references are sometimes
1515 not legitimate addresses. */
1516 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0), FALSE
);
1517 riscv_emit_move (dest
, src
);
1520 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1521 sequence that is valid. */
1524 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1526 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1530 if (GET_CODE (src
) == CONST_INT
)
1532 /* Apply the equivalent of PROMOTE_MODE here for constants to
1534 machine_mode promoted_mode
= mode
;
1535 if (GET_MODE_CLASS (mode
) == MODE_INT
1536 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
1537 promoted_mode
= word_mode
;
1539 if (splittable_const_int_operand (src
, mode
))
1541 reg
= gen_reg_rtx (promoted_mode
);
1542 riscv_move_integer (reg
, reg
, INTVAL (src
), mode
, FALSE
);
1545 reg
= force_reg (promoted_mode
, src
);
1547 if (promoted_mode
!= mode
)
1548 reg
= gen_lowpart (mode
, reg
);
1551 reg
= force_reg (mode
, src
);
1552 riscv_emit_move (dest
, reg
);
1556 /* We need to deal with constants that would be legitimate
1557 immediate_operands but aren't legitimate move_operands. */
1558 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1560 riscv_legitimize_const_move (mode
, dest
, src
);
1561 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1565 /* RISC-V GCC may generate non-legitimate address due to we provide some
1566 pattern for optimize access PIC local symbol and it's make GCC generate
1567 unrecognizable instruction during optmizing. */
1569 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1572 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1575 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1578 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1584 /* Return true if there is an instruction that implements CODE and accepts
1585 X as an immediate operand. */
1588 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1595 /* All shift counts are truncated to a valid constant. */
1604 /* These instructions take 12-bit signed immediates. */
1605 return SMALL_OPERAND (x
);
1608 /* We add 1 to the immediate and use SLT. */
1609 return SMALL_OPERAND (x
+ 1);
1612 /* Likewise SLTU, but reject the always-true case. */
1613 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1617 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1621 /* By default assume that x0 can be used for 0. */
1626 /* Return the cost of binary operation X, given that the instruction
1627 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1628 instructions and that the sequence of a double-word operation takes
1629 DOUBLE_INSNS instructions. */
1632 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1634 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1635 return COSTS_N_INSNS (double_insns
);
1636 return COSTS_N_INSNS (single_insns
);
1639 /* Return the cost of sign- or zero-extending OP. */
1642 riscv_extend_cost (rtx op
, bool unsigned_p
)
1647 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1648 /* We can use ANDI. */
1649 return COSTS_N_INSNS (1);
1651 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1652 /* We can use SEXT.W. */
1653 return COSTS_N_INSNS (1);
1655 /* We need to use a shift left and a shift right. */
1656 return COSTS_N_INSNS (2);
1659 /* Implement TARGET_RTX_COSTS. */
1661 #define SINGLE_SHIFT_COST 1
1664 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1665 int *total
, bool speed
)
1667 bool float_mode_p
= FLOAT_MODE_P (mode
);
1670 switch (GET_CODE (x
))
1673 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1684 if ((cost
= riscv_const_insns (x
)) > 0)
1686 /* If the constant is likely to be stored in a GPR, SETs of
1687 single-insn constants are as cheap as register sets; we
1688 never want to CSE them. */
1689 if (cost
== 1 && outer_code
== SET
)
1691 /* When we load a constant more than once, it usually is better
1692 to duplicate the last operation in the sequence than to CSE
1693 the constant itself. */
1694 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1695 *total
= COSTS_N_INSNS (1);
1697 else /* The instruction will be fetched from the constant pool. */
1698 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1702 /* If the address is legitimate, return the number of
1703 instructions it needs. */
1704 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1706 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1709 /* Otherwise use the default handling. */
1713 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1719 /* Double-word operations use two single-word operations. */
1720 *total
= riscv_binary_cost (x
, 1, 2);
1724 /* This is an SImode shift. */
1725 if (outer_code
== SET
1726 && CONST_INT_P (XEXP (x
, 1))
1727 && CONST_INT_P (XEXP (x
, 2))
1728 && (INTVAL (XEXP (x
, 2)) > 0)
1729 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1731 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1739 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1740 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1744 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1748 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1752 /* This is an SImode shift. */
1753 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1754 && GET_MODE (XEXP (x
, 0)) == SImode
)
1756 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1769 /* Branch comparisons have VOIDmode, so use the first operand's
1771 mode
= GET_MODE (XEXP (x
, 0));
1773 *total
= tune_info
->fp_add
[mode
== DFmode
];
1775 *total
= riscv_binary_cost (x
, 1, 3);
1780 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1781 mode
= GET_MODE (XEXP (x
, 0));
1782 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1786 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1787 mode
= GET_MODE (XEXP (x
, 0));
1788 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1792 /* (FLT(A, A) || FGT(B, B)). */
1793 mode
= GET_MODE (XEXP (x
, 0));
1794 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1801 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1802 mode
= GET_MODE (XEXP (x
, 0));
1803 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1809 *total
= tune_info
->fp_add
[mode
== DFmode
];
1811 *total
= riscv_binary_cost (x
, 1, 4);
1816 rtx op
= XEXP (x
, 0);
1817 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1819 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1820 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1821 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1822 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1828 *total
= tune_info
->fp_add
[mode
== DFmode
];
1830 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1835 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1836 else if (!TARGET_MUL
)
1837 /* Estimate the cost of a library call. */
1838 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1839 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1840 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1842 *total
= COSTS_N_INSNS (1);
1844 *total
= tune_info
->int_mul
[mode
== DImode
];
1852 *total
= tune_info
->fp_div
[mode
== DFmode
];
1860 /* Estimate the cost of a library call. */
1861 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1863 *total
= tune_info
->int_div
[mode
== DImode
];
1865 *total
= COSTS_N_INSNS (1);
1869 /* This is an SImode shift. */
1870 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1872 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1877 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1881 case UNSIGNED_FLOAT
:
1884 case FLOAT_TRUNCATE
:
1885 *total
= tune_info
->fp_add
[mode
== DFmode
];
1889 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1890 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1891 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1892 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1896 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1898 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1909 /* Implement TARGET_ADDRESS_COST. */
1912 riscv_address_cost (rtx addr
, machine_mode mode
,
1913 addr_space_t as ATTRIBUTE_UNUSED
,
1914 bool speed ATTRIBUTE_UNUSED
)
1916 /* When optimizing for size, make uncompressible 32-bit addresses more
1917 * expensive so that compressible 32-bit addresses are preferred. */
1918 if (TARGET_RVC
&& !speed
&& riscv_mshorten_memrefs
&& mode
== SImode
1919 && !riscv_compressed_lw_address_p (addr
))
1920 return riscv_address_insns (addr
, mode
, false) + 1;
1921 return riscv_address_insns (addr
, mode
, false);
1924 /* Return one word of double-word value OP. HIGH_P is true to select the
1925 high part or false to select the low part. */
1928 riscv_subword (rtx op
, bool high_p
)
1930 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1931 machine_mode mode
= GET_MODE (op
);
1933 if (mode
== VOIDmode
)
1934 mode
= TARGET_64BIT
? TImode
: DImode
;
1937 return adjust_address (op
, word_mode
, byte
);
1940 gcc_assert (!FP_REG_RTX_P (op
));
1942 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1945 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1948 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1953 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1954 of zeroing an FPR with FCVT.D.W. */
1955 if (TARGET_DOUBLE_FLOAT
1956 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1957 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1958 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1959 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1965 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1966 this function handles 64-bit moves for which riscv_split_64bit_move_p
1967 holds. For 64-bit targets, this function handles 128-bit moves. */
1970 riscv_split_doubleword_move (rtx dest
, rtx src
)
1974 /* The operation can be split into two normal moves. Decide in
1975 which order to do them. */
1976 low_dest
= riscv_subword (dest
, false);
1977 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1979 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1980 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1984 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1985 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1989 /* Return the appropriate instructions to move SRC into DEST. Assume
1990 that SRC is operand 1 and DEST is operand 0. */
1993 riscv_output_move (rtx dest
, rtx src
)
1995 enum rtx_code dest_code
, src_code
;
1999 dest_code
= GET_CODE (dest
);
2000 src_code
= GET_CODE (src
);
2001 mode
= GET_MODE (dest
);
2002 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
2004 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
2007 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2009 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2010 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
2012 if (src_code
== MEM
)
2013 switch (GET_MODE_SIZE (mode
))
2015 case 1: return "lbu\t%0,%1";
2016 case 2: return "lhu\t%0,%1";
2017 case 4: return "lw\t%0,%1";
2018 case 8: return "ld\t%0,%1";
2021 if (src_code
== CONST_INT
)
2024 if (src_code
== HIGH
)
2025 return "lui\t%0,%h1";
2027 if (symbolic_operand (src
, VOIDmode
))
2028 switch (riscv_classify_symbolic_expression (src
))
2030 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
2031 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
2032 case SYMBOL_PCREL
: return "lla\t%0,%1";
2033 default: gcc_unreachable ();
2036 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2037 || (src
== CONST0_RTX (mode
)))
2039 if (dest_code
== REG
)
2041 if (GP_REG_P (REGNO (dest
)))
2042 return "mv\t%0,%z1";
2044 if (FP_REG_P (REGNO (dest
)))
2047 return "fmv.w.x\t%0,%z1";
2049 return "fmv.d.x\t%0,%z1";
2050 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
2051 gcc_assert (src
== CONST0_RTX (mode
));
2052 return "fcvt.d.w\t%0,x0";
2055 if (dest_code
== MEM
)
2056 switch (GET_MODE_SIZE (mode
))
2058 case 1: return "sb\t%z1,%0";
2059 case 2: return "sh\t%z1,%0";
2060 case 4: return "sw\t%z1,%0";
2061 case 8: return "sd\t%z1,%0";
2064 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2066 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2067 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
2069 if (dest_code
== MEM
)
2070 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
2072 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2074 if (src_code
== MEM
)
2075 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
2081 riscv_output_return ()
2083 if (cfun
->machine
->naked_p
)
2090 /* Return true if CMP1 is a suitable second operand for integer ordering
2091 test CODE. See also the *sCC patterns in riscv.md. */
2094 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
2100 return reg_or_0_operand (cmp1
, VOIDmode
);
2104 return cmp1
== const1_rtx
;
2108 return arith_operand (cmp1
, VOIDmode
);
2111 return sle_operand (cmp1
, VOIDmode
);
2114 return sleu_operand (cmp1
, VOIDmode
);
2121 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
2122 integer ordering test *CODE, or if an equivalent combination can
2123 be formed by adjusting *CODE and *CMP1. When returning true, update
2124 *CODE and *CMP1 with the chosen code and operand, otherwise leave
2128 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
2131 HOST_WIDE_INT plus_one
;
2133 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
2136 if (CONST_INT_P (*cmp1
))
2140 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2141 if (INTVAL (*cmp1
) < plus_one
)
2144 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2150 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2154 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2165 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2166 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2167 is nonnull, it's OK to set TARGET to the inverse of the result and
2168 flip *INVERT_PTR instead. */
2171 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
2172 rtx target
, rtx cmp0
, rtx cmp1
)
2176 /* First see if there is a RISCV instruction that can do this operation.
2177 If not, try doing the same for the inverse operation. If that also
2178 fails, force CMP1 into a register and try again. */
2179 mode
= GET_MODE (cmp0
);
2180 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
2181 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
2184 enum rtx_code inv_code
= reverse_condition (code
);
2185 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
2187 cmp1
= force_reg (mode
, cmp1
);
2188 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
2190 else if (invert_ptr
== 0)
2192 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
2193 inv_code
, cmp0
, cmp1
);
2194 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2198 *invert_ptr
= !*invert_ptr
;
2199 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2204 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2205 The register will have the same mode as CMP0. */
2208 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2210 if (cmp1
== const0_rtx
)
2213 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2214 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2217 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2220 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2222 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2223 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2225 /* It is more profitable to zero-extend QImode values. But not if the
2226 first operand has already been sign-extended, and the second one is
2227 is a constant or has already been sign-extended also. */
2228 if (unsigned_condition (code
) == code
2229 && (GET_MODE (*op0
) == QImode
2230 && ! (GET_CODE (*op0
) == SUBREG
2231 && SUBREG_PROMOTED_VAR_P (*op0
)
2232 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2233 && (CONST_INT_P (*op1
)
2234 || (GET_CODE (*op1
) == SUBREG
2235 && SUBREG_PROMOTED_VAR_P (*op1
)
2236 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2238 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2239 if (CONST_INT_P (*op1
))
2240 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2242 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2246 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2247 if (*op1
!= const0_rtx
)
2248 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2253 /* Convert a comparison into something that can be used in a branch. On
2254 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2255 used to compare them. Update them to describe the final comparison. */
2258 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2260 if (splittable_const_int_operand (*op1
, VOIDmode
))
2262 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2264 if (*code
== EQ
|| *code
== NE
)
2266 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2267 if (SMALL_OPERAND (-rhs
))
2269 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2276 static const enum rtx_code mag_comparisons
[][2] = {
2277 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2280 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2281 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2283 HOST_WIDE_INT new_rhs
;
2284 bool increment
= *code
== mag_comparisons
[i
][0];
2285 bool decrement
= *code
== mag_comparisons
[i
][1];
2286 if (!increment
&& !decrement
)
2289 new_rhs
= rhs
+ (increment
? 1 : -1);
2290 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2291 && (rhs
< 0) == (new_rhs
< 0))
2293 *op1
= GEN_INT (new_rhs
);
2294 *code
= mag_comparisons
[i
][increment
];
2301 riscv_extend_comparands (*code
, op0
, op1
);
2303 *op0
= force_reg (word_mode
, *op0
);
2304 if (*op1
!= const0_rtx
)
2305 *op1
= force_reg (word_mode
, *op1
);
2308 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2311 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2313 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2314 enum rtx_code fp_code
= *code
;
2324 /* a == a && b == b */
2325 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2326 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2327 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2332 /* ordered(a, b) > (a == b) */
2334 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2335 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2336 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2337 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2340 #define UNORDERED_COMPARISON(CODE, CMP) \
2343 *op0 = gen_reg_rtx (word_mode); \
2344 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2345 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2346 else if (GET_MODE (cmp_op0) == SFmode) \
2347 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2348 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2349 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2350 else if (GET_MODE (cmp_op0) == DFmode) \
2351 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2353 gcc_unreachable (); \
2354 *op1 = const0_rtx; \
2358 std::swap (cmp_op0
, cmp_op1
);
2361 UNORDERED_COMPARISON(UNGT
, le
)
2364 std::swap (cmp_op0
, cmp_op1
);
2367 UNORDERED_COMPARISON(UNGE
, lt
)
2368 #undef UNORDERED_COMPARISON
2380 /* We have instructions for these cases. */
2381 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2386 /* (a < b) | (a > b) */
2387 tmp0
= riscv_force_binary (word_mode
, LT
, cmp_op0
, cmp_op1
);
2388 tmp1
= riscv_force_binary (word_mode
, GT
, cmp_op0
, cmp_op1
);
2389 *op0
= riscv_force_binary (word_mode
, IOR
, tmp0
, tmp1
);
2398 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2401 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2403 riscv_extend_comparands (code
, &op0
, &op1
);
2404 op0
= force_reg (word_mode
, op0
);
2406 if (code
== EQ
|| code
== NE
)
2408 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2409 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2412 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2415 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2418 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2420 riscv_emit_float_compare (&code
, &op0
, &op1
);
2422 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2423 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2426 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2429 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2431 if (FLOAT_MODE_P (GET_MODE (op1
)))
2432 riscv_emit_float_compare (&code
, &op0
, &op1
);
2434 riscv_emit_int_compare (&code
, &op0
, &op1
);
2436 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2437 emit_jump_insn (gen_condjump (condition
, label
));
2440 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
2443 riscv_expand_conditional_move (rtx dest
, rtx cons
, rtx alt
, rtx_code code
,
2446 riscv_emit_int_compare (&code
, &op0
, &op1
);
2447 rtx cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
2448 emit_insn (gen_rtx_SET (dest
, gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), cond
,
2452 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2453 least PARM_BOUNDARY bits of alignment, but will be given anything up
2454 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2457 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2459 unsigned int alignment
;
2461 /* Use natural alignment if the type is not aggregate data. */
2462 if (type
&& !AGGREGATE_TYPE_P (type
))
2463 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2465 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2467 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2470 /* If MODE represents an argument that can be passed or returned in
2471 floating-point registers, return the number of registers, else 0. */
2474 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2476 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2478 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2481 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2490 HOST_WIDE_INT offset
;
2491 } riscv_aggregate_field
;
2493 /* Identify subfields of aggregates that are candidates for passing in
2494 floating-point registers. */
2497 riscv_flatten_aggregate_field (const_tree type
,
2498 riscv_aggregate_field fields
[2],
2499 int n
, HOST_WIDE_INT offset
,
2500 bool ignore_zero_width_bit_field_p
)
2502 switch (TREE_CODE (type
))
2505 /* Can't handle incomplete types nor sizes that are not fixed. */
2506 if (!COMPLETE_TYPE_P (type
)
2507 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2508 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2511 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2512 if (TREE_CODE (f
) == FIELD_DECL
)
2514 if (!TYPE_P (TREE_TYPE (f
)))
2517 /* The C++ front end strips zero-length bit-fields from structs.
2518 So we need to ignore them in the C front end to make C code
2519 compatible with C++ code. */
2520 if (ignore_zero_width_bit_field_p
2521 && DECL_BIT_FIELD (f
)
2522 && (DECL_SIZE (f
) == NULL_TREE
2523 || integer_zerop (DECL_SIZE (f
))))
2527 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2528 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
),
2530 ignore_zero_width_bit_field_p
);
2539 HOST_WIDE_INT n_elts
;
2540 riscv_aggregate_field subfields
[2];
2541 tree index
= TYPE_DOMAIN (type
);
2542 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2543 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2544 subfields
, 0, offset
,
2545 ignore_zero_width_bit_field_p
);
2547 /* Can't handle incomplete types nor sizes that are not fixed. */
2548 if (n_subfields
<= 0
2549 || !COMPLETE_TYPE_P (type
)
2550 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2552 || !TYPE_MAX_VALUE (index
)
2553 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2554 || !TYPE_MIN_VALUE (index
)
2555 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2556 || !tree_fits_uhwi_p (elt_size
))
2559 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2560 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2561 gcc_assert (n_elts
>= 0);
2563 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2564 for (int j
= 0; j
< n_subfields
; j
++)
2569 fields
[n
] = subfields
[j
];
2570 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2578 /* Complex type need consume 2 field, so n must be 0. */
2582 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2584 if (elt_size
<= UNITS_PER_FP_ARG
)
2586 fields
[0].type
= TREE_TYPE (type
);
2587 fields
[0].offset
= offset
;
2588 fields
[1].type
= TREE_TYPE (type
);
2589 fields
[1].offset
= offset
+ elt_size
;
2599 && ((SCALAR_FLOAT_TYPE_P (type
)
2600 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2601 || (INTEGRAL_TYPE_P (type
)
2602 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2604 fields
[n
].type
= type
;
2605 fields
[n
].offset
= offset
;
2613 /* Identify candidate aggregates for passing in floating-point registers.
2614 Candidates have at most two fields after flattening. */
2617 riscv_flatten_aggregate_argument (const_tree type
,
2618 riscv_aggregate_field fields
[2],
2619 bool ignore_zero_width_bit_field_p
)
2621 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2624 return riscv_flatten_aggregate_field (type
, fields
, 0, 0,
2625 ignore_zero_width_bit_field_p
);
2628 /* See whether TYPE is a record whose fields should be returned in one or
2629 two floating-point registers. If so, populate FIELDS accordingly. */
2632 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2633 riscv_aggregate_field fields
[2])
2635 static int warned
= 0;
2637 /* This is the old ABI, which differs for C++ and C. */
2638 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2639 for (int i
= 0; i
< n_old
; i
++)
2640 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2646 /* This is the new ABI, which is the same for C++ and C. */
2647 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2648 for (int i
= 0; i
< n_new
; i
++)
2649 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2655 if ((n_old
!= n_new
) && (warned
== 0))
2657 warning (0, "ABI for flattened struct with zero-length bit-fields "
2658 "changed in GCC 10");
2662 return n_new
> 0 ? n_new
: 0;
2665 /* See whether TYPE is a record whose fields should be returned in one or
2666 floating-point register and one integer register. If so, populate
2667 FIELDS accordingly. */
2670 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2671 riscv_aggregate_field fields
[2])
2673 static int warned
= 0;
2675 /* This is the old ABI, which differs for C++ and C. */
2676 unsigned num_int_old
= 0, num_float_old
= 0;
2677 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2678 for (int i
= 0; i
< n_old
; i
++)
2680 num_float_old
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2681 num_int_old
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2684 /* This is the new ABI, which is the same for C++ and C. */
2685 unsigned num_int_new
= 0, num_float_new
= 0;
2686 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2687 for (int i
= 0; i
< n_new
; i
++)
2689 num_float_new
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2690 num_int_new
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2693 if (((num_int_old
== 1 && num_float_old
== 1
2694 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
))
2695 || (num_int_new
== 1 && num_float_new
== 1
2696 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
)))
2699 warning (0, "ABI for flattened struct with zero-length bit-fields "
2700 "changed in GCC 10");
2704 return num_int_new
== 1 && num_float_new
== 1;
2707 /* Return the representation of an argument passed or returned in an FPR
2708 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2709 two modes may be different for structures like:
2711 struct __attribute__((packed)) foo { float f; }
2713 where the SFmode value "f" is passed in REGNO but the struct itself
2714 has mode BLKmode. */
2717 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2718 machine_mode value_mode
,
2719 HOST_WIDE_INT offset
)
2721 rtx x
= gen_rtx_REG (value_mode
, regno
);
2723 if (type_mode
!= value_mode
)
2725 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, GEN_INT (offset
));
2726 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2731 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2732 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2733 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2737 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2738 machine_mode mode1
, HOST_WIDE_INT offset1
,
2739 unsigned regno2
, machine_mode mode2
,
2740 HOST_WIDE_INT offset2
)
2742 return gen_rtx_PARALLEL
2745 gen_rtx_EXPR_LIST (VOIDmode
,
2746 gen_rtx_REG (mode1
, regno1
),
2748 gen_rtx_EXPR_LIST (VOIDmode
,
2749 gen_rtx_REG (mode2
, regno2
),
2750 GEN_INT (offset2
))));
2753 /* Fill INFO with information about a single argument, and return an
2754 RTL pattern to pass or return the argument. CUM is the cumulative
2755 state for earlier arguments. MODE is the mode of this argument and
2756 TYPE is its type (if known). NAMED is true if this is a named
2757 (fixed) argument rather than a variable one. RETURN_P is true if
2758 returning the argument, or false if passing the argument. */
2761 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2762 machine_mode mode
, const_tree type
, bool named
,
2765 unsigned num_bytes
, num_words
;
2766 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2767 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2768 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2770 memset (info
, 0, sizeof (*info
));
2771 info
->gpr_offset
= cum
->num_gprs
;
2772 info
->fpr_offset
= cum
->num_fprs
;
2776 riscv_aggregate_field fields
[2];
2777 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2778 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2780 /* Pass one- or two-element floating-point aggregates in FPRs. */
2781 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2782 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2783 switch (info
->num_fprs
)
2786 return riscv_pass_fpr_single (mode
, fregno
,
2787 TYPE_MODE (fields
[0].type
),
2791 return riscv_pass_fpr_pair (mode
, fregno
,
2792 TYPE_MODE (fields
[0].type
),
2795 TYPE_MODE (fields
[1].type
),
2802 /* Pass real and complex floating-point numbers in FPRs. */
2803 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2804 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2805 switch (GET_MODE_CLASS (mode
))
2808 return gen_rtx_REG (mode
, fregno
);
2810 case MODE_COMPLEX_FLOAT
:
2811 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2812 fregno
+ 1, GET_MODE_INNER (mode
),
2813 GET_MODE_UNIT_SIZE (mode
));
2819 /* Pass structs with one float and one integer in an FPR and a GPR. */
2820 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2821 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2822 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2827 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2828 std::swap (fregno
, gregno
);
2830 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2832 gregno
, TYPE_MODE (fields
[1].type
),
2837 /* Work out the size of the argument. */
2838 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2839 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2841 /* Doubleword-aligned varargs start on an even register boundary. */
2842 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2843 info
->gpr_offset
+= info
->gpr_offset
& 1;
2845 /* Partition the argument between registers and stack. */
2847 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2848 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2850 if (info
->num_gprs
|| return_p
)
2851 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2856 /* Implement TARGET_FUNCTION_ARG. */
2859 riscv_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2861 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2862 struct riscv_arg_info info
;
2864 if (arg
.end_marker_p ())
2867 return riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2870 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2873 riscv_function_arg_advance (cumulative_args_t cum_v
,
2874 const function_arg_info
&arg
)
2876 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2877 struct riscv_arg_info info
;
2879 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2881 /* Advance the register count. This has the effect of setting
2882 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2883 argument required us to skip the final GPR and pass the whole
2884 argument on the stack. */
2885 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2886 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2889 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2892 riscv_arg_partial_bytes (cumulative_args_t cum
,
2893 const function_arg_info
&generic_arg
)
2895 struct riscv_arg_info arg
;
2897 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), generic_arg
.mode
,
2898 generic_arg
.type
, generic_arg
.named
, false);
2899 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2902 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2903 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2904 VALTYPE is null and MODE is the mode of the return value. */
2907 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2909 struct riscv_arg_info info
;
2910 CUMULATIVE_ARGS args
;
2914 int unsigned_p
= TYPE_UNSIGNED (type
);
2916 mode
= TYPE_MODE (type
);
2918 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2919 return values, promote the mode here too. */
2920 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2923 memset (&args
, 0, sizeof args
);
2924 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2927 /* Implement TARGET_PASS_BY_REFERENCE. */
2930 riscv_pass_by_reference (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2932 HOST_WIDE_INT size
= arg
.type_size_in_bytes ();
2933 struct riscv_arg_info info
;
2934 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2936 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2937 never pass variadic arguments in floating-point registers, so we can
2938 avoid the call to riscv_get_arg_info in this case. */
2941 /* Don't pass by reference if we can use a floating-point register. */
2942 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2947 /* Pass by reference if the data do not fit in two integer registers. */
2948 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2951 /* Implement TARGET_RETURN_IN_MEMORY. */
2954 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2956 CUMULATIVE_ARGS args
;
2957 cumulative_args_t cum
= pack_cumulative_args (&args
);
2959 /* The rules for returning in memory are the same as for passing the
2960 first named argument by reference. */
2961 memset (&args
, 0, sizeof args
);
2962 function_arg_info
arg (const_cast<tree
> (type
), /*named=*/true);
2963 return riscv_pass_by_reference (cum
, arg
);
2966 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2969 riscv_setup_incoming_varargs (cumulative_args_t cum
,
2970 const function_arg_info
&arg
,
2971 int *pretend_size ATTRIBUTE_UNUSED
, int no_rtl
)
2973 CUMULATIVE_ARGS local_cum
;
2976 /* The caller has advanced CUM up to, but not beyond, the last named
2977 argument. Advance a local copy of CUM past the last "real" named
2978 argument, to find out how many registers are left over. */
2979 local_cum
= *get_cumulative_args (cum
);
2980 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), arg
);
2982 /* Found out how many registers we need to save. */
2983 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2985 if (!no_rtl
&& gp_saved
> 0)
2987 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2988 REG_PARM_STACK_SPACE (cfun
->decl
)
2989 - gp_saved
* UNITS_PER_WORD
);
2990 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2991 set_mem_alias_set (mem
, get_varargs_alias_set ());
2993 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2996 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2997 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
3000 /* Handle an attribute requiring a FUNCTION_DECL;
3001 arguments as in struct attribute_spec.handler. */
3003 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
3004 tree args ATTRIBUTE_UNUSED
,
3005 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
3007 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3009 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3011 *no_add_attrs
= true;
3017 /* Verify type based attributes. NODE is the what the attribute is being
3018 applied to. NAME is the attribute name. ARGS are the attribute args.
3019 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
3020 the attribute should be ignored. */
3023 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
3024 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
3026 /* Check for an argument. */
3027 if (is_attribute_p ("interrupt", name
))
3031 tree cst
= TREE_VALUE (args
);
3034 if (TREE_CODE (cst
) != STRING_CST
)
3036 warning (OPT_Wattributes
,
3037 "%qE attribute requires a string argument",
3039 *no_add_attrs
= true;
3043 string
= TREE_STRING_POINTER (cst
);
3044 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
3045 && strcmp (string
, "machine"))
3047 warning (OPT_Wattributes
,
3048 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
3050 *no_add_attrs
= true;
3058 /* Return true if function TYPE is an interrupt function. */
3060 riscv_interrupt_type_p (tree type
)
3062 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
3065 /* Return true if FUNC is a naked function. */
3067 riscv_naked_function_p (tree func
)
3069 tree func_decl
= func
;
3070 if (func
== NULL_TREE
)
3071 func_decl
= current_function_decl
;
3072 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
3075 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
3077 riscv_allocate_stack_slots_for_args ()
3079 /* Naked functions should not allocate stack slots for arguments. */
3080 return !riscv_naked_function_p (current_function_decl
);
3083 /* Implement TARGET_WARN_FUNC_RETURN. */
3085 riscv_warn_func_return (tree decl
)
3087 /* Naked functions are implemented entirely in assembly, including the
3088 return sequence, so suppress warnings about this. */
3089 return !riscv_naked_function_p (decl
);
3092 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
3095 riscv_va_start (tree valist
, rtx nextarg
)
3097 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
3098 std_expand_builtin_va_start (valist
, nextarg
);
3101 /* Make ADDR suitable for use as a call or sibcall target. */
3104 riscv_legitimize_call_address (rtx addr
)
3106 if (!call_insn_operand (addr
, VOIDmode
))
3108 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
3109 riscv_emit_move (reg
, addr
);
3115 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3116 Assume that the areas do not overlap. */
3119 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3121 HOST_WIDE_INT offset
, delta
;
3122 unsigned HOST_WIDE_INT bits
;
3124 enum machine_mode mode
;
3127 bits
= MAX (BITS_PER_UNIT
,
3128 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
3130 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
3131 delta
= bits
/ BITS_PER_UNIT
;
3133 /* Allocate a buffer for the temporary registers. */
3134 regs
= XALLOCAVEC (rtx
, length
/ delta
);
3136 /* Load as many BITS-sized chunks as possible. Use a normal load if
3137 the source has enough alignment, otherwise use left/right pairs. */
3138 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3140 regs
[i
] = gen_reg_rtx (mode
);
3141 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
3144 /* Copy the chunks to the destination. */
3145 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3146 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
3148 /* Mop up any left-over bytes. */
3149 if (offset
< length
)
3151 src
= adjust_address (src
, BLKmode
, offset
);
3152 dest
= adjust_address (dest
, BLKmode
, offset
);
3153 move_by_pieces (dest
, src
, length
- offset
,
3154 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
3158 /* Helper function for doing a loop-based block operation on memory
3159 reference MEM. Each iteration of the loop will operate on LENGTH
3162 Create a new base register for use within the loop and point it to
3163 the start of MEM. Create a new memory reference that uses this
3164 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3167 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
3168 rtx
*loop_reg
, rtx
*loop_mem
)
3170 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3172 /* Although the new mem does not refer to a known location,
3173 it does keep up to LENGTH bytes of alignment. */
3174 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3175 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3178 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
3179 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
3180 the memory regions do not overlap. */
3183 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
3184 HOST_WIDE_INT bytes_per_iter
)
3186 rtx label
, src_reg
, dest_reg
, final_src
, test
;
3187 HOST_WIDE_INT leftover
;
3189 leftover
= length
% bytes_per_iter
;
3192 /* Create registers and memory references for use within the loop. */
3193 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
3194 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
3196 /* Calculate the value that SRC_REG should have after the last iteration
3198 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3201 /* Emit the start of the loop. */
3202 label
= gen_label_rtx ();
3205 /* Emit the loop body. */
3206 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
3208 /* Move on to the next block. */
3209 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
3210 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
3212 /* Emit the loop condition. */
3213 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
3214 if (Pmode
== DImode
)
3215 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
3217 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
3219 /* Mop up any left-over bytes. */
3221 riscv_block_move_straight (dest
, src
, leftover
);
3223 emit_insn(gen_nop ());
3226 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
3227 memory reference SRC to memory reference DEST. */
3230 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
3232 if (CONST_INT_P (length
))
3234 HOST_WIDE_INT factor
, align
;
3236 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
3237 factor
= BITS_PER_WORD
/ align
;
3239 if (optimize_function_for_size_p (cfun
)
3240 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
3243 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
3245 riscv_block_move_straight (dest
, src
, INTVAL (length
));
3248 else if (optimize
&& align
>= BITS_PER_WORD
)
3250 unsigned min_iter_words
3251 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
3252 unsigned iter_words
= min_iter_words
;
3253 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
3255 /* Lengthen the loop body if it shortens the tail. */
3256 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
3258 unsigned cur_cost
= iter_words
+ words
% iter_words
;
3259 unsigned new_cost
= i
+ words
% i
;
3260 if (new_cost
<= cur_cost
)
3264 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
3271 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3272 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3275 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
3279 switch (riscv_classify_symbolic_expression (op
))
3281 case SYMBOL_ABSOLUTE
:
3282 reloc
= hi_reloc
? "%hi" : "%lo";
3286 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3290 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3294 output_operand_lossage ("invalid use of '%%%c'", hi_reloc
? 'h' : 'R');
3298 fprintf (file
, "%s(", reloc
);
3299 output_addr_const (file
, riscv_strip_unspec_address (op
));
3303 /* Return true if the .AQ suffix should be added to an AMO to implement the
3304 acquire portion of memory model MODEL. */
3307 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3311 case MEMMODEL_ACQ_REL
:
3312 case MEMMODEL_SEQ_CST
:
3313 case MEMMODEL_SYNC_SEQ_CST
:
3314 case MEMMODEL_ACQUIRE
:
3315 case MEMMODEL_CONSUME
:
3316 case MEMMODEL_SYNC_ACQUIRE
:
3319 case MEMMODEL_RELEASE
:
3320 case MEMMODEL_SYNC_RELEASE
:
3321 case MEMMODEL_RELAXED
:
3329 /* Return true if a FENCE should be emitted to before a memory access to
3330 implement the release portion of memory model MODEL. */
3333 riscv_memmodel_needs_release_fence (enum memmodel model
)
3337 case MEMMODEL_ACQ_REL
:
3338 case MEMMODEL_SEQ_CST
:
3339 case MEMMODEL_SYNC_SEQ_CST
:
3340 case MEMMODEL_RELEASE
:
3341 case MEMMODEL_SYNC_RELEASE
:
3344 case MEMMODEL_ACQUIRE
:
3345 case MEMMODEL_CONSUME
:
3346 case MEMMODEL_SYNC_ACQUIRE
:
3347 case MEMMODEL_RELAXED
:
3355 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3357 'h' Print the high-part relocation associated with OP, after stripping
3359 'R' Print the low-part relocation associated with OP.
3360 'C' Print the integer branch condition for comparison OP.
3361 'A' Print the atomic operation suffix for memory model OP.
3362 'F' Print a FENCE if the memory model requires a release.
3363 'z' Print x0 if OP is zero, otherwise print OP normally.
3364 'i' Print i if the operand is not a register. */
3367 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3369 machine_mode mode
= GET_MODE (op
);
3370 enum rtx_code code
= GET_CODE (op
);
3377 riscv_print_operand_reloc (file
, op
, true);
3381 riscv_print_operand_reloc (file
, op
, false);
3385 /* The RTL names match the instruction names. */
3386 fputs (GET_RTX_NAME (code
), file
);
3390 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3391 fputs (".aq", file
);
3395 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3396 fputs ("fence iorw,ow; ", file
);
3408 if (letter
&& letter
!= 'z')
3409 output_operand_lossage ("invalid use of '%%%c'", letter
);
3410 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3414 if (letter
&& letter
!= 'z')
3415 output_operand_lossage ("invalid use of '%%%c'", letter
);
3417 output_address (mode
, XEXP (op
, 0));
3421 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3422 fputs (reg_names
[GP_REG_FIRST
], file
);
3423 else if (letter
&& letter
!= 'z')
3424 output_operand_lossage ("invalid use of '%%%c'", letter
);
3426 output_addr_const (file
, riscv_strip_unspec_address (op
));
3432 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3435 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3437 struct riscv_address_info addr
;
3439 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3443 riscv_print_operand (file
, addr
.offset
, 0);
3444 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3447 case ADDRESS_LO_SUM
:
3448 riscv_print_operand_reloc (file
, addr
.offset
, false);
3449 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3452 case ADDRESS_CONST_INT
:
3453 output_addr_const (file
, x
);
3454 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3457 case ADDRESS_SYMBOLIC
:
3458 output_addr_const (file
, riscv_strip_unspec_address (x
));
3465 riscv_size_ok_for_small_data_p (int size
)
3467 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3470 /* Return true if EXP should be placed in the small data section. */
3473 riscv_in_small_data_p (const_tree x
)
3475 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3478 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3480 const char *sec
= DECL_SECTION_NAME (x
);
3481 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3484 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3487 /* Switch to the appropriate section for output of DECL. */
3490 riscv_select_section (tree decl
, int reloc
,
3491 unsigned HOST_WIDE_INT align
)
3493 switch (categorize_decl_for_section (decl
, reloc
))
3495 case SECCAT_SRODATA
:
3496 return get_named_section (decl
, ".srodata", reloc
);
3499 return default_elf_select_section (decl
, reloc
, align
);
3503 /* Switch to the appropriate section for output of DECL. */
3506 riscv_unique_section (tree decl
, int reloc
)
3508 const char *prefix
= NULL
;
3509 bool one_only
= DECL_ONE_ONLY (decl
) && !HAVE_COMDAT_GROUP
;
3511 switch (categorize_decl_for_section (decl
, reloc
))
3513 case SECCAT_SRODATA
:
3514 prefix
= one_only
? ".sr" : ".srodata";
3522 const char *name
, *linkonce
;
3525 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3526 name
= targetm
.strip_name_encoding (name
);
3528 /* If we're using one_only, then there needs to be a .gnu.linkonce
3529 prefix to the section name. */
3530 linkonce
= one_only
? ".gnu.linkonce" : "";
3532 string
= ACONCAT ((linkonce
, prefix
, ".", name
, NULL
));
3534 set_decl_section_name (decl
, string
);
3537 default_unique_section (decl
, reloc
);
3540 /* Return a section for X, handling small data. */
3543 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3544 unsigned HOST_WIDE_INT align
)
3546 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3548 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3550 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3552 /* Rename .rodata.cst* to .srodata.cst*. */
3553 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3554 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3555 return get_section (name
, s
->named
.common
.flags
, NULL
);
3558 if (s
== data_section
)
3559 return sdata_section
;
3565 /* Make the last instruction frame-related and note that it performs
3566 the operation described by FRAME_PATTERN. */
3569 riscv_set_frame_expr (rtx frame_pattern
)
3573 insn
= get_last_insn ();
3574 RTX_FRAME_RELATED_P (insn
) = 1;
3575 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3580 /* Return a frame-related rtx that stores REG at MEM.
3581 REG must be a single register. */
3584 riscv_frame_set (rtx mem
, rtx reg
)
3586 rtx set
= gen_rtx_SET (mem
, reg
);
3587 RTX_FRAME_RELATED_P (set
) = 1;
3591 /* Return true if the current function must save register REGNO. */
3594 riscv_save_reg_p (unsigned int regno
)
3596 bool call_saved
= !global_regs
[regno
] && !call_used_or_fixed_reg_p (regno
);
3597 bool might_clobber
= crtl
->saves_all_registers
3598 || df_regs_ever_live_p (regno
);
3600 if (call_saved
&& might_clobber
)
3603 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3606 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3609 /* If this is an interrupt handler, then must save extra registers. */
3610 if (cfun
->machine
->interrupt_handler_p
)
3612 /* zero register is always zero. */
3613 if (regno
== GP_REG_FIRST
)
3616 /* The function will return the stack pointer to its original value. */
3617 if (regno
== STACK_POINTER_REGNUM
)
3620 /* By convention, we assume that gp and tp are safe. */
3621 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3624 /* We must save every register used in this function. If this is not a
3625 leaf function, then we must save all temporary registers. */
3626 if (df_regs_ever_live_p (regno
)
3627 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
3634 /* Determine whether to call GPR save/restore routines. */
3636 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3638 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3639 || cfun
->machine
->interrupt_handler_p
)
3642 return frame
->save_libcall_adjustment
!= 0;
3645 /* Determine which GPR save/restore routine to call. */
3648 riscv_save_libcall_count (unsigned mask
)
3650 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3651 if (BITSET_P (mask
, n
))
3652 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3656 /* Populate the current function's riscv_frame_info structure.
3658 RISC-V stack frames grown downward. High addresses are at the top.
3660 +-------------------------------+
3662 | incoming stack arguments |
3664 +-------------------------------+ <-- incoming stack pointer
3666 | callee-allocated save area |
3667 | for arguments that are |
3668 | split between registers and |
3671 +-------------------------------+ <-- arg_pointer_rtx
3673 | callee-allocated save area |
3674 | for register varargs |
3676 +-------------------------------+ <-- hard_frame_pointer_rtx;
3677 | | stack_pointer_rtx + gp_sp_offset
3678 | GPR save area | + UNITS_PER_WORD
3680 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3681 | | + UNITS_PER_HWVALUE
3684 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3688 P +-------------------------------+
3690 | outgoing stack arguments |
3692 +-------------------------------+ <-- stack_pointer_rtx
3694 Dynamic stack allocations such as alloca insert data at point P.
3695 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3696 hard_frame_pointer_rtx unchanged. */
3698 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3701 riscv_compute_frame_info (void)
3703 struct riscv_frame_info
*frame
;
3704 HOST_WIDE_INT offset
;
3705 bool interrupt_save_t1
= false;
3706 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3708 frame
= &cfun
->machine
->frame
;
3710 /* In an interrupt function, if we have a large frame, then we need to
3711 save/restore t1. We check for this before clearing the frame struct. */
3712 if (cfun
->machine
->interrupt_handler_p
)
3714 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3715 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3716 interrupt_save_t1
= true;
3719 memset (frame
, 0, sizeof (*frame
));
3721 if (!cfun
->machine
->naked_p
)
3723 /* Find out which GPRs we need to save. */
3724 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3725 if (riscv_save_reg_p (regno
)
3726 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3727 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3729 /* If this function calls eh_return, we must also save and restore the
3730 EH data registers. */
3731 if (crtl
->calls_eh_return
)
3732 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3733 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3735 /* Find out which FPRs we need to save. This loop must iterate over
3736 the same space as its companion in riscv_for_each_saved_reg. */
3737 if (TARGET_HARD_FLOAT
)
3738 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3739 if (riscv_save_reg_p (regno
))
3740 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3743 /* At the bottom of the frame are any outgoing stack arguments. */
3744 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3745 /* Next are local stack variables. */
3746 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3747 /* The virtual frame pointer points above the local variables. */
3748 frame
->frame_pointer_offset
= offset
;
3749 /* Next are the callee-saved FPRs. */
3751 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3752 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3753 /* Next are the callee-saved GPRs. */
3756 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3757 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3759 /* Only use save/restore routines if they don't alter the stack size. */
3760 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3762 /* Libcall saves/restores 3 registers at once, so we need to
3763 allocate 12 bytes for callee-saved register. */
3765 x_save_size
= 3 * UNITS_PER_WORD
;
3767 frame
->save_libcall_adjustment
= x_save_size
;
3770 offset
+= x_save_size
;
3772 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3773 /* The hard frame pointer points above the callee-saved GPRs. */
3774 frame
->hard_frame_pointer_offset
= offset
;
3775 /* Above the hard frame pointer is the callee-allocated varags save area. */
3776 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3777 /* Next is the callee-allocated area for pretend stack arguments. */
3778 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3779 /* Arg pointer must be below pretend args, but must be above alignment
3781 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3782 frame
->total_size
= offset
;
3783 /* Next points the incoming stack pointer and any incoming arguments. */
3785 /* Only use save/restore routines when the GPRs are atop the frame. */
3786 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3787 frame
->save_libcall_adjustment
= 0;
3790 /* Make sure that we're not trying to eliminate to the wrong hard frame
3794 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3796 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3799 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3800 or argument pointer. TO is either the stack pointer or hard frame
3804 riscv_initial_elimination_offset (int from
, int to
)
3806 HOST_WIDE_INT src
, dest
;
3808 riscv_compute_frame_info ();
3810 if (to
== HARD_FRAME_POINTER_REGNUM
)
3811 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3812 else if (to
== STACK_POINTER_REGNUM
)
3813 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3817 if (from
== FRAME_POINTER_REGNUM
)
3818 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3819 else if (from
== ARG_POINTER_REGNUM
)
3820 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3827 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3831 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3836 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3839 /* Emit code to change the current function's return address to
3840 ADDRESS. SCRATCH is available as a scratch register, if needed.
3841 ADDRESS and SCRATCH are both word-mode GPRs. */
3844 riscv_set_return_address (rtx address
, rtx scratch
)
3848 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3849 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3850 cfun
->machine
->frame
.gp_sp_offset
);
3851 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3854 /* A function to save or store a register. The first argument is the
3855 register and the second is the stack slot. */
3856 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3858 /* Use FN to save or restore register REGNO. MODE is the register's
3859 mode and OFFSET is the offset of its save slot from the current
3863 riscv_save_restore_reg (machine_mode mode
, int regno
,
3864 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3868 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3869 fn (gen_rtx_REG (mode
, regno
), mem
);
3872 /* Call FN for each register that is saved by the current function.
3873 SP_OFFSET is the offset of the current stack pointer from the start
3877 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
3878 bool epilogue
, bool maybe_eh_return
)
3880 HOST_WIDE_INT offset
;
3882 /* Save the link register and s-registers. */
3883 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3884 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3885 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3887 bool handle_reg
= TRUE
;
3889 /* If this is a normal return in a function that calls the eh_return
3890 builtin, then do not restore the eh return data registers as that
3891 would clobber the return value. But we do still need to save them
3892 in the prologue, and restore them for an exception return, so we
3893 need special handling here. */
3894 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
3896 unsigned int i
, regnum
;
3898 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
3900 if (regno
== regnum
)
3908 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3909 offset
-= UNITS_PER_WORD
;
3912 /* This loop must iterate over the same space as its companion in
3913 riscv_compute_frame_info. */
3914 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3915 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3916 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3918 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3920 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3921 offset
-= GET_MODE_SIZE (mode
);
3925 /* Save register REG to MEM. Make the instruction frame-related. */
3928 riscv_save_reg (rtx reg
, rtx mem
)
3930 riscv_emit_move (mem
, reg
);
3931 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3934 /* Restore register REG from MEM. */
3937 riscv_restore_reg (rtx reg
, rtx mem
)
3939 rtx insn
= riscv_emit_move (reg
, mem
);
3940 rtx dwarf
= NULL_RTX
;
3941 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3943 if (epilogue_cfa_sp_offset
&& REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
3945 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3946 GEN_INT (epilogue_cfa_sp_offset
));
3947 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3950 REG_NOTES (insn
) = dwarf
;
3951 RTX_FRAME_RELATED_P (insn
) = 1;
3954 /* For stack frames that can't be allocated with a single ADDI instruction,
3955 compute the best value to initially allocate. It must at a minimum
3956 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3957 try to pick a value that will allow compression of the register saves
3958 without adding extra instructions. */
3960 static HOST_WIDE_INT
3961 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3963 if (SMALL_OPERAND (frame
->total_size
))
3964 return frame
->total_size
;
3966 HOST_WIDE_INT min_first_step
=
3967 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3968 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3969 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3970 gcc_assert (min_first_step
<= max_first_step
);
3972 /* As an optimization, use the least-significant bits of the total frame
3973 size, so that the second adjustment step is just LUI + ADD. */
3974 if (!SMALL_OPERAND (min_second_step
)
3975 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3976 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3977 return frame
->total_size
% IMM_REACH
;
3981 /* If we need two subtracts, and one is small enough to allow compressed
3982 loads and stores, then put that one first. */
3983 if (IN_RANGE (min_second_step
, 0,
3984 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3985 return MAX (min_second_step
, min_first_step
);
3987 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3988 with the minimum first step, so that we can get compressed loads and
3990 else if (!SMALL_OPERAND (min_second_step
))
3991 return min_first_step
;
3994 return max_first_step
;
3998 riscv_adjust_libcall_cfi_prologue ()
4000 rtx dwarf
= NULL_RTX
;
4001 rtx adjust_sp_rtx
, reg
, mem
, insn
;
4002 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
4005 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4006 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4008 /* The save order is ra, s0, s1, s2 to s11. */
4009 if (regno
== RETURN_ADDR_REGNUM
)
4010 offset
= saved_size
- UNITS_PER_WORD
;
4011 else if (regno
== S0_REGNUM
)
4012 offset
= saved_size
- UNITS_PER_WORD
* 2;
4013 else if (regno
== S1_REGNUM
)
4014 offset
= saved_size
- UNITS_PER_WORD
* 3;
4016 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
4018 reg
= gen_rtx_REG (SImode
, regno
);
4019 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
4023 insn
= gen_rtx_SET (mem
, reg
);
4024 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
4027 /* Debug info for adjust sp. */
4028 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
4029 stack_pointer_rtx
, GEN_INT (-saved_size
));
4030 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4036 riscv_emit_stack_tie (void)
4038 if (Pmode
== SImode
)
4039 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4041 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4044 /* Expand the "prologue" pattern. */
4047 riscv_expand_prologue (void)
4049 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4050 HOST_WIDE_INT size
= frame
->total_size
;
4051 unsigned mask
= frame
->mask
;
4054 if (flag_stack_usage_info
)
4055 current_function_static_stack_size
= size
;
4057 if (cfun
->machine
->naked_p
)
4060 /* When optimizing for size, call a subroutine to save the registers. */
4061 if (riscv_use_save_libcall (frame
))
4063 rtx dwarf
= NULL_RTX
;
4064 dwarf
= riscv_adjust_libcall_cfi_prologue ();
4066 size
-= frame
->save_libcall_adjustment
;
4067 insn
= emit_insn (riscv_gen_gpr_save_insn (frame
));
4068 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4070 RTX_FRAME_RELATED_P (insn
) = 1;
4071 REG_NOTES (insn
) = dwarf
;
4074 /* Save the registers. */
4075 if ((frame
->mask
| frame
->fmask
) != 0)
4077 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
4079 insn
= gen_add3_insn (stack_pointer_rtx
,
4082 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4084 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
4087 frame
->mask
= mask
; /* Undo the above fib. */
4089 /* Set up the frame pointer, if we're using one. */
4090 if (frame_pointer_needed
)
4092 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
4093 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
4094 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4096 riscv_emit_stack_tie ();
4099 /* Allocate the rest of the frame. */
4102 if (SMALL_OPERAND (-size
))
4104 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4106 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4110 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
4111 emit_insn (gen_add3_insn (stack_pointer_rtx
,
4113 RISCV_PROLOGUE_TEMP (Pmode
)));
4115 /* Describe the effect of the previous instructions. */
4116 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
4117 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
4118 riscv_set_frame_expr (insn
);
4124 riscv_adjust_libcall_cfi_epilogue ()
4126 rtx dwarf
= NULL_RTX
;
4127 rtx adjust_sp_rtx
, reg
;
4128 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
4130 /* Debug info for adjust sp. */
4131 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
4132 stack_pointer_rtx
, GEN_INT (saved_size
));
4133 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4136 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4137 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4139 reg
= gen_rtx_REG (SImode
, regno
);
4140 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
4146 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
4147 style says which. */
4150 riscv_expand_epilogue (int style
)
4152 /* Split the frame into two. STEP1 is the amount of stack we should
4153 deallocate before restoring the registers. STEP2 is the amount we
4154 should deallocate afterwards.
4156 Start off by assuming that no registers need to be restored. */
4157 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4158 unsigned mask
= frame
->mask
;
4159 HOST_WIDE_INT step1
= frame
->total_size
;
4160 HOST_WIDE_INT step2
= 0;
4161 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
4162 && riscv_use_save_libcall (frame
));
4163 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4166 /* We need to add memory barrier to prevent read from deallocated stack. */
4167 bool need_barrier_p
= (get_frame_size ()
4168 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
4170 if (cfun
->machine
->naked_p
)
4172 gcc_assert (style
== NORMAL_RETURN
);
4174 emit_jump_insn (gen_return ());
4179 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
4181 emit_jump_insn (gen_return ());
4185 /* Reset the epilogue cfa info before starting to emit the epilogue. */
4186 epilogue_cfa_sp_offset
= 0;
4188 /* Move past any dynamic stack allocations. */
4189 if (cfun
->calls_alloca
)
4191 /* Emit a barrier to prevent loads from a deallocated stack. */
4192 riscv_emit_stack_tie ();
4193 need_barrier_p
= false;
4195 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
4196 if (!SMALL_OPERAND (INTVAL (adjust
)))
4198 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4199 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4203 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
4206 rtx dwarf
= NULL_RTX
;
4207 rtx cfa_adjust_value
= gen_rtx_PLUS (
4208 Pmode
, hard_frame_pointer_rtx
,
4209 GEN_INT (-frame
->hard_frame_pointer_offset
));
4210 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
4211 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
4212 RTX_FRAME_RELATED_P (insn
) = 1;
4214 REG_NOTES (insn
) = dwarf
;
4217 /* If we need to restore registers, deallocate as much stack as
4218 possible in the second step without going out of range. */
4219 if ((frame
->mask
| frame
->fmask
) != 0)
4221 step2
= riscv_first_stack_step (frame
);
4225 /* Set TARGET to BASE + STEP1. */
4228 /* Emit a barrier to prevent loads from a deallocated stack. */
4229 riscv_emit_stack_tie ();
4230 need_barrier_p
= false;
4232 /* Get an rtx for STEP1 that we can add to BASE. */
4233 rtx adjust
= GEN_INT (step1
);
4234 if (!SMALL_OPERAND (step1
))
4236 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4237 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4241 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
4243 rtx dwarf
= NULL_RTX
;
4244 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4247 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4248 RTX_FRAME_RELATED_P (insn
) = 1;
4250 REG_NOTES (insn
) = dwarf
;
4252 else if (frame_pointer_needed
)
4254 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4256 epilogue_cfa_sp_offset
= step2
;
4259 if (use_restore_libcall
)
4260 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4262 /* Restore the registers. */
4263 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
4264 true, style
== EXCEPTION_RETURN
);
4266 if (use_restore_libcall
)
4268 frame
->mask
= mask
; /* Undo the above fib. */
4269 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
4270 step2
-= frame
->save_libcall_adjustment
;
4274 riscv_emit_stack_tie ();
4276 /* Deallocate the final bit of the frame. */
4279 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4282 rtx dwarf
= NULL_RTX
;
4283 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4285 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4286 RTX_FRAME_RELATED_P (insn
) = 1;
4288 REG_NOTES (insn
) = dwarf
;
4291 if (use_restore_libcall
)
4293 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
4294 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
4295 RTX_FRAME_RELATED_P (insn
) = 1;
4296 REG_NOTES (insn
) = dwarf
;
4298 emit_jump_insn (gen_gpr_restore_return (ra
));
4302 /* Add in the __builtin_eh_return stack adjustment. */
4303 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
4304 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4305 EH_RETURN_STACKADJ_RTX
));
4307 /* Return from interrupt. */
4308 if (cfun
->machine
->interrupt_handler_p
)
4310 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
4312 gcc_assert (mode
!= UNKNOWN_MODE
);
4314 if (mode
== MACHINE_MODE
)
4315 emit_jump_insn (gen_riscv_mret ());
4316 else if (mode
== SUPERVISOR_MODE
)
4317 emit_jump_insn (gen_riscv_sret ());
4319 emit_jump_insn (gen_riscv_uret ());
4321 else if (style
!= SIBCALL_RETURN
)
4322 emit_jump_insn (gen_simple_return_internal (ra
));
4325 /* Implement EPILOGUE_USES. */
4328 riscv_epilogue_uses (unsigned int regno
)
4330 if (regno
== RETURN_ADDR_REGNUM
)
4333 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4335 /* An interrupt function restores temp regs, so we must indicate that
4336 they are live at function end. */
4337 if (df_regs_ever_live_p (regno
)
4338 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
4345 /* Return nonzero if this function is known to have a null epilogue.
4346 This allows the optimizer to omit jumps to jumps if no stack
4350 riscv_can_use_return_insn (void)
4352 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4353 && ! cfun
->machine
->interrupt_handler_p
);
4356 /* Given that there exists at least one variable that is set (produced)
4357 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4358 IN_INSN represents one or more memory store operations and none of
4359 the variables set by OUT_INSN is used by IN_INSN as the address of a
4360 store operation. If either IN_INSN or OUT_INSN does not represent
4361 a "single" RTL SET expression (as loosely defined by the
4362 implementation of the single_set function) or a PARALLEL with only
4363 SETs, CLOBBERs, and USEs inside, this function returns false.
4365 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4366 conditions that result in assertion failures in the generic
4367 store_data_bypass_p function and returns FALSE in such cases.
4369 This is required to make -msave-restore work with the sifive-7
4370 pipeline description. */
4373 riscv_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
4375 rtx out_set
, in_set
;
4376 rtx out_pat
, in_pat
;
4377 rtx out_exp
, in_exp
;
4380 in_set
= single_set (in_insn
);
4383 if (MEM_P (SET_DEST (in_set
)))
4385 out_set
= single_set (out_insn
);
4388 out_pat
= PATTERN (out_insn
);
4389 if (GET_CODE (out_pat
) == PARALLEL
)
4391 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
4393 out_exp
= XVECEXP (out_pat
, 0, i
);
4394 if ((GET_CODE (out_exp
) == CLOBBER
)
4395 || (GET_CODE (out_exp
) == USE
))
4397 else if (GET_CODE (out_exp
) != SET
)
4406 in_pat
= PATTERN (in_insn
);
4407 if (GET_CODE (in_pat
) != PARALLEL
)
4410 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
4412 in_exp
= XVECEXP (in_pat
, 0, i
);
4413 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
4415 else if (GET_CODE (in_exp
) != SET
)
4418 if (MEM_P (SET_DEST (in_exp
)))
4420 out_set
= single_set (out_insn
);
4423 out_pat
= PATTERN (out_insn
);
4424 if (GET_CODE (out_pat
) != PARALLEL
)
4426 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
4428 out_exp
= XVECEXP (out_pat
, 0, j
);
4429 if ((GET_CODE (out_exp
) == CLOBBER
)
4430 || (GET_CODE (out_exp
) == USE
))
4432 else if (GET_CODE (out_exp
) != SET
)
4440 return store_data_bypass_p (out_insn
, in_insn
);
4443 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4445 When floating-point registers are wider than integer ones, moves between
4446 them must go through memory. */
4449 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4452 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4453 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4456 /* Implement TARGET_REGISTER_MOVE_COST. */
4459 riscv_register_move_cost (machine_mode mode
,
4460 reg_class_t from
, reg_class_t to
)
4462 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4465 /* Implement TARGET_HARD_REGNO_NREGS. */
4468 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4470 if (FP_REG_P (regno
))
4471 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4473 /* All other registers are word-sized. */
4474 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4477 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4480 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4482 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4484 if (GP_REG_P (regno
))
4486 if (!GP_REG_P (regno
+ nregs
- 1))
4489 else if (FP_REG_P (regno
))
4491 if (!FP_REG_P (regno
+ nregs
- 1))
4494 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4495 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4498 /* Only use callee-saved registers if a potential callee is guaranteed
4499 to spill the requisite width. */
4500 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4501 || (!call_used_or_fixed_reg_p (regno
)
4502 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4508 /* Require same callee-savedness for all registers. */
4509 for (unsigned i
= 1; i
< nregs
; i
++)
4510 if (call_used_or_fixed_reg_p (regno
)
4511 != call_used_or_fixed_reg_p (regno
+ i
))
4517 /* Implement TARGET_MODES_TIEABLE_P.
4519 Don't allow floating-point modes to be tied, since type punning of
4520 single-precision and double-precision is implementation defined. */
4523 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4525 return (mode1
== mode2
4526 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4527 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4530 /* Implement CLASS_MAX_NREGS. */
4532 static unsigned char
4533 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4535 if (reg_class_subset_p (FP_REGS
, rclass
))
4536 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4538 if (reg_class_subset_p (GR_REGS
, rclass
))
4539 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4544 /* Implement TARGET_MEMORY_MOVE_COST. */
4547 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4549 return (tune_info
->memory_cost
4550 + memory_move_secondary_cost (mode
, rclass
, in
));
4553 /* Return the number of instructions that can be issued per cycle. */
4556 riscv_issue_rate (void)
4558 return tune_info
->issue_rate
;
4561 /* Auxiliary function to emit RISC-V ELF attribute. */
4563 riscv_emit_attribute ()
4565 fprintf (asm_out_file
, "\t.attribute arch, \"%s\"\n",
4566 riscv_arch_str ().c_str ());
4568 fprintf (asm_out_file
, "\t.attribute unaligned_access, %d\n",
4569 TARGET_STRICT_ALIGN
? 0 : 1);
4571 fprintf (asm_out_file
, "\t.attribute stack_align, %d\n",
4572 riscv_stack_boundary
/ 8);
4575 /* Implement TARGET_ASM_FILE_START. */
4578 riscv_file_start (void)
4580 default_file_start ();
4582 /* Instruct GAS to generate position-[in]dependent code. */
4583 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4585 /* If the user specifies "-mno-relax" on the command line then disable linker
4586 relaxation in the assembler. */
4588 fprintf (asm_out_file
, "\t.option norelax\n");
4590 if (riscv_emit_attribute_p
)
4591 riscv_emit_attribute ();
4594 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4595 in order to avoid duplicating too much logic from elsewhere. */
4598 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4599 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4602 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
4603 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4606 /* Pretend to be a post-reload pass while generating rtl. */
4607 reload_completed
= 1;
4609 /* Mark the end of the (empty) prologue. */
4610 emit_note (NOTE_INSN_PROLOGUE_END
);
4612 /* Determine if we can use a sibcall to call FUNCTION directly. */
4613 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4615 /* We need two temporary registers in some cases. */
4616 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4617 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4619 /* Find out which register contains the "this" pointer. */
4620 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4621 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4623 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4625 /* Add DELTA to THIS_RTX. */
4628 rtx offset
= GEN_INT (delta
);
4629 if (!SMALL_OPERAND (delta
))
4631 riscv_emit_move (temp1
, offset
);
4634 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4637 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4638 if (vcall_offset
!= 0)
4642 /* Set TEMP1 to *THIS_RTX. */
4643 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4645 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4646 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4648 /* Load the offset and add it to THIS_RTX. */
4649 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4650 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4653 /* Jump to the target function. */
4654 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4655 SIBLING_CALL_P (insn
) = 1;
4657 /* Run just enough of rest_of_compilation. This sequence was
4658 "borrowed" from alpha.c. */
4659 insn
= get_insns ();
4660 split_all_insns_noflow ();
4661 shorten_branches (insn
);
4662 assemble_start_function (thunk_fndecl
, fnname
);
4663 final_start_function (insn
, file
, 1);
4664 final (insn
, file
, 1);
4665 final_end_function ();
4666 assemble_end_function (thunk_fndecl
, fnname
);
4668 /* Clean up the vars set above. Note that final_end_function resets
4669 the global pointer for us. */
4670 reload_completed
= 0;
4673 /* Allocate a chunk of memory for per-function machine-dependent data. */
4675 static struct machine_function
*
4676 riscv_init_machine_status (void)
4678 return ggc_cleared_alloc
<machine_function
> ();
4681 /* Implement TARGET_OPTION_OVERRIDE. */
4684 riscv_option_override (void)
4686 const struct riscv_cpu_info
*cpu
;
4688 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4689 SUBTARGET_OVERRIDE_OPTIONS
;
4692 flag_pcc_struct_return
= 0;
4697 /* The presence of the M extension implies that division instructions
4698 are present, so include them unless explicitly disabled. */
4699 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4700 target_flags
|= MASK_DIV
;
4701 else if (!TARGET_MUL
&& TARGET_DIV
)
4702 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4704 /* Likewise floating-point division and square root. */
4705 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4706 target_flags
|= MASK_FDIV
;
4708 /* Handle -mtune. */
4709 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4710 RISCV_TUNE_STRING_DEFAULT
);
4711 riscv_microarchitecture
= cpu
->microarchitecture
;
4712 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4714 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4715 for size. For architectures that trap and emulate unaligned accesses,
4716 the performance cost is too great, even for -Os. Similarly, if
4717 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4718 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4719 || TARGET_STRICT_ALIGN
);
4720 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4721 && cpu
->tune_info
->slow_unaligned_access
)
4722 target_flags
|= MASK_STRICT_ALIGN
;
4724 /* If the user hasn't specified a branch cost, use the processor's
4726 if (riscv_branch_cost
== 0)
4727 riscv_branch_cost
= tune_info
->branch_cost
;
4729 /* Function to allocate machine-dependent function status. */
4730 init_machine_status
= &riscv_init_machine_status
;
4733 riscv_cmodel
= CM_PIC
;
4735 /* We get better code with explicit relocs for CM_MEDLOW, but
4736 worse code for the others (for now). Pick the best default. */
4737 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4738 if (riscv_cmodel
== CM_MEDLOW
)
4739 target_flags
|= MASK_EXPLICIT_RELOCS
;
4741 /* Require that the ISA supports the requested floating-point ABI. */
4742 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4743 error ("requested ABI requires %<-march%> to subsume the %qc extension",
4744 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4746 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4747 error ("rv32e requires ilp32e ABI");
4749 /* We do not yet support ILP32 on RV64. */
4750 if (BITS_PER_WORD
!= POINTER_SIZE
)
4751 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE
);
4753 /* Validate -mpreferred-stack-boundary= value. */
4754 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4755 if (riscv_preferred_stack_boundary_arg
)
4757 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4760 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4761 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
4762 riscv_preferred_stack_boundary_arg
, min
, max
);
4764 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4767 if (riscv_emit_attribute_p
< 0)
4768 #ifdef HAVE_AS_RISCV_ATTRIBUTE
4769 riscv_emit_attribute_p
= TARGET_RISCV_ATTRIBUTE
;
4771 riscv_emit_attribute_p
= 0;
4773 if (riscv_emit_attribute_p
)
4774 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
4775 " [%<-mriscv-attribute%>]");
4780 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4783 riscv_conditional_register_usage (void)
4785 /* We have only x0~x15 on RV32E. */
4788 for (int r
= 16; r
<= 31; r
++)
4792 if (riscv_abi
== ABI_ILP32E
)
4794 for (int r
= 16; r
<= 31; r
++)
4795 call_used_regs
[r
] = 1;
4798 if (!TARGET_HARD_FLOAT
)
4800 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4801 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4804 /* In the soft-float ABI, there are no callee-saved FP registers. */
4805 if (UNITS_PER_FP_ARG
== 0)
4807 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4808 call_used_regs
[regno
] = 1;
4812 /* Return a register priority for hard reg REGNO. */
4815 riscv_register_priority (int regno
)
4817 /* Favor compressed registers to improve the odds of RVC instruction
4819 if (riscv_compressed_reg_p (regno
))
4825 /* Implement TARGET_TRAMPOLINE_INIT. */
4828 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4830 rtx addr
, end_addr
, mem
;
4831 uint32_t trampoline
[4];
4833 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4835 /* Work out the offsets of the pointers from the start of the
4837 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4839 /* Get pointers to the beginning and end of the code block. */
4840 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4841 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4842 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4845 if (Pmode
== SImode
)
4847 chain_value
= force_reg (Pmode
, chain_value
);
4849 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4850 /* lui t2, hi(chain)
4852 addi t2, t2, lo(chain)
4855 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4856 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4858 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4861 rtx imm12_mask
= gen_reg_rtx (SImode
);
4862 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4864 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4866 /* Gen lui t2, hi(chain). */
4867 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4869 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4871 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4872 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4873 gen_int_mode (lui_hi_chain_code
, SImode
));
4875 mem
= adjust_address (m_tramp
, SImode
, 0);
4876 riscv_emit_move (mem
, lui_hi_chain
);
4878 /* Gen lui t1, hi(func). */
4879 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4881 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4883 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4884 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4885 gen_int_mode (lui_hi_func_code
, SImode
));
4887 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4888 riscv_emit_move (mem
, lui_hi_func
);
4890 /* Gen addi t2, t2, lo(chain). */
4891 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4893 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4895 lo_chain_code
= OPCODE_ADDI
4896 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4897 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4899 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4900 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4902 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4903 riscv_emit_move (mem
, addi_lo_chain
);
4905 /* Gen jr r1, lo(func). */
4906 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4908 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4910 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4912 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4913 force_reg (SImode
, GEN_INT (lo_func_code
)));
4915 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4916 riscv_emit_move (mem
, jr_lo_func
);
4920 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4921 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4924 l[wd] t1, target_function_offset(t2)
4925 l[wd] t2, static_chain_offset(t2)
4928 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4929 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4930 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4931 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4932 | (target_function_offset
<< SHIFT_IMM
);
4933 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4934 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4935 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4936 | (static_chain_offset
<< SHIFT_IMM
);
4937 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4939 /* Copy the trampoline code. */
4940 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4942 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4943 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4946 /* Set up the static chain pointer field. */
4947 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4948 riscv_emit_move (mem
, chain_value
);
4950 /* Set up the target function field. */
4951 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4952 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4955 /* Flush the code part of the trampoline. */
4956 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4957 emit_insn (gen_clear_cache (addr
, end_addr
));
4960 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4963 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4964 tree exp ATTRIBUTE_UNUSED
)
4966 /* Don't use sibcalls when use save-restore routine. */
4967 if (TARGET_SAVE_RESTORE
)
4970 /* Don't use sibcall for naked functions. */
4971 if (cfun
->machine
->naked_p
)
4974 /* Don't use sibcall for interrupt functions. */
4975 if (cfun
->machine
->interrupt_handler_p
)
4981 /* Get the interrupt type, return UNKNOWN_MODE if it's not
4982 interrupt function. */
4983 static enum riscv_privilege_levels
4984 riscv_get_interrupt_type (tree decl
)
4986 gcc_assert (decl
!= NULL_TREE
);
4988 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
4989 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
4990 return UNKNOWN_MODE
;
4993 = TREE_VALUE (lookup_attribute ("interrupt",
4994 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
4996 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
4998 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
5000 if (!strcmp (string
, "user"))
5002 else if (!strcmp (string
, "supervisor"))
5003 return SUPERVISOR_MODE
;
5004 else /* Must be "machine". */
5005 return MACHINE_MODE
;
5008 /* Interrupt attributes are machine mode by default. */
5009 return MACHINE_MODE
;
5012 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
5013 /* Sanity cheching for above function attributes. */
5015 riscv_set_current_function (tree decl
)
5017 if (decl
== NULL_TREE
5018 || current_function_decl
== NULL_TREE
5019 || current_function_decl
== error_mark_node
5021 || cfun
->machine
->attributes_checked_p
)
5024 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
5025 cfun
->machine
->interrupt_handler_p
5026 = riscv_interrupt_type_p (TREE_TYPE (decl
));
5028 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
5029 error ("function attributes %qs and %qs are mutually exclusive",
5030 "interrupt", "naked");
5032 if (cfun
->machine
->interrupt_handler_p
)
5034 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
5035 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
5037 if (TREE_CODE (ret
) != VOID_TYPE
)
5038 error ("%qs function cannot return a value", "interrupt");
5040 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
5041 error ("%qs function cannot have arguments", "interrupt");
5043 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
5045 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
5048 /* Don't print the above diagnostics more than once. */
5049 cfun
->machine
->attributes_checked_p
= 1;
5052 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
5054 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
5056 tree combined_attrs
;
5058 enum riscv_privilege_levels old_interrupt_type
5059 = riscv_get_interrupt_type (olddecl
);
5060 enum riscv_privilege_levels new_interrupt_type
5061 = riscv_get_interrupt_type (newdecl
);
5063 /* Check old and new has same interrupt type. */
5064 if ((old_interrupt_type
!= UNKNOWN_MODE
)
5065 && (new_interrupt_type
!= UNKNOWN_MODE
)
5066 && (old_interrupt_type
!= new_interrupt_type
))
5067 error ("%qs function cannot have different interrupt type", "interrupt");
5069 /* Create combined attributes. */
5070 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
5071 DECL_ATTRIBUTES (newdecl
));
5073 return combined_attrs
;
5076 /* Implement TARGET_CANNOT_COPY_INSN_P. */
5079 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
5081 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
5084 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
5087 riscv_slow_unaligned_access (machine_mode
, unsigned int)
5089 return riscv_slow_unaligned_access_p
;
5092 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
5095 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
5097 return !reg_classes_intersect_p (FP_REGS
, rclass
);
5101 /* Implement TARGET_CONSTANT_ALIGNMENT. */
5103 static HOST_WIDE_INT
5104 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
5106 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
5107 && (riscv_align_data_type
== riscv_align_data_type_xlen
))
5108 return MAX (align
, BITS_PER_WORD
);
5112 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
5114 /* This function is equivalent to default_promote_function_mode_always_promote
5115 except that it returns a promoted mode even if type is NULL_TREE. This is
5116 needed by libcalls which have no type (only a mode) such as fixed conversion
5117 routines that take a signed or unsigned char/short/int argument and convert
5118 it to a fixed type. */
5121 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
5123 int *punsignedp ATTRIBUTE_UNUSED
,
5124 const_tree fntype ATTRIBUTE_UNUSED
,
5125 int for_return ATTRIBUTE_UNUSED
)
5129 if (type
!= NULL_TREE
)
5130 return promote_mode (type
, mode
, punsignedp
);
5132 unsignedp
= *punsignedp
;
5133 PROMOTE_MODE (mode
, unsignedp
, type
);
5134 *punsignedp
= unsignedp
;
5138 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
5143 /* Do nothing unless we have -msave-restore */
5144 if (TARGET_SAVE_RESTORE
)
5145 riscv_remove_unneeded_save_restore_calls ();
5148 /* Return nonzero if register FROM_REGNO can be renamed to register
5152 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED
,
5155 /* Interrupt functions can only use registers that have already been
5156 saved by the prologue, even if they would normally be
5158 return !cfun
->machine
->interrupt_handler_p
|| df_regs_ever_live_p (to_regno
);
5161 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
5164 riscv_new_address_profitable_p (rtx memref
, rtx_insn
*insn
, rtx new_addr
)
5166 /* Prefer old address if it is less expensive. */
5167 addr_space_t as
= MEM_ADDR_SPACE (memref
);
5168 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
5169 int old_cost
= address_cost (XEXP (memref
, 0), GET_MODE (memref
), as
, speed
);
5170 int new_cost
= address_cost (new_addr
, GET_MODE (memref
), as
, speed
);
5171 return new_cost
<= old_cost
;
5174 /* Helper function for generating gpr_save pattern. */
5177 riscv_gen_gpr_save_insn (struct riscv_frame_info
*frame
)
5179 unsigned count
= riscv_save_libcall_count (frame
->mask
);
5180 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
5181 unsigned veclen
= 1 + 2 + 1 + count
;
5182 rtvec vec
= rtvec_alloc (veclen
);
5184 gcc_assert (veclen
<= ARRAY_SIZE (gpr_save_reg_order
));
5186 RTVEC_ELT (vec
, 0) =
5187 gen_rtx_UNSPEC_VOLATILE (VOIDmode
,
5188 gen_rtvec (1, GEN_INT (count
)), UNSPECV_GPR_SAVE
);
5190 for (unsigned i
= 1; i
< veclen
; ++i
)
5192 unsigned regno
= gpr_save_reg_order
[i
];
5193 rtx reg
= gen_rtx_REG (Pmode
, regno
);
5196 /* t0 and t1 are CLOBBERs, others are USEs. */
5198 elt
= gen_rtx_CLOBBER (Pmode
, reg
);
5200 elt
= gen_rtx_USE (Pmode
, reg
);
5202 RTVEC_ELT (vec
, i
) = elt
;
5205 /* Largest number of caller-save register must set in mask if we are
5206 not using __riscv_save_0. */
5207 gcc_assert ((count
== 0) ||
5208 BITSET_P (frame
->mask
, gpr_save_reg_order
[veclen
- 1]));
5210 return gen_rtx_PARALLEL (VOIDmode
, vec
);
5213 /* Return true if it's valid gpr_save pattern. */
5216 riscv_gpr_save_operation_p (rtx op
)
5218 unsigned len
= XVECLEN (op
, 0);
5219 gcc_assert (len
<= ARRAY_SIZE (gpr_save_reg_order
));
5220 for (unsigned i
= 0; i
< len
; i
++)
5222 rtx elt
= XVECEXP (op
, 0, i
);
5225 /* First element in parallel is unspec. */
5226 if (GET_CODE (elt
) != UNSPEC_VOLATILE
5227 || GET_CODE (XVECEXP (elt
, 0, 0)) != CONST_INT
5228 || XINT (elt
, 1) != UNSPECV_GPR_SAVE
)
5233 /* Two CLOBBER and USEs, must check the order. */
5234 unsigned expect_code
= i
< 3 ? CLOBBER
: USE
;
5235 if (GET_CODE (elt
) != expect_code
5236 || !REG_P (XEXP (elt
, 1))
5237 || (REGNO (XEXP (elt
, 1)) != gpr_save_reg_order
[i
]))
5245 /* Initialize the GCC target structure. */
5246 #undef TARGET_ASM_ALIGNED_HI_OP
5247 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
5248 #undef TARGET_ASM_ALIGNED_SI_OP
5249 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5250 #undef TARGET_ASM_ALIGNED_DI_OP
5251 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
5253 #undef TARGET_OPTION_OVERRIDE
5254 #define TARGET_OPTION_OVERRIDE riscv_option_override
5256 #undef TARGET_LEGITIMIZE_ADDRESS
5257 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
5259 #undef TARGET_SCHED_ISSUE_RATE
5260 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
5262 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5263 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
5265 #undef TARGET_SET_CURRENT_FUNCTION
5266 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
5268 #undef TARGET_REGISTER_MOVE_COST
5269 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
5270 #undef TARGET_MEMORY_MOVE_COST
5271 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
5272 #undef TARGET_RTX_COSTS
5273 #define TARGET_RTX_COSTS riscv_rtx_costs
5274 #undef TARGET_ADDRESS_COST
5275 #define TARGET_ADDRESS_COST riscv_address_cost
5277 #undef TARGET_ASM_FILE_START
5278 #define TARGET_ASM_FILE_START riscv_file_start
5279 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5280 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5282 #undef TARGET_EXPAND_BUILTIN_VA_START
5283 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
5285 #undef TARGET_PROMOTE_FUNCTION_MODE
5286 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
5288 #undef TARGET_RETURN_IN_MEMORY
5289 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
5291 #undef TARGET_ASM_OUTPUT_MI_THUNK
5292 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
5293 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5294 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5296 #undef TARGET_PRINT_OPERAND
5297 #define TARGET_PRINT_OPERAND riscv_print_operand
5298 #undef TARGET_PRINT_OPERAND_ADDRESS
5299 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
5301 #undef TARGET_SETUP_INCOMING_VARARGS
5302 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
5303 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
5304 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
5305 #undef TARGET_STRICT_ARGUMENT_NAMING
5306 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
5307 #undef TARGET_MUST_PASS_IN_STACK
5308 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
5309 #undef TARGET_PASS_BY_REFERENCE
5310 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
5311 #undef TARGET_ARG_PARTIAL_BYTES
5312 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
5313 #undef TARGET_FUNCTION_ARG
5314 #define TARGET_FUNCTION_ARG riscv_function_arg
5315 #undef TARGET_FUNCTION_ARG_ADVANCE
5316 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
5317 #undef TARGET_FUNCTION_ARG_BOUNDARY
5318 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
5320 /* The generic ELF target does not always have TLS support. */
5322 #undef TARGET_HAVE_TLS
5323 #define TARGET_HAVE_TLS true
5326 #undef TARGET_CANNOT_FORCE_CONST_MEM
5327 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
5329 #undef TARGET_LEGITIMATE_CONSTANT_P
5330 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
5332 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5333 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
5335 #undef TARGET_LEGITIMATE_ADDRESS_P
5336 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
5338 #undef TARGET_CAN_ELIMINATE
5339 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
5341 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5342 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
5344 #undef TARGET_CLASS_MAX_NREGS
5345 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
5347 #undef TARGET_TRAMPOLINE_INIT
5348 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
5350 #undef TARGET_IN_SMALL_DATA_P
5351 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
5353 #undef TARGET_HAVE_SRODATA_SECTION
5354 #define TARGET_HAVE_SRODATA_SECTION true
5356 #undef TARGET_ASM_SELECT_SECTION
5357 #define TARGET_ASM_SELECT_SECTION riscv_select_section
5359 #undef TARGET_ASM_UNIQUE_SECTION
5360 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
5362 #undef TARGET_ASM_SELECT_RTX_SECTION
5363 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
5365 #undef TARGET_MIN_ANCHOR_OFFSET
5366 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
5368 #undef TARGET_MAX_ANCHOR_OFFSET
5369 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
5371 #undef TARGET_REGISTER_PRIORITY
5372 #define TARGET_REGISTER_PRIORITY riscv_register_priority
5374 #undef TARGET_CANNOT_COPY_INSN_P
5375 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
5377 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
5378 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5380 #undef TARGET_INIT_BUILTINS
5381 #define TARGET_INIT_BUILTINS riscv_init_builtins
5383 #undef TARGET_BUILTIN_DECL
5384 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5386 #undef TARGET_EXPAND_BUILTIN
5387 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5389 #undef TARGET_HARD_REGNO_NREGS
5390 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5391 #undef TARGET_HARD_REGNO_MODE_OK
5392 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5394 #undef TARGET_MODES_TIEABLE_P
5395 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5397 #undef TARGET_SLOW_UNALIGNED_ACCESS
5398 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5400 #undef TARGET_SECONDARY_MEMORY_NEEDED
5401 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5403 #undef TARGET_CAN_CHANGE_MODE_CLASS
5404 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5406 #undef TARGET_CONSTANT_ALIGNMENT
5407 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5409 #undef TARGET_MERGE_DECL_ATTRIBUTES
5410 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5412 #undef TARGET_ATTRIBUTE_TABLE
5413 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5415 #undef TARGET_WARN_FUNC_RETURN
5416 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5418 /* The low bit is ignored by jump instructions so is safe to use. */
5419 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5420 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5422 #undef TARGET_MACHINE_DEPENDENT_REORG
5423 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
5425 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
5426 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
5428 struct gcc_target targetm
= TARGET_INITIALIZER
;
5430 #include "gt-riscv.h"