Handle Octeon 3 not supporting MIPS paired-single instructions.
[official-gcc.git] / gcc / testsuite / gcc.target / mips / umips-lwp-6.c
blob9534974de8fcf3f1bc3074d78558a275ac3f07a3
1 /* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
2 /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
4 void MICROMIPS
5 foo (int *r4)
7 int r5 = r4[512];
8 int r6 = r4[513];
9 r4[2] = r6 * r6;
11 register int r5asm asm ("$5") = r5;
12 register int r6asm asm ("$6") = r6;
13 asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
17 /* { dg-final { scan-assembler-not "\tlwp" } }*/