Handle Octeon 3 not supporting MIPS paired-single instructions.
[official-gcc.git] / gcc / testsuite / gcc.target / mips / cache-1.c
blobf5c3dd307d8b592941efd36e21ec61e53c7c4cb5
1 /* { dg-options "isa>=3" } */
2 /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
4 NOMIPS16 void
5 f1 (int *area)
7 __builtin_mips_cache (20, area);
10 NOMIPS16 void
11 f2 (const short *area)
13 __builtin_mips_cache (24, area + 10);
16 NOMIPS16 void
17 f3 (volatile unsigned int *area, int offset)
19 __builtin_mips_cache (0, area + offset);
22 NOMIPS16 void
23 f4 (const volatile unsigned char *area)
25 __builtin_mips_cache (4, area - 80);
28 /* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
29 /* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
30 /* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */
31 /* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */