1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "basic-block.h"
43 #include "diagnostic-core.h"
44 #include "sched-int.h"
47 #include "target-def.h"
48 #include "common/common-target.h"
50 #include "hash-table.h"
51 #include "langhooks.h"
58 #include "tm-constrs.h"
59 #include "sel-sched.h"
64 /* This is used for communication between ASM_OUTPUT_LABEL and
65 ASM_OUTPUT_LABELREF. */
66 int ia64_asm_output_label
= 0;
68 /* Register names for ia64_expand_prologue. */
69 static const char * const ia64_reg_numbers
[96] =
70 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
71 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
72 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
73 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
74 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
75 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
76 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
77 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
78 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
79 "r104","r105","r106","r107","r108","r109","r110","r111",
80 "r112","r113","r114","r115","r116","r117","r118","r119",
81 "r120","r121","r122","r123","r124","r125","r126","r127"};
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_input_reg_names
[8] =
85 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
87 /* ??? These strings could be shared with REGISTER_NAMES. */
88 static const char * const ia64_local_reg_names
[80] =
89 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
90 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
91 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
92 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
93 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
94 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
95 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
96 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
97 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
98 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
100 /* ??? These strings could be shared with REGISTER_NAMES. */
101 static const char * const ia64_output_reg_names
[8] =
102 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
104 /* Variables which are this size or smaller are put in the sdata/sbss
107 unsigned int ia64_section_threshold
;
109 /* The following variable is used by the DFA insn scheduler. The value is
110 TRUE if we do insn bundling instead of insn scheduling. */
122 number_of_ia64_frame_regs
125 /* Structure to be filled in by ia64_compute_frame_size with register
126 save masks and offsets for the current function. */
128 struct ia64_frame_info
130 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
131 the caller's scratch area. */
132 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
133 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
134 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
135 HARD_REG_SET mask
; /* mask of saved registers. */
136 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
137 registers or long-term scratches. */
138 int n_spilled
; /* number of spilled registers. */
139 int r
[number_of_ia64_frame_regs
]; /* Frame related registers. */
140 int n_input_regs
; /* number of input registers used. */
141 int n_local_regs
; /* number of local registers used. */
142 int n_output_regs
; /* number of output registers used. */
143 int n_rotate_regs
; /* number of rotating registers used. */
145 char need_regstk
; /* true if a .regstk directive needed. */
146 char initialized
; /* true if the data is finalized. */
149 /* Current frame information calculated by ia64_compute_frame_size. */
150 static struct ia64_frame_info current_frame_info
;
151 /* The actual registers that are emitted. */
152 static int emitted_frame_related_regs
[number_of_ia64_frame_regs
];
154 static int ia64_first_cycle_multipass_dfa_lookahead (void);
155 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
156 static void ia64_init_dfa_pre_cycle_insn (void);
157 static rtx
ia64_dfa_pre_cycle_insn (void);
158 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
159 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx
);
160 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
161 static void ia64_h_i_d_extended (void);
162 static void * ia64_alloc_sched_context (void);
163 static void ia64_init_sched_context (void *, bool);
164 static void ia64_set_sched_context (void *);
165 static void ia64_clear_sched_context (void *);
166 static void ia64_free_sched_context (void *);
167 static int ia64_mode_to_int (enum machine_mode
);
168 static void ia64_set_sched_flags (spec_info_t
);
169 static ds_t
ia64_get_insn_spec_ds (rtx
);
170 static ds_t
ia64_get_insn_checked_ds (rtx
);
171 static bool ia64_skip_rtx_p (const_rtx
);
172 static int ia64_speculate_insn (rtx
, ds_t
, rtx
*);
173 static bool ia64_needs_block_p (ds_t
);
174 static rtx
ia64_gen_spec_check (rtx
, rtx
, ds_t
);
175 static int ia64_spec_check_p (rtx
);
176 static int ia64_spec_check_src_p (rtx
);
177 static rtx
gen_tls_get_addr (void);
178 static rtx
gen_thread_pointer (void);
179 static int find_gr_spill (enum ia64_frame_regs
, int);
180 static int next_scratch_gr_reg (void);
181 static void mark_reg_gr_used_mask (rtx
, void *);
182 static void ia64_compute_frame_size (HOST_WIDE_INT
);
183 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
184 static void finish_spill_pointers (void);
185 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
186 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
187 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
188 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
189 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
190 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
192 static void ia64_option_override (void);
193 static bool ia64_can_eliminate (const int, const int);
194 static enum machine_mode
hfa_element_mode (const_tree
, bool);
195 static void ia64_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
197 static int ia64_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
199 static rtx
ia64_function_arg_1 (cumulative_args_t
, enum machine_mode
,
200 const_tree
, bool, bool);
201 static rtx
ia64_function_arg (cumulative_args_t
, enum machine_mode
,
203 static rtx
ia64_function_incoming_arg (cumulative_args_t
,
204 enum machine_mode
, const_tree
, bool);
205 static void ia64_function_arg_advance (cumulative_args_t
, enum machine_mode
,
207 static unsigned int ia64_function_arg_boundary (enum machine_mode
,
209 static bool ia64_function_ok_for_sibcall (tree
, tree
);
210 static bool ia64_return_in_memory (const_tree
, const_tree
);
211 static rtx
ia64_function_value (const_tree
, const_tree
, bool);
212 static rtx
ia64_libcall_value (enum machine_mode
, const_rtx
);
213 static bool ia64_function_value_regno_p (const unsigned int);
214 static int ia64_register_move_cost (enum machine_mode
, reg_class_t
,
216 static int ia64_memory_move_cost (enum machine_mode mode
, reg_class_t
,
218 static bool ia64_rtx_costs (rtx
, int, int, int, int *, bool);
219 static int ia64_unspec_may_trap_p (const_rtx
, unsigned);
220 static void fix_range (const char *);
221 static struct machine_function
* ia64_init_machine_status (void);
222 static void emit_insn_group_barriers (FILE *);
223 static void emit_all_insn_group_barriers (FILE *);
224 static void final_emit_insn_group_barriers (FILE *);
225 static void emit_predicate_relation_info (void);
226 static void ia64_reorg (void);
227 static bool ia64_in_small_data_p (const_tree
);
228 static void process_epilogue (FILE *, rtx
, bool, bool);
230 static bool ia64_assemble_integer (rtx
, unsigned int, int);
231 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
232 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
233 static void ia64_output_function_end_prologue (FILE *);
235 static void ia64_print_operand (FILE *, rtx
, int);
236 static void ia64_print_operand_address (FILE *, rtx
);
237 static bool ia64_print_operand_punct_valid_p (unsigned char code
);
239 static int ia64_issue_rate (void);
240 static int ia64_adjust_cost_2 (rtx
, int, rtx
, int, dw_t
);
241 static void ia64_sched_init (FILE *, int, int);
242 static void ia64_sched_init_global (FILE *, int, int);
243 static void ia64_sched_finish_global (FILE *, int);
244 static void ia64_sched_finish (FILE *, int);
245 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
246 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
247 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
248 static int ia64_variable_issue (FILE *, int, rtx
, int);
250 static void ia64_asm_unwind_emit (FILE *, rtx
);
251 static void ia64_asm_emit_except_personality (rtx
);
252 static void ia64_asm_init_sections (void);
254 static enum unwind_info_type
ia64_debug_unwind_info (void);
256 static struct bundle_state
*get_free_bundle_state (void);
257 static void free_bundle_state (struct bundle_state
*);
258 static void initiate_bundle_states (void);
259 static void finish_bundle_states (void);
260 static int insert_bundle_state (struct bundle_state
*);
261 static void initiate_bundle_state_table (void);
262 static void finish_bundle_state_table (void);
263 static int try_issue_nops (struct bundle_state
*, int);
264 static int try_issue_insn (struct bundle_state
*, rtx
);
265 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
266 static int get_max_pos (state_t
);
267 static int get_template (state_t
, int);
269 static rtx
get_next_important_insn (rtx
, rtx
);
270 static bool important_for_bundling_p (rtx
);
271 static bool unknown_for_bundling_p (rtx
);
272 static void bundling (FILE *, int, rtx
, rtx
);
274 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
275 HOST_WIDE_INT
, tree
);
276 static void ia64_file_start (void);
277 static void ia64_globalize_decl_name (FILE *, tree
);
279 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
280 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
281 static section
*ia64_select_rtx_section (enum machine_mode
, rtx
,
282 unsigned HOST_WIDE_INT
);
283 static void ia64_output_dwarf_dtprel (FILE *, int, rtx
)
285 static unsigned int ia64_section_type_flags (tree
, const char *, int);
286 static void ia64_init_libfuncs (void)
288 static void ia64_hpux_init_libfuncs (void)
290 static void ia64_sysv4_init_libfuncs (void)
292 static void ia64_vms_init_libfuncs (void)
294 static void ia64_soft_fp_init_libfuncs (void)
296 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode
)
298 static tree
ia64_vms_common_object_attribute (tree
*, tree
, tree
, int, bool *)
301 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
302 static tree
ia64_handle_version_id_attribute (tree
*, tree
, tree
, int, bool *);
303 static void ia64_encode_section_info (tree
, rtx
, int);
304 static rtx
ia64_struct_value_rtx (tree
, int);
305 static tree
ia64_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
306 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
307 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
308 static bool ia64_legitimate_constant_p (enum machine_mode
, rtx
);
309 static bool ia64_legitimate_address_p (enum machine_mode
, rtx
, bool);
310 static bool ia64_cannot_force_const_mem (enum machine_mode
, rtx
);
311 static const char *ia64_mangle_type (const_tree
);
312 static const char *ia64_invalid_conversion (const_tree
, const_tree
);
313 static const char *ia64_invalid_unary_op (int, const_tree
);
314 static const char *ia64_invalid_binary_op (int, const_tree
, const_tree
);
315 static enum machine_mode
ia64_c_mode_for_suffix (char);
316 static void ia64_trampoline_init (rtx
, tree
, rtx
);
317 static void ia64_override_options_after_change (void);
318 static bool ia64_member_type_forces_blk (const_tree
, enum machine_mode
);
320 static tree
ia64_builtin_decl (unsigned, bool);
322 static reg_class_t
ia64_preferred_reload_class (rtx
, reg_class_t
);
323 static enum machine_mode
ia64_get_reg_raw_mode (int regno
);
324 static section
* ia64_hpux_function_section (tree
, enum node_frequency
,
327 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
328 const unsigned char *sel
);
330 #define MAX_VECT_LEN 8
332 struct expand_vec_perm_d
334 rtx target
, op0
, op1
;
335 unsigned char perm
[MAX_VECT_LEN
];
336 enum machine_mode vmode
;
342 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
);
345 /* Table of valid machine attributes. */
346 static const struct attribute_spec ia64_attribute_table
[] =
348 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
349 affects_type_identity } */
350 { "syscall_linkage", 0, 0, false, true, true, NULL
, false },
351 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
,
353 #if TARGET_ABI_OPEN_VMS
354 { "common_object", 1, 1, true, false, false,
355 ia64_vms_common_object_attribute
, false },
357 { "version_id", 1, 1, true, false, false,
358 ia64_handle_version_id_attribute
, false },
359 { NULL
, 0, 0, false, false, false, NULL
, false }
362 /* Initialize the GCC target structure. */
363 #undef TARGET_ATTRIBUTE_TABLE
364 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
366 #undef TARGET_INIT_BUILTINS
367 #define TARGET_INIT_BUILTINS ia64_init_builtins
369 #undef TARGET_EXPAND_BUILTIN
370 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
372 #undef TARGET_BUILTIN_DECL
373 #define TARGET_BUILTIN_DECL ia64_builtin_decl
375 #undef TARGET_ASM_BYTE_OP
376 #define TARGET_ASM_BYTE_OP "\tdata1\t"
377 #undef TARGET_ASM_ALIGNED_HI_OP
378 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
379 #undef TARGET_ASM_ALIGNED_SI_OP
380 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
381 #undef TARGET_ASM_ALIGNED_DI_OP
382 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
383 #undef TARGET_ASM_UNALIGNED_HI_OP
384 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
385 #undef TARGET_ASM_UNALIGNED_SI_OP
386 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
387 #undef TARGET_ASM_UNALIGNED_DI_OP
388 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
389 #undef TARGET_ASM_INTEGER
390 #define TARGET_ASM_INTEGER ia64_assemble_integer
392 #undef TARGET_OPTION_OVERRIDE
393 #define TARGET_OPTION_OVERRIDE ia64_option_override
395 #undef TARGET_ASM_FUNCTION_PROLOGUE
396 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
397 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
398 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
399 #undef TARGET_ASM_FUNCTION_EPILOGUE
400 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
402 #undef TARGET_PRINT_OPERAND
403 #define TARGET_PRINT_OPERAND ia64_print_operand
404 #undef TARGET_PRINT_OPERAND_ADDRESS
405 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
406 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
407 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
409 #undef TARGET_IN_SMALL_DATA_P
410 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
412 #undef TARGET_SCHED_ADJUST_COST_2
413 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
414 #undef TARGET_SCHED_ISSUE_RATE
415 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
416 #undef TARGET_SCHED_VARIABLE_ISSUE
417 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
418 #undef TARGET_SCHED_INIT
419 #define TARGET_SCHED_INIT ia64_sched_init
420 #undef TARGET_SCHED_FINISH
421 #define TARGET_SCHED_FINISH ia64_sched_finish
422 #undef TARGET_SCHED_INIT_GLOBAL
423 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
424 #undef TARGET_SCHED_FINISH_GLOBAL
425 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
426 #undef TARGET_SCHED_REORDER
427 #define TARGET_SCHED_REORDER ia64_sched_reorder
428 #undef TARGET_SCHED_REORDER2
429 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
431 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
432 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
434 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
435 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
437 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
438 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
439 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
440 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
442 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
443 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
444 ia64_first_cycle_multipass_dfa_lookahead_guard
446 #undef TARGET_SCHED_DFA_NEW_CYCLE
447 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
449 #undef TARGET_SCHED_H_I_D_EXTENDED
450 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
452 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
453 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
455 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
456 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
458 #undef TARGET_SCHED_SET_SCHED_CONTEXT
459 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
461 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
462 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
464 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
465 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
467 #undef TARGET_SCHED_SET_SCHED_FLAGS
468 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
470 #undef TARGET_SCHED_GET_INSN_SPEC_DS
471 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
473 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
474 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
476 #undef TARGET_SCHED_SPECULATE_INSN
477 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
479 #undef TARGET_SCHED_NEEDS_BLOCK_P
480 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
482 #undef TARGET_SCHED_GEN_SPEC_CHECK
483 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
485 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
486 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
487 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
489 #undef TARGET_SCHED_SKIP_RTX_P
490 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
492 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
493 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
494 #undef TARGET_ARG_PARTIAL_BYTES
495 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
496 #undef TARGET_FUNCTION_ARG
497 #define TARGET_FUNCTION_ARG ia64_function_arg
498 #undef TARGET_FUNCTION_INCOMING_ARG
499 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
500 #undef TARGET_FUNCTION_ARG_ADVANCE
501 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
502 #undef TARGET_FUNCTION_ARG_BOUNDARY
503 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
505 #undef TARGET_ASM_OUTPUT_MI_THUNK
506 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
507 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
508 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
510 #undef TARGET_ASM_FILE_START
511 #define TARGET_ASM_FILE_START ia64_file_start
513 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
514 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
516 #undef TARGET_REGISTER_MOVE_COST
517 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
518 #undef TARGET_MEMORY_MOVE_COST
519 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
520 #undef TARGET_RTX_COSTS
521 #define TARGET_RTX_COSTS ia64_rtx_costs
522 #undef TARGET_ADDRESS_COST
523 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
525 #undef TARGET_UNSPEC_MAY_TRAP_P
526 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
528 #undef TARGET_MACHINE_DEPENDENT_REORG
529 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
531 #undef TARGET_ENCODE_SECTION_INFO
532 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
534 #undef TARGET_SECTION_TYPE_FLAGS
535 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
538 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
539 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
542 /* ??? Investigate. */
544 #undef TARGET_PROMOTE_PROTOTYPES
545 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
548 #undef TARGET_FUNCTION_VALUE
549 #define TARGET_FUNCTION_VALUE ia64_function_value
550 #undef TARGET_LIBCALL_VALUE
551 #define TARGET_LIBCALL_VALUE ia64_libcall_value
552 #undef TARGET_FUNCTION_VALUE_REGNO_P
553 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
555 #undef TARGET_STRUCT_VALUE_RTX
556 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
557 #undef TARGET_RETURN_IN_MEMORY
558 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
559 #undef TARGET_SETUP_INCOMING_VARARGS
560 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
561 #undef TARGET_STRICT_ARGUMENT_NAMING
562 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
563 #undef TARGET_MUST_PASS_IN_STACK
564 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
565 #undef TARGET_GET_RAW_RESULT_MODE
566 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
567 #undef TARGET_GET_RAW_ARG_MODE
568 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
570 #undef TARGET_MEMBER_TYPE_FORCES_BLK
571 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
573 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
574 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
576 #undef TARGET_ASM_UNWIND_EMIT
577 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
578 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
579 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
580 #undef TARGET_ASM_INIT_SECTIONS
581 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
583 #undef TARGET_DEBUG_UNWIND_INFO
584 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
586 #undef TARGET_SCALAR_MODE_SUPPORTED_P
587 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
588 #undef TARGET_VECTOR_MODE_SUPPORTED_P
589 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
591 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
592 in an order different from the specified program order. */
593 #undef TARGET_RELAXED_ORDERING
594 #define TARGET_RELAXED_ORDERING true
596 #undef TARGET_LEGITIMATE_CONSTANT_P
597 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
598 #undef TARGET_LEGITIMATE_ADDRESS_P
599 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
601 #undef TARGET_CANNOT_FORCE_CONST_MEM
602 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
604 #undef TARGET_MANGLE_TYPE
605 #define TARGET_MANGLE_TYPE ia64_mangle_type
607 #undef TARGET_INVALID_CONVERSION
608 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
609 #undef TARGET_INVALID_UNARY_OP
610 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
611 #undef TARGET_INVALID_BINARY_OP
612 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
614 #undef TARGET_C_MODE_FOR_SUFFIX
615 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
617 #undef TARGET_CAN_ELIMINATE
618 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
620 #undef TARGET_TRAMPOLINE_INIT
621 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
623 #undef TARGET_INVALID_WITHIN_DOLOOP
624 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
626 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
627 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
629 #undef TARGET_PREFERRED_RELOAD_CLASS
630 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
632 #undef TARGET_DELAY_SCHED2
633 #define TARGET_DELAY_SCHED2 true
635 /* Variable tracking should be run after all optimizations which
636 change order of insns. It also needs a valid CFG. */
637 #undef TARGET_DELAY_VARTRACK
638 #define TARGET_DELAY_VARTRACK true
640 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
641 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
643 struct gcc_target targetm
= TARGET_INITIALIZER
;
647 ADDR_AREA_NORMAL
, /* normal address area */
648 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
652 static GTY(()) tree small_ident1
;
653 static GTY(()) tree small_ident2
;
658 if (small_ident1
== 0)
660 small_ident1
= get_identifier ("small");
661 small_ident2
= get_identifier ("__small__");
665 /* Retrieve the address area that has been chosen for the given decl. */
667 static ia64_addr_area
668 ia64_get_addr_area (tree decl
)
672 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
678 id
= TREE_VALUE (TREE_VALUE (model_attr
));
679 if (id
== small_ident1
|| id
== small_ident2
)
680 return ADDR_AREA_SMALL
;
682 return ADDR_AREA_NORMAL
;
686 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
687 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
689 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
691 tree arg
, decl
= *node
;
694 arg
= TREE_VALUE (args
);
695 if (arg
== small_ident1
|| arg
== small_ident2
)
697 addr_area
= ADDR_AREA_SMALL
;
701 warning (OPT_Wattributes
, "invalid argument of %qE attribute",
703 *no_add_attrs
= true;
706 switch (TREE_CODE (decl
))
709 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
711 && !TREE_STATIC (decl
))
713 error_at (DECL_SOURCE_LOCATION (decl
),
714 "an address area attribute cannot be specified for "
716 *no_add_attrs
= true;
718 area
= ia64_get_addr_area (decl
);
719 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
721 error ("address area of %q+D conflicts with previous "
722 "declaration", decl
);
723 *no_add_attrs
= true;
728 error_at (DECL_SOURCE_LOCATION (decl
),
729 "address area attribute cannot be specified for "
731 *no_add_attrs
= true;
735 warning (OPT_Wattributes
, "%qE attribute ignored",
737 *no_add_attrs
= true;
744 /* Part of the low level implementation of DEC Ada pragma Common_Object which
745 enables the shared use of variables stored in overlaid linker areas
746 corresponding to the use of Fortran COMMON. */
749 ia64_vms_common_object_attribute (tree
*node
, tree name
, tree args
,
750 int flags ATTRIBUTE_UNUSED
,
756 gcc_assert (DECL_P (decl
));
758 DECL_COMMON (decl
) = 1;
759 id
= TREE_VALUE (args
);
760 if (TREE_CODE (id
) != IDENTIFIER_NODE
&& TREE_CODE (id
) != STRING_CST
)
762 error ("%qE attribute requires a string constant argument", name
);
763 *no_add_attrs
= true;
769 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
772 ia64_vms_output_aligned_decl_common (FILE *file
, tree decl
, const char *name
,
773 unsigned HOST_WIDE_INT size
,
776 tree attr
= DECL_ATTRIBUTES (decl
);
779 attr
= lookup_attribute ("common_object", attr
);
782 tree id
= TREE_VALUE (TREE_VALUE (attr
));
785 if (TREE_CODE (id
) == IDENTIFIER_NODE
)
786 name
= IDENTIFIER_POINTER (id
);
787 else if (TREE_CODE (id
) == STRING_CST
)
788 name
= TREE_STRING_POINTER (id
);
792 fprintf (file
, "\t.vms_common\t\"%s\",", name
);
795 fprintf (file
, "%s", COMMON_ASM_OP
);
797 /* Code from elfos.h. */
798 assemble_name (file
, name
);
799 fprintf (file
, ","HOST_WIDE_INT_PRINT_UNSIGNED
",%u",
800 size
, align
/ BITS_PER_UNIT
);
806 ia64_encode_addr_area (tree decl
, rtx symbol
)
810 flags
= SYMBOL_REF_FLAGS (symbol
);
811 switch (ia64_get_addr_area (decl
))
813 case ADDR_AREA_NORMAL
: break;
814 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
815 default: gcc_unreachable ();
817 SYMBOL_REF_FLAGS (symbol
) = flags
;
821 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
823 default_encode_section_info (decl
, rtl
, first
);
825 /* Careful not to prod global register variables. */
826 if (TREE_CODE (decl
) == VAR_DECL
827 && GET_CODE (DECL_RTL (decl
)) == MEM
828 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
829 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
830 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
833 /* Return 1 if the operands of a move are ok. */
836 ia64_move_ok (rtx dst
, rtx src
)
838 /* If we're under init_recog_no_volatile, we'll not be able to use
839 memory_operand. So check the code directly and don't worry about
840 the validity of the underlying address, which should have been
841 checked elsewhere anyway. */
842 if (GET_CODE (dst
) != MEM
)
844 if (GET_CODE (src
) == MEM
)
846 if (register_operand (src
, VOIDmode
))
849 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
850 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
851 return src
== const0_rtx
;
853 return satisfies_constraint_G (src
);
856 /* Return 1 if the operands are ok for a floating point load pair. */
859 ia64_load_pair_ok (rtx dst
, rtx src
)
861 /* ??? There is a thinko in the implementation of the "x" constraint and the
862 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
863 also return false for it. */
864 if (GET_CODE (dst
) != REG
865 || !(FP_REGNO_P (REGNO (dst
)) && FP_REGNO_P (REGNO (dst
) + 1)))
867 if (GET_CODE (src
) != MEM
|| MEM_VOLATILE_P (src
))
869 switch (GET_CODE (XEXP (src
, 0)))
878 rtx adjust
= XEXP (XEXP (XEXP (src
, 0), 1), 1);
880 if (GET_CODE (adjust
) != CONST_INT
881 || INTVAL (adjust
) != GET_MODE_SIZE (GET_MODE (src
)))
892 addp4_optimize_ok (rtx op1
, rtx op2
)
894 return (basereg_operand (op1
, GET_MODE(op1
)) !=
895 basereg_operand (op2
, GET_MODE(op2
)));
898 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
899 Return the length of the field, or <= 0 on failure. */
902 ia64_depz_field_mask (rtx rop
, rtx rshift
)
904 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
905 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
907 /* Get rid of the zero bits we're shifting in. */
910 /* We must now have a solid block of 1's at bit 0. */
911 return exact_log2 (op
+ 1);
914 /* Return the TLS model to use for ADDR. */
916 static enum tls_model
917 tls_symbolic_operand_type (rtx addr
)
919 enum tls_model tls_kind
= TLS_MODEL_NONE
;
921 if (GET_CODE (addr
) == CONST
)
923 if (GET_CODE (XEXP (addr
, 0)) == PLUS
924 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
925 tls_kind
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr
, 0), 0));
927 else if (GET_CODE (addr
) == SYMBOL_REF
)
928 tls_kind
= SYMBOL_REF_TLS_MODEL (addr
);
933 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
934 as a base register. */
937 ia64_reg_ok_for_base_p (const_rtx reg
, bool strict
)
940 && REGNO_OK_FOR_BASE_P (REGNO (reg
)))
943 && (GENERAL_REGNO_P (REGNO (reg
))
944 || !HARD_REGISTER_P (reg
)))
951 ia64_legitimate_address_reg (const_rtx reg
, bool strict
)
953 if ((REG_P (reg
) && ia64_reg_ok_for_base_p (reg
, strict
))
954 || (GET_CODE (reg
) == SUBREG
&& REG_P (XEXP (reg
, 0))
955 && ia64_reg_ok_for_base_p (XEXP (reg
, 0), strict
)))
962 ia64_legitimate_address_disp (const_rtx reg
, const_rtx disp
, bool strict
)
964 if (GET_CODE (disp
) == PLUS
965 && rtx_equal_p (reg
, XEXP (disp
, 0))
966 && (ia64_legitimate_address_reg (XEXP (disp
, 1), strict
)
967 || (CONST_INT_P (XEXP (disp
, 1))
968 && IN_RANGE (INTVAL (XEXP (disp
, 1)), -256, 255))))
974 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
977 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
980 if (ia64_legitimate_address_reg (x
, strict
))
982 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == POST_DEC
)
983 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
984 && XEXP (x
, 0) != arg_pointer_rtx
)
986 else if (GET_CODE (x
) == POST_MODIFY
987 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
988 && XEXP (x
, 0) != arg_pointer_rtx
989 && ia64_legitimate_address_disp (XEXP (x
, 0), XEXP (x
, 1), strict
))
995 /* Return true if X is a constant that is valid for some immediate
996 field in an instruction. */
999 ia64_legitimate_constant_p (enum machine_mode mode
, rtx x
)
1001 switch (GET_CODE (x
))
1008 if (GET_MODE (x
) == VOIDmode
|| mode
== SFmode
|| mode
== DFmode
)
1010 return satisfies_constraint_G (x
);
1014 /* ??? Short term workaround for PR 28490. We must make the code here
1015 match the code in ia64_expand_move and move_operand, even though they
1016 are both technically wrong. */
1017 if (tls_symbolic_operand_type (x
) == 0)
1019 HOST_WIDE_INT addend
= 0;
1022 if (GET_CODE (op
) == CONST
1023 && GET_CODE (XEXP (op
, 0)) == PLUS
1024 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1026 addend
= INTVAL (XEXP (XEXP (op
, 0), 1));
1027 op
= XEXP (XEXP (op
, 0), 0);
1030 if (any_offset_symbol_operand (op
, mode
)
1031 || function_operand (op
, mode
))
1033 if (aligned_offset_symbol_operand (op
, mode
))
1034 return (addend
& 0x3fff) == 0;
1040 if (mode
== V2SFmode
)
1041 return satisfies_constraint_Y (x
);
1043 return (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
1044 && GET_MODE_SIZE (mode
) <= 8);
1051 /* Don't allow TLS addresses to get spilled to memory. */
1054 ia64_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1058 return tls_symbolic_operand_type (x
) != 0;
1061 /* Expand a symbolic constant load. */
1064 ia64_expand_load_address (rtx dest
, rtx src
)
1066 gcc_assert (GET_CODE (dest
) == REG
);
1068 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1069 having to pointer-extend the value afterward. Other forms of address
1070 computation below are also more natural to compute as 64-bit quantities.
1071 If we've been given an SImode destination register, change it. */
1072 if (GET_MODE (dest
) != Pmode
)
1073 dest
= gen_rtx_REG_offset (dest
, Pmode
, REGNO (dest
),
1074 byte_lowpart_offset (Pmode
, GET_MODE (dest
)));
1078 if (small_addr_symbolic_operand (src
, VOIDmode
))
1081 if (TARGET_AUTO_PIC
)
1082 emit_insn (gen_load_gprel64 (dest
, src
));
1083 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1084 emit_insn (gen_load_fptr (dest
, src
));
1085 else if (sdata_symbolic_operand (src
, VOIDmode
))
1086 emit_insn (gen_load_gprel (dest
, src
));
1089 HOST_WIDE_INT addend
= 0;
1092 /* We did split constant offsets in ia64_expand_move, and we did try
1093 to keep them split in move_operand, but we also allowed reload to
1094 rematerialize arbitrary constants rather than spill the value to
1095 the stack and reload it. So we have to be prepared here to split
1096 them apart again. */
1097 if (GET_CODE (src
) == CONST
)
1099 HOST_WIDE_INT hi
, lo
;
1101 hi
= INTVAL (XEXP (XEXP (src
, 0), 1));
1102 lo
= ((hi
& 0x3fff) ^ 0x2000) - 0x2000;
1108 src
= plus_constant (Pmode
, XEXP (XEXP (src
, 0), 0), hi
);
1112 tmp
= gen_rtx_HIGH (Pmode
, src
);
1113 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1114 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1116 tmp
= gen_rtx_LO_SUM (Pmode
, gen_const_mem (Pmode
, dest
), src
);
1117 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1121 tmp
= gen_rtx_PLUS (Pmode
, dest
, GEN_INT (addend
));
1122 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1129 static GTY(()) rtx gen_tls_tga
;
1131 gen_tls_get_addr (void)
1134 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1138 static GTY(()) rtx thread_pointer_rtx
;
1140 gen_thread_pointer (void)
1142 if (!thread_pointer_rtx
)
1143 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1144 return thread_pointer_rtx
;
1148 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
,
1149 rtx orig_op1
, HOST_WIDE_INT addend
)
1151 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1153 HOST_WIDE_INT addend_lo
, addend_hi
;
1157 case TLS_MODEL_GLOBAL_DYNAMIC
:
1160 tga_op1
= gen_reg_rtx (Pmode
);
1161 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1163 tga_op2
= gen_reg_rtx (Pmode
);
1164 emit_insn (gen_load_dtprel (tga_op2
, op1
));
1166 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1167 LCT_CONST
, Pmode
, 2, tga_op1
,
1168 Pmode
, tga_op2
, Pmode
);
1170 insns
= get_insns ();
1173 if (GET_MODE (op0
) != Pmode
)
1175 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1178 case TLS_MODEL_LOCAL_DYNAMIC
:
1179 /* ??? This isn't the completely proper way to do local-dynamic
1180 If the call to __tls_get_addr is used only by a single symbol,
1181 then we should (somehow) move the dtprel to the second arg
1182 to avoid the extra add. */
1185 tga_op1
= gen_reg_rtx (Pmode
);
1186 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1188 tga_op2
= const0_rtx
;
1190 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1191 LCT_CONST
, Pmode
, 2, tga_op1
,
1192 Pmode
, tga_op2
, Pmode
);
1194 insns
= get_insns ();
1197 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1199 tmp
= gen_reg_rtx (Pmode
);
1200 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1202 if (!register_operand (op0
, Pmode
))
1203 op0
= gen_reg_rtx (Pmode
);
1206 emit_insn (gen_load_dtprel (op0
, op1
));
1207 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1210 emit_insn (gen_add_dtprel (op0
, op1
, tmp
));
1213 case TLS_MODEL_INITIAL_EXEC
:
1214 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1215 addend_hi
= addend
- addend_lo
;
1217 op1
= plus_constant (Pmode
, op1
, addend_hi
);
1220 tmp
= gen_reg_rtx (Pmode
);
1221 emit_insn (gen_load_tprel (tmp
, op1
));
1223 if (!register_operand (op0
, Pmode
))
1224 op0
= gen_reg_rtx (Pmode
);
1225 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1228 case TLS_MODEL_LOCAL_EXEC
:
1229 if (!register_operand (op0
, Pmode
))
1230 op0
= gen_reg_rtx (Pmode
);
1236 emit_insn (gen_load_tprel (op0
, op1
));
1237 emit_insn (gen_adddi3 (op0
, op0
, gen_thread_pointer ()));
1240 emit_insn (gen_add_tprel (op0
, op1
, gen_thread_pointer ()));
1248 op0
= expand_simple_binop (Pmode
, PLUS
, op0
, GEN_INT (addend
),
1249 orig_op0
, 1, OPTAB_DIRECT
);
1250 if (orig_op0
== op0
)
1252 if (GET_MODE (orig_op0
) == Pmode
)
1254 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1258 ia64_expand_move (rtx op0
, rtx op1
)
1260 enum machine_mode mode
= GET_MODE (op0
);
1262 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1263 op1
= force_reg (mode
, op1
);
1265 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1267 HOST_WIDE_INT addend
= 0;
1268 enum tls_model tls_kind
;
1271 if (GET_CODE (op1
) == CONST
1272 && GET_CODE (XEXP (op1
, 0)) == PLUS
1273 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
)
1275 addend
= INTVAL (XEXP (XEXP (op1
, 0), 1));
1276 sym
= XEXP (XEXP (op1
, 0), 0);
1279 tls_kind
= tls_symbolic_operand_type (sym
);
1281 return ia64_expand_tls_address (tls_kind
, op0
, sym
, op1
, addend
);
1283 if (any_offset_symbol_operand (sym
, mode
))
1285 else if (aligned_offset_symbol_operand (sym
, mode
))
1287 HOST_WIDE_INT addend_lo
, addend_hi
;
1289 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1290 addend_hi
= addend
- addend_lo
;
1294 op1
= plus_constant (mode
, sym
, addend_hi
);
1303 if (reload_completed
)
1305 /* We really should have taken care of this offset earlier. */
1306 gcc_assert (addend
== 0);
1307 if (ia64_expand_load_address (op0
, op1
))
1313 rtx subtarget
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (mode
);
1315 emit_insn (gen_rtx_SET (VOIDmode
, subtarget
, op1
));
1317 op1
= expand_simple_binop (mode
, PLUS
, subtarget
,
1318 GEN_INT (addend
), op0
, 1, OPTAB_DIRECT
);
1327 /* Split a move from OP1 to OP0 conditional on COND. */
1330 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1332 rtx insn
, first
= get_last_insn ();
1334 emit_move_insn (op0
, op1
);
1336 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1338 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1342 /* Split a post-reload TImode or TFmode reference into two DImode
1343 components. This is made extra difficult by the fact that we do
1344 not get any scratch registers to work with, because reload cannot
1345 be prevented from giving us a scratch that overlaps the register
1346 pair involved. So instead, when addressing memory, we tweak the
1347 pointer register up and back down with POST_INCs. Or up and not
1348 back down when we can get away with it.
1350 REVERSED is true when the loads must be done in reversed order
1351 (high word first) for correctness. DEAD is true when the pointer
1352 dies with the second insn we generate and therefore the second
1353 address must not carry a postmodify.
1355 May return an insn which is to be emitted after the moves. */
1358 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1362 switch (GET_CODE (in
))
1365 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1366 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1371 /* Cannot occur reversed. */
1372 gcc_assert (!reversed
);
1374 if (GET_MODE (in
) != TFmode
)
1375 split_double (in
, &out
[0], &out
[1]);
1377 /* split_double does not understand how to split a TFmode
1378 quantity into a pair of DImode constants. */
1381 unsigned HOST_WIDE_INT p
[2];
1382 long l
[4]; /* TFmode is 128 bits */
1384 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1385 real_to_target (l
, &r
, TFmode
);
1387 if (FLOAT_WORDS_BIG_ENDIAN
)
1389 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1390 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1394 p
[0] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1395 p
[1] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1397 out
[0] = GEN_INT (p
[0]);
1398 out
[1] = GEN_INT (p
[1]);
1404 rtx base
= XEXP (in
, 0);
1407 switch (GET_CODE (base
))
1412 out
[0] = adjust_automodify_address
1413 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1414 out
[1] = adjust_automodify_address
1415 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1419 /* Reversal requires a pre-increment, which can only
1420 be done as a separate insn. */
1421 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1422 out
[0] = adjust_automodify_address
1423 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1424 out
[1] = adjust_address (in
, DImode
, 0);
1429 gcc_assert (!reversed
&& !dead
);
1431 /* Just do the increment in two steps. */
1432 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1433 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1437 gcc_assert (!reversed
&& !dead
);
1439 /* Add 8, subtract 24. */
1440 base
= XEXP (base
, 0);
1441 out
[0] = adjust_automodify_address
1442 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1443 out
[1] = adjust_automodify_address
1445 gen_rtx_POST_MODIFY (Pmode
, base
,
1446 plus_constant (Pmode
, base
, -24)),
1451 gcc_assert (!reversed
&& !dead
);
1453 /* Extract and adjust the modification. This case is
1454 trickier than the others, because we might have an
1455 index register, or we might have a combined offset that
1456 doesn't fit a signed 9-bit displacement field. We can
1457 assume the incoming expression is already legitimate. */
1458 offset
= XEXP (base
, 1);
1459 base
= XEXP (base
, 0);
1461 out
[0] = adjust_automodify_address
1462 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1464 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1466 /* Can't adjust the postmodify to match. Emit the
1467 original, then a separate addition insn. */
1468 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1469 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1473 gcc_assert (GET_CODE (XEXP (offset
, 1)) == CONST_INT
);
1474 if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1476 /* Again the postmodify cannot be made to match,
1477 but in this case it's more efficient to get rid
1478 of the postmodify entirely and fix up with an
1480 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1482 (base
, base
, GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1486 /* Combined offset still fits in the displacement field.
1487 (We cannot overflow it at the high end.) */
1488 out
[1] = adjust_automodify_address
1489 (in
, DImode
, gen_rtx_POST_MODIFY
1490 (Pmode
, base
, gen_rtx_PLUS
1492 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1511 /* Split a TImode or TFmode move instruction after reload.
1512 This is used by *movtf_internal and *movti_internal. */
1514 ia64_split_tmode_move (rtx operands
[])
1516 rtx in
[2], out
[2], insn
;
1519 bool reversed
= false;
1521 /* It is possible for reload to decide to overwrite a pointer with
1522 the value it points to. In that case we have to do the loads in
1523 the appropriate order so that the pointer is not destroyed too
1524 early. Also we must not generate a postmodify for that second
1525 load, or rws_access_regno will die. */
1526 if (GET_CODE (operands
[1]) == MEM
1527 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1529 rtx base
= XEXP (operands
[1], 0);
1530 while (GET_CODE (base
) != REG
)
1531 base
= XEXP (base
, 0);
1533 if (REGNO (base
) == REGNO (operands
[0]))
1537 /* Another reason to do the moves in reversed order is if the first
1538 element of the target register pair is also the second element of
1539 the source register pair. */
1540 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1541 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1544 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1545 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1547 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1548 if (GET_CODE (EXP) == MEM \
1549 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1550 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1551 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1552 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1554 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1555 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1556 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1558 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1559 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1560 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1563 emit_insn (fixup
[0]);
1565 emit_insn (fixup
[1]);
1567 #undef MAYBE_ADD_REG_INC_NOTE
1570 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1571 through memory plus an extra GR scratch register. Except that you can
1572 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1573 SECONDARY_RELOAD_CLASS, but not both.
1575 We got into problems in the first place by allowing a construct like
1576 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1577 This solution attempts to prevent this situation from occurring. When
1578 we see something like the above, we spill the inner register to memory. */
1581 spill_xfmode_rfmode_operand (rtx in
, int force
, enum machine_mode mode
)
1583 if (GET_CODE (in
) == SUBREG
1584 && GET_MODE (SUBREG_REG (in
)) == TImode
1585 && GET_CODE (SUBREG_REG (in
)) == REG
)
1587 rtx memt
= assign_stack_temp (TImode
, 16);
1588 emit_move_insn (memt
, SUBREG_REG (in
));
1589 return adjust_address (memt
, mode
, 0);
1591 else if (force
&& GET_CODE (in
) == REG
)
1593 rtx memx
= assign_stack_temp (mode
, 16);
1594 emit_move_insn (memx
, in
);
1601 /* Expand the movxf or movrf pattern (MODE says which) with the given
1602 OPERANDS, returning true if the pattern should then invoke
1606 ia64_expand_movxf_movrf (enum machine_mode mode
, rtx operands
[])
1608 rtx op0
= operands
[0];
1610 if (GET_CODE (op0
) == SUBREG
)
1611 op0
= SUBREG_REG (op0
);
1613 /* We must support XFmode loads into general registers for stdarg/vararg,
1614 unprototyped calls, and a rare case where a long double is passed as
1615 an argument after a float HFA fills the FP registers. We split them into
1616 DImode loads for convenience. We also need to support XFmode stores
1617 for the last case. This case does not happen for stdarg/vararg routines,
1618 because we do a block store to memory of unnamed arguments. */
1620 if (GET_CODE (op0
) == REG
&& GR_REGNO_P (REGNO (op0
)))
1624 /* We're hoping to transform everything that deals with XFmode
1625 quantities and GR registers early in the compiler. */
1626 gcc_assert (can_create_pseudo_p ());
1628 /* Struct to register can just use TImode instead. */
1629 if ((GET_CODE (operands
[1]) == SUBREG
1630 && GET_MODE (SUBREG_REG (operands
[1])) == TImode
)
1631 || (GET_CODE (operands
[1]) == REG
1632 && GR_REGNO_P (REGNO (operands
[1]))))
1634 rtx op1
= operands
[1];
1636 if (GET_CODE (op1
) == SUBREG
)
1637 op1
= SUBREG_REG (op1
);
1639 op1
= gen_rtx_REG (TImode
, REGNO (op1
));
1641 emit_move_insn (gen_rtx_REG (TImode
, REGNO (op0
)), op1
);
1645 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1647 /* Don't word-swap when reading in the constant. */
1648 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
)),
1649 operand_subword (operands
[1], WORDS_BIG_ENDIAN
,
1651 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
) + 1),
1652 operand_subword (operands
[1], !WORDS_BIG_ENDIAN
,
1657 /* If the quantity is in a register not known to be GR, spill it. */
1658 if (register_operand (operands
[1], mode
))
1659 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 1, mode
);
1661 gcc_assert (GET_CODE (operands
[1]) == MEM
);
1663 /* Don't word-swap when reading in the value. */
1664 out
[0] = gen_rtx_REG (DImode
, REGNO (op0
));
1665 out
[1] = gen_rtx_REG (DImode
, REGNO (op0
) + 1);
1667 emit_move_insn (out
[0], adjust_address (operands
[1], DImode
, 0));
1668 emit_move_insn (out
[1], adjust_address (operands
[1], DImode
, 8));
1672 if (GET_CODE (operands
[1]) == REG
&& GR_REGNO_P (REGNO (operands
[1])))
1674 /* We're hoping to transform everything that deals with XFmode
1675 quantities and GR registers early in the compiler. */
1676 gcc_assert (can_create_pseudo_p ());
1678 /* Op0 can't be a GR_REG here, as that case is handled above.
1679 If op0 is a register, then we spill op1, so that we now have a
1680 MEM operand. This requires creating an XFmode subreg of a TImode reg
1681 to force the spill. */
1682 if (register_operand (operands
[0], mode
))
1684 rtx op1
= gen_rtx_REG (TImode
, REGNO (operands
[1]));
1685 op1
= gen_rtx_SUBREG (mode
, op1
, 0);
1686 operands
[1] = spill_xfmode_rfmode_operand (op1
, 0, mode
);
1693 gcc_assert (GET_CODE (operands
[0]) == MEM
);
1695 /* Don't word-swap when writing out the value. */
1696 in
[0] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
1697 in
[1] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
1699 emit_move_insn (adjust_address (operands
[0], DImode
, 0), in
[0]);
1700 emit_move_insn (adjust_address (operands
[0], DImode
, 8), in
[1]);
1705 if (!reload_in_progress
&& !reload_completed
)
1707 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 0, mode
);
1709 if (GET_MODE (op0
) == TImode
&& GET_CODE (op0
) == REG
)
1711 rtx memt
, memx
, in
= operands
[1];
1712 if (CONSTANT_P (in
))
1713 in
= validize_mem (force_const_mem (mode
, in
));
1714 if (GET_CODE (in
) == MEM
)
1715 memt
= adjust_address (in
, TImode
, 0);
1718 memt
= assign_stack_temp (TImode
, 16);
1719 memx
= adjust_address (memt
, mode
, 0);
1720 emit_move_insn (memx
, in
);
1722 emit_move_insn (op0
, memt
);
1726 if (!ia64_move_ok (operands
[0], operands
[1]))
1727 operands
[1] = force_reg (mode
, operands
[1]);
1733 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1734 with the expression that holds the compare result (in VOIDmode). */
1736 static GTY(()) rtx cmptf_libfunc
;
1739 ia64_expand_compare (rtx
*expr
, rtx
*op0
, rtx
*op1
)
1741 enum rtx_code code
= GET_CODE (*expr
);
1744 /* If we have a BImode input, then we already have a compare result, and
1745 do not need to emit another comparison. */
1746 if (GET_MODE (*op0
) == BImode
)
1748 gcc_assert ((code
== NE
|| code
== EQ
) && *op1
== const0_rtx
);
1751 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1752 magic number as its third argument, that indicates what to do.
1753 The return value is an integer to be compared against zero. */
1754 else if (TARGET_HPUX
&& GET_MODE (*op0
) == TFmode
)
1757 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1764 enum rtx_code ncode
;
1767 gcc_assert (cmptf_libfunc
&& GET_MODE (*op1
) == TFmode
);
1770 /* 1 = equal, 0 = not equal. Equality operators do
1771 not raise FP_INVALID when given an SNaN operand. */
1772 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1773 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1774 /* isunordered() from C99. */
1775 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1776 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1777 /* Relational operators raise FP_INVALID when given
1779 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1780 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1781 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1782 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1783 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1784 Expanders for buneq etc. weuld have to be added to ia64.md
1785 for this to be useful. */
1786 default: gcc_unreachable ();
1791 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1792 *op0
, TFmode
, *op1
, TFmode
,
1793 GEN_INT (magic
), DImode
);
1794 cmp
= gen_reg_rtx (BImode
);
1795 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1796 gen_rtx_fmt_ee (ncode
, BImode
,
1799 insns
= get_insns ();
1802 emit_libcall_block (insns
, cmp
, cmp
,
1803 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
));
1808 cmp
= gen_reg_rtx (BImode
);
1809 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1810 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
)));
1814 *expr
= gen_rtx_fmt_ee (code
, VOIDmode
, cmp
, const0_rtx
);
1819 /* Generate an integral vector comparison. Return true if the condition has
1820 been reversed, and so the sense of the comparison should be inverted. */
1823 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1824 rtx dest
, rtx op0
, rtx op1
)
1826 bool negate
= false;
1829 /* Canonicalize the comparison to EQ, GT, GTU. */
1840 code
= reverse_condition (code
);
1846 code
= reverse_condition (code
);
1852 code
= swap_condition (code
);
1853 x
= op0
, op0
= op1
, op1
= x
;
1860 /* Unsigned parallel compare is not supported by the hardware. Play some
1861 tricks to turn this into a signed comparison against 0. */
1870 /* Subtract (-(INT MAX) - 1) from both operands to make
1872 mask
= GEN_INT (0x80000000);
1873 mask
= gen_rtx_CONST_VECTOR (V2SImode
, gen_rtvec (2, mask
, mask
));
1874 mask
= force_reg (mode
, mask
);
1875 t1
= gen_reg_rtx (mode
);
1876 emit_insn (gen_subv2si3 (t1
, op0
, mask
));
1877 t2
= gen_reg_rtx (mode
);
1878 emit_insn (gen_subv2si3 (t2
, op1
, mask
));
1887 /* Perform a parallel unsigned saturating subtraction. */
1888 x
= gen_reg_rtx (mode
);
1889 emit_insn (gen_rtx_SET (VOIDmode
, x
,
1890 gen_rtx_US_MINUS (mode
, op0
, op1
)));
1894 op1
= CONST0_RTX (mode
);
1903 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1904 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1909 /* Emit an integral vector conditional move. */
1912 ia64_expand_vecint_cmov (rtx operands
[])
1914 enum machine_mode mode
= GET_MODE (operands
[0]);
1915 enum rtx_code code
= GET_CODE (operands
[3]);
1919 cmp
= gen_reg_rtx (mode
);
1920 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1921 operands
[4], operands
[5]);
1923 ot
= operands
[1+negate
];
1924 of
= operands
[2-negate
];
1926 if (ot
== CONST0_RTX (mode
))
1928 if (of
== CONST0_RTX (mode
))
1930 emit_move_insn (operands
[0], ot
);
1934 x
= gen_rtx_NOT (mode
, cmp
);
1935 x
= gen_rtx_AND (mode
, x
, of
);
1936 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1938 else if (of
== CONST0_RTX (mode
))
1940 x
= gen_rtx_AND (mode
, cmp
, ot
);
1941 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1947 t
= gen_reg_rtx (mode
);
1948 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1949 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1951 f
= gen_reg_rtx (mode
);
1952 x
= gen_rtx_NOT (mode
, cmp
);
1953 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1954 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1956 x
= gen_rtx_IOR (mode
, t
, f
);
1957 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1961 /* Emit an integral vector min or max operation. Return true if all done. */
1964 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1969 /* These four combinations are supported directly. */
1970 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
1972 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
1975 /* This combination can be implemented with only saturating subtraction. */
1976 if (mode
== V4HImode
&& code
== UMAX
)
1978 rtx x
, tmp
= gen_reg_rtx (mode
);
1980 x
= gen_rtx_US_MINUS (mode
, operands
[1], operands
[2]);
1981 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, x
));
1983 emit_insn (gen_addv4hi3 (operands
[0], tmp
, operands
[2]));
1987 /* Everything else implemented via vector comparisons. */
1988 xops
[0] = operands
[0];
1989 xops
[4] = xops
[1] = operands
[1];
1990 xops
[5] = xops
[2] = operands
[2];
2009 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
2011 ia64_expand_vecint_cmov (xops
);
2015 /* The vectors LO and HI each contain N halves of a double-wide vector.
2016 Reassemble either the first N/2 or the second N/2 elements. */
2019 ia64_unpack_assemble (rtx out
, rtx lo
, rtx hi
, bool highp
)
2021 enum machine_mode vmode
= GET_MODE (lo
);
2022 unsigned int i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
2023 struct expand_vec_perm_d d
;
2026 d
.target
= gen_lowpart (vmode
, out
);
2027 d
.op0
= (TARGET_BIG_ENDIAN
? hi
: lo
);
2028 d
.op1
= (TARGET_BIG_ENDIAN
? lo
: hi
);
2031 d
.one_operand_p
= false;
2032 d
.testing_p
= false;
2034 high
= (highp
? nelt
/ 2 : 0);
2035 for (i
= 0; i
< nelt
/ 2; ++i
)
2037 d
.perm
[i
* 2] = i
+ high
;
2038 d
.perm
[i
* 2 + 1] = i
+ high
+ nelt
;
2041 ok
= ia64_expand_vec_perm_const_1 (&d
);
2045 /* Return a vector of the sign-extension of VEC. */
2048 ia64_unpack_sign (rtx vec
, bool unsignedp
)
2050 enum machine_mode mode
= GET_MODE (vec
);
2051 rtx zero
= CONST0_RTX (mode
);
2057 rtx sign
= gen_reg_rtx (mode
);
2060 neg
= ia64_expand_vecint_compare (LT
, mode
, sign
, vec
, zero
);
2067 /* Emit an integral vector unpack operation. */
2070 ia64_expand_unpack (rtx operands
[3], bool unsignedp
, bool highp
)
2072 rtx sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2073 ia64_unpack_assemble (operands
[0], operands
[1], sign
, highp
);
2076 /* Emit an integral vector widening sum operations. */
2079 ia64_expand_widen_sum (rtx operands
[3], bool unsignedp
)
2081 enum machine_mode wmode
;
2084 sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2086 wmode
= GET_MODE (operands
[0]);
2087 l
= gen_reg_rtx (wmode
);
2088 h
= gen_reg_rtx (wmode
);
2090 ia64_unpack_assemble (l
, operands
[1], sign
, false);
2091 ia64_unpack_assemble (h
, operands
[1], sign
, true);
2093 t
= expand_binop (wmode
, add_optab
, l
, operands
[2], NULL
, 0, OPTAB_DIRECT
);
2094 t
= expand_binop (wmode
, add_optab
, h
, t
, operands
[0], 0, OPTAB_DIRECT
);
2095 if (t
!= operands
[0])
2096 emit_move_insn (operands
[0], t
);
2099 /* Emit the appropriate sequence for a call. */
2102 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
2107 addr
= XEXP (addr
, 0);
2108 addr
= convert_memory_address (DImode
, addr
);
2109 b0
= gen_rtx_REG (DImode
, R_BR (0));
2111 /* ??? Should do this for functions known to bind local too. */
2112 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
2115 insn
= gen_sibcall_nogp (addr
);
2117 insn
= gen_call_nogp (addr
, b0
);
2119 insn
= gen_call_value_nogp (retval
, addr
, b0
);
2120 insn
= emit_call_insn (insn
);
2125 insn
= gen_sibcall_gp (addr
);
2127 insn
= gen_call_gp (addr
, b0
);
2129 insn
= gen_call_value_gp (retval
, addr
, b0
);
2130 insn
= emit_call_insn (insn
);
2132 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2136 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
2138 if (TARGET_ABI_OPEN_VMS
)
2139 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2140 gen_rtx_REG (DImode
, GR_REG (25)));
2144 reg_emitted (enum ia64_frame_regs r
)
2146 if (emitted_frame_related_regs
[r
] == 0)
2147 emitted_frame_related_regs
[r
] = current_frame_info
.r
[r
];
2149 gcc_assert (emitted_frame_related_regs
[r
] == current_frame_info
.r
[r
]);
2153 get_reg (enum ia64_frame_regs r
)
2156 return current_frame_info
.r
[r
];
2160 is_emitted (int regno
)
2164 for (r
= reg_fp
; r
< number_of_ia64_frame_regs
; r
++)
2165 if (emitted_frame_related_regs
[r
] == regno
)
2171 ia64_reload_gp (void)
2175 if (current_frame_info
.r
[reg_save_gp
])
2177 tmp
= gen_rtx_REG (DImode
, get_reg (reg_save_gp
));
2181 HOST_WIDE_INT offset
;
2184 offset
= (current_frame_info
.spill_cfa_off
2185 + current_frame_info
.spill_size
);
2186 if (frame_pointer_needed
)
2188 tmp
= hard_frame_pointer_rtx
;
2193 tmp
= stack_pointer_rtx
;
2194 offset
= current_frame_info
.total_size
- offset
;
2197 offset_r
= GEN_INT (offset
);
2198 if (satisfies_constraint_I (offset_r
))
2199 emit_insn (gen_adddi3 (pic_offset_table_rtx
, tmp
, offset_r
));
2202 emit_move_insn (pic_offset_table_rtx
, offset_r
);
2203 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
2204 pic_offset_table_rtx
, tmp
));
2207 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
2210 emit_move_insn (pic_offset_table_rtx
, tmp
);
2214 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
2215 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
2218 bool is_desc
= false;
2220 /* If we find we're calling through a register, then we're actually
2221 calling through a descriptor, so load up the values. */
2222 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
2227 /* ??? We are currently constrained to *not* use peep2, because
2228 we can legitimately change the global lifetime of the GP
2229 (in the form of killing where previously live). This is
2230 because a call through a descriptor doesn't use the previous
2231 value of the GP, while a direct call does, and we do not
2232 commit to either form until the split here.
2234 That said, this means that we lack precise life info for
2235 whether ADDR is dead after this call. This is not terribly
2236 important, since we can fix things up essentially for free
2237 with the POST_DEC below, but it's nice to not use it when we
2238 can immediately tell it's not necessary. */
2239 addr_dead_p
= ((noreturn_p
|| sibcall_p
2240 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
2242 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
2244 /* Load the code address into scratch_b. */
2245 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
2246 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2247 emit_move_insn (scratch_r
, tmp
);
2248 emit_move_insn (scratch_b
, scratch_r
);
2250 /* Load the GP address. If ADDR is not dead here, then we must
2251 revert the change made above via the POST_INCREMENT. */
2253 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
2256 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2257 emit_move_insn (pic_offset_table_rtx
, tmp
);
2264 insn
= gen_sibcall_nogp (addr
);
2266 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
2268 insn
= gen_call_nogp (addr
, retaddr
);
2269 emit_call_insn (insn
);
2271 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
2275 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2277 This differs from the generic code in that we know about the zero-extending
2278 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2279 also know that ld.acq+cmpxchg.rel equals a full barrier.
2281 The loop we want to generate looks like
2286 new_reg = cmp_reg op val;
2287 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2288 if (cmp_reg != old_reg)
2291 Note that we only do the plain load from memory once. Subsequent
2292 iterations use the value loaded by the compare-and-swap pattern. */
2295 ia64_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
2296 rtx old_dst
, rtx new_dst
, enum memmodel model
)
2298 enum machine_mode mode
= GET_MODE (mem
);
2299 rtx old_reg
, new_reg
, cmp_reg
, ar_ccv
, label
;
2300 enum insn_code icode
;
2302 /* Special case for using fetchadd. */
2303 if ((mode
== SImode
|| mode
== DImode
)
2304 && (code
== PLUS
|| code
== MINUS
)
2305 && fetchadd_operand (val
, mode
))
2308 val
= GEN_INT (-INTVAL (val
));
2311 old_dst
= gen_reg_rtx (mode
);
2315 case MEMMODEL_ACQ_REL
:
2316 case MEMMODEL_SEQ_CST
:
2317 emit_insn (gen_memory_barrier ());
2319 case MEMMODEL_RELAXED
:
2320 case MEMMODEL_ACQUIRE
:
2321 case MEMMODEL_CONSUME
:
2323 icode
= CODE_FOR_fetchadd_acq_si
;
2325 icode
= CODE_FOR_fetchadd_acq_di
;
2327 case MEMMODEL_RELEASE
:
2329 icode
= CODE_FOR_fetchadd_rel_si
;
2331 icode
= CODE_FOR_fetchadd_rel_di
;
2338 emit_insn (GEN_FCN (icode
) (old_dst
, mem
, val
));
2342 new_reg
= expand_simple_binop (mode
, PLUS
, old_dst
, val
, new_dst
,
2344 if (new_reg
!= new_dst
)
2345 emit_move_insn (new_dst
, new_reg
);
2350 /* Because of the volatile mem read, we get an ld.acq, which is the
2351 front half of the full barrier. The end half is the cmpxchg.rel.
2352 For relaxed and release memory models, we don't need this. But we
2353 also don't bother trying to prevent it either. */
2354 gcc_assert (model
== MEMMODEL_RELAXED
2355 || model
== MEMMODEL_RELEASE
2356 || MEM_VOLATILE_P (mem
));
2358 old_reg
= gen_reg_rtx (DImode
);
2359 cmp_reg
= gen_reg_rtx (DImode
);
2360 label
= gen_label_rtx ();
2364 val
= simplify_gen_subreg (DImode
, val
, mode
, 0);
2365 emit_insn (gen_extend_insn (cmp_reg
, mem
, DImode
, mode
, 1));
2368 emit_move_insn (cmp_reg
, mem
);
2372 ar_ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
2373 emit_move_insn (old_reg
, cmp_reg
);
2374 emit_move_insn (ar_ccv
, cmp_reg
);
2377 emit_move_insn (old_dst
, gen_lowpart (mode
, cmp_reg
));
2382 new_reg
= expand_simple_binop (DImode
, AND
, new_reg
, val
, NULL_RTX
,
2383 true, OPTAB_DIRECT
);
2384 new_reg
= expand_simple_unop (DImode
, code
, new_reg
, NULL_RTX
, true);
2387 new_reg
= expand_simple_binop (DImode
, code
, new_reg
, val
, NULL_RTX
,
2388 true, OPTAB_DIRECT
);
2391 new_reg
= gen_lowpart (mode
, new_reg
);
2393 emit_move_insn (new_dst
, new_reg
);
2397 case MEMMODEL_RELAXED
:
2398 case MEMMODEL_ACQUIRE
:
2399 case MEMMODEL_CONSUME
:
2402 case QImode
: icode
= CODE_FOR_cmpxchg_acq_qi
; break;
2403 case HImode
: icode
= CODE_FOR_cmpxchg_acq_hi
; break;
2404 case SImode
: icode
= CODE_FOR_cmpxchg_acq_si
; break;
2405 case DImode
: icode
= CODE_FOR_cmpxchg_acq_di
; break;
2411 case MEMMODEL_RELEASE
:
2412 case MEMMODEL_ACQ_REL
:
2413 case MEMMODEL_SEQ_CST
:
2416 case QImode
: icode
= CODE_FOR_cmpxchg_rel_qi
; break;
2417 case HImode
: icode
= CODE_FOR_cmpxchg_rel_hi
; break;
2418 case SImode
: icode
= CODE_FOR_cmpxchg_rel_si
; break;
2419 case DImode
: icode
= CODE_FOR_cmpxchg_rel_di
; break;
2429 emit_insn (GEN_FCN (icode
) (cmp_reg
, mem
, ar_ccv
, new_reg
));
2431 emit_cmp_and_jump_insns (cmp_reg
, old_reg
, NE
, NULL
, DImode
, true, label
);
2434 /* Begin the assembly file. */
2437 ia64_file_start (void)
2439 default_file_start ();
2440 emit_safe_across_calls ();
2444 emit_safe_across_calls (void)
2446 unsigned int rs
, re
;
2453 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
2457 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
2461 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
2465 fputc (',', asm_out_file
);
2467 fprintf (asm_out_file
, "p%u", rs
);
2469 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
2473 fputc ('\n', asm_out_file
);
2476 /* Globalize a declaration. */
2479 ia64_globalize_decl_name (FILE * stream
, tree decl
)
2481 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2482 tree version_attr
= lookup_attribute ("version_id", DECL_ATTRIBUTES (decl
));
2485 tree v
= TREE_VALUE (TREE_VALUE (version_attr
));
2486 const char *p
= TREE_STRING_POINTER (v
);
2487 fprintf (stream
, "\t.alias %s#, \"%s{%s}\"\n", name
, name
, p
);
2489 targetm
.asm_out
.globalize_label (stream
, name
);
2490 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2491 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "function");
2494 /* Helper function for ia64_compute_frame_size: find an appropriate general
2495 register to spill some special register to. SPECIAL_SPILL_MASK contains
2496 bits in GR0 to GR31 that have already been allocated by this routine.
2497 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2500 find_gr_spill (enum ia64_frame_regs r
, int try_locals
)
2504 if (emitted_frame_related_regs
[r
] != 0)
2506 regno
= emitted_frame_related_regs
[r
];
2507 if (regno
>= LOC_REG (0) && regno
< LOC_REG (80 - frame_pointer_needed
)
2508 && current_frame_info
.n_local_regs
< regno
- LOC_REG (0) + 1)
2509 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2510 else if (crtl
->is_leaf
2511 && regno
>= GR_REG (1) && regno
<= GR_REG (31))
2512 current_frame_info
.gr_used_mask
|= 1 << regno
;
2517 /* If this is a leaf function, first try an otherwise unused
2518 call-clobbered register. */
2521 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2522 if (! df_regs_ever_live_p (regno
)
2523 && call_used_regs
[regno
]
2524 && ! fixed_regs
[regno
]
2525 && ! global_regs
[regno
]
2526 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0
2527 && ! is_emitted (regno
))
2529 current_frame_info
.gr_used_mask
|= 1 << regno
;
2536 regno
= current_frame_info
.n_local_regs
;
2537 /* If there is a frame pointer, then we can't use loc79, because
2538 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2539 reg_name switching code in ia64_expand_prologue. */
2540 while (regno
< (80 - frame_pointer_needed
))
2541 if (! is_emitted (LOC_REG (regno
++)))
2543 current_frame_info
.n_local_regs
= regno
;
2544 return LOC_REG (regno
- 1);
2548 /* Failed to find a general register to spill to. Must use stack. */
2552 /* In order to make for nice schedules, we try to allocate every temporary
2553 to a different register. We must of course stay away from call-saved,
2554 fixed, and global registers. We must also stay away from registers
2555 allocated in current_frame_info.gr_used_mask, since those include regs
2556 used all through the prologue.
2558 Any register allocated here must be used immediately. The idea is to
2559 aid scheduling, not to solve data flow problems. */
2561 static int last_scratch_gr_reg
;
2564 next_scratch_gr_reg (void)
2568 for (i
= 0; i
< 32; ++i
)
2570 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
2571 if (call_used_regs
[regno
]
2572 && ! fixed_regs
[regno
]
2573 && ! global_regs
[regno
]
2574 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
2576 last_scratch_gr_reg
= regno
;
2581 /* There must be _something_ available. */
2585 /* Helper function for ia64_compute_frame_size, called through
2586 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2589 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2591 unsigned int regno
= REGNO (reg
);
2594 unsigned int i
, n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2595 for (i
= 0; i
< n
; ++i
)
2596 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2601 /* Returns the number of bytes offset between the frame pointer and the stack
2602 pointer for the current function. SIZE is the number of bytes of space
2603 needed for local variables. */
2606 ia64_compute_frame_size (HOST_WIDE_INT size
)
2608 HOST_WIDE_INT total_size
;
2609 HOST_WIDE_INT spill_size
= 0;
2610 HOST_WIDE_INT extra_spill_size
= 0;
2611 HOST_WIDE_INT pretend_args_size
;
2614 int spilled_gr_p
= 0;
2615 int spilled_fr_p
= 0;
2621 if (current_frame_info
.initialized
)
2624 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2625 CLEAR_HARD_REG_SET (mask
);
2627 /* Don't allocate scratches to the return register. */
2628 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2630 /* Don't allocate scratches to the EH scratch registers. */
2631 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2632 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2633 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2634 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2636 /* Static stack checking uses r2 and r3. */
2637 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
2638 current_frame_info
.gr_used_mask
|= 0xc;
2640 /* Find the size of the register stack frame. We have only 80 local
2641 registers, because we reserve 8 for the inputs and 8 for the
2644 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2645 since we'll be adjusting that down later. */
2646 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2647 for (; regno
>= LOC_REG (0); regno
--)
2648 if (df_regs_ever_live_p (regno
) && !is_emitted (regno
))
2650 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2652 /* For functions marked with the syscall_linkage attribute, we must mark
2653 all eight input registers as in use, so that locals aren't visible to
2656 if (cfun
->machine
->n_varargs
> 0
2657 || lookup_attribute ("syscall_linkage",
2658 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2659 current_frame_info
.n_input_regs
= 8;
2662 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2663 if (df_regs_ever_live_p (regno
))
2665 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2668 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2669 if (df_regs_ever_live_p (regno
))
2671 i
= regno
- OUT_REG (0) + 1;
2673 #ifndef PROFILE_HOOK
2674 /* When -p profiling, we need one output register for the mcount argument.
2675 Likewise for -a profiling for the bb_init_func argument. For -ax
2676 profiling, we need two output registers for the two bb_init_trace_func
2681 current_frame_info
.n_output_regs
= i
;
2683 /* ??? No rotating register support yet. */
2684 current_frame_info
.n_rotate_regs
= 0;
2686 /* Discover which registers need spilling, and how much room that
2687 will take. Begin with floating point and general registers,
2688 which will always wind up on the stack. */
2690 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2691 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2693 SET_HARD_REG_BIT (mask
, regno
);
2699 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2700 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2702 SET_HARD_REG_BIT (mask
, regno
);
2708 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2709 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2711 SET_HARD_REG_BIT (mask
, regno
);
2716 /* Now come all special registers that might get saved in other
2717 general registers. */
2719 if (frame_pointer_needed
)
2721 current_frame_info
.r
[reg_fp
] = find_gr_spill (reg_fp
, 1);
2722 /* If we did not get a register, then we take LOC79. This is guaranteed
2723 to be free, even if regs_ever_live is already set, because this is
2724 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2725 as we don't count loc79 above. */
2726 if (current_frame_info
.r
[reg_fp
] == 0)
2728 current_frame_info
.r
[reg_fp
] = LOC_REG (79);
2729 current_frame_info
.n_local_regs
= LOC_REG (79) - LOC_REG (0) + 1;
2733 if (! crtl
->is_leaf
)
2735 /* Emit a save of BR0 if we call other functions. Do this even
2736 if this function doesn't return, as EH depends on this to be
2737 able to unwind the stack. */
2738 SET_HARD_REG_BIT (mask
, BR_REG (0));
2740 current_frame_info
.r
[reg_save_b0
] = find_gr_spill (reg_save_b0
, 1);
2741 if (current_frame_info
.r
[reg_save_b0
] == 0)
2743 extra_spill_size
+= 8;
2747 /* Similarly for ar.pfs. */
2748 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2749 current_frame_info
.r
[reg_save_ar_pfs
] = find_gr_spill (reg_save_ar_pfs
, 1);
2750 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2752 extra_spill_size
+= 8;
2756 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2757 registers are clobbered, so we fall back to the stack. */
2758 current_frame_info
.r
[reg_save_gp
]
2759 = (cfun
->calls_setjmp
? 0 : find_gr_spill (reg_save_gp
, 1));
2760 if (current_frame_info
.r
[reg_save_gp
] == 0)
2762 SET_HARD_REG_BIT (mask
, GR_REG (1));
2769 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs
[BR_REG (0)])
2771 SET_HARD_REG_BIT (mask
, BR_REG (0));
2772 extra_spill_size
+= 8;
2776 if (df_regs_ever_live_p (AR_PFS_REGNUM
))
2778 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2779 current_frame_info
.r
[reg_save_ar_pfs
]
2780 = find_gr_spill (reg_save_ar_pfs
, 1);
2781 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2783 extra_spill_size
+= 8;
2789 /* Unwind descriptor hackery: things are most efficient if we allocate
2790 consecutive GR save registers for RP, PFS, FP in that order. However,
2791 it is absolutely critical that FP get the only hard register that's
2792 guaranteed to be free, so we allocated it first. If all three did
2793 happen to be allocated hard regs, and are consecutive, rearrange them
2794 into the preferred order now.
2796 If we have already emitted code for any of those registers,
2797 then it's already too late to change. */
2798 min_regno
= MIN (current_frame_info
.r
[reg_fp
],
2799 MIN (current_frame_info
.r
[reg_save_b0
],
2800 current_frame_info
.r
[reg_save_ar_pfs
]));
2801 max_regno
= MAX (current_frame_info
.r
[reg_fp
],
2802 MAX (current_frame_info
.r
[reg_save_b0
],
2803 current_frame_info
.r
[reg_save_ar_pfs
]));
2805 && min_regno
+ 2 == max_regno
2806 && (current_frame_info
.r
[reg_fp
] == min_regno
+ 1
2807 || current_frame_info
.r
[reg_save_b0
] == min_regno
+ 1
2808 || current_frame_info
.r
[reg_save_ar_pfs
] == min_regno
+ 1)
2809 && (emitted_frame_related_regs
[reg_save_b0
] == 0
2810 || emitted_frame_related_regs
[reg_save_b0
] == min_regno
)
2811 && (emitted_frame_related_regs
[reg_save_ar_pfs
] == 0
2812 || emitted_frame_related_regs
[reg_save_ar_pfs
] == min_regno
+ 1)
2813 && (emitted_frame_related_regs
[reg_fp
] == 0
2814 || emitted_frame_related_regs
[reg_fp
] == min_regno
+ 2))
2816 current_frame_info
.r
[reg_save_b0
] = min_regno
;
2817 current_frame_info
.r
[reg_save_ar_pfs
] = min_regno
+ 1;
2818 current_frame_info
.r
[reg_fp
] = min_regno
+ 2;
2821 /* See if we need to store the predicate register block. */
2822 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2823 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2825 if (regno
<= PR_REG (63))
2827 SET_HARD_REG_BIT (mask
, PR_REG (0));
2828 current_frame_info
.r
[reg_save_pr
] = find_gr_spill (reg_save_pr
, 1);
2829 if (current_frame_info
.r
[reg_save_pr
] == 0)
2831 extra_spill_size
+= 8;
2835 /* ??? Mark them all as used so that register renaming and such
2836 are free to use them. */
2837 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2838 df_set_regs_ever_live (regno
, true);
2841 /* If we're forced to use st8.spill, we're forced to save and restore
2842 ar.unat as well. The check for existing liveness allows inline asm
2843 to touch ar.unat. */
2844 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2845 || df_regs_ever_live_p (AR_UNAT_REGNUM
))
2847 df_set_regs_ever_live (AR_UNAT_REGNUM
, true);
2848 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2849 current_frame_info
.r
[reg_save_ar_unat
]
2850 = find_gr_spill (reg_save_ar_unat
, spill_size
== 0);
2851 if (current_frame_info
.r
[reg_save_ar_unat
] == 0)
2853 extra_spill_size
+= 8;
2858 if (df_regs_ever_live_p (AR_LC_REGNUM
))
2860 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2861 current_frame_info
.r
[reg_save_ar_lc
]
2862 = find_gr_spill (reg_save_ar_lc
, spill_size
== 0);
2863 if (current_frame_info
.r
[reg_save_ar_lc
] == 0)
2865 extra_spill_size
+= 8;
2870 /* If we have an odd number of words of pretend arguments written to
2871 the stack, then the FR save area will be unaligned. We round the
2872 size of this area up to keep things 16 byte aligned. */
2874 pretend_args_size
= IA64_STACK_ALIGN (crtl
->args
.pretend_args_size
);
2876 pretend_args_size
= crtl
->args
.pretend_args_size
;
2878 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2879 + crtl
->outgoing_args_size
);
2880 total_size
= IA64_STACK_ALIGN (total_size
);
2882 /* We always use the 16-byte scratch area provided by the caller, but
2883 if we are a leaf function, there's no one to which we need to provide
2884 a scratch area. However, if the function allocates dynamic stack space,
2885 the dynamic offset is computed early and contains STACK_POINTER_OFFSET,
2886 so we need to cope. */
2887 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
2888 total_size
= MAX (0, total_size
- 16);
2890 current_frame_info
.total_size
= total_size
;
2891 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2892 current_frame_info
.spill_size
= spill_size
;
2893 current_frame_info
.extra_spill_size
= extra_spill_size
;
2894 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2895 current_frame_info
.n_spilled
= n_spilled
;
2896 current_frame_info
.initialized
= reload_completed
;
2899 /* Worker function for TARGET_CAN_ELIMINATE. */
2902 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2904 return (to
== BR_REG (0) ? crtl
->is_leaf
: true);
2907 /* Compute the initial difference between the specified pair of registers. */
2910 ia64_initial_elimination_offset (int from
, int to
)
2912 HOST_WIDE_INT offset
;
2914 ia64_compute_frame_size (get_frame_size ());
2917 case FRAME_POINTER_REGNUM
:
2920 case HARD_FRAME_POINTER_REGNUM
:
2921 offset
= -current_frame_info
.total_size
;
2922 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2923 offset
+= 16 + crtl
->outgoing_args_size
;
2926 case STACK_POINTER_REGNUM
:
2928 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2929 offset
+= 16 + crtl
->outgoing_args_size
;
2937 case ARG_POINTER_REGNUM
:
2938 /* Arguments start above the 16 byte save area, unless stdarg
2939 in which case we store through the 16 byte save area. */
2942 case HARD_FRAME_POINTER_REGNUM
:
2943 offset
= 16 - crtl
->args
.pretend_args_size
;
2946 case STACK_POINTER_REGNUM
:
2947 offset
= (current_frame_info
.total_size
2948 + 16 - crtl
->args
.pretend_args_size
);
2963 /* If there are more than a trivial number of register spills, we use
2964 two interleaved iterators so that we can get two memory references
2967 In order to simplify things in the prologue and epilogue expanders,
2968 we use helper functions to fix up the memory references after the
2969 fact with the appropriate offsets to a POST_MODIFY memory mode.
2970 The following data structure tracks the state of the two iterators
2971 while insns are being emitted. */
2973 struct spill_fill_data
2975 rtx init_after
; /* point at which to emit initializations */
2976 rtx init_reg
[2]; /* initial base register */
2977 rtx iter_reg
[2]; /* the iterator registers */
2978 rtx
*prev_addr
[2]; /* address of last memory use */
2979 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2980 HOST_WIDE_INT prev_off
[2]; /* last offset */
2981 int n_iter
; /* number of iterators in use */
2982 int next_iter
; /* next iterator to use */
2983 unsigned int save_gr_used_mask
;
2986 static struct spill_fill_data spill_fill_data
;
2989 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2993 spill_fill_data
.init_after
= get_last_insn ();
2994 spill_fill_data
.init_reg
[0] = init_reg
;
2995 spill_fill_data
.init_reg
[1] = init_reg
;
2996 spill_fill_data
.prev_addr
[0] = NULL
;
2997 spill_fill_data
.prev_addr
[1] = NULL
;
2998 spill_fill_data
.prev_insn
[0] = NULL
;
2999 spill_fill_data
.prev_insn
[1] = NULL
;
3000 spill_fill_data
.prev_off
[0] = cfa_off
;
3001 spill_fill_data
.prev_off
[1] = cfa_off
;
3002 spill_fill_data
.next_iter
= 0;
3003 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
3005 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
3006 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
3008 int regno
= next_scratch_gr_reg ();
3009 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
3010 current_frame_info
.gr_used_mask
|= 1 << regno
;
3015 finish_spill_pointers (void)
3017 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
3021 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
3023 int iter
= spill_fill_data
.next_iter
;
3024 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
3025 rtx disp_rtx
= GEN_INT (disp
);
3028 if (spill_fill_data
.prev_addr
[iter
])
3030 if (satisfies_constraint_N (disp_rtx
))
3032 *spill_fill_data
.prev_addr
[iter
]
3033 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
3034 gen_rtx_PLUS (DImode
,
3035 spill_fill_data
.iter_reg
[iter
],
3037 add_reg_note (spill_fill_data
.prev_insn
[iter
],
3038 REG_INC
, spill_fill_data
.iter_reg
[iter
]);
3042 /* ??? Could use register post_modify for loads. */
3043 if (!satisfies_constraint_I (disp_rtx
))
3045 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3046 emit_move_insn (tmp
, disp_rtx
);
3049 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3050 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
3053 /* Micro-optimization: if we've created a frame pointer, it's at
3054 CFA 0, which may allow the real iterator to be initialized lower,
3055 slightly increasing parallelism. Also, if there are few saves
3056 it may eliminate the iterator entirely. */
3058 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
3059 && frame_pointer_needed
)
3061 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
3062 set_mem_alias_set (mem
, get_varargs_alias_set ());
3070 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
3071 spill_fill_data
.init_reg
[iter
]);
3076 if (!satisfies_constraint_I (disp_rtx
))
3078 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3079 emit_move_insn (tmp
, disp_rtx
);
3083 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3084 spill_fill_data
.init_reg
[iter
],
3091 /* Careful for being the first insn in a sequence. */
3092 if (spill_fill_data
.init_after
)
3093 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
3096 rtx first
= get_insns ();
3098 insn
= emit_insn_before (seq
, first
);
3100 insn
= emit_insn (seq
);
3102 spill_fill_data
.init_after
= insn
;
3105 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
3107 /* ??? Not all of the spills are for varargs, but some of them are.
3108 The rest of the spills belong in an alias set of their own. But
3109 it doesn't actually hurt to include them here. */
3110 set_mem_alias_set (mem
, get_varargs_alias_set ());
3112 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
3113 spill_fill_data
.prev_off
[iter
] = cfa_off
;
3115 if (++iter
>= spill_fill_data
.n_iter
)
3117 spill_fill_data
.next_iter
= iter
;
3123 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
3126 int iter
= spill_fill_data
.next_iter
;
3129 mem
= spill_restore_mem (reg
, cfa_off
);
3130 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
3131 spill_fill_data
.prev_insn
[iter
] = insn
;
3138 RTX_FRAME_RELATED_P (insn
) = 1;
3140 /* Don't even pretend that the unwind code can intuit its way
3141 through a pair of interleaved post_modify iterators. Just
3142 provide the correct answer. */
3144 if (frame_pointer_needed
)
3146 base
= hard_frame_pointer_rtx
;
3151 base
= stack_pointer_rtx
;
3152 off
= current_frame_info
.total_size
- cfa_off
;
3155 add_reg_note (insn
, REG_CFA_OFFSET
,
3156 gen_rtx_SET (VOIDmode
,
3157 gen_rtx_MEM (GET_MODE (reg
),
3158 plus_constant (Pmode
,
3165 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
3167 int iter
= spill_fill_data
.next_iter
;
3170 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
3171 GEN_INT (cfa_off
)));
3172 spill_fill_data
.prev_insn
[iter
] = insn
;
3175 /* Wrapper functions that discards the CONST_INT spill offset. These
3176 exist so that we can give gr_spill/gr_fill the offset they need and
3177 use a consistent function interface. */
3180 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3182 return gen_movdi (dest
, src
);
3186 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3188 return gen_fr_spill (dest
, src
);
3192 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3194 return gen_fr_restore (dest
, src
);
3197 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3199 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3200 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3202 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3203 inclusive. These are offsets from the current stack pointer. SOL is the
3204 size of local registers. ??? This clobbers r2 and r3. */
3207 ia64_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
, int sol
)
3209 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3210 of the Register Stack Engine. We also need to probe it after checking
3211 that the 2 stacks don't overlap. */
3212 const int bs_size
= BACKING_STORE_SIZE (sol
);
3213 rtx r2
= gen_rtx_REG (Pmode
, GR_REG (2));
3214 rtx r3
= gen_rtx_REG (Pmode
, GR_REG (3));
3216 /* Detect collision of the 2 stacks if necessary. */
3217 if (bs_size
> 0 || size
> 0)
3219 rtx p6
= gen_rtx_REG (BImode
, PR_REG (6));
3221 emit_insn (gen_bsp_value (r3
));
3222 emit_move_insn (r2
, GEN_INT (-(first
+ size
)));
3224 /* Compare current value of BSP and SP registers. */
3225 emit_insn (gen_rtx_SET (VOIDmode
, p6
,
3226 gen_rtx_fmt_ee (LTU
, BImode
,
3227 r3
, stack_pointer_rtx
)));
3229 /* Compute the address of the probe for the Backing Store (which grows
3230 towards higher addresses). We probe only at the first offset of
3231 the next page because some OS (eg Linux/ia64) only extend the
3232 backing store when this specific address is hit (but generate a SEGV
3233 on other address). Page size is the worst case (4KB). The reserve
3234 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3235 Also compute the address of the last probe for the memory stack
3236 (which grows towards lower addresses). */
3237 emit_insn (gen_rtx_SET (VOIDmode
, r3
, plus_constant (Pmode
, r3
, 4095)));
3238 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3239 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3241 /* Compare them and raise SEGV if the former has topped the latter. */
3242 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3243 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
,
3245 gen_rtx_SET (VOIDmode
, p6
,
3246 gen_rtx_fmt_ee (GEU
, BImode
,
3248 emit_insn (gen_rtx_SET (VOIDmode
,
3249 gen_rtx_ZERO_EXTRACT (DImode
, r3
, GEN_INT (12),
3252 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3253 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
,
3255 gen_rtx_TRAP_IF (VOIDmode
, const1_rtx
,
3259 /* Probe the Backing Store if necessary. */
3261 emit_stack_probe (r3
);
3263 /* Probe the memory stack if necessary. */
3267 /* See if we have a constant small number of probes to generate. If so,
3268 that's the easy case. */
3269 else if (size
<= PROBE_INTERVAL
)
3270 emit_stack_probe (r2
);
3272 /* The run-time loop is made up of 8 insns in the generic case while this
3273 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3274 else if (size
<= 4 * PROBE_INTERVAL
)
3278 emit_move_insn (r2
, GEN_INT (-(first
+ PROBE_INTERVAL
)));
3279 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3280 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3281 emit_stack_probe (r2
);
3283 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3284 it exceeds SIZE. If only two probes are needed, this will not
3285 generate any code. Then probe at FIRST + SIZE. */
3286 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
3288 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3289 plus_constant (Pmode
, r2
, -PROBE_INTERVAL
)));
3290 emit_stack_probe (r2
);
3293 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3294 plus_constant (Pmode
, r2
,
3295 (i
- PROBE_INTERVAL
) - size
)));
3296 emit_stack_probe (r2
);
3299 /* Otherwise, do the same as above, but in a loop. Note that we must be
3300 extra careful with variables wrapping around because we might be at
3301 the very top (or the very bottom) of the address space and we have
3302 to be able to handle this case properly; in particular, we use an
3303 equality test for the loop condition. */
3306 HOST_WIDE_INT rounded_size
;
3308 emit_move_insn (r2
, GEN_INT (-first
));
3311 /* Step 1: round SIZE to the previous multiple of the interval. */
3313 rounded_size
= size
& -PROBE_INTERVAL
;
3316 /* Step 2: compute initial and final value of the loop counter. */
3318 /* TEST_ADDR = SP + FIRST. */
3319 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3320 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3322 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3323 if (rounded_size
> (1 << 21))
3325 emit_move_insn (r3
, GEN_INT (-rounded_size
));
3326 emit_insn (gen_rtx_SET (VOIDmode
, r3
, gen_rtx_PLUS (Pmode
, r2
, r3
)));
3329 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
3330 gen_rtx_PLUS (Pmode
, r2
,
3331 GEN_INT (-rounded_size
))));
3336 while (TEST_ADDR != LAST_ADDR)
3338 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3342 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3343 until it is equal to ROUNDED_SIZE. */
3345 emit_insn (gen_probe_stack_range (r2
, r2
, r3
));
3348 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3349 that SIZE is equal to ROUNDED_SIZE. */
3351 /* TEMP = SIZE - ROUNDED_SIZE. */
3352 if (size
!= rounded_size
)
3354 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3355 plus_constant (Pmode
, r2
,
3356 rounded_size
- size
)));
3357 emit_stack_probe (r2
);
3361 /* Make sure nothing is scheduled before we are done. */
3362 emit_insn (gen_blockage ());
3365 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3366 absolute addresses. */
3369 output_probe_stack_range (rtx reg1
, rtx reg2
)
3371 static int labelno
= 0;
3372 char loop_lab
[32], end_lab
[32];
3375 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
3376 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
3378 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
3380 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3383 xops
[2] = gen_rtx_REG (BImode
, PR_REG (6));
3384 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops
);
3385 fprintf (asm_out_file
, "\t(%s) br.cond.dpnt ", reg_names
[REGNO (xops
[2])]);
3386 assemble_name_raw (asm_out_file
, end_lab
);
3387 fputc ('\n', asm_out_file
);
3389 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3390 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
3391 output_asm_insn ("addl %0 = %1, %0", xops
);
3392 fputs ("\t;;\n", asm_out_file
);
3394 /* Probe at TEST_ADDR and branch. */
3395 output_asm_insn ("probe.w.fault %0, 0", xops
);
3396 fprintf (asm_out_file
, "\tbr ");
3397 assemble_name_raw (asm_out_file
, loop_lab
);
3398 fputc ('\n', asm_out_file
);
3400 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
3405 /* Called after register allocation to add any instructions needed for the
3406 prologue. Using a prologue insn is favored compared to putting all of the
3407 instructions in output_function_prologue(), since it allows the scheduler
3408 to intermix instructions with the saves of the caller saved registers. In
3409 some cases, it might be necessary to emit a barrier instruction as the last
3410 insn to prevent such scheduling.
3412 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3413 so that the debug info generation code can handle them properly.
3415 The register save area is laid out like so:
3417 [ varargs spill area ]
3418 [ fr register spill area ]
3419 [ br register spill area ]
3420 [ ar register spill area ]
3421 [ pr register spill area ]
3422 [ gr register spill area ] */
3424 /* ??? Get inefficient code when the frame size is larger than can fit in an
3425 adds instruction. */
3428 ia64_expand_prologue (void)
3430 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
3431 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
3434 ia64_compute_frame_size (get_frame_size ());
3435 last_scratch_gr_reg
= 15;
3437 if (flag_stack_usage_info
)
3438 current_function_static_stack_size
= current_frame_info
.total_size
;
3440 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
3441 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
,
3442 current_frame_info
.total_size
,
3443 current_frame_info
.n_input_regs
3444 + current_frame_info
.n_local_regs
);
3448 fprintf (dump_file
, "ia64 frame related registers "
3449 "recorded in current_frame_info.r[]:\n");
3450 #define PRINTREG(a) if (current_frame_info.r[a]) \
3451 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3453 PRINTREG(reg_save_b0
);
3454 PRINTREG(reg_save_pr
);
3455 PRINTREG(reg_save_ar_pfs
);
3456 PRINTREG(reg_save_ar_unat
);
3457 PRINTREG(reg_save_ar_lc
);
3458 PRINTREG(reg_save_gp
);
3462 /* If there is no epilogue, then we don't need some prologue insns.
3463 We need to avoid emitting the dead prologue insns, because flow
3464 will complain about them. */
3470 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
3471 if ((e
->flags
& EDGE_FAKE
) == 0
3472 && (e
->flags
& EDGE_FALLTHRU
) != 0)
3474 epilogue_p
= (e
!= NULL
);
3479 /* Set the local, input, and output register names. We need to do this
3480 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3481 half. If we use in/loc/out register names, then we get assembler errors
3482 in crtn.S because there is no alloc insn or regstk directive in there. */
3483 if (! TARGET_REG_NAMES
)
3485 int inputs
= current_frame_info
.n_input_regs
;
3486 int locals
= current_frame_info
.n_local_regs
;
3487 int outputs
= current_frame_info
.n_output_regs
;
3489 for (i
= 0; i
< inputs
; i
++)
3490 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
3491 for (i
= 0; i
< locals
; i
++)
3492 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
3493 for (i
= 0; i
< outputs
; i
++)
3494 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
3497 /* Set the frame pointer register name. The regnum is logically loc79,
3498 but of course we'll not have allocated that many locals. Rather than
3499 worrying about renumbering the existing rtxs, we adjust the name. */
3500 /* ??? This code means that we can never use one local register when
3501 there is a frame pointer. loc79 gets wasted in this case, as it is
3502 renamed to a register that will never be used. See also the try_locals
3503 code in find_gr_spill. */
3504 if (current_frame_info
.r
[reg_fp
])
3506 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3507 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3508 = reg_names
[current_frame_info
.r
[reg_fp
]];
3509 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
3512 /* We don't need an alloc instruction if we've used no outputs or locals. */
3513 if (current_frame_info
.n_local_regs
== 0
3514 && current_frame_info
.n_output_regs
== 0
3515 && current_frame_info
.n_input_regs
<= crtl
->args
.info
.int_regs
3516 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3518 /* If there is no alloc, but there are input registers used, then we
3519 need a .regstk directive. */
3520 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
3521 ar_pfs_save_reg
= NULL_RTX
;
3525 current_frame_info
.need_regstk
= 0;
3527 if (current_frame_info
.r
[reg_save_ar_pfs
])
3529 regno
= current_frame_info
.r
[reg_save_ar_pfs
];
3530 reg_emitted (reg_save_ar_pfs
);
3533 regno
= next_scratch_gr_reg ();
3534 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
3536 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
3537 GEN_INT (current_frame_info
.n_input_regs
),
3538 GEN_INT (current_frame_info
.n_local_regs
),
3539 GEN_INT (current_frame_info
.n_output_regs
),
3540 GEN_INT (current_frame_info
.n_rotate_regs
)));
3541 if (current_frame_info
.r
[reg_save_ar_pfs
])
3543 RTX_FRAME_RELATED_P (insn
) = 1;
3544 add_reg_note (insn
, REG_CFA_REGISTER
,
3545 gen_rtx_SET (VOIDmode
,
3547 gen_rtx_REG (DImode
, AR_PFS_REGNUM
)));
3551 /* Set up frame pointer, stack pointer, and spill iterators. */
3553 n_varargs
= cfun
->machine
->n_varargs
;
3554 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
3555 stack_pointer_rtx
, 0);
3557 if (frame_pointer_needed
)
3559 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3560 RTX_FRAME_RELATED_P (insn
) = 1;
3562 /* Force the unwind info to recognize this as defining a new CFA,
3563 rather than some temp register setup. */
3564 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL_RTX
);
3567 if (current_frame_info
.total_size
!= 0)
3569 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
3572 if (satisfies_constraint_I (frame_size_rtx
))
3573 offset
= frame_size_rtx
;
3576 regno
= next_scratch_gr_reg ();
3577 offset
= gen_rtx_REG (DImode
, regno
);
3578 emit_move_insn (offset
, frame_size_rtx
);
3581 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
3582 stack_pointer_rtx
, offset
));
3584 if (! frame_pointer_needed
)
3586 RTX_FRAME_RELATED_P (insn
) = 1;
3587 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3588 gen_rtx_SET (VOIDmode
,
3590 gen_rtx_PLUS (DImode
,
3595 /* ??? At this point we must generate a magic insn that appears to
3596 modify the stack pointer, the frame pointer, and all spill
3597 iterators. This would allow the most scheduling freedom. For
3598 now, just hard stop. */
3599 emit_insn (gen_blockage ());
3602 /* Must copy out ar.unat before doing any integer spills. */
3603 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3605 if (current_frame_info
.r
[reg_save_ar_unat
])
3608 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3609 reg_emitted (reg_save_ar_unat
);
3613 alt_regno
= next_scratch_gr_reg ();
3614 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3615 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3618 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3619 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
3620 if (current_frame_info
.r
[reg_save_ar_unat
])
3622 RTX_FRAME_RELATED_P (insn
) = 1;
3623 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3626 /* Even if we're not going to generate an epilogue, we still
3627 need to save the register so that EH works. */
3628 if (! epilogue_p
&& current_frame_info
.r
[reg_save_ar_unat
])
3629 emit_insn (gen_prologue_use (ar_unat_save_reg
));
3632 ar_unat_save_reg
= NULL_RTX
;
3634 /* Spill all varargs registers. Do this before spilling any GR registers,
3635 since we want the UNAT bits for the GR registers to override the UNAT
3636 bits from varargs, which we don't care about. */
3639 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
3641 reg
= gen_rtx_REG (DImode
, regno
);
3642 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
3645 /* Locate the bottom of the register save area. */
3646 cfa_off
= (current_frame_info
.spill_cfa_off
3647 + current_frame_info
.spill_size
3648 + current_frame_info
.extra_spill_size
);
3650 /* Save the predicate register block either in a register or in memory. */
3651 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3653 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3654 if (current_frame_info
.r
[reg_save_pr
] != 0)
3656 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3657 reg_emitted (reg_save_pr
);
3658 insn
= emit_move_insn (alt_reg
, reg
);
3660 /* ??? Denote pr spill/fill by a DImode move that modifies all
3661 64 hard registers. */
3662 RTX_FRAME_RELATED_P (insn
) = 1;
3663 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3665 /* Even if we're not going to generate an epilogue, we still
3666 need to save the register so that EH works. */
3668 emit_insn (gen_prologue_use (alt_reg
));
3672 alt_regno
= next_scratch_gr_reg ();
3673 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3674 insn
= emit_move_insn (alt_reg
, reg
);
3675 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3680 /* Handle AR regs in numerical order. All of them get special handling. */
3681 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
3682 && current_frame_info
.r
[reg_save_ar_unat
] == 0)
3684 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3685 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
3689 /* The alloc insn already copied ar.pfs into a general register. The
3690 only thing we have to do now is copy that register to a stack slot
3691 if we'd not allocated a local register for the job. */
3692 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
3693 && current_frame_info
.r
[reg_save_ar_pfs
] == 0)
3695 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3696 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
3700 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3702 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3703 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3705 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3706 reg_emitted (reg_save_ar_lc
);
3707 insn
= emit_move_insn (alt_reg
, reg
);
3708 RTX_FRAME_RELATED_P (insn
) = 1;
3709 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3711 /* Even if we're not going to generate an epilogue, we still
3712 need to save the register so that EH works. */
3714 emit_insn (gen_prologue_use (alt_reg
));
3718 alt_regno
= next_scratch_gr_reg ();
3719 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3720 emit_move_insn (alt_reg
, reg
);
3721 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3726 /* Save the return pointer. */
3727 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3729 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3730 if (current_frame_info
.r
[reg_save_b0
] != 0)
3732 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3733 reg_emitted (reg_save_b0
);
3734 insn
= emit_move_insn (alt_reg
, reg
);
3735 RTX_FRAME_RELATED_P (insn
) = 1;
3736 add_reg_note (insn
, REG_CFA_REGISTER
,
3737 gen_rtx_SET (VOIDmode
, alt_reg
, pc_rtx
));
3739 /* Even if we're not going to generate an epilogue, we still
3740 need to save the register so that EH works. */
3742 emit_insn (gen_prologue_use (alt_reg
));
3746 alt_regno
= next_scratch_gr_reg ();
3747 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3748 emit_move_insn (alt_reg
, reg
);
3749 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3754 if (current_frame_info
.r
[reg_save_gp
])
3756 reg_emitted (reg_save_gp
);
3757 insn
= emit_move_insn (gen_rtx_REG (DImode
,
3758 current_frame_info
.r
[reg_save_gp
]),
3759 pic_offset_table_rtx
);
3762 /* We should now be at the base of the gr/br/fr spill area. */
3763 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3764 + current_frame_info
.spill_size
));
3766 /* Spill all general registers. */
3767 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3768 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3770 reg
= gen_rtx_REG (DImode
, regno
);
3771 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
3775 /* Spill the rest of the BR registers. */
3776 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3777 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3779 alt_regno
= next_scratch_gr_reg ();
3780 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3781 reg
= gen_rtx_REG (DImode
, regno
);
3782 emit_move_insn (alt_reg
, reg
);
3783 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3787 /* Align the frame and spill all FR registers. */
3788 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3789 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3791 gcc_assert (!(cfa_off
& 15));
3792 reg
= gen_rtx_REG (XFmode
, regno
);
3793 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
3797 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3799 finish_spill_pointers ();
3802 /* Output the textual info surrounding the prologue. */
3805 ia64_start_function (FILE *file
, const char *fnname
,
3806 tree decl ATTRIBUTE_UNUSED
)
3808 #if TARGET_ABI_OPEN_VMS
3809 vms_start_function (fnname
);
3812 fputs ("\t.proc ", file
);
3813 assemble_name (file
, fnname
);
3815 ASM_OUTPUT_LABEL (file
, fnname
);
3818 /* Called after register allocation to add any instructions needed for the
3819 epilogue. Using an epilogue insn is favored compared to putting all of the
3820 instructions in output_function_prologue(), since it allows the scheduler
3821 to intermix instructions with the saves of the caller saved registers. In
3822 some cases, it might be necessary to emit a barrier instruction as the last
3823 insn to prevent such scheduling. */
3826 ia64_expand_epilogue (int sibcall_p
)
3828 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
3829 int regno
, alt_regno
, cfa_off
;
3831 ia64_compute_frame_size (get_frame_size ());
3833 /* If there is a frame pointer, then we use it instead of the stack
3834 pointer, so that the stack pointer does not need to be valid when
3835 the epilogue starts. See EXIT_IGNORE_STACK. */
3836 if (frame_pointer_needed
)
3837 setup_spill_pointers (current_frame_info
.n_spilled
,
3838 hard_frame_pointer_rtx
, 0);
3840 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
3841 current_frame_info
.total_size
);
3843 if (current_frame_info
.total_size
!= 0)
3845 /* ??? At this point we must generate a magic insn that appears to
3846 modify the spill iterators and the frame pointer. This would
3847 allow the most scheduling freedom. For now, just hard stop. */
3848 emit_insn (gen_blockage ());
3851 /* Locate the bottom of the register save area. */
3852 cfa_off
= (current_frame_info
.spill_cfa_off
3853 + current_frame_info
.spill_size
3854 + current_frame_info
.extra_spill_size
);
3856 /* Restore the predicate registers. */
3857 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3859 if (current_frame_info
.r
[reg_save_pr
] != 0)
3861 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3862 reg_emitted (reg_save_pr
);
3866 alt_regno
= next_scratch_gr_reg ();
3867 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3868 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3871 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3872 emit_move_insn (reg
, alt_reg
);
3875 /* Restore the application registers. */
3877 /* Load the saved unat from the stack, but do not restore it until
3878 after the GRs have been restored. */
3879 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3881 if (current_frame_info
.r
[reg_save_ar_unat
] != 0)
3884 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3885 reg_emitted (reg_save_ar_unat
);
3889 alt_regno
= next_scratch_gr_reg ();
3890 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3891 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3892 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3897 ar_unat_save_reg
= NULL_RTX
;
3899 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0)
3901 reg_emitted (reg_save_ar_pfs
);
3902 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_pfs
]);
3903 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3904 emit_move_insn (reg
, alt_reg
);
3906 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3908 alt_regno
= next_scratch_gr_reg ();
3909 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3910 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3912 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3913 emit_move_insn (reg
, alt_reg
);
3916 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3918 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3920 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3921 reg_emitted (reg_save_ar_lc
);
3925 alt_regno
= next_scratch_gr_reg ();
3926 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3927 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3930 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3931 emit_move_insn (reg
, alt_reg
);
3934 /* Restore the return pointer. */
3935 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3937 if (current_frame_info
.r
[reg_save_b0
] != 0)
3939 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3940 reg_emitted (reg_save_b0
);
3944 alt_regno
= next_scratch_gr_reg ();
3945 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3946 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3949 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3950 emit_move_insn (reg
, alt_reg
);
3953 /* We should now be at the base of the gr/br/fr spill area. */
3954 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3955 + current_frame_info
.spill_size
));
3957 /* The GP may be stored on the stack in the prologue, but it's
3958 never restored in the epilogue. Skip the stack slot. */
3959 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3962 /* Restore all general registers. */
3963 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3964 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3966 reg
= gen_rtx_REG (DImode
, regno
);
3967 do_restore (gen_gr_restore
, reg
, cfa_off
);
3971 /* Restore the branch registers. */
3972 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3973 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3975 alt_regno
= next_scratch_gr_reg ();
3976 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3977 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3979 reg
= gen_rtx_REG (DImode
, regno
);
3980 emit_move_insn (reg
, alt_reg
);
3983 /* Restore floating point registers. */
3984 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3985 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3987 gcc_assert (!(cfa_off
& 15));
3988 reg
= gen_rtx_REG (XFmode
, regno
);
3989 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
3993 /* Restore ar.unat for real. */
3994 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3996 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3997 emit_move_insn (reg
, ar_unat_save_reg
);
4000 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
4002 finish_spill_pointers ();
4004 if (current_frame_info
.total_size
4005 || cfun
->machine
->ia64_eh_epilogue_sp
4006 || frame_pointer_needed
)
4008 /* ??? At this point we must generate a magic insn that appears to
4009 modify the spill iterators, the stack pointer, and the frame
4010 pointer. This would allow the most scheduling freedom. For now,
4012 emit_insn (gen_blockage ());
4015 if (cfun
->machine
->ia64_eh_epilogue_sp
)
4016 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
4017 else if (frame_pointer_needed
)
4019 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
4020 RTX_FRAME_RELATED_P (insn
) = 1;
4021 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL
);
4023 else if (current_frame_info
.total_size
)
4025 rtx offset
, frame_size_rtx
;
4027 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
4028 if (satisfies_constraint_I (frame_size_rtx
))
4029 offset
= frame_size_rtx
;
4032 regno
= next_scratch_gr_reg ();
4033 offset
= gen_rtx_REG (DImode
, regno
);
4034 emit_move_insn (offset
, frame_size_rtx
);
4037 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
4040 RTX_FRAME_RELATED_P (insn
) = 1;
4041 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4042 gen_rtx_SET (VOIDmode
,
4044 gen_rtx_PLUS (DImode
,
4049 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
4050 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
4053 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
4056 int fp
= GR_REG (2);
4057 /* We need a throw away register here, r0 and r1 are reserved,
4058 so r2 is the first available call clobbered register. If
4059 there was a frame_pointer register, we may have swapped the
4060 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4061 sure we're using the string "r2" when emitting the register
4062 name for the assembler. */
4063 if (current_frame_info
.r
[reg_fp
]
4064 && current_frame_info
.r
[reg_fp
] == GR_REG (2))
4065 fp
= HARD_FRAME_POINTER_REGNUM
;
4067 /* We must emit an alloc to force the input registers to become output
4068 registers. Otherwise, if the callee tries to pass its parameters
4069 through to another call without an intervening alloc, then these
4071 /* ??? We don't need to preserve all input registers. We only need to
4072 preserve those input registers used as arguments to the sibling call.
4073 It is unclear how to compute that number here. */
4074 if (current_frame_info
.n_input_regs
!= 0)
4076 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
4078 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
4079 const0_rtx
, const0_rtx
,
4080 n_inputs
, const0_rtx
));
4081 RTX_FRAME_RELATED_P (insn
) = 1;
4083 /* ??? We need to mark the alloc as frame-related so that it gets
4084 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4085 But there's nothing dwarf2 related to be done wrt the register
4086 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4087 the empty parallel means dwarf2out will not see anything. */
4088 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4089 gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (0)));
4094 /* Return 1 if br.ret can do all the work required to return from a
4098 ia64_direct_return (void)
4100 if (reload_completed
&& ! frame_pointer_needed
)
4102 ia64_compute_frame_size (get_frame_size ());
4104 return (current_frame_info
.total_size
== 0
4105 && current_frame_info
.n_spilled
== 0
4106 && current_frame_info
.r
[reg_save_b0
] == 0
4107 && current_frame_info
.r
[reg_save_pr
] == 0
4108 && current_frame_info
.r
[reg_save_ar_pfs
] == 0
4109 && current_frame_info
.r
[reg_save_ar_unat
] == 0
4110 && current_frame_info
.r
[reg_save_ar_lc
] == 0);
4115 /* Return the magic cookie that we use to hold the return address
4116 during early compilation. */
4119 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
4123 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
4126 /* Split this value after reload, now that we know where the return
4127 address is saved. */
4130 ia64_split_return_addr_rtx (rtx dest
)
4134 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
4136 if (current_frame_info
.r
[reg_save_b0
] != 0)
4138 src
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
4139 reg_emitted (reg_save_b0
);
4147 /* Compute offset from CFA for BR0. */
4148 /* ??? Must be kept in sync with ia64_expand_prologue. */
4149 off
= (current_frame_info
.spill_cfa_off
4150 + current_frame_info
.spill_size
);
4151 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
4152 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4155 /* Convert CFA offset to a register based offset. */
4156 if (frame_pointer_needed
)
4157 src
= hard_frame_pointer_rtx
;
4160 src
= stack_pointer_rtx
;
4161 off
+= current_frame_info
.total_size
;
4164 /* Load address into scratch register. */
4165 off_r
= GEN_INT (off
);
4166 if (satisfies_constraint_I (off_r
))
4167 emit_insn (gen_adddi3 (dest
, src
, off_r
));
4170 emit_move_insn (dest
, off_r
);
4171 emit_insn (gen_adddi3 (dest
, src
, dest
));
4174 src
= gen_rtx_MEM (Pmode
, dest
);
4178 src
= gen_rtx_REG (DImode
, BR_REG (0));
4180 emit_move_insn (dest
, src
);
4184 ia64_hard_regno_rename_ok (int from
, int to
)
4186 /* Don't clobber any of the registers we reserved for the prologue. */
4189 for (r
= reg_fp
; r
<= reg_save_ar_lc
; r
++)
4190 if (to
== current_frame_info
.r
[r
]
4191 || from
== current_frame_info
.r
[r
]
4192 || to
== emitted_frame_related_regs
[r
]
4193 || from
== emitted_frame_related_regs
[r
])
4196 /* Don't use output registers outside the register frame. */
4197 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
4200 /* Retain even/oddness on predicate register pairs. */
4201 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
4202 return (from
& 1) == (to
& 1);
4207 /* Target hook for assembling integer objects. Handle word-sized
4208 aligned objects and detect the cases when @fptr is needed. */
4211 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4213 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
4214 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
4215 && GET_CODE (x
) == SYMBOL_REF
4216 && SYMBOL_REF_FUNCTION_P (x
))
4218 static const char * const directive
[2][2] = {
4219 /* 64-bit pointer */ /* 32-bit pointer */
4220 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4221 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4223 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
4224 output_addr_const (asm_out_file
, x
);
4225 fputs (")\n", asm_out_file
);
4228 return default_assemble_integer (x
, size
, aligned_p
);
4231 /* Emit the function prologue. */
4234 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4236 int mask
, grsave
, grsave_prev
;
4238 if (current_frame_info
.need_regstk
)
4239 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
4240 current_frame_info
.n_input_regs
,
4241 current_frame_info
.n_local_regs
,
4242 current_frame_info
.n_output_regs
,
4243 current_frame_info
.n_rotate_regs
);
4245 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4248 /* Emit the .prologue directive. */
4251 grsave
= grsave_prev
= 0;
4252 if (current_frame_info
.r
[reg_save_b0
] != 0)
4255 grsave
= grsave_prev
= current_frame_info
.r
[reg_save_b0
];
4257 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0
4258 && (grsave_prev
== 0
4259 || current_frame_info
.r
[reg_save_ar_pfs
] == grsave_prev
+ 1))
4262 if (grsave_prev
== 0)
4263 grsave
= current_frame_info
.r
[reg_save_ar_pfs
];
4264 grsave_prev
= current_frame_info
.r
[reg_save_ar_pfs
];
4266 if (current_frame_info
.r
[reg_fp
] != 0
4267 && (grsave_prev
== 0
4268 || current_frame_info
.r
[reg_fp
] == grsave_prev
+ 1))
4271 if (grsave_prev
== 0)
4272 grsave
= HARD_FRAME_POINTER_REGNUM
;
4273 grsave_prev
= current_frame_info
.r
[reg_fp
];
4275 if (current_frame_info
.r
[reg_save_pr
] != 0
4276 && (grsave_prev
== 0
4277 || current_frame_info
.r
[reg_save_pr
] == grsave_prev
+ 1))
4280 if (grsave_prev
== 0)
4281 grsave
= current_frame_info
.r
[reg_save_pr
];
4284 if (mask
&& TARGET_GNU_AS
)
4285 fprintf (file
, "\t.prologue %d, %d\n", mask
,
4286 ia64_dbx_register_number (grsave
));
4288 fputs ("\t.prologue\n", file
);
4290 /* Emit a .spill directive, if necessary, to relocate the base of
4291 the register spill area. */
4292 if (current_frame_info
.spill_cfa_off
!= -16)
4293 fprintf (file
, "\t.spill %ld\n",
4294 (long) (current_frame_info
.spill_cfa_off
4295 + current_frame_info
.spill_size
));
4298 /* Emit the .body directive at the scheduled end of the prologue. */
4301 ia64_output_function_end_prologue (FILE *file
)
4303 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4306 fputs ("\t.body\n", file
);
4309 /* Emit the function epilogue. */
4312 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
4313 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4317 if (current_frame_info
.r
[reg_fp
])
4319 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
4320 reg_names
[HARD_FRAME_POINTER_REGNUM
]
4321 = reg_names
[current_frame_info
.r
[reg_fp
]];
4322 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
4323 reg_emitted (reg_fp
);
4325 if (! TARGET_REG_NAMES
)
4327 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
4328 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
4329 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
4330 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
4331 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
4332 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
4335 current_frame_info
.initialized
= 0;
4339 ia64_dbx_register_number (int regno
)
4341 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4342 from its home at loc79 to something inside the register frame. We
4343 must perform the same renumbering here for the debug info. */
4344 if (current_frame_info
.r
[reg_fp
])
4346 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4347 regno
= current_frame_info
.r
[reg_fp
];
4348 else if (regno
== current_frame_info
.r
[reg_fp
])
4349 regno
= HARD_FRAME_POINTER_REGNUM
;
4352 if (IN_REGNO_P (regno
))
4353 return 32 + regno
- IN_REG (0);
4354 else if (LOC_REGNO_P (regno
))
4355 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
4356 else if (OUT_REGNO_P (regno
))
4357 return (32 + current_frame_info
.n_input_regs
4358 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
4363 /* Implement TARGET_TRAMPOLINE_INIT.
4365 The trampoline should set the static chain pointer to value placed
4366 into the trampoline and should branch to the specified routine.
4367 To make the normal indirect-subroutine calling convention work,
4368 the trampoline must look like a function descriptor; the first
4369 word being the target address and the second being the target's
4372 We abuse the concept of a global pointer by arranging for it
4373 to point to the data we need to load. The complete trampoline
4374 has the following form:
4376 +-------------------+ \
4377 TRAMP: | __ia64_trampoline | |
4378 +-------------------+ > fake function descriptor
4380 +-------------------+ /
4381 | target descriptor |
4382 +-------------------+
4384 +-------------------+
4388 ia64_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
4390 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4391 rtx addr
, addr_reg
, tramp
, eight
= GEN_INT (8);
4393 /* The Intel assembler requires that the global __ia64_trampoline symbol
4394 be declared explicitly */
4397 static bool declared_ia64_trampoline
= false;
4399 if (!declared_ia64_trampoline
)
4401 declared_ia64_trampoline
= true;
4402 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
4403 "__ia64_trampoline");
4407 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4408 addr
= convert_memory_address (Pmode
, XEXP (m_tramp
, 0));
4409 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
4410 static_chain
= convert_memory_address (Pmode
, static_chain
);
4412 /* Load up our iterator. */
4413 addr_reg
= copy_to_reg (addr
);
4414 m_tramp
= adjust_automodify_address (m_tramp
, Pmode
, addr_reg
, 0);
4416 /* The first two words are the fake descriptor:
4417 __ia64_trampoline, ADDR+16. */
4418 tramp
= gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline");
4419 if (TARGET_ABI_OPEN_VMS
)
4421 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4422 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4423 relocation against function symbols to make it identical to the
4424 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4425 strict ELF and dereference to get the bare code address. */
4426 rtx reg
= gen_reg_rtx (Pmode
);
4427 SYMBOL_REF_FLAGS (tramp
) |= SYMBOL_FLAG_FUNCTION
;
4428 emit_move_insn (reg
, tramp
);
4429 emit_move_insn (reg
, gen_rtx_MEM (Pmode
, reg
));
4432 emit_move_insn (m_tramp
, tramp
);
4433 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4434 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4436 emit_move_insn (m_tramp
, force_reg (Pmode
, plus_constant (Pmode
, addr
, 16)));
4437 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4438 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4440 /* The third word is the target descriptor. */
4441 emit_move_insn (m_tramp
, force_reg (Pmode
, fnaddr
));
4442 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4443 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4445 /* The fourth word is the static chain. */
4446 emit_move_insn (m_tramp
, static_chain
);
4449 /* Do any needed setup for a variadic function. CUM has not been updated
4450 for the last named argument which has type TYPE and mode MODE.
4452 We generate the actual spill instructions during prologue generation. */
4455 ia64_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
4456 tree type
, int * pretend_size
,
4457 int second_time ATTRIBUTE_UNUSED
)
4459 CUMULATIVE_ARGS next_cum
= *get_cumulative_args (cum
);
4461 /* Skip the current argument. */
4462 ia64_function_arg_advance (pack_cumulative_args (&next_cum
), mode
, type
, 1);
4464 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
4466 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
4467 *pretend_size
= n
* UNITS_PER_WORD
;
4468 cfun
->machine
->n_varargs
= n
;
4472 /* Check whether TYPE is a homogeneous floating point aggregate. If
4473 it is, return the mode of the floating point type that appears
4474 in all leafs. If it is not, return VOIDmode.
4476 An aggregate is a homogeneous floating point aggregate is if all
4477 fields/elements in it have the same floating point type (e.g,
4478 SFmode). 128-bit quad-precision floats are excluded.
4480 Variable sized aggregates should never arrive here, since we should
4481 have already decided to pass them by reference. Top-level zero-sized
4482 aggregates are excluded because our parallels crash the middle-end. */
4484 static enum machine_mode
4485 hfa_element_mode (const_tree type
, bool nested
)
4487 enum machine_mode element_mode
= VOIDmode
;
4488 enum machine_mode mode
;
4489 enum tree_code code
= TREE_CODE (type
);
4490 int know_element_mode
= 0;
4493 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
4498 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
4499 case BOOLEAN_TYPE
: case POINTER_TYPE
:
4500 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
4501 case LANG_TYPE
: case FUNCTION_TYPE
:
4504 /* Fortran complex types are supposed to be HFAs, so we need to handle
4505 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4508 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
4509 && TYPE_MODE (type
) != TCmode
)
4510 return GET_MODE_INNER (TYPE_MODE (type
));
4515 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4516 mode if this is contained within an aggregate. */
4517 if (nested
&& TYPE_MODE (type
) != TFmode
)
4518 return TYPE_MODE (type
);
4523 return hfa_element_mode (TREE_TYPE (type
), 1);
4527 case QUAL_UNION_TYPE
:
4528 for (t
= TYPE_FIELDS (type
); t
; t
= DECL_CHAIN (t
))
4530 if (TREE_CODE (t
) != FIELD_DECL
)
4533 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
4534 if (know_element_mode
)
4536 if (mode
!= element_mode
)
4539 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
4543 know_element_mode
= 1;
4544 element_mode
= mode
;
4547 return element_mode
;
4550 /* If we reach here, we probably have some front-end specific type
4551 that the backend doesn't know about. This can happen via the
4552 aggregate_value_p call in init_function_start. All we can do is
4553 ignore unknown tree types. */
4560 /* Return the number of words required to hold a quantity of TYPE and MODE
4561 when passed as an argument. */
4563 ia64_function_arg_words (const_tree type
, enum machine_mode mode
)
4567 if (mode
== BLKmode
)
4568 words
= int_size_in_bytes (type
);
4570 words
= GET_MODE_SIZE (mode
);
4572 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
4575 /* Return the number of registers that should be skipped so the current
4576 argument (described by TYPE and WORDS) will be properly aligned.
4578 Integer and float arguments larger than 8 bytes start at the next
4579 even boundary. Aggregates larger than 8 bytes start at the next
4580 even boundary if the aggregate has 16 byte alignment. Note that
4581 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4582 but are still to be aligned in registers.
4584 ??? The ABI does not specify how to handle aggregates with
4585 alignment from 9 to 15 bytes, or greater than 16. We handle them
4586 all as if they had 16 byte alignment. Such aggregates can occur
4587 only if gcc extensions are used. */
4589 ia64_function_arg_offset (const CUMULATIVE_ARGS
*cum
,
4590 const_tree type
, int words
)
4592 /* No registers are skipped on VMS. */
4593 if (TARGET_ABI_OPEN_VMS
|| (cum
->words
& 1) == 0)
4597 && TREE_CODE (type
) != INTEGER_TYPE
4598 && TREE_CODE (type
) != REAL_TYPE
)
4599 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
4604 /* Return rtx for register where argument is passed, or zero if it is passed
4606 /* ??? 128-bit quad-precision floats are always passed in general
4610 ia64_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
4611 const_tree type
, bool named
, bool incoming
)
4613 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4615 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
4616 int words
= ia64_function_arg_words (type
, mode
);
4617 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4618 enum machine_mode hfa_mode
= VOIDmode
;
4620 /* For OPEN VMS, emit the instruction setting up the argument register here,
4621 when we know this will be together with the other arguments setup related
4622 insns. This is not the conceptually best place to do this, but this is
4623 the easiest as we have convenient access to cumulative args info. */
4625 if (TARGET_ABI_OPEN_VMS
&& mode
== VOIDmode
&& type
== void_type_node
4628 unsigned HOST_WIDE_INT regval
= cum
->words
;
4631 for (i
= 0; i
< 8; i
++)
4632 regval
|= ((int) cum
->atypes
[i
]) << (i
* 3 + 8);
4634 emit_move_insn (gen_rtx_REG (DImode
, GR_REG (25)),
4638 /* If all argument slots are used, then it must go on the stack. */
4639 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4642 /* On OpenVMS argument is either in Rn or Fn. */
4643 if (TARGET_ABI_OPEN_VMS
)
4645 if (FLOAT_MODE_P (mode
))
4646 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->words
);
4648 return gen_rtx_REG (mode
, basereg
+ cum
->words
);
4651 /* Check for and handle homogeneous FP aggregates. */
4653 hfa_mode
= hfa_element_mode (type
, 0);
4655 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4656 and unprototyped hfas are passed specially. */
4657 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4661 int fp_regs
= cum
->fp_regs
;
4662 int int_regs
= cum
->words
+ offset
;
4663 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4667 /* If prototyped, pass it in FR regs then GR regs.
4668 If not prototyped, pass it in both FR and GR regs.
4670 If this is an SFmode aggregate, then it is possible to run out of
4671 FR regs while GR regs are still left. In that case, we pass the
4672 remaining part in the GR regs. */
4674 /* Fill the FP regs. We do this always. We stop if we reach the end
4675 of the argument, the last FP register, or the last argument slot. */
4677 byte_size
= ((mode
== BLKmode
)
4678 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4679 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4681 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4682 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
4684 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4685 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
4689 args_byte_size
+= hfa_size
;
4693 /* If no prototype, then the whole thing must go in GR regs. */
4694 if (! cum
->prototype
)
4696 /* If this is an SFmode aggregate, then we might have some left over
4697 that needs to go in GR regs. */
4698 else if (byte_size
!= offset
)
4699 int_regs
+= offset
/ UNITS_PER_WORD
;
4701 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4703 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
4705 enum machine_mode gr_mode
= DImode
;
4706 unsigned int gr_size
;
4708 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4709 then this goes in a GR reg left adjusted/little endian, right
4710 adjusted/big endian. */
4711 /* ??? Currently this is handled wrong, because 4-byte hunks are
4712 always right adjusted/little endian. */
4715 /* If we have an even 4 byte hunk because the aggregate is a
4716 multiple of 4 bytes in size, then this goes in a GR reg right
4717 adjusted/little endian. */
4718 else if (byte_size
- offset
== 4)
4721 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4722 gen_rtx_REG (gr_mode
, (basereg
4726 gr_size
= GET_MODE_SIZE (gr_mode
);
4728 if (gr_size
== UNITS_PER_WORD
4729 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
4731 else if (gr_size
> UNITS_PER_WORD
)
4732 int_regs
+= gr_size
/ UNITS_PER_WORD
;
4734 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4737 /* Integral and aggregates go in general registers. If we have run out of
4738 FR registers, then FP values must also go in general registers. This can
4739 happen when we have a SFmode HFA. */
4740 else if (mode
== TFmode
|| mode
== TCmode
4741 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4743 int byte_size
= ((mode
== BLKmode
)
4744 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4745 if (BYTES_BIG_ENDIAN
4746 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
4747 && byte_size
< UNITS_PER_WORD
4750 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4751 gen_rtx_REG (DImode
,
4752 (basereg
+ cum
->words
4755 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
4758 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4762 /* If there is a prototype, then FP values go in a FR register when
4763 named, and in a GR register when unnamed. */
4764 else if (cum
->prototype
)
4767 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
4768 /* In big-endian mode, an anonymous SFmode value must be represented
4769 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4770 the value into the high half of the general register. */
4771 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
4772 return gen_rtx_PARALLEL (mode
,
4774 gen_rtx_EXPR_LIST (VOIDmode
,
4775 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
4778 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4780 /* If there is no prototype, then FP values go in both FR and GR
4784 /* See comment above. */
4785 enum machine_mode inner_mode
=
4786 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
4788 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4789 gen_rtx_REG (mode
, (FR_ARG_FIRST
4792 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4793 gen_rtx_REG (inner_mode
,
4794 (basereg
+ cum
->words
4798 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
4802 /* Implement TARGET_FUNCION_ARG target hook. */
4805 ia64_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
4806 const_tree type
, bool named
)
4808 return ia64_function_arg_1 (cum
, mode
, type
, named
, false);
4811 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4814 ia64_function_incoming_arg (cumulative_args_t cum
,
4815 enum machine_mode mode
,
4816 const_tree type
, bool named
)
4818 return ia64_function_arg_1 (cum
, mode
, type
, named
, true);
4821 /* Return number of bytes, at the beginning of the argument, that must be
4822 put in registers. 0 is the argument is entirely in registers or entirely
4826 ia64_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
4827 tree type
, bool named ATTRIBUTE_UNUSED
)
4829 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4831 int words
= ia64_function_arg_words (type
, mode
);
4832 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4834 /* If all argument slots are used, then it must go on the stack. */
4835 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4838 /* It doesn't matter whether the argument goes in FR or GR regs. If
4839 it fits within the 8 argument slots, then it goes entirely in
4840 registers. If it extends past the last argument slot, then the rest
4841 goes on the stack. */
4843 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
4846 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
4849 /* Return ivms_arg_type based on machine_mode. */
4851 static enum ivms_arg_type
4852 ia64_arg_type (enum machine_mode mode
)
4865 /* Update CUM to point after this argument. This is patterned after
4866 ia64_function_arg. */
4869 ia64_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
4870 const_tree type
, bool named
)
4872 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4873 int words
= ia64_function_arg_words (type
, mode
);
4874 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4875 enum machine_mode hfa_mode
= VOIDmode
;
4877 /* If all arg slots are already full, then there is nothing to do. */
4878 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
4880 cum
->words
+= words
+ offset
;
4884 cum
->atypes
[cum
->words
] = ia64_arg_type (mode
);
4885 cum
->words
+= words
+ offset
;
4887 /* On OpenVMS argument is either in Rn or Fn. */
4888 if (TARGET_ABI_OPEN_VMS
)
4890 cum
->int_regs
= cum
->words
;
4891 cum
->fp_regs
= cum
->words
;
4895 /* Check for and handle homogeneous FP aggregates. */
4897 hfa_mode
= hfa_element_mode (type
, 0);
4899 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4900 and unprototyped hfas are passed specially. */
4901 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4903 int fp_regs
= cum
->fp_regs
;
4904 /* This is the original value of cum->words + offset. */
4905 int int_regs
= cum
->words
- words
;
4906 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4910 /* If prototyped, pass it in FR regs then GR regs.
4911 If not prototyped, pass it in both FR and GR regs.
4913 If this is an SFmode aggregate, then it is possible to run out of
4914 FR regs while GR regs are still left. In that case, we pass the
4915 remaining part in the GR regs. */
4917 /* Fill the FP regs. We do this always. We stop if we reach the end
4918 of the argument, the last FP register, or the last argument slot. */
4920 byte_size
= ((mode
== BLKmode
)
4921 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4922 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4924 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4925 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
4928 args_byte_size
+= hfa_size
;
4932 cum
->fp_regs
= fp_regs
;
4935 /* Integral and aggregates go in general registers. So do TFmode FP values.
4936 If we have run out of FR registers, then other FP values must also go in
4937 general registers. This can happen when we have a SFmode HFA. */
4938 else if (mode
== TFmode
|| mode
== TCmode
4939 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4940 cum
->int_regs
= cum
->words
;
4942 /* If there is a prototype, then FP values go in a FR register when
4943 named, and in a GR register when unnamed. */
4944 else if (cum
->prototype
)
4947 cum
->int_regs
= cum
->words
;
4949 /* ??? Complex types should not reach here. */
4950 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4952 /* If there is no prototype, then FP values go in both FR and GR
4956 /* ??? Complex types should not reach here. */
4957 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4958 cum
->int_regs
= cum
->words
;
4962 /* Arguments with alignment larger than 8 bytes start at the next even
4963 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4964 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4967 ia64_function_arg_boundary (enum machine_mode mode
, const_tree type
)
4969 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
4970 return PARM_BOUNDARY
* 2;
4974 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
4975 return PARM_BOUNDARY
* 2;
4977 return PARM_BOUNDARY
;
4980 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
4981 return PARM_BOUNDARY
* 2;
4983 return PARM_BOUNDARY
;
4986 /* True if it is OK to do sibling call optimization for the specified
4987 call expression EXP. DECL will be the called function, or NULL if
4988 this is an indirect call. */
4990 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
4992 /* We can't perform a sibcall if the current function has the syscall_linkage
4994 if (lookup_attribute ("syscall_linkage",
4995 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
4998 /* We must always return with our current GP. This means we can
4999 only sibcall to functions defined in the current module unless
5000 TARGET_CONST_GP is set to true. */
5001 return (decl
&& (*targetm
.binds_local_p
) (decl
)) || TARGET_CONST_GP
;
5005 /* Implement va_arg. */
5008 ia64_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
5011 /* Variable sized types are passed by reference. */
5012 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5014 tree ptrtype
= build_pointer_type (type
);
5015 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
5016 return build_va_arg_indirect_ref (addr
);
5019 /* Aggregate arguments with alignment larger than 8 bytes start at
5020 the next even boundary. Integer and floating point arguments
5021 do so if they are larger than 8 bytes, whether or not they are
5022 also aligned larger than 8 bytes. */
5023 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
5024 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
5026 tree t
= fold_build_pointer_plus_hwi (valist
, 2 * UNITS_PER_WORD
- 1);
5027 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5028 build_int_cst (TREE_TYPE (t
), -2 * UNITS_PER_WORD
));
5029 gimplify_assign (unshare_expr (valist
), t
, pre_p
);
5032 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5035 /* Return 1 if function return value returned in memory. Return 0 if it is
5039 ia64_return_in_memory (const_tree valtype
, const_tree fntype ATTRIBUTE_UNUSED
)
5041 enum machine_mode mode
;
5042 enum machine_mode hfa_mode
;
5043 HOST_WIDE_INT byte_size
;
5045 mode
= TYPE_MODE (valtype
);
5046 byte_size
= GET_MODE_SIZE (mode
);
5047 if (mode
== BLKmode
)
5049 byte_size
= int_size_in_bytes (valtype
);
5054 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5056 hfa_mode
= hfa_element_mode (valtype
, 0);
5057 if (hfa_mode
!= VOIDmode
)
5059 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
5061 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
5066 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
5072 /* Return rtx for register that holds the function return value. */
5075 ia64_function_value (const_tree valtype
,
5076 const_tree fn_decl_or_type
,
5077 bool outgoing ATTRIBUTE_UNUSED
)
5079 enum machine_mode mode
;
5080 enum machine_mode hfa_mode
;
5082 const_tree func
= fn_decl_or_type
;
5085 && !DECL_P (fn_decl_or_type
))
5088 mode
= TYPE_MODE (valtype
);
5089 hfa_mode
= hfa_element_mode (valtype
, 0);
5091 if (hfa_mode
!= VOIDmode
)
5099 hfa_size
= GET_MODE_SIZE (hfa_mode
);
5100 byte_size
= ((mode
== BLKmode
)
5101 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
5103 for (i
= 0; offset
< byte_size
; i
++)
5105 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5106 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
5110 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5112 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
5113 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
5116 bool need_parallel
= false;
5118 /* In big-endian mode, we need to manage the layout of aggregates
5119 in the registers so that we get the bits properly aligned in
5120 the highpart of the registers. */
5121 if (BYTES_BIG_ENDIAN
5122 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
5123 need_parallel
= true;
5125 /* Something like struct S { long double x; char a[0] } is not an
5126 HFA structure, and therefore doesn't go in fp registers. But
5127 the middle-end will give it XFmode anyway, and XFmode values
5128 don't normally fit in integer registers. So we need to smuggle
5129 the value inside a parallel. */
5130 else if (mode
== XFmode
|| mode
== XCmode
|| mode
== RFmode
)
5131 need_parallel
= true;
5141 bytesize
= int_size_in_bytes (valtype
);
5142 /* An empty PARALLEL is invalid here, but the return value
5143 doesn't matter for empty structs. */
5145 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5146 for (i
= 0; offset
< bytesize
; i
++)
5148 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5149 gen_rtx_REG (DImode
,
5152 offset
+= UNITS_PER_WORD
;
5154 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5157 mode
= promote_function_mode (valtype
, mode
, &unsignedp
,
5158 func
? TREE_TYPE (func
) : NULL_TREE
,
5161 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5165 /* Worker function for TARGET_LIBCALL_VALUE. */
5168 ia64_libcall_value (enum machine_mode mode
,
5169 const_rtx fun ATTRIBUTE_UNUSED
)
5171 return gen_rtx_REG (mode
,
5172 (((GET_MODE_CLASS (mode
) == MODE_FLOAT
5173 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5174 && (mode
) != TFmode
)
5175 ? FR_RET_FIRST
: GR_RET_FIRST
));
5178 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5181 ia64_function_value_regno_p (const unsigned int regno
)
5183 return ((regno
>= GR_RET_FIRST
&& regno
<= GR_RET_LAST
)
5184 || (regno
>= FR_RET_FIRST
&& regno
<= FR_RET_LAST
));
5187 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5188 We need to emit DTP-relative relocations. */
5191 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5193 gcc_assert (size
== 4 || size
== 8);
5195 fputs ("\tdata4.ua\t@dtprel(", file
);
5197 fputs ("\tdata8.ua\t@dtprel(", file
);
5198 output_addr_const (file
, x
);
5202 /* Print a memory address as an operand to reference that memory location. */
5204 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5205 also call this from ia64_print_operand for memory addresses. */
5208 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
5209 rtx address ATTRIBUTE_UNUSED
)
5213 /* Print an operand to an assembler instruction.
5214 C Swap and print a comparison operator.
5215 D Print an FP comparison operator.
5216 E Print 32 - constant, for SImode shifts as extract.
5217 e Print 64 - constant, for DImode rotates.
5218 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5219 a floating point register emitted normally.
5220 G A floating point constant.
5221 I Invert a predicate register by adding 1.
5222 J Select the proper predicate register for a condition.
5223 j Select the inverse predicate register for a condition.
5224 O Append .acq for volatile load.
5225 P Postincrement of a MEM.
5226 Q Append .rel for volatile store.
5227 R Print .s .d or nothing for a single, double or no truncation.
5228 S Shift amount for shladd instruction.
5229 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5230 for Intel assembler.
5231 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5232 for Intel assembler.
5233 X A pair of floating point registers.
5234 r Print register name, or constant 0 as r0. HP compatibility for
5236 v Print vector constant value as an 8-byte integer value. */
5239 ia64_print_operand (FILE * file
, rtx x
, int code
)
5246 /* Handled below. */
5251 enum rtx_code c
= swap_condition (GET_CODE (x
));
5252 fputs (GET_RTX_NAME (c
), file
);
5257 switch (GET_CODE (x
))
5281 str
= GET_RTX_NAME (GET_CODE (x
));
5288 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
5292 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
5296 if (x
== CONST0_RTX (GET_MODE (x
)))
5297 str
= reg_names
[FR_REG (0)];
5298 else if (x
== CONST1_RTX (GET_MODE (x
)))
5299 str
= reg_names
[FR_REG (1)];
5302 gcc_assert (GET_CODE (x
) == REG
);
5303 str
= reg_names
[REGNO (x
)];
5312 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
5313 real_to_target (val
, &rv
, GET_MODE (x
));
5314 if (GET_MODE (x
) == SFmode
)
5315 fprintf (file
, "0x%08lx", val
[0] & 0xffffffff);
5316 else if (GET_MODE (x
) == DFmode
)
5317 fprintf (file
, "0x%08lx%08lx", (WORDS_BIG_ENDIAN
? val
[0] : val
[1])
5319 (WORDS_BIG_ENDIAN
? val
[1] : val
[0])
5322 output_operand_lossage ("invalid %%G mode");
5327 fputs (reg_names
[REGNO (x
) + 1], file
);
5333 unsigned int regno
= REGNO (XEXP (x
, 0));
5334 if (GET_CODE (x
) == EQ
)
5338 fputs (reg_names
[regno
], file
);
5343 if (MEM_VOLATILE_P (x
))
5344 fputs(".acq", file
);
5349 HOST_WIDE_INT value
;
5351 switch (GET_CODE (XEXP (x
, 0)))
5357 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5358 if (GET_CODE (x
) == CONST_INT
)
5362 gcc_assert (GET_CODE (x
) == REG
);
5363 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
5369 value
= GET_MODE_SIZE (GET_MODE (x
));
5373 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
5377 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
5382 if (MEM_VOLATILE_P (x
))
5383 fputs(".rel", file
);
5387 if (x
== CONST0_RTX (GET_MODE (x
)))
5389 else if (x
== CONST1_RTX (GET_MODE (x
)))
5391 else if (x
== CONST2_RTX (GET_MODE (x
)))
5394 output_operand_lossage ("invalid %%R value");
5398 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5402 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5404 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
5410 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5412 const char *prefix
= "0x";
5413 if (INTVAL (x
) & 0x80000000)
5415 fprintf (file
, "0xffffffff");
5418 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
5425 unsigned int regno
= REGNO (x
);
5426 fprintf (file
, "%s, %s", reg_names
[regno
], reg_names
[regno
+ 1]);
5431 /* If this operand is the constant zero, write it as register zero.
5432 Any register, zero, or CONST_INT value is OK here. */
5433 if (GET_CODE (x
) == REG
)
5434 fputs (reg_names
[REGNO (x
)], file
);
5435 else if (x
== CONST0_RTX (GET_MODE (x
)))
5437 else if (GET_CODE (x
) == CONST_INT
)
5438 output_addr_const (file
, x
);
5440 output_operand_lossage ("invalid %%r value");
5444 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
5445 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
5452 /* For conditional branches, returns or calls, substitute
5453 sptk, dptk, dpnt, or spnt for %s. */
5454 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
5457 int pred_val
= INTVAL (XEXP (x
, 0));
5459 /* Guess top and bottom 10% statically predicted. */
5460 if (pred_val
< REG_BR_PROB_BASE
/ 50
5461 && br_prob_note_reliable_p (x
))
5463 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
5465 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98
5466 || !br_prob_note_reliable_p (x
))
5471 else if (CALL_P (current_output_insn
))
5476 fputs (which
, file
);
5481 x
= current_insn_predicate
;
5484 unsigned int regno
= REGNO (XEXP (x
, 0));
5485 if (GET_CODE (x
) == EQ
)
5487 fprintf (file
, "(%s) ", reg_names
[regno
]);
5492 output_operand_lossage ("ia64_print_operand: unknown code");
5496 switch (GET_CODE (x
))
5498 /* This happens for the spill/restore instructions. */
5503 /* ... fall through ... */
5506 fputs (reg_names
[REGNO (x
)], file
);
5511 rtx addr
= XEXP (x
, 0);
5512 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
5513 addr
= XEXP (addr
, 0);
5514 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
5519 output_addr_const (file
, x
);
5526 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5529 ia64_print_operand_punct_valid_p (unsigned char code
)
5531 return (code
== '+' || code
== ',');
5534 /* Compute a (partial) cost for rtx X. Return true if the complete
5535 cost has been computed, and false if subexpressions should be
5536 scanned. In either case, *TOTAL contains the cost result. */
5537 /* ??? This is incomplete. */
5540 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
5541 int *total
, bool speed ATTRIBUTE_UNUSED
)
5549 *total
= satisfies_constraint_J (x
) ? 0 : COSTS_N_INSNS (1);
5552 if (satisfies_constraint_I (x
))
5554 else if (satisfies_constraint_J (x
))
5557 *total
= COSTS_N_INSNS (1);
5560 if (satisfies_constraint_K (x
) || satisfies_constraint_L (x
))
5563 *total
= COSTS_N_INSNS (1);
5568 *total
= COSTS_N_INSNS (1);
5574 *total
= COSTS_N_INSNS (3);
5578 *total
= COSTS_N_INSNS (4);
5582 /* For multiplies wider than HImode, we have to go to the FPU,
5583 which normally involves copies. Plus there's the latency
5584 of the multiply itself, and the latency of the instructions to
5585 transfer integer regs to FP regs. */
5586 if (FLOAT_MODE_P (GET_MODE (x
)))
5587 *total
= COSTS_N_INSNS (4);
5588 else if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
5589 *total
= COSTS_N_INSNS (10);
5591 *total
= COSTS_N_INSNS (2);
5596 if (FLOAT_MODE_P (GET_MODE (x
)))
5598 *total
= COSTS_N_INSNS (4);
5606 *total
= COSTS_N_INSNS (1);
5613 /* We make divide expensive, so that divide-by-constant will be
5614 optimized to a multiply. */
5615 *total
= COSTS_N_INSNS (60);
5623 /* Calculate the cost of moving data from a register in class FROM to
5624 one in class TO, using MODE. */
5627 ia64_register_move_cost (enum machine_mode mode
, reg_class_t from
,
5630 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5631 if (to
== ADDL_REGS
)
5633 if (from
== ADDL_REGS
)
5636 /* All costs are symmetric, so reduce cases by putting the
5637 lower number class as the destination. */
5640 reg_class_t tmp
= to
;
5641 to
= from
, from
= tmp
;
5644 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5645 so that we get secondary memory reloads. Between FR_REGS,
5646 we have to make this at least as expensive as memory_move_cost
5647 to avoid spectacularly poor register class preferencing. */
5648 if (mode
== XFmode
|| mode
== RFmode
)
5650 if (to
!= GR_REGS
|| from
!= GR_REGS
)
5651 return memory_move_cost (mode
, to
, false);
5659 /* Moving between PR registers takes two insns. */
5660 if (from
== PR_REGS
)
5662 /* Moving between PR and anything but GR is impossible. */
5663 if (from
!= GR_REGS
)
5664 return memory_move_cost (mode
, to
, false);
5668 /* Moving between BR and anything but GR is impossible. */
5669 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
5670 return memory_move_cost (mode
, to
, false);
5675 /* Moving between AR and anything but GR is impossible. */
5676 if (from
!= GR_REGS
)
5677 return memory_move_cost (mode
, to
, false);
5683 case GR_AND_FR_REGS
:
5684 case GR_AND_BR_REGS
:
5695 /* Calculate the cost of moving data of MODE from a register to or from
5699 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
5701 bool in ATTRIBUTE_UNUSED
)
5703 if (rclass
== GENERAL_REGS
5704 || rclass
== FR_REGS
5705 || rclass
== FP_REGS
5706 || rclass
== GR_AND_FR_REGS
)
5712 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5713 on RCLASS to use when copying X into that class. */
5716 ia64_preferred_reload_class (rtx x
, reg_class_t rclass
)
5722 /* Don't allow volatile mem reloads into floating point registers.
5723 This is defined to force reload to choose the r/m case instead
5724 of the f/f case when reloading (set (reg fX) (mem/v)). */
5725 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
5728 /* Force all unrecognized constants into the constant pool. */
5746 /* This function returns the register class required for a secondary
5747 register when copying between one of the registers in RCLASS, and X,
5748 using MODE. A return value of NO_REGS means that no secondary register
5752 ia64_secondary_reload_class (enum reg_class rclass
,
5753 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
5757 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5758 regno
= true_regnum (x
);
5765 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5766 interaction. We end up with two pseudos with overlapping lifetimes
5767 both of which are equiv to the same constant, and both which need
5768 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5769 changes depending on the path length, which means the qty_first_reg
5770 check in make_regs_eqv can give different answers at different times.
5771 At some point I'll probably need a reload_indi pattern to handle
5774 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5775 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5776 non-general registers for good measure. */
5777 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
5780 /* This is needed if a pseudo used as a call_operand gets spilled to a
5782 if (GET_CODE (x
) == MEM
)
5788 /* Need to go through general registers to get to other class regs. */
5789 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
5792 /* This can happen when a paradoxical subreg is an operand to the
5794 /* ??? This shouldn't be necessary after instruction scheduling is
5795 enabled, because paradoxical subregs are not accepted by
5796 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5797 stop the paradoxical subreg stupidity in the *_operand functions
5799 if (GET_CODE (x
) == MEM
5800 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
5801 || GET_MODE (x
) == QImode
))
5804 /* This can happen because of the ior/and/etc patterns that accept FP
5805 registers as operands. If the third operand is a constant, then it
5806 needs to be reloaded into a FP register. */
5807 if (GET_CODE (x
) == CONST_INT
)
5810 /* This can happen because of register elimination in a muldi3 insn.
5811 E.g. `26107 * (unsigned long)&u'. */
5812 if (GET_CODE (x
) == PLUS
)
5817 /* ??? This happens if we cse/gcse a BImode value across a call,
5818 and the function has a nonlocal goto. This is because global
5819 does not allocate call crossing pseudos to hard registers when
5820 crtl->has_nonlocal_goto is true. This is relatively
5821 common for C++ programs that use exceptions. To reproduce,
5822 return NO_REGS and compile libstdc++. */
5823 if (GET_CODE (x
) == MEM
)
5826 /* This can happen when we take a BImode subreg of a DImode value,
5827 and that DImode value winds up in some non-GR register. */
5828 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
5840 /* Implement targetm.unspec_may_trap_p hook. */
5842 ia64_unspec_may_trap_p (const_rtx x
, unsigned flags
)
5844 switch (XINT (x
, 1))
5850 case UNSPEC_CHKACLR
:
5852 /* These unspecs are just wrappers. */
5853 return may_trap_p_1 (XVECEXP (x
, 0, 0), flags
);
5856 return default_unspec_may_trap_p (x
, flags
);
5860 /* Parse the -mfixed-range= option string. */
5863 fix_range (const char *const_str
)
5866 char *str
, *dash
, *comma
;
5868 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5869 REG2 are either register names or register numbers. The effect
5870 of this option is to mark the registers in the range from REG1 to
5871 REG2 as ``fixed'' so they won't be used by the compiler. This is
5872 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5874 i
= strlen (const_str
);
5875 str
= (char *) alloca (i
+ 1);
5876 memcpy (str
, const_str
, i
+ 1);
5880 dash
= strchr (str
, '-');
5883 warning (0, "value of -mfixed-range must have form REG1-REG2");
5888 comma
= strchr (dash
+ 1, ',');
5892 first
= decode_reg_name (str
);
5895 warning (0, "unknown register name: %s", str
);
5899 last
= decode_reg_name (dash
+ 1);
5902 warning (0, "unknown register name: %s", dash
+ 1);
5910 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
5914 for (i
= first
; i
<= last
; ++i
)
5915 fixed_regs
[i
] = call_used_regs
[i
] = 1;
5925 /* Implement TARGET_OPTION_OVERRIDE. */
5928 ia64_option_override (void)
5931 cl_deferred_option
*opt
;
5932 vec
<cl_deferred_option
> *v
5933 = (vec
<cl_deferred_option
> *) ia64_deferred_options
;
5936 FOR_EACH_VEC_ELT (*v
, i
, opt
)
5938 switch (opt
->opt_index
)
5940 case OPT_mfixed_range_
:
5941 fix_range (opt
->arg
);
5949 if (TARGET_AUTO_PIC
)
5950 target_flags
|= MASK_CONST_GP
;
5952 /* Numerous experiment shows that IRA based loop pressure
5953 calculation works better for RTL loop invariant motion on targets
5954 with enough (>= 32) registers. It is an expensive optimization.
5955 So it is on only for peak performance. */
5957 flag_ira_loop_pressure
= 1;
5960 ia64_section_threshold
= (global_options_set
.x_g_switch_value
5962 : IA64_DEFAULT_GVALUE
);
5964 init_machine_status
= ia64_init_machine_status
;
5966 if (align_functions
<= 0)
5967 align_functions
= 64;
5968 if (align_loops
<= 0)
5970 if (TARGET_ABI_OPEN_VMS
)
5973 ia64_override_options_after_change();
5976 /* Implement targetm.override_options_after_change. */
5979 ia64_override_options_after_change (void)
5982 && !global_options_set
.x_flag_selective_scheduling
5983 && !global_options_set
.x_flag_selective_scheduling2
)
5985 flag_selective_scheduling2
= 1;
5986 flag_sel_sched_pipelining
= 1;
5988 if (mflag_sched_control_spec
== 2)
5990 /* Control speculation is on by default for the selective scheduler,
5991 but not for the Haifa scheduler. */
5992 mflag_sched_control_spec
= flag_selective_scheduling2
? 1 : 0;
5994 if (flag_sel_sched_pipelining
&& flag_auto_inc_dec
)
5996 /* FIXME: remove this when we'd implement breaking autoinsns as
5997 a transformation. */
5998 flag_auto_inc_dec
= 0;
6002 /* Initialize the record of emitted frame related registers. */
6004 void ia64_init_expanders (void)
6006 memset (&emitted_frame_related_regs
, 0, sizeof (emitted_frame_related_regs
));
6009 static struct machine_function
*
6010 ia64_init_machine_status (void)
6012 return ggc_alloc_cleared_machine_function ();
6015 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
6016 static enum attr_type
ia64_safe_type (rtx
);
6018 static enum attr_itanium_class
6019 ia64_safe_itanium_class (rtx insn
)
6021 if (recog_memoized (insn
) >= 0)
6022 return get_attr_itanium_class (insn
);
6023 else if (DEBUG_INSN_P (insn
))
6024 return ITANIUM_CLASS_IGNORE
;
6026 return ITANIUM_CLASS_UNKNOWN
;
6029 static enum attr_type
6030 ia64_safe_type (rtx insn
)
6032 if (recog_memoized (insn
) >= 0)
6033 return get_attr_type (insn
);
6035 return TYPE_UNKNOWN
;
6038 /* The following collection of routines emit instruction group stop bits as
6039 necessary to avoid dependencies. */
6041 /* Need to track some additional registers as far as serialization is
6042 concerned so we can properly handle br.call and br.ret. We could
6043 make these registers visible to gcc, but since these registers are
6044 never explicitly used in gcc generated code, it seems wasteful to
6045 do so (plus it would make the call and return patterns needlessly
6047 #define REG_RP (BR_REG (0))
6048 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6049 /* This is used for volatile asms which may require a stop bit immediately
6050 before and after them. */
6051 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6052 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6053 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6055 /* For each register, we keep track of how it has been written in the
6056 current instruction group.
6058 If a register is written unconditionally (no qualifying predicate),
6059 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6061 If a register is written if its qualifying predicate P is true, we
6062 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6063 may be written again by the complement of P (P^1) and when this happens,
6064 WRITE_COUNT gets set to 2.
6066 The result of this is that whenever an insn attempts to write a register
6067 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6069 If a predicate register is written by a floating-point insn, we set
6070 WRITTEN_BY_FP to true.
6072 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6073 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6075 #if GCC_VERSION >= 4000
6076 #define RWS_FIELD_TYPE __extension__ unsigned short
6078 #define RWS_FIELD_TYPE unsigned int
6080 struct reg_write_state
6082 RWS_FIELD_TYPE write_count
: 2;
6083 RWS_FIELD_TYPE first_pred
: 10;
6084 RWS_FIELD_TYPE written_by_fp
: 1;
6085 RWS_FIELD_TYPE written_by_and
: 1;
6086 RWS_FIELD_TYPE written_by_or
: 1;
6089 /* Cumulative info for the current instruction group. */
6090 struct reg_write_state rws_sum
[NUM_REGS
];
6091 #ifdef ENABLE_CHECKING
6092 /* Bitmap whether a register has been written in the current insn. */
6093 HARD_REG_ELT_TYPE rws_insn
[(NUM_REGS
+ HOST_BITS_PER_WIDEST_FAST_INT
- 1)
6094 / HOST_BITS_PER_WIDEST_FAST_INT
];
6097 rws_insn_set (int regno
)
6099 gcc_assert (!TEST_HARD_REG_BIT (rws_insn
, regno
));
6100 SET_HARD_REG_BIT (rws_insn
, regno
);
6104 rws_insn_test (int regno
)
6106 return TEST_HARD_REG_BIT (rws_insn
, regno
);
6109 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6110 unsigned char rws_insn
[2];
6113 rws_insn_set (int regno
)
6115 if (regno
== REG_AR_CFM
)
6117 else if (regno
== REG_VOLATILE
)
6122 rws_insn_test (int regno
)
6124 if (regno
== REG_AR_CFM
)
6126 if (regno
== REG_VOLATILE
)
6132 /* Indicates whether this is the first instruction after a stop bit,
6133 in which case we don't need another stop bit. Without this,
6134 ia64_variable_issue will die when scheduling an alloc. */
6135 static int first_instruction
;
6137 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6138 RTL for one instruction. */
6141 unsigned int is_write
: 1; /* Is register being written? */
6142 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
6143 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
6144 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
6145 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
6146 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
6149 static void rws_update (int, struct reg_flags
, int);
6150 static int rws_access_regno (int, struct reg_flags
, int);
6151 static int rws_access_reg (rtx
, struct reg_flags
, int);
6152 static void update_set_flags (rtx
, struct reg_flags
*);
6153 static int set_src_needs_barrier (rtx
, struct reg_flags
, int);
6154 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
6155 static void init_insn_group_barriers (void);
6156 static int group_barrier_needed (rtx
);
6157 static int safe_group_barrier_needed (rtx
);
6158 static int in_safe_group_barrier
;
6160 /* Update *RWS for REGNO, which is being written by the current instruction,
6161 with predicate PRED, and associated register flags in FLAGS. */
6164 rws_update (int regno
, struct reg_flags flags
, int pred
)
6167 rws_sum
[regno
].write_count
++;
6169 rws_sum
[regno
].write_count
= 2;
6170 rws_sum
[regno
].written_by_fp
|= flags
.is_fp
;
6171 /* ??? Not tracking and/or across differing predicates. */
6172 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6173 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6174 rws_sum
[regno
].first_pred
= pred
;
6177 /* Handle an access to register REGNO of type FLAGS using predicate register
6178 PRED. Update rws_sum array. Return 1 if this access creates
6179 a dependency with an earlier instruction in the same group. */
6182 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
6184 int need_barrier
= 0;
6186 gcc_assert (regno
< NUM_REGS
);
6188 if (! PR_REGNO_P (regno
))
6189 flags
.is_and
= flags
.is_or
= 0;
6195 rws_insn_set (regno
);
6196 write_count
= rws_sum
[regno
].write_count
;
6198 switch (write_count
)
6201 /* The register has not been written yet. */
6202 if (!in_safe_group_barrier
)
6203 rws_update (regno
, flags
, pred
);
6207 /* The register has been written via a predicate. Treat
6208 it like a unconditional write and do not try to check
6209 for complementary pred reg in earlier write. */
6210 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6212 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6216 if (!in_safe_group_barrier
)
6217 rws_update (regno
, flags
, pred
);
6221 /* The register has been unconditionally written already. We
6223 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6225 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6229 if (!in_safe_group_barrier
)
6231 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6232 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6242 if (flags
.is_branch
)
6244 /* Branches have several RAW exceptions that allow to avoid
6247 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
6248 /* RAW dependencies on branch regs are permissible as long
6249 as the writer is a non-branch instruction. Since we
6250 never generate code that uses a branch register written
6251 by a branch instruction, handling this case is
6255 if (REGNO_REG_CLASS (regno
) == PR_REGS
6256 && ! rws_sum
[regno
].written_by_fp
)
6257 /* The predicates of a branch are available within the
6258 same insn group as long as the predicate was written by
6259 something other than a floating-point instruction. */
6263 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6265 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6268 switch (rws_sum
[regno
].write_count
)
6271 /* The register has not been written yet. */
6275 /* The register has been written via a predicate, assume we
6276 need a barrier (don't check for complementary regs). */
6281 /* The register has been unconditionally written already. We
6291 return need_barrier
;
6295 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
6297 int regno
= REGNO (reg
);
6298 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
6301 return rws_access_regno (regno
, flags
, pred
);
6304 int need_barrier
= 0;
6306 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
6307 return need_barrier
;
6311 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6312 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6315 update_set_flags (rtx x
, struct reg_flags
*pflags
)
6317 rtx src
= SET_SRC (x
);
6319 switch (GET_CODE (src
))
6325 /* There are four cases here:
6326 (1) The destination is (pc), in which case this is a branch,
6327 nothing here applies.
6328 (2) The destination is ar.lc, in which case this is a
6329 doloop_end_internal,
6330 (3) The destination is an fp register, in which case this is
6331 an fselect instruction.
6332 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6333 this is a check load.
6334 In all cases, nothing we do in this function applies. */
6338 if (COMPARISON_P (src
)
6339 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src
, 0))))
6340 /* Set pflags->is_fp to 1 so that we know we're dealing
6341 with a floating point comparison when processing the
6342 destination of the SET. */
6345 /* Discover if this is a parallel comparison. We only handle
6346 and.orcm and or.andcm at present, since we must retain a
6347 strict inverse on the predicate pair. */
6348 else if (GET_CODE (src
) == AND
)
6350 else if (GET_CODE (src
) == IOR
)
6357 /* Subroutine of rtx_needs_barrier; this function determines whether the
6358 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6359 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6363 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6365 int need_barrier
= 0;
6367 rtx src
= SET_SRC (x
);
6369 if (GET_CODE (src
) == CALL
)
6370 /* We don't need to worry about the result registers that
6371 get written by subroutine call. */
6372 return rtx_needs_barrier (src
, flags
, pred
);
6373 else if (SET_DEST (x
) == pc_rtx
)
6375 /* X is a conditional branch. */
6376 /* ??? This seems redundant, as the caller sets this bit for
6378 if (!ia64_spec_check_src_p (src
))
6379 flags
.is_branch
= 1;
6380 return rtx_needs_barrier (src
, flags
, pred
);
6383 if (ia64_spec_check_src_p (src
))
6384 /* Avoid checking one register twice (in condition
6385 and in 'then' section) for ldc pattern. */
6387 gcc_assert (REG_P (XEXP (src
, 2)));
6388 need_barrier
= rtx_needs_barrier (XEXP (src
, 2), flags
, pred
);
6390 /* We process MEM below. */
6391 src
= XEXP (src
, 1);
6394 need_barrier
|= rtx_needs_barrier (src
, flags
, pred
);
6397 if (GET_CODE (dst
) == ZERO_EXTRACT
)
6399 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
6400 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
6402 return need_barrier
;
6405 /* Handle an access to rtx X of type FLAGS using predicate register
6406 PRED. Return 1 if this access creates a dependency with an earlier
6407 instruction in the same group. */
6410 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6413 int is_complemented
= 0;
6414 int need_barrier
= 0;
6415 const char *format_ptr
;
6416 struct reg_flags new_flags
;
6424 switch (GET_CODE (x
))
6427 update_set_flags (x
, &new_flags
);
6428 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
);
6429 if (GET_CODE (SET_SRC (x
)) != CALL
)
6431 new_flags
.is_write
= 1;
6432 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
6437 new_flags
.is_write
= 0;
6438 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6440 /* Avoid multiple register writes, in case this is a pattern with
6441 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6442 if (! flags
.is_sibcall
&& ! rws_insn_test (REG_AR_CFM
))
6444 new_flags
.is_write
= 1;
6445 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
6446 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
6447 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6452 /* X is a predicated instruction. */
6454 cond
= COND_EXEC_TEST (x
);
6456 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
6458 if (GET_CODE (cond
) == EQ
)
6459 is_complemented
= 1;
6460 cond
= XEXP (cond
, 0);
6461 gcc_assert (GET_CODE (cond
) == REG
6462 && REGNO_REG_CLASS (REGNO (cond
)) == PR_REGS
);
6463 pred
= REGNO (cond
);
6464 if (is_complemented
)
6467 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
6468 return need_barrier
;
6472 /* Clobber & use are for earlier compiler-phases only. */
6477 /* We always emit stop bits for traditional asms. We emit stop bits
6478 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6479 if (GET_CODE (x
) != ASM_OPERANDS
6480 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
6482 /* Avoid writing the register multiple times if we have multiple
6483 asm outputs. This avoids a failure in rws_access_reg. */
6484 if (! rws_insn_test (REG_VOLATILE
))
6486 new_flags
.is_write
= 1;
6487 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
6492 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6493 We cannot just fall through here since then we would be confused
6494 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6495 traditional asms unlike their normal usage. */
6497 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
6498 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
6503 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6505 rtx pat
= XVECEXP (x
, 0, i
);
6506 switch (GET_CODE (pat
))
6509 update_set_flags (pat
, &new_flags
);
6510 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
);
6516 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6520 if (REG_P (XEXP (pat
, 0))
6521 && extract_asm_operands (x
) != NULL_RTX
6522 && REGNO (XEXP (pat
, 0)) != AR_UNAT_REGNUM
)
6524 new_flags
.is_write
= 1;
6525 need_barrier
|= rtx_needs_barrier (XEXP (pat
, 0),
6538 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6540 rtx pat
= XVECEXP (x
, 0, i
);
6541 if (GET_CODE (pat
) == SET
)
6543 if (GET_CODE (SET_SRC (pat
)) != CALL
)
6545 new_flags
.is_write
= 1;
6546 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
6550 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
6551 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6556 need_barrier
|= rtx_needs_barrier (SUBREG_REG (x
), flags
, pred
);
6559 if (REGNO (x
) == AR_UNAT_REGNUM
)
6561 for (i
= 0; i
< 64; ++i
)
6562 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
6565 need_barrier
= rws_access_reg (x
, flags
, pred
);
6569 /* Find the regs used in memory address computation. */
6570 new_flags
.is_write
= 0;
6571 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6574 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
6575 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
6578 /* Operators with side-effects. */
6579 case POST_INC
: case POST_DEC
:
6580 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6582 new_flags
.is_write
= 0;
6583 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6584 new_flags
.is_write
= 1;
6585 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6589 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6591 new_flags
.is_write
= 0;
6592 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6593 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6594 new_flags
.is_write
= 1;
6595 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6598 /* Handle common unary and binary ops for efficiency. */
6599 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
6600 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
6601 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
6602 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
6603 case NE
: case EQ
: case GE
: case GT
: case LE
:
6604 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
6605 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6606 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6609 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
6610 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
6611 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
6612 case SQRT
: case FFS
: case POPCOUNT
:
6613 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6617 /* VEC_SELECT's second argument is a PARALLEL with integers that
6618 describe the elements selected. On ia64, those integers are
6619 always constants. Avoid walking the PARALLEL so that we don't
6620 get confused with "normal" parallels and then die. */
6621 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6625 switch (XINT (x
, 1))
6627 case UNSPEC_LTOFF_DTPMOD
:
6628 case UNSPEC_LTOFF_DTPREL
:
6630 case UNSPEC_LTOFF_TPREL
:
6632 case UNSPEC_PRED_REL_MUTEX
:
6633 case UNSPEC_PIC_CALL
:
6635 case UNSPEC_FETCHADD_ACQ
:
6636 case UNSPEC_FETCHADD_REL
:
6637 case UNSPEC_BSP_VALUE
:
6638 case UNSPEC_FLUSHRS
:
6639 case UNSPEC_BUNDLE_SELECTOR
:
6642 case UNSPEC_GR_SPILL
:
6643 case UNSPEC_GR_RESTORE
:
6645 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
6646 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
6648 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6649 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
6650 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
6655 case UNSPEC_FR_SPILL
:
6656 case UNSPEC_FR_RESTORE
:
6657 case UNSPEC_GETF_EXP
:
6658 case UNSPEC_SETF_EXP
:
6660 case UNSPEC_FR_SQRT_RECIP_APPROX
:
6661 case UNSPEC_FR_SQRT_RECIP_APPROX_RES
:
6666 case UNSPEC_CHKACLR
:
6668 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6671 case UNSPEC_FR_RECIP_APPROX
:
6673 case UNSPEC_COPYSIGN
:
6674 case UNSPEC_FR_RECIP_APPROX_RES
:
6675 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6676 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6679 case UNSPEC_CMPXCHG_ACQ
:
6680 case UNSPEC_CMPXCHG_REL
:
6681 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6682 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
6690 case UNSPEC_VOLATILE
:
6691 switch (XINT (x
, 1))
6694 /* Alloc must always be the first instruction of a group.
6695 We force this by always returning true. */
6696 /* ??? We might get better scheduling if we explicitly check for
6697 input/local/output register dependencies, and modify the
6698 scheduler so that alloc is always reordered to the start of
6699 the current group. We could then eliminate all of the
6700 first_instruction code. */
6701 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6703 new_flags
.is_write
= 1;
6704 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6707 case UNSPECV_SET_BSP
:
6708 case UNSPECV_PROBE_STACK_RANGE
:
6712 case UNSPECV_BLOCKAGE
:
6713 case UNSPECV_INSN_GROUP_BARRIER
:
6715 case UNSPECV_PSAC_ALL
:
6716 case UNSPECV_PSAC_NORMAL
:
6719 case UNSPECV_PROBE_STACK_ADDRESS
:
6720 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6729 new_flags
.is_write
= 0;
6730 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
6731 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6733 new_flags
.is_write
= 1;
6734 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6735 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6739 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
6740 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6741 switch (format_ptr
[i
])
6743 case '0': /* unused field */
6744 case 'i': /* integer */
6745 case 'n': /* note */
6746 case 'w': /* wide integer */
6747 case 's': /* pointer to string */
6748 case 'S': /* optional pointer to string */
6752 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
6757 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
6758 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
6767 return need_barrier
;
6770 /* Clear out the state for group_barrier_needed at the start of a
6771 sequence of insns. */
6774 init_insn_group_barriers (void)
6776 memset (rws_sum
, 0, sizeof (rws_sum
));
6777 first_instruction
= 1;
6780 /* Given the current state, determine whether a group barrier (a stop bit) is
6781 necessary before INSN. Return nonzero if so. This modifies the state to
6782 include the effects of INSN as a side-effect. */
6785 group_barrier_needed (rtx insn
)
6788 int need_barrier
= 0;
6789 struct reg_flags flags
;
6791 memset (&flags
, 0, sizeof (flags
));
6792 switch (GET_CODE (insn
))
6799 /* A barrier doesn't imply an instruction group boundary. */
6803 memset (rws_insn
, 0, sizeof (rws_insn
));
6807 flags
.is_branch
= 1;
6808 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
6809 memset (rws_insn
, 0, sizeof (rws_insn
));
6811 /* Don't bundle a call following another call. */
6812 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6818 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
6822 if (!ia64_spec_check_p (insn
))
6823 flags
.is_branch
= 1;
6825 /* Don't bundle a jump following a call. */
6826 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6834 if (GET_CODE (PATTERN (insn
)) == USE
6835 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6836 /* Don't care about USE and CLOBBER "insns"---those are used to
6837 indicate to the optimizer that it shouldn't get rid of
6838 certain operations. */
6841 pat
= PATTERN (insn
);
6843 /* Ug. Hack hacks hacked elsewhere. */
6844 switch (recog_memoized (insn
))
6846 /* We play dependency tricks with the epilogue in order
6847 to get proper schedules. Undo this for dv analysis. */
6848 case CODE_FOR_epilogue_deallocate_stack
:
6849 case CODE_FOR_prologue_allocate_stack
:
6850 pat
= XVECEXP (pat
, 0, 0);
6853 /* The pattern we use for br.cloop confuses the code above.
6854 The second element of the vector is representative. */
6855 case CODE_FOR_doloop_end_internal
:
6856 pat
= XVECEXP (pat
, 0, 1);
6859 /* Doesn't generate code. */
6860 case CODE_FOR_pred_rel_mutex
:
6861 case CODE_FOR_prologue_use
:
6868 memset (rws_insn
, 0, sizeof (rws_insn
));
6869 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
6871 /* Check to see if the previous instruction was a volatile
6874 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
6882 if (first_instruction
&& important_for_bundling_p (insn
))
6885 first_instruction
= 0;
6888 return need_barrier
;
6891 /* Like group_barrier_needed, but do not clobber the current state. */
6894 safe_group_barrier_needed (rtx insn
)
6896 int saved_first_instruction
;
6899 saved_first_instruction
= first_instruction
;
6900 in_safe_group_barrier
= 1;
6902 t
= group_barrier_needed (insn
);
6904 first_instruction
= saved_first_instruction
;
6905 in_safe_group_barrier
= 0;
6910 /* Scan the current function and insert stop bits as necessary to
6911 eliminate dependencies. This function assumes that a final
6912 instruction scheduling pass has been run which has already
6913 inserted most of the necessary stop bits. This function only
6914 inserts new ones at basic block boundaries, since these are
6915 invisible to the scheduler. */
6918 emit_insn_group_barriers (FILE *dump
)
6922 int insns_since_last_label
= 0;
6924 init_insn_group_barriers ();
6926 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6930 if (insns_since_last_label
)
6932 insns_since_last_label
= 0;
6934 else if (NOTE_P (insn
)
6935 && NOTE_KIND (insn
) == NOTE_INSN_BASIC_BLOCK
)
6937 if (insns_since_last_label
)
6939 insns_since_last_label
= 0;
6941 else if (NONJUMP_INSN_P (insn
)
6942 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
6943 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
6945 init_insn_group_barriers ();
6948 else if (NONDEBUG_INSN_P (insn
))
6950 insns_since_last_label
= 1;
6952 if (group_barrier_needed (insn
))
6957 fprintf (dump
, "Emitting stop before label %d\n",
6958 INSN_UID (last_label
));
6959 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
6962 init_insn_group_barriers ();
6970 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6971 This function has to emit all necessary group barriers. */
6974 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
6978 init_insn_group_barriers ();
6980 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6982 if (BARRIER_P (insn
))
6984 rtx last
= prev_active_insn (insn
);
6988 if (JUMP_TABLE_DATA_P (last
))
6989 last
= prev_active_insn (last
);
6990 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6991 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
6993 init_insn_group_barriers ();
6995 else if (NONDEBUG_INSN_P (insn
))
6997 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
6998 init_insn_group_barriers ();
6999 else if (group_barrier_needed (insn
))
7001 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
7002 init_insn_group_barriers ();
7003 group_barrier_needed (insn
);
7011 /* Instruction scheduling support. */
7013 #define NR_BUNDLES 10
7015 /* A list of names of all available bundles. */
7017 static const char *bundle_name
[NR_BUNDLES
] =
7023 #if NR_BUNDLES == 10
7033 /* Nonzero if we should insert stop bits into the schedule. */
7035 int ia64_final_schedule
= 0;
7037 /* Codes of the corresponding queried units: */
7039 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
7040 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
7042 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
7043 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
7045 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
7047 /* The following variable value is an insn group barrier. */
7049 static rtx dfa_stop_insn
;
7051 /* The following variable value is the last issued insn. */
7053 static rtx last_scheduled_insn
;
7055 /* The following variable value is pointer to a DFA state used as
7056 temporary variable. */
7058 static state_t temp_dfa_state
= NULL
;
7060 /* The following variable value is DFA state after issuing the last
7063 static state_t prev_cycle_state
= NULL
;
7065 /* The following array element values are TRUE if the corresponding
7066 insn requires to add stop bits before it. */
7068 static char *stops_p
= NULL
;
7070 /* The following variable is used to set up the mentioned above array. */
7072 static int stop_before_p
= 0;
7074 /* The following variable value is length of the arrays `clocks' and
7077 static int clocks_length
;
7079 /* The following variable value is number of data speculations in progress. */
7080 static int pending_data_specs
= 0;
7082 /* Number of memory references on current and three future processor cycles. */
7083 static char mem_ops_in_group
[4];
7085 /* Number of current processor cycle (from scheduler's point of view). */
7086 static int current_cycle
;
7088 static rtx
ia64_single_set (rtx
);
7089 static void ia64_emit_insn_before (rtx
, rtx
);
7091 /* Map a bundle number to its pseudo-op. */
7094 get_bundle_name (int b
)
7096 return bundle_name
[b
];
7100 /* Return the maximum number of instructions a cpu can issue. */
7103 ia64_issue_rate (void)
7108 /* Helper function - like single_set, but look inside COND_EXEC. */
7111 ia64_single_set (rtx insn
)
7113 rtx x
= PATTERN (insn
), ret
;
7114 if (GET_CODE (x
) == COND_EXEC
)
7115 x
= COND_EXEC_CODE (x
);
7116 if (GET_CODE (x
) == SET
)
7119 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7120 Although they are not classical single set, the second set is there just
7121 to protect it from moving past FP-relative stack accesses. */
7122 switch (recog_memoized (insn
))
7124 case CODE_FOR_prologue_allocate_stack
:
7125 case CODE_FOR_epilogue_deallocate_stack
:
7126 ret
= XVECEXP (x
, 0, 0);
7130 ret
= single_set_2 (insn
, x
);
7137 /* Adjust the cost of a scheduling dependency.
7138 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7139 COST is the current cost, DW is dependency weakness. */
7141 ia64_adjust_cost_2 (rtx insn
, int dep_type1
, rtx dep_insn
, int cost
, dw_t dw
)
7143 enum reg_note dep_type
= (enum reg_note
) dep_type1
;
7144 enum attr_itanium_class dep_class
;
7145 enum attr_itanium_class insn_class
;
7147 insn_class
= ia64_safe_itanium_class (insn
);
7148 dep_class
= ia64_safe_itanium_class (dep_insn
);
7150 /* Treat true memory dependencies separately. Ignore apparent true
7151 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7152 if (dep_type
== REG_DEP_TRUE
7153 && (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
)
7154 && (insn_class
== ITANIUM_CLASS_BR
|| insn_class
== ITANIUM_CLASS_SCALL
))
7157 if (dw
== MIN_DEP_WEAK
)
7158 /* Store and load are likely to alias, use higher cost to avoid stall. */
7159 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST
);
7160 else if (dw
> MIN_DEP_WEAK
)
7162 /* Store and load are less likely to alias. */
7163 if (mflag_sched_fp_mem_deps_zero_cost
&& dep_class
== ITANIUM_CLASS_STF
)
7164 /* Assume there will be no cache conflict for floating-point data.
7165 For integer data, L1 conflict penalty is huge (17 cycles), so we
7166 never assume it will not cause a conflict. */
7172 if (dep_type
!= REG_DEP_OUTPUT
)
7175 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
7176 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
7182 /* Like emit_insn_before, but skip cycle_display notes.
7183 ??? When cycle display notes are implemented, update this. */
7186 ia64_emit_insn_before (rtx insn
, rtx before
)
7188 emit_insn_before (insn
, before
);
7191 /* The following function marks insns who produce addresses for load
7192 and store insns. Such insns will be placed into M slots because it
7193 decrease latency time for Itanium1 (see function
7194 `ia64_produce_address_p' and the DFA descriptions). */
7197 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
7199 rtx insn
, next
, next_tail
;
7201 /* Before reload, which_alternative is not set, which means that
7202 ia64_safe_itanium_class will produce wrong results for (at least)
7203 move instructions. */
7204 if (!reload_completed
)
7207 next_tail
= NEXT_INSN (tail
);
7208 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7211 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7213 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
7215 sd_iterator_def sd_it
;
7217 bool has_mem_op_consumer_p
= false;
7219 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
7221 enum attr_itanium_class c
;
7223 if (DEP_TYPE (dep
) != REG_DEP_TRUE
)
7226 next
= DEP_CON (dep
);
7227 c
= ia64_safe_itanium_class (next
);
7228 if ((c
== ITANIUM_CLASS_ST
7229 || c
== ITANIUM_CLASS_STF
)
7230 && ia64_st_address_bypass_p (insn
, next
))
7232 has_mem_op_consumer_p
= true;
7235 else if ((c
== ITANIUM_CLASS_LD
7236 || c
== ITANIUM_CLASS_FLD
7237 || c
== ITANIUM_CLASS_FLDP
)
7238 && ia64_ld_address_bypass_p (insn
, next
))
7240 has_mem_op_consumer_p
= true;
7245 insn
->call
= has_mem_op_consumer_p
;
7249 /* We're beginning a new block. Initialize data structures as necessary. */
7252 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7253 int sched_verbose ATTRIBUTE_UNUSED
,
7254 int max_ready ATTRIBUTE_UNUSED
)
7256 #ifdef ENABLE_CHECKING
7259 if (!sel_sched_p () && reload_completed
)
7260 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7261 insn
!= current_sched_info
->next_tail
;
7262 insn
= NEXT_INSN (insn
))
7263 gcc_assert (!SCHED_GROUP_P (insn
));
7265 last_scheduled_insn
= NULL_RTX
;
7266 init_insn_group_barriers ();
7269 memset (mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7272 /* We're beginning a scheduling pass. Check assertion. */
7275 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED
,
7276 int sched_verbose ATTRIBUTE_UNUSED
,
7277 int max_ready ATTRIBUTE_UNUSED
)
7279 gcc_assert (pending_data_specs
== 0);
7282 /* Scheduling pass is now finished. Free/reset static variable. */
7284 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
7285 int sched_verbose ATTRIBUTE_UNUSED
)
7287 gcc_assert (pending_data_specs
== 0);
7290 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7291 speculation check), FALSE otherwise. */
7293 is_load_p (rtx insn
)
7295 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7298 ((insn_class
== ITANIUM_CLASS_LD
|| insn_class
== ITANIUM_CLASS_FLD
)
7299 && get_attr_check_load (insn
) == CHECK_LOAD_NO
);
7302 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7303 (taking account for 3-cycle cache reference postponing for stores: Intel
7304 Itanium 2 Reference Manual for Software Development and Optimization,
7307 record_memory_reference (rtx insn
)
7309 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7311 switch (insn_class
) {
7312 case ITANIUM_CLASS_FLD
:
7313 case ITANIUM_CLASS_LD
:
7314 mem_ops_in_group
[current_cycle
% 4]++;
7316 case ITANIUM_CLASS_STF
:
7317 case ITANIUM_CLASS_ST
:
7318 mem_ops_in_group
[(current_cycle
+ 3) % 4]++;
7324 /* We are about to being issuing insns for this clock cycle.
7325 Override the default sort algorithm to better slot instructions. */
7328 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
7329 int *pn_ready
, int clock_var
,
7333 int n_ready
= *pn_ready
;
7334 rtx
*e_ready
= ready
+ n_ready
;
7338 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
7340 if (reorder_type
== 0)
7342 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7344 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7345 if (insnp
< e_ready
)
7348 enum attr_type t
= ia64_safe_type (insn
);
7349 if (t
== TYPE_UNKNOWN
)
7351 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7352 || asm_noperands (PATTERN (insn
)) >= 0)
7354 rtx lowest
= ready
[n_asms
];
7355 ready
[n_asms
] = insn
;
7361 rtx highest
= ready
[n_ready
- 1];
7362 ready
[n_ready
- 1] = insn
;
7369 if (n_asms
< n_ready
)
7371 /* Some normal insns to process. Skip the asms. */
7375 else if (n_ready
> 0)
7379 if (ia64_final_schedule
)
7382 int nr_need_stop
= 0;
7384 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7385 if (safe_group_barrier_needed (*insnp
))
7388 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
7390 if (reorder_type
== 0)
7393 /* Move down everything that needs a stop bit, preserving
7395 while (insnp
-- > ready
+ deleted
)
7396 while (insnp
>= ready
+ deleted
)
7399 if (! safe_group_barrier_needed (insn
))
7401 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7409 current_cycle
= clock_var
;
7410 if (reload_completed
&& mem_ops_in_group
[clock_var
% 4] >= ia64_max_memory_insns
)
7415 /* Move down loads/stores, preserving relative order. */
7416 while (insnp
-- > ready
+ moved
)
7417 while (insnp
>= ready
+ moved
)
7420 if (! is_load_p (insn
))
7422 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7433 /* We are about to being issuing insns for this clock cycle. Override
7434 the default sort algorithm to better slot instructions. */
7437 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
7440 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
7441 pn_ready
, clock_var
, 0);
7444 /* Like ia64_sched_reorder, but called after issuing each insn.
7445 Override the default sort algorithm to better slot instructions. */
7448 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
7449 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
7450 int *pn_ready
, int clock_var
)
7452 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
7456 /* We are about to issue INSN. Return the number of insns left on the
7457 ready queue that can be issued this cycle. */
7460 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
7461 int sched_verbose ATTRIBUTE_UNUSED
,
7462 rtx insn ATTRIBUTE_UNUSED
,
7463 int can_issue_more ATTRIBUTE_UNUSED
)
7465 if (sched_deps_info
->generate_spec_deps
&& !sel_sched_p ())
7466 /* Modulo scheduling does not extend h_i_d when emitting
7467 new instructions. Don't use h_i_d, if we don't have to. */
7469 if (DONE_SPEC (insn
) & BEGIN_DATA
)
7470 pending_data_specs
++;
7471 if (CHECK_SPEC (insn
) & BEGIN_DATA
)
7472 pending_data_specs
--;
7475 if (DEBUG_INSN_P (insn
))
7478 last_scheduled_insn
= insn
;
7479 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
7480 if (reload_completed
)
7482 int needed
= group_barrier_needed (insn
);
7484 gcc_assert (!needed
);
7486 init_insn_group_barriers ();
7487 stops_p
[INSN_UID (insn
)] = stop_before_p
;
7490 record_memory_reference (insn
);
7495 /* We are choosing insn from the ready queue. Return nonzero if INSN
7499 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
7501 gcc_assert (insn
&& INSN_P (insn
));
7502 return ((!reload_completed
7503 || !safe_group_barrier_needed (insn
))
7504 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn
)
7505 && (!mflag_sched_mem_insns_hard_limit
7506 || !is_load_p (insn
)
7507 || mem_ops_in_group
[current_cycle
% 4] < ia64_max_memory_insns
));
7510 /* We are choosing insn from the ready queue. Return nonzero if INSN
7514 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn
)
7516 gcc_assert (insn
&& INSN_P (insn
));
7517 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7518 we keep ALAT half-empty. */
7519 return (pending_data_specs
< 16
7520 || !(TODO_SPEC (insn
) & BEGIN_DATA
));
7523 /* The following variable value is pseudo-insn used by the DFA insn
7524 scheduler to change the DFA state when the simulated clock is
7527 static rtx dfa_pre_cycle_insn
;
7529 /* Returns 1 when a meaningful insn was scheduled between the last group
7530 barrier and LAST. */
7532 scheduled_good_insn (rtx last
)
7534 if (last
&& recog_memoized (last
) >= 0)
7538 last
!= NULL
&& !NOTE_INSN_BASIC_BLOCK_P (last
)
7539 && !stops_p
[INSN_UID (last
)];
7540 last
= PREV_INSN (last
))
7541 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7542 the ebb we're scheduling. */
7543 if (INSN_P (last
) && recog_memoized (last
) >= 0)
7549 /* We are about to being issuing INSN. Return nonzero if we cannot
7550 issue it on given cycle CLOCK and return zero if we should not sort
7551 the ready queue on the next clock start. */
7554 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
7555 int clock
, int *sort_p
)
7557 gcc_assert (insn
&& INSN_P (insn
));
7559 if (DEBUG_INSN_P (insn
))
7562 /* When a group barrier is needed for insn, last_scheduled_insn
7564 gcc_assert (!(reload_completed
&& safe_group_barrier_needed (insn
))
7565 || last_scheduled_insn
);
7567 if ((reload_completed
7568 && (safe_group_barrier_needed (insn
)
7569 || (mflag_sched_stop_bits_after_every_cycle
7570 && last_clock
!= clock
7571 && last_scheduled_insn
7572 && scheduled_good_insn (last_scheduled_insn
))))
7573 || (last_scheduled_insn
7574 && (CALL_P (last_scheduled_insn
)
7575 || unknown_for_bundling_p (last_scheduled_insn
))))
7577 init_insn_group_barriers ();
7579 if (verbose
&& dump
)
7580 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
7581 last_clock
== clock
? " + cycle advance" : "");
7584 current_cycle
= clock
;
7585 mem_ops_in_group
[current_cycle
% 4] = 0;
7587 if (last_clock
== clock
)
7589 state_transition (curr_state
, dfa_stop_insn
);
7590 if (TARGET_EARLY_STOP_BITS
)
7591 *sort_p
= (last_scheduled_insn
== NULL_RTX
7592 || ! CALL_P (last_scheduled_insn
));
7598 if (last_scheduled_insn
)
7600 if (unknown_for_bundling_p (last_scheduled_insn
))
7601 state_reset (curr_state
);
7604 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
7605 state_transition (curr_state
, dfa_stop_insn
);
7606 state_transition (curr_state
, dfa_pre_cycle_insn
);
7607 state_transition (curr_state
, NULL
);
7614 /* Implement targetm.sched.h_i_d_extended hook.
7615 Extend internal data structures. */
7617 ia64_h_i_d_extended (void)
7619 if (stops_p
!= NULL
)
7621 int new_clocks_length
= get_max_uid () * 3 / 2;
7622 stops_p
= (char *) xrecalloc (stops_p
, new_clocks_length
, clocks_length
, 1);
7623 clocks_length
= new_clocks_length
;
7628 /* This structure describes the data used by the backend to guide scheduling.
7629 When the current scheduling point is switched, this data should be saved
7630 and restored later, if the scheduler returns to this point. */
7631 struct _ia64_sched_context
7633 state_t prev_cycle_state
;
7634 rtx last_scheduled_insn
;
7635 struct reg_write_state rws_sum
[NUM_REGS
];
7636 struct reg_write_state rws_insn
[NUM_REGS
];
7637 int first_instruction
;
7638 int pending_data_specs
;
7640 char mem_ops_in_group
[4];
7642 typedef struct _ia64_sched_context
*ia64_sched_context_t
;
7644 /* Allocates a scheduling context. */
7646 ia64_alloc_sched_context (void)
7648 return xmalloc (sizeof (struct _ia64_sched_context
));
7651 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7652 the global context otherwise. */
7654 ia64_init_sched_context (void *_sc
, bool clean_p
)
7656 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7658 sc
->prev_cycle_state
= xmalloc (dfa_state_size
);
7661 state_reset (sc
->prev_cycle_state
);
7662 sc
->last_scheduled_insn
= NULL_RTX
;
7663 memset (sc
->rws_sum
, 0, sizeof (rws_sum
));
7664 memset (sc
->rws_insn
, 0, sizeof (rws_insn
));
7665 sc
->first_instruction
= 1;
7666 sc
->pending_data_specs
= 0;
7667 sc
->current_cycle
= 0;
7668 memset (sc
->mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7672 memcpy (sc
->prev_cycle_state
, prev_cycle_state
, dfa_state_size
);
7673 sc
->last_scheduled_insn
= last_scheduled_insn
;
7674 memcpy (sc
->rws_sum
, rws_sum
, sizeof (rws_sum
));
7675 memcpy (sc
->rws_insn
, rws_insn
, sizeof (rws_insn
));
7676 sc
->first_instruction
= first_instruction
;
7677 sc
->pending_data_specs
= pending_data_specs
;
7678 sc
->current_cycle
= current_cycle
;
7679 memcpy (sc
->mem_ops_in_group
, mem_ops_in_group
, sizeof (mem_ops_in_group
));
7683 /* Sets the global scheduling context to the one pointed to by _SC. */
7685 ia64_set_sched_context (void *_sc
)
7687 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7689 gcc_assert (sc
!= NULL
);
7691 memcpy (prev_cycle_state
, sc
->prev_cycle_state
, dfa_state_size
);
7692 last_scheduled_insn
= sc
->last_scheduled_insn
;
7693 memcpy (rws_sum
, sc
->rws_sum
, sizeof (rws_sum
));
7694 memcpy (rws_insn
, sc
->rws_insn
, sizeof (rws_insn
));
7695 first_instruction
= sc
->first_instruction
;
7696 pending_data_specs
= sc
->pending_data_specs
;
7697 current_cycle
= sc
->current_cycle
;
7698 memcpy (mem_ops_in_group
, sc
->mem_ops_in_group
, sizeof (mem_ops_in_group
));
7701 /* Clears the data in the _SC scheduling context. */
7703 ia64_clear_sched_context (void *_sc
)
7705 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7707 free (sc
->prev_cycle_state
);
7708 sc
->prev_cycle_state
= NULL
;
7711 /* Frees the _SC scheduling context. */
7713 ia64_free_sched_context (void *_sc
)
7715 gcc_assert (_sc
!= NULL
);
7720 typedef rtx (* gen_func_t
) (rtx
, rtx
);
7722 /* Return a function that will generate a load of mode MODE_NO
7723 with speculation types TS. */
7725 get_spec_load_gen_function (ds_t ts
, int mode_no
)
7727 static gen_func_t gen_ld_
[] = {
7737 gen_zero_extendqidi2
,
7738 gen_zero_extendhidi2
,
7739 gen_zero_extendsidi2
,
7742 static gen_func_t gen_ld_a
[] = {
7752 gen_zero_extendqidi2_advanced
,
7753 gen_zero_extendhidi2_advanced
,
7754 gen_zero_extendsidi2_advanced
,
7756 static gen_func_t gen_ld_s
[] = {
7757 gen_movbi_speculative
,
7758 gen_movqi_speculative
,
7759 gen_movhi_speculative
,
7760 gen_movsi_speculative
,
7761 gen_movdi_speculative
,
7762 gen_movsf_speculative
,
7763 gen_movdf_speculative
,
7764 gen_movxf_speculative
,
7765 gen_movti_speculative
,
7766 gen_zero_extendqidi2_speculative
,
7767 gen_zero_extendhidi2_speculative
,
7768 gen_zero_extendsidi2_speculative
,
7770 static gen_func_t gen_ld_sa
[] = {
7771 gen_movbi_speculative_advanced
,
7772 gen_movqi_speculative_advanced
,
7773 gen_movhi_speculative_advanced
,
7774 gen_movsi_speculative_advanced
,
7775 gen_movdi_speculative_advanced
,
7776 gen_movsf_speculative_advanced
,
7777 gen_movdf_speculative_advanced
,
7778 gen_movxf_speculative_advanced
,
7779 gen_movti_speculative_advanced
,
7780 gen_zero_extendqidi2_speculative_advanced
,
7781 gen_zero_extendhidi2_speculative_advanced
,
7782 gen_zero_extendsidi2_speculative_advanced
,
7784 static gen_func_t gen_ld_s_a
[] = {
7785 gen_movbi_speculative_a
,
7786 gen_movqi_speculative_a
,
7787 gen_movhi_speculative_a
,
7788 gen_movsi_speculative_a
,
7789 gen_movdi_speculative_a
,
7790 gen_movsf_speculative_a
,
7791 gen_movdf_speculative_a
,
7792 gen_movxf_speculative_a
,
7793 gen_movti_speculative_a
,
7794 gen_zero_extendqidi2_speculative_a
,
7795 gen_zero_extendhidi2_speculative_a
,
7796 gen_zero_extendsidi2_speculative_a
,
7801 if (ts
& BEGIN_DATA
)
7803 if (ts
& BEGIN_CONTROL
)
7808 else if (ts
& BEGIN_CONTROL
)
7810 if ((spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
)
7811 || ia64_needs_block_p (ts
))
7814 gen_ld
= gen_ld_s_a
;
7821 return gen_ld
[mode_no
];
7824 /* Constants that help mapping 'enum machine_mode' to int. */
7827 SPEC_MODE_INVALID
= -1,
7828 SPEC_MODE_FIRST
= 0,
7829 SPEC_MODE_FOR_EXTEND_FIRST
= 1,
7830 SPEC_MODE_FOR_EXTEND_LAST
= 3,
7836 /* Offset to reach ZERO_EXTEND patterns. */
7837 SPEC_GEN_EXTEND_OFFSET
= SPEC_MODE_LAST
- SPEC_MODE_FOR_EXTEND_FIRST
+ 1
7840 /* Return index of the MODE. */
7842 ia64_mode_to_int (enum machine_mode mode
)
7846 case BImode
: return 0; /* SPEC_MODE_FIRST */
7847 case QImode
: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7848 case HImode
: return 2;
7849 case SImode
: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7850 case DImode
: return 4;
7851 case SFmode
: return 5;
7852 case DFmode
: return 6;
7853 case XFmode
: return 7;
7855 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7856 mentioned in itanium[12].md. Predicate fp_register_operand also
7857 needs to be defined. Bottom line: better disable for now. */
7858 return SPEC_MODE_INVALID
;
7859 default: return SPEC_MODE_INVALID
;
7863 /* Provide information about speculation capabilities. */
7865 ia64_set_sched_flags (spec_info_t spec_info
)
7867 unsigned int *flags
= &(current_sched_info
->flags
);
7869 if (*flags
& SCHED_RGN
7870 || *flags
& SCHED_EBB
7871 || *flags
& SEL_SCHED
)
7875 if ((mflag_sched_br_data_spec
&& !reload_completed
&& optimize
> 0)
7876 || (mflag_sched_ar_data_spec
&& reload_completed
))
7881 && ((mflag_sched_br_in_data_spec
&& !reload_completed
)
7882 || (mflag_sched_ar_in_data_spec
&& reload_completed
)))
7886 if (mflag_sched_control_spec
7888 || reload_completed
))
7890 mask
|= BEGIN_CONTROL
;
7892 if (!sel_sched_p () && mflag_sched_in_control_spec
)
7893 mask
|= BE_IN_CONTROL
;
7896 spec_info
->mask
= mask
;
7900 *flags
|= USE_DEPS_LIST
| DO_SPECULATION
;
7902 if (mask
& BE_IN_SPEC
)
7905 spec_info
->flags
= 0;
7907 if ((mask
& DATA_SPEC
) && mflag_sched_prefer_non_data_spec_insns
)
7908 spec_info
->flags
|= PREFER_NON_DATA_SPEC
;
7910 if (mask
& CONTROL_SPEC
)
7912 if (mflag_sched_prefer_non_control_spec_insns
)
7913 spec_info
->flags
|= PREFER_NON_CONTROL_SPEC
;
7915 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec
)
7916 spec_info
->flags
|= SEL_SCHED_SPEC_DONT_CHECK_CONTROL
;
7919 if (sched_verbose
>= 1)
7920 spec_info
->dump
= sched_dump
;
7922 spec_info
->dump
= 0;
7924 if (mflag_sched_count_spec_in_critical_path
)
7925 spec_info
->flags
|= COUNT_SPEC_IN_CRITICAL_PATH
;
7929 spec_info
->mask
= 0;
7932 /* If INSN is an appropriate load return its mode.
7933 Return -1 otherwise. */
7935 get_mode_no_for_insn (rtx insn
)
7937 rtx reg
, mem
, mode_rtx
;
7941 extract_insn_cached (insn
);
7943 /* We use WHICH_ALTERNATIVE only after reload. This will
7944 guarantee that reload won't touch a speculative insn. */
7946 if (recog_data
.n_operands
!= 2)
7949 reg
= recog_data
.operand
[0];
7950 mem
= recog_data
.operand
[1];
7952 /* We should use MEM's mode since REG's mode in presence of
7953 ZERO_EXTEND will always be DImode. */
7954 if (get_attr_speculable1 (insn
) == SPECULABLE1_YES
)
7955 /* Process non-speculative ld. */
7957 if (!reload_completed
)
7959 /* Do not speculate into regs like ar.lc. */
7960 if (!REG_P (reg
) || AR_REGNO_P (REGNO (reg
)))
7967 rtx mem_reg
= XEXP (mem
, 0);
7969 if (!REG_P (mem_reg
))
7975 else if (get_attr_speculable2 (insn
) == SPECULABLE2_YES
)
7977 gcc_assert (REG_P (reg
) && MEM_P (mem
));
7983 else if (get_attr_data_speculative (insn
) == DATA_SPECULATIVE_YES
7984 || get_attr_control_speculative (insn
) == CONTROL_SPECULATIVE_YES
7985 || get_attr_check_load (insn
) == CHECK_LOAD_YES
)
7986 /* Process speculative ld or ld.c. */
7988 gcc_assert (REG_P (reg
) && MEM_P (mem
));
7993 enum attr_itanium_class attr_class
= get_attr_itanium_class (insn
);
7995 if (attr_class
== ITANIUM_CLASS_CHK_A
7996 || attr_class
== ITANIUM_CLASS_CHK_S_I
7997 || attr_class
== ITANIUM_CLASS_CHK_S_F
)
8004 mode_no
= ia64_mode_to_int (GET_MODE (mode_rtx
));
8006 if (mode_no
== SPEC_MODE_INVALID
)
8009 extend_p
= (GET_MODE (reg
) != GET_MODE (mode_rtx
));
8013 if (!(SPEC_MODE_FOR_EXTEND_FIRST
<= mode_no
8014 && mode_no
<= SPEC_MODE_FOR_EXTEND_LAST
))
8017 mode_no
+= SPEC_GEN_EXTEND_OFFSET
;
8023 /* If X is an unspec part of a speculative load, return its code.
8024 Return -1 otherwise. */
8026 get_spec_unspec_code (const_rtx x
)
8028 if (GET_CODE (x
) != UNSPEC
)
8050 /* Implement skip_rtx_p hook. */
8052 ia64_skip_rtx_p (const_rtx x
)
8054 return get_spec_unspec_code (x
) != -1;
8057 /* If INSN is a speculative load, return its UNSPEC code.
8058 Return -1 otherwise. */
8060 get_insn_spec_code (const_rtx insn
)
8064 pat
= PATTERN (insn
);
8066 if (GET_CODE (pat
) == COND_EXEC
)
8067 pat
= COND_EXEC_CODE (pat
);
8069 if (GET_CODE (pat
) != SET
)
8072 reg
= SET_DEST (pat
);
8076 mem
= SET_SRC (pat
);
8077 if (GET_CODE (mem
) == ZERO_EXTEND
)
8078 mem
= XEXP (mem
, 0);
8080 return get_spec_unspec_code (mem
);
8083 /* If INSN is a speculative load, return a ds with the speculation types.
8084 Otherwise [if INSN is a normal instruction] return 0. */
8086 ia64_get_insn_spec_ds (rtx insn
)
8088 int code
= get_insn_spec_code (insn
);
8097 return BEGIN_CONTROL
;
8100 return BEGIN_DATA
| BEGIN_CONTROL
;
8107 /* If INSN is a speculative load return a ds with the speculation types that
8109 Otherwise [if INSN is a normal instruction] return 0. */
8111 ia64_get_insn_checked_ds (rtx insn
)
8113 int code
= get_insn_spec_code (insn
);
8118 return BEGIN_DATA
| BEGIN_CONTROL
;
8121 return BEGIN_CONTROL
;
8125 return BEGIN_DATA
| BEGIN_CONTROL
;
8132 /* If GEN_P is true, calculate the index of needed speculation check and return
8133 speculative pattern for INSN with speculative mode TS, machine mode
8134 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8135 If GEN_P is false, just calculate the index of needed speculation check. */
8137 ia64_gen_spec_load (rtx insn
, ds_t ts
, int mode_no
)
8140 gen_func_t gen_load
;
8142 gen_load
= get_spec_load_gen_function (ts
, mode_no
);
8144 new_pat
= gen_load (copy_rtx (recog_data
.operand
[0]),
8145 copy_rtx (recog_data
.operand
[1]));
8147 pat
= PATTERN (insn
);
8148 if (GET_CODE (pat
) == COND_EXEC
)
8149 new_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8156 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED
,
8157 ds_t ds ATTRIBUTE_UNUSED
)
8162 /* Implement targetm.sched.speculate_insn hook.
8163 Check if the INSN can be TS speculative.
8164 If 'no' - return -1.
8165 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8166 If current pattern of the INSN already provides TS speculation,
8169 ia64_speculate_insn (rtx insn
, ds_t ts
, rtx
*new_pat
)
8174 gcc_assert (!(ts
& ~SPECULATIVE
));
8176 if (ia64_spec_check_p (insn
))
8179 if ((ts
& BE_IN_SPEC
)
8180 && !insn_can_be_in_speculative_p (insn
, ts
))
8183 mode_no
= get_mode_no_for_insn (insn
);
8185 if (mode_no
!= SPEC_MODE_INVALID
)
8187 if (ia64_get_insn_spec_ds (insn
) == ds_get_speculation_types (ts
))
8192 *new_pat
= ia64_gen_spec_load (insn
, ts
, mode_no
);
8201 /* Return a function that will generate a check for speculation TS with mode
8203 If simple check is needed, pass true for SIMPLE_CHECK_P.
8204 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8206 get_spec_check_gen_function (ds_t ts
, int mode_no
,
8207 bool simple_check_p
, bool clearing_check_p
)
8209 static gen_func_t gen_ld_c_clr
[] = {
8219 gen_zero_extendqidi2_clr
,
8220 gen_zero_extendhidi2_clr
,
8221 gen_zero_extendsidi2_clr
,
8223 static gen_func_t gen_ld_c_nc
[] = {
8233 gen_zero_extendqidi2_nc
,
8234 gen_zero_extendhidi2_nc
,
8235 gen_zero_extendsidi2_nc
,
8237 static gen_func_t gen_chk_a_clr
[] = {
8238 gen_advanced_load_check_clr_bi
,
8239 gen_advanced_load_check_clr_qi
,
8240 gen_advanced_load_check_clr_hi
,
8241 gen_advanced_load_check_clr_si
,
8242 gen_advanced_load_check_clr_di
,
8243 gen_advanced_load_check_clr_sf
,
8244 gen_advanced_load_check_clr_df
,
8245 gen_advanced_load_check_clr_xf
,
8246 gen_advanced_load_check_clr_ti
,
8247 gen_advanced_load_check_clr_di
,
8248 gen_advanced_load_check_clr_di
,
8249 gen_advanced_load_check_clr_di
,
8251 static gen_func_t gen_chk_a_nc
[] = {
8252 gen_advanced_load_check_nc_bi
,
8253 gen_advanced_load_check_nc_qi
,
8254 gen_advanced_load_check_nc_hi
,
8255 gen_advanced_load_check_nc_si
,
8256 gen_advanced_load_check_nc_di
,
8257 gen_advanced_load_check_nc_sf
,
8258 gen_advanced_load_check_nc_df
,
8259 gen_advanced_load_check_nc_xf
,
8260 gen_advanced_load_check_nc_ti
,
8261 gen_advanced_load_check_nc_di
,
8262 gen_advanced_load_check_nc_di
,
8263 gen_advanced_load_check_nc_di
,
8265 static gen_func_t gen_chk_s
[] = {
8266 gen_speculation_check_bi
,
8267 gen_speculation_check_qi
,
8268 gen_speculation_check_hi
,
8269 gen_speculation_check_si
,
8270 gen_speculation_check_di
,
8271 gen_speculation_check_sf
,
8272 gen_speculation_check_df
,
8273 gen_speculation_check_xf
,
8274 gen_speculation_check_ti
,
8275 gen_speculation_check_di
,
8276 gen_speculation_check_di
,
8277 gen_speculation_check_di
,
8280 gen_func_t
*gen_check
;
8282 if (ts
& BEGIN_DATA
)
8284 /* We don't need recovery because even if this is ld.sa
8285 ALAT entry will be allocated only if NAT bit is set to zero.
8286 So it is enough to use ld.c here. */
8290 gcc_assert (mflag_sched_spec_ldc
);
8292 if (clearing_check_p
)
8293 gen_check
= gen_ld_c_clr
;
8295 gen_check
= gen_ld_c_nc
;
8299 if (clearing_check_p
)
8300 gen_check
= gen_chk_a_clr
;
8302 gen_check
= gen_chk_a_nc
;
8305 else if (ts
& BEGIN_CONTROL
)
8308 /* We might want to use ld.sa -> ld.c instead of
8311 gcc_assert (!ia64_needs_block_p (ts
));
8313 if (clearing_check_p
)
8314 gen_check
= gen_ld_c_clr
;
8316 gen_check
= gen_ld_c_nc
;
8320 gen_check
= gen_chk_s
;
8326 gcc_assert (mode_no
>= 0);
8327 return gen_check
[mode_no
];
8330 /* Return nonzero, if INSN needs branchy recovery check. */
8332 ia64_needs_block_p (ds_t ts
)
8334 if (ts
& BEGIN_DATA
)
8335 return !mflag_sched_spec_ldc
;
8337 gcc_assert ((ts
& BEGIN_CONTROL
) != 0);
8339 return !(mflag_sched_spec_control_ldc
&& mflag_sched_spec_ldc
);
8342 /* Generate (or regenerate) a recovery check for INSN. */
8344 ia64_gen_spec_check (rtx insn
, rtx label
, ds_t ds
)
8346 rtx op1
, pat
, check_pat
;
8347 gen_func_t gen_check
;
8350 mode_no
= get_mode_no_for_insn (insn
);
8351 gcc_assert (mode_no
>= 0);
8357 gcc_assert (!ia64_needs_block_p (ds
));
8358 op1
= copy_rtx (recog_data
.operand
[1]);
8361 gen_check
= get_spec_check_gen_function (ds
, mode_no
, label
== NULL_RTX
,
8364 check_pat
= gen_check (copy_rtx (recog_data
.operand
[0]), op1
);
8366 pat
= PATTERN (insn
);
8367 if (GET_CODE (pat
) == COND_EXEC
)
8368 check_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8374 /* Return nonzero, if X is branchy recovery check. */
8376 ia64_spec_check_p (rtx x
)
8379 if (GET_CODE (x
) == COND_EXEC
)
8380 x
= COND_EXEC_CODE (x
);
8381 if (GET_CODE (x
) == SET
)
8382 return ia64_spec_check_src_p (SET_SRC (x
));
8386 /* Return nonzero, if SRC belongs to recovery check. */
8388 ia64_spec_check_src_p (rtx src
)
8390 if (GET_CODE (src
) == IF_THEN_ELSE
)
8395 if (GET_CODE (t
) == NE
)
8399 if (GET_CODE (t
) == UNSPEC
)
8405 if (code
== UNSPEC_LDCCLR
8406 || code
== UNSPEC_LDCNC
8407 || code
== UNSPEC_CHKACLR
8408 || code
== UNSPEC_CHKANC
8409 || code
== UNSPEC_CHKS
)
8411 gcc_assert (code
!= 0);
8421 /* The following page contains abstract data `bundle states' which are
8422 used for bundling insns (inserting nops and template generation). */
8424 /* The following describes state of insn bundling. */
8428 /* Unique bundle state number to identify them in the debugging
8431 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
8432 /* number nops before and after the insn */
8433 short before_nops_num
, after_nops_num
;
8434 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
8436 int cost
; /* cost of the state in cycles */
8437 int accumulated_insns_num
; /* number of all previous insns including
8438 nops. L is considered as 2 insns */
8439 int branch_deviation
; /* deviation of previous branches from 3rd slots */
8440 int middle_bundle_stops
; /* number of stop bits in the middle of bundles */
8441 struct bundle_state
*next
; /* next state with the same insn_num */
8442 struct bundle_state
*originator
; /* originator (previous insn state) */
8443 /* All bundle states are in the following chain. */
8444 struct bundle_state
*allocated_states_chain
;
8445 /* The DFA State after issuing the insn and the nops. */
8449 /* The following is map insn number to the corresponding bundle state. */
8451 static struct bundle_state
**index_to_bundle_states
;
8453 /* The unique number of next bundle state. */
8455 static int bundle_states_num
;
8457 /* All allocated bundle states are in the following chain. */
8459 static struct bundle_state
*allocated_bundle_states_chain
;
8461 /* All allocated but not used bundle states are in the following
8464 static struct bundle_state
*free_bundle_state_chain
;
8467 /* The following function returns a free bundle state. */
8469 static struct bundle_state
*
8470 get_free_bundle_state (void)
8472 struct bundle_state
*result
;
8474 if (free_bundle_state_chain
!= NULL
)
8476 result
= free_bundle_state_chain
;
8477 free_bundle_state_chain
= result
->next
;
8481 result
= XNEW (struct bundle_state
);
8482 result
->dfa_state
= xmalloc (dfa_state_size
);
8483 result
->allocated_states_chain
= allocated_bundle_states_chain
;
8484 allocated_bundle_states_chain
= result
;
8486 result
->unique_num
= bundle_states_num
++;
8491 /* The following function frees given bundle state. */
8494 free_bundle_state (struct bundle_state
*state
)
8496 state
->next
= free_bundle_state_chain
;
8497 free_bundle_state_chain
= state
;
8500 /* Start work with abstract data `bundle states'. */
8503 initiate_bundle_states (void)
8505 bundle_states_num
= 0;
8506 free_bundle_state_chain
= NULL
;
8507 allocated_bundle_states_chain
= NULL
;
8510 /* Finish work with abstract data `bundle states'. */
8513 finish_bundle_states (void)
8515 struct bundle_state
*curr_state
, *next_state
;
8517 for (curr_state
= allocated_bundle_states_chain
;
8519 curr_state
= next_state
)
8521 next_state
= curr_state
->allocated_states_chain
;
8522 free (curr_state
->dfa_state
);
8527 /* Hashtable helpers. */
8529 struct bundle_state_hasher
: typed_noop_remove
<bundle_state
>
8531 typedef bundle_state value_type
;
8532 typedef bundle_state compare_type
;
8533 static inline hashval_t
hash (const value_type
*);
8534 static inline bool equal (const value_type
*, const compare_type
*);
8537 /* The function returns hash of BUNDLE_STATE. */
8540 bundle_state_hasher::hash (const value_type
*state
)
8544 for (result
= i
= 0; i
< dfa_state_size
; i
++)
8545 result
+= (((unsigned char *) state
->dfa_state
) [i
]
8546 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
8547 return result
+ state
->insn_num
;
8550 /* The function returns nonzero if the bundle state keys are equal. */
8553 bundle_state_hasher::equal (const value_type
*state1
,
8554 const compare_type
*state2
)
8556 return (state1
->insn_num
== state2
->insn_num
8557 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
8558 dfa_state_size
) == 0);
8561 /* Hash table of the bundle states. The key is dfa_state and insn_num
8562 of the bundle states. */
8564 static hash_table
<bundle_state_hasher
> bundle_state_table
;
8566 /* The function inserts the BUNDLE_STATE into the hash table. The
8567 function returns nonzero if the bundle has been inserted into the
8568 table. The table contains the best bundle state with given key. */
8571 insert_bundle_state (struct bundle_state
*bundle_state
)
8573 struct bundle_state
**entry_ptr
;
8575 entry_ptr
= bundle_state_table
.find_slot (bundle_state
, INSERT
);
8576 if (*entry_ptr
== NULL
)
8578 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
8579 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
8580 *entry_ptr
= bundle_state
;
8583 else if (bundle_state
->cost
< (*entry_ptr
)->cost
8584 || (bundle_state
->cost
== (*entry_ptr
)->cost
8585 && ((*entry_ptr
)->accumulated_insns_num
8586 > bundle_state
->accumulated_insns_num
8587 || ((*entry_ptr
)->accumulated_insns_num
8588 == bundle_state
->accumulated_insns_num
8589 && ((*entry_ptr
)->branch_deviation
8590 > bundle_state
->branch_deviation
8591 || ((*entry_ptr
)->branch_deviation
8592 == bundle_state
->branch_deviation
8593 && (*entry_ptr
)->middle_bundle_stops
8594 > bundle_state
->middle_bundle_stops
))))))
8597 struct bundle_state temp
;
8600 **entry_ptr
= *bundle_state
;
8601 (*entry_ptr
)->next
= temp
.next
;
8602 *bundle_state
= temp
;
8607 /* Start work with the hash table. */
8610 initiate_bundle_state_table (void)
8612 bundle_state_table
.create (50);
8615 /* Finish work with the hash table. */
8618 finish_bundle_state_table (void)
8620 bundle_state_table
.dispose ();
8625 /* The following variable is a insn `nop' used to check bundle states
8626 with different number of inserted nops. */
8628 static rtx ia64_nop
;
8630 /* The following function tries to issue NOPS_NUM nops for the current
8631 state without advancing processor cycle. If it failed, the
8632 function returns FALSE and frees the current state. */
8635 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
8639 for (i
= 0; i
< nops_num
; i
++)
8640 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
8642 free_bundle_state (curr_state
);
8648 /* The following function tries to issue INSN for the current
8649 state without advancing processor cycle. If it failed, the
8650 function returns FALSE and frees the current state. */
8653 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
8655 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
8657 free_bundle_state (curr_state
);
8663 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8664 starting with ORIGINATOR without advancing processor cycle. If
8665 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8666 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8667 If it was successful, the function creates new bundle state and
8668 insert into the hash table and into `index_to_bundle_states'. */
8671 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
8672 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
8674 struct bundle_state
*curr_state
;
8676 curr_state
= get_free_bundle_state ();
8677 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
8678 curr_state
->insn
= insn
;
8679 curr_state
->insn_num
= originator
->insn_num
+ 1;
8680 curr_state
->cost
= originator
->cost
;
8681 curr_state
->originator
= originator
;
8682 curr_state
->before_nops_num
= before_nops_num
;
8683 curr_state
->after_nops_num
= 0;
8684 curr_state
->accumulated_insns_num
8685 = originator
->accumulated_insns_num
+ before_nops_num
;
8686 curr_state
->branch_deviation
= originator
->branch_deviation
;
8687 curr_state
->middle_bundle_stops
= originator
->middle_bundle_stops
;
8689 if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
8691 gcc_assert (GET_MODE (insn
) != TImode
);
8692 if (!try_issue_nops (curr_state
, before_nops_num
))
8694 if (!try_issue_insn (curr_state
, insn
))
8696 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
8697 if (curr_state
->accumulated_insns_num
% 3 != 0)
8698 curr_state
->middle_bundle_stops
++;
8699 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
8700 && curr_state
->accumulated_insns_num
% 3 != 0)
8702 free_bundle_state (curr_state
);
8706 else if (GET_MODE (insn
) != TImode
)
8708 if (!try_issue_nops (curr_state
, before_nops_num
))
8710 if (!try_issue_insn (curr_state
, insn
))
8712 curr_state
->accumulated_insns_num
++;
8713 gcc_assert (!unknown_for_bundling_p (insn
));
8715 if (ia64_safe_type (insn
) == TYPE_L
)
8716 curr_state
->accumulated_insns_num
++;
8720 /* If this is an insn that must be first in a group, then don't allow
8721 nops to be emitted before it. Currently, alloc is the only such
8722 supported instruction. */
8723 /* ??? The bundling automatons should handle this for us, but they do
8724 not yet have support for the first_insn attribute. */
8725 if (before_nops_num
> 0 && get_attr_first_insn (insn
) == FIRST_INSN_YES
)
8727 free_bundle_state (curr_state
);
8731 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
8732 state_transition (curr_state
->dfa_state
, NULL
);
8734 if (!try_issue_nops (curr_state
, before_nops_num
))
8736 if (!try_issue_insn (curr_state
, insn
))
8738 curr_state
->accumulated_insns_num
++;
8739 if (unknown_for_bundling_p (insn
))
8741 /* Finish bundle containing asm insn. */
8742 curr_state
->after_nops_num
8743 = 3 - curr_state
->accumulated_insns_num
% 3;
8744 curr_state
->accumulated_insns_num
8745 += 3 - curr_state
->accumulated_insns_num
% 3;
8747 else if (ia64_safe_type (insn
) == TYPE_L
)
8748 curr_state
->accumulated_insns_num
++;
8750 if (ia64_safe_type (insn
) == TYPE_B
)
8751 curr_state
->branch_deviation
8752 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
8753 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
8755 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
8758 struct bundle_state
*curr_state1
;
8759 struct bundle_state
*allocated_states_chain
;
8761 curr_state1
= get_free_bundle_state ();
8762 dfa_state
= curr_state1
->dfa_state
;
8763 allocated_states_chain
= curr_state1
->allocated_states_chain
;
8764 *curr_state1
= *curr_state
;
8765 curr_state1
->dfa_state
= dfa_state
;
8766 curr_state1
->allocated_states_chain
= allocated_states_chain
;
8767 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
8769 curr_state
= curr_state1
;
8771 if (!try_issue_nops (curr_state
,
8772 3 - curr_state
->accumulated_insns_num
% 3))
8774 curr_state
->after_nops_num
8775 = 3 - curr_state
->accumulated_insns_num
% 3;
8776 curr_state
->accumulated_insns_num
8777 += 3 - curr_state
->accumulated_insns_num
% 3;
8779 if (!insert_bundle_state (curr_state
))
8780 free_bundle_state (curr_state
);
8784 /* The following function returns position in the two window bundle
8788 get_max_pos (state_t state
)
8790 if (cpu_unit_reservation_p (state
, pos_6
))
8792 else if (cpu_unit_reservation_p (state
, pos_5
))
8794 else if (cpu_unit_reservation_p (state
, pos_4
))
8796 else if (cpu_unit_reservation_p (state
, pos_3
))
8798 else if (cpu_unit_reservation_p (state
, pos_2
))
8800 else if (cpu_unit_reservation_p (state
, pos_1
))
8806 /* The function returns code of a possible template for given position
8807 and state. The function should be called only with 2 values of
8808 position equal to 3 or 6. We avoid generating F NOPs by putting
8809 templates containing F insns at the end of the template search
8810 because undocumented anomaly in McKinley derived cores which can
8811 cause stalls if an F-unit insn (including a NOP) is issued within a
8812 six-cycle window after reading certain application registers (such
8813 as ar.bsp). Furthermore, power-considerations also argue against
8814 the use of F-unit instructions unless they're really needed. */
8817 get_template (state_t state
, int pos
)
8822 if (cpu_unit_reservation_p (state
, _0mmi_
))
8824 else if (cpu_unit_reservation_p (state
, _0mii_
))
8826 else if (cpu_unit_reservation_p (state
, _0mmb_
))
8828 else if (cpu_unit_reservation_p (state
, _0mib_
))
8830 else if (cpu_unit_reservation_p (state
, _0mbb_
))
8832 else if (cpu_unit_reservation_p (state
, _0bbb_
))
8834 else if (cpu_unit_reservation_p (state
, _0mmf_
))
8836 else if (cpu_unit_reservation_p (state
, _0mfi_
))
8838 else if (cpu_unit_reservation_p (state
, _0mfb_
))
8840 else if (cpu_unit_reservation_p (state
, _0mlx_
))
8845 if (cpu_unit_reservation_p (state
, _1mmi_
))
8847 else if (cpu_unit_reservation_p (state
, _1mii_
))
8849 else if (cpu_unit_reservation_p (state
, _1mmb_
))
8851 else if (cpu_unit_reservation_p (state
, _1mib_
))
8853 else if (cpu_unit_reservation_p (state
, _1mbb_
))
8855 else if (cpu_unit_reservation_p (state
, _1bbb_
))
8857 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
8859 else if (cpu_unit_reservation_p (state
, _1mfi_
))
8861 else if (cpu_unit_reservation_p (state
, _1mfb_
))
8863 else if (cpu_unit_reservation_p (state
, _1mlx_
))
8872 /* True when INSN is important for bundling. */
8875 important_for_bundling_p (rtx insn
)
8877 return (INSN_P (insn
)
8878 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
8879 && GET_CODE (PATTERN (insn
)) != USE
8880 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8883 /* The following function returns an insn important for insn bundling
8884 followed by INSN and before TAIL. */
8887 get_next_important_insn (rtx insn
, rtx tail
)
8889 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
8890 if (important_for_bundling_p (insn
))
8895 /* True when INSN is unknown, but important, for bundling. */
8898 unknown_for_bundling_p (rtx insn
)
8900 return (INSN_P (insn
)
8901 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_UNKNOWN
8902 && GET_CODE (PATTERN (insn
)) != USE
8903 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8906 /* Add a bundle selector TEMPLATE0 before INSN. */
8909 ia64_add_bundle_selector_before (int template0
, rtx insn
)
8911 rtx b
= gen_bundle_selector (GEN_INT (template0
));
8913 ia64_emit_insn_before (b
, insn
);
8914 #if NR_BUNDLES == 10
8915 if ((template0
== 4 || template0
== 5)
8916 && ia64_except_unwind_info (&global_options
) == UI_TARGET
)
8919 rtx note
= NULL_RTX
;
8921 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8922 first or second slot. If it is and has REG_EH_NOTE set, copy it
8923 to following nops, as br.call sets rp to the address of following
8924 bundle and therefore an EH region end must be on a bundle
8926 insn
= PREV_INSN (insn
);
8927 for (i
= 0; i
< 3; i
++)
8930 insn
= next_active_insn (insn
);
8931 while (NONJUMP_INSN_P (insn
)
8932 && get_attr_empty (insn
) == EMPTY_YES
);
8934 note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8939 gcc_assert ((code
= recog_memoized (insn
)) == CODE_FOR_nop
8940 || code
== CODE_FOR_nop_b
);
8941 if (find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
8944 add_reg_note (insn
, REG_EH_REGION
, XEXP (note
, 0));
8951 /* The following function does insn bundling. Bundling means
8952 inserting templates and nop insns to fit insn groups into permitted
8953 templates. Instruction scheduling uses NDFA (non-deterministic
8954 finite automata) encoding informations about the templates and the
8955 inserted nops. Nondeterminism of the automata permits follows
8956 all possible insn sequences very fast.
8958 Unfortunately it is not possible to get information about inserting
8959 nop insns and used templates from the automata states. The
8960 automata only says that we can issue an insn possibly inserting
8961 some nops before it and using some template. Therefore insn
8962 bundling in this function is implemented by using DFA
8963 (deterministic finite automata). We follow all possible insn
8964 sequences by inserting 0-2 nops (that is what the NDFA describe for
8965 insn scheduling) before/after each insn being bundled. We know the
8966 start of simulated processor cycle from insn scheduling (insn
8967 starting a new cycle has TImode).
8969 Simple implementation of insn bundling would create enormous
8970 number of possible insn sequences satisfying information about new
8971 cycle ticks taken from the insn scheduling. To make the algorithm
8972 practical we use dynamic programming. Each decision (about
8973 inserting nops and implicitly about previous decisions) is described
8974 by structure bundle_state (see above). If we generate the same
8975 bundle state (key is automaton state after issuing the insns and
8976 nops for it), we reuse already generated one. As consequence we
8977 reject some decisions which cannot improve the solution and
8978 reduce memory for the algorithm.
8980 When we reach the end of EBB (extended basic block), we choose the
8981 best sequence and then, moving back in EBB, insert templates for
8982 the best alternative. The templates are taken from querying
8983 automaton state for each insn in chosen bundle states.
8985 So the algorithm makes two (forward and backward) passes through
8989 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
8991 struct bundle_state
*curr_state
, *next_state
, *best_state
;
8992 rtx insn
, next_insn
;
8994 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
8995 int pos
= 0, max_pos
, template0
, template1
;
8998 enum attr_type type
;
9001 /* Count insns in the EBB. */
9002 for (insn
= NEXT_INSN (prev_head_insn
);
9003 insn
&& insn
!= tail
;
9004 insn
= NEXT_INSN (insn
))
9010 dfa_clean_insn_cache ();
9011 initiate_bundle_state_table ();
9012 index_to_bundle_states
= XNEWVEC (struct bundle_state
*, insn_num
+ 2);
9013 /* First (forward) pass -- generation of bundle states. */
9014 curr_state
= get_free_bundle_state ();
9015 curr_state
->insn
= NULL
;
9016 curr_state
->before_nops_num
= 0;
9017 curr_state
->after_nops_num
= 0;
9018 curr_state
->insn_num
= 0;
9019 curr_state
->cost
= 0;
9020 curr_state
->accumulated_insns_num
= 0;
9021 curr_state
->branch_deviation
= 0;
9022 curr_state
->middle_bundle_stops
= 0;
9023 curr_state
->next
= NULL
;
9024 curr_state
->originator
= NULL
;
9025 state_reset (curr_state
->dfa_state
);
9026 index_to_bundle_states
[0] = curr_state
;
9028 /* Shift cycle mark if it is put on insn which could be ignored. */
9029 for (insn
= NEXT_INSN (prev_head_insn
);
9031 insn
= NEXT_INSN (insn
))
9033 && !important_for_bundling_p (insn
)
9034 && GET_MODE (insn
) == TImode
)
9036 PUT_MODE (insn
, VOIDmode
);
9037 for (next_insn
= NEXT_INSN (insn
);
9039 next_insn
= NEXT_INSN (next_insn
))
9040 if (important_for_bundling_p (next_insn
)
9041 && INSN_CODE (next_insn
) != CODE_FOR_insn_group_barrier
)
9043 PUT_MODE (next_insn
, TImode
);
9047 /* Forward pass: generation of bundle states. */
9048 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
9052 gcc_assert (important_for_bundling_p (insn
));
9053 type
= ia64_safe_type (insn
);
9054 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
9056 index_to_bundle_states
[insn_num
] = NULL
;
9057 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
9059 curr_state
= next_state
)
9061 pos
= curr_state
->accumulated_insns_num
% 3;
9062 next_state
= curr_state
->next
;
9063 /* We must fill up the current bundle in order to start a
9064 subsequent asm insn in a new bundle. Asm insn is always
9065 placed in a separate bundle. */
9067 = (next_insn
!= NULL_RTX
9068 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
9069 && unknown_for_bundling_p (next_insn
));
9070 /* We may fill up the current bundle if it is the cycle end
9071 without a group barrier. */
9073 = (only_bundle_end_p
|| next_insn
== NULL_RTX
9074 || (GET_MODE (next_insn
) == TImode
9075 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
9076 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
9078 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
9080 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
9082 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
9085 gcc_assert (index_to_bundle_states
[insn_num
]);
9086 for (curr_state
= index_to_bundle_states
[insn_num
];
9088 curr_state
= curr_state
->next
)
9089 if (verbose
>= 2 && dump
)
9091 /* This structure is taken from generated code of the
9092 pipeline hazard recognizer (see file insn-attrtab.c).
9093 Please don't forget to change the structure if a new
9094 automaton is added to .md file. */
9097 unsigned short one_automaton_state
;
9098 unsigned short oneb_automaton_state
;
9099 unsigned short two_automaton_state
;
9100 unsigned short twob_automaton_state
;
9105 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9106 curr_state
->unique_num
,
9107 (curr_state
->originator
== NULL
9108 ? -1 : curr_state
->originator
->unique_num
),
9110 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9111 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9112 curr_state
->middle_bundle_stops
,
9113 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9118 /* We should find a solution because the 2nd insn scheduling has
9120 gcc_assert (index_to_bundle_states
[insn_num
]);
9121 /* Find a state corresponding to the best insn sequence. */
9123 for (curr_state
= index_to_bundle_states
[insn_num
];
9125 curr_state
= curr_state
->next
)
9126 /* We are just looking at the states with fully filled up last
9127 bundle. The first we prefer insn sequences with minimal cost
9128 then with minimal inserted nops and finally with branch insns
9129 placed in the 3rd slots. */
9130 if (curr_state
->accumulated_insns_num
% 3 == 0
9131 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
9132 || (best_state
->cost
== curr_state
->cost
9133 && (curr_state
->accumulated_insns_num
9134 < best_state
->accumulated_insns_num
9135 || (curr_state
->accumulated_insns_num
9136 == best_state
->accumulated_insns_num
9137 && (curr_state
->branch_deviation
9138 < best_state
->branch_deviation
9139 || (curr_state
->branch_deviation
9140 == best_state
->branch_deviation
9141 && curr_state
->middle_bundle_stops
9142 < best_state
->middle_bundle_stops
)))))))
9143 best_state
= curr_state
;
9144 /* Second (backward) pass: adding nops and templates. */
9145 gcc_assert (best_state
);
9146 insn_num
= best_state
->before_nops_num
;
9147 template0
= template1
= -1;
9148 for (curr_state
= best_state
;
9149 curr_state
->originator
!= NULL
;
9150 curr_state
= curr_state
->originator
)
9152 insn
= curr_state
->insn
;
9153 asm_p
= unknown_for_bundling_p (insn
);
9155 if (verbose
>= 2 && dump
)
9159 unsigned short one_automaton_state
;
9160 unsigned short oneb_automaton_state
;
9161 unsigned short two_automaton_state
;
9162 unsigned short twob_automaton_state
;
9167 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9168 curr_state
->unique_num
,
9169 (curr_state
->originator
== NULL
9170 ? -1 : curr_state
->originator
->unique_num
),
9172 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9173 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9174 curr_state
->middle_bundle_stops
,
9175 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9178 /* Find the position in the current bundle window. The window can
9179 contain at most two bundles. Two bundle window means that
9180 the processor will make two bundle rotation. */
9181 max_pos
= get_max_pos (curr_state
->dfa_state
);
9183 /* The following (negative template number) means that the
9184 processor did one bundle rotation. */
9185 || (max_pos
== 3 && template0
< 0))
9187 /* We are at the end of the window -- find template(s) for
9191 template0
= get_template (curr_state
->dfa_state
, 3);
9194 template1
= get_template (curr_state
->dfa_state
, 3);
9195 template0
= get_template (curr_state
->dfa_state
, 6);
9198 if (max_pos
> 3 && template1
< 0)
9199 /* It may happen when we have the stop inside a bundle. */
9201 gcc_assert (pos
<= 3);
9202 template1
= get_template (curr_state
->dfa_state
, 3);
9206 /* Emit nops after the current insn. */
9207 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
9210 emit_insn_after (nop
, insn
);
9212 gcc_assert (pos
>= 0);
9215 /* We are at the start of a bundle: emit the template
9216 (it should be defined). */
9217 gcc_assert (template0
>= 0);
9218 ia64_add_bundle_selector_before (template0
, nop
);
9219 /* If we have two bundle window, we make one bundle
9220 rotation. Otherwise template0 will be undefined
9221 (negative value). */
9222 template0
= template1
;
9226 /* Move the position backward in the window. Group barrier has
9227 no slot. Asm insn takes all bundle. */
9228 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9229 && !unknown_for_bundling_p (insn
))
9231 /* Long insn takes 2 slots. */
9232 if (ia64_safe_type (insn
) == TYPE_L
)
9234 gcc_assert (pos
>= 0);
9236 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9237 && !unknown_for_bundling_p (insn
))
9239 /* The current insn is at the bundle start: emit the
9241 gcc_assert (template0
>= 0);
9242 ia64_add_bundle_selector_before (template0
, insn
);
9243 b
= PREV_INSN (insn
);
9245 /* See comment above in analogous place for emitting nops
9247 template0
= template1
;
9250 /* Emit nops after the current insn. */
9251 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
9254 ia64_emit_insn_before (nop
, insn
);
9255 nop
= PREV_INSN (insn
);
9258 gcc_assert (pos
>= 0);
9261 /* See comment above in analogous place for emitting nops
9263 gcc_assert (template0
>= 0);
9264 ia64_add_bundle_selector_before (template0
, insn
);
9265 b
= PREV_INSN (insn
);
9267 template0
= template1
;
9273 #ifdef ENABLE_CHECKING
9275 /* Assert right calculation of middle_bundle_stops. */
9276 int num
= best_state
->middle_bundle_stops
;
9277 bool start_bundle
= true, end_bundle
= false;
9279 for (insn
= NEXT_INSN (prev_head_insn
);
9280 insn
&& insn
!= tail
;
9281 insn
= NEXT_INSN (insn
))
9285 if (recog_memoized (insn
) == CODE_FOR_bundle_selector
)
9286 start_bundle
= true;
9291 for (next_insn
= NEXT_INSN (insn
);
9292 next_insn
&& next_insn
!= tail
;
9293 next_insn
= NEXT_INSN (next_insn
))
9294 if (INSN_P (next_insn
)
9295 && (ia64_safe_itanium_class (next_insn
)
9296 != ITANIUM_CLASS_IGNORE
9297 || recog_memoized (next_insn
)
9298 == CODE_FOR_bundle_selector
)
9299 && GET_CODE (PATTERN (next_insn
)) != USE
9300 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
9303 end_bundle
= next_insn
== NULL_RTX
9304 || next_insn
== tail
9305 || (INSN_P (next_insn
)
9306 && recog_memoized (next_insn
)
9307 == CODE_FOR_bundle_selector
);
9308 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
9309 && !start_bundle
&& !end_bundle
9311 && !unknown_for_bundling_p (next_insn
))
9314 start_bundle
= false;
9318 gcc_assert (num
== 0);
9322 free (index_to_bundle_states
);
9323 finish_bundle_state_table ();
9325 dfa_clean_insn_cache ();
9328 /* The following function is called at the end of scheduling BB or
9329 EBB. After reload, it inserts stop bits and does insn bundling. */
9332 ia64_sched_finish (FILE *dump
, int sched_verbose
)
9335 fprintf (dump
, "// Finishing schedule.\n");
9336 if (!reload_completed
)
9338 if (reload_completed
)
9340 final_emit_insn_group_barriers (dump
);
9341 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
9342 current_sched_info
->next_tail
);
9343 if (sched_verbose
&& dump
)
9344 fprintf (dump
, "// finishing %d-%d\n",
9345 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
9346 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
9352 /* The following function inserts stop bits in scheduled BB or EBB. */
9355 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
9358 int need_barrier_p
= 0;
9359 int seen_good_insn
= 0;
9361 init_insn_group_barriers ();
9363 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
9364 insn
!= current_sched_info
->next_tail
;
9365 insn
= NEXT_INSN (insn
))
9367 if (BARRIER_P (insn
))
9369 rtx last
= prev_active_insn (insn
);
9373 if (JUMP_TABLE_DATA_P (last
))
9374 last
= prev_active_insn (last
);
9375 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9376 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
9378 init_insn_group_barriers ();
9382 else if (NONDEBUG_INSN_P (insn
))
9384 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
9386 init_insn_group_barriers ();
9390 else if (need_barrier_p
|| group_barrier_needed (insn
)
9391 || (mflag_sched_stop_bits_after_every_cycle
9392 && GET_MODE (insn
) == TImode
9395 if (TARGET_EARLY_STOP_BITS
)
9400 last
!= current_sched_info
->prev_head
;
9401 last
= PREV_INSN (last
))
9402 if (INSN_P (last
) && GET_MODE (last
) == TImode
9403 && stops_p
[INSN_UID (last
)])
9405 if (last
== current_sched_info
->prev_head
)
9407 last
= prev_active_insn (last
);
9409 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9410 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9412 init_insn_group_barriers ();
9413 for (last
= NEXT_INSN (last
);
9415 last
= NEXT_INSN (last
))
9418 group_barrier_needed (last
);
9419 if (recog_memoized (last
) >= 0
9420 && important_for_bundling_p (last
))
9426 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9428 init_insn_group_barriers ();
9431 group_barrier_needed (insn
);
9432 if (recog_memoized (insn
) >= 0
9433 && important_for_bundling_p (insn
))
9436 else if (recog_memoized (insn
) >= 0
9437 && important_for_bundling_p (insn
))
9439 need_barrier_p
= (CALL_P (insn
) || unknown_for_bundling_p (insn
));
9446 /* If the following function returns TRUE, we will use the DFA
9450 ia64_first_cycle_multipass_dfa_lookahead (void)
9452 return (reload_completed
? 6 : 4);
9455 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9458 ia64_init_dfa_pre_cycle_insn (void)
9460 if (temp_dfa_state
== NULL
)
9462 dfa_state_size
= state_size ();
9463 temp_dfa_state
= xmalloc (dfa_state_size
);
9464 prev_cycle_state
= xmalloc (dfa_state_size
);
9466 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
9467 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
9468 recog_memoized (dfa_pre_cycle_insn
);
9469 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9470 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
9471 recog_memoized (dfa_stop_insn
);
9474 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9475 used by the DFA insn scheduler. */
9478 ia64_dfa_pre_cycle_insn (void)
9480 return dfa_pre_cycle_insn
;
9483 /* The following function returns TRUE if PRODUCER (of type ilog or
9484 ld) produces address for CONSUMER (of type st or stf). */
9487 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
9491 gcc_assert (producer
&& consumer
);
9492 dest
= ia64_single_set (producer
);
9494 reg
= SET_DEST (dest
);
9496 if (GET_CODE (reg
) == SUBREG
)
9497 reg
= SUBREG_REG (reg
);
9498 gcc_assert (GET_CODE (reg
) == REG
);
9500 dest
= ia64_single_set (consumer
);
9502 mem
= SET_DEST (dest
);
9503 gcc_assert (mem
&& GET_CODE (mem
) == MEM
);
9504 return reg_mentioned_p (reg
, mem
);
9507 /* The following function returns TRUE if PRODUCER (of type ilog or
9508 ld) produces address for CONSUMER (of type ld or fld). */
9511 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
9513 rtx dest
, src
, reg
, mem
;
9515 gcc_assert (producer
&& consumer
);
9516 dest
= ia64_single_set (producer
);
9518 reg
= SET_DEST (dest
);
9520 if (GET_CODE (reg
) == SUBREG
)
9521 reg
= SUBREG_REG (reg
);
9522 gcc_assert (GET_CODE (reg
) == REG
);
9524 src
= ia64_single_set (consumer
);
9526 mem
= SET_SRC (src
);
9529 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
9530 mem
= XVECEXP (mem
, 0, 0);
9531 else if (GET_CODE (mem
) == IF_THEN_ELSE
)
9532 /* ??? Is this bypass necessary for ld.c? */
9534 gcc_assert (XINT (XEXP (XEXP (mem
, 0), 0), 1) == UNSPEC_LDCCLR
);
9535 mem
= XEXP (mem
, 1);
9538 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
9539 mem
= XEXP (mem
, 0);
9541 if (GET_CODE (mem
) == UNSPEC
)
9543 int c
= XINT (mem
, 1);
9545 gcc_assert (c
== UNSPEC_LDA
|| c
== UNSPEC_LDS
|| c
== UNSPEC_LDS_A
9546 || c
== UNSPEC_LDSA
);
9547 mem
= XVECEXP (mem
, 0, 0);
9550 /* Note that LO_SUM is used for GOT loads. */
9551 gcc_assert (GET_CODE (mem
) == LO_SUM
|| GET_CODE (mem
) == MEM
);
9553 return reg_mentioned_p (reg
, mem
);
9556 /* The following function returns TRUE if INSN produces address for a
9557 load/store insn. We will place such insns into M slot because it
9558 decreases its latency time. */
9561 ia64_produce_address_p (rtx insn
)
9567 /* Emit pseudo-ops for the assembler to describe predicate relations.
9568 At present this assumes that we only consider predicate pairs to
9569 be mutex, and that the assembler can deduce proper values from
9570 straight-line code. */
9573 emit_predicate_relation_info (void)
9577 FOR_EACH_BB_REVERSE (bb
)
9580 rtx head
= BB_HEAD (bb
);
9582 /* We only need such notes at code labels. */
9583 if (! LABEL_P (head
))
9585 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head
)))
9586 head
= NEXT_INSN (head
);
9588 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9589 grabbing the entire block of predicate registers. */
9590 for (r
= PR_REG (2); r
< PR_REG (64); r
+= 2)
9591 if (REGNO_REG_SET_P (df_get_live_in (bb
), r
))
9593 rtx p
= gen_rtx_REG (BImode
, r
);
9594 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
9595 if (head
== BB_END (bb
))
9601 /* Look for conditional calls that do not return, and protect predicate
9602 relations around them. Otherwise the assembler will assume the call
9603 returns, and complain about uses of call-clobbered predicates after
9605 FOR_EACH_BB_REVERSE (bb
)
9607 rtx insn
= BB_HEAD (bb
);
9612 && GET_CODE (PATTERN (insn
)) == COND_EXEC
9613 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
9615 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
9616 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
9617 if (BB_HEAD (bb
) == insn
)
9619 if (BB_END (bb
) == insn
)
9623 if (insn
== BB_END (bb
))
9625 insn
= NEXT_INSN (insn
);
9630 /* Perform machine dependent operations on the rtl chain INSNS. */
9635 /* We are freeing block_for_insn in the toplev to keep compatibility
9636 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9637 compute_bb_for_insn ();
9639 /* If optimizing, we'll have split before scheduling. */
9643 if (optimize
&& flag_schedule_insns_after_reload
9644 && dbg_cnt (ia64_sched2
))
9647 timevar_push (TV_SCHED2
);
9648 ia64_final_schedule
= 1;
9650 /* We can't let modulo-sched prevent us from scheduling any bbs,
9651 since we need the final schedule to produce bundle information. */
9653 bb
->flags
&= ~BB_DISABLE_SCHEDULE
;
9655 initiate_bundle_states ();
9656 ia64_nop
= make_insn_raw (gen_nop ());
9657 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
9658 recog_memoized (ia64_nop
);
9659 clocks_length
= get_max_uid () + 1;
9660 stops_p
= XCNEWVEC (char, clocks_length
);
9662 if (ia64_tune
== PROCESSOR_ITANIUM2
)
9664 pos_1
= get_cpu_unit_code ("2_1");
9665 pos_2
= get_cpu_unit_code ("2_2");
9666 pos_3
= get_cpu_unit_code ("2_3");
9667 pos_4
= get_cpu_unit_code ("2_4");
9668 pos_5
= get_cpu_unit_code ("2_5");
9669 pos_6
= get_cpu_unit_code ("2_6");
9670 _0mii_
= get_cpu_unit_code ("2b_0mii.");
9671 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
9672 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
9673 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
9674 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
9675 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
9676 _0mib_
= get_cpu_unit_code ("2b_0mib.");
9677 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
9678 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
9679 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
9680 _1mii_
= get_cpu_unit_code ("2b_1mii.");
9681 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
9682 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
9683 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
9684 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
9685 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
9686 _1mib_
= get_cpu_unit_code ("2b_1mib.");
9687 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
9688 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
9689 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
9693 pos_1
= get_cpu_unit_code ("1_1");
9694 pos_2
= get_cpu_unit_code ("1_2");
9695 pos_3
= get_cpu_unit_code ("1_3");
9696 pos_4
= get_cpu_unit_code ("1_4");
9697 pos_5
= get_cpu_unit_code ("1_5");
9698 pos_6
= get_cpu_unit_code ("1_6");
9699 _0mii_
= get_cpu_unit_code ("1b_0mii.");
9700 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
9701 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
9702 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
9703 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
9704 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
9705 _0mib_
= get_cpu_unit_code ("1b_0mib.");
9706 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
9707 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
9708 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
9709 _1mii_
= get_cpu_unit_code ("1b_1mii.");
9710 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
9711 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
9712 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
9713 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
9714 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
9715 _1mib_
= get_cpu_unit_code ("1b_1mib.");
9716 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
9717 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
9718 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
9721 if (flag_selective_scheduling2
9722 && !maybe_skip_selective_scheduling ())
9723 run_selective_scheduling ();
9727 /* Redo alignment computation, as it might gone wrong. */
9728 compute_alignments ();
9730 /* We cannot reuse this one because it has been corrupted by the
9732 finish_bundle_states ();
9735 emit_insn_group_barriers (dump_file
);
9737 ia64_final_schedule
= 0;
9738 timevar_pop (TV_SCHED2
);
9741 emit_all_insn_group_barriers (dump_file
);
9745 /* A call must not be the last instruction in a function, so that the
9746 return address is still within the function, so that unwinding works
9747 properly. Note that IA-64 differs from dwarf2 on this point. */
9748 if (ia64_except_unwind_info (&global_options
) == UI_TARGET
)
9753 insn
= get_last_insn ();
9754 if (! INSN_P (insn
))
9755 insn
= prev_active_insn (insn
);
9758 /* Skip over insns that expand to nothing. */
9759 while (NONJUMP_INSN_P (insn
)
9760 && get_attr_empty (insn
) == EMPTY_YES
)
9762 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
9763 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
9765 insn
= prev_active_insn (insn
);
9770 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9771 emit_insn (gen_break_f ());
9772 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9777 emit_predicate_relation_info ();
9779 if (flag_var_tracking
)
9781 timevar_push (TV_VAR_TRACKING
);
9782 variable_tracking_main ();
9783 timevar_pop (TV_VAR_TRACKING
);
9785 df_finish_pass (false);
9788 /* Return true if REGNO is used by the epilogue. */
9791 ia64_epilogue_uses (int regno
)
9796 /* With a call to a function in another module, we will write a new
9797 value to "gp". After returning from such a call, we need to make
9798 sure the function restores the original gp-value, even if the
9799 function itself does not use the gp anymore. */
9800 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
9802 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9803 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9804 /* For functions defined with the syscall_linkage attribute, all
9805 input registers are marked as live at all function exits. This
9806 prevents the register allocator from using the input registers,
9807 which in turn makes it possible to restart a system call after
9808 an interrupt without having to save/restore the input registers.
9809 This also prevents kernel data from leaking to application code. */
9810 return lookup_attribute ("syscall_linkage",
9811 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
9814 /* Conditional return patterns can't represent the use of `b0' as
9815 the return address, so we force the value live this way. */
9819 /* Likewise for ar.pfs, which is used by br.ret. */
9827 /* Return true if REGNO is used by the frame unwinder. */
9830 ia64_eh_uses (int regno
)
9834 if (! reload_completed
)
9840 for (r
= reg_save_b0
; r
<= reg_save_ar_lc
; r
++)
9841 if (regno
== current_frame_info
.r
[r
]
9842 || regno
== emitted_frame_related_regs
[r
])
9848 /* Return true if this goes in small data/bss. */
9850 /* ??? We could also support own long data here. Generating movl/add/ld8
9851 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9852 code faster because there is one less load. This also includes incomplete
9853 types which can't go in sdata/sbss. */
9856 ia64_in_small_data_p (const_tree exp
)
9858 if (TARGET_NO_SDATA
)
9861 /* We want to merge strings, so we never consider them small data. */
9862 if (TREE_CODE (exp
) == STRING_CST
)
9865 /* Functions are never small data. */
9866 if (TREE_CODE (exp
) == FUNCTION_DECL
)
9869 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
9871 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
9873 if (strcmp (section
, ".sdata") == 0
9874 || strncmp (section
, ".sdata.", 7) == 0
9875 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
9876 || strcmp (section
, ".sbss") == 0
9877 || strncmp (section
, ".sbss.", 6) == 0
9878 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
9883 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
9885 /* If this is an incomplete type with size 0, then we can't put it
9886 in sdata because it might be too big when completed. */
9887 if (size
> 0 && size
<= ia64_section_threshold
)
9894 /* Output assembly directives for prologue regions. */
9896 /* The current basic block number. */
9898 static bool last_block
;
9900 /* True if we need a copy_state command at the start of the next block. */
9902 static bool need_copy_state
;
9904 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9905 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9908 /* The function emits unwind directives for the start of an epilogue. */
9911 process_epilogue (FILE *asm_out_file
, rtx insn ATTRIBUTE_UNUSED
,
9912 bool unwind
, bool frame ATTRIBUTE_UNUSED
)
9914 /* If this isn't the last block of the function, then we need to label the
9915 current state, and copy it back in at the start of the next block. */
9920 fprintf (asm_out_file
, "\t.label_state %d\n",
9921 ++cfun
->machine
->state_num
);
9922 need_copy_state
= true;
9926 fprintf (asm_out_file
, "\t.restore sp\n");
9929 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9932 process_cfa_adjust_cfa (FILE *asm_out_file
, rtx pat
, rtx insn
,
9933 bool unwind
, bool frame
)
9935 rtx dest
= SET_DEST (pat
);
9936 rtx src
= SET_SRC (pat
);
9938 if (dest
== stack_pointer_rtx
)
9940 if (GET_CODE (src
) == PLUS
)
9942 rtx op0
= XEXP (src
, 0);
9943 rtx op1
= XEXP (src
, 1);
9945 gcc_assert (op0
== dest
&& GET_CODE (op1
) == CONST_INT
);
9947 if (INTVAL (op1
) < 0)
9949 gcc_assert (!frame_pointer_needed
);
9951 fprintf (asm_out_file
,
9952 "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
9956 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9960 gcc_assert (src
== hard_frame_pointer_rtx
);
9961 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9964 else if (dest
== hard_frame_pointer_rtx
)
9966 gcc_assert (src
== stack_pointer_rtx
);
9967 gcc_assert (frame_pointer_needed
);
9970 fprintf (asm_out_file
, "\t.vframe r%d\n",
9971 ia64_dbx_register_number (REGNO (dest
)));
9977 /* This function processes a SET pattern for REG_CFA_REGISTER. */
9980 process_cfa_register (FILE *asm_out_file
, rtx pat
, bool unwind
)
9982 rtx dest
= SET_DEST (pat
);
9983 rtx src
= SET_SRC (pat
);
9984 int dest_regno
= REGNO (dest
);
9989 /* Saving return address pointer. */
9991 fprintf (asm_out_file
, "\t.save rp, r%d\n",
9992 ia64_dbx_register_number (dest_regno
));
9996 src_regno
= REGNO (src
);
10001 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_pr
]);
10003 fprintf (asm_out_file
, "\t.save pr, r%d\n",
10004 ia64_dbx_register_number (dest_regno
));
10007 case AR_UNAT_REGNUM
:
10008 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_unat
]);
10010 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
10011 ia64_dbx_register_number (dest_regno
));
10015 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_lc
]);
10017 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
10018 ia64_dbx_register_number (dest_regno
));
10022 /* Everything else should indicate being stored to memory. */
10023 gcc_unreachable ();
10027 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10030 process_cfa_offset (FILE *asm_out_file
, rtx pat
, bool unwind
)
10032 rtx dest
= SET_DEST (pat
);
10033 rtx src
= SET_SRC (pat
);
10034 int src_regno
= REGNO (src
);
10035 const char *saveop
;
10039 gcc_assert (MEM_P (dest
));
10040 if (GET_CODE (XEXP (dest
, 0)) == REG
)
10042 base
= XEXP (dest
, 0);
10047 gcc_assert (GET_CODE (XEXP (dest
, 0)) == PLUS
10048 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
);
10049 base
= XEXP (XEXP (dest
, 0), 0);
10050 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
10053 if (base
== hard_frame_pointer_rtx
)
10055 saveop
= ".savepsp";
10060 gcc_assert (base
== stack_pointer_rtx
);
10061 saveop
= ".savesp";
10064 src_regno
= REGNO (src
);
10068 gcc_assert (!current_frame_info
.r
[reg_save_b0
]);
10070 fprintf (asm_out_file
, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC
"\n",
10075 gcc_assert (!current_frame_info
.r
[reg_save_pr
]);
10077 fprintf (asm_out_file
, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC
"\n",
10082 gcc_assert (!current_frame_info
.r
[reg_save_ar_lc
]);
10084 fprintf (asm_out_file
, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC
"\n",
10088 case AR_PFS_REGNUM
:
10089 gcc_assert (!current_frame_info
.r
[reg_save_ar_pfs
]);
10091 fprintf (asm_out_file
, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC
"\n",
10095 case AR_UNAT_REGNUM
:
10096 gcc_assert (!current_frame_info
.r
[reg_save_ar_unat
]);
10098 fprintf (asm_out_file
, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC
"\n",
10107 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
10108 1 << (src_regno
- GR_REG (4)));
10117 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
10118 1 << (src_regno
- BR_REG (1)));
10126 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
10127 1 << (src_regno
- FR_REG (2)));
10130 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10131 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10132 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10133 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10135 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
10136 1 << (src_regno
- FR_REG (12)));
10140 /* ??? For some reason we mark other general registers, even those
10141 we can't represent in the unwind info. Ignore them. */
10146 /* This function looks at a single insn and emits any directives
10147 required to unwind this insn. */
10150 ia64_asm_unwind_emit (FILE *asm_out_file
, rtx insn
)
10152 bool unwind
= ia64_except_unwind_info (&global_options
) == UI_TARGET
;
10153 bool frame
= dwarf2out_do_frame ();
10157 if (!unwind
&& !frame
)
10160 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
10162 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
10164 /* Restore unwind state from immediately before the epilogue. */
10165 if (need_copy_state
)
10169 fprintf (asm_out_file
, "\t.body\n");
10170 fprintf (asm_out_file
, "\t.copy_state %d\n",
10171 cfun
->machine
->state_num
);
10173 need_copy_state
= false;
10177 if (NOTE_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
10180 /* Look for the ALLOC insn. */
10181 if (INSN_CODE (insn
) == CODE_FOR_alloc
)
10183 rtx dest
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
10184 int dest_regno
= REGNO (dest
);
10186 /* If this is the final destination for ar.pfs, then this must
10187 be the alloc in the prologue. */
10188 if (dest_regno
== current_frame_info
.r
[reg_save_ar_pfs
])
10191 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
10192 ia64_dbx_register_number (dest_regno
));
10196 /* This must be an alloc before a sibcall. We must drop the
10197 old frame info. The easiest way to drop the old frame
10198 info is to ensure we had a ".restore sp" directive
10199 followed by a new prologue. If the procedure doesn't
10200 have a memory-stack frame, we'll issue a dummy ".restore
10202 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
10203 /* if haven't done process_epilogue() yet, do it now */
10204 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
10206 fprintf (asm_out_file
, "\t.prologue\n");
10211 handled_one
= false;
10212 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
10213 switch (REG_NOTE_KIND (note
))
10215 case REG_CFA_ADJUST_CFA
:
10216 pat
= XEXP (note
, 0);
10218 pat
= PATTERN (insn
);
10219 process_cfa_adjust_cfa (asm_out_file
, pat
, insn
, unwind
, frame
);
10220 handled_one
= true;
10223 case REG_CFA_OFFSET
:
10224 pat
= XEXP (note
, 0);
10226 pat
= PATTERN (insn
);
10227 process_cfa_offset (asm_out_file
, pat
, unwind
);
10228 handled_one
= true;
10231 case REG_CFA_REGISTER
:
10232 pat
= XEXP (note
, 0);
10234 pat
= PATTERN (insn
);
10235 process_cfa_register (asm_out_file
, pat
, unwind
);
10236 handled_one
= true;
10239 case REG_FRAME_RELATED_EXPR
:
10240 case REG_CFA_DEF_CFA
:
10241 case REG_CFA_EXPRESSION
:
10242 case REG_CFA_RESTORE
:
10243 case REG_CFA_SET_VDRAP
:
10244 /* Not used in the ia64 port. */
10245 gcc_unreachable ();
10248 /* Not a frame-related note. */
10252 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10253 explicit action to take. No guessing required. */
10254 gcc_assert (handled_one
);
10257 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10260 ia64_asm_emit_except_personality (rtx personality
)
10262 fputs ("\t.personality\t", asm_out_file
);
10263 output_addr_const (asm_out_file
, personality
);
10264 fputc ('\n', asm_out_file
);
10267 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10270 ia64_asm_init_sections (void)
10272 exception_section
= get_unnamed_section (0, output_section_asm_op
,
10276 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10278 static enum unwind_info_type
10279 ia64_debug_unwind_info (void)
10287 IA64_BUILTIN_COPYSIGNQ
,
10288 IA64_BUILTIN_FABSQ
,
10289 IA64_BUILTIN_FLUSHRS
,
10291 IA64_BUILTIN_HUGE_VALQ
,
10295 static GTY(()) tree ia64_builtins
[(int) IA64_BUILTIN_max
];
10298 ia64_init_builtins (void)
10304 /* The __fpreg type. */
10305 fpreg_type
= make_node (REAL_TYPE
);
10306 TYPE_PRECISION (fpreg_type
) = 82;
10307 layout_type (fpreg_type
);
10308 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
10310 /* The __float80 type. */
10311 float80_type
= make_node (REAL_TYPE
);
10312 TYPE_PRECISION (float80_type
) = 80;
10313 layout_type (float80_type
);
10314 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
10316 /* The __float128 type. */
10320 tree float128_type
= make_node (REAL_TYPE
);
10322 TYPE_PRECISION (float128_type
) = 128;
10323 layout_type (float128_type
);
10324 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
10326 /* TFmode support builtins. */
10327 ftype
= build_function_type_list (float128_type
, NULL_TREE
);
10328 decl
= add_builtin_function ("__builtin_infq", ftype
,
10329 IA64_BUILTIN_INFQ
, BUILT_IN_MD
,
10331 ia64_builtins
[IA64_BUILTIN_INFQ
] = decl
;
10333 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
10334 IA64_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
10336 ia64_builtins
[IA64_BUILTIN_HUGE_VALQ
] = decl
;
10338 ftype
= build_function_type_list (float128_type
,
10341 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
10342 IA64_BUILTIN_FABSQ
, BUILT_IN_MD
,
10343 "__fabstf2", NULL_TREE
);
10344 TREE_READONLY (decl
) = 1;
10345 ia64_builtins
[IA64_BUILTIN_FABSQ
] = decl
;
10347 ftype
= build_function_type_list (float128_type
,
10351 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
10352 IA64_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
10353 "__copysigntf3", NULL_TREE
);
10354 TREE_READONLY (decl
) = 1;
10355 ia64_builtins
[IA64_BUILTIN_COPYSIGNQ
] = decl
;
10358 /* Under HPUX, this is a synonym for "long double". */
10359 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
10362 /* Fwrite on VMS is non-standard. */
10363 #if TARGET_ABI_OPEN_VMS
10364 vms_patch_builtins ();
10367 #define def_builtin(name, type, code) \
10368 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10371 decl
= def_builtin ("__builtin_ia64_bsp",
10372 build_function_type_list (ptr_type_node
, NULL_TREE
),
10374 ia64_builtins
[IA64_BUILTIN_BSP
] = decl
;
10376 decl
= def_builtin ("__builtin_ia64_flushrs",
10377 build_function_type_list (void_type_node
, NULL_TREE
),
10378 IA64_BUILTIN_FLUSHRS
);
10379 ia64_builtins
[IA64_BUILTIN_FLUSHRS
] = decl
;
10385 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
10386 set_user_assembler_name (decl
, "_Isfinite");
10387 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
10388 set_user_assembler_name (decl
, "_Isfinitef");
10389 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEL
)) != NULL_TREE
)
10390 set_user_assembler_name (decl
, "_Isfinitef128");
10395 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10396 enum machine_mode mode ATTRIBUTE_UNUSED
,
10397 int ignore ATTRIBUTE_UNUSED
)
10399 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10400 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10404 case IA64_BUILTIN_BSP
:
10405 if (! target
|| ! register_operand (target
, DImode
))
10406 target
= gen_reg_rtx (DImode
);
10407 emit_insn (gen_bsp_value (target
));
10408 #ifdef POINTERS_EXTEND_UNSIGNED
10409 target
= convert_memory_address (ptr_mode
, target
);
10413 case IA64_BUILTIN_FLUSHRS
:
10414 emit_insn (gen_flushrs ());
10417 case IA64_BUILTIN_INFQ
:
10418 case IA64_BUILTIN_HUGE_VALQ
:
10420 enum machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
10421 REAL_VALUE_TYPE inf
;
10425 tmp
= CONST_DOUBLE_FROM_REAL_VALUE (inf
, target_mode
);
10427 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
10430 target
= gen_reg_rtx (target_mode
);
10432 emit_move_insn (target
, tmp
);
10436 case IA64_BUILTIN_FABSQ
:
10437 case IA64_BUILTIN_COPYSIGNQ
:
10438 return expand_call (exp
, target
, ignore
);
10441 gcc_unreachable ();
10447 /* Return the ia64 builtin for CODE. */
10450 ia64_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10452 if (code
>= IA64_BUILTIN_max
)
10453 return error_mark_node
;
10455 return ia64_builtins
[code
];
10458 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10459 most significant bits of the stack slot. */
10462 ia64_hpux_function_arg_padding (enum machine_mode mode
, const_tree type
)
10464 /* Exception to normal case for structures/unions/etc. */
10466 if (type
&& AGGREGATE_TYPE_P (type
)
10467 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
10470 /* Fall back to the default. */
10471 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
10474 /* Emit text to declare externally defined variables and functions, because
10475 the Intel assembler does not support undefined externals. */
10478 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
10480 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10481 set in order to avoid putting out names that are never really
10483 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
10485 /* maybe_assemble_visibility will return 1 if the assembler
10486 visibility directive is output. */
10487 int need_visibility
= ((*targetm
.binds_local_p
) (decl
)
10488 && maybe_assemble_visibility (decl
));
10490 /* GNU as does not need anything here, but the HP linker does
10491 need something for external functions. */
10492 if ((TARGET_HPUX_LD
|| !TARGET_GNU_AS
)
10493 && TREE_CODE (decl
) == FUNCTION_DECL
)
10494 (*targetm
.asm_out
.globalize_decl_name
) (file
, decl
);
10495 else if (need_visibility
&& !TARGET_GNU_AS
)
10496 (*targetm
.asm_out
.globalize_label
) (file
, name
);
10500 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10501 modes of word_mode and larger. Rename the TFmode libfuncs using the
10502 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10503 backward compatibility. */
10506 ia64_init_libfuncs (void)
10508 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
10509 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
10510 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
10511 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
10513 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
10514 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
10515 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
10516 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
10517 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
10519 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
10520 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
10521 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
10522 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
10523 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
10524 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
10526 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
10527 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
10528 set_conv_libfunc (sfix_optab
, TImode
, TFmode
, "_U_Qfcnvfxt_quad_to_quad");
10529 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
10530 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
10532 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
10533 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
10534 set_conv_libfunc (sfloat_optab
, TFmode
, TImode
, "_U_Qfcnvxf_quad_to_quad");
10535 /* HP-UX 11.23 libc does not have a function for unsigned
10536 SImode-to-TFmode conversion. */
10537 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_U_Qfcnvxuf_dbl_to_quad");
10540 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10543 ia64_hpux_init_libfuncs (void)
10545 ia64_init_libfuncs ();
10547 /* The HP SI millicode division and mod functions expect DI arguments.
10548 By turning them off completely we avoid using both libgcc and the
10549 non-standard millicode routines and use the HP DI millicode routines
10552 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10553 set_optab_libfunc (udiv_optab
, SImode
, 0);
10554 set_optab_libfunc (smod_optab
, SImode
, 0);
10555 set_optab_libfunc (umod_optab
, SImode
, 0);
10557 set_optab_libfunc (sdiv_optab
, DImode
, "__milli_divI");
10558 set_optab_libfunc (udiv_optab
, DImode
, "__milli_divU");
10559 set_optab_libfunc (smod_optab
, DImode
, "__milli_remI");
10560 set_optab_libfunc (umod_optab
, DImode
, "__milli_remU");
10562 /* HP-UX libc has TF min/max/abs routines in it. */
10563 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
10564 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
10565 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
10567 /* ia64_expand_compare uses this. */
10568 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
10570 /* These should never be used. */
10571 set_optab_libfunc (eq_optab
, TFmode
, 0);
10572 set_optab_libfunc (ne_optab
, TFmode
, 0);
10573 set_optab_libfunc (gt_optab
, TFmode
, 0);
10574 set_optab_libfunc (ge_optab
, TFmode
, 0);
10575 set_optab_libfunc (lt_optab
, TFmode
, 0);
10576 set_optab_libfunc (le_optab
, TFmode
, 0);
10579 /* Rename the division and modulus functions in VMS. */
10582 ia64_vms_init_libfuncs (void)
10584 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10585 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10586 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10587 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10588 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10589 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10590 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10591 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10592 abort_libfunc
= init_one_libfunc ("decc$abort");
10593 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
10594 #ifdef MEM_LIBFUNCS_INIT
10599 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10600 the HPUX conventions. */
10603 ia64_sysv4_init_libfuncs (void)
10605 ia64_init_libfuncs ();
10607 /* These functions are not part of the HPUX TFmode interface. We
10608 use them instead of _U_Qfcmp, which doesn't work the way we
10610 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
10611 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
10612 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
10613 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
10614 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
10615 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
10617 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10618 glibc doesn't have them. */
10624 ia64_soft_fp_init_libfuncs (void)
10629 ia64_vms_valid_pointer_mode (enum machine_mode mode
)
10631 return (mode
== SImode
|| mode
== DImode
);
10634 /* For HPUX, it is illegal to have relocations in shared segments. */
10637 ia64_hpux_reloc_rw_mask (void)
10642 /* For others, relax this so that relocations to local data goes in
10643 read-only segments, but we still cannot allow global relocations
10644 in read-only segments. */
10647 ia64_reloc_rw_mask (void)
10649 return flag_pic
? 3 : 2;
10652 /* Return the section to use for X. The only special thing we do here
10653 is to honor small data. */
10656 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
10657 unsigned HOST_WIDE_INT align
)
10659 if (GET_MODE_SIZE (mode
) > 0
10660 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
10661 && !TARGET_NO_SDATA
)
10662 return sdata_section
;
10664 return default_elf_select_rtx_section (mode
, x
, align
);
10667 static unsigned int
10668 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
10670 unsigned int flags
= 0;
10672 if (strcmp (name
, ".sdata") == 0
10673 || strncmp (name
, ".sdata.", 7) == 0
10674 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
10675 || strncmp (name
, ".sdata2.", 8) == 0
10676 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
10677 || strcmp (name
, ".sbss") == 0
10678 || strncmp (name
, ".sbss.", 6) == 0
10679 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
10680 flags
= SECTION_SMALL
;
10682 flags
|= default_section_type_flags (decl
, name
, reloc
);
10686 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10687 structure type and that the address of that type should be passed
10688 in out0, rather than in r8. */
10691 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
10693 tree ret_type
= TREE_TYPE (fntype
);
10695 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10696 as the structure return address parameter, if the return value
10697 type has a non-trivial copy constructor or destructor. It is not
10698 clear if this same convention should be used for other
10699 programming languages. Until G++ 3.4, we incorrectly used r8 for
10700 these return values. */
10701 return (abi_version_at_least (2)
10703 && TYPE_MODE (ret_type
) == BLKmode
10704 && TREE_ADDRESSABLE (ret_type
)
10705 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
10708 /* Output the assembler code for a thunk function. THUNK_DECL is the
10709 declaration for the thunk function itself, FUNCTION is the decl for
10710 the target function. DELTA is an immediate constant offset to be
10711 added to THIS. If VCALL_OFFSET is nonzero, the word at
10712 *(*this + vcall_offset) should be added to THIS. */
10715 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10716 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10719 rtx this_rtx
, insn
, funexp
;
10720 unsigned int this_parmno
;
10721 unsigned int this_regno
;
10724 reload_completed
= 1;
10725 epilogue_completed
= 1;
10727 /* Set things up as ia64_expand_prologue might. */
10728 last_scratch_gr_reg
= 15;
10730 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
10731 current_frame_info
.spill_cfa_off
= -16;
10732 current_frame_info
.n_input_regs
= 1;
10733 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
10735 /* Mark the end of the (empty) prologue. */
10736 emit_note (NOTE_INSN_PROLOGUE_END
);
10738 /* Figure out whether "this" will be the first parameter (the
10739 typical case) or the second parameter (as happens when the
10740 virtual function returns certain class objects). */
10742 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
10744 this_regno
= IN_REG (this_parmno
);
10745 if (!TARGET_REG_NAMES
)
10746 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
10748 this_rtx
= gen_rtx_REG (Pmode
, this_regno
);
10750 /* Apply the constant offset, if required. */
10751 delta_rtx
= GEN_INT (delta
);
10754 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
10755 REG_POINTER (tmp
) = 1;
10756 if (delta
&& satisfies_constraint_I (delta_rtx
))
10758 emit_insn (gen_ptr_extend_plus_imm (this_rtx
, tmp
, delta_rtx
));
10762 emit_insn (gen_ptr_extend (this_rtx
, tmp
));
10766 if (!satisfies_constraint_I (delta_rtx
))
10768 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10769 emit_move_insn (tmp
, delta_rtx
);
10772 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
10775 /* Apply the offset from the vtable, if required. */
10778 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10779 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10783 rtx t
= gen_rtx_REG (ptr_mode
, 2);
10784 REG_POINTER (t
) = 1;
10785 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this_rtx
));
10786 if (satisfies_constraint_I (vcall_offset_rtx
))
10788 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
, vcall_offset_rtx
));
10792 emit_insn (gen_ptr_extend (tmp
, t
));
10795 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
10799 if (!satisfies_constraint_J (vcall_offset_rtx
))
10801 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
10802 emit_move_insn (tmp2
, vcall_offset_rtx
);
10803 vcall_offset_rtx
= tmp2
;
10805 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
10809 emit_insn (gen_zero_extendsidi2 (tmp
, gen_rtx_MEM (ptr_mode
, tmp
)));
10811 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
10813 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
10816 /* Generate a tail call to the target function. */
10817 if (! TREE_USED (function
))
10819 assemble_external (function
);
10820 TREE_USED (function
) = 1;
10822 funexp
= XEXP (DECL_RTL (function
), 0);
10823 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10824 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
10825 insn
= get_last_insn ();
10826 SIBLING_CALL_P (insn
) = 1;
10828 /* Code generation for calls relies on splitting. */
10829 reload_completed
= 1;
10830 epilogue_completed
= 1;
10831 try_split (PATTERN (insn
), insn
, 0);
10835 /* Run just enough of rest_of_compilation to get the insns emitted.
10836 There's not really enough bulk here to make other passes such as
10837 instruction scheduling worth while. Note that use_thunk calls
10838 assemble_start_function and assemble_end_function. */
10840 emit_all_insn_group_barriers (NULL
);
10841 insn
= get_insns ();
10842 shorten_branches (insn
);
10843 final_start_function (insn
, file
, 1);
10844 final (insn
, file
, 1);
10845 final_end_function ();
10847 reload_completed
= 0;
10848 epilogue_completed
= 0;
10851 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10854 ia64_struct_value_rtx (tree fntype
,
10855 int incoming ATTRIBUTE_UNUSED
)
10857 if (TARGET_ABI_OPEN_VMS
||
10858 (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
)))
10860 return gen_rtx_REG (Pmode
, GR_REG (8));
10864 ia64_scalar_mode_supported_p (enum machine_mode mode
)
10890 ia64_vector_mode_supported_p (enum machine_mode mode
)
10907 /* Implement the FUNCTION_PROFILER macro. */
10910 ia64_output_function_profiler (FILE *file
, int labelno
)
10912 bool indirect_call
;
10914 /* If the function needs a static chain and the static chain
10915 register is r15, we use an indirect call so as to bypass
10916 the PLT stub in case the executable is dynamically linked,
10917 because the stub clobbers r15 as per 5.3.6 of the psABI.
10918 We don't need to do that in non canonical PIC mode. */
10920 if (cfun
->static_chain_decl
&& !TARGET_NO_PIC
&& !TARGET_AUTO_PIC
)
10922 gcc_assert (STATIC_CHAIN_REGNUM
== 15);
10923 indirect_call
= true;
10926 indirect_call
= false;
10929 fputs ("\t.prologue 4, r40\n", file
);
10931 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file
);
10932 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file
);
10934 if (NO_PROFILE_COUNTERS
)
10935 fputs ("\tmov out3 = r0\n", file
);
10939 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10941 if (TARGET_AUTO_PIC
)
10942 fputs ("\tmovl out3 = @gprel(", file
);
10944 fputs ("\taddl out3 = @ltoff(", file
);
10945 assemble_name (file
, buf
);
10946 if (TARGET_AUTO_PIC
)
10947 fputs (")\n", file
);
10949 fputs ("), r1\n", file
);
10953 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file
);
10954 fputs ("\t;;\n", file
);
10956 fputs ("\t.save rp, r42\n", file
);
10957 fputs ("\tmov out2 = b0\n", file
);
10959 fputs ("\tld8 r14 = [r14]\n\t;;\n", file
);
10960 fputs ("\t.body\n", file
);
10961 fputs ("\tmov out1 = r1\n", file
);
10964 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file
);
10965 fputs ("\tmov b6 = r16\n", file
);
10966 fputs ("\tld8 r1 = [r14]\n", file
);
10967 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file
);
10970 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file
);
10973 static GTY(()) rtx mcount_func_rtx
;
10975 gen_mcount_func_rtx (void)
10977 if (!mcount_func_rtx
)
10978 mcount_func_rtx
= init_one_libfunc ("_mcount");
10979 return mcount_func_rtx
;
10983 ia64_profile_hook (int labelno
)
10987 if (NO_PROFILE_COUNTERS
)
10988 label
= const0_rtx
;
10992 const char *label_name
;
10993 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10994 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
10995 label
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
10996 SYMBOL_REF_FLAGS (label
) = SYMBOL_FLAG_LOCAL
;
10998 ip
= gen_reg_rtx (Pmode
);
10999 emit_insn (gen_ip_value (ip
));
11000 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL
,
11002 gen_rtx_REG (Pmode
, BR_REG (0)), Pmode
,
11007 /* Return the mangling of TYPE if it is an extended fundamental type. */
11009 static const char *
11010 ia64_mangle_type (const_tree type
)
11012 type
= TYPE_MAIN_VARIANT (type
);
11014 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
11015 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
11018 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11020 if (!TARGET_HPUX
&& TYPE_MODE (type
) == TFmode
)
11022 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11023 an extended mangling. Elsewhere, "e" is available since long
11024 double is 80 bits. */
11025 if (TYPE_MODE (type
) == XFmode
)
11026 return TARGET_HPUX
? "u9__float80" : "e";
11027 if (TYPE_MODE (type
) == RFmode
)
11028 return "u7__fpreg";
11032 /* Return the diagnostic message string if conversion from FROMTYPE to
11033 TOTYPE is not allowed, NULL otherwise. */
11034 static const char *
11035 ia64_invalid_conversion (const_tree fromtype
, const_tree totype
)
11037 /* Reject nontrivial conversion to or from __fpreg. */
11038 if (TYPE_MODE (fromtype
) == RFmode
11039 && TYPE_MODE (totype
) != RFmode
11040 && TYPE_MODE (totype
) != VOIDmode
)
11041 return N_("invalid conversion from %<__fpreg%>");
11042 if (TYPE_MODE (totype
) == RFmode
11043 && TYPE_MODE (fromtype
) != RFmode
)
11044 return N_("invalid conversion to %<__fpreg%>");
11048 /* Return the diagnostic message string if the unary operation OP is
11049 not permitted on TYPE, NULL otherwise. */
11050 static const char *
11051 ia64_invalid_unary_op (int op
, const_tree type
)
11053 /* Reject operations on __fpreg other than unary + or &. */
11054 if (TYPE_MODE (type
) == RFmode
11055 && op
!= CONVERT_EXPR
11056 && op
!= ADDR_EXPR
)
11057 return N_("invalid operation on %<__fpreg%>");
11061 /* Return the diagnostic message string if the binary operation OP is
11062 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11063 static const char *
11064 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
11066 /* Reject operations on __fpreg. */
11067 if (TYPE_MODE (type1
) == RFmode
|| TYPE_MODE (type2
) == RFmode
)
11068 return N_("invalid operation on %<__fpreg%>");
11072 /* HP-UX version_id attribute.
11073 For object foo, if the version_id is set to 1234 put out an alias
11074 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11075 other than an alias statement because it is an illegal symbol name. */
11078 ia64_handle_version_id_attribute (tree
*node ATTRIBUTE_UNUSED
,
11079 tree name ATTRIBUTE_UNUSED
,
11081 int flags ATTRIBUTE_UNUSED
,
11082 bool *no_add_attrs
)
11084 tree arg
= TREE_VALUE (args
);
11086 if (TREE_CODE (arg
) != STRING_CST
)
11088 error("version attribute is not a string");
11089 *no_add_attrs
= true;
11095 /* Target hook for c_mode_for_suffix. */
11097 static enum machine_mode
11098 ia64_c_mode_for_suffix (char suffix
)
11108 static GTY(()) rtx ia64_dconst_0_5_rtx
;
11111 ia64_dconst_0_5 (void)
11113 if (! ia64_dconst_0_5_rtx
)
11115 REAL_VALUE_TYPE rv
;
11116 real_from_string (&rv
, "0.5");
11117 ia64_dconst_0_5_rtx
= const_double_from_real_value (rv
, DFmode
);
11119 return ia64_dconst_0_5_rtx
;
11122 static GTY(()) rtx ia64_dconst_0_375_rtx
;
11125 ia64_dconst_0_375 (void)
11127 if (! ia64_dconst_0_375_rtx
)
11129 REAL_VALUE_TYPE rv
;
11130 real_from_string (&rv
, "0.375");
11131 ia64_dconst_0_375_rtx
= const_double_from_real_value (rv
, DFmode
);
11133 return ia64_dconst_0_375_rtx
;
11136 static enum machine_mode
11137 ia64_get_reg_raw_mode (int regno
)
11139 if (FR_REGNO_P (regno
))
11141 return default_get_reg_raw_mode(regno
);
11144 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11148 ia64_member_type_forces_blk (const_tree
, enum machine_mode mode
)
11150 return TARGET_HPUX
&& mode
== TFmode
;
11153 /* Always default to .text section until HP-UX linker is fixed. */
11155 ATTRIBUTE_UNUSED
static section
*
11156 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED
,
11157 enum node_frequency freq ATTRIBUTE_UNUSED
,
11158 bool startup ATTRIBUTE_UNUSED
,
11159 bool exit ATTRIBUTE_UNUSED
)
11164 /* Construct (set target (vec_select op0 (parallel perm))) and
11165 return true if that's a valid instruction in the active ISA. */
11168 expand_vselect (rtx target
, rtx op0
, const unsigned char *perm
, unsigned nelt
)
11170 rtx rperm
[MAX_VECT_LEN
], x
;
11173 for (i
= 0; i
< nelt
; ++i
)
11174 rperm
[i
] = GEN_INT (perm
[i
]);
11176 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
11177 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
11178 x
= gen_rtx_SET (VOIDmode
, target
, x
);
11181 if (recog_memoized (x
) < 0)
11189 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11192 expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
11193 const unsigned char *perm
, unsigned nelt
)
11195 enum machine_mode v2mode
;
11198 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
11199 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
11200 return expand_vselect (target
, x
, perm
, nelt
);
11203 /* Try to expand a no-op permutation. */
11206 expand_vec_perm_identity (struct expand_vec_perm_d
*d
)
11208 unsigned i
, nelt
= d
->nelt
;
11210 for (i
= 0; i
< nelt
; ++i
)
11211 if (d
->perm
[i
] != i
)
11215 emit_move_insn (d
->target
, d
->op0
);
11220 /* Try to expand D via a shrp instruction. */
11223 expand_vec_perm_shrp (struct expand_vec_perm_d
*d
)
11225 unsigned i
, nelt
= d
->nelt
, shift
, mask
;
11228 /* ??? Don't force V2SFmode into the integer registers. */
11229 if (d
->vmode
== V2SFmode
)
11232 mask
= (d
->one_operand_p
? nelt
- 1 : 2 * nelt
- 1);
11234 shift
= d
->perm
[0];
11235 if (BYTES_BIG_ENDIAN
&& shift
> nelt
)
11238 for (i
= 1; i
< nelt
; ++i
)
11239 if (d
->perm
[i
] != ((shift
+ i
) & mask
))
11245 hi
= shift
< nelt
? d
->op1
: d
->op0
;
11246 lo
= shift
< nelt
? d
->op0
: d
->op1
;
11250 shift
*= GET_MODE_UNIT_SIZE (d
->vmode
) * BITS_PER_UNIT
;
11252 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11253 gcc_assert (IN_RANGE (shift
, 1, 63));
11255 /* Recall that big-endian elements are numbered starting at the top of
11256 the register. Ideally we'd have a shift-left-pair. But since we
11257 don't, convert to a shift the other direction. */
11258 if (BYTES_BIG_ENDIAN
)
11259 shift
= 64 - shift
;
11261 tmp
= gen_reg_rtx (DImode
);
11262 hi
= gen_lowpart (DImode
, hi
);
11263 lo
= gen_lowpart (DImode
, lo
);
11264 emit_insn (gen_shrp (tmp
, hi
, lo
, GEN_INT (shift
)));
11266 emit_move_insn (d
->target
, gen_lowpart (d
->vmode
, tmp
));
11270 /* Try to instantiate D in a single instruction. */
11273 expand_vec_perm_1 (struct expand_vec_perm_d
*d
)
11275 unsigned i
, nelt
= d
->nelt
;
11276 unsigned char perm2
[MAX_VECT_LEN
];
11278 /* Try single-operand selections. */
11279 if (d
->one_operand_p
)
11281 if (expand_vec_perm_identity (d
))
11283 if (expand_vselect (d
->target
, d
->op0
, d
->perm
, nelt
))
11287 /* Try two operand selections. */
11288 if (expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, d
->perm
, nelt
))
11291 /* Recognize interleave style patterns with reversed operands. */
11292 if (!d
->one_operand_p
)
11294 for (i
= 0; i
< nelt
; ++i
)
11296 unsigned e
= d
->perm
[i
];
11304 if (expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
11308 if (expand_vec_perm_shrp (d
))
11311 /* ??? Look for deposit-like permutations where most of the result
11312 comes from one vector unchanged and the rest comes from a
11313 sequential hunk of the other vector. */
11318 /* Pattern match broadcast permutations. */
11321 expand_vec_perm_broadcast (struct expand_vec_perm_d
*d
)
11323 unsigned i
, elt
, nelt
= d
->nelt
;
11324 unsigned char perm2
[2];
11328 if (!d
->one_operand_p
)
11332 for (i
= 1; i
< nelt
; ++i
)
11333 if (d
->perm
[i
] != elt
)
11340 /* Implementable by interleave. */
11342 perm2
[1] = elt
+ 2;
11343 ok
= expand_vselect_vconcat (d
->target
, d
->op0
, d
->op0
, perm2
, 2);
11348 /* Implementable by extract + broadcast. */
11349 if (BYTES_BIG_ENDIAN
)
11351 elt
*= BITS_PER_UNIT
;
11352 temp
= gen_reg_rtx (DImode
);
11353 emit_insn (gen_extzv (temp
, gen_lowpart (DImode
, d
->op0
),
11354 GEN_INT (8), GEN_INT (elt
)));
11355 emit_insn (gen_mux1_brcst_qi (d
->target
, gen_lowpart (QImode
, temp
)));
11359 /* Should have been matched directly by vec_select. */
11361 gcc_unreachable ();
11367 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11368 two vector permutation into a single vector permutation by using
11369 an interleave operation to merge the vectors. */
11372 expand_vec_perm_interleave_2 (struct expand_vec_perm_d
*d
)
11374 struct expand_vec_perm_d dremap
, dfinal
;
11375 unsigned char remap
[2 * MAX_VECT_LEN
];
11376 unsigned contents
, i
, nelt
, nelt2
;
11377 unsigned h0
, h1
, h2
, h3
;
11381 if (d
->one_operand_p
)
11387 /* Examine from whence the elements come. */
11389 for (i
= 0; i
< nelt
; ++i
)
11390 contents
|= 1u << d
->perm
[i
];
11392 memset (remap
, 0xff, sizeof (remap
));
11395 h0
= (1u << nelt2
) - 1;
11398 h3
= h0
<< (nelt
+ nelt2
);
11400 if ((contents
& (h0
| h2
)) == contents
) /* punpck even halves */
11402 for (i
= 0; i
< nelt
; ++i
)
11404 unsigned which
= i
/ 2 + (i
& 1 ? nelt
: 0);
11406 dremap
.perm
[i
] = which
;
11409 else if ((contents
& (h1
| h3
)) == contents
) /* punpck odd halves */
11411 for (i
= 0; i
< nelt
; ++i
)
11413 unsigned which
= i
/ 2 + nelt2
+ (i
& 1 ? nelt
: 0);
11415 dremap
.perm
[i
] = which
;
11418 else if ((contents
& 0x5555) == contents
) /* mix even elements */
11420 for (i
= 0; i
< nelt
; ++i
)
11422 unsigned which
= (i
& ~1) + (i
& 1 ? nelt
: 0);
11424 dremap
.perm
[i
] = which
;
11427 else if ((contents
& 0xaaaa) == contents
) /* mix odd elements */
11429 for (i
= 0; i
< nelt
; ++i
)
11431 unsigned which
= (i
| 1) + (i
& 1 ? nelt
: 0);
11433 dremap
.perm
[i
] = which
;
11436 else if (floor_log2 (contents
) - ctz_hwi (contents
) < (int)nelt
) /* shrp */
11438 unsigned shift
= ctz_hwi (contents
);
11439 for (i
= 0; i
< nelt
; ++i
)
11441 unsigned which
= (i
+ shift
) & (2 * nelt
- 1);
11443 dremap
.perm
[i
] = which
;
11449 /* Use the remapping array set up above to move the elements from their
11450 swizzled locations into their final destinations. */
11452 for (i
= 0; i
< nelt
; ++i
)
11454 unsigned e
= remap
[d
->perm
[i
]];
11455 gcc_assert (e
< nelt
);
11456 dfinal
.perm
[i
] = e
;
11458 dfinal
.op0
= gen_reg_rtx (dfinal
.vmode
);
11459 dfinal
.op1
= dfinal
.op0
;
11460 dfinal
.one_operand_p
= true;
11461 dremap
.target
= dfinal
.op0
;
11463 /* Test if the final remap can be done with a single insn. For V4HImode
11464 this *will* succeed. For V8QImode or V2SImode it may not. */
11466 ok
= expand_vec_perm_1 (&dfinal
);
11467 seq
= get_insns ();
11474 ok
= expand_vec_perm_1 (&dremap
);
11481 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11482 constant permutation via two mux2 and a merge. */
11485 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d
*d
)
11487 unsigned char perm2
[4];
11490 rtx t0
, t1
, mask
, x
;
11493 if (d
->vmode
!= V4HImode
|| d
->one_operand_p
)
11498 for (i
= 0; i
< 4; ++i
)
11500 perm2
[i
] = d
->perm
[i
] & 3;
11501 rmask
[i
] = (d
->perm
[i
] & 4 ? const0_rtx
: constm1_rtx
);
11503 mask
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmask
));
11504 mask
= force_reg (V4HImode
, mask
);
11506 t0
= gen_reg_rtx (V4HImode
);
11507 t1
= gen_reg_rtx (V4HImode
);
11509 ok
= expand_vselect (t0
, d
->op0
, perm2
, 4);
11511 ok
= expand_vselect (t1
, d
->op1
, perm2
, 4);
11514 x
= gen_rtx_AND (V4HImode
, mask
, t0
);
11515 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
11517 x
= gen_rtx_NOT (V4HImode
, mask
);
11518 x
= gen_rtx_AND (V4HImode
, x
, t1
);
11519 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
11521 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
11522 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
11527 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11528 With all of the interface bits taken care of, perform the expansion
11529 in D and return true on success. */
11532 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
11534 if (expand_vec_perm_1 (d
))
11536 if (expand_vec_perm_broadcast (d
))
11538 if (expand_vec_perm_interleave_2 (d
))
11540 if (expand_vec_perm_v4hi_5 (d
))
11546 ia64_expand_vec_perm_const (rtx operands
[4])
11548 struct expand_vec_perm_d d
;
11549 unsigned char perm
[MAX_VECT_LEN
];
11550 int i
, nelt
, which
;
11553 d
.target
= operands
[0];
11554 d
.op0
= operands
[1];
11555 d
.op1
= operands
[2];
11558 d
.vmode
= GET_MODE (d
.target
);
11559 gcc_assert (VECTOR_MODE_P (d
.vmode
));
11560 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11561 d
.testing_p
= false;
11563 gcc_assert (GET_CODE (sel
) == CONST_VECTOR
);
11564 gcc_assert (XVECLEN (sel
, 0) == nelt
);
11565 gcc_checking_assert (sizeof (d
.perm
) == sizeof (perm
));
11567 for (i
= which
= 0; i
< nelt
; ++i
)
11569 rtx e
= XVECEXP (sel
, 0, i
);
11570 int ei
= INTVAL (e
) & (2 * nelt
- 1);
11572 which
|= (ei
< nelt
? 1 : 2);
11583 if (!rtx_equal_p (d
.op0
, d
.op1
))
11585 d
.one_operand_p
= false;
11589 /* The elements of PERM do not suggest that only the first operand
11590 is used, but both operands are identical. Allow easier matching
11591 of the permutation by folding the permutation into the single
11593 for (i
= 0; i
< nelt
; ++i
)
11594 if (d
.perm
[i
] >= nelt
)
11600 d
.one_operand_p
= true;
11604 for (i
= 0; i
< nelt
; ++i
)
11607 d
.one_operand_p
= true;
11611 if (ia64_expand_vec_perm_const_1 (&d
))
11614 /* If the mask says both arguments are needed, but they are the same,
11615 the above tried to expand with one_operand_p true. If that didn't
11616 work, retry with one_operand_p false, as that's what we used in _ok. */
11617 if (which
== 3 && d
.one_operand_p
)
11619 memcpy (d
.perm
, perm
, sizeof (perm
));
11620 d
.one_operand_p
= false;
11621 return ia64_expand_vec_perm_const_1 (&d
);
11627 /* Implement targetm.vectorize.vec_perm_const_ok. */
11630 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
11631 const unsigned char *sel
)
11633 struct expand_vec_perm_d d
;
11634 unsigned int i
, nelt
, which
;
11638 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11639 d
.testing_p
= true;
11641 /* Extract the values from the vector CST into the permutation
11643 memcpy (d
.perm
, sel
, nelt
);
11644 for (i
= which
= 0; i
< nelt
; ++i
)
11646 unsigned char e
= d
.perm
[i
];
11647 gcc_assert (e
< 2 * nelt
);
11648 which
|= (e
< nelt
? 1 : 2);
11651 /* For all elements from second vector, fold the elements to first. */
11653 for (i
= 0; i
< nelt
; ++i
)
11656 /* Check whether the mask can be applied to the vector type. */
11657 d
.one_operand_p
= (which
!= 3);
11659 /* Otherwise we have to go through the motions and see if we can
11660 figure out how to generate the requested permutation. */
11661 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
11662 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
11663 if (!d
.one_operand_p
)
11664 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
11667 ret
= ia64_expand_vec_perm_const_1 (&d
);
11674 ia64_expand_vec_setv2sf (rtx operands
[3])
11676 struct expand_vec_perm_d d
;
11677 unsigned int which
;
11680 d
.target
= operands
[0];
11681 d
.op0
= operands
[0];
11682 d
.op1
= gen_reg_rtx (V2SFmode
);
11683 d
.vmode
= V2SFmode
;
11685 d
.one_operand_p
= false;
11686 d
.testing_p
= false;
11688 which
= INTVAL (operands
[2]);
11689 gcc_assert (which
<= 1);
11690 d
.perm
[0] = 1 - which
;
11691 d
.perm
[1] = which
+ 2;
11693 emit_insn (gen_fpack (d
.op1
, operands
[1], CONST0_RTX (SFmode
)));
11695 ok
= ia64_expand_vec_perm_const_1 (&d
);
11700 ia64_expand_vec_perm_even_odd (rtx target
, rtx op0
, rtx op1
, int odd
)
11702 struct expand_vec_perm_d d
;
11703 enum machine_mode vmode
= GET_MODE (target
);
11704 unsigned int i
, nelt
= GET_MODE_NUNITS (vmode
);
11712 d
.one_operand_p
= false;
11713 d
.testing_p
= false;
11715 for (i
= 0; i
< nelt
; ++i
)
11716 d
.perm
[i
] = i
* 2 + odd
;
11718 ok
= ia64_expand_vec_perm_const_1 (&d
);
11722 #include "gt-ia64.h"