| blob | 8f3549ebdd8cf653a6f0fa54e0a9e99d6e44aaeb |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 ])
142 ;;
143 ;; UNSPEC_VOLATILE usage
144 ;;
146 (define_c_enum "unspecv"
147 [UNSPECV_BLOCK
148 UNSPECV_LL ; load-locked
149 UNSPECV_SC ; store-conditional
150 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
151 UNSPECV_EH_RR ; eh_reg_restore
152 UNSPECV_ISYNC ; isync instruction
153 UNSPECV_MFTB ; move from time base
154 UNSPECV_NLGR ; non-local goto receiver
155 UNSPECV_MFFS ; Move from FPSCR
156 UNSPECV_MTFSF ; Move to FPSCR Fields
157 ])
159 \f
160 ;; Define an insn type attribute. This is used in function unit delay
161 ;; computations.
162 (define_attr "type"
163 "integer,two,three,
164 add,logical,shift,insert,
165 mul,halfmul,div,
166 exts,cntlz,popcnt,isel,
167 load,store,fpload,fpstore,vecload,vecstore,
168 cmp,
169 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
170 compare,
171 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
172 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
173 brinc,
174 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
175 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
176 htm"
177 (const_string "integer"))
179 ;; What data size does this instruction work on?
180 ;; This is used for insert, mul.
181 (define_attr "size" "8,16,32,64" (const_string "32"))
183 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
184 ;; This is used for add, logical, shift, exts, mul.
185 (define_attr "dot" "no,yes" (const_string "no"))
187 ;; Does this instruction sign-extend its result?
188 ;; This is used for load insns.
189 (define_attr "sign_extend" "no,yes" (const_string "no"))
191 ;; Does this instruction use indexed (that is, reg+reg) addressing?
192 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
193 ;; it is automatically set based on that. If a load or store instruction
194 ;; has fewer than two operands it needs to set this attribute manually
195 ;; or the compiler will crash.
196 (define_attr "indexed" "no,yes"
197 (if_then_else (ior (match_operand 0 "indexed_address_mem")
198 (match_operand 1 "indexed_address_mem"))
199 (const_string "yes")
200 (const_string "no")))
202 ;; Does this instruction use update addressing?
203 ;; This is used for load and store insns. See the comments for "indexed".
204 (define_attr "update" "no,yes"
205 (if_then_else (ior (match_operand 0 "update_address_mem")
206 (match_operand 1 "update_address_mem"))
207 (const_string "yes")
208 (const_string "no")))
210 ;; Is this instruction using operands[2] as shift amount, and can that be a
211 ;; register?
212 ;; This is used for shift insns.
213 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
215 ;; Is this instruction using a shift amount from a register?
216 ;; This is used for shift insns.
217 (define_attr "var_shift" "no,yes"
218 (if_then_else (and (eq_attr "type" "shift")
219 (eq_attr "maybe_var_shift" "yes"))
220 (if_then_else (match_operand 2 "gpc_reg_operand")
221 (const_string "yes")
222 (const_string "no"))
223 (const_string "no")))
225 ;; Define floating point instruction sub-types for use with Xfpu.md
226 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
228 ;; Length (in bytes).
229 ; '(pc)' in the following doesn't include the instruction itself; it is
230 ; calculated as if the instruction had zero size.
231 (define_attr "length" ""
232 (if_then_else (eq_attr "type" "branch")
233 (if_then_else (and (ge (minus (match_dup 0) (pc))
234 (const_int -32768))
235 (lt (minus (match_dup 0) (pc))
236 (const_int 32764)))
237 (const_int 4)
238 (const_int 8))
239 (const_int 4)))
241 ;; Processor type -- this attribute must exactly match the processor_type
242 ;; enumeration in rs6000-opts.h.
243 (define_attr "cpu"
244 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
245 ppc750,ppc7400,ppc7450,
246 ppc403,ppc405,ppc440,ppc476,
247 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
248 power4,power5,power6,power7,power8,
249 rs64a,mpccore,cell,ppca2,titan"
250 (const (symbol_ref "rs6000_cpu_attr")))
253 ;; If this instruction is microcoded on the CELL processor
254 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
255 (define_attr "cell_micro" "not,conditional,always"
256 (if_then_else (ior (eq_attr "type" "compare")
257 (and (eq_attr "type" "shift,exts,mul")
258 (eq_attr "dot" "yes"))
259 (and (eq_attr "type" "load")
260 (eq_attr "sign_extend" "yes"))
261 (and (eq_attr "type" "shift")
262 (eq_attr "var_shift" "yes")))
263 (const_string "always")
264 (const_string "not")))
266 (automata_option "ndfa")
268 (include "rs64.md")
269 (include "mpc.md")
270 (include "40x.md")
271 (include "440.md")
272 (include "476.md")
273 (include "601.md")
274 (include "603.md")
275 (include "6xx.md")
276 (include "7xx.md")
277 (include "7450.md")
278 (include "8540.md")
279 (include "e300c2c3.md")
280 (include "e500mc.md")
281 (include "e500mc64.md")
282 (include "e5500.md")
283 (include "e6500.md")
284 (include "power4.md")
285 (include "power5.md")
286 (include "power6.md")
287 (include "power7.md")
288 (include "power8.md")
289 (include "cell.md")
290 (include "xfpu.md")
291 (include "a2.md")
292 (include "titan.md")
294 (include "predicates.md")
295 (include "constraints.md")
297 (include "darwin.md")
299 \f
300 ;; Mode iterators
302 ; This mode iterator allows :GPR to be used to indicate the allowable size
303 ; of whole values in GPRs.
304 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
306 ; Any supported integer mode.
307 (define_mode_iterator INT [QI HI SI DI TI PTI])
309 ; Any supported integer mode that fits in one register.
310 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
312 ; Everything we can extend QImode to.
313 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
315 ; Everything we can extend HImode to.
316 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
318 ; Everything we can extend SImode to.
319 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
321 ; QImode or HImode for small atomic ops
322 (define_mode_iterator QHI [QI HI])
324 ; HImode or SImode for sign extended fusion ops
325 (define_mode_iterator HSI [HI SI])
327 ; SImode or DImode, even if DImode doesn't fit in GPRs.
328 (define_mode_iterator SDI [SI DI])
330 ; The size of a pointer. Also, the size of the value that a record-condition
331 ; (one with a '.') will compare; and the size used for arithmetic carries.
332 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
334 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
335 ; PTImode is GPR only)
336 (define_mode_iterator TI2 [TI PTI])
338 ; Any hardware-supported floating-point mode
339 (define_mode_iterator FP [
340 (SF "TARGET_HARD_FLOAT
341 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
342 (DF "TARGET_HARD_FLOAT
343 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
344 (TF "!TARGET_IEEEQUAD
345 && TARGET_HARD_FLOAT
346 && (TARGET_FPRS || TARGET_E500_DOUBLE)
347 && TARGET_LONG_DOUBLE_128")
348 (DD "TARGET_DFP")
349 (TD "TARGET_DFP")])
351 ; Any fma capable floating-point mode.
352 (define_mode_iterator FMA_F [
353 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
354 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
355 || VECTOR_UNIT_VSX_P (DFmode)")
356 (V2SF "TARGET_PAIRED_FLOAT")
357 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
358 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
359 ])
361 ; Floating point move iterators to combine binary and decimal moves
362 (define_mode_iterator FMOVE32 [SF SD])
363 (define_mode_iterator FMOVE64 [DF DD])
364 (define_mode_iterator FMOVE64X [DI DF DD])
365 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
366 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
368 ; Iterators for 128 bit types for direct move
369 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
370 (V16QI "")
371 (V8HI "")
372 (V4SI "")
373 (V4SF "")
374 (V2DI "")
375 (V2DF "")
376 (V1TI "")])
378 ; Whether a floating point move is ok, don't allow SD without hardware FP
379 (define_mode_attr fmove_ok [(SF "")
380 (DF "")
381 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
382 (DD "")])
384 ; Convert REAL_VALUE to the appropriate bits
385 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
386 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
387 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
388 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
390 ; Definitions for load to 32-bit fpr register
391 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
392 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
393 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
394 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
396 ; Definitions for store from 32-bit fpr register
397 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
398 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
399 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
400 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
402 ; Definitions for 32-bit fpr direct move
403 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
405 ; These modes do not fit in integer registers in 32-bit mode.
406 ; but on e500v2, the gpr are 64 bit registers
407 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
409 ; Iterator for reciprocal estimate instructions
410 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
412 ; Iterator for just SF/DF
413 (define_mode_iterator SFDF [SF DF])
415 ; SF/DF suffix for traditional floating instructions
416 (define_mode_attr Ftrad [(SF "s") (DF "")])
418 ; SF/DF suffix for VSX instructions
419 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
421 ; SF/DF constraint for arithmetic on traditional floating point registers
422 (define_mode_attr Ff [(SF "f") (DF "d")])
424 ; SF/DF constraint for arithmetic on VSX registers
425 (define_mode_attr Fv [(SF "wy") (DF "ws")])
427 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
428 (define_mode_attr Fs [(SF "s") (DF "d")])
430 ; FRE/FRES support
431 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
432 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
434 ; Conditional returns.
435 (define_code_iterator any_return [return simple_return])
436 (define_code_attr return_pred [(return "direct_return ()")
437 (simple_return "1")])
438 (define_code_attr return_str [(return "") (simple_return "simple_")])
440 ; Signed/unsigned variants of ops.
441 (define_code_iterator any_extend [sign_extend zero_extend])
442 (define_code_attr u [(sign_extend "") (zero_extend "u")])
443 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
445 ; Various instructions that come in SI and DI forms.
446 ; A generic w/d attribute, for things like cmpw/cmpd.
447 (define_mode_attr wd [(QI "b")
448 (HI "h")
449 (SI "w")
450 (DI "d")
451 (V16QI "b")
452 (V8HI "h")
453 (V4SI "w")
454 (V2DI "d")])
456 ;; How many bits in this mode?
457 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
459 ; DImode bits
460 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
462 ;; ISEL/ISEL64 target selection
463 (define_mode_attr sel [(SI "") (DI "64")])
465 ;; Bitmask for shift instructions
466 (define_mode_attr hH [(SI "h") (DI "H")])
468 ;; A mode twice the size of the given mode
469 (define_mode_attr dmode [(SI "di") (DI "ti")])
470 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
472 ;; Suffix for reload patterns
473 (define_mode_attr ptrsize [(SI "32bit")
474 (DI "64bit")])
476 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
477 (DI "TARGET_64BIT")])
479 (define_mode_attr mptrsize [(SI "si")
480 (DI "di")])
482 (define_mode_attr ptrload [(SI "lwz")
483 (DI "ld")])
485 (define_mode_attr ptrm [(SI "m")
486 (DI "Y")])
488 (define_mode_attr rreg [(SF "f")
489 (DF "ws")
490 (TF "f")
491 (TD "f")
492 (V4SF "wf")
493 (V2DF "wd")])
495 (define_mode_attr rreg2 [(SF "f")
496 (DF "d")])
498 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
499 (DF "TARGET_FCFID")])
501 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
502 (DF "TARGET_E500_DOUBLE")])
504 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
505 (DF "TARGET_DOUBLE_FLOAT")])
507 ;; Mode iterator for logical operations on 128-bit types
508 (define_mode_iterator BOOL_128 [TI
509 PTI
510 (V16QI "TARGET_ALTIVEC")
511 (V8HI "TARGET_ALTIVEC")
512 (V4SI "TARGET_ALTIVEC")
513 (V4SF "TARGET_ALTIVEC")
514 (V2DI "TARGET_ALTIVEC")
515 (V2DF "TARGET_ALTIVEC")
516 (V1TI "TARGET_ALTIVEC")])
518 ;; For the GPRs we use 3 constraints for register outputs, two that are the
519 ;; same as the output register, and a third where the output register is an
520 ;; early clobber, so we don't have to deal with register overlaps. For the
521 ;; vector types, we prefer to use the vector registers. For TI mode, allow
522 ;; either.
524 ;; Mode attribute for boolean operation register constraints for output
525 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
526 (PTI "&r,r,r")
527 (V16QI "wa,v,&?r,?r,?r")
528 (V8HI "wa,v,&?r,?r,?r")
529 (V4SI "wa,v,&?r,?r,?r")
530 (V4SF "wa,v,&?r,?r,?r")
531 (V2DI "wa,v,&?r,?r,?r")
532 (V2DF "wa,v,&?r,?r,?r")
533 (V1TI "wa,v,&?r,?r,?r")])
535 ;; Mode attribute for boolean operation register constraints for operand1
536 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
537 (PTI "r,0,r")
538 (V16QI "wa,v,r,0,r")
539 (V8HI "wa,v,r,0,r")
540 (V4SI "wa,v,r,0,r")
541 (V4SF "wa,v,r,0,r")
542 (V2DI "wa,v,r,0,r")
543 (V2DF "wa,v,r,0,r")
544 (V1TI "wa,v,r,0,r")])
546 ;; Mode attribute for boolean operation register constraints for operand2
547 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
548 (PTI "r,r,0")
549 (V16QI "wa,v,r,r,0")
550 (V8HI "wa,v,r,r,0")
551 (V4SI "wa,v,r,r,0")
552 (V4SF "wa,v,r,r,0")
553 (V2DI "wa,v,r,r,0")
554 (V2DF "wa,v,r,r,0")
555 (V1TI "wa,v,r,r,0")])
557 ;; Mode attribute for boolean operation register constraints for operand1
558 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
559 ;; is used for operand1 or operand2
560 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
561 (PTI "r,0,0")
562 (V16QI "wa,v,r,0,0")
563 (V8HI "wa,v,r,0,0")
564 (V4SI "wa,v,r,0,0")
565 (V4SF "wa,v,r,0,0")
566 (V2DI "wa,v,r,0,0")
567 (V2DF "wa,v,r,0,0")
568 (V1TI "wa,v,r,0,0")])
569 \f
570 ;; Start with fixed-point load and store insns. Here we put only the more
571 ;; complex forms. Basic data transfer is done later.
573 (define_insn "zero_extendqi<mode>2"
574 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
575 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
576 ""
577 "@
578 lbz%U1%X1 %0,%1
579 rlwinm %0,%1,0,0xff"
580 [(set_attr "type" "load,shift")])
582 (define_insn_and_split "*zero_extendqi<mode>2_dot"
583 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
584 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
585 (const_int 0)))
586 (clobber (match_scratch:EXTQI 0 "=r,r"))]
587 "rs6000_gen_cell_microcode"
588 "@
589 andi. %0,%1,0xff
590 #"
591 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
592 [(set (match_dup 0)
593 (zero_extend:EXTQI (match_dup 1)))
594 (set (match_dup 2)
595 (compare:CC (match_dup 0)
596 (const_int 0)))]
597 ""
598 [(set_attr "type" "logical")
599 (set_attr "dot" "yes")
600 (set_attr "length" "4,8")])
602 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
603 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
604 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
605 (const_int 0)))
606 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
607 (zero_extend:EXTQI (match_dup 1)))]
608 "rs6000_gen_cell_microcode"
609 "@
610 andi. %0,%1,0xff
611 #"
612 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
613 [(set (match_dup 0)
614 (zero_extend:EXTQI (match_dup 1)))
615 (set (match_dup 2)
616 (compare:CC (match_dup 0)
617 (const_int 0)))]
618 ""
619 [(set_attr "type" "logical")
620 (set_attr "dot" "yes")
621 (set_attr "length" "4,8")])
624 (define_insn "zero_extendhi<mode>2"
625 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
626 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
627 ""
628 "@
629 lhz%U1%X1 %0,%1
630 rlwinm %0,%1,0,0xffff"
631 [(set_attr "type" "load,shift")])
633 (define_insn_and_split "*zero_extendhi<mode>2_dot"
634 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
635 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
636 (const_int 0)))
637 (clobber (match_scratch:EXTHI 0 "=r,r"))]
638 "rs6000_gen_cell_microcode"
639 "@
640 andi. %0,%1,0xffff
641 #"
642 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
643 [(set (match_dup 0)
644 (zero_extend:EXTHI (match_dup 1)))
645 (set (match_dup 2)
646 (compare:CC (match_dup 0)
647 (const_int 0)))]
648 ""
649 [(set_attr "type" "logical")
650 (set_attr "dot" "yes")
651 (set_attr "length" "4,8")])
653 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
654 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
655 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
656 (const_int 0)))
657 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
658 (zero_extend:EXTHI (match_dup 1)))]
659 "rs6000_gen_cell_microcode"
660 "@
661 andi. %0,%1,0xffff
662 #"
663 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
664 [(set (match_dup 0)
665 (zero_extend:EXTHI (match_dup 1)))
666 (set (match_dup 2)
667 (compare:CC (match_dup 0)
668 (const_int 0)))]
669 ""
670 [(set_attr "type" "logical")
671 (set_attr "dot" "yes")
672 (set_attr "length" "4,8")])
675 (define_insn "zero_extendsi<mode>2"
676 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
677 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
678 ""
679 "@
680 lwz%U1%X1 %0,%1
681 rldicl %0,%1,0,32
682 mtvsrwz %x0,%1
683 lfiwzx %0,%y1
684 lxsiwzx %x0,%y1"
685 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
687 (define_insn_and_split "*zero_extendsi<mode>2_dot"
688 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
690 (const_int 0)))
691 (clobber (match_scratch:EXTSI 0 "=r,r"))]
692 "rs6000_gen_cell_microcode"
693 "@
694 rldicl. %0,%1,0,32
695 #"
696 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
697 [(set (match_dup 0)
698 (zero_extend:DI (match_dup 1)))
699 (set (match_dup 2)
700 (compare:CC (match_dup 0)
701 (const_int 0)))]
702 ""
703 [(set_attr "type" "shift")
704 (set_attr "dot" "yes")
705 (set_attr "length" "4,8")])
707 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
708 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
709 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
710 (const_int 0)))
711 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
712 (zero_extend:EXTSI (match_dup 1)))]
713 "rs6000_gen_cell_microcode"
714 "@
715 rldicl. %0,%1,0,32
716 #"
717 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
718 [(set (match_dup 0)
719 (zero_extend:EXTSI (match_dup 1)))
720 (set (match_dup 2)
721 (compare:CC (match_dup 0)
722 (const_int 0)))]
723 ""
724 [(set_attr "type" "shift")
725 (set_attr "dot" "yes")
726 (set_attr "length" "4,8")])
729 (define_insn "extendqi<mode>2"
730 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
731 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
732 ""
733 "extsb %0,%1"
734 [(set_attr "type" "exts")])
736 (define_insn_and_split "*extendqi<mode>2_dot"
737 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
738 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
739 (const_int 0)))
740 (clobber (match_scratch:EXTQI 0 "=r,r"))]
741 "rs6000_gen_cell_microcode"
742 "@
743 extsb. %0,%1
744 #"
745 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
746 [(set (match_dup 0)
747 (sign_extend:EXTQI (match_dup 1)))
748 (set (match_dup 2)
749 (compare:CC (match_dup 0)
750 (const_int 0)))]
751 ""
752 [(set_attr "type" "exts")
753 (set_attr "dot" "yes")
754 (set_attr "length" "4,8")])
756 (define_insn_and_split "*extendqi<mode>2_dot2"
757 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
758 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
759 (const_int 0)))
760 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
761 (sign_extend:EXTQI (match_dup 1)))]
762 "rs6000_gen_cell_microcode"
763 "@
764 extsb. %0,%1
765 #"
766 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
767 [(set (match_dup 0)
768 (sign_extend:EXTQI (match_dup 1)))
769 (set (match_dup 2)
770 (compare:CC (match_dup 0)
771 (const_int 0)))]
772 ""
773 [(set_attr "type" "exts")
774 (set_attr "dot" "yes")
775 (set_attr "length" "4,8")])
778 (define_expand "extendhi<mode>2"
779 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
780 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
781 ""
782 "")
784 (define_insn "*extendhi<mode>2"
785 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
786 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
787 "rs6000_gen_cell_microcode"
788 "@
789 lha%U1%X1 %0,%1
790 extsh %0,%1"
791 [(set_attr "type" "load,exts")
792 (set_attr "sign_extend" "yes")])
794 (define_insn "*extendhi<mode>2_noload"
795 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
796 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
797 "!rs6000_gen_cell_microcode"
798 "extsh %0,%1"
799 [(set_attr "type" "exts")])
801 (define_insn_and_split "*extendhi<mode>2_dot"
802 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
803 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
804 (const_int 0)))
805 (clobber (match_scratch:EXTHI 0 "=r,r"))]
806 "rs6000_gen_cell_microcode"
807 "@
808 extsh. %0,%1
809 #"
810 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
811 [(set (match_dup 0)
812 (sign_extend:EXTHI (match_dup 1)))
813 (set (match_dup 2)
814 (compare:CC (match_dup 0)
815 (const_int 0)))]
816 ""
817 [(set_attr "type" "exts")
818 (set_attr "dot" "yes")
819 (set_attr "length" "4,8")])
821 (define_insn_and_split "*extendhi<mode>2_dot2"
822 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
823 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
824 (const_int 0)))
825 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
826 (sign_extend:EXTHI (match_dup 1)))]
827 "rs6000_gen_cell_microcode"
828 "@
829 extsh. %0,%1
830 #"
831 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
832 [(set (match_dup 0)
833 (sign_extend:EXTHI (match_dup 1)))
834 (set (match_dup 2)
835 (compare:CC (match_dup 0)
836 (const_int 0)))]
837 ""
838 [(set_attr "type" "exts")
839 (set_attr "dot" "yes")
840 (set_attr "length" "4,8")])
843 (define_insn "extendsi<mode>2"
844 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
845 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
846 ""
847 "@
848 lwa%U1%X1 %0,%1
849 extsw %0,%1
850 mtvsrwa %x0,%1
851 lfiwax %0,%y1
852 lxsiwax %x0,%y1"
853 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
854 (set_attr "sign_extend" "yes")])
856 (define_insn_and_split "*extendsi<mode>2_dot"
857 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
858 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
859 (const_int 0)))
860 (clobber (match_scratch:EXTSI 0 "=r,r"))]
861 "rs6000_gen_cell_microcode"
862 "@
863 extsw. %0,%1
864 #"
865 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
866 [(set (match_dup 0)
867 (sign_extend:EXTSI (match_dup 1)))
868 (set (match_dup 2)
869 (compare:CC (match_dup 0)
870 (const_int 0)))]
871 ""
872 [(set_attr "type" "exts")
873 (set_attr "dot" "yes")
874 (set_attr "length" "4,8")])
876 (define_insn_and_split "*extendsi<mode>2_dot2"
877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
878 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
879 (const_int 0)))
880 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
881 (sign_extend:EXTSI (match_dup 1)))]
882 "rs6000_gen_cell_microcode"
883 "@
884 extsw. %0,%1
885 #"
886 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
887 [(set (match_dup 0)
888 (sign_extend:EXTSI (match_dup 1)))
889 (set (match_dup 2)
890 (compare:CC (match_dup 0)
891 (const_int 0)))]
892 ""
893 [(set_attr "type" "exts")
894 (set_attr "dot" "yes")
895 (set_attr "length" "4,8")])
896 \f
897 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
899 (define_insn "*macchwc"
900 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
901 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
902 (match_operand:SI 2 "gpc_reg_operand" "r")
903 (const_int 16))
904 (sign_extend:SI
905 (match_operand:HI 1 "gpc_reg_operand" "r")))
906 (match_operand:SI 4 "gpc_reg_operand" "0"))
907 (const_int 0)))
908 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
909 (plus:SI (mult:SI (ashiftrt:SI
910 (match_dup 2)
911 (const_int 16))
912 (sign_extend:SI
913 (match_dup 1)))
914 (match_dup 4)))]
915 "TARGET_MULHW"
916 "macchw. %0,%1,%2"
917 [(set_attr "type" "halfmul")])
919 (define_insn "*macchw"
920 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
921 (plus:SI (mult:SI (ashiftrt:SI
922 (match_operand:SI 2 "gpc_reg_operand" "r")
923 (const_int 16))
924 (sign_extend:SI
925 (match_operand:HI 1 "gpc_reg_operand" "r")))
926 (match_operand:SI 3 "gpc_reg_operand" "0")))]
927 "TARGET_MULHW"
928 "macchw %0,%1,%2"
929 [(set_attr "type" "halfmul")])
931 (define_insn "*macchwuc"
932 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
933 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
934 (match_operand:SI 2 "gpc_reg_operand" "r")
935 (const_int 16))
936 (zero_extend:SI
937 (match_operand:HI 1 "gpc_reg_operand" "r")))
938 (match_operand:SI 4 "gpc_reg_operand" "0"))
939 (const_int 0)))
940 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 (plus:SI (mult:SI (lshiftrt:SI
942 (match_dup 2)
943 (const_int 16))
944 (zero_extend:SI
945 (match_dup 1)))
946 (match_dup 4)))]
947 "TARGET_MULHW"
948 "macchwu. %0,%1,%2"
949 [(set_attr "type" "halfmul")])
951 (define_insn "*macchwu"
952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
953 (plus:SI (mult:SI (lshiftrt:SI
954 (match_operand:SI 2 "gpc_reg_operand" "r")
955 (const_int 16))
956 (zero_extend:SI
957 (match_operand:HI 1 "gpc_reg_operand" "r")))
958 (match_operand:SI 3 "gpc_reg_operand" "0")))]
959 "TARGET_MULHW"
960 "macchwu %0,%1,%2"
961 [(set_attr "type" "halfmul")])
963 (define_insn "*machhwc"
964 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
965 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
966 (match_operand:SI 1 "gpc_reg_operand" "%r")
967 (const_int 16))
968 (ashiftrt:SI
969 (match_operand:SI 2 "gpc_reg_operand" "r")
970 (const_int 16)))
971 (match_operand:SI 4 "gpc_reg_operand" "0"))
972 (const_int 0)))
973 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (plus:SI (mult:SI (ashiftrt:SI
975 (match_dup 1)
976 (const_int 16))
977 (ashiftrt:SI
978 (match_dup 2)
979 (const_int 16)))
980 (match_dup 4)))]
981 "TARGET_MULHW"
982 "machhw. %0,%1,%2"
983 [(set_attr "type" "halfmul")])
985 (define_insn "*machhw"
986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_operand:SI 1 "gpc_reg_operand" "%r")
989 (const_int 16))
990 (ashiftrt:SI
991 (match_operand:SI 2 "gpc_reg_operand" "r")
992 (const_int 16)))
993 (match_operand:SI 3 "gpc_reg_operand" "0")))]
994 "TARGET_MULHW"
995 "machhw %0,%1,%2"
996 [(set_attr "type" "halfmul")])
998 (define_insn "*machhwuc"
999 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1000 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1001 (match_operand:SI 1 "gpc_reg_operand" "%r")
1002 (const_int 16))
1003 (lshiftrt:SI
1004 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (const_int 16)))
1006 (match_operand:SI 4 "gpc_reg_operand" "0"))
1007 (const_int 0)))
1008 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1009 (plus:SI (mult:SI (lshiftrt:SI
1010 (match_dup 1)
1011 (const_int 16))
1012 (lshiftrt:SI
1013 (match_dup 2)
1014 (const_int 16)))
1015 (match_dup 4)))]
1016 "TARGET_MULHW"
1017 "machhwu. %0,%1,%2"
1018 [(set_attr "type" "halfmul")])
1020 (define_insn "*machhwu"
1021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (lshiftrt:SI
1023 (match_operand:SI 1 "gpc_reg_operand" "%r")
1024 (const_int 16))
1025 (lshiftrt:SI
1026 (match_operand:SI 2 "gpc_reg_operand" "r")
1027 (const_int 16)))
1028 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1029 "TARGET_MULHW"
1030 "machhwu %0,%1,%2"
1031 [(set_attr "type" "halfmul")])
1033 (define_insn "*maclhwc"
1034 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1035 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1037 (sign_extend:SI
1038 (match_operand:HI 2 "gpc_reg_operand" "r")))
1039 (match_operand:SI 4 "gpc_reg_operand" "0"))
1040 (const_int 0)))
1041 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1042 (plus:SI (mult:SI (sign_extend:SI
1043 (match_dup 1))
1044 (sign_extend:SI
1045 (match_dup 2)))
1046 (match_dup 4)))]
1047 "TARGET_MULHW"
1048 "maclhw. %0,%1,%2"
1049 [(set_attr "type" "halfmul")])
1051 (define_insn "*maclhw"
1052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (sign_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1055 (sign_extend:SI
1056 (match_operand:HI 2 "gpc_reg_operand" "r")))
1057 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1058 "TARGET_MULHW"
1059 "maclhw %0,%1,%2"
1060 [(set_attr "type" "halfmul")])
1062 (define_insn "*maclhwuc"
1063 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1064 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1065 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1066 (zero_extend:SI
1067 (match_operand:HI 2 "gpc_reg_operand" "r")))
1068 (match_operand:SI 4 "gpc_reg_operand" "0"))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (zero_extend:SI
1072 (match_dup 1))
1073 (zero_extend:SI
1074 (match_dup 2)))
1075 (match_dup 4)))]
1076 "TARGET_MULHW"
1077 "maclhwu. %0,%1,%2"
1078 [(set_attr "type" "halfmul")])
1080 (define_insn "*maclhwu"
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (zero_extend:SI
1083 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1084 (zero_extend:SI
1085 (match_operand:HI 2 "gpc_reg_operand" "r")))
1086 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1087 "TARGET_MULHW"
1088 "maclhwu %0,%1,%2"
1089 [(set_attr "type" "halfmul")])
1091 (define_insn "*nmacchwc"
1092 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1093 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1094 (mult:SI (ashiftrt:SI
1095 (match_operand:SI 2 "gpc_reg_operand" "r")
1096 (const_int 16))
1097 (sign_extend:SI
1098 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1099 (const_int 0)))
1100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (minus:SI (match_dup 4)
1102 (mult:SI (ashiftrt:SI
1103 (match_dup 2)
1104 (const_int 16))
1105 (sign_extend:SI
1106 (match_dup 1)))))]
1107 "TARGET_MULHW"
1108 "nmacchw. %0,%1,%2"
1109 [(set_attr "type" "halfmul")])
1111 (define_insn "*nmacchw"
1112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1113 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1114 (mult:SI (ashiftrt:SI
1115 (match_operand:SI 2 "gpc_reg_operand" "r")
1116 (const_int 16))
1117 (sign_extend:SI
1118 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1119 "TARGET_MULHW"
1120 "nmacchw %0,%1,%2"
1121 [(set_attr "type" "halfmul")])
1123 (define_insn "*nmachhwc"
1124 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1125 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1126 (mult:SI (ashiftrt:SI
1127 (match_operand:SI 1 "gpc_reg_operand" "%r")
1128 (const_int 16))
1129 (ashiftrt:SI
1130 (match_operand:SI 2 "gpc_reg_operand" "r")
1131 (const_int 16))))
1132 (const_int 0)))
1133 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1134 (minus:SI (match_dup 4)
1135 (mult:SI (ashiftrt:SI
1136 (match_dup 1)
1137 (const_int 16))
1138 (ashiftrt:SI
1139 (match_dup 2)
1140 (const_int 16)))))]
1141 "TARGET_MULHW"
1142 "nmachhw. %0,%1,%2"
1143 [(set_attr "type" "halfmul")])
1145 (define_insn "*nmachhw"
1146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1148 (mult:SI (ashiftrt:SI
1149 (match_operand:SI 1 "gpc_reg_operand" "%r")
1150 (const_int 16))
1151 (ashiftrt:SI
1152 (match_operand:SI 2 "gpc_reg_operand" "r")
1153 (const_int 16)))))]
1154 "TARGET_MULHW"
1155 "nmachhw %0,%1,%2"
1156 [(set_attr "type" "halfmul")])
1158 (define_insn "*nmaclhwc"
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1160 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1161 (mult:SI (sign_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (sign_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1165 (const_int 0)))
1166 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1167 (minus:SI (match_dup 4)
1168 (mult:SI (sign_extend:SI
1169 (match_dup 1))
1170 (sign_extend:SI
1171 (match_dup 2)))))]
1172 "TARGET_MULHW"
1173 "nmaclhw. %0,%1,%2"
1174 [(set_attr "type" "halfmul")])
1176 (define_insn "*nmaclhw"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1179 (mult:SI (sign_extend:SI
1180 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1181 (sign_extend:SI
1182 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1183 "TARGET_MULHW"
1184 "nmaclhw %0,%1,%2"
1185 [(set_attr "type" "halfmul")])
1187 (define_insn "*mulchwc"
1188 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1189 (compare:CC (mult:SI (ashiftrt:SI
1190 (match_operand:SI 2 "gpc_reg_operand" "r")
1191 (const_int 16))
1192 (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "r")))
1194 (const_int 0)))
1195 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (mult:SI (ashiftrt:SI
1197 (match_dup 2)
1198 (const_int 16))
1199 (sign_extend:SI
1200 (match_dup 1))))]
1201 "TARGET_MULHW"
1202 "mulchw. %0,%1,%2"
1203 [(set_attr "type" "halfmul")])
1205 (define_insn "*mulchw"
1206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1207 (mult:SI (ashiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16))
1210 (sign_extend:SI
1211 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1212 "TARGET_MULHW"
1213 "mulchw %0,%1,%2"
1214 [(set_attr "type" "halfmul")])
1216 (define_insn "*mulchwuc"
1217 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1218 (compare:CC (mult:SI (lshiftrt:SI
1219 (match_operand:SI 2 "gpc_reg_operand" "r")
1220 (const_int 16))
1221 (zero_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "r")))
1223 (const_int 0)))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (mult:SI (lshiftrt:SI
1226 (match_dup 2)
1227 (const_int 16))
1228 (zero_extend:SI
1229 (match_dup 1))))]
1230 "TARGET_MULHW"
1231 "mulchwu. %0,%1,%2"
1232 [(set_attr "type" "halfmul")])
1234 (define_insn "*mulchwu"
1235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1236 (mult:SI (lshiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (zero_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1241 "TARGET_MULHW"
1242 "mulchwu %0,%1,%2"
1243 [(set_attr "type" "halfmul")])
1245 (define_insn "*mulhhwc"
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (mult:SI (ashiftrt:SI
1248 (match_operand:SI 1 "gpc_reg_operand" "%r")
1249 (const_int 16))
1250 (ashiftrt:SI
1251 (match_operand:SI 2 "gpc_reg_operand" "r")
1252 (const_int 16)))
1253 (const_int 0)))
1254 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (ashiftrt:SI
1256 (match_dup 1)
1257 (const_int 16))
1258 (ashiftrt:SI
1259 (match_dup 2)
1260 (const_int 16))))]
1261 "TARGET_MULHW"
1262 "mulhhw. %0,%1,%2"
1263 [(set_attr "type" "halfmul")])
1265 (define_insn "*mulhhw"
1266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1267 (mult:SI (ashiftrt:SI
1268 (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 (const_int 16))
1270 (ashiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16))))]
1273 "TARGET_MULHW"
1274 "mulhhw %0,%1,%2"
1275 [(set_attr "type" "halfmul")])
1277 (define_insn "*mulhhwuc"
1278 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1279 (compare:CC (mult:SI (lshiftrt:SI
1280 (match_operand:SI 1 "gpc_reg_operand" "%r")
1281 (const_int 16))
1282 (lshiftrt:SI
1283 (match_operand:SI 2 "gpc_reg_operand" "r")
1284 (const_int 16)))
1285 (const_int 0)))
1286 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (lshiftrt:SI
1288 (match_dup 1)
1289 (const_int 16))
1290 (lshiftrt:SI
1291 (match_dup 2)
1292 (const_int 16))))]
1293 "TARGET_MULHW"
1294 "mulhhwu. %0,%1,%2"
1295 [(set_attr "type" "halfmul")])
1297 (define_insn "*mulhhwu"
1298 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1299 (mult:SI (lshiftrt:SI
1300 (match_operand:SI 1 "gpc_reg_operand" "%r")
1301 (const_int 16))
1302 (lshiftrt:SI
1303 (match_operand:SI 2 "gpc_reg_operand" "r")
1304 (const_int 16))))]
1305 "TARGET_MULHW"
1306 "mulhhwu %0,%1,%2"
1307 [(set_attr "type" "halfmul")])
1309 (define_insn "*mullhwc"
1310 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1311 (compare:CC (mult:SI (sign_extend:SI
1312 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1313 (sign_extend:SI
1314 (match_operand:HI 2 "gpc_reg_operand" "r")))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (mult:SI (sign_extend:SI
1318 (match_dup 1))
1319 (sign_extend:SI
1320 (match_dup 2))))]
1321 "TARGET_MULHW"
1322 "mullhw. %0,%1,%2"
1323 [(set_attr "type" "halfmul")])
1325 (define_insn "*mullhw"
1326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1327 (mult:SI (sign_extend:SI
1328 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1329 (sign_extend:SI
1330 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1331 "TARGET_MULHW"
1332 "mullhw %0,%1,%2"
1333 [(set_attr "type" "halfmul")])
1335 (define_insn "*mullhwuc"
1336 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1337 (compare:CC (mult:SI (zero_extend:SI
1338 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1339 (zero_extend:SI
1340 (match_operand:HI 2 "gpc_reg_operand" "r")))
1341 (const_int 0)))
1342 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 (mult:SI (zero_extend:SI
1344 (match_dup 1))
1345 (zero_extend:SI
1346 (match_dup 2))))]
1347 "TARGET_MULHW"
1348 "mullhwu. %0,%1,%2"
1349 [(set_attr "type" "halfmul")])
1351 (define_insn "*mullhwu"
1352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1353 (mult:SI (zero_extend:SI
1354 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1355 (zero_extend:SI
1356 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1357 "TARGET_MULHW"
1358 "mullhwu %0,%1,%2"
1359 [(set_attr "type" "halfmul")])
1360 \f
1361 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1362 (define_insn "dlmzb"
1363 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1364 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1365 (match_operand:SI 2 "gpc_reg_operand" "r")]
1366 UNSPEC_DLMZB_CR))
1367 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1368 (unspec:SI [(match_dup 1)
1369 (match_dup 2)]
1370 UNSPEC_DLMZB))]
1371 "TARGET_DLMZB"
1372 "dlmzb. %0,%1,%2")
1374 (define_expand "strlensi"
1375 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1376 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1377 (match_operand:QI 2 "const_int_operand" "")
1378 (match_operand 3 "const_int_operand" "")]
1379 UNSPEC_DLMZB_STRLEN))
1380 (clobber (match_scratch:CC 4 "=x"))]
1381 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1382 {
1383 rtx result = operands[0];
1384 rtx src = operands[1];
1385 rtx search_char = operands[2];
1386 rtx align = operands[3];
1387 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1388 rtx loop_label, end_label, mem, cr0, cond;
1389 if (search_char != const0_rtx
1390 || GET_CODE (align) != CONST_INT
1391 || INTVAL (align) < 8)
1392 FAIL;
1393 word1 = gen_reg_rtx (SImode);
1394 word2 = gen_reg_rtx (SImode);
1395 scratch_dlmzb = gen_reg_rtx (SImode);
1396 scratch_string = gen_reg_rtx (Pmode);
1397 loop_label = gen_label_rtx ();
1398 end_label = gen_label_rtx ();
1399 addr = force_reg (Pmode, XEXP (src, 0));
1400 emit_move_insn (scratch_string, addr);
1401 emit_label (loop_label);
1402 mem = change_address (src, SImode, scratch_string);
1403 emit_move_insn (word1, mem);
1404 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1405 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1406 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1407 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1408 emit_jump_insn (gen_rtx_SET (VOIDmode,
1409 pc_rtx,
1410 gen_rtx_IF_THEN_ELSE (VOIDmode,
1411 cond,
1412 gen_rtx_LABEL_REF
1413 (VOIDmode,
1414 end_label),
1415 pc_rtx)));
1416 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1417 emit_jump_insn (gen_rtx_SET (VOIDmode,
1418 pc_rtx,
1419 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1420 emit_barrier ();
1421 emit_label (end_label);
1422 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1423 emit_insn (gen_subsi3 (result, scratch_string, addr));
1424 emit_insn (gen_subsi3 (result, result, const1_rtx));
1425 DONE;
1426 })
1427 \f
1428 ;; Fixed-point arithmetic insns.
1430 (define_expand "add<mode>3"
1431 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1432 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1433 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1434 ""
1435 {
1436 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1437 {
1438 if (non_short_cint_operand (operands[2], DImode))
1439 FAIL;
1440 }
1441 else if (GET_CODE (operands[2]) == CONST_INT
1442 && ! add_operand (operands[2], <MODE>mode))
1443 {
1444 rtx tmp = ((!can_create_pseudo_p ()
1445 || rtx_equal_p (operands[0], operands[1]))
1446 ? operands[0] : gen_reg_rtx (<MODE>mode));
1448 HOST_WIDE_INT val = INTVAL (operands[2]);
1449 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1450 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1452 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1453 FAIL;
1455 /* The ordering here is important for the prolog expander.
1456 When space is allocated from the stack, adding 'low' first may
1457 produce a temporary deallocation (which would be bad). */
1458 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1459 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1460 DONE;
1461 }
1462 })
1464 ;; Discourage ai/addic because of carry but provide it in an alternative
1465 ;; allowing register zero as source.
1466 (define_insn "*add<mode>3_internal1"
1467 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1468 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1469 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1470 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1471 "@
1472 add %0,%1,%2
1473 addi %0,%1,%2
1474 addic %0,%1,%2
1475 addis %0,%1,%v2"
1476 [(set_attr "type" "add")])
1478 (define_insn "addsi3_high"
1479 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1480 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1481 (high:SI (match_operand 2 "" ""))))]
1482 "TARGET_MACHO && !TARGET_64BIT"
1483 "addis %0,%1,ha16(%2)"
1484 [(set_attr "type" "add")])
1486 (define_insn "*add<mode>3_internal2"
1487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1488 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1489 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1490 (const_int 0)))
1491 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1492 ""
1493 "@
1494 add. %3,%1,%2
1495 addic. %3,%1,%2
1496 #
1497 #"
1498 [(set_attr "type" "add,compare,compare,compare")
1499 (set_attr "dot" "yes")
1500 (set_attr "length" "4,4,8,8")])
1502 (define_split
1503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1504 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1505 (match_operand:GPR 2 "reg_or_short_operand" ""))
1506 (const_int 0)))
1507 (clobber (match_scratch:GPR 3 ""))]
1508 "reload_completed"
1509 [(set (match_dup 3)
1510 (plus:GPR (match_dup 1)
1511 (match_dup 2)))
1512 (set (match_dup 0)
1513 (compare:CC (match_dup 3)
1514 (const_int 0)))]
1515 "")
1517 (define_insn "*add<mode>3_internal3"
1518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1519 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1520 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1521 (const_int 0)))
1522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1523 (plus:P (match_dup 1)
1524 (match_dup 2)))]
1525 ""
1526 "@
1527 add. %0,%1,%2
1528 addic. %0,%1,%2
1529 #
1530 #"
1531 [(set_attr "type" "add,compare,compare,compare")
1532 (set_attr "dot" "yes")
1533 (set_attr "length" "4,4,8,8")])
1535 (define_split
1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1538 (match_operand:P 2 "reg_or_short_operand" ""))
1539 (const_int 0)))
1540 (set (match_operand:P 0 "gpc_reg_operand" "")
1541 (plus:P (match_dup 1) (match_dup 2)))]
1542 "reload_completed"
1543 [(set (match_dup 0)
1544 (plus:P (match_dup 1)
1545 (match_dup 2)))
1546 (set (match_dup 3)
1547 (compare:CC (match_dup 0)
1548 (const_int 0)))]
1549 "")
1551 ;; Split an add that we can't do in one insn into two insns, each of which
1552 ;; does one 16-bit part. This is used by combine. Note that the low-order
1553 ;; add should be last in case the result gets used in an address.
1555 (define_split
1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1558 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1559 ""
1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1562 {
1563 HOST_WIDE_INT val = INTVAL (operands[2]);
1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1567 operands[4] = GEN_INT (low);
1568 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1569 operands[3] = GEN_INT (rest);
1570 else if (can_create_pseudo_p ())
1571 {
1572 operands[3] = gen_reg_rtx (DImode);
1573 emit_move_insn (operands[3], operands[2]);
1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1575 DONE;
1576 }
1577 else
1578 FAIL;
1579 })
1581 (define_expand "one_cmpl<mode>2"
1582 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1583 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1584 ""
1585 {
1586 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1587 {
1588 rs6000_split_logical (operands, NOT, false, false, false);
1589 DONE;
1590 }
1591 })
1593 (define_insn "*one_cmpl<mode>2"
1594 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1595 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1596 ""
1597 "nor %0,%1,%1")
1599 (define_insn ""
1600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1602 (const_int 0)))
1603 (clobber (match_scratch:P 2 "=r,r"))]
1604 ""
1605 "@
1606 nor. %2,%1,%1
1607 #"
1608 [(set_attr "type" "logical,compare")
1609 (set_attr "dot" "yes")
1610 (set_attr "length" "4,8")])
1612 (define_split
1613 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1615 (const_int 0)))
1616 (clobber (match_scratch:P 2 ""))]
1617 "reload_completed"
1618 [(set (match_dup 2)
1619 (not:P (match_dup 1)))
1620 (set (match_dup 0)
1621 (compare:CC (match_dup 2)
1622 (const_int 0)))]
1623 "")
1625 (define_insn ""
1626 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1628 (const_int 0)))
1629 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1630 (not:P (match_dup 1)))]
1631 ""
1632 "@
1633 nor. %0,%1,%1
1634 #"
1635 [(set_attr "type" "logical,compare")
1636 (set_attr "dot" "yes")
1637 (set_attr "length" "4,8")])
1639 (define_split
1640 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1641 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1642 (const_int 0)))
1643 (set (match_operand:P 0 "gpc_reg_operand" "")
1644 (not:P (match_dup 1)))]
1645 "reload_completed"
1646 [(set (match_dup 0)
1647 (not:P (match_dup 1)))
1648 (set (match_dup 2)
1649 (compare:CC (match_dup 0)
1650 (const_int 0)))]
1651 "")
1653 (define_insn ""
1654 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1655 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1656 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1657 ""
1658 "@
1659 subf %0,%2,%1
1660 subfic %0,%2,%1"
1661 [(set_attr "type" "add")])
1663 (define_insn ""
1664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1665 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1666 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 3 "=r,r"))]
1669 ""
1670 "@
1671 subf. %3,%2,%1
1672 #"
1673 [(set_attr "type" "add")
1674 (set_attr "dot" "yes")
1675 (set_attr "length" "4,8")])
1677 (define_split
1678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1679 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1680 (match_operand:P 2 "gpc_reg_operand" ""))
1681 (const_int 0)))
1682 (clobber (match_scratch:P 3 ""))]
1683 "reload_completed"
1684 [(set (match_dup 3)
1685 (minus:P (match_dup 1)
1686 (match_dup 2)))
1687 (set (match_dup 0)
1688 (compare:CC (match_dup 3)
1689 (const_int 0)))]
1690 "")
1692 (define_insn ""
1693 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1694 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1695 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1696 (const_int 0)))
1697 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1698 (minus:P (match_dup 1)
1699 (match_dup 2)))]
1700 ""
1701 "@
1702 subf. %0,%2,%1
1703 #"
1704 [(set_attr "type" "add")
1705 (set_attr "dot" "yes")
1706 (set_attr "length" "4,8")])
1708 (define_split
1709 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1710 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1711 (match_operand:P 2 "gpc_reg_operand" ""))
1712 (const_int 0)))
1713 (set (match_operand:P 0 "gpc_reg_operand" "")
1714 (minus:P (match_dup 1)
1715 (match_dup 2)))]
1716 "reload_completed"
1717 [(set (match_dup 0)
1718 (minus:P (match_dup 1)
1719 (match_dup 2)))
1720 (set (match_dup 3)
1721 (compare:CC (match_dup 0)
1722 (const_int 0)))]
1723 "")
1725 (define_expand "sub<mode>3"
1726 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1727 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1728 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1729 ""
1730 "
1731 {
1732 if (GET_CODE (operands[2]) == CONST_INT)
1733 {
1734 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1735 negate_rtx (<MODE>mode, operands[2])));
1736 DONE;
1737 }
1738 }")
1740 (define_expand "neg<mode>2"
1741 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1742 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1743 ""
1744 "")
1746 (define_insn "*neg<mode>2_internal"
1747 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1748 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1749 ""
1750 "neg %0,%1"
1751 [(set_attr "type" "add")])
1753 (define_insn ""
1754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1755 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1756 (const_int 0)))
1757 (clobber (match_scratch:P 2 "=r,r"))]
1758 ""
1759 "@
1760 neg. %2,%1
1761 #"
1762 [(set_attr "type" "add")
1763 (set_attr "dot" "yes")
1764 (set_attr "length" "4,8")])
1766 (define_split
1767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1768 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1769 (const_int 0)))
1770 (clobber (match_scratch:P 2 ""))]
1771 "reload_completed"
1772 [(set (match_dup 2)
1773 (neg:P (match_dup 1)))
1774 (set (match_dup 0)
1775 (compare:CC (match_dup 2)
1776 (const_int 0)))]
1777 "")
1779 (define_insn ""
1780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1781 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1782 (const_int 0)))
1783 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1784 (neg:P (match_dup 1)))]
1785 ""
1786 "@
1787 neg. %0,%1
1788 #"
1789 [(set_attr "type" "add")
1790 (set_attr "dot" "yes")
1791 (set_attr "length" "4,8")])
1793 (define_split
1794 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1795 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1796 (const_int 0)))
1797 (set (match_operand:P 0 "gpc_reg_operand" "")
1798 (neg:P (match_dup 1)))]
1799 "reload_completed"
1800 [(set (match_dup 0)
1801 (neg:P (match_dup 1)))
1802 (set (match_dup 2)
1803 (compare:CC (match_dup 0)
1804 (const_int 0)))]
1805 "")
1807 (define_insn "clz<mode>2"
1808 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1809 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1810 ""
1811 "cntlz<wd> %0,%1"
1812 [(set_attr "type" "cntlz")])
1814 (define_expand "ctz<mode>2"
1815 [(set (match_dup 2)
1816 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1817 (set (match_dup 3)
1818 (and:GPR (match_dup 1)
1819 (match_dup 2)))
1820 (set (match_dup 4)
1821 (clz:GPR (match_dup 3)))
1822 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1823 (minus:GPR (match_dup 5)
1824 (match_dup 4)))]
1825 ""
1826 {
1827 operands[2] = gen_reg_rtx (<MODE>mode);
1828 operands[3] = gen_reg_rtx (<MODE>mode);
1829 operands[4] = gen_reg_rtx (<MODE>mode);
1830 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1831 })
1833 (define_expand "ffs<mode>2"
1834 [(set (match_dup 2)
1835 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1836 (set (match_dup 3)
1837 (and:GPR (match_dup 1)
1838 (match_dup 2)))
1839 (set (match_dup 4)
1840 (clz:GPR (match_dup 3)))
1841 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1842 (minus:GPR (match_dup 5)
1843 (match_dup 4)))]
1844 ""
1845 {
1846 operands[2] = gen_reg_rtx (<MODE>mode);
1847 operands[3] = gen_reg_rtx (<MODE>mode);
1848 operands[4] = gen_reg_rtx (<MODE>mode);
1849 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1850 })
1852 (define_insn "popcntb<mode>2"
1853 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1854 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1855 UNSPEC_POPCNTB))]
1856 "TARGET_POPCNTB"
1857 "popcntb %0,%1"
1858 [(set_attr "length" "4")
1859 (set_attr "type" "popcnt")])
1861 (define_insn "popcntd<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1864 "TARGET_POPCNTD"
1865 "popcnt<wd> %0,%1"
1866 [(set_attr "length" "4")
1867 (set_attr "type" "popcnt")])
1869 (define_expand "popcount<mode>2"
1870 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1871 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1872 "TARGET_POPCNTB || TARGET_POPCNTD"
1873 {
1874 rs6000_emit_popcount (operands[0], operands[1]);
1875 DONE;
1876 })
1878 (define_insn "parity<mode>2_cmpb"
1879 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1880 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1881 "TARGET_CMPB && TARGET_POPCNTB"
1882 "prty<wd> %0,%1"
1883 [(set_attr "length" "4")
1884 (set_attr "type" "popcnt")])
1886 (define_expand "parity<mode>2"
1887 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1888 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1889 "TARGET_POPCNTB"
1890 {
1891 rs6000_emit_parity (operands[0], operands[1]);
1892 DONE;
1893 })
1895 ;; Since the hardware zeros the upper part of the register, save generating the
1896 ;; AND immediate if we are converting to unsigned
1897 (define_insn "*bswaphi2_extenddi"
1898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1899 (zero_extend:DI
1900 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1901 "TARGET_POWERPC64"
1902 "lhbrx %0,%y1"
1903 [(set_attr "length" "4")
1904 (set_attr "type" "load")])
1906 (define_insn "*bswaphi2_extendsi"
1907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1908 (zero_extend:SI
1909 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1910 ""
1911 "lhbrx %0,%y1"
1912 [(set_attr "length" "4")
1913 (set_attr "type" "load")])
1915 (define_expand "bswaphi2"
1916 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1917 (bswap:HI
1918 (match_operand:HI 1 "reg_or_mem_operand" "")))
1919 (clobber (match_scratch:SI 2 ""))])]
1920 ""
1921 {
1922 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1923 operands[1] = force_reg (HImode, operands[1]);
1924 })
1926 (define_insn "bswaphi2_internal"
1927 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1928 (bswap:HI
1929 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1930 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1931 ""
1932 "@
1933 lhbrx %0,%y1
1934 sthbrx %1,%y0
1935 #"
1936 [(set_attr "length" "4,4,12")
1937 (set_attr "type" "load,store,*")])
1939 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1940 ;; correct for -mlittle as well as -mbig.
1941 (define_split
1942 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1943 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1944 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1945 "reload_completed"
1946 [(set (match_dup 3)
1947 (zero_extract:SI (match_dup 4)
1948 (const_int 8)
1949 (const_int 16)))
1950 (set (match_dup 2)
1951 (and:SI (ashift:SI (match_dup 4)
1952 (const_int 8))
1953 (const_int 65280))) ;; 0xff00
1954 (set (match_dup 3)
1955 (ior:SI (match_dup 3)
1956 (match_dup 2)))]
1957 "
1958 {
1959 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1960 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1961 }")
1963 (define_insn "*bswapsi2_extenddi"
1964 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1965 (zero_extend:DI
1966 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1967 "TARGET_POWERPC64"
1968 "lwbrx %0,%y1"
1969 [(set_attr "length" "4")
1970 (set_attr "type" "load")])
1972 (define_expand "bswapsi2"
1973 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1974 (bswap:SI
1975 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1976 ""
1977 {
1978 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1979 operands[1] = force_reg (SImode, operands[1]);
1980 })
1982 (define_insn "*bswapsi2_internal"
1983 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1984 (bswap:SI
1985 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1986 ""
1987 "@
1988 lwbrx %0,%y1
1989 stwbrx %1,%y0
1990 #"
1991 [(set_attr "length" "4,4,12")
1992 (set_attr "type" "load,store,*")])
1994 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1995 ;; zero_extract insns do not change for -mlittle.
1996 (define_split
1997 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1998 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1999 "reload_completed"
2000 [(set (match_dup 0)
2001 (rotate:SI (match_dup 1) (const_int 8)))
2002 (set (zero_extract:SI (match_dup 0)
2003 (const_int 8)
2004 (const_int 0))
2005 (match_dup 1))
2006 (set (zero_extract:SI (match_dup 0)
2007 (const_int 8)
2008 (const_int 16))
2009 (rotate:SI (match_dup 1)
2010 (const_int 16)))]
2011 "")
2013 (define_expand "bswapdi2"
2014 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2015 (bswap:DI
2016 (match_operand:DI 1 "reg_or_mem_operand" "")))
2017 (clobber (match_scratch:DI 2 ""))
2018 (clobber (match_scratch:DI 3 ""))
2019 (clobber (match_scratch:DI 4 ""))])]
2020 ""
2021 {
2022 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2023 operands[1] = force_reg (DImode, operands[1]);
2025 if (!TARGET_POWERPC64)
2026 {
2027 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2028 that uses 64-bit registers needs the same scratch registers as 64-bit
2029 mode. */
2030 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2031 DONE;
2032 }
2033 })
2035 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2036 (define_insn "*bswapdi2_ldbrx"
2037 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2038 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2039 (clobber (match_scratch:DI 2 "=X,X,&r"))
2040 (clobber (match_scratch:DI 3 "=X,X,&r"))
2041 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2042 "TARGET_POWERPC64 && TARGET_LDBRX
2043 && (REG_P (operands[0]) || REG_P (operands[1]))"
2044 "@
2045 ldbrx %0,%y1
2046 stdbrx %1,%y0
2047 #"
2048 [(set_attr "length" "4,4,36")
2049 (set_attr "type" "load,store,*")])
2051 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2052 (define_insn "*bswapdi2_64bit"
2053 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2054 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2055 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2056 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2057 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2058 "TARGET_POWERPC64 && !TARGET_LDBRX
2059 && (REG_P (operands[0]) || REG_P (operands[1]))
2060 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2061 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2062 "#"
2063 [(set_attr "length" "16,12,36")])
2065 (define_split
2066 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2067 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2068 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2069 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2070 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2071 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2072 [(const_int 0)]
2073 "
2074 {
2075 rtx dest = operands[0];
2076 rtx src = operands[1];
2077 rtx op2 = operands[2];
2078 rtx op3 = operands[3];
2079 rtx op4 = operands[4];
2080 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2081 BYTES_BIG_ENDIAN ? 4 : 0);
2082 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2083 BYTES_BIG_ENDIAN ? 4 : 0);
2084 rtx addr1;
2085 rtx addr2;
2086 rtx word_high;
2087 rtx word_low;
2089 addr1 = XEXP (src, 0);
2090 if (GET_CODE (addr1) == PLUS)
2091 {
2092 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2093 if (TARGET_AVOID_XFORM)
2094 {
2095 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2096 addr2 = op2;
2097 }
2098 else
2099 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2100 }
2101 else if (TARGET_AVOID_XFORM)
2102 {
2103 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2104 addr2 = op2;
2105 }
2106 else
2107 {
2108 emit_move_insn (op2, GEN_INT (4));
2109 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2110 }
2112 if (BYTES_BIG_ENDIAN)
2113 {
2114 word_high = change_address (src, SImode, addr1);
2115 word_low = change_address (src, SImode, addr2);
2116 }
2117 else
2118 {
2119 word_high = change_address (src, SImode, addr2);
2120 word_low = change_address (src, SImode, addr1);
2121 }
2123 emit_insn (gen_bswapsi2 (op3_32, word_low));
2124 emit_insn (gen_bswapsi2 (op4_32, word_high));
2125 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2126 emit_insn (gen_iordi3 (dest, dest, op4));
2127 DONE;
2128 }")
2130 (define_split
2131 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2132 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2133 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2134 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2135 (clobber (match_operand:DI 4 "" ""))]
2136 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2137 [(const_int 0)]
2138 "
2139 {
2140 rtx dest = operands[0];
2141 rtx src = operands[1];
2142 rtx op2 = operands[2];
2143 rtx op3 = operands[3];
2144 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2145 BYTES_BIG_ENDIAN ? 4 : 0);
2146 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2147 BYTES_BIG_ENDIAN ? 4 : 0);
2148 rtx addr1;
2149 rtx addr2;
2150 rtx word_high;
2151 rtx word_low;
2153 addr1 = XEXP (dest, 0);
2154 if (GET_CODE (addr1) == PLUS)
2155 {
2156 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2157 if (TARGET_AVOID_XFORM)
2158 {
2159 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2160 addr2 = op2;
2161 }
2162 else
2163 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2164 }
2165 else if (TARGET_AVOID_XFORM)
2166 {
2167 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2168 addr2 = op2;
2169 }
2170 else
2171 {
2172 emit_move_insn (op2, GEN_INT (4));
2173 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2174 }
2176 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2177 if (BYTES_BIG_ENDIAN)
2178 {
2179 word_high = change_address (dest, SImode, addr1);
2180 word_low = change_address (dest, SImode, addr2);
2181 }
2182 else
2183 {
2184 word_high = change_address (dest, SImode, addr2);
2185 word_low = change_address (dest, SImode, addr1);
2186 }
2187 emit_insn (gen_bswapsi2 (word_high, src_si));
2188 emit_insn (gen_bswapsi2 (word_low, op3_si));
2189 DONE;
2190 }")
2192 (define_split
2193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2194 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2195 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2196 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2197 (clobber (match_operand:DI 4 "" ""))]
2198 "TARGET_POWERPC64 && reload_completed"
2199 [(const_int 0)]
2200 "
2201 {
2202 rtx dest = operands[0];
2203 rtx src = operands[1];
2204 rtx op2 = operands[2];
2205 rtx op3 = operands[3];
2206 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2207 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2208 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2209 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2210 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2212 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2213 emit_insn (gen_bswapsi2 (dest_si, src_si));
2214 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2215 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2216 emit_insn (gen_iordi3 (dest, dest, op3));
2217 DONE;
2218 }")
2220 (define_insn "bswapdi2_32bit"
2221 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2222 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2223 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2224 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2225 "#"
2226 [(set_attr "length" "16,12,36")])
2228 (define_split
2229 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2230 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2231 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2232 "!TARGET_POWERPC64 && reload_completed"
2233 [(const_int 0)]
2234 "
2235 {
2236 rtx dest = operands[0];
2237 rtx src = operands[1];
2238 rtx op2 = operands[2];
2239 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2240 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2241 rtx addr1;
2242 rtx addr2;
2243 rtx word1;
2244 rtx word2;
2246 addr1 = XEXP (src, 0);
2247 if (GET_CODE (addr1) == PLUS)
2248 {
2249 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2250 if (TARGET_AVOID_XFORM)
2251 {
2252 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2253 addr2 = op2;
2254 }
2255 else
2256 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2257 }
2258 else if (TARGET_AVOID_XFORM)
2259 {
2260 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2261 addr2 = op2;
2262 }
2263 else
2264 {
2265 emit_move_insn (op2, GEN_INT (4));
2266 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2267 }
2269 word1 = change_address (src, SImode, addr1);
2270 word2 = change_address (src, SImode, addr2);
2272 emit_insn (gen_bswapsi2 (dest2, word1));
2273 emit_insn (gen_bswapsi2 (dest1, word2));
2274 DONE;
2275 }")
2277 (define_split
2278 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2279 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2280 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2281 "!TARGET_POWERPC64 && reload_completed"
2282 [(const_int 0)]
2283 "
2284 {
2285 rtx dest = operands[0];
2286 rtx src = operands[1];
2287 rtx op2 = operands[2];
2288 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2289 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2290 rtx addr1;
2291 rtx addr2;
2292 rtx word1;
2293 rtx word2;
2295 addr1 = XEXP (dest, 0);
2296 if (GET_CODE (addr1) == PLUS)
2297 {
2298 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2299 if (TARGET_AVOID_XFORM)
2300 {
2301 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2302 addr2 = op2;
2303 }
2304 else
2305 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2306 }
2307 else if (TARGET_AVOID_XFORM)
2308 {
2309 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2310 addr2 = op2;
2311 }
2312 else
2313 {
2314 emit_move_insn (op2, GEN_INT (4));
2315 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2316 }
2318 word1 = change_address (dest, SImode, addr1);
2319 word2 = change_address (dest, SImode, addr2);
2321 emit_insn (gen_bswapsi2 (word2, src1));
2322 emit_insn (gen_bswapsi2 (word1, src2));
2323 DONE;
2324 }")
2326 (define_split
2327 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2328 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2329 (clobber (match_operand:SI 2 "" ""))]
2330 "!TARGET_POWERPC64 && reload_completed"
2331 [(const_int 0)]
2332 "
2333 {
2334 rtx dest = operands[0];
2335 rtx src = operands[1];
2336 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2337 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2338 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2339 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2341 emit_insn (gen_bswapsi2 (dest1, src2));
2342 emit_insn (gen_bswapsi2 (dest2, src1));
2343 DONE;
2344 }")
2347 (define_insn "mul<mode>3"
2348 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2349 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2350 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2351 ""
2352 "@
2353 mull<wd> %0,%1,%2
2354 mulli %0,%1,%2"
2355 [(set_attr "type" "mul")
2356 (set (attr "size")
2357 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2358 (const_string "8")
2359 (match_operand:GPR 2 "short_cint_operand" "")
2360 (const_string "16")]
2361 (const_string "<bits>")))])
2363 (define_insn_and_split "*mul<mode>3_dot"
2364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2365 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2366 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2367 (const_int 0)))
2368 (clobber (match_scratch:GPR 0 "=r,r"))]
2369 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2370 "@
2371 mull<wd>. %0,%1,%2
2372 #"
2373 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2374 [(set (match_dup 0)
2375 (mult:GPR (match_dup 1)
2376 (match_dup 2)))
2377 (set (match_dup 3)
2378 (compare:CC (match_dup 0)
2379 (const_int 0)))]
2380 ""
2381 [(set_attr "type" "mul")
2382 (set_attr "size" "<bits>")
2383 (set_attr "dot" "yes")
2384 (set_attr "length" "4,8")])
2386 (define_insn_and_split "*mul<mode>3_dot2"
2387 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2388 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2389 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2390 (const_int 0)))
2391 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2392 (mult:GPR (match_dup 1)
2393 (match_dup 2)))]
2394 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2395 "@
2396 mull<wd>. %0,%1,%2
2397 #"
2398 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2399 [(set (match_dup 0)
2400 (mult:GPR (match_dup 1)
2401 (match_dup 2)))
2402 (set (match_dup 3)
2403 (compare:CC (match_dup 0)
2404 (const_int 0)))]
2405 ""
2406 [(set_attr "type" "mul")
2407 (set_attr "size" "<bits>")
2408 (set_attr "dot" "yes")
2409 (set_attr "length" "4,8")])
2412 (define_expand "<su>mul<mode>3_highpart"
2413 [(set (match_operand:GPR 0 "gpc_reg_operand")
2414 (subreg:GPR
2415 (mult:<DMODE> (any_extend:<DMODE>
2416 (match_operand:GPR 1 "gpc_reg_operand"))
2417 (any_extend:<DMODE>
2418 (match_operand:GPR 2 "gpc_reg_operand")))
2419 0))]
2420 ""
2421 {
2422 if (<MODE>mode == SImode && TARGET_POWERPC64)
2423 {
2424 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2425 operands[2]));
2426 DONE;
2427 }
2429 if (!WORDS_BIG_ENDIAN)
2430 {
2431 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2432 operands[2]));
2433 DONE;
2434 }
2435 })
2437 (define_insn "*<su>mul<mode>3_highpart"
2438 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2439 (subreg:GPR
2440 (mult:<DMODE> (any_extend:<DMODE>
2441 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2442 (any_extend:<DMODE>
2443 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2444 0))]
2445 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2446 "mulh<wd><u> %0,%1,%2"
2447 [(set_attr "type" "mul")
2448 (set_attr "size" "<bits>")])
2450 (define_insn "<su>mulsi3_highpart_le"
2451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2452 (subreg:SI
2453 (mult:DI (any_extend:DI
2454 (match_operand:SI 1 "gpc_reg_operand" "r"))
2455 (any_extend:DI
2456 (match_operand:SI 2 "gpc_reg_operand" "r")))
2457 4))]
2458 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2459 "mulhw<u> %0,%1,%2"
2460 [(set_attr "type" "mul")])
2462 (define_insn "<su>muldi3_highpart_le"
2463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2464 (subreg:DI
2465 (mult:TI (any_extend:TI
2466 (match_operand:DI 1 "gpc_reg_operand" "r"))
2467 (any_extend:TI
2468 (match_operand:DI 2 "gpc_reg_operand" "r")))
2469 8))]
2470 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2471 "mulhd<u> %0,%1,%2"
2472 [(set_attr "type" "mul")
2473 (set_attr "size" "64")])
2475 (define_insn "<su>mulsi3_highpart_64"
2476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2477 (truncate:SI
2478 (lshiftrt:DI
2479 (mult:DI (any_extend:DI
2480 (match_operand:SI 1 "gpc_reg_operand" "r"))
2481 (any_extend:DI
2482 (match_operand:SI 2 "gpc_reg_operand" "r")))
2483 (const_int 32))))]
2484 "TARGET_POWERPC64"
2485 "mulhw<u> %0,%1,%2"
2486 [(set_attr "type" "mul")])
2488 (define_expand "<u>mul<mode><dmode>3"
2489 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2490 (mult:<DMODE> (any_extend:<DMODE>
2491 (match_operand:GPR 1 "gpc_reg_operand"))
2492 (any_extend:<DMODE>
2493 (match_operand:GPR 2 "gpc_reg_operand"))))]
2494 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2495 {
2496 rtx l = gen_reg_rtx (<MODE>mode);
2497 rtx h = gen_reg_rtx (<MODE>mode);
2498 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2499 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2500 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2501 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2502 DONE;
2503 })
2506 (define_insn "udiv<mode>3"
2507 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2508 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2509 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2510 ""
2511 "div<wd>u %0,%1,%2"
2512 [(set_attr "type" "div")
2513 (set_attr "size" "<bits>")])
2516 ;; For powers of two we can do srai/aze for divide and then adjust for
2517 ;; modulus. If it isn't a power of two, force operands into register and do
2518 ;; a normal divide.
2519 (define_expand "div<mode>3"
2520 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2521 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2522 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2523 ""
2524 {
2525 if (GET_CODE (operands[2]) != CONST_INT
2526 || INTVAL (operands[2]) <= 0
2527 || exact_log2 (INTVAL (operands[2])) < 0)
2528 operands[2] = force_reg (<MODE>mode, operands[2]);
2529 })
2531 (define_insn "*div<mode>3"
2532 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2533 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2534 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2535 ""
2536 "div<wd> %0,%1,%2"
2537 [(set_attr "type" "div")
2538 (set_attr "size" "<bits>")])
2540 (define_expand "mod<mode>3"
2541 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2542 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2543 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2544 ""
2545 "
2546 {
2547 int i;
2548 rtx temp1;
2549 rtx temp2;
2551 if (GET_CODE (operands[2]) != CONST_INT
2552 || INTVAL (operands[2]) <= 0
2553 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2554 FAIL;
2556 temp1 = gen_reg_rtx (<MODE>mode);
2557 temp2 = gen_reg_rtx (<MODE>mode);
2559 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2560 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2561 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2562 DONE;
2563 }")
2565 (define_insn ""
2566 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2567 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2568 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2569 ""
2570 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2571 [(set_attr "type" "two")
2572 (set_attr "length" "8")])
2574 (define_insn ""
2575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2576 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2577 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2578 (const_int 0)))
2579 (clobber (match_scratch:P 3 "=r,r"))]
2580 ""
2581 "@
2582 sra<wd>i %3,%1,%p2\;addze. %3,%3
2583 #"
2584 [(set_attr "type" "compare")
2585 (set_attr "length" "8,12")
2586 (set_attr "cell_micro" "not")])
2588 (define_split
2589 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2590 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2591 (match_operand:GPR 2 "exact_log2_cint_operand"
2592 ""))
2593 (const_int 0)))
2594 (clobber (match_scratch:GPR 3 ""))]
2595 "reload_completed"
2596 [(set (match_dup 3)
2597 (div:<MODE> (match_dup 1) (match_dup 2)))
2598 (set (match_dup 0)
2599 (compare:CC (match_dup 3)
2600 (const_int 0)))]
2601 "")
2603 (define_insn ""
2604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2605 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2606 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2607 (const_int 0)))
2608 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2609 (div:P (match_dup 1) (match_dup 2)))]
2610 ""
2611 "@
2612 sra<wd>i %0,%1,%p2\;addze. %0,%0
2613 #"
2614 [(set_attr "type" "compare")
2615 (set_attr "length" "8,12")
2616 (set_attr "cell_micro" "not")])
2618 (define_split
2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2620 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2621 (match_operand:GPR 2 "exact_log2_cint_operand"
2622 ""))
2623 (const_int 0)))
2624 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2625 (div:GPR (match_dup 1) (match_dup 2)))]
2626 "reload_completed"
2627 [(set (match_dup 0)
2628 (div:<MODE> (match_dup 1) (match_dup 2)))
2629 (set (match_dup 3)
2630 (compare:CC (match_dup 0)
2631 (const_int 0)))]
2632 "")
2633 \f
2634 ;; Logical instructions
2635 ;; The logical instructions are mostly combined by using match_operator,
2636 ;; but the plain AND insns are somewhat different because there is no
2637 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2638 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2640 (define_expand "and<mode>3"
2641 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2642 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2643 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2644 ""
2645 {
2646 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2647 {
2648 rs6000_split_logical (operands, AND, false, false, false);
2649 DONE;
2650 }
2652 if (logical_const_operand (operands[2], <MODE>mode)
2653 && !any_mask_operand (operands[2], <MODE>mode))
2654 {
2655 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2656 DONE;
2657 }
2659 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2660 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2661 operands[2] = force_reg (<MODE>mode, operands[2]);
2662 })
2665 (define_insn "*and<mode>3"
2666 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2667 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2668 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2669 ""
2670 "and %0,%1,%2"
2671 [(set_attr "type" "logical")])
2673 (define_insn_and_split "*and<mode>3_dot"
2674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2675 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2676 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2677 (const_int 0)))
2678 (clobber (match_scratch:GPR 0 "=r,r"))]
2679 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2680 "@
2681 and. %0,%1,%2
2682 #"
2683 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2684 [(set (match_dup 0)
2685 (and:GPR (match_dup 1)
2686 (match_dup 2)))
2687 (set (match_dup 3)
2688 (compare:CC (match_dup 0)
2689 (const_int 0)))]
2690 ""
2691 [(set_attr "type" "logical")
2692 (set_attr "dot" "yes")
2693 (set_attr "length" "4,8")])
2695 (define_insn_and_split "*and<mode>3_dot2"
2696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2697 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2698 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2699 (const_int 0)))
2700 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2701 (and:GPR (match_dup 1)
2702 (match_dup 2)))]
2703 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2704 "@
2705 and. %0,%1,%2
2706 #"
2707 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2708 [(set (match_dup 0)
2709 (and:GPR (match_dup 1)
2710 (match_dup 2)))
2711 (set (match_dup 3)
2712 (compare:CC (match_dup 0)
2713 (const_int 0)))]
2714 ""
2715 [(set_attr "type" "logical")
2716 (set_attr "dot" "yes")
2717 (set_attr "length" "4,8")])
2720 (define_insn "and<mode>3_imm"
2721 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2722 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2723 (match_operand:GPR 2 "logical_const_operand" "n")))
2724 (clobber (match_scratch:CC 3 "=x"))]
2725 "rs6000_gen_cell_microcode
2726 && !any_mask_operand (operands[2], <MODE>mode)"
2727 "andi%e2. %0,%1,%u2"
2728 [(set_attr "type" "logical")
2729 (set_attr "dot" "yes")])
2731 (define_insn_and_split "*and<mode>3_imm_dot"
2732 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2733 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2734 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2735 (const_int 0)))
2736 (clobber (match_scratch:GPR 0 "=r,r"))
2737 (clobber (match_scratch:CC 4 "=X,x"))]
2738 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2739 && rs6000_gen_cell_microcode"
2740 "@
2741 andi%e2. %0,%1,%u2
2742 #"
2743 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2744 [(parallel [(set (match_dup 0)
2745 (and:GPR (match_dup 1)
2746 (match_dup 2)))
2747 (clobber (match_dup 4))])
2748 (set (match_dup 3)
2749 (compare:CC (match_dup 0)
2750 (const_int 0)))]
2751 ""
2752 [(set_attr "type" "logical")
2753 (set_attr "dot" "yes")
2754 (set_attr "length" "4,8")])
2756 (define_insn_and_split "*and<mode>3_imm_dot2"
2757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2758 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2759 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2760 (const_int 0)))
2761 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2762 (and:GPR (match_dup 1)
2763 (match_dup 2)))
2764 (clobber (match_scratch:CC 4 "=X,x"))]
2765 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2766 && rs6000_gen_cell_microcode"
2767 "@
2768 andi%e2. %0,%1,%u2
2769 #"
2770 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2771 [(parallel [(set (match_dup 0)
2772 (and:GPR (match_dup 1)
2773 (match_dup 2)))
2774 (clobber (match_dup 4))])
2775 (set (match_dup 3)
2776 (compare:CC (match_dup 0)
2777 (const_int 0)))]
2778 ""
2779 [(set_attr "type" "logical")
2780 (set_attr "dot" "yes")
2781 (set_attr "length" "4,8")])
2784 (define_insn "*and<mode>3_mask"
2785 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2786 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2787 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2788 ""
2789 "@
2790 rldic%B2 %0,%1,0,%S2
2791 rlwinm %0,%1,0,%m2,%M2"
2792 [(set_attr "type" "shift")])
2794 (define_insn_and_split "*and<mode>3_mask_dot"
2795 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2796 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2797 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2798 (const_int 0)))
2799 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2800 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2801 && rs6000_gen_cell_microcode
2802 && !logical_const_operand (operands[2], <MODE>mode)"
2803 "@
2804 rldic%B2. %0,%1,0,%S2
2805 rlwinm. %0,%1,0,%m2,%M2
2806 #
2807 #"
2808 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2809 [(set (match_dup 0)
2810 (and:GPR (match_dup 1)
2811 (match_dup 2)))
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 ""
2816 [(set_attr "type" "shift")
2817 (set_attr "dot" "yes")
2818 (set_attr "length" "4,4,8,8")])
2820 (define_insn_and_split "*and<mode>3_mask_dot2"
2821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2822 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2823 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2824 (const_int 0)))
2825 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2826 (and:GPR (match_dup 1)
2827 (match_dup 2)))]
2828 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2829 && rs6000_gen_cell_microcode
2830 && !logical_const_operand (operands[2], <MODE>mode)"
2831 "@
2832 rldic%B2. %0,%1,0,%S2
2833 rlwinm. %0,%1,0,%m2,%M2
2834 #
2835 #"
2836 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2837 [(set (match_dup 0)
2838 (and:GPR (match_dup 1)
2839 (match_dup 2)))
2840 (set (match_dup 3)
2841 (compare:CC (match_dup 0)
2842 (const_int 0)))]
2843 ""
2844 [(set_attr "type" "shift")
2845 (set_attr "dot" "yes")
2846 (set_attr "length" "4,4,8,8")])
2850 (define_insn "andsi3_internal0_nomc"
2851 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2852 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2853 (match_operand:SI 2 "and_operand" "?r,T")))]
2854 "!rs6000_gen_cell_microcode"
2855 "@
2856 and %0,%1,%2
2857 rlwinm %0,%1,0,%m2,%M2"
2858 [(set_attr "type" "logical,shift")])
2861 ;; Handle the PowerPC64 rlwinm corner case
2863 (define_insn_and_split "*andsi3_internal6"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2865 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2866 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2867 "TARGET_POWERPC64"
2868 "#"
2869 "TARGET_POWERPC64"
2870 [(set (match_dup 0)
2871 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2872 (match_dup 4)))
2873 (set (match_dup 0)
2874 (rotate:SI (match_dup 0) (match_dup 5)))]
2875 "
2876 {
2877 int mb = extract_MB (operands[2]);
2878 int me = extract_ME (operands[2]);
2879 operands[3] = GEN_INT (me + 1);
2880 operands[5] = GEN_INT (32 - (me + 1));
2881 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2882 }"
2883 [(set_attr "length" "8")])
2886 (define_expand "ior<mode>3"
2887 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2888 (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2889 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2890 ""
2891 {
2892 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2893 {
2894 rs6000_split_logical (operands, IOR, false, false, false);
2895 DONE;
2896 }
2898 if (non_logical_cint_operand (operands[2], <MODE>mode))
2899 {
2900 rtx tmp = ((!can_create_pseudo_p ()
2901 || rtx_equal_p (operands[0], operands[1]))
2902 ? operands[0] : gen_reg_rtx (<MODE>mode));
2903 HOST_WIDE_INT value = INTVAL (operands[2]);
2905 emit_insn (gen_ior<mode>3 (tmp, operands[1],
2906 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2908 emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2909 DONE;
2910 }
2912 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2913 operands[2] = force_reg (<MODE>mode, operands[2]);
2914 })
2916 (define_expand "xor<mode>3"
2917 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2918 (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2919 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2920 ""
2921 {
2922 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2923 {
2924 rs6000_split_logical (operands, XOR, false, false, false);
2925 DONE;
2926 }
2928 if (non_logical_cint_operand (operands[2], <MODE>mode))
2929 {
2930 rtx tmp = ((!can_create_pseudo_p ()
2931 || rtx_equal_p (operands[0], operands[1]))
2932 ? operands[0] : gen_reg_rtx (<MODE>mode));
2933 HOST_WIDE_INT value = INTVAL (operands[2]);
2935 emit_insn (gen_xor<mode>3 (tmp, operands[1],
2936 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2938 emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2939 DONE;
2940 }
2942 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2943 operands[2] = force_reg (<MODE>mode, operands[2]);
2944 })
2946 (define_insn "*bool<mode>3"
2947 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2948 (match_operator:GPR 3 "boolean_or_operator"
2949 [(match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2950 (match_operand:GPR 2 "logical_operand" "r,n")]))]
2951 ""
2952 "@
2953 %q3 %0,%1,%2
2954 %q3i%e2 %0,%1,%u2"
2955 [(set_attr "type" "logical")])
2957 (define_insn_and_split "*bool<mode>3_dot"
2958 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2959 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
2960 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2961 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2962 (const_int 0)))
2963 (clobber (match_scratch:GPR 0 "=r,r"))]
2964 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2965 "@
2966 %q3. %0,%1,%2
2967 #"
2968 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2969 [(set (match_dup 0)
2970 (match_dup 3))
2971 (set (match_dup 4)
2972 (compare:CC (match_dup 0)
2973 (const_int 0)))]
2974 ""
2975 [(set_attr "type" "logical")
2976 (set_attr "dot" "yes")
2977 (set_attr "length" "4,8")])
2979 (define_insn_and_split "*bool<mode>3_dot2"
2980 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2981 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
2982 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2983 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2984 (const_int 0)))
2985 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2986 (match_dup 3))]
2987 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2988 "@
2989 %q3. %0,%1,%2
2990 #"
2991 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2992 [(set (match_dup 0)
2993 (match_dup 3))
2994 (set (match_dup 4)
2995 (compare:CC (match_dup 0)
2996 (const_int 0)))]
2997 ""
2998 [(set_attr "type" "logical")
2999 (set_attr "dot" "yes")
3000 (set_attr "length" "4,8")])
3002 ;; Split a logical operation that we can't do in one insn into two insns,
3003 ;; each of which does one 16-bit part. This is used by combine.
3005 (define_split
3006 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3007 (match_operator:GPR 3 "boolean_or_operator"
3008 [(match_operand:GPR 1 "gpc_reg_operand" "")
3009 (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
3010 ""
3011 [(set (match_dup 0) (match_dup 4))
3012 (set (match_dup 0) (match_dup 5))]
3013 {
3014 rtx i;
3015 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3016 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3017 operands[1], i);
3018 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3019 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3020 operands[0], i);
3021 })
3024 (define_insn "*boolc<mode>3"
3025 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3026 (match_operator:GPR 3 "boolean_operator"
3027 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3028 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3029 ""
3030 "%q3 %0,%1,%2"
3031 [(set_attr "type" "logical")])
3033 (define_insn_and_split "*boolc<mode>3_dot"
3034 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3035 (compare:CC (match_operator:GPR 3 "boolean_operator"
3036 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3037 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3038 (const_int 0)))
3039 (clobber (match_scratch:GPR 0 "=r,r"))]
3040 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3041 "@
3042 %q3. %0,%1,%2
3043 #"
3044 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3045 [(set (match_dup 0)
3046 (match_dup 3))
3047 (set (match_dup 4)
3048 (compare:CC (match_dup 0)
3049 (const_int 0)))]
3050 ""
3051 [(set_attr "type" "logical")
3052 (set_attr "dot" "yes")
3053 (set_attr "length" "4,8")])
3055 (define_insn_and_split "*boolc<mode>3_dot2"
3056 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3057 (compare:CC (match_operator:GPR 3 "boolean_operator"
3058 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3059 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3060 (const_int 0)))
3061 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3062 (match_dup 3))]
3063 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3064 "@
3065 %q3. %0,%1,%2
3066 #"
3067 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3068 [(set (match_dup 0)
3069 (match_dup 3))
3070 (set (match_dup 4)
3071 (compare:CC (match_dup 0)
3072 (const_int 0)))]
3073 ""
3074 [(set_attr "type" "logical")
3075 (set_attr "dot" "yes")
3076 (set_attr "length" "4,8")])
3079 (define_insn "*boolcc<mode>3"
3080 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3081 (match_operator:GPR 3 "boolean_operator"
3082 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3083 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3084 ""
3085 "%q3 %0,%1,%2"
3086 [(set_attr "type" "logical")])
3088 (define_insn_and_split "*boolcc<mode>3_dot"
3089 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3090 (compare:CC (match_operator:GPR 3 "boolean_operator"
3091 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3092 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3093 (const_int 0)))
3094 (clobber (match_scratch:GPR 0 "=r,r"))]
3095 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3096 "@
3097 %q3. %0,%1,%2
3098 #"
3099 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3100 [(set (match_dup 0)
3101 (match_dup 3))
3102 (set (match_dup 4)
3103 (compare:CC (match_dup 0)
3104 (const_int 0)))]
3105 ""
3106 [(set_attr "type" "logical")
3107 (set_attr "dot" "yes")
3108 (set_attr "length" "4,8")])
3110 (define_insn_and_split "*boolcc<mode>3_dot2"
3111 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3112 (compare:CC (match_operator:GPR 3 "boolean_operator"
3113 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3114 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3115 (const_int 0)))
3116 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3117 (match_dup 3))]
3118 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3119 "@
3120 %q3. %0,%1,%2
3121 #"
3122 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3123 [(set (match_dup 0)
3124 (match_dup 3))
3125 (set (match_dup 4)
3126 (compare:CC (match_dup 0)
3127 (const_int 0)))]
3128 ""
3129 [(set_attr "type" "logical")
3130 (set_attr "dot" "yes")
3131 (set_attr "length" "4,8")])
3134 ;; TODO: Should have dots of this as well.
3135 (define_insn "*eqv<mode>3"
3136 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3137 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3138 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3139 ""
3140 "eqv %0,%1,%2"
3141 [(set_attr "type" "logical")])
3142 \f
3143 ;; Rotate and shift insns, in all their variants. These support shifts,
3144 ;; field inserts and extracts, and various combinations thereof.
3145 (define_expand "insv"
3146 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3147 (match_operand:SI 1 "const_int_operand" "")
3148 (match_operand:SI 2 "const_int_operand" ""))
3149 (match_operand 3 "gpc_reg_operand" ""))]
3150 ""
3151 "
3152 {
3153 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3154 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3155 compiler if the address of the structure is taken later. Likewise, do
3156 not handle invalid E500 subregs. */
3157 if (GET_CODE (operands[0]) == SUBREG
3158 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3159 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3160 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3161 FAIL;
3163 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3164 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3165 operands[3]));
3166 else
3167 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3168 operands[3]));
3169 DONE;
3170 }")
3172 (define_insn "insvsi_internal"
3173 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3174 (match_operand:SI 1 "const_int_operand" "i")
3175 (match_operand:SI 2 "const_int_operand" "i"))
3176 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3177 ""
3178 "*
3179 {
3180 int start = INTVAL (operands[2]) & 31;
3181 int size = INTVAL (operands[1]) & 31;
3183 operands[4] = GEN_INT (32 - start - size);
3184 operands[1] = GEN_INT (start + size - 1);
3185 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3186 }"
3187 [(set_attr "type" "insert")])
3189 (define_insn "*insvsi_internal1"
3190 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3191 (match_operand:SI 1 "const_int_operand" "i")
3192 (match_operand:SI 2 "const_int_operand" "i"))
3193 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3194 (match_operand:SI 4 "const_int_operand" "i")))]
3195 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3196 "*
3197 {
3198 int shift = INTVAL (operands[4]) & 31;
3199 int start = INTVAL (operands[2]) & 31;
3200 int size = INTVAL (operands[1]) & 31;
3202 operands[4] = GEN_INT (shift - start - size);
3203 operands[1] = GEN_INT (start + size - 1);
3204 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3205 }"
3206 [(set_attr "type" "insert")])
3208 (define_insn "*insvsi_internal2"
3209 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3210 (match_operand:SI 1 "const_int_operand" "i")
3211 (match_operand:SI 2 "const_int_operand" "i"))
3212 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3213 (match_operand:SI 4 "const_int_operand" "i")))]
3214 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3215 "*
3216 {
3217 int shift = INTVAL (operands[4]) & 31;
3218 int start = INTVAL (operands[2]) & 31;
3219 int size = INTVAL (operands[1]) & 31;
3221 operands[4] = GEN_INT (32 - shift - start - size);
3222 operands[1] = GEN_INT (start + size - 1);
3223 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3224 }"
3225 [(set_attr "type" "insert")])
3227 (define_insn "*insvsi_internal3"
3228 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3229 (match_operand:SI 1 "const_int_operand" "i")
3230 (match_operand:SI 2 "const_int_operand" "i"))
3231 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3232 (match_operand:SI 4 "const_int_operand" "i")))]
3233 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3234 "*
3235 {
3236 int shift = INTVAL (operands[4]) & 31;
3237 int start = INTVAL (operands[2]) & 31;
3238 int size = INTVAL (operands[1]) & 31;
3240 operands[4] = GEN_INT (32 - shift - start - size);
3241 operands[1] = GEN_INT (start + size - 1);
3242 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3243 }"
3244 [(set_attr "type" "insert")])
3246 (define_insn "*insvsi_internal4"
3247 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3248 (match_operand:SI 1 "const_int_operand" "i")
3249 (match_operand:SI 2 "const_int_operand" "i"))
3250 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3251 (match_operand:SI 4 "const_int_operand" "i")
3252 (match_operand:SI 5 "const_int_operand" "i")))]
3253 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3254 "*
3255 {
3256 int extract_start = INTVAL (operands[5]) & 31;
3257 int extract_size = INTVAL (operands[4]) & 31;
3258 int insert_start = INTVAL (operands[2]) & 31;
3259 int insert_size = INTVAL (operands[1]) & 31;
3261 /* Align extract field with insert field */
3262 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3263 operands[1] = GEN_INT (insert_start + insert_size - 1);
3264 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3265 }"
3266 [(set_attr "type" "insert")])
3268 ;; combine patterns for rlwimi
3269 (define_insn "*insvsi_internal5"
3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3271 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3272 (match_operand:SI 1 "mask_operand" "i"))
3273 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3274 (match_operand:SI 2 "const_int_operand" "i"))
3275 (match_operand:SI 5 "mask_operand" "i"))))]
3276 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3277 "*
3278 {
3279 int me = extract_ME(operands[5]);
3280 int mb = extract_MB(operands[5]);
3281 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3282 operands[2] = GEN_INT(mb);
3283 operands[1] = GEN_INT(me);
3284 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3285 }"
3286 [(set_attr "type" "insert")])
3288 (define_insn "*insvsi_internal6"
3289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3290 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (match_operand:SI 5 "mask_operand" "i"))
3293 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3294 (match_operand:SI 1 "mask_operand" "i"))))]
3295 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3296 "*
3297 {
3298 int me = extract_ME(operands[5]);
3299 int mb = extract_MB(operands[5]);
3300 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3301 operands[2] = GEN_INT(mb);
3302 operands[1] = GEN_INT(me);
3303 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3304 }"
3305 [(set_attr "type" "insert")])
3307 (define_insn "insvdi_internal"
3308 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3309 (match_operand:SI 1 "const_int_operand" "i")
3310 (match_operand:SI 2 "const_int_operand" "i"))
3311 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3312 "TARGET_POWERPC64"
3313 "*
3314 {
3315 int start = INTVAL (operands[2]) & 63;
3316 int size = INTVAL (operands[1]) & 63;
3318 operands[1] = GEN_INT (64 - start - size);
3319 return \"rldimi %0,%3,%H1,%H2\";
3320 }"
3321 [(set_attr "type" "insert")
3322 (set_attr "size" "64")])
3324 (define_insn "*insvdi_internal2"
3325 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3326 (match_operand:SI 1 "const_int_operand" "i")
3327 (match_operand:SI 2 "const_int_operand" "i"))
3328 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3329 (match_operand:SI 4 "const_int_operand" "i")))]
3330 "TARGET_POWERPC64
3331 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3332 "*
3333 {
3334 int shift = INTVAL (operands[4]) & 63;
3335 int start = (INTVAL (operands[2]) & 63) - 32;
3336 int size = INTVAL (operands[1]) & 63;
3338 operands[4] = GEN_INT (64 - shift - start - size);
3339 operands[2] = GEN_INT (start);
3340 operands[1] = GEN_INT (start + size - 1);
3341 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3342 }")
3344 (define_insn "*insvdi_internal3"
3345 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3346 (match_operand:SI 1 "const_int_operand" "i")
3347 (match_operand:SI 2 "const_int_operand" "i"))
3348 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3349 (match_operand:SI 4 "const_int_operand" "i")))]
3350 "TARGET_POWERPC64
3351 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3352 "*
3353 {
3354 int shift = INTVAL (operands[4]) & 63;
3355 int start = (INTVAL (operands[2]) & 63) - 32;
3356 int size = INTVAL (operands[1]) & 63;
3358 operands[4] = GEN_INT (64 - shift - start - size);
3359 operands[2] = GEN_INT (start);
3360 operands[1] = GEN_INT (start + size - 1);
3361 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3362 }")
3364 (define_expand "extzv"
3365 [(set (match_operand 0 "gpc_reg_operand" "")
3366 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3367 (match_operand:SI 2 "const_int_operand" "")
3368 (match_operand:SI 3 "const_int_operand" "")))]
3369 ""
3370 "
3371 {
3372 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3373 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3374 compiler if the address of the structure is taken later. */
3375 if (GET_CODE (operands[0]) == SUBREG
3376 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3377 FAIL;
3379 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3380 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3381 operands[3]));
3382 else
3383 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3384 operands[3]));
3385 DONE;
3386 }")
3388 (define_insn "extzvsi_internal"
3389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3390 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3391 (match_operand:SI 2 "const_int_operand" "i")
3392 (match_operand:SI 3 "const_int_operand" "i")))]
3393 ""
3394 "*
3395 {
3396 int start = INTVAL (operands[3]) & 31;
3397 int size = INTVAL (operands[2]) & 31;
3399 if (start + size >= 32)
3400 operands[3] = const0_rtx;
3401 else
3402 operands[3] = GEN_INT (start + size);
3403 return \"rlwinm %0,%1,%3,%s2,31\";
3404 }"
3405 [(set_attr "type" "shift")])
3407 (define_insn "*extzvsi_internal1"
3408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3409 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3410 (match_operand:SI 2 "const_int_operand" "i,i")
3411 (match_operand:SI 3 "const_int_operand" "i,i"))
3412 (const_int 0)))
3413 (clobber (match_scratch:SI 4 "=r,r"))]
3414 ""
3415 "*
3416 {
3417 int start = INTVAL (operands[3]) & 31;
3418 int size = INTVAL (operands[2]) & 31;
3420 /* Force split for non-cc0 compare. */
3421 if (which_alternative == 1)
3422 return \"#\";
3424 /* If the bit-field being tested fits in the upper or lower half of a
3425 word, it is possible to use andiu. or andil. to test it. This is
3426 useful because the condition register set-use delay is smaller for
3427 andi[ul]. than for rlinm. This doesn't work when the starting bit
3428 position is 0 because the LT and GT bits may be set wrong. */
3430 if ((start > 0 && start + size <= 16) || start >= 16)
3431 {
3432 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3433 - (1 << (16 - (start & 15) - size))));
3434 if (start < 16)
3435 return \"andis. %4,%1,%3\";
3436 else
3437 return \"andi. %4,%1,%3\";
3438 }
3440 if (start + size >= 32)
3441 operands[3] = const0_rtx;
3442 else
3443 operands[3] = GEN_INT (start + size);
3444 return \"rlwinm. %4,%1,%3,%s2,31\";
3445 }"
3446 [(set_attr "type" "shift")
3447 (set_attr "dot" "yes")
3448 (set_attr "length" "4,8")])
3450 (define_split
3451 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3452 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3453 (match_operand:SI 2 "const_int_operand" "")
3454 (match_operand:SI 3 "const_int_operand" ""))
3455 (const_int 0)))
3456 (clobber (match_scratch:SI 4 ""))]
3457 "reload_completed"
3458 [(set (match_dup 4)
3459 (zero_extract:SI (match_dup 1) (match_dup 2)
3460 (match_dup 3)))
3461 (set (match_dup 0)
3462 (compare:CC (match_dup 4)
3463 (const_int 0)))]
3464 "")
3466 (define_insn "*extzvsi_internal2"
3467 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3468 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3469 (match_operand:SI 2 "const_int_operand" "i,i")
3470 (match_operand:SI 3 "const_int_operand" "i,i"))
3471 (const_int 0)))
3472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3473 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3474 ""
3475 "*
3476 {
3477 int start = INTVAL (operands[3]) & 31;
3478 int size = INTVAL (operands[2]) & 31;
3480 /* Force split for non-cc0 compare. */
3481 if (which_alternative == 1)
3482 return \"#\";
3484 /* Since we are using the output value, we can't ignore any need for
3485 a shift. The bit-field must end at the LSB. */
3486 if (start >= 16 && start + size == 32)
3487 {
3488 operands[3] = GEN_INT ((1 << size) - 1);
3489 return \"andi. %0,%1,%3\";
3490 }
3492 if (start + size >= 32)
3493 operands[3] = const0_rtx;
3494 else
3495 operands[3] = GEN_INT (start + size);
3496 return \"rlwinm. %0,%1,%3,%s2,31\";
3497 }"
3498 [(set_attr "type" "shift")
3499 (set_attr "dot" "yes")
3500 (set_attr "length" "4,8")])
3502 (define_split
3503 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3504 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3505 (match_operand:SI 2 "const_int_operand" "")
3506 (match_operand:SI 3 "const_int_operand" ""))
3507 (const_int 0)))
3508 (set (match_operand:SI 0 "gpc_reg_operand" "")
3509 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3510 "reload_completed"
3511 [(set (match_dup 0)
3512 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3513 (set (match_dup 4)
3514 (compare:CC (match_dup 0)
3515 (const_int 0)))]
3516 "")
3518 (define_insn "extzvdi_internal"
3519 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3520 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3521 (match_operand:SI 2 "const_int_operand" "i")
3522 (match_operand:SI 3 "const_int_operand" "i")))]
3523 "TARGET_POWERPC64"
3524 "*
3525 {
3526 int start = INTVAL (operands[3]) & 63;
3527 int size = INTVAL (operands[2]) & 63;
3529 if (start + size >= 64)
3530 operands[3] = const0_rtx;
3531 else
3532 operands[3] = GEN_INT (start + size);
3533 operands[2] = GEN_INT (64 - size);
3534 return \"rldicl %0,%1,%3,%2\";
3535 }"
3536 [(set_attr "type" "shift")])
3538 (define_insn "*extzvdi_internal1"
3539 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3540 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3541 (match_operand:SI 2 "const_int_operand" "i")
3542 (match_operand:SI 3 "const_int_operand" "i"))
3543 (const_int 0)))
3544 (clobber (match_scratch:DI 4 "=r"))]
3545 "TARGET_64BIT && rs6000_gen_cell_microcode"
3546 "*
3547 {
3548 int start = INTVAL (operands[3]) & 63;
3549 int size = INTVAL (operands[2]) & 63;
3551 if (start + size >= 64)
3552 operands[3] = const0_rtx;
3553 else
3554 operands[3] = GEN_INT (start + size);
3555 operands[2] = GEN_INT (64 - size);
3556 return \"rldicl. %4,%1,%3,%2\";
3557 }"
3558 [(set_attr "type" "shift")
3559 (set_attr "dot" "yes")])
3561 (define_insn "*extzvdi_internal2"
3562 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3563 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3564 (match_operand:SI 2 "const_int_operand" "i")
3565 (match_operand:SI 3 "const_int_operand" "i"))
3566 (const_int 0)))
3567 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3568 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3569 "TARGET_64BIT && rs6000_gen_cell_microcode"
3570 "*
3571 {
3572 int start = INTVAL (operands[3]) & 63;
3573 int size = INTVAL (operands[2]) & 63;
3575 if (start + size >= 64)
3576 operands[3] = const0_rtx;
3577 else
3578 operands[3] = GEN_INT (start + size);
3579 operands[2] = GEN_INT (64 - size);
3580 return \"rldicl. %0,%1,%3,%2\";
3581 }"
3582 [(set_attr "type" "shift")
3583 (set_attr "dot" "yes")])
3586 (define_insn "rotl<mode>3"
3587 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3588 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3589 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3590 ""
3591 "rotl<wd>%I2 %0,%1,%<hH>2"
3592 [(set_attr "type" "shift")
3593 (set_attr "maybe_var_shift" "yes")])
3595 (define_insn "*rotlsi3_64"
3596 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3597 (zero_extend:DI
3598 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3599 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3600 "TARGET_POWERPC64"
3601 "rotlw%I2 %0,%1,%h2"
3602 [(set_attr "type" "shift")
3603 (set_attr "maybe_var_shift" "yes")])
3605 (define_insn_and_split "*rotl<mode>3_dot"
3606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3607 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3608 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3609 (const_int 0)))
3610 (clobber (match_scratch:GPR 0 "=r,r"))]
3611 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3612 "@
3613 rotl<wd>%I2. %0,%1,%<hH>2
3614 #"
3615 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3616 [(set (match_dup 0)
3617 (rotate:GPR (match_dup 1)
3618 (match_dup 2)))
3619 (set (match_dup 3)
3620 (compare:CC (match_dup 0)
3621 (const_int 0)))]
3622 ""
3623 [(set_attr "type" "shift")
3624 (set_attr "maybe_var_shift" "yes")
3625 (set_attr "dot" "yes")
3626 (set_attr "length" "4,8")])
3628 (define_insn_and_split "*rotl<mode>3_dot2"
3629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3630 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3631 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3632 (const_int 0)))
3633 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3634 (rotate:GPR (match_dup 1)
3635 (match_dup 2)))]
3636 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3637 "@
3638 rotl<wd>%I2. %0,%1,%<hH>2
3639 #"
3640 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3641 [(set (match_dup 0)
3642 (rotate:GPR (match_dup 1)
3643 (match_dup 2)))
3644 (set (match_dup 3)
3645 (compare:CC (match_dup 0)
3646 (const_int 0)))]
3647 ""
3648 [(set_attr "type" "shift")
3649 (set_attr "maybe_var_shift" "yes")
3650 (set_attr "dot" "yes")
3651 (set_attr "length" "4,8")])
3654 (define_insn "*rotlsi3_internal4"
3655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3656 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3657 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3658 (match_operand:SI 3 "mask_operand" "n")))]
3659 ""
3660 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3661 [(set_attr "type" "shift")
3662 (set_attr "maybe_var_shift" "yes")])
3664 (define_insn "*rotlsi3_internal5"
3665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3666 (compare:CC (and:SI
3667 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3668 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3669 (match_operand:SI 3 "mask_operand" "n,n"))
3670 (const_int 0)))
3671 (clobber (match_scratch:SI 4 "=r,r"))]
3672 ""
3673 "@
3674 rlw%I2nm. %4,%1,%h2,%m3,%M3
3675 #"
3676 [(set_attr "type" "shift")
3677 (set_attr "maybe_var_shift" "yes")
3678 (set_attr "dot" "yes")
3679 (set_attr "length" "4,8")])
3681 (define_split
3682 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3683 (compare:CC (and:SI
3684 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3685 (match_operand:SI 2 "reg_or_cint_operand" ""))
3686 (match_operand:SI 3 "mask_operand" ""))
3687 (const_int 0)))
3688 (clobber (match_scratch:SI 4 ""))]
3689 "reload_completed"
3690 [(set (match_dup 4)
3691 (and:SI (rotate:SI (match_dup 1)
3692 (match_dup 2))
3693 (match_dup 3)))
3694 (set (match_dup 0)
3695 (compare:CC (match_dup 4)
3696 (const_int 0)))]
3697 "")
3699 (define_insn "*rotlsi3_internal6"
3700 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3701 (compare:CC (and:SI
3702 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3703 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3704 (match_operand:SI 3 "mask_operand" "n,n"))
3705 (const_int 0)))
3706 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3707 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3708 ""
3709 "@
3710 rlw%I2nm. %0,%1,%h2,%m3,%M3
3711 #"
3712 [(set_attr "type" "shift")
3713 (set_attr "maybe_var_shift" "yes")
3714 (set_attr "dot" "yes")
3715 (set_attr "length" "4,8")])
3717 (define_split
3718 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3719 (compare:CC (and:SI
3720 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3721 (match_operand:SI 2 "reg_or_cint_operand" ""))
3722 (match_operand:SI 3 "mask_operand" ""))
3723 (const_int 0)))
3724 (set (match_operand:SI 0 "gpc_reg_operand" "")
3725 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3726 "reload_completed"
3727 [(set (match_dup 0)
3728 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3729 (set (match_dup 4)
3730 (compare:CC (match_dup 0)
3731 (const_int 0)))]
3732 "")
3734 (define_insn "*rotlsi3_internal7le"
3735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3736 (zero_extend:SI
3737 (subreg:QI
3738 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3739 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3740 "!BYTES_BIG_ENDIAN"
3741 "rlw%I2nm %0,%1,%h2,0xff"
3742 [(set (attr "cell_micro")
3743 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3744 (const_string "not")
3745 (const_string "always")))
3746 (set_attr "type" "shift")])
3748 (define_insn "*rotlsi3_internal7be"
3749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3750 (zero_extend:SI
3751 (subreg:QI
3752 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3753 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3754 "BYTES_BIG_ENDIAN"
3755 "rlw%I2nm %0,%1,%h2,0xff"
3756 [(set (attr "cell_micro")
3757 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3758 (const_string "not")
3759 (const_string "always")))
3760 (set_attr "type" "shift")])
3762 (define_insn "*rotlsi3_internal8le"
3763 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3764 (compare:CC (zero_extend:SI
3765 (subreg:QI
3766 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3767 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3768 (const_int 0)))
3769 (clobber (match_scratch:SI 3 "=r,r"))]
3770 "!BYTES_BIG_ENDIAN"
3771 "@
3772 rlw%I2nm. %3,%1,%h2,0xff
3773 #"
3774 [(set_attr "type" "shift")
3775 (set_attr "maybe_var_shift" "yes")
3776 (set_attr "dot" "yes")
3777 (set_attr "length" "4,8")])
3779 (define_insn "*rotlsi3_internal8be"
3780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3781 (compare:CC (zero_extend:SI
3782 (subreg:QI
3783 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3784 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3785 (const_int 0)))
3786 (clobber (match_scratch:SI 3 "=r,r"))]
3787 "BYTES_BIG_ENDIAN"
3788 "@
3789 rlw%I2nm. %3,%1,%h2,0xff
3790 #"
3791 [(set_attr "type" "shift")
3792 (set_attr "maybe_var_shift" "yes")
3793 (set_attr "dot" "yes")
3794 (set_attr "length" "4,8")])
3796 (define_split
3797 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3798 (compare:CC (zero_extend:SI
3799 (subreg:QI
3800 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3801 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3802 (const_int 0)))
3803 (clobber (match_scratch:SI 3 ""))]
3804 "!BYTES_BIG_ENDIAN && reload_completed"
3805 [(set (match_dup 3)
3806 (zero_extend:SI (subreg:QI
3807 (rotate:SI (match_dup 1)
3808 (match_dup 2)) 0)))
3809 (set (match_dup 0)
3810 (compare:CC (match_dup 3)
3811 (const_int 0)))]
3812 "")
3814 (define_split
3815 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3816 (compare:CC (zero_extend:SI
3817 (subreg:QI
3818 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3819 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3820 (const_int 0)))
3821 (clobber (match_scratch:SI 3 ""))]
3822 "BYTES_BIG_ENDIAN && reload_completed"
3823 [(set (match_dup 3)
3824 (zero_extend:SI (subreg:QI
3825 (rotate:SI (match_dup 1)
3826 (match_dup 2)) 3)))
3827 (set (match_dup 0)
3828 (compare:CC (match_dup 3)
3829 (const_int 0)))]
3830 "")
3832 (define_insn "*rotlsi3_internal9le"
3833 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3834 (compare:CC (zero_extend:SI
3835 (subreg:QI
3836 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3837 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3838 (const_int 0)))
3839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3840 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3841 "!BYTES_BIG_ENDIAN"
3842 "@
3843 rlw%I2nm. %0,%1,%h2,0xff
3844 #"
3845 [(set_attr "type" "shift")
3846 (set_attr "maybe_var_shift" "yes")
3847 (set_attr "dot" "yes")
3848 (set_attr "length" "4,8")])
3850 (define_insn "*rotlsi3_internal9be"
3851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3852 (compare:CC (zero_extend:SI
3853 (subreg:QI
3854 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3855 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3856 (const_int 0)))
3857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3858 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3859 "BYTES_BIG_ENDIAN"
3860 "@
3861 rlw%I2nm. %0,%1,%h2,0xff
3862 #"
3863 [(set_attr "type" "shift")
3864 (set_attr "maybe_var_shift" "yes")
3865 (set_attr "dot" "yes")
3866 (set_attr "length" "4,8")])
3868 (define_split
3869 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3870 (compare:CC (zero_extend:SI
3871 (subreg:QI
3872 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3873 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3874 (const_int 0)))
3875 (set (match_operand:SI 0 "gpc_reg_operand" "")
3876 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3877 "!BYTES_BIG_ENDIAN && reload_completed"
3878 [(set (match_dup 0)
3879 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3880 (set (match_dup 3)
3881 (compare:CC (match_dup 0)
3882 (const_int 0)))]
3883 "")
3885 (define_split
3886 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3887 (compare:CC (zero_extend:SI
3888 (subreg:QI
3889 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3890 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3891 (const_int 0)))
3892 (set (match_operand:SI 0 "gpc_reg_operand" "")
3893 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3894 "BYTES_BIG_ENDIAN && reload_completed"
3895 [(set (match_dup 0)
3896 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3897 (set (match_dup 3)
3898 (compare:CC (match_dup 0)
3899 (const_int 0)))]
3900 "")
3902 (define_insn "*rotlsi3_internal10le"
3903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3904 (zero_extend:SI
3905 (subreg:HI
3906 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3907 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3908 "!BYTES_BIG_ENDIAN"
3909 "rlw%I2nm %0,%1,%h2,0xffff"
3910 [(set_attr "type" "shift")
3911 (set_attr "maybe_var_shift" "yes")])
3913 (define_insn "*rotlsi3_internal10be"
3914 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3915 (zero_extend:SI
3916 (subreg:HI
3917 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3919 "BYTES_BIG_ENDIAN"
3920 "rlw%I2nm %0,%1,%h2,0xffff"
3921 [(set_attr "type" "shift")
3922 (set_attr "maybe_var_shift" "yes")])
3924 (define_insn "*rotlsi3_internal11le"
3925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3926 (compare:CC (zero_extend:SI
3927 (subreg:HI
3928 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3929 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3930 (const_int 0)))
3931 (clobber (match_scratch:SI 3 "=r,r"))]
3932 "!BYTES_BIG_ENDIAN"
3933 "@
3934 rlw%I2nm. %3,%1,%h2,0xffff
3935 #"
3936 [(set_attr "type" "shift")
3937 (set_attr "maybe_var_shift" "yes")
3938 (set_attr "dot" "yes")
3939 (set_attr "length" "4,8")])
3941 (define_insn "*rotlsi3_internal11be"
3942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3943 (compare:CC (zero_extend:SI
3944 (subreg:HI
3945 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3946 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3947 (const_int 0)))
3948 (clobber (match_scratch:SI 3 "=r,r"))]
3949 "BYTES_BIG_ENDIAN"
3950 "@
3951 rlw%I2nm. %3,%1,%h2,0xffff
3952 #"
3953 [(set_attr "type" "shift")
3954 (set_attr "maybe_var_shift" "yes")
3955 (set_attr "dot" "yes")
3956 (set_attr "length" "4,8")])
3958 (define_split
3959 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3960 (compare:CC (zero_extend:SI
3961 (subreg:HI
3962 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3964 (const_int 0)))
3965 (clobber (match_scratch:SI 3 ""))]
3966 "!BYTES_BIG_ENDIAN && reload_completed"
3967 [(set (match_dup 3)
3968 (zero_extend:SI (subreg:HI
3969 (rotate:SI (match_dup 1)
3970 (match_dup 2)) 0)))
3971 (set (match_dup 0)
3972 (compare:CC (match_dup 3)
3973 (const_int 0)))]
3974 "")
3976 (define_split
3977 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3978 (compare:CC (zero_extend:SI
3979 (subreg:HI
3980 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3981 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
3982 (const_int 0)))
3983 (clobber (match_scratch:SI 3 ""))]
3984 "BYTES_BIG_ENDIAN && reload_completed"
3985 [(set (match_dup 3)
3986 (zero_extend:SI (subreg:HI
3987 (rotate:SI (match_dup 1)
3988 (match_dup 2)) 2)))
3989 (set (match_dup 0)
3990 (compare:CC (match_dup 3)
3991 (const_int 0)))]
3992 "")
3994 (define_insn "*rotlsi3_internal12le"
3995 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3996 (compare:CC (zero_extend:SI
3997 (subreg:HI
3998 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3999 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4000 (const_int 0)))
4001 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4002 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4003 "!BYTES_BIG_ENDIAN"
4004 "@
4005 rlw%I2nm. %0,%1,%h2,0xffff
4006 #"
4007 [(set_attr "type" "shift")
4008 (set_attr "maybe_var_shift" "yes")
4009 (set_attr "dot" "yes")
4010 (set_attr "length" "4,8")])
4012 (define_insn "*rotlsi3_internal12be"
4013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4014 (compare:CC (zero_extend:SI
4015 (subreg:HI
4016 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4017 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4018 (const_int 0)))
4019 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4020 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4021 "BYTES_BIG_ENDIAN"
4022 "@
4023 rlw%I2nm. %0,%1,%h2,0xffff
4024 #"
4025 [(set_attr "type" "shift")
4026 (set_attr "maybe_var_shift" "yes")
4027 (set_attr "dot" "yes")
4028 (set_attr "length" "4,8")])
4030 (define_split
4031 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4032 (compare:CC (zero_extend:SI
4033 (subreg:HI
4034 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4035 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4036 (const_int 0)))
4037 (set (match_operand:SI 0 "gpc_reg_operand" "")
4038 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4039 "!BYTES_BIG_ENDIAN && reload_completed"
4040 [(set (match_dup 0)
4041 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4042 (set (match_dup 3)
4043 (compare:CC (match_dup 0)
4044 (const_int 0)))]
4045 "")
4047 (define_split
4048 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4049 (compare:CC (zero_extend:SI
4050 (subreg:HI
4051 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4052 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4053 (const_int 0)))
4054 (set (match_operand:SI 0 "gpc_reg_operand" "")
4055 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4056 "BYTES_BIG_ENDIAN && reload_completed"
4057 [(set (match_dup 0)
4058 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4059 (set (match_dup 3)
4060 (compare:CC (match_dup 0)
4061 (const_int 0)))]
4062 "")
4065 (define_insn "ashl<mode>3"
4066 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4067 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4069 ""
4070 "sl<wd>%I2 %0,%1,%<hH>2"
4071 [(set_attr "type" "shift")
4072 (set_attr "maybe_var_shift" "yes")])
4074 (define_insn "*ashlsi3_64"
4075 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4076 (zero_extend:DI
4077 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4078 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4079 "TARGET_POWERPC64"
4080 "slw%I2 %0,%1,%h2"
4081 [(set_attr "type" "shift")
4082 (set_attr "maybe_var_shift" "yes")])
4084 (define_insn_and_split "*ashl<mode>3_dot"
4085 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4086 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4087 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4088 (const_int 0)))
4089 (clobber (match_scratch:GPR 0 "=r,r"))]
4090 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4091 "@
4092 sl<wd>%I2. %0,%1,%<hH>2
4093 #"
4094 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4095 [(set (match_dup 0)
4096 (ashift:GPR (match_dup 1)
4097 (match_dup 2)))
4098 (set (match_dup 3)
4099 (compare:CC (match_dup 0)
4100 (const_int 0)))]
4101 ""
4102 [(set_attr "type" "shift")
4103 (set_attr "maybe_var_shift" "yes")
4104 (set_attr "dot" "yes")
4105 (set_attr "length" "4,8")])
4107 (define_insn_and_split "*ashl<mode>3_dot2"
4108 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4109 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4110 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4111 (const_int 0)))
4112 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4113 (ashift:GPR (match_dup 1)
4114 (match_dup 2)))]
4115 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4116 "@
4117 sl<wd>%I2. %0,%1,%<hH>2
4118 #"
4119 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4120 [(set (match_dup 0)
4121 (ashift:GPR (match_dup 1)
4122 (match_dup 2)))
4123 (set (match_dup 3)
4124 (compare:CC (match_dup 0)
4125 (const_int 0)))]
4126 ""
4127 [(set_attr "type" "shift")
4128 (set_attr "maybe_var_shift" "yes")
4129 (set_attr "dot" "yes")
4130 (set_attr "length" "4,8")])
4133 (define_insn "rlwinm"
4134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4135 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4136 (match_operand:SI 2 "const_int_operand" "i"))
4137 (match_operand:SI 3 "mask_operand" "n")))]
4138 "includes_lshift_p (operands[2], operands[3])"
4139 "rlwinm %0,%1,%h2,%m3,%M3"
4140 [(set_attr "type" "shift")])
4142 (define_insn ""
4143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4144 (compare:CC
4145 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4146 (match_operand:SI 2 "const_int_operand" "i,i"))
4147 (match_operand:SI 3 "mask_operand" "n,n"))
4148 (const_int 0)))
4149 (clobber (match_scratch:SI 4 "=r,r"))]
4150 "includes_lshift_p (operands[2], operands[3])"
4151 "@
4152 rlwinm. %4,%1,%h2,%m3,%M3
4153 #"
4154 [(set_attr "type" "shift")
4155 (set_attr "dot" "yes")
4156 (set_attr "length" "4,8")])
4158 (define_split
4159 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4160 (compare:CC
4161 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4162 (match_operand:SI 2 "const_int_operand" ""))
4163 (match_operand:SI 3 "mask_operand" ""))
4164 (const_int 0)))
4165 (clobber (match_scratch:SI 4 ""))]
4166 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4167 [(set (match_dup 4)
4168 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4169 (match_dup 3)))
4170 (set (match_dup 0)
4171 (compare:CC (match_dup 4)
4172 (const_int 0)))]
4173 "")
4175 (define_insn ""
4176 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4177 (compare:CC
4178 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4179 (match_operand:SI 2 "const_int_operand" "i,i"))
4180 (match_operand:SI 3 "mask_operand" "n,n"))
4181 (const_int 0)))
4182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4183 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4184 "includes_lshift_p (operands[2], operands[3])"
4185 "@
4186 rlwinm. %0,%1,%h2,%m3,%M3
4187 #"
4188 [(set_attr "type" "shift")
4189 (set_attr "dot" "yes")
4190 (set_attr "length" "4,8")])
4192 (define_split
4193 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4194 (compare:CC
4195 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4196 (match_operand:SI 2 "const_int_operand" ""))
4197 (match_operand:SI 3 "mask_operand" ""))
4198 (const_int 0)))
4199 (set (match_operand:SI 0 "gpc_reg_operand" "")
4200 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4201 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4202 [(set (match_dup 0)
4203 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4204 (set (match_dup 4)
4205 (compare:CC (match_dup 0)
4206 (const_int 0)))]
4207 "")
4210 (define_insn "lshr<mode>3"
4211 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4212 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4213 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4214 ""
4215 "sr<wd>%I2 %0,%1,%<hH>2"
4216 [(set_attr "type" "shift")
4217 (set_attr "maybe_var_shift" "yes")])
4219 (define_insn "*lshrsi3_64"
4220 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4221 (zero_extend:DI
4222 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4223 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4224 "TARGET_POWERPC64"
4225 "srw%I2 %0,%1,%h2"
4226 [(set_attr "type" "shift")
4227 (set_attr "maybe_var_shift" "yes")])
4229 (define_insn_and_split "*lshr<mode>3_dot"
4230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4231 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4232 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4233 (const_int 0)))
4234 (clobber (match_scratch:GPR 0 "=r,r"))]
4235 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4236 "@
4237 sr<wd>%I2. %0,%1,%<hH>2
4238 #"
4239 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4240 [(set (match_dup 0)
4241 (lshiftrt:GPR (match_dup 1)
4242 (match_dup 2)))
4243 (set (match_dup 3)
4244 (compare:CC (match_dup 0)
4245 (const_int 0)))]
4246 ""
4247 [(set_attr "type" "shift")
4248 (set_attr "maybe_var_shift" "yes")
4249 (set_attr "dot" "yes")
4250 (set_attr "length" "4,8")])
4252 (define_insn_and_split "*lshr<mode>3_dot2"
4253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4254 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4256 (const_int 0)))
4257 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4258 (lshiftrt:GPR (match_dup 1)
4259 (match_dup 2)))]
4260 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4261 "@
4262 sr<wd>%I2. %0,%1,%<hH>2
4263 #"
4264 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4265 [(set (match_dup 0)
4266 (lshiftrt:GPR (match_dup 1)
4267 (match_dup 2)))
4268 (set (match_dup 3)
4269 (compare:CC (match_dup 0)
4270 (const_int 0)))]
4271 ""
4272 [(set_attr "type" "shift")
4273 (set_attr "maybe_var_shift" "yes")
4274 (set_attr "dot" "yes")
4275 (set_attr "length" "4,8")])
4278 (define_insn ""
4279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4280 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4281 (match_operand:SI 2 "const_int_operand" "i"))
4282 (match_operand:SI 3 "mask_operand" "n")))]
4283 "includes_rshift_p (operands[2], operands[3])"
4284 "rlwinm %0,%1,%s2,%m3,%M3"
4285 [(set_attr "type" "shift")])
4287 (define_insn ""
4288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4289 (compare:CC
4290 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4291 (match_operand:SI 2 "const_int_operand" "i,i"))
4292 (match_operand:SI 3 "mask_operand" "n,n"))
4293 (const_int 0)))
4294 (clobber (match_scratch:SI 4 "=r,r"))]
4295 "includes_rshift_p (operands[2], operands[3])"
4296 "@
4297 rlwinm. %4,%1,%s2,%m3,%M3
4298 #"
4299 [(set_attr "type" "shift")
4300 (set_attr "dot" "yes")
4301 (set_attr "length" "4,8")])
4303 (define_split
4304 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4305 (compare:CC
4306 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4307 (match_operand:SI 2 "const_int_operand" ""))
4308 (match_operand:SI 3 "mask_operand" ""))
4309 (const_int 0)))
4310 (clobber (match_scratch:SI 4 ""))]
4311 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4312 [(set (match_dup 4)
4313 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4314 (match_dup 3)))
4315 (set (match_dup 0)
4316 (compare:CC (match_dup 4)
4317 (const_int 0)))]
4318 "")
4320 (define_insn ""
4321 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4322 (compare:CC
4323 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4324 (match_operand:SI 2 "const_int_operand" "i,i"))
4325 (match_operand:SI 3 "mask_operand" "n,n"))
4326 (const_int 0)))
4327 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4328 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4329 "includes_rshift_p (operands[2], operands[3])"
4330 "@
4331 rlwinm. %0,%1,%s2,%m3,%M3
4332 #"
4333 [(set_attr "type" "shift")
4334 (set_attr "dot" "yes")
4335 (set_attr "length" "4,8")])
4337 (define_split
4338 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4339 (compare:CC
4340 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4341 (match_operand:SI 2 "const_int_operand" ""))
4342 (match_operand:SI 3 "mask_operand" ""))
4343 (const_int 0)))
4344 (set (match_operand:SI 0 "gpc_reg_operand" "")
4345 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4346 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4347 [(set (match_dup 0)
4348 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4349 (set (match_dup 4)
4350 (compare:CC (match_dup 0)
4351 (const_int 0)))]
4352 "")
4354 (define_insn "*lshiftrt_internal1le"
4355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4356 (zero_extend:SI
4357 (subreg:QI
4358 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4359 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4360 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4361 "rlwinm %0,%1,%s2,0xff"
4362 [(set_attr "type" "shift")])
4364 (define_insn "*lshiftrt_internal1be"
4365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4366 (zero_extend:SI
4367 (subreg:QI
4368 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4369 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4370 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4371 "rlwinm %0,%1,%s2,0xff"
4372 [(set_attr "type" "shift")])
4374 (define_insn "*lshiftrt_internal2le"
4375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4376 (compare:CC
4377 (zero_extend:SI
4378 (subreg:QI
4379 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4380 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4381 (const_int 0)))
4382 (clobber (match_scratch:SI 3 "=r,r"))]
4383 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4384 "@
4385 rlwinm. %3,%1,%s2,0xff
4386 #"
4387 [(set_attr "type" "shift")
4388 (set_attr "dot" "yes")
4389 (set_attr "length" "4,8")])
4391 (define_insn "*lshiftrt_internal2be"
4392 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4393 (compare:CC
4394 (zero_extend:SI
4395 (subreg:QI
4396 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4397 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4398 (const_int 0)))
4399 (clobber (match_scratch:SI 3 "=r,r"))]
4400 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4401 "@
4402 rlwinm. %3,%1,%s2,0xff
4403 #"
4404 [(set_attr "type" "shift")
4405 (set_attr "dot" "yes")
4406 (set_attr "length" "4,8")])
4408 (define_split
4409 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4410 (compare:CC
4411 (zero_extend:SI
4412 (subreg:QI
4413 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4414 (match_operand:SI 2 "const_int_operand" "")) 0))
4415 (const_int 0)))
4416 (clobber (match_scratch:SI 3 ""))]
4417 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4418 [(set (match_dup 3)
4419 (zero_extend:SI (subreg:QI
4420 (lshiftrt:SI (match_dup 1)
4421 (match_dup 2)) 0)))
4422 (set (match_dup 0)
4423 (compare:CC (match_dup 3)
4424 (const_int 0)))]
4425 "")
4427 (define_split
4428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4429 (compare:CC
4430 (zero_extend:SI
4431 (subreg:QI
4432 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4433 (match_operand:SI 2 "const_int_operand" "")) 3))
4434 (const_int 0)))
4435 (clobber (match_scratch:SI 3 ""))]
4436 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4437 [(set (match_dup 3)
4438 (zero_extend:SI (subreg:QI
4439 (lshiftrt:SI (match_dup 1)
4440 (match_dup 2)) 3)))
4441 (set (match_dup 0)
4442 (compare:CC (match_dup 3)
4443 (const_int 0)))]
4444 "")
4446 (define_insn "*lshiftrt_internal3le"
4447 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4448 (compare:CC
4449 (zero_extend:SI
4450 (subreg:QI
4451 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4452 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4453 (const_int 0)))
4454 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4455 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4456 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4457 "@
4458 rlwinm. %0,%1,%s2,0xff
4459 #"
4460 [(set_attr "type" "shift")
4461 (set_attr "dot" "yes")
4462 (set_attr "length" "4,8")])
4464 (define_insn "*lshiftrt_internal3be"
4465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4466 (compare:CC
4467 (zero_extend:SI
4468 (subreg:QI
4469 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4470 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4471 (const_int 0)))
4472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4473 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4474 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4475 "@
4476 rlwinm. %0,%1,%s2,0xff
4477 #"
4478 [(set_attr "type" "shift")
4479 (set_attr "dot" "yes")
4480 (set_attr "length" "4,8")])
4482 (define_split
4483 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4484 (compare:CC
4485 (zero_extend:SI
4486 (subreg:QI
4487 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4488 (match_operand:SI 2 "const_int_operand" "")) 0))
4489 (const_int 0)))
4490 (set (match_operand:SI 0 "gpc_reg_operand" "")
4491 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4492 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4493 [(set (match_dup 0)
4494 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4495 (set (match_dup 3)
4496 (compare:CC (match_dup 0)
4497 (const_int 0)))]
4498 "")
4500 (define_split
4501 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4502 (compare:CC
4503 (zero_extend:SI
4504 (subreg:QI
4505 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4506 (match_operand:SI 2 "const_int_operand" "")) 3))
4507 (const_int 0)))
4508 (set (match_operand:SI 0 "gpc_reg_operand" "")
4509 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4510 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4511 [(set (match_dup 0)
4512 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4513 (set (match_dup 3)
4514 (compare:CC (match_dup 0)
4515 (const_int 0)))]
4516 "")
4518 (define_insn "*lshiftrt_internal4le"
4519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4520 (zero_extend:SI
4521 (subreg:HI
4522 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4523 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4524 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4525 "rlwinm %0,%1,%s2,0xffff"
4526 [(set_attr "type" "shift")])
4528 (define_insn "*lshiftrt_internal4be"
4529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4530 (zero_extend:SI
4531 (subreg:HI
4532 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4533 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4534 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4535 "rlwinm %0,%1,%s2,0xffff"
4536 [(set_attr "type" "shift")])
4538 (define_insn "*lshiftrt_internal5le"
4539 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4540 (compare:CC
4541 (zero_extend:SI
4542 (subreg:HI
4543 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4544 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4545 (const_int 0)))
4546 (clobber (match_scratch:SI 3 "=r,r"))]
4547 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4548 "@
4549 rlwinm. %3,%1,%s2,0xffff
4550 #"
4551 [(set_attr "type" "shift")
4552 (set_attr "dot" "yes")
4553 (set_attr "length" "4,8")])
4555 (define_insn "*lshiftrt_internal5be"
4556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4557 (compare:CC
4558 (zero_extend:SI
4559 (subreg:HI
4560 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4561 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4562 (const_int 0)))
4563 (clobber (match_scratch:SI 3 "=r,r"))]
4564 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4565 "@
4566 rlwinm. %3,%1,%s2,0xffff
4567 #"
4568 [(set_attr "type" "shift")
4569 (set_attr "dot" "yes")
4570 (set_attr "length" "4,8")])
4572 (define_split
4573 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4574 (compare:CC
4575 (zero_extend:SI
4576 (subreg:HI
4577 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4578 (match_operand:SI 2 "const_int_operand" "")) 0))
4579 (const_int 0)))
4580 (clobber (match_scratch:SI 3 ""))]
4581 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4582 [(set (match_dup 3)
4583 (zero_extend:SI (subreg:HI
4584 (lshiftrt:SI (match_dup 1)
4585 (match_dup 2)) 0)))
4586 (set (match_dup 0)
4587 (compare:CC (match_dup 3)
4588 (const_int 0)))]
4589 "")
4591 (define_split
4592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4593 (compare:CC
4594 (zero_extend:SI
4595 (subreg:HI
4596 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4597 (match_operand:SI 2 "const_int_operand" "")) 2))
4598 (const_int 0)))
4599 (clobber (match_scratch:SI 3 ""))]
4600 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4601 [(set (match_dup 3)
4602 (zero_extend:SI (subreg:HI
4603 (lshiftrt:SI (match_dup 1)
4604 (match_dup 2)) 2)))
4605 (set (match_dup 0)
4606 (compare:CC (match_dup 3)
4607 (const_int 0)))]
4608 "")
4610 (define_insn "*lshiftrt_internal5le"
4611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4612 (compare:CC
4613 (zero_extend:SI
4614 (subreg:HI
4615 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4616 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4617 (const_int 0)))
4618 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4619 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4620 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4621 "@
4622 rlwinm. %0,%1,%s2,0xffff
4623 #"
4624 [(set_attr "type" "shift")
4625 (set_attr "dot" "yes")
4626 (set_attr "length" "4,8")])
4628 (define_insn "*lshiftrt_internal5be"
4629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4630 (compare:CC
4631 (zero_extend:SI
4632 (subreg:HI
4633 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4634 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4635 (const_int 0)))
4636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4637 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4638 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4639 "@
4640 rlwinm. %0,%1,%s2,0xffff
4641 #"
4642 [(set_attr "type" "shift")
4643 (set_attr "dot" "yes")
4644 (set_attr "length" "4,8")])
4646 (define_split
4647 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4648 (compare:CC
4649 (zero_extend:SI
4650 (subreg:HI
4651 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4652 (match_operand:SI 2 "const_int_operand" "")) 0))
4653 (const_int 0)))
4654 (set (match_operand:SI 0 "gpc_reg_operand" "")
4655 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4656 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4657 [(set (match_dup 0)
4658 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4659 (set (match_dup 3)
4660 (compare:CC (match_dup 0)
4661 (const_int 0)))]
4662 "")
4664 (define_split
4665 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4666 (compare:CC
4667 (zero_extend:SI
4668 (subreg:HI
4669 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4670 (match_operand:SI 2 "const_int_operand" "")) 2))
4671 (const_int 0)))
4672 (set (match_operand:SI 0 "gpc_reg_operand" "")
4673 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4674 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4675 [(set (match_dup 0)
4676 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4677 (set (match_dup 3)
4678 (compare:CC (match_dup 0)
4679 (const_int 0)))]
4680 "")
4683 (define_expand "ashr<mode>3"
4684 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4685 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4686 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4687 ""
4688 {
4689 /* The generic code does not generate optimal code for the low word
4690 (it should be a rlwimi and a rot). Until we have target code to
4691 solve this generically, keep this expander. */
4693 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4694 {
4695 if (CONST_INT_P (operands[2]))
4696 {
4697 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4698 DONE;
4699 }
4700 else
4701 FAIL;
4702 }
4703 })
4705 (define_insn "*ashr<mode>3"
4706 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4707 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4708 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4709 ""
4710 "sra<wd>%I2 %0,%1,%<hH>2"
4711 [(set_attr "type" "shift")
4712 (set_attr "maybe_var_shift" "yes")])
4714 (define_insn "*ashrsi3_64"
4715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4716 (sign_extend:DI
4717 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4718 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4719 "TARGET_POWERPC64"
4720 "sraw%I2 %0,%1,%h2"
4721 [(set_attr "type" "shift")
4722 (set_attr "maybe_var_shift" "yes")])
4724 (define_insn_and_split "*ashr<mode>3_dot"
4725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4726 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4727 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4728 (const_int 0)))
4729 (clobber (match_scratch:GPR 0 "=r,r"))]
4730 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4731 "@
4732 sra<wd>%I2. %0,%1,%<hH>2
4733 #"
4734 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4735 [(set (match_dup 0)
4736 (ashiftrt:GPR (match_dup 1)
4737 (match_dup 2)))
4738 (set (match_dup 3)
4739 (compare:CC (match_dup 0)
4740 (const_int 0)))]
4741 ""
4742 [(set_attr "type" "shift")
4743 (set_attr "maybe_var_shift" "yes")
4744 (set_attr "dot" "yes")
4745 (set_attr "length" "4,8")])
4747 (define_insn_and_split "*ashr<mode>3_dot2"
4748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4749 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4750 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4751 (const_int 0)))
4752 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4753 (ashiftrt:GPR (match_dup 1)
4754 (match_dup 2)))]
4755 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4756 "@
4757 sra<wd>%I2. %0,%1,%<hH>2
4758 #"
4759 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4760 [(set (match_dup 0)
4761 (ashiftrt:GPR (match_dup 1)
4762 (match_dup 2)))
4763 (set (match_dup 3)
4764 (compare:CC (match_dup 0)
4765 (const_int 0)))]
4766 ""
4767 [(set_attr "type" "shift")
4768 (set_attr "maybe_var_shift" "yes")
4769 (set_attr "dot" "yes")
4770 (set_attr "length" "4,8")])
4771 \f
4772 ;; Builtins to replace a division to generate FRE reciprocal estimate
4773 ;; instructions and the necessary fixup instructions
4774 (define_expand "recip<mode>3"
4775 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4776 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4777 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4778 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4779 {
4780 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4781 DONE;
4782 })
4784 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4785 ;; hardware division. This is only done before register allocation and with
4786 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4787 (define_split
4788 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4789 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4790 (match_operand 2 "gpc_reg_operand" "")))]
4791 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4792 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4793 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4794 [(const_int 0)]
4795 {
4796 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4797 DONE;
4798 })
4800 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4801 ;; appropriate fixup.
4802 (define_expand "rsqrt<mode>2"
4803 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4804 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4805 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4806 {
4807 rs6000_emit_swrsqrt (operands[0], operands[1]);
4808 DONE;
4809 })
4810 \f
4811 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4812 ;; modes here, and also add in conditional vsx/power8-vector support to access
4813 ;; values in the traditional Altivec registers if the appropriate
4814 ;; -mupper-regs-{df,sf} option is enabled.
4816 (define_expand "abs<mode>2"
4817 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4818 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4819 "TARGET_<MODE>_INSN"
4820 "")
4822 (define_insn "*abs<mode>2_fpr"
4823 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4824 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4825 "TARGET_<MODE>_FPR"
4826 "@
4827 fabs %0,%1
4828 xsabsdp %x0,%x1"
4829 [(set_attr "type" "fp")
4830 (set_attr "fp_type" "fp_addsub_<Fs>")])
4832 (define_insn "*nabs<mode>2_fpr"
4833 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4834 (neg:SFDF
4835 (abs:SFDF
4836 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4837 "TARGET_<MODE>_FPR"
4838 "@
4839 fnabs %0,%1
4840 xsnabsdp %x0,%x1"
4841 [(set_attr "type" "fp")
4842 (set_attr "fp_type" "fp_addsub_<Fs>")])
4844 (define_expand "neg<mode>2"
4845 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4846 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4847 "TARGET_<MODE>_INSN"
4848 "")
4850 (define_insn "*neg<mode>2_fpr"
4851 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4852 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4853 "TARGET_<MODE>_FPR"
4854 "@
4855 fneg %0,%1
4856 xsnegdp %x0,%x1"
4857 [(set_attr "type" "fp")
4858 (set_attr "fp_type" "fp_addsub_<Fs>")])
4860 (define_expand "add<mode>3"
4861 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4862 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4863 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4864 "TARGET_<MODE>_INSN"
4865 "")
4867 (define_insn "*add<mode>3_fpr"
4868 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4869 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4870 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4871 "TARGET_<MODE>_FPR"
4872 "@
4873 fadd<Ftrad> %0,%1,%2
4874 xsadd<Fvsx> %x0,%x1,%x2"
4875 [(set_attr "type" "fp")
4876 (set_attr "fp_type" "fp_addsub_<Fs>")])
4878 (define_expand "sub<mode>3"
4879 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4880 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4881 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4882 "TARGET_<MODE>_INSN"
4883 "")
4885 (define_insn "*sub<mode>3_fpr"
4886 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4887 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4888 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4889 "TARGET_<MODE>_FPR"
4890 "@
4891 fsub<Ftrad> %0,%1,%2
4892 xssub<Fvsx> %x0,%x1,%x2"
4893 [(set_attr "type" "fp")
4894 (set_attr "fp_type" "fp_addsub_<Fs>")])
4896 (define_expand "mul<mode>3"
4897 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4898 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4899 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4900 "TARGET_<MODE>_INSN"
4901 "")
4903 (define_insn "*mul<mode>3_fpr"
4904 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4905 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4906 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4907 "TARGET_<MODE>_FPR"
4908 "@
4909 fmul<Ftrad> %0,%1,%2
4910 xsmul<Fvsx> %x0,%x1,%x2"
4911 [(set_attr "type" "dmul")
4912 (set_attr "fp_type" "fp_mul_<Fs>")])
4914 (define_expand "div<mode>3"
4915 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4916 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4917 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4918 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4919 "")
4921 (define_insn "*div<mode>3_fpr"
4922 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4923 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4924 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4925 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4926 "@
4927 fdiv<Ftrad> %0,%1,%2
4928 xsdiv<Fvsx> %x0,%x1,%x2"
4929 [(set_attr "type" "<Fs>div")
4930 (set_attr "fp_type" "fp_div_<Fs>")])
4932 (define_insn "sqrt<mode>2"
4933 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4934 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4935 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4936 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4937 "@
4938 fsqrt<Ftrad> %0,%1
4939 xssqrt<Fvsx> %x0,%x1"
4940 [(set_attr "type" "<Fs>sqrt")
4941 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4943 ;; Floating point reciprocal approximation
4944 (define_insn "fre<Fs>"
4945 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4946 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4947 UNSPEC_FRES))]
4948 "TARGET_<FFRE>"
4949 "@
4950 fre<Ftrad> %0,%1
4951 xsre<Fvsx> %x0,%x1"
4952 [(set_attr "type" "fp")])
4954 (define_insn "*rsqrt<mode>2"
4955 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4956 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4957 UNSPEC_RSQRT))]
4958 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4959 "@
4960 frsqrte<Ftrad> %0,%1
4961 xsrsqrte<Fvsx> %x0,%x1"
4962 [(set_attr "type" "fp")])
4964 ;; Floating point comparisons
4965 (define_insn "*cmp<mode>_fpr"
4966 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4967 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4968 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4969 "TARGET_<MODE>_FPR"
4970 "@
4971 fcmpu %0,%1,%2
4972 xscmpudp %0,%x1,%x2"
4973 [(set_attr "type" "fpcompare")])
4975 ;; Floating point conversions
4976 (define_expand "extendsfdf2"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4978 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4979 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4980 "")
4982 (define_insn_and_split "*extendsfdf2_fpr"
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
4984 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
4985 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4986 "@
4987 #
4988 fmr %0,%1
4989 lfs%U1%X1 %0,%1
4990 #
4991 xxlor %x0,%x1,%x1
4992 lxsspx %x0,%y1"
4993 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4994 [(const_int 0)]
4995 {
4996 emit_note (NOTE_INSN_DELETED);
4997 DONE;
4998 }
4999 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5001 (define_expand "truncdfsf2"
5002 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5003 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5004 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5005 "")
5007 (define_insn "*truncdfsf2_fpr"
5008 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5009 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5010 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5011 "frsp %0,%1"
5012 [(set_attr "type" "fp")])
5014 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5015 ;; builtins.c and optabs.c that are not correct for IBM long double
5016 ;; when little-endian.
5017 (define_expand "signbittf2"
5018 [(set (match_dup 2)
5019 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5020 (set (match_dup 3)
5021 (subreg:DI (match_dup 2) 0))
5022 (set (match_dup 4)
5023 (match_dup 5))
5024 (set (match_operand:SI 0 "gpc_reg_operand" "")
5025 (match_dup 6))]
5026 "!TARGET_IEEEQUAD
5027 && TARGET_HARD_FLOAT
5028 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5029 && TARGET_LONG_DOUBLE_128"
5030 {
5031 operands[2] = gen_reg_rtx (DFmode);
5032 operands[3] = gen_reg_rtx (DImode);
5033 if (TARGET_POWERPC64)
5034 {
5035 operands[4] = gen_reg_rtx (DImode);
5036 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5037 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5038 WORDS_BIG_ENDIAN ? 4 : 0);
5039 }
5040 else
5041 {
5042 operands[4] = gen_reg_rtx (SImode);
5043 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5044 WORDS_BIG_ENDIAN ? 0 : 4);
5045 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5046 }
5047 })
5049 (define_expand "copysign<mode>3"
5050 [(set (match_dup 3)
5051 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5052 (set (match_dup 4)
5053 (neg:SFDF (abs:SFDF (match_dup 1))))
5054 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5055 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5056 (match_dup 5))
5057 (match_dup 3)
5058 (match_dup 4)))]
5059 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5060 && ((TARGET_PPC_GFXOPT
5061 && !HONOR_NANS (<MODE>mode)
5062 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5063 || TARGET_CMPB
5064 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5065 {
5066 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5067 {
5068 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5069 operands[2]));
5070 DONE;
5071 }
5073 operands[3] = gen_reg_rtx (<MODE>mode);
5074 operands[4] = gen_reg_rtx (<MODE>mode);
5075 operands[5] = CONST0_RTX (<MODE>mode);
5076 })
5078 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5079 ;; compiler from optimizing -0.0
5080 (define_insn "copysign<mode>3_fcpsgn"
5081 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5082 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5083 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5084 UNSPEC_COPYSIGN))]
5085 "TARGET_<MODE>_FPR && TARGET_CMPB"
5086 "@
5087 fcpsgn %0,%2,%1
5088 xscpsgn<Fvsx> %x0,%x2,%x1"
5089 [(set_attr "type" "fp")])
5091 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5092 ;; fsel instruction and some auxiliary computations. Then we just have a
5093 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5094 ;; combine.
5095 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5096 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5097 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5098 ;; define_splits to make them if made by combine. On VSX machines we have the
5099 ;; min/max instructions.
5100 ;;
5101 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5102 ;; to allow either DF/SF to use only traditional registers.
5104 (define_expand "smax<mode>3"
5105 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5106 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5107 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5108 (match_dup 1)
5109 (match_dup 2)))]
5110 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5111 {
5112 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5113 DONE;
5114 })
5116 (define_insn "*smax<mode>3_vsx"
5117 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5118 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5119 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5120 "TARGET_<MODE>_FPR && TARGET_VSX"
5121 "xsmaxdp %x0,%x1,%x2"
5122 [(set_attr "type" "fp")])
5124 (define_expand "smin<mode>3"
5125 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5126 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5127 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5128 (match_dup 2)
5129 (match_dup 1)))]
5130 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5131 {
5132 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5133 DONE;
5134 })
5136 (define_insn "*smin<mode>3_vsx"
5137 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5138 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5139 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5140 "TARGET_<MODE>_FPR && TARGET_VSX"
5141 "xsmindp %x0,%x1,%x2"
5142 [(set_attr "type" "fp")])
5144 (define_split
5145 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5146 (match_operator:SFDF 3 "min_max_operator"
5147 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5148 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5149 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5150 && !TARGET_VSX"
5151 [(const_int 0)]
5152 {
5153 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5154 operands[2]);
5155 DONE;
5156 })
5158 (define_split
5159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5160 (match_operator:SF 3 "min_max_operator"
5161 [(match_operand:SF 1 "gpc_reg_operand" "")
5162 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5163 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5164 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5165 [(const_int 0)]
5166 "
5167 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5168 operands[1], operands[2]);
5169 DONE;
5170 }")
5172 (define_expand "mov<mode>cc"
5173 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5174 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5175 (match_operand:GPR 2 "gpc_reg_operand" "")
5176 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5177 "TARGET_ISEL<sel>"
5178 "
5179 {
5180 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5181 DONE;
5182 else
5183 FAIL;
5184 }")
5186 ;; We use the BASE_REGS for the isel input operands because, if rA is
5187 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5188 ;; because we may switch the operands and rB may end up being rA.
5189 ;;
5190 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5191 ;; leave out the mode in operand 4 and use one pattern, but reload can
5192 ;; change the mode underneath our feet and then gets confused trying
5193 ;; to reload the value.
5194 (define_insn "isel_signed_<mode>"
5195 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5196 (if_then_else:GPR
5197 (match_operator 1 "scc_comparison_operator"
5198 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5199 (const_int 0)])
5200 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5201 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5202 "TARGET_ISEL<sel>"
5203 "*
5204 { return output_isel (operands); }"
5205 [(set_attr "type" "isel")
5206 (set_attr "length" "4")])
5208 (define_insn "isel_unsigned_<mode>"
5209 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5210 (if_then_else:GPR
5211 (match_operator 1 "scc_comparison_operator"
5212 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5213 (const_int 0)])
5214 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5215 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5216 "TARGET_ISEL<sel>"
5217 "*
5218 { return output_isel (operands); }"
5219 [(set_attr "type" "isel")
5220 (set_attr "length" "4")])
5222 ;; These patterns can be useful for combine; they let combine know that
5223 ;; isel can handle reversed comparisons so long as the operands are
5224 ;; registers.
5226 (define_insn "*isel_reversed_signed_<mode>"
5227 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5228 (if_then_else:GPR
5229 (match_operator 1 "scc_rev_comparison_operator"
5230 [(match_operand:CC 4 "cc_reg_operand" "y")
5231 (const_int 0)])
5232 (match_operand:GPR 2 "gpc_reg_operand" "b")
5233 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5234 "TARGET_ISEL<sel>"
5235 "*
5236 { return output_isel (operands); }"
5237 [(set_attr "type" "isel")
5238 (set_attr "length" "4")])
5240 (define_insn "*isel_reversed_unsigned_<mode>"
5241 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5242 (if_then_else:GPR
5243 (match_operator 1 "scc_rev_comparison_operator"
5244 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5245 (const_int 0)])
5246 (match_operand:GPR 2 "gpc_reg_operand" "b")
5247 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5248 "TARGET_ISEL<sel>"
5249 "*
5250 { return output_isel (operands); }"
5251 [(set_attr "type" "isel")
5252 (set_attr "length" "4")])
5254 (define_expand "movsfcc"
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5256 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5257 (match_operand:SF 2 "gpc_reg_operand" "")
5258 (match_operand:SF 3 "gpc_reg_operand" "")))]
5259 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5260 "
5261 {
5262 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5263 DONE;
5264 else
5265 FAIL;
5266 }")
5268 (define_insn "*fselsfsf4"
5269 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5270 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5271 (match_operand:SF 4 "zero_fp_constant" "F"))
5272 (match_operand:SF 2 "gpc_reg_operand" "f")
5273 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5274 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5275 "fsel %0,%1,%2,%3"
5276 [(set_attr "type" "fp")])
5278 (define_insn "*fseldfsf4"
5279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5280 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5281 (match_operand:DF 4 "zero_fp_constant" "F"))
5282 (match_operand:SF 2 "gpc_reg_operand" "f")
5283 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5284 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5285 "fsel %0,%1,%2,%3"
5286 [(set_attr "type" "fp")])
5288 ;; The conditional move instructions allow us to perform max and min
5289 ;; operations even when
5291 (define_split
5292 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5293 (match_operator:DF 3 "min_max_operator"
5294 [(match_operand:DF 1 "gpc_reg_operand" "")
5295 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5296 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5297 && !flag_trapping_math"
5298 [(const_int 0)]
5299 "
5300 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5301 operands[1], operands[2]);
5302 DONE;
5303 }")
5305 (define_expand "movdfcc"
5306 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5307 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5308 (match_operand:DF 2 "gpc_reg_operand" "")
5309 (match_operand:DF 3 "gpc_reg_operand" "")))]
5310 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5311 "
5312 {
5313 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5314 DONE;
5315 else
5316 FAIL;
5317 }")
5319 (define_insn "*fseldfdf4"
5320 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5321 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5322 (match_operand:DF 4 "zero_fp_constant" "F"))
5323 (match_operand:DF 2 "gpc_reg_operand" "d")
5324 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5325 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5326 "fsel %0,%1,%2,%3"
5327 [(set_attr "type" "fp")])
5329 (define_insn "*fselsfdf4"
5330 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5331 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5332 (match_operand:SF 4 "zero_fp_constant" "F"))
5333 (match_operand:DF 2 "gpc_reg_operand" "d")
5334 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5335 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5336 "fsel %0,%1,%2,%3"
5337 [(set_attr "type" "fp")])
5338 \f
5339 ;; Conversions to and from floating-point.
5341 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5342 ; don't want to support putting SImode in FPR registers.
5343 (define_insn "lfiwax"
5344 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5345 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5346 UNSPEC_LFIWAX))]
5347 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5348 "@
5349 lfiwax %0,%y1
5350 lxsiwax %x0,%y1
5351 mtvsrwa %x0,%1"
5352 [(set_attr "type" "fpload,fpload,mffgpr")])
5354 ; This split must be run before register allocation because it allocates the
5355 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5356 ; it earlier to allow for the combiner to merge insns together where it might
5357 ; not be needed and also in case the insns are deleted as dead code.
5359 (define_insn_and_split "floatsi<mode>2_lfiwax"
5360 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5361 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5362 (clobber (match_scratch:DI 2 "=d"))]
5363 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5364 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5365 "#"
5366 ""
5367 [(pc)]
5368 "
5369 {
5370 rtx dest = operands[0];
5371 rtx src = operands[1];
5372 rtx tmp;
5374 if (!MEM_P (src) && TARGET_POWERPC64
5375 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5376 tmp = convert_to_mode (DImode, src, false);
5377 else
5378 {
5379 tmp = operands[2];
5380 if (GET_CODE (tmp) == SCRATCH)
5381 tmp = gen_reg_rtx (DImode);
5382 if (MEM_P (src))
5383 {
5384 src = rs6000_address_for_fpconvert (src);
5385 emit_insn (gen_lfiwax (tmp, src));
5386 }
5387 else
5388 {
5389 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5390 emit_move_insn (stack, src);
5391 emit_insn (gen_lfiwax (tmp, stack));
5392 }
5393 }
5394 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5395 DONE;
5396 }"
5397 [(set_attr "length" "12")
5398 (set_attr "type" "fpload")])
5400 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5401 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5402 (float:SFDF
5403 (sign_extend:DI
5404 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5405 (clobber (match_scratch:DI 2 "=0,d"))]
5406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5407 && <SI_CONVERT_FP>"
5408 "#"
5409 ""
5410 [(pc)]
5411 "
5412 {
5413 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5414 if (GET_CODE (operands[2]) == SCRATCH)
5415 operands[2] = gen_reg_rtx (DImode);
5416 emit_insn (gen_lfiwax (operands[2], operands[1]));
5417 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5418 DONE;
5419 }"
5420 [(set_attr "length" "8")
5421 (set_attr "type" "fpload")])
5423 (define_insn "lfiwzx"
5424 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5425 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5426 UNSPEC_LFIWZX))]
5427 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5428 "@
5429 lfiwzx %0,%y1
5430 lxsiwzx %x0,%y1
5431 mtvsrwz %x0,%1"
5432 [(set_attr "type" "fpload,fpload,mftgpr")])
5434 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5435 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5436 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5437 (clobber (match_scratch:DI 2 "=d"))]
5438 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5439 && <SI_CONVERT_FP>"
5440 "#"
5441 ""
5442 [(pc)]
5443 "
5444 {
5445 rtx dest = operands[0];
5446 rtx src = operands[1];
5447 rtx tmp;
5449 if (!MEM_P (src) && TARGET_POWERPC64
5450 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5451 tmp = convert_to_mode (DImode, src, true);
5452 else
5453 {
5454 tmp = operands[2];
5455 if (GET_CODE (tmp) == SCRATCH)
5456 tmp = gen_reg_rtx (DImode);
5457 if (MEM_P (src))
5458 {
5459 src = rs6000_address_for_fpconvert (src);
5460 emit_insn (gen_lfiwzx (tmp, src));
5461 }
5462 else
5463 {
5464 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5465 emit_move_insn (stack, src);
5466 emit_insn (gen_lfiwzx (tmp, stack));
5467 }
5468 }
5469 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5470 DONE;
5471 }"
5472 [(set_attr "length" "12")
5473 (set_attr "type" "fpload")])
5475 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5476 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5477 (unsigned_float:SFDF
5478 (zero_extend:DI
5479 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5480 (clobber (match_scratch:DI 2 "=0,d"))]
5481 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5482 && <SI_CONVERT_FP>"
5483 "#"
5484 ""
5485 [(pc)]
5486 "
5487 {
5488 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5489 if (GET_CODE (operands[2]) == SCRATCH)
5490 operands[2] = gen_reg_rtx (DImode);
5491 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5492 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5493 DONE;
5494 }"
5495 [(set_attr "length" "8")
5496 (set_attr "type" "fpload")])
5498 ; For each of these conversions, there is a define_expand, a define_insn
5499 ; with a '#' template, and a define_split (with C code). The idea is
5500 ; to allow constant folding with the template of the define_insn,
5501 ; then to have the insns split later (between sched1 and final).
5503 (define_expand "floatsidf2"
5504 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5505 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5506 (use (match_dup 2))
5507 (use (match_dup 3))
5508 (clobber (match_dup 4))
5509 (clobber (match_dup 5))
5510 (clobber (match_dup 6))])]
5511 "TARGET_HARD_FLOAT
5512 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5513 "
5514 {
5515 if (TARGET_E500_DOUBLE)
5516 {
5517 if (!REG_P (operands[1]))
5518 operands[1] = force_reg (SImode, operands[1]);
5519 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5520 DONE;
5521 }
5522 else if (TARGET_LFIWAX && TARGET_FCFID)
5523 {
5524 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5525 DONE;
5526 }
5527 else if (TARGET_FCFID)
5528 {
5529 rtx dreg = operands[1];
5530 if (!REG_P (dreg))
5531 dreg = force_reg (SImode, dreg);
5532 dreg = convert_to_mode (DImode, dreg, false);
5533 emit_insn (gen_floatdidf2 (operands[0], dreg));
5534 DONE;
5535 }
5537 if (!REG_P (operands[1]))
5538 operands[1] = force_reg (SImode, operands[1]);
5539 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5540 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5541 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5542 operands[5] = gen_reg_rtx (DFmode);
5543 operands[6] = gen_reg_rtx (SImode);
5544 }")
5546 (define_insn_and_split "*floatsidf2_internal"
5547 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5548 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5549 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5550 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5551 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5552 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5553 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5554 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5555 "#"
5556 ""
5557 [(pc)]
5558 "
5559 {
5560 rtx lowword, highword;
5561 gcc_assert (MEM_P (operands[4]));
5562 highword = adjust_address (operands[4], SImode, 0);
5563 lowword = adjust_address (operands[4], SImode, 4);
5564 if (! WORDS_BIG_ENDIAN)
5565 {
5566 rtx tmp;
5567 tmp = highword; highword = lowword; lowword = tmp;
5568 }
5570 emit_insn (gen_xorsi3 (operands[6], operands[1],
5571 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5572 emit_move_insn (lowword, operands[6]);
5573 emit_move_insn (highword, operands[2]);
5574 emit_move_insn (operands[5], operands[4]);
5575 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5576 DONE;
5577 }"
5578 [(set_attr "length" "24")
5579 (set_attr "type" "fp")])
5581 ;; If we don't have a direct conversion to single precision, don't enable this
5582 ;; conversion for 32-bit without fast math, because we don't have the insn to
5583 ;; generate the fixup swizzle to avoid double rounding problems.
5584 (define_expand "floatunssisf2"
5585 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5586 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5587 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5588 && (!TARGET_FPRS
5589 || (TARGET_FPRS
5590 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5591 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5592 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5593 "
5594 {
5595 if (!TARGET_FPRS)
5596 {
5597 if (!REG_P (operands[1]))
5598 operands[1] = force_reg (SImode, operands[1]);
5599 }
5600 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5601 {
5602 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5603 DONE;
5604 }
5605 else
5606 {
5607 rtx dreg = operands[1];
5608 if (!REG_P (dreg))
5609 dreg = force_reg (SImode, dreg);
5610 dreg = convert_to_mode (DImode, dreg, true);
5611 emit_insn (gen_floatdisf2 (operands[0], dreg));
5612 DONE;
5613 }
5614 }")
5616 (define_expand "floatunssidf2"
5617 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5618 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5619 (use (match_dup 2))
5620 (use (match_dup 3))
5621 (clobber (match_dup 4))
5622 (clobber (match_dup 5))])]
5623 "TARGET_HARD_FLOAT
5624 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5625 "
5626 {
5627 if (TARGET_E500_DOUBLE)
5628 {
5629 if (!REG_P (operands[1]))
5630 operands[1] = force_reg (SImode, operands[1]);
5631 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5632 DONE;
5633 }
5634 else if (TARGET_LFIWZX && TARGET_FCFID)
5635 {
5636 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5637 DONE;
5638 }
5639 else if (TARGET_FCFID)
5640 {
5641 rtx dreg = operands[1];
5642 if (!REG_P (dreg))
5643 dreg = force_reg (SImode, dreg);
5644 dreg = convert_to_mode (DImode, dreg, true);
5645 emit_insn (gen_floatdidf2 (operands[0], dreg));
5646 DONE;
5647 }
5649 if (!REG_P (operands[1]))
5650 operands[1] = force_reg (SImode, operands[1]);
5651 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5652 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5653 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5654 operands[5] = gen_reg_rtx (DFmode);
5655 }")
5657 (define_insn_and_split "*floatunssidf2_internal"
5658 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5659 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5660 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5661 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5662 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5663 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5664 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5665 && !(TARGET_FCFID && TARGET_POWERPC64)"
5666 "#"
5667 ""
5668 [(pc)]
5669 "
5670 {
5671 rtx lowword, highword;
5672 gcc_assert (MEM_P (operands[4]));
5673 highword = adjust_address (operands[4], SImode, 0);
5674 lowword = adjust_address (operands[4], SImode, 4);
5675 if (! WORDS_BIG_ENDIAN)
5676 {
5677 rtx tmp;
5678 tmp = highword; highword = lowword; lowword = tmp;
5679 }
5681 emit_move_insn (lowword, operands[1]);
5682 emit_move_insn (highword, operands[2]);
5683 emit_move_insn (operands[5], operands[4]);
5684 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5685 DONE;
5686 }"
5687 [(set_attr "length" "20")
5688 (set_attr "type" "fp")])
5690 (define_expand "fix_trunc<mode>si2"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5692 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5693 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5694 "
5695 {
5696 if (!<E500_CONVERT>)
5697 {
5698 rtx tmp, stack;
5700 if (TARGET_STFIWX)
5701 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5702 else
5703 {
5704 tmp = gen_reg_rtx (DImode);
5705 stack = rs6000_allocate_stack_temp (DImode, true, false);
5706 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5707 tmp, stack));
5708 }
5709 DONE;
5710 }
5711 }")
5713 ; Like the convert to float patterns, this insn must be split before
5714 ; register allocation so that it can allocate the memory slot if it
5715 ; needed
5716 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5717 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5718 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5719 (clobber (match_scratch:DI 2 "=d"))]
5720 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5721 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5722 && TARGET_STFIWX && can_create_pseudo_p ()"
5723 "#"
5724 ""
5725 [(pc)]
5726 {
5727 rtx dest = operands[0];
5728 rtx src = operands[1];
5729 rtx tmp = operands[2];
5731 if (GET_CODE (tmp) == SCRATCH)
5732 tmp = gen_reg_rtx (DImode);
5734 emit_insn (gen_fctiwz_<mode> (tmp, src));
5735 if (MEM_P (dest))
5736 {
5737 dest = rs6000_address_for_fpconvert (dest);
5738 emit_insn (gen_stfiwx (dest, tmp));
5739 DONE;
5740 }
5741 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5742 {
5743 dest = gen_lowpart (DImode, dest);
5744 emit_move_insn (dest, tmp);
5745 DONE;
5746 }
5747 else
5748 {
5749 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5750 emit_insn (gen_stfiwx (stack, tmp));
5751 emit_move_insn (dest, stack);
5752 DONE;
5753 }
5754 }
5755 [(set_attr "length" "12")
5756 (set_attr "type" "fp")])
5758 (define_insn_and_split "fix_trunc<mode>si2_internal"
5759 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5760 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5761 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5762 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5763 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5764 "#"
5765 ""
5766 [(pc)]
5767 "
5768 {
5769 rtx lowword;
5770 gcc_assert (MEM_P (operands[3]));
5771 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5773 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5774 emit_move_insn (operands[3], operands[2]);
5775 emit_move_insn (operands[0], lowword);
5776 DONE;
5777 }"
5778 [(set_attr "length" "16")
5779 (set_attr "type" "fp")])
5781 (define_expand "fix_trunc<mode>di2"
5782 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5783 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5784 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5785 && TARGET_FCFID"
5786 "")
5788 (define_insn "*fix_trunc<mode>di2_fctidz"
5789 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5790 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5791 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5792 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5793 "fctidz %0,%1"
5794 [(set_attr "type" "fp")])
5796 (define_expand "fixuns_trunc<mode>si2"
5797 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5798 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5799 "TARGET_HARD_FLOAT
5800 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5801 || <E500_CONVERT>)"
5802 "
5803 {
5804 if (!<E500_CONVERT>)
5805 {
5806 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5807 DONE;
5808 }
5809 }")
5811 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5812 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5813 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5814 (clobber (match_scratch:DI 2 "=d"))]
5815 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5816 && TARGET_STFIWX && can_create_pseudo_p ()"
5817 "#"
5818 ""
5819 [(pc)]
5820 {
5821 rtx dest = operands[0];
5822 rtx src = operands[1];
5823 rtx tmp = operands[2];
5825 if (GET_CODE (tmp) == SCRATCH)
5826 tmp = gen_reg_rtx (DImode);
5828 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5829 if (MEM_P (dest))
5830 {
5831 dest = rs6000_address_for_fpconvert (dest);
5832 emit_insn (gen_stfiwx (dest, tmp));
5833 DONE;
5834 }
5835 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5836 {
5837 dest = gen_lowpart (DImode, dest);
5838 emit_move_insn (dest, tmp);
5839 DONE;
5840 }
5841 else
5842 {
5843 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5844 emit_insn (gen_stfiwx (stack, tmp));
5845 emit_move_insn (dest, stack);
5846 DONE;
5847 }
5848 }
5849 [(set_attr "length" "12")
5850 (set_attr "type" "fp")])
5852 (define_expand "fixuns_trunc<mode>di2"
5853 [(set (match_operand:DI 0 "register_operand" "")
5854 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5855 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5856 "")
5858 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5859 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5860 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5861 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5862 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5863 "fctiduz %0,%1"
5864 [(set_attr "type" "fp")])
5866 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5867 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5868 ; because the first makes it clear that operand 0 is not live
5869 ; before the instruction.
5870 (define_insn "fctiwz_<mode>"
5871 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5872 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5873 UNSPEC_FCTIWZ))]
5874 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5875 "fctiwz %0,%1"
5876 [(set_attr "type" "fp")])
5878 (define_insn "fctiwuz_<mode>"
5879 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5880 (unspec:DI [(unsigned_fix:SI
5881 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5882 UNSPEC_FCTIWUZ))]
5883 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5884 "fctiwuz %0,%1"
5885 [(set_attr "type" "fp")])
5887 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5888 ;; since the friz instruction does not truncate the value if the floating
5889 ;; point value is < LONG_MIN or > LONG_MAX.
5890 (define_insn "*friz"
5891 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5892 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5893 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5894 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5895 && !flag_trapping_math && TARGET_FRIZ"
5896 "friz %0,%1"
5897 [(set_attr "type" "fp")])
5899 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5900 ;; load to properly sign extend the value, but at least doing a store, load
5901 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5902 ;; if we have 32-bit memory ops
5903 (define_insn_and_split "*round32<mode>2_fprs"
5904 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5905 (float:SFDF
5906 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5907 (clobber (match_scratch:DI 2 "=d"))
5908 (clobber (match_scratch:DI 3 "=d"))]
5909 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5910 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5911 && can_create_pseudo_p ()"
5912 "#"
5913 ""
5914 [(pc)]
5915 {
5916 rtx dest = operands[0];
5917 rtx src = operands[1];
5918 rtx tmp1 = operands[2];
5919 rtx tmp2 = operands[3];
5920 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5922 if (GET_CODE (tmp1) == SCRATCH)
5923 tmp1 = gen_reg_rtx (DImode);
5924 if (GET_CODE (tmp2) == SCRATCH)
5925 tmp2 = gen_reg_rtx (DImode);
5927 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5928 emit_insn (gen_stfiwx (stack, tmp1));
5929 emit_insn (gen_lfiwax (tmp2, stack));
5930 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5931 DONE;
5932 }
5933 [(set_attr "type" "fpload")
5934 (set_attr "length" "16")])
5936 (define_insn_and_split "*roundu32<mode>2_fprs"
5937 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5938 (unsigned_float:SFDF
5939 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5940 (clobber (match_scratch:DI 2 "=d"))
5941 (clobber (match_scratch:DI 3 "=d"))]
5942 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5943 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5944 && can_create_pseudo_p ()"
5945 "#"
5946 ""
5947 [(pc)]
5948 {
5949 rtx dest = operands[0];
5950 rtx src = operands[1];
5951 rtx tmp1 = operands[2];
5952 rtx tmp2 = operands[3];
5953 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5955 if (GET_CODE (tmp1) == SCRATCH)
5956 tmp1 = gen_reg_rtx (DImode);
5957 if (GET_CODE (tmp2) == SCRATCH)
5958 tmp2 = gen_reg_rtx (DImode);
5960 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5961 emit_insn (gen_stfiwx (stack, tmp1));
5962 emit_insn (gen_lfiwzx (tmp2, stack));
5963 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5964 DONE;
5965 }
5966 [(set_attr "type" "fpload")
5967 (set_attr "length" "16")])
5969 ;; No VSX equivalent to fctid
5970 (define_insn "lrint<mode>di2"
5971 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5972 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5973 UNSPEC_FCTID))]
5974 "TARGET_<MODE>_FPR && TARGET_FPRND"
5975 "fctid %0,%1"
5976 [(set_attr "type" "fp")])
5978 (define_insn "btrunc<mode>2"
5979 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5980 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5981 UNSPEC_FRIZ))]
5982 "TARGET_<MODE>_FPR && TARGET_FPRND"
5983 "@
5984 friz %0,%1
5985 xsrdpiz %x0,%x1"
5986 [(set_attr "type" "fp")
5987 (set_attr "fp_type" "fp_addsub_<Fs>")])
5989 (define_insn "ceil<mode>2"
5990 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5991 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5992 UNSPEC_FRIP))]
5993 "TARGET_<MODE>_FPR && TARGET_FPRND"
5994 "@
5995 frip %0,%1
5996 xsrdpip %x0,%x1"
5997 [(set_attr "type" "fp")
5998 (set_attr "fp_type" "fp_addsub_<Fs>")])
6000 (define_insn "floor<mode>2"
6001 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6002 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6003 UNSPEC_FRIM))]
6004 "TARGET_<MODE>_FPR && TARGET_FPRND"
6005 "@
6006 frim %0,%1
6007 xsrdpim %x0,%x1"
6008 [(set_attr "type" "fp")
6009 (set_attr "fp_type" "fp_addsub_<Fs>")])
6011 ;; No VSX equivalent to frin
6012 (define_insn "round<mode>2"
6013 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6014 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6015 UNSPEC_FRIN))]
6016 "TARGET_<MODE>_FPR && TARGET_FPRND"
6017 "frin %0,%1"
6018 [(set_attr "type" "fp")
6019 (set_attr "fp_type" "fp_addsub_<Fs>")])
6021 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6022 (define_insn "stfiwx"
6023 [(set (match_operand:SI 0 "memory_operand" "=Z")
6024 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6025 UNSPEC_STFIWX))]
6026 "TARGET_PPC_GFXOPT"
6027 "stfiwx %1,%y0"
6028 [(set_attr "type" "fpstore")])
6030 ;; If we don't have a direct conversion to single precision, don't enable this
6031 ;; conversion for 32-bit without fast math, because we don't have the insn to
6032 ;; generate the fixup swizzle to avoid double rounding problems.
6033 (define_expand "floatsisf2"
6034 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6035 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6036 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6037 && (!TARGET_FPRS
6038 || (TARGET_FPRS
6039 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6040 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6041 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6042 "
6043 {
6044 if (!TARGET_FPRS)
6045 {
6046 if (!REG_P (operands[1]))
6047 operands[1] = force_reg (SImode, operands[1]);
6048 }
6049 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6050 {
6051 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6052 DONE;
6053 }
6054 else if (TARGET_FCFID && TARGET_LFIWAX)
6055 {
6056 rtx dfreg = gen_reg_rtx (DFmode);
6057 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6058 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6059 DONE;
6060 }
6061 else
6062 {
6063 rtx dreg = operands[1];
6064 if (!REG_P (dreg))
6065 dreg = force_reg (SImode, dreg);
6066 dreg = convert_to_mode (DImode, dreg, false);
6067 emit_insn (gen_floatdisf2 (operands[0], dreg));
6068 DONE;
6069 }
6070 }")
6072 (define_expand "floatdidf2"
6073 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6074 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6075 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6076 "")
6078 (define_insn "*floatdidf2_fpr"
6079 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6080 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6081 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6082 && !VECTOR_UNIT_VSX_P (DFmode)"
6083 "fcfid %0,%1"
6084 [(set_attr "type" "fp")])
6086 ; Allow the combiner to merge source memory operands to the conversion so that
6087 ; the optimizer/register allocator doesn't try to load the value too early in a
6088 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6089 ; hit. We will split after reload to avoid the trip through the GPRs
6091 (define_insn_and_split "*floatdidf2_mem"
6092 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6093 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6094 (clobber (match_scratch:DI 2 "=d"))]
6095 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6096 "#"
6097 "&& reload_completed"
6098 [(set (match_dup 2) (match_dup 1))
6099 (set (match_dup 0) (float:DF (match_dup 2)))]
6100 ""
6101 [(set_attr "length" "8")
6102 (set_attr "type" "fpload")])
6104 (define_expand "floatunsdidf2"
6105 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6106 (unsigned_float:DF
6107 (match_operand:DI 1 "gpc_reg_operand" "")))]
6108 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6109 "")
6111 (define_insn "*floatunsdidf2_fcfidu"
6112 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6113 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6114 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6115 "fcfidu %0,%1"
6116 [(set_attr "type" "fp")
6117 (set_attr "length" "4")])
6119 (define_insn_and_split "*floatunsdidf2_mem"
6120 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6121 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6122 (clobber (match_scratch:DI 2 "=d"))]
6123 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6124 "#"
6125 "&& reload_completed"
6126 [(set (match_dup 2) (match_dup 1))
6127 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6128 ""
6129 [(set_attr "length" "8")
6130 (set_attr "type" "fpload")])
6132 (define_expand "floatdisf2"
6133 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6134 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6135 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6136 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6137 "
6138 {
6139 if (!TARGET_FCFIDS)
6140 {
6141 rtx val = operands[1];
6142 if (!flag_unsafe_math_optimizations)
6143 {
6144 rtx label = gen_label_rtx ();
6145 val = gen_reg_rtx (DImode);
6146 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6147 emit_label (label);
6148 }
6149 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6150 DONE;
6151 }
6152 }")
6154 (define_insn "floatdisf2_fcfids"
6155 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6156 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6157 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6158 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6159 "fcfids %0,%1"
6160 [(set_attr "type" "fp")])
6162 (define_insn_and_split "*floatdisf2_mem"
6163 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6164 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6165 (clobber (match_scratch:DI 2 "=f"))]
6166 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6167 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6168 "#"
6169 "&& reload_completed"
6170 [(pc)]
6171 "
6172 {
6173 emit_move_insn (operands[2], operands[1]);
6174 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6175 DONE;
6176 }"
6177 [(set_attr "length" "8")])
6179 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6180 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6181 ;; from double rounding.
6182 ;; Instead of creating a new cpu type for two FP operations, just use fp
6183 (define_insn_and_split "floatdisf2_internal1"
6184 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6185 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6186 (clobber (match_scratch:DF 2 "=d"))]
6187 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6188 "#"
6189 "&& reload_completed"
6190 [(set (match_dup 2)
6191 (float:DF (match_dup 1)))
6192 (set (match_dup 0)
6193 (float_truncate:SF (match_dup 2)))]
6194 ""
6195 [(set_attr "length" "8")
6196 (set_attr "type" "fp")])
6198 ;; Twiddles bits to avoid double rounding.
6199 ;; Bits that might be truncated when converting to DFmode are replaced
6200 ;; by a bit that won't be lost at that stage, but is below the SFmode
6201 ;; rounding position.
6202 (define_expand "floatdisf2_internal2"
6203 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6204 (const_int 53)))
6205 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6206 (const_int 2047)))
6207 (set (match_dup 3) (plus:DI (match_dup 3)
6208 (const_int 1)))
6209 (set (match_dup 0) (plus:DI (match_dup 0)
6210 (const_int 2047)))
6211 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6212 (const_int 2)))
6213 (set (match_dup 0) (ior:DI (match_dup 0)
6214 (match_dup 1)))
6215 (set (match_dup 0) (and:DI (match_dup 0)
6216 (const_int -2048)))
6217 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6218 (label_ref (match_operand:DI 2 "" ""))
6219 (pc)))
6220 (set (match_dup 0) (match_dup 1))]
6221 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6222 "
6223 {
6224 operands[3] = gen_reg_rtx (DImode);
6225 operands[4] = gen_reg_rtx (CCUNSmode);
6226 }")
6228 (define_expand "floatunsdisf2"
6229 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6230 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6231 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6232 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6233 "")
6235 (define_insn "floatunsdisf2_fcfidus"
6236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6237 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6238 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6239 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6240 "fcfidus %0,%1"
6241 [(set_attr "type" "fp")])
6243 (define_insn_and_split "*floatunsdisf2_mem"
6244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6245 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6246 (clobber (match_scratch:DI 2 "=f"))]
6247 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6248 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6249 "#"
6250 "&& reload_completed"
6251 [(pc)]
6252 "
6253 {
6254 emit_move_insn (operands[2], operands[1]);
6255 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6256 DONE;
6257 }"
6258 [(set_attr "length" "8")
6259 (set_attr "type" "fpload")])
6260 \f
6261 ;; Define the TImode operations that can be done in a small number
6262 ;; of instructions. The & constraints are to prevent the register
6263 ;; allocator from allocating registers that overlap with the inputs
6264 ;; (for example, having an input in 7,8 and an output in 6,7). We
6265 ;; also allow for the output being the same as one of the inputs.
6267 (define_insn "addti3"
6268 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6269 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6270 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6271 "TARGET_64BIT"
6272 {
6273 if (WORDS_BIG_ENDIAN)
6274 return (GET_CODE (operands[2])) != CONST_INT
6275 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6276 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6277 else
6278 return (GET_CODE (operands[2])) != CONST_INT
6279 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6280 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6281 }
6282 [(set_attr "type" "two")
6283 (set_attr "length" "8")])
6285 (define_insn "subti3"
6286 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6287 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6288 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6289 "TARGET_64BIT"
6290 {
6291 if (WORDS_BIG_ENDIAN)
6292 return (GET_CODE (operands[1]) != CONST_INT)
6293 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6294 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6295 else
6296 return (GET_CODE (operands[1]) != CONST_INT)
6297 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6298 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6299 }
6300 [(set_attr "type" "two")
6301 (set_attr "length" "8")])
6304 ;; Define the DImode operations that can be done in a small number
6305 ;; of instructions. The & constraints are to prevent the register
6306 ;; allocator from allocating registers that overlap with the inputs
6307 ;; (for example, having an input in 7,8 and an output in 6,7). We
6308 ;; also allow for the output being the same as one of the inputs.
6310 (define_insn "*adddi3_noppc64"
6311 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6312 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6313 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6314 "! TARGET_POWERPC64"
6315 "*
6316 {
6317 if (WORDS_BIG_ENDIAN)
6318 return (GET_CODE (operands[2])) != CONST_INT
6319 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6320 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6321 else
6322 return (GET_CODE (operands[2])) != CONST_INT
6323 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6324 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6325 }"
6326 [(set_attr "type" "two")
6327 (set_attr "length" "8")])
6329 (define_insn "*subdi3_noppc64"
6330 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6331 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6332 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6333 "! TARGET_POWERPC64"
6334 "*
6335 {
6336 if (WORDS_BIG_ENDIAN)
6337 return (GET_CODE (operands[1]) != CONST_INT)
6338 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6339 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6340 else
6341 return (GET_CODE (operands[1]) != CONST_INT)
6342 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6343 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6344 }"
6345 [(set_attr "type" "two")
6346 (set_attr "length" "8")])
6348 (define_insn "*negdi2_noppc64"
6349 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6350 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6351 "! TARGET_POWERPC64"
6352 "*
6353 {
6354 return (WORDS_BIG_ENDIAN)
6355 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6356 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6357 }"
6358 [(set_attr "type" "two")
6359 (set_attr "length" "8")])
6362 ;; Shift by a variable amount is too complex to be worth open-coding. We
6363 ;; just handle shifts by constants.
6364 (define_insn "ashrdi3_no_power"
6365 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6366 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6367 (match_operand:SI 2 "const_int_operand" "M,i")))]
6368 "!TARGET_POWERPC64"
6369 "*
6370 {
6371 switch (which_alternative)
6372 {
6373 default:
6374 gcc_unreachable ();
6375 case 0:
6376 if (WORDS_BIG_ENDIAN)
6377 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6378 else
6379 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6380 case 1:
6381 if (WORDS_BIG_ENDIAN)
6382 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6383 else
6384 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6385 }
6386 }"
6387 [(set_attr "type" "two,three")
6388 (set_attr "length" "8,12")])
6390 (define_insn "*ashrdisi3_noppc64be"
6391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6392 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6393 (const_int 32)) 4))]
6394 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6395 "*
6396 {
6397 if (REGNO (operands[0]) == REGNO (operands[1]))
6398 return \"\";
6399 else
6400 return \"mr %0,%1\";
6401 }"
6402 [(set_attr "length" "4")])
6404 \f
6405 ;; PowerPC64 DImode operations.
6407 (define_insn "*rotldi3_internal4"
6408 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6409 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6410 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6411 (match_operand:DI 3 "mask64_operand" "n")))]
6412 "TARGET_POWERPC64"
6413 "rld%I2c%B3 %0,%1,%H2,%S3"
6414 [(set_attr "type" "shift")
6415 (set_attr "maybe_var_shift" "yes")])
6417 (define_insn "*rotldi3_internal5"
6418 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6419 (compare:CC (and:DI
6420 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6421 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6422 (match_operand:DI 3 "mask64_operand" "n,n"))
6423 (const_int 0)))
6424 (clobber (match_scratch:DI 4 "=r,r"))]
6425 "TARGET_64BIT"
6426 "@
6427 rld%I2c%B3. %4,%1,%H2,%S3
6428 #"
6429 [(set_attr "type" "shift")
6430 (set_attr "maybe_var_shift" "yes")
6431 (set_attr "dot" "yes")
6432 (set_attr "length" "4,8")])
6434 (define_split
6435 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6436 (compare:CC (and:DI
6437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6438 (match_operand:DI 2 "reg_or_cint_operand" ""))
6439 (match_operand:DI 3 "mask64_operand" ""))
6440 (const_int 0)))
6441 (clobber (match_scratch:DI 4 ""))]
6442 "TARGET_POWERPC64 && reload_completed"
6443 [(set (match_dup 4)
6444 (and:DI (rotate:DI (match_dup 1)
6445 (match_dup 2))
6446 (match_dup 3)))
6447 (set (match_dup 0)
6448 (compare:CC (match_dup 4)
6449 (const_int 0)))]
6450 "")
6452 (define_insn "*rotldi3_internal6"
6453 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6454 (compare:CC (and:DI
6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6457 (match_operand:DI 3 "mask64_operand" "n,n"))
6458 (const_int 0)))
6459 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6460 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6461 "TARGET_64BIT"
6462 "@
6463 rld%I2c%B3. %0,%1,%H2,%S3
6464 #"
6465 [(set_attr "type" "shift")
6466 (set_attr "maybe_var_shift" "yes")
6467 (set_attr "dot" "yes")
6468 (set_attr "length" "4,8")])
6470 (define_split
6471 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6472 (compare:CC (and:DI
6473 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6474 (match_operand:DI 2 "reg_or_cint_operand" ""))
6475 (match_operand:DI 3 "mask64_operand" ""))
6476 (const_int 0)))
6477 (set (match_operand:DI 0 "gpc_reg_operand" "")
6478 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6479 "TARGET_POWERPC64 && reload_completed"
6480 [(set (match_dup 0)
6481 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6482 (set (match_dup 4)
6483 (compare:CC (match_dup 0)
6484 (const_int 0)))]
6485 "")
6487 (define_insn "*rotldi3_internal7le"
6488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6489 (zero_extend:DI
6490 (subreg:QI
6491 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6492 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6493 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6494 "rld%I2cl %0,%1,%H2,56"
6495 [(set_attr "type" "shift")
6496 (set_attr "maybe_var_shift" "yes")])
6498 (define_insn "*rotldi3_internal7be"
6499 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6500 (zero_extend:DI
6501 (subreg:QI
6502 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6503 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6504 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6505 "rld%I2cl %0,%1,%H2,56"
6506 [(set_attr "type" "shift")
6507 (set_attr "maybe_var_shift" "yes")])
6509 (define_insn "*rotldi3_internal8le"
6510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6511 (compare:CC (zero_extend:DI
6512 (subreg:QI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6514 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 3 "=r,r"))]
6517 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6518 "@
6519 rld%I2cl. %3,%1,%H2,56
6520 #"
6521 [(set_attr "type" "shift")
6522 (set_attr "maybe_var_shift" "yes")
6523 (set_attr "dot" "yes")
6524 (set_attr "length" "4,8")])
6526 (define_insn "*rotldi3_internal8be"
6527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6528 (compare:CC (zero_extend:DI
6529 (subreg:QI
6530 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6532 (const_int 0)))
6533 (clobber (match_scratch:DI 3 "=r,r"))]
6534 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6535 "@
6536 rld%I2cl. %3,%1,%H2,56
6537 #"
6538 [(set_attr "type" "shift")
6539 (set_attr "maybe_var_shift" "yes")
6540 (set_attr "dot" "yes")
6541 (set_attr "length" "4,8")])
6543 (define_split
6544 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6545 (compare:CC (zero_extend:DI
6546 (subreg:QI
6547 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6548 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6549 (const_int 0)))
6550 (clobber (match_scratch:DI 3 ""))]
6551 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6552 [(set (match_dup 3)
6553 (zero_extend:DI (subreg:QI
6554 (rotate:DI (match_dup 1)
6555 (match_dup 2)) 0)))
6556 (set (match_dup 0)
6557 (compare:CC (match_dup 3)
6558 (const_int 0)))]
6559 "")
6561 (define_split
6562 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6563 (compare:CC (zero_extend:DI
6564 (subreg:QI
6565 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6566 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6567 (const_int 0)))
6568 (clobber (match_scratch:DI 3 ""))]
6569 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6570 [(set (match_dup 3)
6571 (zero_extend:DI (subreg:QI
6572 (rotate:DI (match_dup 1)
6573 (match_dup 2)) 7)))
6574 (set (match_dup 0)
6575 (compare:CC (match_dup 3)
6576 (const_int 0)))]
6577 "")
6579 (define_insn "*rotldi3_internal9le"
6580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6581 (compare:CC (zero_extend:DI
6582 (subreg:QI
6583 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6584 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6585 (const_int 0)))
6586 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6587 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6588 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6589 "@
6590 rld%I2cl. %0,%1,%H2,56
6591 #"
6592 [(set_attr "type" "shift")
6593 (set_attr "maybe_var_shift" "yes")
6594 (set_attr "dot" "yes")
6595 (set_attr "length" "4,8")])
6597 (define_insn "*rotldi3_internal9be"
6598 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6599 (compare:CC (zero_extend:DI
6600 (subreg:QI
6601 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6602 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6603 (const_int 0)))
6604 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6605 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6606 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6607 "@
6608 rld%I2cl. %0,%1,%H2,56
6609 #"
6610 [(set_attr "type" "shift")
6611 (set_attr "maybe_var_shift" "yes")
6612 (set_attr "dot" "yes")
6613 (set_attr "length" "4,8")])
6615 (define_split
6616 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6617 (compare:CC (zero_extend:DI
6618 (subreg:QI
6619 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6620 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6621 (const_int 0)))
6622 (set (match_operand:DI 0 "gpc_reg_operand" "")
6623 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6624 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6625 [(set (match_dup 0)
6626 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6627 (set (match_dup 3)
6628 (compare:CC (match_dup 0)
6629 (const_int 0)))]
6630 "")
6632 (define_split
6633 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6634 (compare:CC (zero_extend:DI
6635 (subreg:QI
6636 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6637 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6638 (const_int 0)))
6639 (set (match_operand:DI 0 "gpc_reg_operand" "")
6640 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6641 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6642 [(set (match_dup 0)
6643 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6644 (set (match_dup 3)
6645 (compare:CC (match_dup 0)
6646 (const_int 0)))]
6647 "")
6649 (define_insn "*rotldi3_internal10le"
6650 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6651 (zero_extend:DI
6652 (subreg:HI
6653 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6654 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6655 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6656 "rld%I2cl %0,%1,%H2,48"
6657 [(set_attr "type" "shift")
6658 (set_attr "maybe_var_shift" "yes")])
6660 (define_insn "*rotldi3_internal10be"
6661 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6662 (zero_extend:DI
6663 (subreg:HI
6664 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6665 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6666 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6667 "rld%I2cl %0,%1,%H2,48"
6668 [(set_attr "type" "shift")
6669 (set_attr "maybe_var_shift" "yes")])
6671 (define_insn "*rotldi3_internal11le"
6672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6673 (compare:CC (zero_extend:DI
6674 (subreg:HI
6675 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6676 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6677 (const_int 0)))
6678 (clobber (match_scratch:DI 3 "=r,r"))]
6679 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6680 "@
6681 rld%I2cl. %3,%1,%H2,48
6682 #"
6683 [(set_attr "type" "shift")
6684 (set_attr "maybe_var_shift" "yes")
6685 (set_attr "dot" "yes")
6686 (set_attr "length" "4,8")])
6688 (define_insn "*rotldi3_internal11be"
6689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6690 (compare:CC (zero_extend:DI
6691 (subreg:HI
6692 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6693 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6694 (const_int 0)))
6695 (clobber (match_scratch:DI 3 "=r,r"))]
6696 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6697 "@
6698 rld%I2cl. %3,%1,%H2,48
6699 #"
6700 [(set_attr "type" "shift")
6701 (set_attr "maybe_var_shift" "yes")
6702 (set_attr "dot" "yes")
6703 (set_attr "length" "4,8")])
6705 (define_split
6706 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6707 (compare:CC (zero_extend:DI
6708 (subreg:HI
6709 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6710 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6711 (const_int 0)))
6712 (clobber (match_scratch:DI 3 ""))]
6713 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6714 [(set (match_dup 3)
6715 (zero_extend:DI (subreg:HI
6716 (rotate:DI (match_dup 1)
6717 (match_dup 2)) 0)))
6718 (set (match_dup 0)
6719 (compare:CC (match_dup 3)
6720 (const_int 0)))]
6721 "")
6723 (define_split
6724 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6725 (compare:CC (zero_extend:DI
6726 (subreg:HI
6727 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6728 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6729 (const_int 0)))
6730 (clobber (match_scratch:DI 3 ""))]
6731 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6732 [(set (match_dup 3)
6733 (zero_extend:DI (subreg:HI
6734 (rotate:DI (match_dup 1)
6735 (match_dup 2)) 6)))
6736 (set (match_dup 0)
6737 (compare:CC (match_dup 3)
6738 (const_int 0)))]
6739 "")
6741 (define_insn "*rotldi3_internal12le"
6742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6743 (compare:CC (zero_extend:DI
6744 (subreg:HI
6745 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6746 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6747 (const_int 0)))
6748 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6749 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6750 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6751 "@
6752 rld%I2cl. %0,%1,%H2,48
6753 #"
6754 [(set_attr "type" "shift")
6755 (set_attr "maybe_var_shift" "yes")
6756 (set_attr "dot" "yes")
6757 (set_attr "length" "4,8")])
6759 (define_insn "*rotldi3_internal12be"
6760 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6761 (compare:CC (zero_extend:DI
6762 (subreg:HI
6763 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6764 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6765 (const_int 0)))
6766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6767 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6768 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6769 "@
6770 rld%I2cl. %0,%1,%H2,48
6771 #"
6772 [(set_attr "type" "shift")
6773 (set_attr "maybe_var_shift" "yes")
6774 (set_attr "dot" "yes")
6775 (set_attr "length" "4,8")])
6777 (define_split
6778 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6779 (compare:CC (zero_extend:DI
6780 (subreg:HI
6781 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6782 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6783 (const_int 0)))
6784 (set (match_operand:DI 0 "gpc_reg_operand" "")
6785 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6786 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6787 [(set (match_dup 0)
6788 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6789 (set (match_dup 3)
6790 (compare:CC (match_dup 0)
6791 (const_int 0)))]
6792 "")
6794 (define_split
6795 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6796 (compare:CC (zero_extend:DI
6797 (subreg:HI
6798 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6799 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6800 (const_int 0)))
6801 (set (match_operand:DI 0 "gpc_reg_operand" "")
6802 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6803 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6804 [(set (match_dup 0)
6805 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6806 (set (match_dup 3)
6807 (compare:CC (match_dup 0)
6808 (const_int 0)))]
6809 "")
6811 (define_insn "*rotldi3_internal13le"
6812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6813 (zero_extend:DI
6814 (subreg:SI
6815 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6816 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6817 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6818 "rld%I2cl %0,%1,%H2,32"
6819 [(set_attr "type" "shift")
6820 (set_attr "maybe_var_shift" "yes")])
6822 (define_insn "*rotldi3_internal13be"
6823 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6824 (zero_extend:DI
6825 (subreg:SI
6826 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6827 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6828 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6829 "rld%I2cl %0,%1,%H2,32"
6830 [(set_attr "type" "shift")
6831 (set_attr "maybe_var_shift" "yes")])
6833 (define_insn "*rotldi3_internal14le"
6834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6835 (compare:CC (zero_extend:DI
6836 (subreg:SI
6837 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6838 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6839 (const_int 0)))
6840 (clobber (match_scratch:DI 3 "=r,r"))]
6841 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6842 "@
6843 rld%I2cl. %3,%1,%H2,32
6844 #"
6845 [(set_attr "type" "shift")
6846 (set_attr "maybe_var_shift" "yes")
6847 (set_attr "dot" "yes")
6848 (set_attr "length" "4,8")])
6850 (define_insn "*rotldi3_internal14be"
6851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6852 (compare:CC (zero_extend:DI
6853 (subreg:SI
6854 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6855 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6856 (const_int 0)))
6857 (clobber (match_scratch:DI 3 "=r,r"))]
6858 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6859 "@
6860 rld%I2cl. %3,%1,%H2,32
6861 #"
6862 [(set_attr "type" "shift")
6863 (set_attr "maybe_var_shift" "yes")
6864 (set_attr "dot" "yes")
6865 (set_attr "length" "4,8")])
6867 (define_split
6868 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6869 (compare:CC (zero_extend:DI
6870 (subreg:SI
6871 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6872 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6873 (const_int 0)))
6874 (clobber (match_scratch:DI 3 ""))]
6875 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6876 [(set (match_dup 3)
6877 (zero_extend:DI (subreg:SI
6878 (rotate:DI (match_dup 1)
6879 (match_dup 2)) 0)))
6880 (set (match_dup 0)
6881 (compare:CC (match_dup 3)
6882 (const_int 0)))]
6883 "")
6885 (define_split
6886 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6887 (compare:CC (zero_extend:DI
6888 (subreg:SI
6889 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6890 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6891 (const_int 0)))
6892 (clobber (match_scratch:DI 3 ""))]
6893 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6894 [(set (match_dup 3)
6895 (zero_extend:DI (subreg:SI
6896 (rotate:DI (match_dup 1)
6897 (match_dup 2)) 4)))
6898 (set (match_dup 0)
6899 (compare:CC (match_dup 3)
6900 (const_int 0)))]
6901 "")
6903 (define_insn "*rotldi3_internal15le"
6904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6905 (compare:CC (zero_extend:DI
6906 (subreg:SI
6907 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6908 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6909 (const_int 0)))
6910 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6911 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6912 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6913 "@
6914 rld%I2cl. %0,%1,%H2,32
6915 #"
6916 [(set_attr "type" "shift")
6917 (set_attr "maybe_var_shift" "yes")
6918 (set_attr "dot" "yes")
6919 (set_attr "length" "4,8")])
6921 (define_insn "*rotldi3_internal15be"
6922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6923 (compare:CC (zero_extend:DI
6924 (subreg:SI
6925 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6926 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6927 (const_int 0)))
6928 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6929 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6930 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6931 "@
6932 rld%I2cl. %0,%1,%H2,32
6933 #"
6934 [(set_attr "type" "shift")
6935 (set_attr "maybe_var_shift" "yes")
6936 (set_attr "dot" "yes")
6937 (set_attr "length" "4,8")])
6939 (define_split
6940 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6941 (compare:CC (zero_extend:DI
6942 (subreg:SI
6943 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6944 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6945 (const_int 0)))
6946 (set (match_operand:DI 0 "gpc_reg_operand" "")
6947 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6948 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6949 [(set (match_dup 0)
6950 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6951 (set (match_dup 3)
6952 (compare:CC (match_dup 0)
6953 (const_int 0)))]
6954 "")
6956 (define_split
6957 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6958 (compare:CC (zero_extend:DI
6959 (subreg:SI
6960 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6961 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6962 (const_int 0)))
6963 (set (match_operand:DI 0 "gpc_reg_operand" "")
6964 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6965 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6966 [(set (match_dup 0)
6967 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
6968 (set (match_dup 3)
6969 (compare:CC (match_dup 0)
6970 (const_int 0)))]
6971 "")
6973 (define_insn "*ashldi3_internal4"
6974 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6975 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6976 (match_operand:SI 2 "const_int_operand" "i"))
6977 (match_operand:DI 3 "const_int_operand" "n")))]
6978 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6979 "rldic %0,%1,%H2,%W3"
6980 [(set_attr "type" "shift")])
6982 (define_insn "ashldi3_internal5"
6983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6984 (compare:CC
6985 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6986 (match_operand:SI 2 "const_int_operand" "i,i"))
6987 (match_operand:DI 3 "const_int_operand" "n,n"))
6988 (const_int 0)))
6989 (clobber (match_scratch:DI 4 "=r,r"))]
6990 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6991 "@
6992 rldic. %4,%1,%H2,%W3
6993 #"
6994 [(set_attr "type" "shift")
6995 (set_attr "dot" "yes")
6996 (set_attr "length" "4,8")])
6998 (define_split
6999 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7000 (compare:CC
7001 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7002 (match_operand:SI 2 "const_int_operand" ""))
7003 (match_operand:DI 3 "const_int_operand" ""))
7004 (const_int 0)))
7005 (clobber (match_scratch:DI 4 ""))]
7006 "TARGET_POWERPC64 && reload_completed
7007 && includes_rldic_lshift_p (operands[2], operands[3])"
7008 [(set (match_dup 4)
7009 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7010 (match_dup 3)))
7011 (set (match_dup 0)
7012 (compare:CC (match_dup 4)
7013 (const_int 0)))]
7014 "")
7016 (define_insn "*ashldi3_internal6"
7017 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7018 (compare:CC
7019 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7020 (match_operand:SI 2 "const_int_operand" "i,i"))
7021 (match_operand:DI 3 "const_int_operand" "n,n"))
7022 (const_int 0)))
7023 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7024 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7025 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7026 "@
7027 rldic. %0,%1,%H2,%W3
7028 #"
7029 [(set_attr "type" "shift")
7030 (set_attr "dot" "yes")
7031 (set_attr "length" "4,8")])
7033 (define_split
7034 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7035 (compare:CC
7036 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7037 (match_operand:SI 2 "const_int_operand" ""))
7038 (match_operand:DI 3 "const_int_operand" ""))
7039 (const_int 0)))
7040 (set (match_operand:DI 0 "gpc_reg_operand" "")
7041 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7042 "TARGET_POWERPC64 && reload_completed
7043 && includes_rldic_lshift_p (operands[2], operands[3])"
7044 [(set (match_dup 0)
7045 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7046 (match_dup 3)))
7047 (set (match_dup 4)
7048 (compare:CC (match_dup 0)
7049 (const_int 0)))]
7050 "")
7052 (define_insn "*ashldi3_internal7"
7053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7054 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7055 (match_operand:SI 2 "const_int_operand" "i"))
7056 (match_operand:DI 3 "mask64_operand" "n")))]
7057 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7058 "rldicr %0,%1,%H2,%S3"
7059 [(set_attr "type" "shift")])
7061 (define_insn "ashldi3_internal8"
7062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7063 (compare:CC
7064 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7065 (match_operand:SI 2 "const_int_operand" "i,i"))
7066 (match_operand:DI 3 "mask64_operand" "n,n"))
7067 (const_int 0)))
7068 (clobber (match_scratch:DI 4 "=r,r"))]
7069 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7070 "@
7071 rldicr. %4,%1,%H2,%S3
7072 #"
7073 [(set_attr "type" "shift")
7074 (set_attr "dot" "yes")
7075 (set_attr "length" "4,8")])
7077 (define_split
7078 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7079 (compare:CC
7080 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7081 (match_operand:SI 2 "const_int_operand" ""))
7082 (match_operand:DI 3 "mask64_operand" ""))
7083 (const_int 0)))
7084 (clobber (match_scratch:DI 4 ""))]
7085 "TARGET_POWERPC64 && reload_completed
7086 && includes_rldicr_lshift_p (operands[2], operands[3])"
7087 [(set (match_dup 4)
7088 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7089 (match_dup 3)))
7090 (set (match_dup 0)
7091 (compare:CC (match_dup 4)
7092 (const_int 0)))]
7093 "")
7095 (define_insn "*ashldi3_internal9"
7096 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7097 (compare:CC
7098 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7099 (match_operand:SI 2 "const_int_operand" "i,i"))
7100 (match_operand:DI 3 "mask64_operand" "n,n"))
7101 (const_int 0)))
7102 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7103 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7104 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7105 "@
7106 rldicr. %0,%1,%H2,%S3
7107 #"
7108 [(set_attr "type" "shift")
7109 (set_attr "dot" "yes")
7110 (set_attr "length" "4,8")])
7112 (define_split
7113 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7114 (compare:CC
7115 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7116 (match_operand:SI 2 "const_int_operand" ""))
7117 (match_operand:DI 3 "mask64_operand" ""))
7118 (const_int 0)))
7119 (set (match_operand:DI 0 "gpc_reg_operand" "")
7120 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7121 "TARGET_POWERPC64 && reload_completed
7122 && includes_rldicr_lshift_p (operands[2], operands[3])"
7123 [(set (match_dup 0)
7124 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7125 (match_dup 3)))
7126 (set (match_dup 4)
7127 (compare:CC (match_dup 0)
7128 (const_int 0)))]
7129 "")
7132 (define_insn_and_split "*anddi3_2rld"
7133 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7134 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7135 (match_operand:DI 2 "and_2rld_operand" "n")))]
7136 "TARGET_POWERPC64"
7137 "#"
7138 ""
7139 [(set (match_dup 0)
7140 (and:DI (rotate:DI (match_dup 1)
7141 (match_dup 4))
7142 (match_dup 5)))
7143 (set (match_dup 0)
7144 (and:DI (rotate:DI (match_dup 0)
7145 (match_dup 6))
7146 (match_dup 7)))]
7147 {
7148 build_mask64_2_operands (operands[2], &operands[4]);
7149 }
7150 [(set_attr "length" "8")])
7152 (define_insn_and_split "*anddi3_2rld_dot"
7153 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7154 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7155 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7156 (const_int 0)))
7157 (clobber (match_scratch:DI 0 "=r,r"))]
7158 "TARGET_64BIT && rs6000_gen_cell_microcode"
7159 "@
7160 #
7161 #"
7162 "&& reload_completed"
7163 [(set (match_dup 0)
7164 (and:DI (rotate:DI (match_dup 1)
7165 (match_dup 4))
7166 (match_dup 5)))
7167 (parallel [(set (match_dup 3)
7168 (compare:CC (and:DI (rotate:DI (match_dup 0)
7169 (match_dup 6))
7170 (match_dup 7))
7171 (const_int 0)))
7172 (clobber (match_dup 0))])]
7173 {
7174 build_mask64_2_operands (operands[2], &operands[4]);
7175 }
7176 [(set_attr "type" "compare")
7177 (set_attr "dot" "yes")
7178 (set_attr "length" "8,12")])
7180 (define_insn_and_split "*anddi3_2rld_dot2"
7181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7182 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7183 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7184 (const_int 0)))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7186 (and:DI (match_dup 1)
7187 (match_dup 2)))]
7188 "TARGET_64BIT && rs6000_gen_cell_microcode"
7189 "@
7190 #
7191 #"
7192 "&& reload_completed"
7193 [(set (match_dup 0)
7194 (and:DI (rotate:DI (match_dup 1)
7195 (match_dup 4))
7196 (match_dup 5)))
7197 (parallel [(set (match_dup 3)
7198 (compare:CC (and:DI (rotate:DI (match_dup 0)
7199 (match_dup 6))
7200 (match_dup 7))
7201 (const_int 0)))
7202 (set (match_dup 0)
7203 (and:DI (rotate:DI (match_dup 0)
7204 (match_dup 6))
7205 (match_dup 7)))])]
7206 {
7207 build_mask64_2_operands (operands[2], &operands[4]);
7208 }
7209 [(set_attr "type" "compare")
7210 (set_attr "dot" "yes")
7211 (set_attr "length" "8,12")])
7212 \f
7213 ;; 128-bit logical operations expanders
7215 (define_expand "and<mode>3"
7216 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7217 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7218 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7219 ""
7220 "")
7222 (define_expand "ior<mode>3"
7223 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7224 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7225 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7226 ""
7227 "")
7229 (define_expand "xor<mode>3"
7230 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7231 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7232 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7233 ""
7234 "")
7236 (define_expand "one_cmpl<mode>2"
7237 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7238 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7239 ""
7240 "")
7242 (define_expand "nor<mode>3"
7243 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7244 (and:BOOL_128
7245 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7246 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7247 ""
7248 "")
7250 (define_expand "andc<mode>3"
7251 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7252 (and:BOOL_128
7253 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7254 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7255 ""
7256 "")
7258 ;; Power8 vector logical instructions.
7259 (define_expand "eqv<mode>3"
7260 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7261 (not:BOOL_128
7262 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7263 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7264 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7265 "")
7267 ;; Rewrite nand into canonical form
7268 (define_expand "nand<mode>3"
7269 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7270 (ior:BOOL_128
7271 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7272 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7273 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7274 "")
7276 ;; The canonical form is to have the negated element first, so we need to
7277 ;; reverse arguments.
7278 (define_expand "orc<mode>3"
7279 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7280 (ior:BOOL_128
7281 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7282 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7283 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7284 "")
7286 ;; 128-bit logical operations insns and split operations
7287 (define_insn_and_split "*and<mode>3_internal"
7288 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7289 (and:BOOL_128
7290 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7291 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7292 ""
7293 {
7294 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7295 return "xxland %x0,%x1,%x2";
7297 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7298 return "vand %0,%1,%2";
7300 return "#";
7301 }
7302 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7303 [(const_int 0)]
7304 {
7305 rs6000_split_logical (operands, AND, false, false, false);
7306 DONE;
7307 }
7308 [(set (attr "type")
7309 (if_then_else
7310 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7311 (const_string "vecsimple")
7312 (const_string "integer")))
7313 (set (attr "length")
7314 (if_then_else
7315 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7316 (const_string "4")
7317 (if_then_else
7318 (match_test "TARGET_POWERPC64")
7319 (const_string "8")
7320 (const_string "16"))))])
7322 ;; 128-bit IOR/XOR
7323 (define_insn_and_split "*bool<mode>3_internal"
7324 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7325 (match_operator:BOOL_128 3 "boolean_or_operator"
7326 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7327 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7328 ""
7329 {
7330 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7331 return "xxl%q3 %x0,%x1,%x2";
7333 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7334 return "v%q3 %0,%1,%2";
7336 return "#";
7337 }
7338 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7339 [(const_int 0)]
7340 {
7341 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7342 DONE;
7343 }
7344 [(set (attr "type")
7345 (if_then_else
7346 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7347 (const_string "vecsimple")
7348 (const_string "integer")))
7349 (set (attr "length")
7350 (if_then_else
7351 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7352 (const_string "4")
7353 (if_then_else
7354 (match_test "TARGET_POWERPC64")
7355 (const_string "8")
7356 (const_string "16"))))])
7358 ;; 128-bit ANDC/ORC
7359 (define_insn_and_split "*boolc<mode>3_internal1"
7360 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7361 (match_operator:BOOL_128 3 "boolean_operator"
7362 [(not:BOOL_128
7363 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7364 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7365 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7366 {
7367 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7368 return "xxl%q3 %x0,%x1,%x2";
7370 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7371 return "v%q3 %0,%1,%2";
7373 return "#";
7374 }
7375 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7376 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7377 [(const_int 0)]
7378 {
7379 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7380 DONE;
7381 }
7382 [(set (attr "type")
7383 (if_then_else
7384 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7385 (const_string "vecsimple")
7386 (const_string "integer")))
7387 (set (attr "length")
7388 (if_then_else
7389 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7390 (const_string "4")
7391 (if_then_else
7392 (match_test "TARGET_POWERPC64")
7393 (const_string "8")
7394 (const_string "16"))))])
7396 (define_insn_and_split "*boolc<mode>3_internal2"
7397 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7398 (match_operator:TI2 3 "boolean_operator"
7399 [(not:TI2
7400 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7401 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7402 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7403 "#"
7404 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7405 [(const_int 0)]
7406 {
7407 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7408 DONE;
7409 }
7410 [(set_attr "type" "integer")
7411 (set (attr "length")
7412 (if_then_else
7413 (match_test "TARGET_POWERPC64")
7414 (const_string "8")
7415 (const_string "16")))])
7417 ;; 128-bit NAND/NOR
7418 (define_insn_and_split "*boolcc<mode>3_internal1"
7419 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7420 (match_operator:BOOL_128 3 "boolean_operator"
7421 [(not:BOOL_128
7422 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7423 (not:BOOL_128
7424 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7425 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7426 {
7427 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7428 return "xxl%q3 %x0,%x1,%x2";
7430 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7431 return "v%q3 %0,%1,%2";
7433 return "#";
7434 }
7435 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7436 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7437 [(const_int 0)]
7438 {
7439 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7440 DONE;
7441 }
7442 [(set (attr "type")
7443 (if_then_else
7444 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7445 (const_string "vecsimple")
7446 (const_string "integer")))
7447 (set (attr "length")
7448 (if_then_else
7449 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7450 (const_string "4")
7451 (if_then_else
7452 (match_test "TARGET_POWERPC64")
7453 (const_string "8")
7454 (const_string "16"))))])
7456 (define_insn_and_split "*boolcc<mode>3_internal2"
7457 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7458 (match_operator:TI2 3 "boolean_operator"
7459 [(not:TI2
7460 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7461 (not:TI2
7462 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7463 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7464 "#"
7465 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7466 [(const_int 0)]
7467 {
7468 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7469 DONE;
7470 }
7471 [(set_attr "type" "integer")
7472 (set (attr "length")
7473 (if_then_else
7474 (match_test "TARGET_POWERPC64")
7475 (const_string "8")
7476 (const_string "16")))])
7479 ;; 128-bit EQV
7480 (define_insn_and_split "*eqv<mode>3_internal1"
7481 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7482 (not:BOOL_128
7483 (xor:BOOL_128
7484 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7485 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7486 "TARGET_P8_VECTOR"
7487 {
7488 if (vsx_register_operand (operands[0], <MODE>mode))
7489 return "xxleqv %x0,%x1,%x2";
7491 return "#";
7492 }
7493 "TARGET_P8_VECTOR && reload_completed
7494 && int_reg_operand (operands[0], <MODE>mode)"
7495 [(const_int 0)]
7496 {
7497 rs6000_split_logical (operands, XOR, true, false, false);
7498 DONE;
7499 }
7500 [(set (attr "type")
7501 (if_then_else
7502 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7503 (const_string "vecsimple")
7504 (const_string "integer")))
7505 (set (attr "length")
7506 (if_then_else
7507 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7508 (const_string "4")
7509 (if_then_else
7510 (match_test "TARGET_POWERPC64")
7511 (const_string "8")
7512 (const_string "16"))))])
7514 (define_insn_and_split "*eqv<mode>3_internal2"
7515 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7516 (not:TI2
7517 (xor:TI2
7518 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7519 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7520 "!TARGET_P8_VECTOR"
7521 "#"
7522 "reload_completed && !TARGET_P8_VECTOR"
7523 [(const_int 0)]
7524 {
7525 rs6000_split_logical (operands, XOR, true, false, false);
7526 DONE;
7527 }
7528 [(set_attr "type" "integer")
7529 (set (attr "length")
7530 (if_then_else
7531 (match_test "TARGET_POWERPC64")
7532 (const_string "8")
7533 (const_string "16")))])
7535 ;; 128-bit one's complement
7536 (define_insn_and_split "*one_cmpl<mode>3_internal"
7537 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7538 (not:BOOL_128
7539 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7540 ""
7541 {
7542 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7543 return "xxlnor %x0,%x1,%x1";
7545 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7546 return "vnor %0,%1,%1";
7548 return "#";
7549 }
7550 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7551 [(const_int 0)]
7552 {
7553 rs6000_split_logical (operands, NOT, false, false, false);
7554 DONE;
7555 }
7556 [(set (attr "type")
7557 (if_then_else
7558 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7559 (const_string "vecsimple")
7560 (const_string "integer")))
7561 (set (attr "length")
7562 (if_then_else
7563 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7564 (const_string "4")
7565 (if_then_else
7566 (match_test "TARGET_POWERPC64")
7567 (const_string "8")
7568 (const_string "16"))))])
7570 \f
7571 ;; Now define ways of moving data around.
7573 ;; Set up a register with a value from the GOT table
7575 (define_expand "movsi_got"
7576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7577 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7578 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7579 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7580 "
7581 {
7582 if (GET_CODE (operands[1]) == CONST)
7583 {
7584 rtx offset = const0_rtx;
7585 HOST_WIDE_INT value;
7587 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7588 value = INTVAL (offset);
7589 if (value != 0)
7590 {
7591 rtx tmp = (!can_create_pseudo_p ()
7592 ? operands[0]
7593 : gen_reg_rtx (Pmode));
7594 emit_insn (gen_movsi_got (tmp, operands[1]));
7595 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7596 DONE;
7597 }
7598 }
7600 operands[2] = rs6000_got_register (operands[1]);
7601 }")
7603 (define_insn "*movsi_got_internal"
7604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7605 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7606 (match_operand:SI 2 "gpc_reg_operand" "b")]
7607 UNSPEC_MOVSI_GOT))]
7608 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7609 "lwz %0,%a1@got(%2)"
7610 [(set_attr "type" "load")])
7612 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7613 ;; didn't get allocated to a hard register.
7614 (define_split
7615 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7616 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7617 (match_operand:SI 2 "memory_operand" "")]
7618 UNSPEC_MOVSI_GOT))]
7619 "DEFAULT_ABI == ABI_V4
7620 && flag_pic == 1
7621 && (reload_in_progress || reload_completed)"
7622 [(set (match_dup 0) (match_dup 2))
7623 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7624 UNSPEC_MOVSI_GOT))]
7625 "")
7627 ;; For SI, we special-case integers that can't be loaded in one insn. We
7628 ;; do the load 16-bits at a time. We could do this by loading from memory,
7629 ;; and this is even supposed to be faster, but it is simpler not to get
7630 ;; integers in the TOC.
7631 (define_insn "movsi_low"
7632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7633 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7634 (match_operand 2 "" ""))))]
7635 "TARGET_MACHO && ! TARGET_64BIT"
7636 "lwz %0,lo16(%2)(%1)"
7637 [(set_attr "type" "load")
7638 (set_attr "length" "4")])
7640 (define_insn "*movsi_internal1"
7641 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7642 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7643 "!TARGET_SINGLE_FPU &&
7644 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7645 "@
7646 mr %0,%1
7647 la %0,%a1
7648 lwz%U1%X1 %0,%1
7649 stw%U0%X0 %1,%0
7650 li %0,%1
7651 lis %0,%v1
7652 #
7653 mf%1 %0
7654 mt%0 %1
7655 mt%0 %1
7656 nop"
7657 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7658 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7660 (define_insn "*movsi_internal1_single"
7661 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7662 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7663 "TARGET_SINGLE_FPU &&
7664 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7665 "@
7666 mr %0,%1
7667 la %0,%a1
7668 lwz%U1%X1 %0,%1
7669 stw%U0%X0 %1,%0
7670 li %0,%1
7671 lis %0,%v1
7672 #
7673 mf%1 %0
7674 mt%0 %1
7675 mt%0 %1
7676 nop
7677 stfs%U0%X0 %1,%0
7678 lfs%U1%X1 %0,%1"
7679 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7680 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7682 ;; Split a load of a large constant into the appropriate two-insn
7683 ;; sequence.
7685 (define_split
7686 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7687 (match_operand:SI 1 "const_int_operand" ""))]
7688 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7689 && (INTVAL (operands[1]) & 0xffff) != 0"
7690 [(set (match_dup 0)
7691 (match_dup 2))
7692 (set (match_dup 0)
7693 (ior:SI (match_dup 0)
7694 (match_dup 3)))]
7695 "
7696 {
7697 if (rs6000_emit_set_const (operands[0], operands[1]))
7698 DONE;
7699 else
7700 FAIL;
7701 }")
7703 (define_insn "*mov<mode>_internal2"
7704 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7705 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7706 (const_int 0)))
7707 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7708 ""
7709 "@
7710 cmp<wd>i %2,%0,0
7711 mr. %0,%1
7712 #"
7713 [(set_attr "type" "cmp,logical,cmp")
7714 (set_attr "dot" "yes")
7715 (set_attr "length" "4,4,8")])
7717 (define_split
7718 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7719 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7720 (const_int 0)))
7721 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7722 "reload_completed"
7723 [(set (match_dup 0) (match_dup 1))
7724 (set (match_dup 2)
7725 (compare:CC (match_dup 0)
7726 (const_int 0)))]
7727 "")
7728 \f
7729 (define_insn "*movhi_internal"
7730 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7731 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7732 "gpc_reg_operand (operands[0], HImode)
7733 || gpc_reg_operand (operands[1], HImode)"
7734 "@
7735 mr %0,%1
7736 lhz%U1%X1 %0,%1
7737 sth%U0%X0 %1,%0
7738 li %0,%w1
7739 mf%1 %0
7740 mt%0 %1
7741 nop"
7742 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7744 (define_expand "mov<mode>"
7745 [(set (match_operand:INT 0 "general_operand" "")
7746 (match_operand:INT 1 "any_operand" ""))]
7747 ""
7748 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7750 (define_insn "*movqi_internal"
7751 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7752 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7753 "gpc_reg_operand (operands[0], QImode)
7754 || gpc_reg_operand (operands[1], QImode)"
7755 "@
7756 mr %0,%1
7757 lbz%U1%X1 %0,%1
7758 stb%U0%X0 %1,%0
7759 li %0,%1
7760 mf%1 %0
7761 mt%0 %1
7762 nop"
7763 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7764 \f
7765 ;; Here is how to move condition codes around. When we store CC data in
7766 ;; an integer register or memory, we store just the high-order 4 bits.
7767 ;; This lets us not shift in the most common case of CR0.
7768 (define_expand "movcc"
7769 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7770 (match_operand:CC 1 "nonimmediate_operand" ""))]
7771 ""
7772 "")
7774 (define_insn "*movcc_internal1"
7775 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7776 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7777 "register_operand (operands[0], CCmode)
7778 || register_operand (operands[1], CCmode)"
7779 "@
7780 mcrf %0,%1
7781 mtcrf 128,%1
7782 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7783 crxor %0,%0,%0
7784 mfcr %0%Q1
7785 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7786 mr %0,%1
7787 li %0,%1
7788 mf%1 %0
7789 mt%0 %1
7790 lwz%U1%X1 %0,%1
7791 stw%U0%X0 %1,%0"
7792 [(set (attr "type")
7793 (cond [(eq_attr "alternative" "0,3")
7794 (const_string "cr_logical")
7795 (eq_attr "alternative" "1,2")
7796 (const_string "mtcr")
7797 (eq_attr "alternative" "6,7")
7798 (const_string "integer")
7799 (eq_attr "alternative" "8")
7800 (const_string "mfjmpr")
7801 (eq_attr "alternative" "9")
7802 (const_string "mtjmpr")
7803 (eq_attr "alternative" "10")
7804 (const_string "load")
7805 (eq_attr "alternative" "11")
7806 (const_string "store")
7807 (match_test "TARGET_MFCRF")
7808 (const_string "mfcrf")
7809 ]
7810 (const_string "mfcr")))
7811 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7812 \f
7813 ;; For floating-point, we normally deal with the floating-point registers
7814 ;; unless -msoft-float is used. The sole exception is that parameter passing
7815 ;; can produce floating-point values in fixed-point registers. Unless the
7816 ;; value is a simple constant or already in memory, we deal with this by
7817 ;; allocating memory and copying the value explicitly via that memory location.
7819 ;; Move 32-bit binary/decimal floating point
7820 (define_expand "mov<mode>"
7821 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7822 (match_operand:FMOVE32 1 "any_operand" ""))]
7823 "<fmove_ok>"
7824 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7826 (define_split
7827 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7828 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7829 "reload_completed
7830 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7831 || (GET_CODE (operands[0]) == SUBREG
7832 && GET_CODE (SUBREG_REG (operands[0])) == REG
7833 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7834 [(set (match_dup 2) (match_dup 3))]
7835 "
7836 {
7837 long l;
7838 REAL_VALUE_TYPE rv;
7840 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7841 <real_value_to_target> (rv, l);
7843 if (! TARGET_POWERPC64)
7844 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7845 else
7846 operands[2] = gen_lowpart (SImode, operands[0]);
7848 operands[3] = gen_int_mode (l, SImode);
7849 }")
7851 (define_insn "mov<mode>_hardfloat"
7852 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7853 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
7854 "(gpc_reg_operand (operands[0], <MODE>mode)
7855 || gpc_reg_operand (operands[1], <MODE>mode))
7856 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7857 "@
7858 mr %0,%1
7859 lwz%U1%X1 %0,%1
7860 stw%U0%X0 %1,%0
7861 fmr %0,%1
7862 xxlor %x0,%x1,%x1
7863 xxlxor %x0,%x0,%x0
7864 <f32_li>
7865 <f32_si>
7866 <f32_lv>
7867 <f32_sv>
7868 mtvsrwz %x0,%1
7869 mfvsrwz %0,%x1
7870 mt%0 %1
7871 mf%1 %0
7872 nop
7873 #
7874 #"
7875 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7876 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7878 (define_insn "*mov<mode>_softfloat"
7879 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7880 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7881 "(gpc_reg_operand (operands[0], <MODE>mode)
7882 || gpc_reg_operand (operands[1], <MODE>mode))
7883 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7884 "@
7885 mr %0,%1
7886 mt%0 %1
7887 mf%1 %0
7888 lwz%U1%X1 %0,%1
7889 stw%U0%X0 %1,%0
7890 li %0,%1
7891 lis %0,%v1
7892 #
7893 #
7894 nop"
7895 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7896 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7898 \f
7899 ;; Move 64-bit binary/decimal floating point
7900 (define_expand "mov<mode>"
7901 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7902 (match_operand:FMOVE64 1 "any_operand" ""))]
7903 ""
7904 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7906 (define_split
7907 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7908 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7909 "! TARGET_POWERPC64 && reload_completed
7910 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7911 || (GET_CODE (operands[0]) == SUBREG
7912 && GET_CODE (SUBREG_REG (operands[0])) == REG
7913 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7914 [(set (match_dup 2) (match_dup 4))
7915 (set (match_dup 3) (match_dup 1))]
7916 "
7917 {
7918 int endian = (WORDS_BIG_ENDIAN == 0);
7919 HOST_WIDE_INT value = INTVAL (operands[1]);
7921 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7922 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7923 operands[4] = GEN_INT (value >> 32);
7924 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7925 }")
7927 (define_split
7928 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7929 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7930 "! TARGET_POWERPC64 && reload_completed
7931 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7932 || (GET_CODE (operands[0]) == SUBREG
7933 && GET_CODE (SUBREG_REG (operands[0])) == REG
7934 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7935 [(set (match_dup 2) (match_dup 4))
7936 (set (match_dup 3) (match_dup 5))]
7937 "
7938 {
7939 int endian = (WORDS_BIG_ENDIAN == 0);
7940 long l[2];
7941 REAL_VALUE_TYPE rv;
7943 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7944 <real_value_to_target> (rv, l);
7946 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7947 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7948 operands[4] = gen_int_mode (l[endian], SImode);
7949 operands[5] = gen_int_mode (l[1 - endian], SImode);
7950 }")
7952 (define_split
7953 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7954 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7955 "TARGET_POWERPC64 && reload_completed
7956 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7957 || (GET_CODE (operands[0]) == SUBREG
7958 && GET_CODE (SUBREG_REG (operands[0])) == REG
7959 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7960 [(set (match_dup 2) (match_dup 3))]
7961 "
7962 {
7963 int endian = (WORDS_BIG_ENDIAN == 0);
7964 long l[2];
7965 REAL_VALUE_TYPE rv;
7966 HOST_WIDE_INT val;
7968 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7969 <real_value_to_target> (rv, l);
7971 operands[2] = gen_lowpart (DImode, operands[0]);
7972 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7973 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7974 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7976 operands[3] = gen_int_mode (val, DImode);
7977 }")
7979 ;; Don't have reload use general registers to load a constant. It is
7980 ;; less efficient than loading the constant into an FP register, since
7981 ;; it will probably be used there.
7983 ;; The move constraints are ordered to prefer floating point registers before
7984 ;; general purpose registers to avoid doing a store and a load to get the value
7985 ;; into a floating point register when it is needed for a floating point
7986 ;; operation. Prefer traditional floating point registers over VSX registers,
7987 ;; since the D-form version of the memory instructions does not need a GPR for
7988 ;; reloading.
7990 (define_insn "*mov<mode>_hardfloat32"
7991 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
7992 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
7993 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7994 && (gpc_reg_operand (operands[0], <MODE>mode)
7995 || gpc_reg_operand (operands[1], <MODE>mode))"
7996 "@
7997 stfd%U0%X0 %1,%0
7998 lfd%U1%X1 %0,%1
7999 fmr %0,%1
8000 lxsd%U1x %x0,%y1
8001 stxsd%U0x %x1,%y0
8002 xxlor %x0,%x1,%x1
8003 xxlxor %x0,%x0,%x0
8004 #
8005 #
8006 #
8007 #
8008 #
8009 #"
8010 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8011 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8013 (define_insn "*mov<mode>_softfloat32"
8014 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8015 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8016 "! TARGET_POWERPC64
8017 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8018 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8019 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8020 && (gpc_reg_operand (operands[0], <MODE>mode)
8021 || gpc_reg_operand (operands[1], <MODE>mode))"
8022 "#"
8023 [(set_attr "type" "store,load,two,*,*,*")
8024 (set_attr "length" "8,8,8,8,12,16")])
8026 ; ld/std require word-aligned displacements -> 'Y' constraint.
8027 ; List Y->r and r->Y before r->r for reload.
8028 (define_insn "*mov<mode>_hardfloat64"
8029 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
8030 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
8031 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8032 && (gpc_reg_operand (operands[0], <MODE>mode)
8033 || gpc_reg_operand (operands[1], <MODE>mode))"
8034 "@
8035 stfd%U0%X0 %1,%0
8036 lfd%U1%X1 %0,%1
8037 fmr %0,%1
8038 lxsd%U1x %x0,%y1
8039 stxsd%U0x %x1,%y0
8040 xxlor %x0,%x1,%x1
8041 xxlxor %x0,%x0,%x0
8042 std%U0%X0 %1,%0
8043 ld%U1%X1 %0,%1
8044 mr %0,%1
8045 mt%0 %1
8046 mf%1 %0
8047 nop
8048 #
8049 #
8050 #
8051 mftgpr %0,%1
8052 mffgpr %0,%1
8053 mfvsrd %0,%x1
8054 mtvsrd %x0,%1"
8055 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8056 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8058 (define_insn "*mov<mode>_softfloat64"
8059 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8060 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8061 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8062 && (gpc_reg_operand (operands[0], <MODE>mode)
8063 || gpc_reg_operand (operands[1], <MODE>mode))"
8064 "@
8065 std%U0%X0 %1,%0
8066 ld%U1%X1 %0,%1
8067 mr %0,%1
8068 mt%0 %1
8069 mf%1 %0
8070 #
8071 #
8072 #
8073 nop"
8074 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8075 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8076 \f
8077 (define_expand "mov<mode>"
8078 [(set (match_operand:FMOVE128 0 "general_operand" "")
8079 (match_operand:FMOVE128 1 "any_operand" ""))]
8080 ""
8081 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8083 ;; It's important to list Y->r and r->Y before r->r because otherwise
8084 ;; reload, given m->r, will try to pick r->r and reload it, which
8085 ;; doesn't make progress.
8087 ;; We can't split little endian direct moves of TDmode, because the words are
8088 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8089 ;; problematical. Don't allow direct move for this case.
8091 (define_insn_and_split "*mov<mode>_64bit_dm"
8092 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8093 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8094 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8095 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8096 && (gpc_reg_operand (operands[0], <MODE>mode)
8097 || gpc_reg_operand (operands[1], <MODE>mode))"
8098 "#"
8099 "&& reload_completed"
8100 [(pc)]
8101 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8102 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8104 (define_insn_and_split "*movtd_64bit_nodm"
8105 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8106 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8107 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8108 && (gpc_reg_operand (operands[0], TDmode)
8109 || gpc_reg_operand (operands[1], TDmode))"
8110 "#"
8111 "&& reload_completed"
8112 [(pc)]
8113 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8114 [(set_attr "length" "8,8,8,12,12,8")])
8116 (define_insn_and_split "*mov<mode>_32bit"
8117 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8118 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8119 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8120 && (gpc_reg_operand (operands[0], <MODE>mode)
8121 || gpc_reg_operand (operands[1], <MODE>mode))"
8122 "#"
8123 "&& reload_completed"
8124 [(pc)]
8125 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8126 [(set_attr "length" "8,8,8,20,20,16")])
8128 (define_insn_and_split "*mov<mode>_softfloat"
8129 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8130 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8131 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8132 && (gpc_reg_operand (operands[0], <MODE>mode)
8133 || gpc_reg_operand (operands[1], <MODE>mode))"
8134 "#"
8135 "&& reload_completed"
8136 [(pc)]
8137 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8138 [(set_attr "length" "20,20,16")])
8140 (define_expand "extenddftf2"
8141 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8142 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8143 "!TARGET_IEEEQUAD
8144 && TARGET_HARD_FLOAT
8145 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8146 && TARGET_LONG_DOUBLE_128"
8147 {
8148 if (TARGET_E500_DOUBLE)
8149 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8150 else
8151 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8152 DONE;
8153 })
8155 (define_expand "extenddftf2_fprs"
8156 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8157 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8158 (use (match_dup 2))])]
8159 "!TARGET_IEEEQUAD
8160 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8161 && TARGET_LONG_DOUBLE_128"
8162 {
8163 operands[2] = CONST0_RTX (DFmode);
8164 /* Generate GOT reference early for SVR4 PIC. */
8165 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8166 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8167 })
8169 (define_insn_and_split "*extenddftf2_internal"
8170 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8171 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8172 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8173 "!TARGET_IEEEQUAD
8174 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8175 && TARGET_LONG_DOUBLE_128"
8176 "#"
8177 "&& reload_completed"
8178 [(pc)]
8179 {
8180 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8181 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8182 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8183 operands[1]);
8184 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8185 operands[2]);
8186 DONE;
8187 })
8189 (define_expand "extendsftf2"
8190 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8191 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8192 "!TARGET_IEEEQUAD
8193 && TARGET_HARD_FLOAT
8194 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8195 && TARGET_LONG_DOUBLE_128"
8196 {
8197 rtx tmp = gen_reg_rtx (DFmode);
8198 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8199 emit_insn (gen_extenddftf2 (operands[0], tmp));
8200 DONE;
8201 })
8203 (define_expand "trunctfdf2"
8204 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8205 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8206 "!TARGET_IEEEQUAD
8207 && TARGET_HARD_FLOAT
8208 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8209 && TARGET_LONG_DOUBLE_128"
8210 "")
8212 (define_insn_and_split "trunctfdf2_internal1"
8213 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8214 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8215 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8216 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8217 "@
8218 #
8219 fmr %0,%1"
8220 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8221 [(const_int 0)]
8222 {
8223 emit_note (NOTE_INSN_DELETED);
8224 DONE;
8225 }
8226 [(set_attr "type" "fp")])
8228 (define_insn "trunctfdf2_internal2"
8229 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8230 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8231 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8232 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8233 && TARGET_LONG_DOUBLE_128"
8234 "fadd %0,%1,%L1"
8235 [(set_attr "type" "fp")
8236 (set_attr "fp_type" "fp_addsub_d")])
8238 (define_expand "trunctfsf2"
8239 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8240 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8241 "!TARGET_IEEEQUAD
8242 && TARGET_HARD_FLOAT
8243 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8244 && TARGET_LONG_DOUBLE_128"
8245 {
8246 if (TARGET_E500_DOUBLE)
8247 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8248 else
8249 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8250 DONE;
8251 })
8253 (define_insn_and_split "trunctfsf2_fprs"
8254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8255 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8256 (clobber (match_scratch:DF 2 "=d"))]
8257 "!TARGET_IEEEQUAD
8258 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8259 && TARGET_LONG_DOUBLE_128"
8260 "#"
8261 "&& reload_completed"
8262 [(set (match_dup 2)
8263 (float_truncate:DF (match_dup 1)))
8264 (set (match_dup 0)
8265 (float_truncate:SF (match_dup 2)))]
8266 "")
8268 (define_expand "floatsitf2"
8269 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8270 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8271 "!TARGET_IEEEQUAD
8272 && TARGET_HARD_FLOAT
8273 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8274 && TARGET_LONG_DOUBLE_128"
8275 {
8276 rtx tmp = gen_reg_rtx (DFmode);
8277 expand_float (tmp, operands[1], false);
8278 emit_insn (gen_extenddftf2 (operands[0], tmp));
8279 DONE;
8280 })
8282 ; fadd, but rounding towards zero.
8283 ; This is probably not the optimal code sequence.
8284 (define_insn "fix_trunc_helper"
8285 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8286 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8287 UNSPEC_FIX_TRUNC_TF))
8288 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8289 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8290 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8291 [(set_attr "type" "fp")
8292 (set_attr "length" "20")])
8294 (define_expand "fix_trunctfsi2"
8295 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8296 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8297 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8298 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8299 {
8300 if (TARGET_E500_DOUBLE)
8301 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8302 else
8303 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8304 DONE;
8305 })
8307 (define_expand "fix_trunctfsi2_fprs"
8308 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8309 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8310 (clobber (match_dup 2))
8311 (clobber (match_dup 3))
8312 (clobber (match_dup 4))
8313 (clobber (match_dup 5))])]
8314 "!TARGET_IEEEQUAD
8315 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8316 {
8317 operands[2] = gen_reg_rtx (DFmode);
8318 operands[3] = gen_reg_rtx (DFmode);
8319 operands[4] = gen_reg_rtx (DImode);
8320 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8321 })
8323 (define_insn_and_split "*fix_trunctfsi2_internal"
8324 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8325 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8326 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8327 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8328 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8329 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8330 "!TARGET_IEEEQUAD
8331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8332 "#"
8333 ""
8334 [(pc)]
8335 {
8336 rtx lowword;
8337 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8339 gcc_assert (MEM_P (operands[5]));
8340 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8342 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8343 emit_move_insn (operands[5], operands[4]);
8344 emit_move_insn (operands[0], lowword);
8345 DONE;
8346 })
8348 (define_expand "negtf2"
8349 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8350 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8351 "!TARGET_IEEEQUAD
8352 && TARGET_HARD_FLOAT
8353 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8354 && TARGET_LONG_DOUBLE_128"
8355 "")
8357 (define_insn "negtf2_internal"
8358 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8359 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8360 "!TARGET_IEEEQUAD
8361 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8362 "*
8363 {
8364 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8365 return \"fneg %L0,%L1\;fneg %0,%1\";
8366 else
8367 return \"fneg %0,%1\;fneg %L0,%L1\";
8368 }"
8369 [(set_attr "type" "fp")
8370 (set_attr "length" "8")])
8372 (define_expand "abstf2"
8373 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8374 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8375 "!TARGET_IEEEQUAD
8376 && TARGET_HARD_FLOAT
8377 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8378 && TARGET_LONG_DOUBLE_128"
8379 "
8380 {
8381 rtx label = gen_label_rtx ();
8382 if (TARGET_E500_DOUBLE)
8383 {
8384 if (flag_finite_math_only && !flag_trapping_math)
8385 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8386 else
8387 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8388 }
8389 else
8390 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8391 emit_label (label);
8392 DONE;
8393 }")
8395 (define_expand "abstf2_internal"
8396 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8397 (match_operand:TF 1 "gpc_reg_operand" ""))
8398 (set (match_dup 3) (match_dup 5))
8399 (set (match_dup 5) (abs:DF (match_dup 5)))
8400 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8401 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8402 (label_ref (match_operand 2 "" ""))
8403 (pc)))
8404 (set (match_dup 6) (neg:DF (match_dup 6)))]
8405 "!TARGET_IEEEQUAD
8406 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8407 && TARGET_LONG_DOUBLE_128"
8408 "
8409 {
8410 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8411 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8412 operands[3] = gen_reg_rtx (DFmode);
8413 operands[4] = gen_reg_rtx (CCFPmode);
8414 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8415 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8416 }")
8417 \f
8418 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8419 ;; must have 3 arguments, and scratch register constraint must be a single
8420 ;; constraint.
8422 ;; Reload patterns to support gpr load/store with misaligned mem.
8423 ;; and multiple gpr load/store at offset >= 0xfffc
8424 (define_expand "reload_<mode>_store"
8425 [(parallel [(match_operand 0 "memory_operand" "=m")
8426 (match_operand 1 "gpc_reg_operand" "r")
8427 (match_operand:GPR 2 "register_operand" "=&b")])]
8428 ""
8429 {
8430 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8431 DONE;
8432 })
8434 (define_expand "reload_<mode>_load"
8435 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8436 (match_operand 1 "memory_operand" "m")
8437 (match_operand:GPR 2 "register_operand" "=b")])]
8438 ""
8439 {
8440 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8441 DONE;
8442 })
8444 \f
8445 ;; Power8 merge instructions to allow direct move to/from floating point
8446 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8447 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8448 ;; value, since it is allocated in reload and not all of the flow information
8449 ;; is setup for it. We have two patterns to do the two moves between gprs and
8450 ;; fprs. There isn't a dependancy between the two, but we could potentially
8451 ;; schedule other instructions between the two instructions. TFmode is
8452 ;; currently limited to traditional FPR registers. If/when this is changed, we
8453 ;; will need to revist %L to make sure it works with VSX registers, or add an
8454 ;; %x version of %L.
8456 (define_insn "p8_fmrgow_<mode>"
8457 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8458 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8459 UNSPEC_P8V_FMRGOW))]
8460 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8461 "fmrgow %0,%1,%L1"
8462 [(set_attr "type" "vecperm")])
8464 (define_insn "p8_mtvsrwz_1"
8465 [(set (match_operand:TF 0 "register_operand" "=d")
8466 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8467 UNSPEC_P8V_MTVSRWZ))]
8468 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8469 "mtvsrwz %x0,%1"
8470 [(set_attr "type" "mftgpr")])
8472 (define_insn "p8_mtvsrwz_2"
8473 [(set (match_operand:TF 0 "register_operand" "+d")
8474 (unspec:TF [(match_dup 0)
8475 (match_operand:SI 1 "register_operand" "r")]
8476 UNSPEC_P8V_MTVSRWZ))]
8477 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8478 "mtvsrwz %L0,%1"
8479 [(set_attr "type" "mftgpr")])
8481 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8482 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8483 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8484 UNSPEC_P8V_RELOAD_FROM_GPR))
8485 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8486 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8487 "#"
8488 "&& reload_completed"
8489 [(const_int 0)]
8490 {
8491 rtx dest = operands[0];
8492 rtx src = operands[1];
8493 rtx tmp = operands[2];
8494 rtx gpr_hi_reg = gen_highpart (SImode, src);
8495 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8497 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8498 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8499 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8500 DONE;
8501 }
8502 [(set_attr "length" "12")
8503 (set_attr "type" "three")])
8505 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8506 (define_insn "p8_mtvsrd_1"
8507 [(set (match_operand:TF 0 "register_operand" "=ws")
8508 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8509 UNSPEC_P8V_MTVSRD))]
8510 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8511 "mtvsrd %0,%1"
8512 [(set_attr "type" "mftgpr")])
8514 (define_insn "p8_mtvsrd_2"
8515 [(set (match_operand:TF 0 "register_operand" "+ws")
8516 (unspec:TF [(match_dup 0)
8517 (match_operand:DI 1 "register_operand" "r")]
8518 UNSPEC_P8V_MTVSRD))]
8519 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8520 "mtvsrd %L0,%1"
8521 [(set_attr "type" "mftgpr")])
8523 (define_insn "p8_xxpermdi_<mode>"
8524 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8525 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8526 UNSPEC_P8V_XXPERMDI))]
8527 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8528 "xxpermdi %x0,%1,%L1,0"
8529 [(set_attr "type" "vecperm")])
8531 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8532 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8533 (unspec:FMOVE128_GPR
8534 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8535 UNSPEC_P8V_RELOAD_FROM_GPR))
8536 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8537 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8538 "#"
8539 "&& reload_completed"
8540 [(const_int 0)]
8541 {
8542 rtx dest = operands[0];
8543 rtx src = operands[1];
8544 rtx tmp = operands[2];
8545 rtx gpr_hi_reg = gen_highpart (DImode, src);
8546 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8548 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8549 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8550 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8551 }
8552 [(set_attr "length" "12")
8553 (set_attr "type" "three")])
8555 (define_split
8556 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8557 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8558 "reload_completed
8559 && (int_reg_operand (operands[0], <MODE>mode)
8560 || int_reg_operand (operands[1], <MODE>mode))"
8561 [(pc)]
8562 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8564 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8565 ;; type is stored internally as double precision in the VSX registers, we have
8566 ;; to convert it from the vector format.
8568 (define_insn_and_split "reload_vsx_from_gprsf"
8569 [(set (match_operand:SF 0 "register_operand" "=wa")
8570 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8571 UNSPEC_P8V_RELOAD_FROM_GPR))
8572 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8573 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8574 "#"
8575 "&& reload_completed"
8576 [(const_int 0)]
8577 {
8578 rtx op0 = operands[0];
8579 rtx op1 = operands[1];
8580 rtx op2 = operands[2];
8581 /* Also use the destination register to hold the unconverted DImode value.
8582 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8583 rather than simplify_gen_subreg. */
8584 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8585 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8587 /* Move SF value to upper 32-bits for xscvspdpn. */
8588 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8589 emit_move_insn (op0_di, op2);
8590 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8591 DONE;
8592 }
8593 [(set_attr "length" "8")
8594 (set_attr "type" "two")])
8596 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8597 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8598 ;; and then doing a move of that.
8599 (define_insn "p8_mfvsrd_3_<mode>"
8600 [(set (match_operand:DF 0 "register_operand" "=r")
8601 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8602 UNSPEC_P8V_RELOAD_FROM_VSX))]
8603 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8604 "mfvsrd %0,%x1"
8605 [(set_attr "type" "mftgpr")])
8607 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8608 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8609 (unspec:FMOVE128_GPR
8610 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8611 UNSPEC_P8V_RELOAD_FROM_VSX))
8612 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8613 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8614 "#"
8615 "&& reload_completed"
8616 [(const_int 0)]
8617 {
8618 rtx dest = operands[0];
8619 rtx src = operands[1];
8620 rtx tmp = operands[2];
8621 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8622 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8624 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8625 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8626 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8627 }
8628 [(set_attr "length" "12")
8629 (set_attr "type" "three")])
8631 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8632 ;; type is stored internally as double precision, we have to convert it to the
8633 ;; vector format.
8635 (define_insn_and_split "reload_gpr_from_vsxsf"
8636 [(set (match_operand:SF 0 "register_operand" "=r")
8637 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8638 UNSPEC_P8V_RELOAD_FROM_VSX))
8639 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8640 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8641 "#"
8642 "&& reload_completed"
8643 [(const_int 0)]
8644 {
8645 rtx op0 = operands[0];
8646 rtx op1 = operands[1];
8647 rtx op2 = operands[2];
8648 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8650 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8651 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8652 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8653 DONE;
8654 }
8655 [(set_attr "length" "12")
8656 (set_attr "type" "three")])
8658 (define_insn "p8_mfvsrd_4_disf"
8659 [(set (match_operand:DI 0 "register_operand" "=r")
8660 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8661 UNSPEC_P8V_RELOAD_FROM_VSX))]
8662 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8663 "mfvsrd %0,%x1"
8664 [(set_attr "type" "mftgpr")])
8666 \f
8667 ;; Next come the multi-word integer load and store and the load and store
8668 ;; multiple insns.
8670 ;; List r->r after r->Y, otherwise reload will try to reload a
8671 ;; non-offsettable address by using r->r which won't make progress.
8672 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8673 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8674 (define_insn "*movdi_internal32"
8675 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8676 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8677 "! TARGET_POWERPC64
8678 && (gpc_reg_operand (operands[0], DImode)
8679 || gpc_reg_operand (operands[1], DImode))"
8680 "@
8681 #
8682 #
8683 #
8684 stfd%U0%X0 %1,%0
8685 lfd%U1%X1 %0,%1
8686 fmr %0,%1
8687 #"
8688 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8690 (define_split
8691 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8692 (match_operand:DI 1 "const_int_operand" ""))]
8693 "! TARGET_POWERPC64 && reload_completed
8694 && gpr_or_gpr_p (operands[0], operands[1])
8695 && !direct_move_p (operands[0], operands[1])"
8696 [(set (match_dup 2) (match_dup 4))
8697 (set (match_dup 3) (match_dup 1))]
8698 "
8699 {
8700 HOST_WIDE_INT value = INTVAL (operands[1]);
8701 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8702 DImode);
8703 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8704 DImode);
8705 operands[4] = GEN_INT (value >> 32);
8706 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8707 }")
8709 (define_split
8710 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8711 (match_operand:DIFD 1 "input_operand" ""))]
8712 "reload_completed && !TARGET_POWERPC64
8713 && gpr_or_gpr_p (operands[0], operands[1])
8714 && !direct_move_p (operands[0], operands[1])"
8715 [(pc)]
8716 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8718 (define_insn "*movdi_internal64"
8719 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8720 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8721 "TARGET_POWERPC64
8722 && (gpc_reg_operand (operands[0], DImode)
8723 || gpc_reg_operand (operands[1], DImode))"
8724 "@
8725 std%U0%X0 %1,%0
8726 ld%U1%X1 %0,%1
8727 mr %0,%1
8728 li %0,%1
8729 lis %0,%v1
8730 #
8731 stfd%U0%X0 %1,%0
8732 lfd%U1%X1 %0,%1
8733 fmr %0,%1
8734 mf%1 %0
8735 mt%0 %1
8736 nop
8737 mftgpr %0,%1
8738 mffgpr %0,%1
8739 mfvsrd %0,%x1
8740 mtvsrd %x0,%1
8741 xxlxor %x0,%x0,%x0"
8742 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8743 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8745 ;; Generate all one-bits and clear left or right.
8746 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8747 (define_split
8748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8749 (match_operand:DI 1 "mask64_operand" ""))]
8750 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8751 [(set (match_dup 0) (const_int -1))
8752 (set (match_dup 0)
8753 (and:DI (rotate:DI (match_dup 0)
8754 (const_int 0))
8755 (match_dup 1)))]
8756 "")
8758 ;; Split a load of a large constant into the appropriate five-instruction
8759 ;; sequence. Handle anything in a constant number of insns.
8760 ;; When non-easy constants can go in the TOC, this should use
8761 ;; easy_fp_constant predicate.
8762 (define_split
8763 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8764 (match_operand:DI 1 "const_int_operand" ""))]
8765 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8766 [(set (match_dup 0) (match_dup 2))
8767 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8768 "
8769 {
8770 if (rs6000_emit_set_const (operands[0], operands[1]))
8771 DONE;
8772 else
8773 FAIL;
8774 }")
8776 (define_split
8777 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8778 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8779 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8780 [(set (match_dup 0) (match_dup 2))
8781 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8782 "
8783 {
8784 if (rs6000_emit_set_const (operands[0], operands[1]))
8785 DONE;
8786 else
8787 FAIL;
8788 }")
8789 \f
8790 ;; TImode/PTImode is similar, except that we usually want to compute the
8791 ;; address into a register and use lsi/stsi (the exception is during reload).
8793 (define_insn "*mov<mode>_string"
8794 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8795 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8796 "! TARGET_POWERPC64
8797 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8798 && (gpc_reg_operand (operands[0], <MODE>mode)
8799 || gpc_reg_operand (operands[1], <MODE>mode))"
8800 "*
8801 {
8802 switch (which_alternative)
8803 {
8804 default:
8805 gcc_unreachable ();
8806 case 0:
8807 if (TARGET_STRING)
8808 return \"stswi %1,%P0,16\";
8809 case 1:
8810 return \"#\";
8811 case 2:
8812 /* If the address is not used in the output, we can use lsi. Otherwise,
8813 fall through to generating four loads. */
8814 if (TARGET_STRING
8815 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8816 return \"lswi %0,%P1,16\";
8817 /* ... fall through ... */
8818 case 3:
8819 case 4:
8820 case 5:
8821 return \"#\";
8822 }
8823 }"
8824 [(set_attr "type" "store,store,load,load,*,*")
8825 (set_attr "update" "yes")
8826 (set_attr "indexed" "yes")
8827 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8828 (const_string "always")
8829 (const_string "conditional")))])
8831 (define_insn "*mov<mode>_ppc64"
8832 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8833 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8834 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8835 && (gpc_reg_operand (operands[0], <MODE>mode)
8836 || gpc_reg_operand (operands[1], <MODE>mode)))"
8837 {
8838 return rs6000_output_move_128bit (operands);
8839 }
8840 [(set_attr "type" "store,store,load,load,*,*")
8841 (set_attr "length" "8")])
8843 (define_split
8844 [(set (match_operand:TI2 0 "int_reg_operand" "")
8845 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8846 "TARGET_POWERPC64
8847 && (VECTOR_MEM_NONE_P (<MODE>mode)
8848 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8849 [(set (match_dup 2) (match_dup 4))
8850 (set (match_dup 3) (match_dup 5))]
8851 "
8852 {
8853 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8854 <MODE>mode);
8855 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8856 <MODE>mode);
8857 if (CONST_WIDE_INT_P (operands[1]))
8858 {
8859 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8860 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8861 }
8862 else if (CONST_INT_P (operands[1]))
8863 {
8864 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8865 operands[5] = operands[1];
8866 }
8867 else
8868 FAIL;
8869 }")
8871 (define_split
8872 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8873 (match_operand:TI2 1 "input_operand" ""))]
8874 "reload_completed
8875 && gpr_or_gpr_p (operands[0], operands[1])
8876 && !direct_move_p (operands[0], operands[1])
8877 && !quad_load_store_p (operands[0], operands[1])"
8878 [(pc)]
8879 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8880 \f
8881 (define_expand "load_multiple"
8882 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8883 (match_operand:SI 1 "" ""))
8884 (use (match_operand:SI 2 "" ""))])]
8885 "TARGET_STRING && !TARGET_POWERPC64"
8886 "
8887 {
8888 int regno;
8889 int count;
8890 rtx op1;
8891 int i;
8893 /* Support only loading a constant number of fixed-point registers from
8894 memory and only bother with this if more than two; the machine
8895 doesn't support more than eight. */
8896 if (GET_CODE (operands[2]) != CONST_INT
8897 || INTVAL (operands[2]) <= 2
8898 || INTVAL (operands[2]) > 8
8899 || GET_CODE (operands[1]) != MEM
8900 || GET_CODE (operands[0]) != REG
8901 || REGNO (operands[0]) >= 32)
8902 FAIL;
8904 count = INTVAL (operands[2]);
8905 regno = REGNO (operands[0]);
8907 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8908 op1 = replace_equiv_address (operands[1],
8909 force_reg (SImode, XEXP (operands[1], 0)));
8911 for (i = 0; i < count; i++)
8912 XVECEXP (operands[3], 0, i)
8913 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8914 adjust_address_nv (op1, SImode, i * 4));
8915 }")
8917 (define_insn "*ldmsi8"
8918 [(match_parallel 0 "load_multiple_operation"
8919 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8920 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8921 (set (match_operand:SI 3 "gpc_reg_operand" "")
8922 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8923 (set (match_operand:SI 4 "gpc_reg_operand" "")
8924 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8925 (set (match_operand:SI 5 "gpc_reg_operand" "")
8926 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8927 (set (match_operand:SI 6 "gpc_reg_operand" "")
8928 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8929 (set (match_operand:SI 7 "gpc_reg_operand" "")
8930 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8931 (set (match_operand:SI 8 "gpc_reg_operand" "")
8932 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8933 (set (match_operand:SI 9 "gpc_reg_operand" "")
8934 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8935 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8936 "*
8937 { return rs6000_output_load_multiple (operands); }"
8938 [(set_attr "type" "load")
8939 (set_attr "update" "yes")
8940 (set_attr "indexed" "yes")
8941 (set_attr "length" "32")])
8943 (define_insn "*ldmsi7"
8944 [(match_parallel 0 "load_multiple_operation"
8945 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8946 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8947 (set (match_operand:SI 3 "gpc_reg_operand" "")
8948 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8949 (set (match_operand:SI 4 "gpc_reg_operand" "")
8950 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8951 (set (match_operand:SI 5 "gpc_reg_operand" "")
8952 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8953 (set (match_operand:SI 6 "gpc_reg_operand" "")
8954 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8955 (set (match_operand:SI 7 "gpc_reg_operand" "")
8956 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8957 (set (match_operand:SI 8 "gpc_reg_operand" "")
8958 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8959 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8960 "*
8961 { return rs6000_output_load_multiple (operands); }"
8962 [(set_attr "type" "load")
8963 (set_attr "update" "yes")
8964 (set_attr "indexed" "yes")
8965 (set_attr "length" "32")])
8967 (define_insn "*ldmsi6"
8968 [(match_parallel 0 "load_multiple_operation"
8969 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8970 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8971 (set (match_operand:SI 3 "gpc_reg_operand" "")
8972 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8973 (set (match_operand:SI 4 "gpc_reg_operand" "")
8974 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8975 (set (match_operand:SI 5 "gpc_reg_operand" "")
8976 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8977 (set (match_operand:SI 6 "gpc_reg_operand" "")
8978 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8979 (set (match_operand:SI 7 "gpc_reg_operand" "")
8980 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8981 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8982 "*
8983 { return rs6000_output_load_multiple (operands); }"
8984 [(set_attr "type" "load")
8985 (set_attr "update" "yes")
8986 (set_attr "indexed" "yes")
8987 (set_attr "length" "32")])
8989 (define_insn "*ldmsi5"
8990 [(match_parallel 0 "load_multiple_operation"
8991 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8992 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8993 (set (match_operand:SI 3 "gpc_reg_operand" "")
8994 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8995 (set (match_operand:SI 4 "gpc_reg_operand" "")
8996 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8997 (set (match_operand:SI 5 "gpc_reg_operand" "")
8998 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8999 (set (match_operand:SI 6 "gpc_reg_operand" "")
9000 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9001 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9002 "*
9003 { return rs6000_output_load_multiple (operands); }"
9004 [(set_attr "type" "load")
9005 (set_attr "update" "yes")
9006 (set_attr "indexed" "yes")
9007 (set_attr "length" "32")])
9009 (define_insn "*ldmsi4"
9010 [(match_parallel 0 "load_multiple_operation"
9011 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9012 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9013 (set (match_operand:SI 3 "gpc_reg_operand" "")
9014 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9015 (set (match_operand:SI 4 "gpc_reg_operand" "")
9016 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9017 (set (match_operand:SI 5 "gpc_reg_operand" "")
9018 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9019 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9020 "*
9021 { return rs6000_output_load_multiple (operands); }"
9022 [(set_attr "type" "load")
9023 (set_attr "update" "yes")
9024 (set_attr "indexed" "yes")
9025 (set_attr "length" "32")])
9027 (define_insn "*ldmsi3"
9028 [(match_parallel 0 "load_multiple_operation"
9029 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9030 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9031 (set (match_operand:SI 3 "gpc_reg_operand" "")
9032 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9033 (set (match_operand:SI 4 "gpc_reg_operand" "")
9034 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9035 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9036 "*
9037 { return rs6000_output_load_multiple (operands); }"
9038 [(set_attr "type" "load")
9039 (set_attr "update" "yes")
9040 (set_attr "indexed" "yes")
9041 (set_attr "length" "32")])
9043 (define_expand "store_multiple"
9044 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9045 (match_operand:SI 1 "" ""))
9046 (clobber (scratch:SI))
9047 (use (match_operand:SI 2 "" ""))])]
9048 "TARGET_STRING && !TARGET_POWERPC64"
9049 "
9050 {
9051 int regno;
9052 int count;
9053 rtx to;
9054 rtx op0;
9055 int i;
9057 /* Support only storing a constant number of fixed-point registers to
9058 memory and only bother with this if more than two; the machine
9059 doesn't support more than eight. */
9060 if (GET_CODE (operands[2]) != CONST_INT
9061 || INTVAL (operands[2]) <= 2
9062 || INTVAL (operands[2]) > 8
9063 || GET_CODE (operands[0]) != MEM
9064 || GET_CODE (operands[1]) != REG
9065 || REGNO (operands[1]) >= 32)
9066 FAIL;
9068 count = INTVAL (operands[2]);
9069 regno = REGNO (operands[1]);
9071 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9072 to = force_reg (SImode, XEXP (operands[0], 0));
9073 op0 = replace_equiv_address (operands[0], to);
9075 XVECEXP (operands[3], 0, 0)
9076 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9077 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9078 gen_rtx_SCRATCH (SImode));
9080 for (i = 1; i < count; i++)
9081 XVECEXP (operands[3], 0, i + 1)
9082 = gen_rtx_SET (VOIDmode,
9083 adjust_address_nv (op0, SImode, i * 4),
9084 gen_rtx_REG (SImode, regno + i));
9085 }")
9087 (define_insn "*stmsi8"
9088 [(match_parallel 0 "store_multiple_operation"
9089 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9090 (match_operand:SI 2 "gpc_reg_operand" "r"))
9091 (clobber (match_scratch:SI 3 "=X"))
9092 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9093 (match_operand:SI 4 "gpc_reg_operand" "r"))
9094 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9095 (match_operand:SI 5 "gpc_reg_operand" "r"))
9096 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9097 (match_operand:SI 6 "gpc_reg_operand" "r"))
9098 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9099 (match_operand:SI 7 "gpc_reg_operand" "r"))
9100 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9101 (match_operand:SI 8 "gpc_reg_operand" "r"))
9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9103 (match_operand:SI 9 "gpc_reg_operand" "r"))
9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9105 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9106 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9107 "stswi %2,%1,%O0"
9108 [(set_attr "type" "store")
9109 (set_attr "update" "yes")
9110 (set_attr "indexed" "yes")
9111 (set_attr "cell_micro" "always")])
9113 (define_insn "*stmsi7"
9114 [(match_parallel 0 "store_multiple_operation"
9115 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9116 (match_operand:SI 2 "gpc_reg_operand" "r"))
9117 (clobber (match_scratch:SI 3 "=X"))
9118 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9119 (match_operand:SI 4 "gpc_reg_operand" "r"))
9120 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9121 (match_operand:SI 5 "gpc_reg_operand" "r"))
9122 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9123 (match_operand:SI 6 "gpc_reg_operand" "r"))
9124 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9125 (match_operand:SI 7 "gpc_reg_operand" "r"))
9126 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9127 (match_operand:SI 8 "gpc_reg_operand" "r"))
9128 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9129 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9130 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9131 "stswi %2,%1,%O0"
9132 [(set_attr "type" "store")
9133 (set_attr "update" "yes")
9134 (set_attr "indexed" "yes")
9135 (set_attr "cell_micro" "always")])
9137 (define_insn "*stmsi6"
9138 [(match_parallel 0 "store_multiple_operation"
9139 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9140 (match_operand:SI 2 "gpc_reg_operand" "r"))
9141 (clobber (match_scratch:SI 3 "=X"))
9142 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9143 (match_operand:SI 4 "gpc_reg_operand" "r"))
9144 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9145 (match_operand:SI 5 "gpc_reg_operand" "r"))
9146 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9147 (match_operand:SI 6 "gpc_reg_operand" "r"))
9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9149 (match_operand:SI 7 "gpc_reg_operand" "r"))
9150 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9151 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9152 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9153 "stswi %2,%1,%O0"
9154 [(set_attr "type" "store")
9155 (set_attr "update" "yes")
9156 (set_attr "indexed" "yes")
9157 (set_attr "cell_micro" "always")])
9159 (define_insn "*stmsi5"
9160 [(match_parallel 0 "store_multiple_operation"
9161 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9162 (match_operand:SI 2 "gpc_reg_operand" "r"))
9163 (clobber (match_scratch:SI 3 "=X"))
9164 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9165 (match_operand:SI 4 "gpc_reg_operand" "r"))
9166 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9167 (match_operand:SI 5 "gpc_reg_operand" "r"))
9168 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9169 (match_operand:SI 6 "gpc_reg_operand" "r"))
9170 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9171 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9172 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9173 "stswi %2,%1,%O0"
9174 [(set_attr "type" "store")
9175 (set_attr "update" "yes")
9176 (set_attr "indexed" "yes")
9177 (set_attr "cell_micro" "always")])
9179 (define_insn "*stmsi4"
9180 [(match_parallel 0 "store_multiple_operation"
9181 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9182 (match_operand:SI 2 "gpc_reg_operand" "r"))
9183 (clobber (match_scratch:SI 3 "=X"))
9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9185 (match_operand:SI 4 "gpc_reg_operand" "r"))
9186 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9187 (match_operand:SI 5 "gpc_reg_operand" "r"))
9188 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9189 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9190 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9191 "stswi %2,%1,%O0"
9192 [(set_attr "type" "store")
9193 (set_attr "update" "yes")
9194 (set_attr "indexed" "yes")
9195 (set_attr "cell_micro" "always")])
9197 (define_insn "*stmsi3"
9198 [(match_parallel 0 "store_multiple_operation"
9199 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9200 (match_operand:SI 2 "gpc_reg_operand" "r"))
9201 (clobber (match_scratch:SI 3 "=X"))
9202 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9203 (match_operand:SI 4 "gpc_reg_operand" "r"))
9204 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9205 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9206 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9207 "stswi %2,%1,%O0"
9208 [(set_attr "type" "store")
9209 (set_attr "update" "yes")
9210 (set_attr "indexed" "yes")
9211 (set_attr "cell_micro" "always")])
9212 \f
9213 (define_expand "setmemsi"
9214 [(parallel [(set (match_operand:BLK 0 "" "")
9215 (match_operand 2 "const_int_operand" ""))
9216 (use (match_operand:SI 1 "" ""))
9217 (use (match_operand:SI 3 "" ""))])]
9218 ""
9219 "
9220 {
9221 /* If value to set is not zero, use the library routine. */
9222 if (operands[2] != const0_rtx)
9223 FAIL;
9225 if (expand_block_clear (operands))
9226 DONE;
9227 else
9228 FAIL;
9229 }")
9231 ;; String/block move insn.
9232 ;; Argument 0 is the destination
9233 ;; Argument 1 is the source
9234 ;; Argument 2 is the length
9235 ;; Argument 3 is the alignment
9237 (define_expand "movmemsi"
9238 [(parallel [(set (match_operand:BLK 0 "" "")
9239 (match_operand:BLK 1 "" ""))
9240 (use (match_operand:SI 2 "" ""))
9241 (use (match_operand:SI 3 "" ""))])]
9242 ""
9243 "
9244 {
9245 if (expand_block_move (operands))
9246 DONE;
9247 else
9248 FAIL;
9249 }")
9251 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9252 ;; register allocator doesn't have a clue about allocating 8 word registers.
9253 ;; rD/rS = r5 is preferred, efficient form.
9254 (define_expand "movmemsi_8reg"
9255 [(parallel [(set (match_operand 0 "" "")
9256 (match_operand 1 "" ""))
9257 (use (match_operand 2 "" ""))
9258 (use (match_operand 3 "" ""))
9259 (clobber (reg:SI 5))
9260 (clobber (reg:SI 6))
9261 (clobber (reg:SI 7))
9262 (clobber (reg:SI 8))
9263 (clobber (reg:SI 9))
9264 (clobber (reg:SI 10))
9265 (clobber (reg:SI 11))
9266 (clobber (reg:SI 12))
9267 (clobber (match_scratch:SI 4 ""))])]
9268 "TARGET_STRING"
9269 "")
9271 (define_insn ""
9272 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9273 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9274 (use (match_operand:SI 2 "immediate_operand" "i"))
9275 (use (match_operand:SI 3 "immediate_operand" "i"))
9276 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9277 (clobber (reg:SI 6))
9278 (clobber (reg:SI 7))
9279 (clobber (reg:SI 8))
9280 (clobber (reg:SI 9))
9281 (clobber (reg:SI 10))
9282 (clobber (reg:SI 11))
9283 (clobber (reg:SI 12))
9284 (clobber (match_scratch:SI 5 "=X"))]
9285 "TARGET_STRING
9286 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9287 || INTVAL (operands[2]) == 0)
9288 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9289 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9290 && REGNO (operands[4]) == 5"
9291 "lswi %4,%1,%2\;stswi %4,%0,%2"
9292 [(set_attr "type" "store")
9293 (set_attr "update" "yes")
9294 (set_attr "indexed" "yes")
9295 (set_attr "cell_micro" "always")
9296 (set_attr "length" "8")])
9298 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9299 ;; register allocator doesn't have a clue about allocating 6 word registers.
9300 ;; rD/rS = r5 is preferred, efficient form.
9301 (define_expand "movmemsi_6reg"
9302 [(parallel [(set (match_operand 0 "" "")
9303 (match_operand 1 "" ""))
9304 (use (match_operand 2 "" ""))
9305 (use (match_operand 3 "" ""))
9306 (clobber (reg:SI 5))
9307 (clobber (reg:SI 6))
9308 (clobber (reg:SI 7))
9309 (clobber (reg:SI 8))
9310 (clobber (reg:SI 9))
9311 (clobber (reg:SI 10))
9312 (clobber (match_scratch:SI 4 ""))])]
9313 "TARGET_STRING"
9314 "")
9316 (define_insn ""
9317 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9318 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9319 (use (match_operand:SI 2 "immediate_operand" "i"))
9320 (use (match_operand:SI 3 "immediate_operand" "i"))
9321 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9322 (clobber (reg:SI 6))
9323 (clobber (reg:SI 7))
9324 (clobber (reg:SI 8))
9325 (clobber (reg:SI 9))
9326 (clobber (reg:SI 10))
9327 (clobber (match_scratch:SI 5 "=X"))]
9328 "TARGET_STRING
9329 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9330 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9331 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9332 && REGNO (operands[4]) == 5"
9333 "lswi %4,%1,%2\;stswi %4,%0,%2"
9334 [(set_attr "type" "store")
9335 (set_attr "update" "yes")
9336 (set_attr "indexed" "yes")
9337 (set_attr "cell_micro" "always")
9338 (set_attr "length" "8")])
9340 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9341 ;; problems with TImode.
9342 ;; rD/rS = r5 is preferred, efficient form.
9343 (define_expand "movmemsi_4reg"
9344 [(parallel [(set (match_operand 0 "" "")
9345 (match_operand 1 "" ""))
9346 (use (match_operand 2 "" ""))
9347 (use (match_operand 3 "" ""))
9348 (clobber (reg:SI 5))
9349 (clobber (reg:SI 6))
9350 (clobber (reg:SI 7))
9351 (clobber (reg:SI 8))
9352 (clobber (match_scratch:SI 4 ""))])]
9353 "TARGET_STRING"
9354 "")
9356 (define_insn ""
9357 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9358 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9359 (use (match_operand:SI 2 "immediate_operand" "i"))
9360 (use (match_operand:SI 3 "immediate_operand" "i"))
9361 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9362 (clobber (reg:SI 6))
9363 (clobber (reg:SI 7))
9364 (clobber (reg:SI 8))
9365 (clobber (match_scratch:SI 5 "=X"))]
9366 "TARGET_STRING
9367 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9368 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9369 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9370 && REGNO (operands[4]) == 5"
9371 "lswi %4,%1,%2\;stswi %4,%0,%2"
9372 [(set_attr "type" "store")
9373 (set_attr "update" "yes")
9374 (set_attr "indexed" "yes")
9375 (set_attr "cell_micro" "always")
9376 (set_attr "length" "8")])
9378 ;; Move up to 8 bytes at a time.
9379 (define_expand "movmemsi_2reg"
9380 [(parallel [(set (match_operand 0 "" "")
9381 (match_operand 1 "" ""))
9382 (use (match_operand 2 "" ""))
9383 (use (match_operand 3 "" ""))
9384 (clobber (match_scratch:DI 4 ""))
9385 (clobber (match_scratch:SI 5 ""))])]
9386 "TARGET_STRING && ! TARGET_POWERPC64"
9387 "")
9389 (define_insn ""
9390 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9391 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9392 (use (match_operand:SI 2 "immediate_operand" "i"))
9393 (use (match_operand:SI 3 "immediate_operand" "i"))
9394 (clobber (match_scratch:DI 4 "=&r"))
9395 (clobber (match_scratch:SI 5 "=X"))]
9396 "TARGET_STRING && ! TARGET_POWERPC64
9397 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9398 "lswi %4,%1,%2\;stswi %4,%0,%2"
9399 [(set_attr "type" "store")
9400 (set_attr "update" "yes")
9401 (set_attr "indexed" "yes")
9402 (set_attr "cell_micro" "always")
9403 (set_attr "length" "8")])
9405 ;; Move up to 4 bytes at a time.
9406 (define_expand "movmemsi_1reg"
9407 [(parallel [(set (match_operand 0 "" "")
9408 (match_operand 1 "" ""))
9409 (use (match_operand 2 "" ""))
9410 (use (match_operand 3 "" ""))
9411 (clobber (match_scratch:SI 4 ""))
9412 (clobber (match_scratch:SI 5 ""))])]
9413 "TARGET_STRING"
9414 "")
9416 (define_insn ""
9417 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9418 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9419 (use (match_operand:SI 2 "immediate_operand" "i"))
9420 (use (match_operand:SI 3 "immediate_operand" "i"))
9421 (clobber (match_scratch:SI 4 "=&r"))
9422 (clobber (match_scratch:SI 5 "=X"))]
9423 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9424 "lswi %4,%1,%2\;stswi %4,%0,%2"
9425 [(set_attr "type" "store")
9426 (set_attr "update" "yes")
9427 (set_attr "indexed" "yes")
9428 (set_attr "cell_micro" "always")
9429 (set_attr "length" "8")])
9430 \f
9431 ;; Define insns that do load or store with update. Some of these we can
9432 ;; get by using pre-decrement or pre-increment, but the hardware can also
9433 ;; do cases where the increment is not the size of the object.
9434 ;;
9435 ;; In all these cases, we use operands 0 and 1 for the register being
9436 ;; incremented because those are the operands that local-alloc will
9437 ;; tie and these are the pair most likely to be tieable (and the ones
9438 ;; that will benefit the most).
9440 (define_insn "*movdi_update1"
9441 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9442 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9443 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9444 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9445 (plus:DI (match_dup 1) (match_dup 2)))]
9446 "TARGET_POWERPC64 && TARGET_UPDATE
9447 && (!avoiding_indexed_address_p (DImode)
9448 || !gpc_reg_operand (operands[2], DImode))"
9449 "@
9450 ldux %3,%0,%2
9451 ldu %3,%2(%0)"
9452 [(set_attr "type" "load")
9453 (set_attr "update" "yes")
9454 (set_attr "indexed" "yes,no")])
9456 (define_insn "movdi_<mode>_update"
9457 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9458 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9459 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9460 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9461 (plus:P (match_dup 1) (match_dup 2)))]
9462 "TARGET_POWERPC64 && TARGET_UPDATE
9463 && (!avoiding_indexed_address_p (Pmode)
9464 || !gpc_reg_operand (operands[2], Pmode)
9465 || (REG_P (operands[0])
9466 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9467 "@
9468 stdux %3,%0,%2
9469 stdu %3,%2(%0)"
9470 [(set_attr "type" "store")
9471 (set_attr "update" "yes")
9472 (set_attr "indexed" "yes,no")])
9474 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9475 ;; needed for stack allocation, even if the user passes -mno-update.
9476 (define_insn "movdi_<mode>_update_stack"
9477 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9478 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9479 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9480 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9481 (plus:P (match_dup 1) (match_dup 2)))]
9482 "TARGET_POWERPC64"
9483 "@
9484 stdux %3,%0,%2
9485 stdu %3,%2(%0)"
9486 [(set_attr "type" "store")
9487 (set_attr "update" "yes")
9488 (set_attr "indexed" "yes,no")])
9490 (define_insn "*movsi_update1"
9491 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9492 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9493 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9494 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9495 (plus:SI (match_dup 1) (match_dup 2)))]
9496 "TARGET_UPDATE
9497 && (!avoiding_indexed_address_p (SImode)
9498 || !gpc_reg_operand (operands[2], SImode))"
9499 "@
9500 lwzux %3,%0,%2
9501 lwzu %3,%2(%0)"
9502 [(set_attr "type" "load")
9503 (set_attr "update" "yes")
9504 (set_attr "indexed" "yes,no")])
9506 (define_insn "*movsi_update2"
9507 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9508 (sign_extend:DI
9509 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9510 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9511 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9512 (plus:DI (match_dup 1) (match_dup 2)))]
9513 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9514 && !avoiding_indexed_address_p (DImode)"
9515 "lwaux %3,%0,%2"
9516 [(set_attr "type" "load")
9517 (set_attr "sign_extend" "yes")
9518 (set_attr "update" "yes")
9519 (set_attr "indexed" "yes")])
9521 (define_insn "movsi_update"
9522 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9523 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9524 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9525 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9526 (plus:SI (match_dup 1) (match_dup 2)))]
9527 "TARGET_UPDATE
9528 && (!avoiding_indexed_address_p (SImode)
9529 || !gpc_reg_operand (operands[2], SImode)
9530 || (REG_P (operands[0])
9531 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9532 "@
9533 stwux %3,%0,%2
9534 stwu %3,%2(%0)"
9535 [(set_attr "type" "store")
9536 (set_attr "update" "yes")
9537 (set_attr "indexed" "yes,no")])
9539 ;; This is an unconditional pattern; needed for stack allocation, even
9540 ;; if the user passes -mno-update.
9541 (define_insn "movsi_update_stack"
9542 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9543 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9544 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9545 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9546 (plus:SI (match_dup 1) (match_dup 2)))]
9547 ""
9548 "@
9549 stwux %3,%0,%2
9550 stwu %3,%2(%0)"
9551 [(set_attr "type" "store")
9552 (set_attr "update" "yes")
9553 (set_attr "indexed" "yes,no")])
9555 (define_insn "*movhi_update1"
9556 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9557 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9558 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9559 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9560 (plus:SI (match_dup 1) (match_dup 2)))]
9561 "TARGET_UPDATE
9562 && (!avoiding_indexed_address_p (SImode)
9563 || !gpc_reg_operand (operands[2], SImode))"
9564 "@
9565 lhzux %3,%0,%2
9566 lhzu %3,%2(%0)"
9567 [(set_attr "type" "load")
9568 (set_attr "update" "yes")
9569 (set_attr "indexed" "yes,no")])
9571 (define_insn "*movhi_update2"
9572 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9573 (zero_extend:SI
9574 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9575 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9576 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9577 (plus:SI (match_dup 1) (match_dup 2)))]
9578 "TARGET_UPDATE
9579 && (!avoiding_indexed_address_p (SImode)
9580 || !gpc_reg_operand (operands[2], SImode))"
9581 "@
9582 lhzux %3,%0,%2
9583 lhzu %3,%2(%0)"
9584 [(set_attr "type" "load")
9585 (set_attr "update" "yes")
9586 (set_attr "indexed" "yes,no")])
9588 (define_insn "*movhi_update3"
9589 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9590 (sign_extend:SI
9591 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9592 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9593 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9594 (plus:SI (match_dup 1) (match_dup 2)))]
9595 "TARGET_UPDATE && rs6000_gen_cell_microcode
9596 && (!avoiding_indexed_address_p (SImode)
9597 || !gpc_reg_operand (operands[2], SImode))"
9598 "@
9599 lhaux %3,%0,%2
9600 lhau %3,%2(%0)"
9601 [(set_attr "type" "load")
9602 (set_attr "sign_extend" "yes")
9603 (set_attr "update" "yes")
9604 (set_attr "indexed" "yes,no")])
9606 (define_insn "*movhi_update4"
9607 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9608 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9609 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9610 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9611 (plus:SI (match_dup 1) (match_dup 2)))]
9612 "TARGET_UPDATE
9613 && (!avoiding_indexed_address_p (SImode)
9614 || !gpc_reg_operand (operands[2], SImode))"
9615 "@
9616 sthux %3,%0,%2
9617 sthu %3,%2(%0)"
9618 [(set_attr "type" "store")
9619 (set_attr "update" "yes")
9620 (set_attr "indexed" "yes,no")])
9622 (define_insn "*movqi_update1"
9623 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9624 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9625 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9626 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9627 (plus:SI (match_dup 1) (match_dup 2)))]
9628 "TARGET_UPDATE
9629 && (!avoiding_indexed_address_p (SImode)
9630 || !gpc_reg_operand (operands[2], SImode))"
9631 "@
9632 lbzux %3,%0,%2
9633 lbzu %3,%2(%0)"
9634 [(set_attr "type" "load")
9635 (set_attr "update" "yes")
9636 (set_attr "indexed" "yes,no")])
9638 (define_insn "*movqi_update2"
9639 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9640 (zero_extend:SI
9641 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9642 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9643 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9644 (plus:SI (match_dup 1) (match_dup 2)))]
9645 "TARGET_UPDATE
9646 && (!avoiding_indexed_address_p (SImode)
9647 || !gpc_reg_operand (operands[2], SImode))"
9648 "@
9649 lbzux %3,%0,%2
9650 lbzu %3,%2(%0)"
9651 [(set_attr "type" "load")
9652 (set_attr "update" "yes")
9653 (set_attr "indexed" "yes,no")])
9655 (define_insn "*movqi_update3"
9656 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9657 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9658 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9660 (plus:SI (match_dup 1) (match_dup 2)))]
9661 "TARGET_UPDATE
9662 && (!avoiding_indexed_address_p (SImode)
9663 || !gpc_reg_operand (operands[2], SImode))"
9664 "@
9665 stbux %3,%0,%2
9666 stbu %3,%2(%0)"
9667 [(set_attr "type" "store")
9668 (set_attr "update" "yes")
9669 (set_attr "indexed" "yes,no")])
9671 (define_insn "*movsf_update1"
9672 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9673 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9674 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9675 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9676 (plus:SI (match_dup 1) (match_dup 2)))]
9677 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9678 && (!avoiding_indexed_address_p (SImode)
9679 || !gpc_reg_operand (operands[2], SImode))"
9680 "@
9681 lfsux %3,%0,%2
9682 lfsu %3,%2(%0)"
9683 [(set_attr "type" "fpload")
9684 (set_attr "update" "yes")
9685 (set_attr "indexed" "yes,no")])
9687 (define_insn "*movsf_update2"
9688 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9689 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9690 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9691 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9692 (plus:SI (match_dup 1) (match_dup 2)))]
9693 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9694 && (!avoiding_indexed_address_p (SImode)
9695 || !gpc_reg_operand (operands[2], SImode))"
9696 "@
9697 stfsux %3,%0,%2
9698 stfsu %3,%2(%0)"
9699 [(set_attr "type" "fpstore")
9700 (set_attr "update" "yes")
9701 (set_attr "indexed" "yes,no")])
9703 (define_insn "*movsf_update3"
9704 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9705 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9706 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9707 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9708 (plus:SI (match_dup 1) (match_dup 2)))]
9709 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9710 && (!avoiding_indexed_address_p (SImode)
9711 || !gpc_reg_operand (operands[2], SImode))"
9712 "@
9713 lwzux %3,%0,%2
9714 lwzu %3,%2(%0)"
9715 [(set_attr "type" "load")
9716 (set_attr "update" "yes")
9717 (set_attr "indexed" "yes,no")])
9719 (define_insn "*movsf_update4"
9720 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9721 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9722 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9723 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9724 (plus:SI (match_dup 1) (match_dup 2)))]
9725 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9726 && (!avoiding_indexed_address_p (SImode)
9727 || !gpc_reg_operand (operands[2], SImode))"
9728 "@
9729 stwux %3,%0,%2
9730 stwu %3,%2(%0)"
9731 [(set_attr "type" "store")
9732 (set_attr "update" "yes")
9733 (set_attr "indexed" "yes,no")])
9735 (define_insn "*movdf_update1"
9736 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9737 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9738 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9739 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9740 (plus:SI (match_dup 1) (match_dup 2)))]
9741 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9742 && (!avoiding_indexed_address_p (SImode)
9743 || !gpc_reg_operand (operands[2], SImode))"
9744 "@
9745 lfdux %3,%0,%2
9746 lfdu %3,%2(%0)"
9747 [(set_attr "type" "fpload")
9748 (set_attr "update" "yes")
9749 (set_attr "indexed" "yes,no")])
9751 (define_insn "*movdf_update2"
9752 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9753 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9754 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9755 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9756 (plus:SI (match_dup 1) (match_dup 2)))]
9757 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9758 && (!avoiding_indexed_address_p (SImode)
9759 || !gpc_reg_operand (operands[2], SImode))"
9760 "@
9761 stfdux %3,%0,%2
9762 stfdu %3,%2(%0)"
9763 [(set_attr "type" "fpstore")
9764 (set_attr "update" "yes")
9765 (set_attr "indexed" "yes,no")])
9768 ;; After inserting conditional returns we can sometimes have
9769 ;; unnecessary register moves. Unfortunately we cannot have a
9770 ;; modeless peephole here, because some single SImode sets have early
9771 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9772 ;; sequences, using get_attr_length here will smash the operands
9773 ;; array. Neither is there an early_cobbler_p predicate.
9774 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9775 (define_peephole2
9776 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9777 (match_operand:DF 1 "any_operand" ""))
9778 (set (match_operand:DF 2 "gpc_reg_operand" "")
9779 (match_dup 0))]
9780 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9781 && peep2_reg_dead_p (2, operands[0])"
9782 [(set (match_dup 2) (match_dup 1))])
9784 (define_peephole2
9785 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9786 (match_operand:SF 1 "any_operand" ""))
9787 (set (match_operand:SF 2 "gpc_reg_operand" "")
9788 (match_dup 0))]
9789 "peep2_reg_dead_p (2, operands[0])"
9790 [(set (match_dup 2) (match_dup 1))])
9792 \f
9793 ;; TLS support.
9795 ;; Mode attributes for different ABIs.
9796 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9797 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9798 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9799 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9801 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9802 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9803 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9804 (match_operand 4 "" "g")))
9805 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9806 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9807 UNSPEC_TLSGD)
9808 (clobber (reg:SI LR_REGNO))]
9809 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9810 {
9811 if (TARGET_CMODEL != CMODEL_SMALL)
9812 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9813 "bl %z3\;nop";
9814 else
9815 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9816 }
9817 "&& TARGET_TLS_MARKERS"
9818 [(set (match_dup 0)
9819 (unspec:TLSmode [(match_dup 1)
9820 (match_dup 2)]
9821 UNSPEC_TLSGD))
9822 (parallel [(set (match_dup 0)
9823 (call (mem:TLSmode (match_dup 3))
9824 (match_dup 4)))
9825 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9826 (clobber (reg:SI LR_REGNO))])]
9827 ""
9828 [(set_attr "type" "two")
9829 (set (attr "length")
9830 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9831 (const_int 16)
9832 (const_int 12)))])
9834 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9835 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9836 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9837 (match_operand 4 "" "g")))
9838 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9839 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9840 UNSPEC_TLSGD)
9841 (clobber (reg:SI LR_REGNO))]
9842 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9843 {
9844 if (flag_pic)
9845 {
9846 if (TARGET_SECURE_PLT && flag_pic == 2)
9847 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9848 else
9849 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9850 }
9851 else
9852 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9853 }
9854 "&& TARGET_TLS_MARKERS"
9855 [(set (match_dup 0)
9856 (unspec:TLSmode [(match_dup 1)
9857 (match_dup 2)]
9858 UNSPEC_TLSGD))
9859 (parallel [(set (match_dup 0)
9860 (call (mem:TLSmode (match_dup 3))
9861 (match_dup 4)))
9862 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9863 (clobber (reg:SI LR_REGNO))])]
9864 ""
9865 [(set_attr "type" "two")
9866 (set_attr "length" "8")])
9868 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9869 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9870 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9871 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9872 UNSPEC_TLSGD))]
9873 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9874 "addi %0,%1,%2@got@tlsgd"
9875 "&& TARGET_CMODEL != CMODEL_SMALL"
9876 [(set (match_dup 3)
9877 (high:TLSmode
9878 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9879 (set (match_dup 0)
9880 (lo_sum:TLSmode (match_dup 3)
9881 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9882 "
9883 {
9884 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9885 }"
9886 [(set (attr "length")
9887 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9888 (const_int 8)
9889 (const_int 4)))])
9891 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9892 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9893 (high:TLSmode
9894 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9895 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9896 UNSPEC_TLSGD)))]
9897 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9898 "addis %0,%1,%2@got@tlsgd@ha"
9899 [(set_attr "length" "4")])
9901 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9902 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9903 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9904 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9905 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9906 UNSPEC_TLSGD)))]
9907 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9908 "addi %0,%1,%2@got@tlsgd@l"
9909 [(set_attr "length" "4")])
9911 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9912 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9913 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9914 (match_operand 2 "" "g")))
9915 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9916 UNSPEC_TLSGD)
9917 (clobber (reg:SI LR_REGNO))]
9918 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9919 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9920 "bl %z1(%3@tlsgd)\;nop"
9921 [(set_attr "type" "branch")
9922 (set_attr "length" "8")])
9924 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9925 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9926 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9927 (match_operand 2 "" "g")))
9928 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9929 UNSPEC_TLSGD)
9930 (clobber (reg:SI LR_REGNO))]
9931 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9932 {
9933 if (flag_pic)
9934 {
9935 if (TARGET_SECURE_PLT && flag_pic == 2)
9936 return "bl %z1+32768(%3@tlsgd)@plt";
9937 return "bl %z1(%3@tlsgd)@plt";
9938 }
9939 return "bl %z1(%3@tlsgd)";
9940 }
9941 [(set_attr "type" "branch")
9942 (set_attr "length" "4")])
9944 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9945 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9946 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9947 (match_operand 3 "" "g")))
9948 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9949 UNSPEC_TLSLD)
9950 (clobber (reg:SI LR_REGNO))]
9951 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9952 {
9953 if (TARGET_CMODEL != CMODEL_SMALL)
9954 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9955 "bl %z2\;nop";
9956 else
9957 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9958 }
9959 "&& TARGET_TLS_MARKERS"
9960 [(set (match_dup 0)
9961 (unspec:TLSmode [(match_dup 1)]
9962 UNSPEC_TLSLD))
9963 (parallel [(set (match_dup 0)
9964 (call (mem:TLSmode (match_dup 2))
9965 (match_dup 3)))
9966 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9967 (clobber (reg:SI LR_REGNO))])]
9968 ""
9969 [(set_attr "type" "two")
9970 (set (attr "length")
9971 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9972 (const_int 16)
9973 (const_int 12)))])
9975 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9976 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9977 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9978 (match_operand 3 "" "g")))
9979 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9980 UNSPEC_TLSLD)
9981 (clobber (reg:SI LR_REGNO))]
9982 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9983 {
9984 if (flag_pic)
9985 {
9986 if (TARGET_SECURE_PLT && flag_pic == 2)
9987 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9988 else
9989 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9990 }
9991 else
9992 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9993 }
9994 "&& TARGET_TLS_MARKERS"
9995 [(set (match_dup 0)
9996 (unspec:TLSmode [(match_dup 1)]
9997 UNSPEC_TLSLD))
9998 (parallel [(set (match_dup 0)
9999 (call (mem:TLSmode (match_dup 2))
10000 (match_dup 3)))
10001 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10002 (clobber (reg:SI LR_REGNO))])]
10003 ""
10004 [(set_attr "length" "8")])
10006 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10007 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10008 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10009 UNSPEC_TLSLD))]
10010 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10011 "addi %0,%1,%&@got@tlsld"
10012 "&& TARGET_CMODEL != CMODEL_SMALL"
10013 [(set (match_dup 2)
10014 (high:TLSmode
10015 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10016 (set (match_dup 0)
10017 (lo_sum:TLSmode (match_dup 2)
10018 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10019 "
10020 {
10021 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10022 }"
10023 [(set (attr "length")
10024 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10025 (const_int 8)
10026 (const_int 4)))])
10028 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10029 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10030 (high:TLSmode
10031 (unspec:TLSmode [(const_int 0)
10032 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10033 UNSPEC_TLSLD)))]
10034 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10035 "addis %0,%1,%&@got@tlsld@ha"
10036 [(set_attr "length" "4")])
10038 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10039 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10040 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10041 (unspec:TLSmode [(const_int 0)
10042 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10043 UNSPEC_TLSLD)))]
10044 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10045 "addi %0,%1,%&@got@tlsld@l"
10046 [(set_attr "length" "4")])
10048 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10049 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10050 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10051 (match_operand 2 "" "g")))
10052 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10053 (clobber (reg:SI LR_REGNO))]
10054 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10055 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10056 "bl %z1(%&@tlsld)\;nop"
10057 [(set_attr "type" "branch")
10058 (set_attr "length" "8")])
10060 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10061 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10062 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10063 (match_operand 2 "" "g")))
10064 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10065 (clobber (reg:SI LR_REGNO))]
10066 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10067 {
10068 if (flag_pic)
10069 {
10070 if (TARGET_SECURE_PLT && flag_pic == 2)
10071 return "bl %z1+32768(%&@tlsld)@plt";
10072 return "bl %z1(%&@tlsld)@plt";
10073 }
10074 return "bl %z1(%&@tlsld)";
10075 }
10076 [(set_attr "type" "branch")
10077 (set_attr "length" "4")])
10079 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10080 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10081 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10082 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10083 UNSPEC_TLSDTPREL))]
10084 "HAVE_AS_TLS"
10085 "addi %0,%1,%2@dtprel")
10087 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10088 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10089 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10090 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10091 UNSPEC_TLSDTPRELHA))]
10092 "HAVE_AS_TLS"
10093 "addis %0,%1,%2@dtprel@ha")
10095 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10096 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10097 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10098 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10099 UNSPEC_TLSDTPRELLO))]
10100 "HAVE_AS_TLS"
10101 "addi %0,%1,%2@dtprel@l")
10103 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10104 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10105 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10106 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10107 UNSPEC_TLSGOTDTPREL))]
10108 "HAVE_AS_TLS"
10109 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10110 "&& TARGET_CMODEL != CMODEL_SMALL"
10111 [(set (match_dup 3)
10112 (high:TLSmode
10113 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10114 (set (match_dup 0)
10115 (lo_sum:TLSmode (match_dup 3)
10116 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10117 "
10118 {
10119 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10120 }"
10121 [(set (attr "length")
10122 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10123 (const_int 8)
10124 (const_int 4)))])
10126 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10127 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10128 (high:TLSmode
10129 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10130 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10131 UNSPEC_TLSGOTDTPREL)))]
10132 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10133 "addis %0,%1,%2@got@dtprel@ha"
10134 [(set_attr "length" "4")])
10136 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10137 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10138 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10139 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10140 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10141 UNSPEC_TLSGOTDTPREL)))]
10142 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10143 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10144 [(set_attr "length" "4")])
10146 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10147 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10148 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10149 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10150 UNSPEC_TLSTPREL))]
10151 "HAVE_AS_TLS"
10152 "addi %0,%1,%2@tprel")
10154 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10155 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10156 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10157 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10158 UNSPEC_TLSTPRELHA))]
10159 "HAVE_AS_TLS"
10160 "addis %0,%1,%2@tprel@ha")
10162 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10163 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10164 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10165 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10166 UNSPEC_TLSTPRELLO))]
10167 "HAVE_AS_TLS"
10168 "addi %0,%1,%2@tprel@l")
10170 ;; "b" output constraint here and on tls_tls input to support linker tls
10171 ;; optimization. The linker may edit the instructions emitted by a
10172 ;; tls_got_tprel/tls_tls pair to addis,addi.
10173 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10174 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10175 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10176 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10177 UNSPEC_TLSGOTTPREL))]
10178 "HAVE_AS_TLS"
10179 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10180 "&& TARGET_CMODEL != CMODEL_SMALL"
10181 [(set (match_dup 3)
10182 (high:TLSmode
10183 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10184 (set (match_dup 0)
10185 (lo_sum:TLSmode (match_dup 3)
10186 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10187 "
10188 {
10189 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10190 }"
10191 [(set (attr "length")
10192 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10193 (const_int 8)
10194 (const_int 4)))])
10196 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10197 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10198 (high:TLSmode
10199 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10200 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10201 UNSPEC_TLSGOTTPREL)))]
10202 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10203 "addis %0,%1,%2@got@tprel@ha"
10204 [(set_attr "length" "4")])
10206 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10208 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10209 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10210 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10211 UNSPEC_TLSGOTTPREL)))]
10212 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10213 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10214 [(set_attr "length" "4")])
10216 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10217 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10218 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10219 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10220 UNSPEC_TLSTLS))]
10221 "TARGET_ELF && HAVE_AS_TLS"
10222 "add %0,%1,%2@tls")
10224 (define_expand "tls_get_tpointer"
10225 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10226 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10227 "TARGET_XCOFF && HAVE_AS_TLS"
10228 "
10229 {
10230 emit_insn (gen_tls_get_tpointer_internal ());
10231 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10232 DONE;
10233 }")
10235 (define_insn "tls_get_tpointer_internal"
10236 [(set (reg:SI 3)
10237 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10238 (clobber (reg:SI LR_REGNO))]
10239 "TARGET_XCOFF && HAVE_AS_TLS"
10240 "bla __get_tpointer")
10242 (define_expand "tls_get_addr<mode>"
10243 [(set (match_operand:P 0 "gpc_reg_operand" "")
10244 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10245 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10246 "TARGET_XCOFF && HAVE_AS_TLS"
10247 "
10248 {
10249 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10250 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10251 emit_insn (gen_tls_get_addr_internal<mode> ());
10252 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10253 DONE;
10254 }")
10256 (define_insn "tls_get_addr_internal<mode>"
10257 [(set (reg:P 3)
10258 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10259 (clobber (reg:P 0))
10260 (clobber (reg:P 4))
10261 (clobber (reg:P 5))
10262 (clobber (reg:P 11))
10263 (clobber (reg:CC CR0_REGNO))
10264 (clobber (reg:P LR_REGNO))]
10265 "TARGET_XCOFF && HAVE_AS_TLS"
10266 "bla __tls_get_addr")
10267 \f
10268 ;; Next come insns related to the calling sequence.
10269 ;;
10270 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10271 ;; We move the back-chain and decrement the stack pointer.
10273 (define_expand "allocate_stack"
10274 [(set (match_operand 0 "gpc_reg_operand" "")
10275 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10276 (set (reg 1)
10277 (minus (reg 1) (match_dup 1)))]
10278 ""
10279 "
10280 { rtx chain = gen_reg_rtx (Pmode);
10281 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10282 rtx neg_op0;
10283 rtx insn, par, set, mem;
10285 emit_move_insn (chain, stack_bot);
10287 /* Check stack bounds if necessary. */
10288 if (crtl->limit_stack)
10289 {
10290 rtx available;
10291 available = expand_binop (Pmode, sub_optab,
10292 stack_pointer_rtx, stack_limit_rtx,
10293 NULL_RTX, 1, OPTAB_WIDEN);
10294 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10295 }
10297 if (GET_CODE (operands[1]) != CONST_INT
10298 || INTVAL (operands[1]) < -32767
10299 || INTVAL (operands[1]) > 32768)
10300 {
10301 neg_op0 = gen_reg_rtx (Pmode);
10302 if (TARGET_32BIT)
10303 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10304 else
10305 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10306 }
10307 else
10308 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10310 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10311 : gen_movdi_di_update_stack))
10312 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10313 chain));
10314 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10315 it now and set the alias set/attributes. The above gen_*_update
10316 calls will generate a PARALLEL with the MEM set being the first
10317 operation. */
10318 par = PATTERN (insn);
10319 gcc_assert (GET_CODE (par) == PARALLEL);
10320 set = XVECEXP (par, 0, 0);
10321 gcc_assert (GET_CODE (set) == SET);
10322 mem = SET_DEST (set);
10323 gcc_assert (MEM_P (mem));
10324 MEM_NOTRAP_P (mem) = 1;
10325 set_mem_alias_set (mem, get_frame_alias_set ());
10327 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10328 DONE;
10329 }")
10331 ;; These patterns say how to save and restore the stack pointer. We need not
10332 ;; save the stack pointer at function level since we are careful to
10333 ;; preserve the backchain. At block level, we have to restore the backchain
10334 ;; when we restore the stack pointer.
10335 ;;
10336 ;; For nonlocal gotos, we must save both the stack pointer and its
10337 ;; backchain and restore both. Note that in the nonlocal case, the
10338 ;; save area is a memory location.
10340 (define_expand "save_stack_function"
10341 [(match_operand 0 "any_operand" "")
10342 (match_operand 1 "any_operand" "")]
10343 ""
10344 "DONE;")
10346 (define_expand "restore_stack_function"
10347 [(match_operand 0 "any_operand" "")
10348 (match_operand 1 "any_operand" "")]
10349 ""
10350 "DONE;")
10352 ;; Adjust stack pointer (op0) to a new value (op1).
10353 ;; First copy old stack backchain to new location, and ensure that the
10354 ;; scheduler won't reorder the sp assignment before the backchain write.
10355 (define_expand "restore_stack_block"
10356 [(set (match_dup 2) (match_dup 3))
10357 (set (match_dup 4) (match_dup 2))
10358 (match_dup 5)
10359 (set (match_operand 0 "register_operand" "")
10360 (match_operand 1 "register_operand" ""))]
10361 ""
10362 "
10363 {
10364 rtvec p;
10366 operands[1] = force_reg (Pmode, operands[1]);
10367 operands[2] = gen_reg_rtx (Pmode);
10368 operands[3] = gen_frame_mem (Pmode, operands[0]);
10369 operands[4] = gen_frame_mem (Pmode, operands[1]);
10370 p = rtvec_alloc (1);
10371 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10372 gen_frame_mem (BLKmode, operands[0]),
10373 const0_rtx);
10374 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10375 }")
10377 (define_expand "save_stack_nonlocal"
10378 [(set (match_dup 3) (match_dup 4))
10379 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10380 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10381 ""
10382 "
10383 {
10384 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10386 /* Copy the backchain to the first word, sp to the second. */
10387 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10388 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10389 operands[3] = gen_reg_rtx (Pmode);
10390 operands[4] = gen_frame_mem (Pmode, operands[1]);
10391 }")
10393 (define_expand "restore_stack_nonlocal"
10394 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10395 (set (match_dup 3) (match_dup 4))
10396 (set (match_dup 5) (match_dup 2))
10397 (match_dup 6)
10398 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10399 ""
10400 "
10401 {
10402 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10403 rtvec p;
10405 /* Restore the backchain from the first word, sp from the second. */
10406 operands[2] = gen_reg_rtx (Pmode);
10407 operands[3] = gen_reg_rtx (Pmode);
10408 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10409 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10410 operands[5] = gen_frame_mem (Pmode, operands[3]);
10411 p = rtvec_alloc (1);
10412 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10413 gen_frame_mem (BLKmode, operands[0]),
10414 const0_rtx);
10415 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10416 }")
10417 \f
10418 ;; TOC register handling.
10420 ;; Code to initialize the TOC register...
10422 (define_insn "load_toc_aix_si"
10423 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10424 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10425 (use (reg:SI 2))])]
10426 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10427 "*
10428 {
10429 char buf[30];
10430 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10431 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10432 operands[2] = gen_rtx_REG (Pmode, 2);
10433 return \"lwz %0,%1(%2)\";
10434 }"
10435 [(set_attr "type" "load")
10436 (set_attr "update" "no")
10437 (set_attr "indexed" "no")])
10439 (define_insn "load_toc_aix_di"
10440 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10441 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10442 (use (reg:DI 2))])]
10443 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10444 "*
10445 {
10446 char buf[30];
10447 #ifdef TARGET_RELOCATABLE
10448 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10449 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10450 #else
10451 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10452 #endif
10453 if (TARGET_ELF)
10454 strcat (buf, \"@toc\");
10455 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10456 operands[2] = gen_rtx_REG (Pmode, 2);
10457 return \"ld %0,%1(%2)\";
10458 }"
10459 [(set_attr "type" "load")
10460 (set_attr "update" "no")
10461 (set_attr "indexed" "no")])
10463 (define_insn "load_toc_v4_pic_si"
10464 [(set (reg:SI LR_REGNO)
10465 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10466 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10467 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10468 [(set_attr "type" "branch")
10469 (set_attr "length" "4")])
10471 (define_expand "load_toc_v4_PIC_1"
10472 [(parallel [(set (reg:SI LR_REGNO)
10473 (match_operand:SI 0 "immediate_operand" "s"))
10474 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10475 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10476 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10477 "")
10479 (define_insn "load_toc_v4_PIC_1_normal"
10480 [(set (reg:SI LR_REGNO)
10481 (match_operand:SI 0 "immediate_operand" "s"))
10482 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10483 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10484 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10485 "bcl 20,31,%0\\n%0:"
10486 [(set_attr "type" "branch")
10487 (set_attr "length" "4")])
10489 (define_insn "load_toc_v4_PIC_1_476"
10490 [(set (reg:SI LR_REGNO)
10491 (match_operand:SI 0 "immediate_operand" "s"))
10492 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10493 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10494 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10495 "*
10496 {
10497 char name[32];
10498 static char templ[32];
10500 get_ppc476_thunk_name (name);
10501 sprintf (templ, \"bl %s\\n%%0:\", name);
10502 return templ;
10503 }"
10504 [(set_attr "type" "branch")
10505 (set_attr "length" "4")])
10507 (define_expand "load_toc_v4_PIC_1b"
10508 [(parallel [(set (reg:SI LR_REGNO)
10509 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10510 (label_ref (match_operand 1 "" ""))]
10511 UNSPEC_TOCPTR))
10512 (match_dup 1)])]
10513 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10514 "")
10516 (define_insn "load_toc_v4_PIC_1b_normal"
10517 [(set (reg:SI LR_REGNO)
10518 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10519 (label_ref (match_operand 1 "" ""))]
10520 UNSPEC_TOCPTR))
10521 (match_dup 1)]
10522 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10523 "bcl 20,31,$+8\;.long %0-$"
10524 [(set_attr "type" "branch")
10525 (set_attr "length" "8")])
10527 (define_insn "load_toc_v4_PIC_1b_476"
10528 [(set (reg:SI LR_REGNO)
10529 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10530 (label_ref (match_operand 1 "" ""))]
10531 UNSPEC_TOCPTR))
10532 (match_dup 1)]
10533 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10534 "*
10535 {
10536 char name[32];
10537 static char templ[32];
10539 get_ppc476_thunk_name (name);
10540 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10541 return templ;
10542 }"
10543 [(set_attr "type" "branch")
10544 (set_attr "length" "16")])
10546 (define_insn "load_toc_v4_PIC_2"
10547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10548 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10549 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10550 (match_operand:SI 3 "immediate_operand" "s")))))]
10551 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10552 "lwz %0,%2-%3(%1)"
10553 [(set_attr "type" "load")])
10555 (define_insn "load_toc_v4_PIC_3b"
10556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10557 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10558 (high:SI
10559 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10560 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10561 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10562 "addis %0,%1,%2-%3@ha")
10564 (define_insn "load_toc_v4_PIC_3c"
10565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10566 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10567 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10568 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10569 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10570 "addi %0,%1,%2-%3@l")
10572 ;; If the TOC is shared over a translation unit, as happens with all
10573 ;; the kinds of PIC that we support, we need to restore the TOC
10574 ;; pointer only when jumping over units of translation.
10575 ;; On Darwin, we need to reload the picbase.
10577 (define_expand "builtin_setjmp_receiver"
10578 [(use (label_ref (match_operand 0 "" "")))]
10579 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10580 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10581 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10582 "
10583 {
10584 #if TARGET_MACHO
10585 if (DEFAULT_ABI == ABI_DARWIN)
10586 {
10587 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10588 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10589 rtx tmplabrtx;
10590 char tmplab[20];
10592 crtl->uses_pic_offset_table = 1;
10593 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10594 CODE_LABEL_NUMBER (operands[0]));
10595 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10597 emit_insn (gen_load_macho_picbase (tmplabrtx));
10598 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10599 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10600 }
10601 else
10602 #endif
10603 rs6000_emit_load_toc_table (FALSE);
10604 DONE;
10605 }")
10607 ;; Largetoc support
10608 (define_insn "*largetoc_high"
10609 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10610 (high:DI
10611 (unspec [(match_operand:DI 1 "" "")
10612 (match_operand:DI 2 "gpc_reg_operand" "b")]
10613 UNSPEC_TOCREL)))]
10614 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10615 "addis %0,%2,%1@toc@ha")
10617 (define_insn "*largetoc_high_aix<mode>"
10618 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10619 (high:P
10620 (unspec [(match_operand:P 1 "" "")
10621 (match_operand:P 2 "gpc_reg_operand" "b")]
10622 UNSPEC_TOCREL)))]
10623 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10624 "addis %0,%1@u(%2)")
10626 (define_insn "*largetoc_high_plus"
10627 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10628 (high:DI
10629 (plus:DI
10630 (unspec [(match_operand:DI 1 "" "")
10631 (match_operand:DI 2 "gpc_reg_operand" "b")]
10632 UNSPEC_TOCREL)
10633 (match_operand:DI 3 "add_cint_operand" "n"))))]
10634 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10635 "addis %0,%2,%1+%3@toc@ha")
10637 (define_insn "*largetoc_high_plus_aix<mode>"
10638 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10639 (high:P
10640 (plus:P
10641 (unspec [(match_operand:P 1 "" "")
10642 (match_operand:P 2 "gpc_reg_operand" "b")]
10643 UNSPEC_TOCREL)
10644 (match_operand:P 3 "add_cint_operand" "n"))))]
10645 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10646 "addis %0,%1+%3@u(%2)")
10648 (define_insn "*largetoc_low"
10649 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10650 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10651 (match_operand:DI 2 "" "")))]
10652 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10653 "@
10654 addi %0,%1,%2@l
10655 addic %0,%1,%2@l")
10657 (define_insn "*largetoc_low_aix<mode>"
10658 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10659 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10660 (match_operand:P 2 "" "")))]
10661 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10662 "la %0,%2@l(%1)")
10664 (define_insn_and_split "*tocref<mode>"
10665 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10666 (match_operand:P 1 "small_toc_ref" "R"))]
10667 "TARGET_TOC"
10668 "la %0,%a1"
10669 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10670 [(set (match_dup 0) (high:P (match_dup 1)))
10671 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10673 ;; Elf specific ways of loading addresses for non-PIC code.
10674 ;; The output of this could be r0, but we make a very strong
10675 ;; preference for a base register because it will usually
10676 ;; be needed there.
10677 (define_insn "elf_high"
10678 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10679 (high:SI (match_operand 1 "" "")))]
10680 "TARGET_ELF && ! TARGET_64BIT"
10681 "lis %0,%1@ha")
10683 (define_insn "elf_low"
10684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10685 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10686 (match_operand 2 "" "")))]
10687 "TARGET_ELF && ! TARGET_64BIT"
10688 "@
10689 la %0,%2@l(%1)
10690 addic %0,%1,%K2")
10691 \f
10692 ;; Call and call_value insns
10693 (define_expand "call"
10694 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10695 (match_operand 1 "" ""))
10696 (use (match_operand 2 "" ""))
10697 (clobber (reg:SI LR_REGNO))])]
10698 ""
10699 "
10700 {
10701 #if TARGET_MACHO
10702 if (MACHOPIC_INDIRECT)
10703 operands[0] = machopic_indirect_call_target (operands[0]);
10704 #endif
10706 gcc_assert (GET_CODE (operands[0]) == MEM);
10707 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10709 operands[0] = XEXP (operands[0], 0);
10711 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10712 {
10713 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10714 DONE;
10715 }
10717 if (GET_CODE (operands[0]) != SYMBOL_REF
10718 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10719 {
10720 if (INTVAL (operands[2]) & CALL_LONG)
10721 operands[0] = rs6000_longcall_ref (operands[0]);
10723 switch (DEFAULT_ABI)
10724 {
10725 case ABI_V4:
10726 case ABI_DARWIN:
10727 operands[0] = force_reg (Pmode, operands[0]);
10728 break;
10730 default:
10731 gcc_unreachable ();
10732 }
10733 }
10734 }")
10736 (define_expand "call_value"
10737 [(parallel [(set (match_operand 0 "" "")
10738 (call (mem:SI (match_operand 1 "address_operand" ""))
10739 (match_operand 2 "" "")))
10740 (use (match_operand 3 "" ""))
10741 (clobber (reg:SI LR_REGNO))])]
10742 ""
10743 "
10744 {
10745 #if TARGET_MACHO
10746 if (MACHOPIC_INDIRECT)
10747 operands[1] = machopic_indirect_call_target (operands[1]);
10748 #endif
10750 gcc_assert (GET_CODE (operands[1]) == MEM);
10751 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10753 operands[1] = XEXP (operands[1], 0);
10755 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10756 {
10757 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10758 DONE;
10759 }
10761 if (GET_CODE (operands[1]) != SYMBOL_REF
10762 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10763 {
10764 if (INTVAL (operands[3]) & CALL_LONG)
10765 operands[1] = rs6000_longcall_ref (operands[1]);
10767 switch (DEFAULT_ABI)
10768 {
10769 case ABI_V4:
10770 case ABI_DARWIN:
10771 operands[1] = force_reg (Pmode, operands[1]);
10772 break;
10774 default:
10775 gcc_unreachable ();
10776 }
10777 }
10778 }")
10780 ;; Call to function in current module. No TOC pointer reload needed.
10781 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10782 ;; either the function was not prototyped, or it was prototyped as a
10783 ;; variable argument function. It is > 0 if FP registers were passed
10784 ;; and < 0 if they were not.
10786 (define_insn "*call_local32"
10787 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10788 (match_operand 1 "" "g,g"))
10789 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10790 (clobber (reg:SI LR_REGNO))]
10791 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10792 "*
10793 {
10794 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10795 output_asm_insn (\"crxor 6,6,6\", operands);
10797 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10798 output_asm_insn (\"creqv 6,6,6\", operands);
10800 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10801 }"
10802 [(set_attr "type" "branch")
10803 (set_attr "length" "4,8")])
10805 (define_insn "*call_local64"
10806 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10807 (match_operand 1 "" "g,g"))
10808 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10809 (clobber (reg:SI LR_REGNO))]
10810 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10811 "*
10812 {
10813 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10814 output_asm_insn (\"crxor 6,6,6\", operands);
10816 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10817 output_asm_insn (\"creqv 6,6,6\", operands);
10819 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10820 }"
10821 [(set_attr "type" "branch")
10822 (set_attr "length" "4,8")])
10824 (define_insn "*call_value_local32"
10825 [(set (match_operand 0 "" "")
10826 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10827 (match_operand 2 "" "g,g")))
10828 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10829 (clobber (reg:SI LR_REGNO))]
10830 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10831 "*
10832 {
10833 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10834 output_asm_insn (\"crxor 6,6,6\", operands);
10836 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10837 output_asm_insn (\"creqv 6,6,6\", operands);
10839 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10840 }"
10841 [(set_attr "type" "branch")
10842 (set_attr "length" "4,8")])
10845 (define_insn "*call_value_local64"
10846 [(set (match_operand 0 "" "")
10847 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10848 (match_operand 2 "" "g,g")))
10849 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10850 (clobber (reg:SI LR_REGNO))]
10851 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10852 "*
10853 {
10854 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10855 output_asm_insn (\"crxor 6,6,6\", operands);
10857 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10858 output_asm_insn (\"creqv 6,6,6\", operands);
10860 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10861 }"
10862 [(set_attr "type" "branch")
10863 (set_attr "length" "4,8")])
10866 ;; A function pointer under System V is just a normal pointer
10867 ;; operands[0] is the function pointer
10868 ;; operands[1] is the stack size to clean up
10869 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10870 ;; which indicates how to set cr1
10872 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10873 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10874 (match_operand 1 "" "g,g,g,g"))
10875 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10876 (clobber (reg:SI LR_REGNO))]
10877 "DEFAULT_ABI == ABI_V4
10878 || DEFAULT_ABI == ABI_DARWIN"
10879 {
10880 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10881 output_asm_insn ("crxor 6,6,6", operands);
10883 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10884 output_asm_insn ("creqv 6,6,6", operands);
10886 return "b%T0l";
10887 }
10888 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10889 (set_attr "length" "4,4,8,8")])
10891 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10892 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10893 (match_operand 1 "" "g,g"))
10894 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10895 (clobber (reg:SI LR_REGNO))]
10896 "(DEFAULT_ABI == ABI_DARWIN
10897 || (DEFAULT_ABI == ABI_V4
10898 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10899 {
10900 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10901 output_asm_insn ("crxor 6,6,6", operands);
10903 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10904 output_asm_insn ("creqv 6,6,6", operands);
10906 #if TARGET_MACHO
10907 return output_call(insn, operands, 0, 2);
10908 #else
10909 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10910 {
10911 gcc_assert (!TARGET_SECURE_PLT);
10912 return "bl %z0@plt";
10913 }
10914 else
10915 return "bl %z0";
10916 #endif
10917 }
10918 "DEFAULT_ABI == ABI_V4
10919 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10920 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10921 [(parallel [(call (mem:SI (match_dup 0))
10922 (match_dup 1))
10923 (use (match_dup 2))
10924 (use (match_dup 3))
10925 (clobber (reg:SI LR_REGNO))])]
10926 {
10927 operands[3] = pic_offset_table_rtx;
10928 }
10929 [(set_attr "type" "branch,branch")
10930 (set_attr "length" "4,8")])
10932 (define_insn "*call_nonlocal_sysv_secure<mode>"
10933 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10934 (match_operand 1 "" "g,g"))
10935 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10936 (use (match_operand:SI 3 "register_operand" "r,r"))
10937 (clobber (reg:SI LR_REGNO))]
10938 "(DEFAULT_ABI == ABI_V4
10939 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10940 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10941 {
10942 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10943 output_asm_insn ("crxor 6,6,6", operands);
10945 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10946 output_asm_insn ("creqv 6,6,6", operands);
10948 if (flag_pic == 2)
10949 /* The magic 32768 offset here and in the other sysv call insns
10950 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10951 See sysv4.h:toc_section. */
10952 return "bl %z0+32768@plt";
10953 else
10954 return "bl %z0@plt";
10955 }
10956 [(set_attr "type" "branch,branch")
10957 (set_attr "length" "4,8")])
10959 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10960 [(set (match_operand 0 "" "")
10961 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10962 (match_operand 2 "" "g,g,g,g")))
10963 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10964 (clobber (reg:SI LR_REGNO))]
10965 "DEFAULT_ABI == ABI_V4
10966 || DEFAULT_ABI == ABI_DARWIN"
10967 {
10968 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10969 output_asm_insn ("crxor 6,6,6", operands);
10971 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10972 output_asm_insn ("creqv 6,6,6", operands);
10974 return "b%T1l";
10975 }
10976 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10977 (set_attr "length" "4,4,8,8")])
10979 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10980 [(set (match_operand 0 "" "")
10981 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10982 (match_operand 2 "" "g,g")))
10983 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10984 (clobber (reg:SI LR_REGNO))]
10985 "(DEFAULT_ABI == ABI_DARWIN
10986 || (DEFAULT_ABI == ABI_V4
10987 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10988 {
10989 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10990 output_asm_insn ("crxor 6,6,6", operands);
10992 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10993 output_asm_insn ("creqv 6,6,6", operands);
10995 #if TARGET_MACHO
10996 return output_call(insn, operands, 1, 3);
10997 #else
10998 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10999 {
11000 gcc_assert (!TARGET_SECURE_PLT);
11001 return "bl %z1@plt";
11002 }
11003 else
11004 return "bl %z1";
11005 #endif
11006 }
11007 "DEFAULT_ABI == ABI_V4
11008 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11009 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11010 [(parallel [(set (match_dup 0)
11011 (call (mem:SI (match_dup 1))
11012 (match_dup 2)))
11013 (use (match_dup 3))
11014 (use (match_dup 4))
11015 (clobber (reg:SI LR_REGNO))])]
11016 {
11017 operands[4] = pic_offset_table_rtx;
11018 }
11019 [(set_attr "type" "branch,branch")
11020 (set_attr "length" "4,8")])
11022 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11023 [(set (match_operand 0 "" "")
11024 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11025 (match_operand 2 "" "g,g")))
11026 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11027 (use (match_operand:SI 4 "register_operand" "r,r"))
11028 (clobber (reg:SI LR_REGNO))]
11029 "(DEFAULT_ABI == ABI_V4
11030 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11031 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11032 {
11033 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11034 output_asm_insn ("crxor 6,6,6", operands);
11036 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11037 output_asm_insn ("creqv 6,6,6", operands);
11039 if (flag_pic == 2)
11040 return "bl %z1+32768@plt";
11041 else
11042 return "bl %z1@plt";
11043 }
11044 [(set_attr "type" "branch,branch")
11045 (set_attr "length" "4,8")])
11048 ;; Call to AIX abi function in the same module.
11050 (define_insn "*call_local_aix<mode>"
11051 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11052 (match_operand 1 "" "g"))
11053 (clobber (reg:P LR_REGNO))]
11054 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11055 "bl %z0"
11056 [(set_attr "type" "branch")
11057 (set_attr "length" "4")])
11059 (define_insn "*call_value_local_aix<mode>"
11060 [(set (match_operand 0 "" "")
11061 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11062 (match_operand 2 "" "g")))
11063 (clobber (reg:P LR_REGNO))]
11064 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11065 "bl %z1"
11066 [(set_attr "type" "branch")
11067 (set_attr "length" "4")])
11069 ;; Call to AIX abi function which may be in another module.
11070 ;; Restore the TOC pointer (r2) after the call.
11072 (define_insn "*call_nonlocal_aix<mode>"
11073 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11074 (match_operand 1 "" "g"))
11075 (clobber (reg:P LR_REGNO))]
11076 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11077 "bl %z0\;nop"
11078 [(set_attr "type" "branch")
11079 (set_attr "length" "8")])
11081 (define_insn "*call_value_nonlocal_aix<mode>"
11082 [(set (match_operand 0 "" "")
11083 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11084 (match_operand 2 "" "g")))
11085 (clobber (reg:P LR_REGNO))]
11086 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11087 "bl %z1\;nop"
11088 [(set_attr "type" "branch")
11089 (set_attr "length" "8")])
11091 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11092 ;; Operand0 is the addresss of the function to call
11093 ;; Operand2 is the location in the function descriptor to load r2 from
11094 ;; Operand3 is the stack location to hold the current TOC pointer
11096 (define_insn "*call_indirect_aix<mode>"
11097 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11098 (match_operand 1 "" "g,g"))
11099 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11100 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11101 (clobber (reg:P LR_REGNO))]
11102 "DEFAULT_ABI == ABI_AIX"
11103 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11104 [(set_attr "type" "jmpreg")
11105 (set_attr "length" "12")])
11107 (define_insn "*call_value_indirect_aix<mode>"
11108 [(set (match_operand 0 "" "")
11109 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11110 (match_operand 2 "" "g,g")))
11111 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11112 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11113 (clobber (reg:P LR_REGNO))]
11114 "DEFAULT_ABI == ABI_AIX"
11115 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11116 [(set_attr "type" "jmpreg")
11117 (set_attr "length" "12")])
11119 ;; Call to indirect functions with the ELFv2 ABI.
11120 ;; Operand0 is the addresss of the function to call
11121 ;; Operand2 is the stack location to hold the current TOC pointer
11123 (define_insn "*call_indirect_elfv2<mode>"
11124 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11125 (match_operand 1 "" "g,g"))
11126 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11127 (clobber (reg:P LR_REGNO))]
11128 "DEFAULT_ABI == ABI_ELFv2"
11129 "b%T0l\;<ptrload> 2,%2"
11130 [(set_attr "type" "jmpreg")
11131 (set_attr "length" "8")])
11133 (define_insn "*call_value_indirect_elfv2<mode>"
11134 [(set (match_operand 0 "" "")
11135 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11136 (match_operand 2 "" "g,g")))
11137 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11138 (clobber (reg:P LR_REGNO))]
11139 "DEFAULT_ABI == ABI_ELFv2"
11140 "b%T1l\;<ptrload> 2,%3"
11141 [(set_attr "type" "jmpreg")
11142 (set_attr "length" "8")])
11145 ;; Call subroutine returning any type.
11146 (define_expand "untyped_call"
11147 [(parallel [(call (match_operand 0 "" "")
11148 (const_int 0))
11149 (match_operand 1 "" "")
11150 (match_operand 2 "" "")])]
11151 ""
11152 "
11153 {
11154 int i;
11156 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11158 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11159 {
11160 rtx set = XVECEXP (operands[2], 0, i);
11161 emit_move_insn (SET_DEST (set), SET_SRC (set));
11162 }
11164 /* The optimizer does not know that the call sets the function value
11165 registers we stored in the result block. We avoid problems by
11166 claiming that all hard registers are used and clobbered at this
11167 point. */
11168 emit_insn (gen_blockage ());
11170 DONE;
11171 }")
11173 ;; sibling call patterns
11174 (define_expand "sibcall"
11175 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11176 (match_operand 1 "" ""))
11177 (use (match_operand 2 "" ""))
11178 (use (reg:SI LR_REGNO))
11179 (simple_return)])]
11180 ""
11181 "
11182 {
11183 #if TARGET_MACHO
11184 if (MACHOPIC_INDIRECT)
11185 operands[0] = machopic_indirect_call_target (operands[0]);
11186 #endif
11188 gcc_assert (GET_CODE (operands[0]) == MEM);
11189 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11191 operands[0] = XEXP (operands[0], 0);
11193 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11194 {
11195 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11196 DONE;
11197 }
11198 }")
11200 (define_expand "sibcall_value"
11201 [(parallel [(set (match_operand 0 "register_operand" "")
11202 (call (mem:SI (match_operand 1 "address_operand" ""))
11203 (match_operand 2 "" "")))
11204 (use (match_operand 3 "" ""))
11205 (use (reg:SI LR_REGNO))
11206 (simple_return)])]
11207 ""
11208 "
11209 {
11210 #if TARGET_MACHO
11211 if (MACHOPIC_INDIRECT)
11212 operands[1] = machopic_indirect_call_target (operands[1]);
11213 #endif
11215 gcc_assert (GET_CODE (operands[1]) == MEM);
11216 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11218 operands[1] = XEXP (operands[1], 0);
11220 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11221 {
11222 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11223 DONE;
11224 }
11225 }")
11227 ;; this and similar patterns must be marked as using LR, otherwise
11228 ;; dataflow will try to delete the store into it. This is true
11229 ;; even when the actual reg to jump to is in CTR, when LR was
11230 ;; saved and restored around the PIC-setting BCL.
11231 (define_insn "*sibcall_local32"
11232 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11233 (match_operand 1 "" "g,g"))
11234 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11235 (use (reg:SI LR_REGNO))
11236 (simple_return)]
11237 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11238 "*
11239 {
11240 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11241 output_asm_insn (\"crxor 6,6,6\", operands);
11243 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11244 output_asm_insn (\"creqv 6,6,6\", operands);
11246 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11247 }"
11248 [(set_attr "type" "branch")
11249 (set_attr "length" "4,8")])
11251 (define_insn "*sibcall_local64"
11252 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11253 (match_operand 1 "" "g,g"))
11254 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11255 (use (reg:SI LR_REGNO))
11256 (simple_return)]
11257 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11258 "*
11259 {
11260 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11261 output_asm_insn (\"crxor 6,6,6\", operands);
11263 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11264 output_asm_insn (\"creqv 6,6,6\", operands);
11266 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11267 }"
11268 [(set_attr "type" "branch")
11269 (set_attr "length" "4,8")])
11271 (define_insn "*sibcall_value_local32"
11272 [(set (match_operand 0 "" "")
11273 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11274 (match_operand 2 "" "g,g")))
11275 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11276 (use (reg:SI LR_REGNO))
11277 (simple_return)]
11278 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11279 "*
11280 {
11281 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11282 output_asm_insn (\"crxor 6,6,6\", operands);
11284 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11285 output_asm_insn (\"creqv 6,6,6\", operands);
11287 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11288 }"
11289 [(set_attr "type" "branch")
11290 (set_attr "length" "4,8")])
11292 (define_insn "*sibcall_value_local64"
11293 [(set (match_operand 0 "" "")
11294 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11295 (match_operand 2 "" "g,g")))
11296 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11297 (use (reg:SI LR_REGNO))
11298 (simple_return)]
11299 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11300 "*
11301 {
11302 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11303 output_asm_insn (\"crxor 6,6,6\", operands);
11305 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11306 output_asm_insn (\"creqv 6,6,6\", operands);
11308 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11309 }"
11310 [(set_attr "type" "branch")
11311 (set_attr "length" "4,8")])
11313 (define_insn "*sibcall_nonlocal_sysv<mode>"
11314 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11315 (match_operand 1 "" ""))
11316 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11317 (use (reg:SI LR_REGNO))
11318 (simple_return)]
11319 "(DEFAULT_ABI == ABI_DARWIN
11320 || DEFAULT_ABI == ABI_V4)
11321 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11322 "*
11323 {
11324 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11325 output_asm_insn (\"crxor 6,6,6\", operands);
11327 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11328 output_asm_insn (\"creqv 6,6,6\", operands);
11330 if (which_alternative >= 2)
11331 return \"b%T0\";
11332 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11333 {
11334 gcc_assert (!TARGET_SECURE_PLT);
11335 return \"b %z0@plt\";
11336 }
11337 else
11338 return \"b %z0\";
11339 }"
11340 [(set_attr "type" "branch")
11341 (set_attr "length" "4,8,4,8")])
11343 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11344 [(set (match_operand 0 "" "")
11345 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11346 (match_operand 2 "" "")))
11347 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11348 (use (reg:SI LR_REGNO))
11349 (simple_return)]
11350 "(DEFAULT_ABI == ABI_DARWIN
11351 || DEFAULT_ABI == ABI_V4)
11352 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11353 "*
11354 {
11355 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11356 output_asm_insn (\"crxor 6,6,6\", operands);
11358 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11359 output_asm_insn (\"creqv 6,6,6\", operands);
11361 if (which_alternative >= 2)
11362 return \"b%T1\";
11363 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11364 {
11365 gcc_assert (!TARGET_SECURE_PLT);
11366 return \"b %z1@plt\";
11367 }
11368 else
11369 return \"b %z1\";
11370 }"
11371 [(set_attr "type" "branch")
11372 (set_attr "length" "4,8,4,8")])
11374 ;; AIX ABI sibling call patterns.
11376 (define_insn "*sibcall_aix<mode>"
11377 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11378 (match_operand 1 "" "g,g"))
11379 (simple_return)]
11380 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11381 "@
11382 b %z0
11383 b%T0"
11384 [(set_attr "type" "branch")
11385 (set_attr "length" "4")])
11387 (define_insn "*sibcall_value_aix<mode>"
11388 [(set (match_operand 0 "" "")
11389 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11390 (match_operand 2 "" "g,g")))
11391 (simple_return)]
11392 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11393 "@
11394 b %z1
11395 b%T1"
11396 [(set_attr "type" "branch")
11397 (set_attr "length" "4")])
11399 (define_expand "sibcall_epilogue"
11400 [(use (const_int 0))]
11401 ""
11402 {
11403 if (!TARGET_SCHED_PROLOG)
11404 emit_insn (gen_blockage ());
11405 rs6000_emit_epilogue (TRUE);
11406 DONE;
11407 })
11409 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11410 ;; all of memory. This blocks insns from being moved across this point.
11412 (define_insn "blockage"
11413 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11414 ""
11415 "")
11417 (define_expand "probe_stack"
11418 [(set (match_operand 0 "memory_operand" "=m")
11419 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11420 ""
11421 {
11422 if (TARGET_64BIT)
11423 emit_insn (gen_probe_stack_di (operands[0]));
11424 else
11425 emit_insn (gen_probe_stack_si (operands[0]));
11426 DONE;
11427 })
11429 (define_insn "probe_stack_<mode>"
11430 [(set (match_operand:P 0 "memory_operand" "=m")
11431 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11432 ""
11433 {
11434 operands[1] = gen_rtx_REG (Pmode, 0);
11435 return "st<wd>%U0%X0 %1,%0";
11436 }
11437 [(set_attr "type" "store")
11438 (set (attr "update")
11439 (if_then_else (match_operand 0 "update_address_mem")
11440 (const_string "yes")
11441 (const_string "no")))
11442 (set (attr "indexed")
11443 (if_then_else (match_operand 0 "indexed_address_mem")
11444 (const_string "yes")
11445 (const_string "no")))
11446 (set_attr "length" "4")])
11448 (define_insn "probe_stack_range<P:mode>"
11449 [(set (match_operand:P 0 "register_operand" "=r")
11450 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11451 (match_operand:P 2 "register_operand" "r")]
11452 UNSPECV_PROBE_STACK_RANGE))]
11453 ""
11454 "* return output_probe_stack_range (operands[0], operands[2]);"
11455 [(set_attr "type" "three")])
11456 \f
11457 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11458 ;; signed & unsigned, and one type of branch.
11459 ;;
11460 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11461 ;; insns, and branches.
11463 (define_expand "cbranch<mode>4"
11464 [(use (match_operator 0 "rs6000_cbranch_operator"
11465 [(match_operand:GPR 1 "gpc_reg_operand" "")
11466 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11467 (use (match_operand 3 ""))]
11468 ""
11469 "
11470 {
11471 /* Take care of the possibility that operands[2] might be negative but
11472 this might be a logical operation. That insn doesn't exist. */
11473 if (GET_CODE (operands[2]) == CONST_INT
11474 && INTVAL (operands[2]) < 0)
11475 {
11476 operands[2] = force_reg (<MODE>mode, operands[2]);
11477 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11478 GET_MODE (operands[0]),
11479 operands[1], operands[2]);
11480 }
11482 rs6000_emit_cbranch (<MODE>mode, operands);
11483 DONE;
11484 }")
11486 (define_expand "cbranch<mode>4"
11487 [(use (match_operator 0 "rs6000_cbranch_operator"
11488 [(match_operand:FP 1 "gpc_reg_operand" "")
11489 (match_operand:FP 2 "gpc_reg_operand" "")]))
11490 (use (match_operand 3 ""))]
11491 ""
11492 "
11493 {
11494 rs6000_emit_cbranch (<MODE>mode, operands);
11495 DONE;
11496 }")
11498 (define_expand "cstore<mode>4"
11499 [(use (match_operator 1 "rs6000_cbranch_operator"
11500 [(match_operand:GPR 2 "gpc_reg_operand" "")
11501 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11502 (clobber (match_operand:SI 0 "register_operand"))]
11503 ""
11504 "
11505 {
11506 /* Take care of the possibility that operands[3] might be negative but
11507 this might be a logical operation. That insn doesn't exist. */
11508 if (GET_CODE (operands[3]) == CONST_INT
11509 && INTVAL (operands[3]) < 0)
11510 {
11511 operands[3] = force_reg (<MODE>mode, operands[3]);
11512 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11513 GET_MODE (operands[1]),
11514 operands[2], operands[3]);
11515 }
11517 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11518 For SEQ, likewise, except that comparisons with zero should be done
11519 with an scc insns. However, due to the order that combine see the
11520 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11521 the cases we don't want to handle or are best handled by portable
11522 code. */
11523 if (GET_CODE (operands[1]) == NE)
11524 FAIL;
11525 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11526 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11527 && operands[3] == const0_rtx)
11528 FAIL;
11529 rs6000_emit_sCOND (<MODE>mode, operands);
11530 DONE;
11531 }")
11533 (define_expand "cstore<mode>4"
11534 [(use (match_operator 1 "rs6000_cbranch_operator"
11535 [(match_operand:FP 2 "gpc_reg_operand" "")
11536 (match_operand:FP 3 "gpc_reg_operand" "")]))
11537 (clobber (match_operand:SI 0 "register_operand"))]
11538 ""
11539 "
11540 {
11541 rs6000_emit_sCOND (<MODE>mode, operands);
11542 DONE;
11543 }")
11546 (define_expand "stack_protect_set"
11547 [(match_operand 0 "memory_operand" "")
11548 (match_operand 1 "memory_operand" "")]
11549 ""
11550 {
11551 #ifdef TARGET_THREAD_SSP_OFFSET
11552 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11553 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11554 operands[1] = gen_rtx_MEM (Pmode, addr);
11555 #endif
11556 if (TARGET_64BIT)
11557 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11558 else
11559 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11560 DONE;
11561 })
11563 (define_insn "stack_protect_setsi"
11564 [(set (match_operand:SI 0 "memory_operand" "=m")
11565 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11566 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11567 "TARGET_32BIT"
11568 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11569 [(set_attr "type" "three")
11570 (set_attr "length" "12")])
11572 (define_insn "stack_protect_setdi"
11573 [(set (match_operand:DI 0 "memory_operand" "=Y")
11574 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11575 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11576 "TARGET_64BIT"
11577 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11578 [(set_attr "type" "three")
11579 (set_attr "length" "12")])
11581 (define_expand "stack_protect_test"
11582 [(match_operand 0 "memory_operand" "")
11583 (match_operand 1 "memory_operand" "")
11584 (match_operand 2 "" "")]
11585 ""
11586 {
11587 rtx test, op0, op1;
11588 #ifdef TARGET_THREAD_SSP_OFFSET
11589 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11590 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11591 operands[1] = gen_rtx_MEM (Pmode, addr);
11592 #endif
11593 op0 = operands[0];
11594 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11595 test = gen_rtx_EQ (VOIDmode, op0, op1);
11596 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11597 DONE;
11598 })
11600 (define_insn "stack_protect_testsi"
11601 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11602 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11603 (match_operand:SI 2 "memory_operand" "m,m")]
11604 UNSPEC_SP_TEST))
11605 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11606 (clobber (match_scratch:SI 3 "=&r,&r"))]
11607 "TARGET_32BIT"
11608 "@
11609 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11610 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11611 [(set_attr "length" "16,20")])
11613 (define_insn "stack_protect_testdi"
11614 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11615 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11616 (match_operand:DI 2 "memory_operand" "Y,Y")]
11617 UNSPEC_SP_TEST))
11618 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11619 (clobber (match_scratch:DI 3 "=&r,&r"))]
11620 "TARGET_64BIT"
11621 "@
11622 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11623 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11624 [(set_attr "length" "16,20")])
11626 \f
11627 ;; Here are the actual compare insns.
11628 (define_insn "*cmp<mode>_internal1"
11629 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11630 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11631 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11632 ""
11633 "cmp<wd>%I2 %0,%1,%2"
11634 [(set_attr "type" "cmp")])
11636 ;; If we are comparing a register for equality with a large constant,
11637 ;; we can do this with an XOR followed by a compare. But this is profitable
11638 ;; only if the large constant is only used for the comparison (and in this
11639 ;; case we already have a register to reuse as scratch).
11640 ;;
11641 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11642 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11644 (define_peephole2
11645 [(set (match_operand:SI 0 "register_operand")
11646 (match_operand:SI 1 "logical_const_operand" ""))
11647 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11648 [(match_dup 0)
11649 (match_operand:SI 2 "logical_const_operand" "")]))
11650 (set (match_operand:CC 4 "cc_reg_operand" "")
11651 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11652 (match_dup 0)))
11653 (set (pc)
11654 (if_then_else (match_operator 6 "equality_operator"
11655 [(match_dup 4) (const_int 0)])
11656 (match_operand 7 "" "")
11657 (match_operand 8 "" "")))]
11658 "peep2_reg_dead_p (3, operands[0])
11659 && peep2_reg_dead_p (4, operands[4])"
11660 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11661 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11662 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11664 {
11665 /* Get the constant we are comparing against, and see what it looks like
11666 when sign-extended from 16 to 32 bits. Then see what constant we could
11667 XOR with SEXTC to get the sign-extended value. */
11668 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11669 SImode,
11670 operands[1], operands[2]);
11671 HOST_WIDE_INT c = INTVAL (cnst);
11672 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11673 HOST_WIDE_INT xorv = c ^ sextc;
11675 operands[9] = GEN_INT (xorv);
11676 operands[10] = GEN_INT (sextc);
11677 })
11679 (define_insn "*cmpsi_internal2"
11680 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11681 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11682 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11683 ""
11684 "cmplw%I2 %0,%1,%b2"
11685 [(set_attr "type" "cmp")])
11687 (define_insn "*cmpdi_internal2"
11688 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11689 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11690 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11691 ""
11692 "cmpld%I2 %0,%1,%b2"
11693 [(set_attr "type" "cmp")])
11695 ;; The following two insns don't exist as single insns, but if we provide
11696 ;; them, we can swap an add and compare, which will enable us to overlap more
11697 ;; of the required delay between a compare and branch. We generate code for
11698 ;; them by splitting.
11700 (define_insn ""
11701 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11702 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11703 (match_operand:SI 2 "short_cint_operand" "i")))
11704 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11705 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11706 ""
11707 "#"
11708 [(set_attr "length" "8")])
11710 (define_insn ""
11711 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11712 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11713 (match_operand:SI 2 "u_short_cint_operand" "i")))
11714 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11715 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11716 ""
11717 "#"
11718 [(set_attr "length" "8")])
11720 (define_split
11721 [(set (match_operand:CC 3 "cc_reg_operand" "")
11722 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11723 (match_operand:SI 2 "short_cint_operand" "")))
11724 (set (match_operand:SI 0 "gpc_reg_operand" "")
11725 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11726 ""
11727 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11728 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11730 (define_split
11731 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11732 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11733 (match_operand:SI 2 "u_short_cint_operand" "")))
11734 (set (match_operand:SI 0 "gpc_reg_operand" "")
11735 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11736 ""
11737 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11738 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11740 ;; Only need to compare second words if first words equal
11741 (define_insn "*cmptf_internal1"
11742 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11743 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11744 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11745 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11747 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11748 [(set_attr "type" "fpcompare")
11749 (set_attr "length" "12")])
11751 (define_insn_and_split "*cmptf_internal2"
11752 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11753 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11754 (match_operand:TF 2 "gpc_reg_operand" "d")))
11755 (clobber (match_scratch:DF 3 "=d"))
11756 (clobber (match_scratch:DF 4 "=d"))
11757 (clobber (match_scratch:DF 5 "=d"))
11758 (clobber (match_scratch:DF 6 "=d"))
11759 (clobber (match_scratch:DF 7 "=d"))
11760 (clobber (match_scratch:DF 8 "=d"))
11761 (clobber (match_scratch:DF 9 "=d"))
11762 (clobber (match_scratch:DF 10 "=d"))
11763 (clobber (match_scratch:GPR 11 "=b"))]
11764 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11765 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11766 "#"
11767 "&& reload_completed"
11768 [(set (match_dup 3) (match_dup 14))
11769 (set (match_dup 4) (match_dup 15))
11770 (set (match_dup 9) (abs:DF (match_dup 5)))
11771 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11772 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11773 (label_ref (match_dup 12))
11774 (pc)))
11775 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11776 (set (pc) (label_ref (match_dup 13)))
11777 (match_dup 12)
11778 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11779 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11780 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11781 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11782 (match_dup 13)]
11783 {
11784 REAL_VALUE_TYPE rv;
11785 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11786 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11788 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11789 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11790 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11791 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11792 operands[12] = gen_label_rtx ();
11793 operands[13] = gen_label_rtx ();
11794 real_inf (&rv);
11795 operands[14] = force_const_mem (DFmode,
11796 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11797 operands[15] = force_const_mem (DFmode,
11798 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11799 DFmode));
11800 if (TARGET_TOC)
11801 {
11802 rtx tocref;
11803 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11804 operands[14] = gen_const_mem (DFmode, tocref);
11805 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11806 operands[15] = gen_const_mem (DFmode, tocref);
11807 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11808 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11809 }
11810 })
11811 \f
11812 ;; Now we have the scc insns. We can do some combinations because of the
11813 ;; way the machine works.
11814 ;;
11815 ;; Note that this is probably faster if we can put an insn between the
11816 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11817 ;; cases the insns below which don't use an intermediate CR field will
11818 ;; be used instead.
11819 (define_insn ""
11820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11821 (match_operator:SI 1 "scc_comparison_operator"
11822 [(match_operand 2 "cc_reg_operand" "y")
11823 (const_int 0)]))]
11824 ""
11825 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11826 [(set (attr "type")
11827 (cond [(match_test "TARGET_MFCRF")
11828 (const_string "mfcrf")
11829 ]
11830 (const_string "mfcr")))
11831 (set_attr "length" "8")])
11833 ;; Same as above, but get the GT bit.
11834 (define_insn "move_from_CR_gt_bit"
11835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11836 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11837 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11838 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11839 [(set_attr "type" "mfcr")
11840 (set_attr "length" "8")])
11842 ;; Same as above, but get the OV/ORDERED bit.
11843 (define_insn "move_from_CR_ov_bit"
11844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11845 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11846 UNSPEC_MV_CR_OV))]
11847 "TARGET_ISEL"
11848 "mfcr %0\;rlwinm %0,%0,%t1,1"
11849 [(set_attr "type" "mfcr")
11850 (set_attr "length" "8")])
11852 (define_insn ""
11853 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11854 (match_operator:DI 1 "scc_comparison_operator"
11855 [(match_operand 2 "cc_reg_operand" "y")
11856 (const_int 0)]))]
11857 "TARGET_POWERPC64"
11858 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11859 [(set (attr "type")
11860 (cond [(match_test "TARGET_MFCRF")
11861 (const_string "mfcrf")
11862 ]
11863 (const_string "mfcr")))
11864 (set_attr "length" "8")])
11866 (define_insn ""
11867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11868 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11869 [(match_operand 2 "cc_reg_operand" "y,y")
11870 (const_int 0)])
11871 (const_int 0)))
11872 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11873 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11874 "TARGET_32BIT"
11875 "@
11876 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11877 #"
11878 [(set_attr "type" "shift")
11879 (set_attr "dot" "yes")
11880 (set_attr "length" "8,16")])
11882 (define_split
11883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11884 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11885 [(match_operand 2 "cc_reg_operand" "")
11886 (const_int 0)])
11887 (const_int 0)))
11888 (set (match_operand:SI 3 "gpc_reg_operand" "")
11889 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11890 "TARGET_32BIT && reload_completed"
11891 [(set (match_dup 3)
11892 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11893 (set (match_dup 0)
11894 (compare:CC (match_dup 3)
11895 (const_int 0)))]
11896 "")
11898 (define_insn ""
11899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11900 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11901 [(match_operand 2 "cc_reg_operand" "y")
11902 (const_int 0)])
11903 (match_operand:SI 3 "const_int_operand" "n")))]
11904 ""
11905 "*
11906 {
11907 int is_bit = ccr_bit (operands[1], 1);
11908 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11909 int count;
11911 if (is_bit >= put_bit)
11912 count = is_bit - put_bit;
11913 else
11914 count = 32 - (put_bit - is_bit);
11916 operands[4] = GEN_INT (count);
11917 operands[5] = GEN_INT (put_bit);
11919 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11920 }"
11921 [(set (attr "type")
11922 (cond [(match_test "TARGET_MFCRF")
11923 (const_string "mfcrf")
11924 ]
11925 (const_string "mfcr")))
11926 (set_attr "length" "8")])
11928 (define_insn ""
11929 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11930 (compare:CC
11931 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11932 [(match_operand 2 "cc_reg_operand" "y,y")
11933 (const_int 0)])
11934 (match_operand:SI 3 "const_int_operand" "n,n"))
11935 (const_int 0)))
11936 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11937 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11938 (match_dup 3)))]
11939 ""
11940 "*
11941 {
11942 int is_bit = ccr_bit (operands[1], 1);
11943 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11944 int count;
11946 /* Force split for non-cc0 compare. */
11947 if (which_alternative == 1)
11948 return \"#\";
11950 if (is_bit >= put_bit)
11951 count = is_bit - put_bit;
11952 else
11953 count = 32 - (put_bit - is_bit);
11955 operands[5] = GEN_INT (count);
11956 operands[6] = GEN_INT (put_bit);
11958 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11959 }"
11960 [(set_attr "type" "shift")
11961 (set_attr "dot" "yes")
11962 (set_attr "length" "8,16")])
11964 (define_split
11965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11966 (compare:CC
11967 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11968 [(match_operand 2 "cc_reg_operand" "")
11969 (const_int 0)])
11970 (match_operand:SI 3 "const_int_operand" ""))
11971 (const_int 0)))
11972 (set (match_operand:SI 4 "gpc_reg_operand" "")
11973 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11974 (match_dup 3)))]
11975 "reload_completed"
11976 [(set (match_dup 4)
11977 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11978 (match_dup 3)))
11979 (set (match_dup 0)
11980 (compare:CC (match_dup 4)
11981 (const_int 0)))]
11982 "")
11984 ;; There is a 3 cycle delay between consecutive mfcr instructions
11985 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11987 (define_peephole
11988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11989 (match_operator:SI 1 "scc_comparison_operator"
11990 [(match_operand 2 "cc_reg_operand" "y")
11991 (const_int 0)]))
11992 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11993 (match_operator:SI 4 "scc_comparison_operator"
11994 [(match_operand 5 "cc_reg_operand" "y")
11995 (const_int 0)]))]
11996 "REGNO (operands[2]) != REGNO (operands[5])"
11997 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11998 [(set_attr "type" "mfcr")
11999 (set_attr "length" "12")])
12001 (define_peephole
12002 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12003 (match_operator:DI 1 "scc_comparison_operator"
12004 [(match_operand 2 "cc_reg_operand" "y")
12005 (const_int 0)]))
12006 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12007 (match_operator:DI 4 "scc_comparison_operator"
12008 [(match_operand 5 "cc_reg_operand" "y")
12009 (const_int 0)]))]
12010 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12011 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12012 [(set_attr "type" "mfcr")
12013 (set_attr "length" "12")])
12015 ;; There are some scc insns that can be done directly, without a compare.
12016 ;; These are faster because they don't involve the communications between
12017 ;; the FXU and branch units. In fact, we will be replacing all of the
12018 ;; integer scc insns here or in the portable methods in emit_store_flag.
12019 ;;
12020 ;; Also support (neg (scc ..)) since that construct is used to replace
12021 ;; branches, (plus (scc ..) ..) since that construct is common and
12022 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12023 ;; cases where it is no more expensive than (neg (scc ..)).
12025 ;; Have reload force a constant into a register for the simple insns that
12026 ;; otherwise won't accept constants. We do this because it is faster than
12027 ;; the cmp/mfcr sequence we would otherwise generate.
12029 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12030 (DI "rKJI")])
12032 (define_insn_and_split "*eq<mode>"
12033 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12034 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12035 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12036 ""
12037 "#"
12038 ""
12039 [(set (match_dup 0)
12040 (clz:GPR (match_dup 3)))
12041 (set (match_dup 0)
12042 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12043 {
12044 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12045 {
12046 /* Use output operand as intermediate. */
12047 operands[3] = operands[0];
12049 if (logical_operand (operands[2], <MODE>mode))
12050 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12051 gen_rtx_XOR (<MODE>mode,
12052 operands[1], operands[2])));
12053 else
12054 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12055 gen_rtx_PLUS (<MODE>mode, operands[1],
12056 negate_rtx (<MODE>mode,
12057 operands[2]))));
12058 }
12059 else
12060 operands[3] = operands[1];
12062 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12063 })
12065 (define_insn_and_split "*eq<mode>_compare"
12066 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12067 (compare:CC
12068 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12069 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12070 (const_int 0)))
12071 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12072 (eq:P (match_dup 1) (match_dup 2)))]
12073 "optimize_size"
12074 "#"
12075 "optimize_size"
12076 [(set (match_dup 0)
12077 (clz:P (match_dup 4)))
12078 (parallel [(set (match_dup 3)
12079 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12080 (const_int 0)))
12081 (set (match_dup 0)
12082 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12083 {
12084 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12085 {
12086 /* Use output operand as intermediate. */
12087 operands[4] = operands[0];
12089 if (logical_operand (operands[2], <MODE>mode))
12090 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12091 gen_rtx_XOR (<MODE>mode,
12092 operands[1], operands[2])));
12093 else
12094 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12095 gen_rtx_PLUS (<MODE>mode, operands[1],
12096 negate_rtx (<MODE>mode,
12097 operands[2]))));
12098 }
12099 else
12100 operands[4] = operands[1];
12102 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12103 })
12105 ;; We have insns of the form shown by the first define_insn below. If
12106 ;; there is something inside the comparison operation, we must split it.
12107 (define_split
12108 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12109 (plus:SI (match_operator 1 "comparison_operator"
12110 [(match_operand:SI 2 "" "")
12111 (match_operand:SI 3
12112 "reg_or_cint_operand" "")])
12113 (match_operand:SI 4 "gpc_reg_operand" "")))
12114 (clobber (match_operand:SI 5 "register_operand" ""))]
12115 "! gpc_reg_operand (operands[2], SImode)"
12116 [(set (match_dup 5) (match_dup 2))
12117 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12118 (match_dup 4)))])
12120 (define_insn "*plus_eqsi"
12121 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12122 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12123 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12124 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12125 "TARGET_32BIT"
12126 "@
12127 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12128 subfic %0,%1,0\;addze %0,%3
12129 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12130 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12131 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12132 [(set_attr "type" "three,two,three,three,three")
12133 (set_attr "length" "12,8,12,12,12")])
12135 (define_insn "*compare_plus_eqsi"
12136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12137 (compare:CC
12138 (plus:SI
12139 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12140 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12141 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12142 (const_int 0)))
12143 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12144 "TARGET_32BIT && optimize_size"
12145 "@
12146 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12147 subfic %4,%1,0\;addze. %4,%3
12148 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12149 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12150 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12151 #
12152 #
12153 #
12154 #
12155 #"
12156 [(set_attr "type" "compare")
12157 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12159 (define_split
12160 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12161 (compare:CC
12162 (plus:SI
12163 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12164 (match_operand:SI 2 "scc_eq_operand" ""))
12165 (match_operand:SI 3 "gpc_reg_operand" ""))
12166 (const_int 0)))
12167 (clobber (match_scratch:SI 4 ""))]
12168 "TARGET_32BIT && optimize_size && reload_completed"
12169 [(set (match_dup 4)
12170 (plus:SI (eq:SI (match_dup 1)
12171 (match_dup 2))
12172 (match_dup 3)))
12173 (set (match_dup 0)
12174 (compare:CC (match_dup 4)
12175 (const_int 0)))]
12176 "")
12178 (define_insn "*plus_eqsi_compare"
12179 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12180 (compare:CC
12181 (plus:SI
12182 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12183 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12184 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12185 (const_int 0)))
12186 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12187 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12188 "TARGET_32BIT && optimize_size"
12189 "@
12190 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12191 subfic %0,%1,0\;addze. %0,%3
12192 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12193 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12194 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12195 #
12196 #
12197 #
12198 #
12199 #"
12200 [(set_attr "type" "compare")
12201 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12203 (define_split
12204 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12205 (compare:CC
12206 (plus:SI
12207 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12208 (match_operand:SI 2 "scc_eq_operand" ""))
12209 (match_operand:SI 3 "gpc_reg_operand" ""))
12210 (const_int 0)))
12211 (set (match_operand:SI 0 "gpc_reg_operand" "")
12212 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12213 "TARGET_32BIT && optimize_size && reload_completed"
12214 [(set (match_dup 0)
12215 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12216 (set (match_dup 4)
12217 (compare:CC (match_dup 0)
12218 (const_int 0)))]
12219 "")
12221 (define_insn "*neg_eq0<mode>"
12222 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12223 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12224 (const_int 0))))]
12225 ""
12226 "addic %0,%1,-1\;subfe %0,%0,%0"
12227 [(set_attr "type" "two")
12228 (set_attr "length" "8")])
12230 (define_insn_and_split "*neg_eq<mode>"
12231 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12232 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12233 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12234 ""
12235 "#"
12236 ""
12237 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12238 {
12239 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12240 {
12241 /* Use output operand as intermediate. */
12242 operands[3] = operands[0];
12244 if (logical_operand (operands[2], <MODE>mode))
12245 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12246 gen_rtx_XOR (<MODE>mode,
12247 operands[1], operands[2])));
12248 else
12249 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12250 gen_rtx_PLUS (<MODE>mode, operands[1],
12251 negate_rtx (<MODE>mode,
12252 operands[2]))));
12253 }
12254 else
12255 operands[3] = operands[1];
12256 })
12258 (define_insn "*ne0_<mode>"
12259 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12260 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12261 (const_int 0)))
12262 (clobber (match_scratch:P 2 "=&r"))]
12263 "!(TARGET_32BIT && TARGET_ISEL)"
12264 "addic %2,%1,-1\;subfe %0,%2,%1"
12265 [(set_attr "type" "two")
12266 (set_attr "length" "8")])
12268 (define_insn "*plus_ne0_<mode>"
12269 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12270 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12271 (const_int 0))
12272 (match_operand:P 2 "gpc_reg_operand" "r")))
12273 (clobber (match_scratch:P 3 "=&r"))]
12274 ""
12275 "addic %3,%1,-1\;addze %0,%2"
12276 [(set_attr "type" "two")
12277 (set_attr "length" "8")])
12279 (define_insn "*compare_plus_ne0_<mode>"
12280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12281 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12282 (const_int 0))
12283 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12284 (const_int 0)))
12285 (clobber (match_scratch:P 3 "=&r,&r"))
12286 (clobber (match_scratch:P 4 "=X,&r"))]
12287 ""
12288 "@
12289 addic %3,%1,-1\;addze. %3,%2
12290 #"
12291 [(set_attr "type" "compare")
12292 (set_attr "length" "8,12")])
12294 (define_split
12295 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12296 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12297 (const_int 0))
12298 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12299 (clobber (match_scratch:P 3 ""))
12300 (clobber (match_scratch:P 4 ""))]
12301 "reload_completed"
12302 [(parallel [(set (match_dup 3)
12303 (plus:P (ne:P (match_dup 1)
12304 (const_int 0))
12305 (match_dup 2)))
12306 (clobber (match_dup 4))])
12307 (set (match_dup 0)
12308 (compare:CC (match_dup 3)
12309 (const_int 0)))]
12310 "")
12312 ; For combine.
12313 (define_insn "*compare_plus_ne0_<mode>_1"
12314 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12315 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12316 (const_int 0))
12317 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12318 (clobber (match_scratch:P 3 "=&r,&r"))
12319 (clobber (match_scratch:P 4 "=X,&r"))]
12320 ""
12321 "@
12322 addic %3,%1,-1\;addze. %3,%2
12323 #"
12324 [(set_attr "type" "compare")
12325 (set_attr "length" "8,12")])
12327 (define_split
12328 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12329 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12330 (const_int 0))
12331 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12332 (clobber (match_scratch:P 3 ""))
12333 (clobber (match_scratch:P 4 ""))]
12334 "reload_completed"
12335 [(parallel [(set (match_dup 3)
12336 (plus:P (ne:P (match_dup 1)
12337 (const_int 0))
12338 (match_dup 2)))
12339 (clobber (match_dup 4))])
12340 (set (match_dup 0)
12341 (compare:CC (match_dup 3)
12342 (const_int 0)))]
12343 "")
12345 (define_insn "*plus_ne0_<mode>_compare"
12346 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12347 (compare:CC
12348 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12349 (const_int 0))
12350 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12351 (const_int 0)))
12352 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12353 (plus:P (ne:P (match_dup 1)
12354 (const_int 0))
12355 (match_dup 2)))
12356 (clobber (match_scratch:P 3 "=&r,&r"))]
12357 ""
12358 "@
12359 addic %3,%1,-1\;addze. %0,%2
12360 #"
12361 [(set_attr "type" "compare")
12362 (set_attr "length" "8,12")])
12364 (define_split
12365 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12366 (compare:CC
12367 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12368 (const_int 0))
12369 (match_operand:P 2 "gpc_reg_operand" ""))
12370 (const_int 0)))
12371 (set (match_operand:P 0 "gpc_reg_operand" "")
12372 (plus:P (ne:P (match_dup 1)
12373 (const_int 0))
12374 (match_dup 2)))
12375 (clobber (match_scratch:P 3 ""))]
12376 "reload_completed"
12377 [(parallel [(set (match_dup 0)
12378 (plus:P (ne:P (match_dup 1)
12379 (const_int 0))
12380 (match_dup 2)))
12381 (clobber (match_dup 3))])
12382 (set (match_dup 4)
12383 (compare:CC (match_dup 0)
12384 (const_int 0)))]
12385 "")
12387 (define_insn "*leu<mode>"
12388 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12389 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12390 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12391 ""
12392 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12393 [(set_attr "type" "three")
12394 (set_attr "length" "12")])
12396 (define_insn "*leu<mode>_compare"
12397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12398 (compare:CC
12399 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12400 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12401 (const_int 0)))
12402 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12403 (leu:P (match_dup 1) (match_dup 2)))]
12404 ""
12405 "@
12406 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12407 #"
12408 [(set_attr "type" "compare")
12409 (set_attr "length" "12,16")])
12411 (define_split
12412 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12413 (compare:CC
12414 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12415 (match_operand:P 2 "reg_or_short_operand" ""))
12416 (const_int 0)))
12417 (set (match_operand:P 0 "gpc_reg_operand" "")
12418 (leu:P (match_dup 1) (match_dup 2)))]
12419 "reload_completed"
12420 [(set (match_dup 0)
12421 (leu:P (match_dup 1) (match_dup 2)))
12422 (set (match_dup 3)
12423 (compare:CC (match_dup 0)
12424 (const_int 0)))]
12425 "")
12427 (define_insn "*plus_leu<mode>"
12428 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12429 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12430 (match_operand:P 2 "reg_or_short_operand" "rI"))
12431 (match_operand:P 3 "gpc_reg_operand" "r")))]
12432 ""
12433 "subf%I2c %0,%1,%2\;addze %0,%3"
12434 [(set_attr "type" "two")
12435 (set_attr "length" "8")])
12437 (define_insn ""
12438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12439 (compare:CC
12440 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12441 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12442 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12443 (const_int 0)))
12444 (clobber (match_scratch:SI 4 "=&r,&r"))]
12445 "TARGET_32BIT"
12446 "@
12447 subf%I2c %4,%1,%2\;addze. %4,%3
12448 #"
12449 [(set_attr "type" "compare")
12450 (set_attr "length" "8,12")])
12452 (define_split
12453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12454 (compare:CC
12455 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12456 (match_operand:SI 2 "reg_or_short_operand" ""))
12457 (match_operand:SI 3 "gpc_reg_operand" ""))
12458 (const_int 0)))
12459 (clobber (match_scratch:SI 4 ""))]
12460 "TARGET_32BIT && reload_completed"
12461 [(set (match_dup 4)
12462 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12463 (match_dup 3)))
12464 (set (match_dup 0)
12465 (compare:CC (match_dup 4)
12466 (const_int 0)))]
12467 "")
12469 (define_insn ""
12470 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12471 (compare:CC
12472 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12473 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12474 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12475 (const_int 0)))
12476 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12477 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12478 "TARGET_32BIT"
12479 "@
12480 subf%I2c %0,%1,%2\;addze. %0,%3
12481 #"
12482 [(set_attr "type" "compare")
12483 (set_attr "length" "8,12")])
12485 (define_split
12486 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12487 (compare:CC
12488 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12489 (match_operand:SI 2 "reg_or_short_operand" ""))
12490 (match_operand:SI 3 "gpc_reg_operand" ""))
12491 (const_int 0)))
12492 (set (match_operand:SI 0 "gpc_reg_operand" "")
12493 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12494 "TARGET_32BIT && reload_completed"
12495 [(set (match_dup 0)
12496 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12497 (set (match_dup 4)
12498 (compare:CC (match_dup 0)
12499 (const_int 0)))]
12500 "")
12502 (define_insn "*neg_leu<mode>"
12503 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12504 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12505 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12506 ""
12507 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12508 [(set_attr "type" "three")
12509 (set_attr "length" "12")])
12511 (define_insn "*and_neg_leu<mode>"
12512 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12513 (and:P (neg:P
12514 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12515 (match_operand:P 2 "reg_or_short_operand" "rI")))
12516 (match_operand:P 3 "gpc_reg_operand" "r")))]
12517 ""
12518 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12519 [(set_attr "type" "three")
12520 (set_attr "length" "12")])
12522 (define_insn ""
12523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12524 (compare:CC
12525 (and:SI (neg:SI
12526 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12527 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12528 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12529 (const_int 0)))
12530 (clobber (match_scratch:SI 4 "=&r,&r"))]
12531 "TARGET_32BIT"
12532 "@
12533 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12534 #"
12535 [(set_attr "type" "compare")
12536 (set_attr "length" "12,16")])
12538 (define_split
12539 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12540 (compare:CC
12541 (and:SI (neg:SI
12542 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12543 (match_operand:SI 2 "reg_or_short_operand" "")))
12544 (match_operand:SI 3 "gpc_reg_operand" ""))
12545 (const_int 0)))
12546 (clobber (match_scratch:SI 4 ""))]
12547 "TARGET_32BIT && reload_completed"
12548 [(set (match_dup 4)
12549 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12550 (match_dup 3)))
12551 (set (match_dup 0)
12552 (compare:CC (match_dup 4)
12553 (const_int 0)))]
12554 "")
12556 (define_insn ""
12557 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12558 (compare:CC
12559 (and:SI (neg:SI
12560 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12561 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12562 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12563 (const_int 0)))
12564 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12565 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12566 "TARGET_32BIT"
12567 "@
12568 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12569 #"
12570 [(set_attr "type" "compare")
12571 (set_attr "length" "12,16")])
12573 (define_split
12574 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12575 (compare:CC
12576 (and:SI (neg:SI
12577 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12578 (match_operand:SI 2 "reg_or_short_operand" "")))
12579 (match_operand:SI 3 "gpc_reg_operand" ""))
12580 (const_int 0)))
12581 (set (match_operand:SI 0 "gpc_reg_operand" "")
12582 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12583 "TARGET_32BIT && reload_completed"
12584 [(set (match_dup 0)
12585 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12586 (match_dup 3)))
12587 (set (match_dup 4)
12588 (compare:CC (match_dup 0)
12589 (const_int 0)))]
12590 "")
12592 (define_insn_and_split "*ltu<mode>"
12593 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12594 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12595 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12596 ""
12597 "#"
12598 ""
12599 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12600 (set (match_dup 0) (neg:P (match_dup 0)))]
12601 "")
12603 (define_insn_and_split "*ltu<mode>_compare"
12604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12605 (compare:CC
12606 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12607 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12608 (const_int 0)))
12609 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12610 (ltu:P (match_dup 1) (match_dup 2)))]
12611 ""
12612 "#"
12613 ""
12614 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12615 (parallel [(set (match_dup 3)
12616 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12617 (set (match_dup 0) (neg:P (match_dup 0)))])]
12618 "")
12620 (define_insn_and_split "*plus_ltu<mode>"
12621 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12622 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12623 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12624 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12625 ""
12626 "#"
12627 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12628 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12629 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12630 "")
12632 (define_insn_and_split "*plus_ltu<mode>_compare"
12633 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12634 (compare:CC
12635 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12636 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12637 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12638 (const_int 0)))
12639 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12640 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12641 ""
12642 "#"
12643 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12644 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12645 (parallel [(set (match_dup 4)
12646 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12647 (const_int 0)))
12648 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12649 "")
12651 (define_insn "*neg_ltu<mode>"
12652 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12653 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12654 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12655 ""
12656 "@
12657 subfc %0,%2,%1\;subfe %0,%0,%0
12658 addic %0,%1,%n2\;subfe %0,%0,%0"
12659 [(set_attr "type" "two")
12660 (set_attr "length" "8")])
12662 (define_insn "*geu<mode>"
12663 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12664 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12665 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12666 ""
12667 "@
12668 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12669 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12670 [(set_attr "type" "three")
12671 (set_attr "length" "12")])
12673 (define_insn "*geu<mode>_compare"
12674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12675 (compare:CC
12676 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12677 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12678 (const_int 0)))
12679 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12680 (geu:P (match_dup 1) (match_dup 2)))]
12681 ""
12682 "@
12683 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12684 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12685 #
12686 #"
12687 [(set_attr "type" "compare")
12688 (set_attr "length" "12,12,16,16")])
12690 (define_split
12691 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12692 (compare:CC
12693 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12694 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12695 (const_int 0)))
12696 (set (match_operand:P 0 "gpc_reg_operand" "")
12697 (geu:P (match_dup 1) (match_dup 2)))]
12698 "reload_completed"
12699 [(set (match_dup 0)
12700 (geu:P (match_dup 1) (match_dup 2)))
12701 (set (match_dup 3)
12702 (compare:CC (match_dup 0)
12703 (const_int 0)))]
12704 "")
12706 (define_insn "*plus_geu<mode>"
12707 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12708 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12709 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12710 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12711 ""
12712 "@
12713 subfc %0,%2,%1\;addze %0,%3
12714 addic %0,%1,%n2\;addze %0,%3"
12715 [(set_attr "type" "two")
12716 (set_attr "length" "8")])
12718 (define_insn ""
12719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12720 (compare:CC
12721 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12722 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12723 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12724 (const_int 0)))
12725 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12726 "TARGET_32BIT"
12727 "@
12728 subfc %4,%2,%1\;addze. %4,%3
12729 addic %4,%1,%n2\;addze. %4,%3
12730 #
12731 #"
12732 [(set_attr "type" "compare")
12733 (set_attr "length" "8,8,12,12")])
12735 (define_split
12736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12737 (compare:CC
12738 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12739 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12740 (match_operand:SI 3 "gpc_reg_operand" ""))
12741 (const_int 0)))
12742 (clobber (match_scratch:SI 4 ""))]
12743 "TARGET_32BIT && reload_completed"
12744 [(set (match_dup 4)
12745 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12746 (match_dup 3)))
12747 (set (match_dup 0)
12748 (compare:CC (match_dup 4)
12749 (const_int 0)))]
12750 "")
12752 (define_insn ""
12753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12754 (compare:CC
12755 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12756 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12757 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12758 (const_int 0)))
12759 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12760 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12761 "TARGET_32BIT"
12762 "@
12763 subfc %0,%2,%1\;addze. %0,%3
12764 addic %0,%1,%n2\;addze. %0,%3
12765 #
12766 #"
12767 [(set_attr "type" "compare")
12768 (set_attr "length" "8,8,12,12")])
12770 (define_split
12771 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12772 (compare:CC
12773 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12774 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12775 (match_operand:SI 3 "gpc_reg_operand" ""))
12776 (const_int 0)))
12777 (set (match_operand:SI 0 "gpc_reg_operand" "")
12778 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12779 "TARGET_32BIT && reload_completed"
12780 [(set (match_dup 0)
12781 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12782 (set (match_dup 4)
12783 (compare:CC (match_dup 0)
12784 (const_int 0)))]
12785 "")
12787 (define_insn "*neg_geu<mode>"
12788 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12789 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12790 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12791 ""
12792 "@
12793 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12794 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12795 [(set_attr "type" "three")
12796 (set_attr "length" "12")])
12798 (define_insn "*and_neg_geu<mode>"
12799 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12800 (and:P (neg:P
12801 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12802 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12803 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12804 ""
12805 "@
12806 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12807 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12808 [(set_attr "type" "three")
12809 (set_attr "length" "12")])
12811 (define_insn ""
12812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12813 (compare:CC
12814 (and:SI (neg:SI
12815 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12816 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12817 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12818 (const_int 0)))
12819 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12820 "TARGET_32BIT"
12821 "@
12822 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12823 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12824 #
12825 #"
12826 [(set_attr "type" "compare")
12827 (set_attr "length" "12,12,16,16")])
12829 (define_split
12830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12831 (compare:CC
12832 (and:SI (neg:SI
12833 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12834 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12835 (match_operand:SI 3 "gpc_reg_operand" ""))
12836 (const_int 0)))
12837 (clobber (match_scratch:SI 4 ""))]
12838 "TARGET_32BIT && reload_completed"
12839 [(set (match_dup 4)
12840 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12841 (match_dup 3)))
12842 (set (match_dup 0)
12843 (compare:CC (match_dup 4)
12844 (const_int 0)))]
12845 "")
12847 (define_insn ""
12848 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12849 (compare:CC
12850 (and:SI (neg:SI
12851 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12852 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12853 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12854 (const_int 0)))
12855 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12856 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12857 "TARGET_32BIT"
12858 "@
12859 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12860 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12861 #
12862 #"
12863 [(set_attr "type" "compare")
12864 (set_attr "length" "12,12,16,16")])
12866 (define_split
12867 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12868 (compare:CC
12869 (and:SI (neg:SI
12870 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12871 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12872 (match_operand:SI 3 "gpc_reg_operand" ""))
12873 (const_int 0)))
12874 (set (match_operand:SI 0 "gpc_reg_operand" "")
12875 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12876 "TARGET_32BIT && reload_completed"
12877 [(set (match_dup 0)
12878 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12879 (set (match_dup 4)
12880 (compare:CC (match_dup 0)
12881 (const_int 0)))]
12882 "")
12884 (define_insn "*plus_gt0<mode>"
12885 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12886 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12887 (const_int 0))
12888 (match_operand:P 2 "gpc_reg_operand" "r")))]
12889 ""
12890 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12891 [(set_attr "type" "three")
12892 (set_attr "length" "12")])
12894 (define_insn ""
12895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12896 (compare:CC
12897 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12898 (const_int 0))
12899 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12900 (const_int 0)))
12901 (clobber (match_scratch:SI 3 "=&r,&r"))]
12902 "TARGET_32BIT"
12903 "@
12904 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12905 #"
12906 [(set_attr "type" "compare")
12907 (set_attr "length" "12,16")])
12909 (define_split
12910 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12911 (compare:CC
12912 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12913 (const_int 0))
12914 (match_operand:SI 2 "gpc_reg_operand" ""))
12915 (const_int 0)))
12916 (clobber (match_scratch:SI 3 ""))]
12917 "TARGET_32BIT && reload_completed"
12918 [(set (match_dup 3)
12919 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12920 (match_dup 2)))
12921 (set (match_dup 0)
12922 (compare:CC (match_dup 3)
12923 (const_int 0)))]
12924 "")
12926 (define_insn ""
12927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12928 (compare:CC
12929 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12930 (const_int 0))
12931 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12932 (const_int 0)))
12933 (clobber (match_scratch:DI 3 "=&r,&r"))]
12934 "TARGET_64BIT"
12935 "@
12936 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12937 #"
12938 [(set_attr "type" "compare")
12939 (set_attr "length" "12,16")])
12941 (define_split
12942 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12943 (compare:CC
12944 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12945 (const_int 0))
12946 (match_operand:DI 2 "gpc_reg_operand" ""))
12947 (const_int 0)))
12948 (clobber (match_scratch:DI 3 ""))]
12949 "TARGET_64BIT && reload_completed"
12950 [(set (match_dup 3)
12951 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12952 (match_dup 2)))
12953 (set (match_dup 0)
12954 (compare:CC (match_dup 3)
12955 (const_int 0)))]
12956 "")
12958 (define_insn ""
12959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12960 (compare:CC
12961 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12962 (const_int 0))
12963 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12964 (const_int 0)))
12965 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12966 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12967 "TARGET_32BIT"
12968 "@
12969 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12970 #"
12971 [(set_attr "type" "compare")
12972 (set_attr "length" "12,16")])
12974 (define_split
12975 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12976 (compare:CC
12977 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12978 (const_int 0))
12979 (match_operand:SI 2 "gpc_reg_operand" ""))
12980 (const_int 0)))
12981 (set (match_operand:SI 0 "gpc_reg_operand" "")
12982 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12983 "TARGET_32BIT && reload_completed"
12984 [(set (match_dup 0)
12985 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12986 (set (match_dup 3)
12987 (compare:CC (match_dup 0)
12988 (const_int 0)))]
12989 "")
12991 (define_insn ""
12992 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12993 (compare:CC
12994 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12995 (const_int 0))
12996 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12997 (const_int 0)))
12998 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12999 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13000 "TARGET_64BIT"
13001 "@
13002 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13003 #"
13004 [(set_attr "type" "compare")
13005 (set_attr "length" "12,16")])
13007 (define_split
13008 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13009 (compare:CC
13010 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13011 (const_int 0))
13012 (match_operand:DI 2 "gpc_reg_operand" ""))
13013 (const_int 0)))
13014 (set (match_operand:DI 0 "gpc_reg_operand" "")
13015 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13016 "TARGET_64BIT && reload_completed"
13017 [(set (match_dup 0)
13018 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13019 (set (match_dup 3)
13020 (compare:CC (match_dup 0)
13021 (const_int 0)))]
13022 "")
13024 (define_insn_and_split "*gtu<mode>"
13025 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13026 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13027 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13028 ""
13029 "#"
13030 ""
13031 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13032 (set (match_dup 0) (neg:P (match_dup 0)))]
13033 "")
13035 (define_insn_and_split "*gtu<mode>_compare"
13036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13037 (compare:CC
13038 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13039 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13040 (const_int 0)))
13041 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13042 (gtu:P (match_dup 1) (match_dup 2)))]
13043 ""
13044 "#"
13045 ""
13046 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13047 (parallel [(set (match_dup 3)
13048 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13049 (set (match_dup 0) (neg:P (match_dup 0)))])]
13050 "")
13052 (define_insn_and_split "*plus_gtu<mode>"
13053 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13054 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13055 (match_operand:P 2 "reg_or_short_operand" "rI"))
13056 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13057 ""
13058 "#"
13059 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13060 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13061 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13062 "")
13064 (define_insn_and_split "*plus_gtu<mode>_compare"
13065 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13066 (compare:CC
13067 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13068 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13069 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13070 (const_int 0)))
13071 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13072 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13073 ""
13074 "#"
13075 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13076 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13077 (parallel [(set (match_dup 4)
13078 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13079 (const_int 0)))
13080 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13081 "")
13083 (define_insn "*neg_gtu<mode>"
13084 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13085 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13086 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13087 ""
13088 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13089 [(set_attr "type" "two")
13090 (set_attr "length" "8")])
13092 \f
13093 ;; Define both directions of branch and return. If we need a reload
13094 ;; register, we'd rather use CR0 since it is much easier to copy a
13095 ;; register CC value to there.
13097 (define_insn ""
13098 [(set (pc)
13099 (if_then_else (match_operator 1 "branch_comparison_operator"
13100 [(match_operand 2
13101 "cc_reg_operand" "y")
13102 (const_int 0)])
13103 (label_ref (match_operand 0 "" ""))
13104 (pc)))]
13105 ""
13106 "*
13107 {
13108 return output_cbranch (operands[1], \"%l0\", 0, insn);
13109 }"
13110 [(set_attr "type" "branch")])
13112 (define_insn ""
13113 [(set (pc)
13114 (if_then_else (match_operator 0 "branch_comparison_operator"
13115 [(match_operand 1
13116 "cc_reg_operand" "y")
13117 (const_int 0)])
13118 (any_return)
13119 (pc)))]
13120 "<return_pred>"
13121 "*
13122 {
13123 return output_cbranch (operands[0], NULL, 0, insn);
13124 }"
13125 [(set_attr "type" "jmpreg")
13126 (set_attr "length" "4")])
13128 (define_insn ""
13129 [(set (pc)
13130 (if_then_else (match_operator 1 "branch_comparison_operator"
13131 [(match_operand 2
13132 "cc_reg_operand" "y")
13133 (const_int 0)])
13134 (pc)
13135 (label_ref (match_operand 0 "" ""))))]
13136 ""
13137 "*
13138 {
13139 return output_cbranch (operands[1], \"%l0\", 1, insn);
13140 }"
13141 [(set_attr "type" "branch")])
13143 (define_insn ""
13144 [(set (pc)
13145 (if_then_else (match_operator 0 "branch_comparison_operator"
13146 [(match_operand 1
13147 "cc_reg_operand" "y")
13148 (const_int 0)])
13149 (pc)
13150 (any_return)))]
13151 "<return_pred>"
13152 "*
13153 {
13154 return output_cbranch (operands[0], NULL, 1, insn);
13155 }"
13156 [(set_attr "type" "jmpreg")
13157 (set_attr "length" "4")])
13159 ;; Logic on condition register values.
13161 ; This pattern matches things like
13162 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13163 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13164 ; (const_int 1)))
13165 ; which are generated by the branch logic.
13166 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13168 (define_insn "*cceq_ior_compare"
13169 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13170 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13171 [(match_operator:SI 2
13172 "branch_positive_comparison_operator"
13173 [(match_operand 3
13174 "cc_reg_operand" "y,y")
13175 (const_int 0)])
13176 (match_operator:SI 4
13177 "branch_positive_comparison_operator"
13178 [(match_operand 5
13179 "cc_reg_operand" "0,y")
13180 (const_int 0)])])
13181 (const_int 1)))]
13182 ""
13183 "cr%q1 %E0,%j2,%j4"
13184 [(set_attr "type" "cr_logical,delayed_cr")])
13186 ; Why is the constant -1 here, but 1 in the previous pattern?
13187 ; Because ~1 has all but the low bit set.
13188 (define_insn ""
13189 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13190 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13191 [(not:SI (match_operator:SI 2
13192 "branch_positive_comparison_operator"
13193 [(match_operand 3
13194 "cc_reg_operand" "y,y")
13195 (const_int 0)]))
13196 (match_operator:SI 4
13197 "branch_positive_comparison_operator"
13198 [(match_operand 5
13199 "cc_reg_operand" "0,y")
13200 (const_int 0)])])
13201 (const_int -1)))]
13202 ""
13203 "cr%q1 %E0,%j2,%j4"
13204 [(set_attr "type" "cr_logical,delayed_cr")])
13206 (define_insn "*cceq_rev_compare"
13207 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13208 (compare:CCEQ (match_operator:SI 1
13209 "branch_positive_comparison_operator"
13210 [(match_operand 2
13211 "cc_reg_operand" "0,y")
13212 (const_int 0)])
13213 (const_int 0)))]
13214 ""
13215 "crnot %E0,%j1"
13216 [(set_attr "type" "cr_logical,delayed_cr")])
13218 ;; If we are comparing the result of two comparisons, this can be done
13219 ;; using creqv or crxor.
13221 (define_insn_and_split ""
13222 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13223 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13224 [(match_operand 2 "cc_reg_operand" "y")
13225 (const_int 0)])
13226 (match_operator 3 "branch_comparison_operator"
13227 [(match_operand 4 "cc_reg_operand" "y")
13228 (const_int 0)])))]
13229 ""
13230 "#"
13231 ""
13232 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13233 (match_dup 5)))]
13234 "
13235 {
13236 int positive_1, positive_2;
13238 positive_1 = branch_positive_comparison_operator (operands[1],
13239 GET_MODE (operands[1]));
13240 positive_2 = branch_positive_comparison_operator (operands[3],
13241 GET_MODE (operands[3]));
13243 if (! positive_1)
13244 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13245 GET_CODE (operands[1])),
13246 SImode,
13247 operands[2], const0_rtx);
13248 else if (GET_MODE (operands[1]) != SImode)
13249 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13250 operands[2], const0_rtx);
13252 if (! positive_2)
13253 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13254 GET_CODE (operands[3])),
13255 SImode,
13256 operands[4], const0_rtx);
13257 else if (GET_MODE (operands[3]) != SImode)
13258 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13259 operands[4], const0_rtx);
13261 if (positive_1 == positive_2)
13262 {
13263 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13264 operands[5] = constm1_rtx;
13265 }
13266 else
13267 {
13268 operands[5] = const1_rtx;
13269 }
13270 }")
13272 ;; Unconditional branch and return.
13274 (define_insn "jump"
13275 [(set (pc)
13276 (label_ref (match_operand 0 "" "")))]
13277 ""
13278 "b %l0"
13279 [(set_attr "type" "branch")])
13281 (define_insn "<return_str>return"
13282 [(any_return)]
13283 "<return_pred>"
13284 "blr"
13285 [(set_attr "type" "jmpreg")])
13287 (define_expand "indirect_jump"
13288 [(set (pc) (match_operand 0 "register_operand" ""))])
13290 (define_insn "*indirect_jump<mode>"
13291 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13292 ""
13293 "@
13294 bctr
13295 blr"
13296 [(set_attr "type" "jmpreg")])
13298 ;; Table jump for switch statements:
13299 (define_expand "tablejump"
13300 [(use (match_operand 0 "" ""))
13301 (use (label_ref (match_operand 1 "" "")))]
13302 ""
13303 "
13304 {
13305 if (TARGET_32BIT)
13306 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13307 else
13308 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13309 DONE;
13310 }")
13312 (define_expand "tablejumpsi"
13313 [(set (match_dup 3)
13314 (plus:SI (match_operand:SI 0 "" "")
13315 (match_dup 2)))
13316 (parallel [(set (pc) (match_dup 3))
13317 (use (label_ref (match_operand 1 "" "")))])]
13318 "TARGET_32BIT"
13319 "
13320 { operands[0] = force_reg (SImode, operands[0]);
13321 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13322 operands[3] = gen_reg_rtx (SImode);
13323 }")
13325 (define_expand "tablejumpdi"
13326 [(set (match_dup 4)
13327 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13328 (set (match_dup 3)
13329 (plus:DI (match_dup 4)
13330 (match_dup 2)))
13331 (parallel [(set (pc) (match_dup 3))
13332 (use (label_ref (match_operand 1 "" "")))])]
13333 "TARGET_64BIT"
13334 "
13335 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13336 operands[3] = gen_reg_rtx (DImode);
13337 operands[4] = gen_reg_rtx (DImode);
13338 }")
13340 (define_insn "*tablejump<mode>_internal1"
13341 [(set (pc)
13342 (match_operand:P 0 "register_operand" "c,*l"))
13343 (use (label_ref (match_operand 1 "" "")))]
13344 ""
13345 "@
13346 bctr
13347 blr"
13348 [(set_attr "type" "jmpreg")])
13350 (define_insn "nop"
13351 [(const_int 0)]
13352 ""
13353 "nop")
13355 (define_insn "group_ending_nop"
13356 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13357 ""
13358 "*
13359 {
13360 if (rs6000_cpu_attr == CPU_POWER6)
13361 return \"ori 1,1,0\";
13362 return \"ori 2,2,0\";
13363 }")
13364 \f
13365 ;; Define the subtract-one-and-jump insns, starting with the template
13366 ;; so loop.c knows what to generate.
13368 (define_expand "doloop_end"
13369 [(use (match_operand 0 "" "")) ; loop pseudo
13370 (use (match_operand 1 "" ""))] ; label
13371 ""
13372 "
13373 {
13374 if (TARGET_64BIT)
13375 {
13376 if (GET_MODE (operands[0]) != DImode)
13377 FAIL;
13378 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13379 }
13380 else
13381 {
13382 if (GET_MODE (operands[0]) != SImode)
13383 FAIL;
13384 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13385 }
13386 DONE;
13387 }")
13389 (define_expand "ctr<mode>"
13390 [(parallel [(set (pc)
13391 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13392 (const_int 1))
13393 (label_ref (match_operand 1 "" ""))
13394 (pc)))
13395 (set (match_dup 0)
13396 (plus:P (match_dup 0)
13397 (const_int -1)))
13398 (clobber (match_scratch:CC 2 ""))
13399 (clobber (match_scratch:P 3 ""))])]
13400 ""
13401 "")
13403 ;; We need to be able to do this for any operand, including MEM, or we
13404 ;; will cause reload to blow up since we don't allow output reloads on
13405 ;; JUMP_INSNs.
13406 ;; For the length attribute to be calculated correctly, the
13407 ;; label MUST be operand 0.
13409 (define_insn "*ctr<mode>_internal1"
13410 [(set (pc)
13411 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13412 (const_int 1))
13413 (label_ref (match_operand 0 "" ""))
13414 (pc)))
13415 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13416 (plus:P (match_dup 1)
13417 (const_int -1)))
13418 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13419 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13420 ""
13421 "*
13422 {
13423 if (which_alternative != 0)
13424 return \"#\";
13425 else if (get_attr_length (insn) == 4)
13426 return \"bdnz %l0\";
13427 else
13428 return \"bdz $+8\;b %l0\";
13429 }"
13430 [(set_attr "type" "branch")
13431 (set_attr "length" "*,12,16,16")])
13433 (define_insn "*ctr<mode>_internal2"
13434 [(set (pc)
13435 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13436 (const_int 1))
13437 (pc)
13438 (label_ref (match_operand 0 "" ""))))
13439 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13440 (plus:P (match_dup 1)
13441 (const_int -1)))
13442 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13443 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13444 ""
13445 "*
13446 {
13447 if (which_alternative != 0)
13448 return \"#\";
13449 else if (get_attr_length (insn) == 4)
13450 return \"bdz %l0\";
13451 else
13452 return \"bdnz $+8\;b %l0\";
13453 }"
13454 [(set_attr "type" "branch")
13455 (set_attr "length" "*,12,16,16")])
13457 ;; Similar but use EQ
13459 (define_insn "*ctr<mode>_internal5"
13460 [(set (pc)
13461 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13462 (const_int 1))
13463 (label_ref (match_operand 0 "" ""))
13464 (pc)))
13465 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13466 (plus:P (match_dup 1)
13467 (const_int -1)))
13468 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13469 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13470 ""
13471 "*
13472 {
13473 if (which_alternative != 0)
13474 return \"#\";
13475 else if (get_attr_length (insn) == 4)
13476 return \"bdz %l0\";
13477 else
13478 return \"bdnz $+8\;b %l0\";
13479 }"
13480 [(set_attr "type" "branch")
13481 (set_attr "length" "*,12,16,16")])
13483 (define_insn "*ctr<mode>_internal6"
13484 [(set (pc)
13485 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13486 (const_int 1))
13487 (pc)
13488 (label_ref (match_operand 0 "" ""))))
13489 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13490 (plus:P (match_dup 1)
13491 (const_int -1)))
13492 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13493 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13494 ""
13495 "*
13496 {
13497 if (which_alternative != 0)
13498 return \"#\";
13499 else if (get_attr_length (insn) == 4)
13500 return \"bdnz %l0\";
13501 else
13502 return \"bdz $+8\;b %l0\";
13503 }"
13504 [(set_attr "type" "branch")
13505 (set_attr "length" "*,12,16,16")])
13507 ;; Now the splitters if we could not allocate the CTR register
13509 (define_split
13510 [(set (pc)
13511 (if_then_else (match_operator 2 "comparison_operator"
13512 [(match_operand:P 1 "gpc_reg_operand" "")
13513 (const_int 1)])
13514 (match_operand 5 "" "")
13515 (match_operand 6 "" "")))
13516 (set (match_operand:P 0 "gpc_reg_operand" "")
13517 (plus:P (match_dup 1) (const_int -1)))
13518 (clobber (match_scratch:CC 3 ""))
13519 (clobber (match_scratch:P 4 ""))]
13520 "reload_completed"
13521 [(parallel [(set (match_dup 3)
13522 (compare:CC (plus:P (match_dup 1)
13523 (const_int -1))
13524 (const_int 0)))
13525 (set (match_dup 0)
13526 (plus:P (match_dup 1)
13527 (const_int -1)))])
13528 (set (pc) (if_then_else (match_dup 7)
13529 (match_dup 5)
13530 (match_dup 6)))]
13531 "
13532 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13533 operands[3], const0_rtx); }")
13535 (define_split
13536 [(set (pc)
13537 (if_then_else (match_operator 2 "comparison_operator"
13538 [(match_operand:P 1 "gpc_reg_operand" "")
13539 (const_int 1)])
13540 (match_operand 5 "" "")
13541 (match_operand 6 "" "")))
13542 (set (match_operand:P 0 "nonimmediate_operand" "")
13543 (plus:P (match_dup 1) (const_int -1)))
13544 (clobber (match_scratch:CC 3 ""))
13545 (clobber (match_scratch:P 4 ""))]
13546 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13547 [(parallel [(set (match_dup 3)
13548 (compare:CC (plus:P (match_dup 1)
13549 (const_int -1))
13550 (const_int 0)))
13551 (set (match_dup 4)
13552 (plus:P (match_dup 1)
13553 (const_int -1)))])
13554 (set (match_dup 0)
13555 (match_dup 4))
13556 (set (pc) (if_then_else (match_dup 7)
13557 (match_dup 5)
13558 (match_dup 6)))]
13559 "
13560 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13561 operands[3], const0_rtx); }")
13562 \f
13563 (define_insn "trap"
13564 [(trap_if (const_int 1) (const_int 0))]
13565 ""
13566 "trap"
13567 [(set_attr "type" "trap")])
13569 (define_expand "ctrap<mode>4"
13570 [(trap_if (match_operator 0 "ordered_comparison_operator"
13571 [(match_operand:GPR 1 "register_operand")
13572 (match_operand:GPR 2 "reg_or_short_operand")])
13573 (match_operand 3 "zero_constant" ""))]
13574 ""
13575 "")
13577 (define_insn ""
13578 [(trap_if (match_operator 0 "ordered_comparison_operator"
13579 [(match_operand:GPR 1 "register_operand" "r")
13580 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13581 (const_int 0))]
13582 ""
13583 "t<wd>%V0%I2 %1,%2"
13584 [(set_attr "type" "trap")])
13585 \f
13586 ;; Insns related to generating the function prologue and epilogue.
13588 (define_expand "prologue"
13589 [(use (const_int 0))]
13590 ""
13591 {
13592 rs6000_emit_prologue ();
13593 if (!TARGET_SCHED_PROLOG)
13594 emit_insn (gen_blockage ());
13595 DONE;
13596 })
13598 (define_insn "*movesi_from_cr_one"
13599 [(match_parallel 0 "mfcr_operation"
13600 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13601 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13602 (match_operand 3 "immediate_operand" "n")]
13603 UNSPEC_MOVESI_FROM_CR))])]
13604 "TARGET_MFCRF"
13605 "*
13606 {
13607 int mask = 0;
13608 int i;
13609 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13610 {
13611 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13612 operands[4] = GEN_INT (mask);
13613 output_asm_insn (\"mfcr %1,%4\", operands);
13614 }
13615 return \"\";
13616 }"
13617 [(set_attr "type" "mfcrf")])
13619 (define_insn "movesi_from_cr"
13620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13621 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13622 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13623 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13624 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13625 UNSPEC_MOVESI_FROM_CR))]
13626 ""
13627 "mfcr %0"
13628 [(set_attr "type" "mfcr")])
13630 (define_insn "*crsave"
13631 [(match_parallel 0 "crsave_operation"
13632 [(set (match_operand:SI 1 "memory_operand" "=m")
13633 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13634 ""
13635 "stw %2,%1"
13636 [(set_attr "type" "store")])
13638 (define_insn "*stmw"
13639 [(match_parallel 0 "stmw_operation"
13640 [(set (match_operand:SI 1 "memory_operand" "=m")
13641 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13642 "TARGET_MULTIPLE"
13643 "stmw %2,%1"
13644 [(set_attr "type" "store")
13645 (set_attr "update" "yes")
13646 (set_attr "indexed" "yes")])
13648 ; The following comment applies to:
13649 ; save_gpregs_*
13650 ; save_fpregs_*
13651 ; restore_gpregs*
13652 ; return_and_restore_gpregs*
13653 ; return_and_restore_fpregs*
13654 ; return_and_restore_fpregs_aix*
13655 ;
13656 ; The out-of-line save / restore functions expects one input argument.
13657 ; Since those are not standard call_insn's, we must avoid using
13658 ; MATCH_OPERAND for that argument. That way the register rename
13659 ; optimization will not try to rename this register.
13660 ; Each pattern is repeated for each possible register number used in
13661 ; various ABIs (r11, r1, and for some functions r12)
13663 (define_insn "*save_gpregs_<mode>_r11"
13664 [(match_parallel 0 "any_parallel_operand"
13665 [(clobber (reg:P 65))
13666 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13667 (use (reg:P 11))
13668 (set (match_operand:P 2 "memory_operand" "=m")
13669 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13670 ""
13671 "bl %1"
13672 [(set_attr "type" "branch")
13673 (set_attr "length" "4")])
13675 (define_insn "*save_gpregs_<mode>_r12"
13676 [(match_parallel 0 "any_parallel_operand"
13677 [(clobber (reg:P 65))
13678 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13679 (use (reg:P 12))
13680 (set (match_operand:P 2 "memory_operand" "=m")
13681 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13682 ""
13683 "bl %1"
13684 [(set_attr "type" "branch")
13685 (set_attr "length" "4")])
13687 (define_insn "*save_gpregs_<mode>_r1"
13688 [(match_parallel 0 "any_parallel_operand"
13689 [(clobber (reg:P 65))
13690 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13691 (use (reg:P 1))
13692 (set (match_operand:P 2 "memory_operand" "=m")
13693 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13694 ""
13695 "bl %1"
13696 [(set_attr "type" "branch")
13697 (set_attr "length" "4")])
13699 (define_insn "*save_fpregs_<mode>_r11"
13700 [(match_parallel 0 "any_parallel_operand"
13701 [(clobber (reg:P 65))
13702 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13703 (use (reg:P 11))
13704 (set (match_operand:DF 2 "memory_operand" "=m")
13705 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13706 ""
13707 "bl %1"
13708 [(set_attr "type" "branch")
13709 (set_attr "length" "4")])
13711 (define_insn "*save_fpregs_<mode>_r12"
13712 [(match_parallel 0 "any_parallel_operand"
13713 [(clobber (reg:P 65))
13714 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13715 (use (reg:P 12))
13716 (set (match_operand:DF 2 "memory_operand" "=m")
13717 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13718 ""
13719 "bl %1"
13720 [(set_attr "type" "branch")
13721 (set_attr "length" "4")])
13723 (define_insn "*save_fpregs_<mode>_r1"
13724 [(match_parallel 0 "any_parallel_operand"
13725 [(clobber (reg:P 65))
13726 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13727 (use (reg:P 1))
13728 (set (match_operand:DF 2 "memory_operand" "=m")
13729 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13730 ""
13731 "bl %1"
13732 [(set_attr "type" "branch")
13733 (set_attr "length" "4")])
13735 ; This is to explain that changes to the stack pointer should
13736 ; not be moved over loads from or stores to stack memory.
13737 (define_insn "stack_tie"
13738 [(match_parallel 0 "tie_operand"
13739 [(set (mem:BLK (reg 1)) (const_int 0))])]
13740 ""
13741 ""
13742 [(set_attr "length" "0")])
13744 (define_expand "epilogue"
13745 [(use (const_int 0))]
13746 ""
13747 {
13748 if (!TARGET_SCHED_PROLOG)
13749 emit_insn (gen_blockage ());
13750 rs6000_emit_epilogue (FALSE);
13751 DONE;
13752 })
13754 ; On some processors, doing the mtcrf one CC register at a time is
13755 ; faster (like on the 604e). On others, doing them all at once is
13756 ; faster; for instance, on the 601 and 750.
13758 (define_expand "movsi_to_cr_one"
13759 [(set (match_operand:CC 0 "cc_reg_operand" "")
13760 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13761 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13762 ""
13763 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13765 (define_insn "*movsi_to_cr"
13766 [(match_parallel 0 "mtcrf_operation"
13767 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13768 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13769 (match_operand 3 "immediate_operand" "n")]
13770 UNSPEC_MOVESI_TO_CR))])]
13771 ""
13772 "*
13773 {
13774 int mask = 0;
13775 int i;
13776 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13777 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13778 operands[4] = GEN_INT (mask);
13779 return \"mtcrf %4,%2\";
13780 }"
13781 [(set_attr "type" "mtcr")])
13783 (define_insn "*mtcrfsi"
13784 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13785 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13786 (match_operand 2 "immediate_operand" "n")]
13787 UNSPEC_MOVESI_TO_CR))]
13788 "GET_CODE (operands[0]) == REG
13789 && CR_REGNO_P (REGNO (operands[0]))
13790 && GET_CODE (operands[2]) == CONST_INT
13791 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13792 "mtcrf %R0,%1"
13793 [(set_attr "type" "mtcr")])
13795 ; The load-multiple instructions have similar properties.
13796 ; Note that "load_multiple" is a name known to the machine-independent
13797 ; code that actually corresponds to the PowerPC load-string.
13799 (define_insn "*lmw"
13800 [(match_parallel 0 "lmw_operation"
13801 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13802 (match_operand:SI 2 "memory_operand" "m"))])]
13803 "TARGET_MULTIPLE"
13804 "lmw %1,%2"
13805 [(set_attr "type" "load")
13806 (set_attr "update" "yes")
13807 (set_attr "indexed" "yes")
13808 (set_attr "cell_micro" "always")])
13810 (define_insn "*return_internal_<mode>"
13811 [(simple_return)
13812 (use (match_operand:P 0 "register_operand" "lc"))]
13813 ""
13814 "b%T0"
13815 [(set_attr "type" "jmpreg")])
13817 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13818 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13820 ; The following comment applies to:
13821 ; save_gpregs_*
13822 ; save_fpregs_*
13823 ; restore_gpregs*
13824 ; return_and_restore_gpregs*
13825 ; return_and_restore_fpregs*
13826 ; return_and_restore_fpregs_aix*
13827 ;
13828 ; The out-of-line save / restore functions expects one input argument.
13829 ; Since those are not standard call_insn's, we must avoid using
13830 ; MATCH_OPERAND for that argument. That way the register rename
13831 ; optimization will not try to rename this register.
13832 ; Each pattern is repeated for each possible register number used in
13833 ; various ABIs (r11, r1, and for some functions r12)
13835 (define_insn "*restore_gpregs_<mode>_r11"
13836 [(match_parallel 0 "any_parallel_operand"
13837 [(clobber (match_operand:P 1 "register_operand" "=l"))
13838 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13839 (use (reg:P 11))
13840 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13841 (match_operand:P 4 "memory_operand" "m"))])]
13842 ""
13843 "bl %2"
13844 [(set_attr "type" "branch")
13845 (set_attr "length" "4")])
13847 (define_insn "*restore_gpregs_<mode>_r12"
13848 [(match_parallel 0 "any_parallel_operand"
13849 [(clobber (match_operand:P 1 "register_operand" "=l"))
13850 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13851 (use (reg:P 12))
13852 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13853 (match_operand:P 4 "memory_operand" "m"))])]
13854 ""
13855 "bl %2"
13856 [(set_attr "type" "branch")
13857 (set_attr "length" "4")])
13859 (define_insn "*restore_gpregs_<mode>_r1"
13860 [(match_parallel 0 "any_parallel_operand"
13861 [(clobber (match_operand:P 1 "register_operand" "=l"))
13862 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13863 (use (reg:P 1))
13864 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13865 (match_operand:P 4 "memory_operand" "m"))])]
13866 ""
13867 "bl %2"
13868 [(set_attr "type" "branch")
13869 (set_attr "length" "4")])
13871 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13872 [(match_parallel 0 "any_parallel_operand"
13873 [(return)
13874 (clobber (match_operand:P 1 "register_operand" "=l"))
13875 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13876 (use (reg:P 11))
13877 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13878 (match_operand:P 4 "memory_operand" "m"))])]
13879 ""
13880 "b %2"
13881 [(set_attr "type" "branch")
13882 (set_attr "length" "4")])
13884 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13885 [(match_parallel 0 "any_parallel_operand"
13886 [(return)
13887 (clobber (match_operand:P 1 "register_operand" "=l"))
13888 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13889 (use (reg:P 12))
13890 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13891 (match_operand:P 4 "memory_operand" "m"))])]
13892 ""
13893 "b %2"
13894 [(set_attr "type" "branch")
13895 (set_attr "length" "4")])
13897 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13898 [(match_parallel 0 "any_parallel_operand"
13899 [(return)
13900 (clobber (match_operand:P 1 "register_operand" "=l"))
13901 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13902 (use (reg:P 1))
13903 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13904 (match_operand:P 4 "memory_operand" "m"))])]
13905 ""
13906 "b %2"
13907 [(set_attr "type" "branch")
13908 (set_attr "length" "4")])
13910 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13911 [(match_parallel 0 "any_parallel_operand"
13912 [(return)
13913 (clobber (match_operand:P 1 "register_operand" "=l"))
13914 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13915 (use (reg:P 11))
13916 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13917 (match_operand:DF 4 "memory_operand" "m"))])]
13918 ""
13919 "b %2"
13920 [(set_attr "type" "branch")
13921 (set_attr "length" "4")])
13923 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13924 [(match_parallel 0 "any_parallel_operand"
13925 [(return)
13926 (clobber (match_operand:P 1 "register_operand" "=l"))
13927 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13928 (use (reg:P 12))
13929 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13930 (match_operand:DF 4 "memory_operand" "m"))])]
13931 ""
13932 "b %2"
13933 [(set_attr "type" "branch")
13934 (set_attr "length" "4")])
13936 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13937 [(match_parallel 0 "any_parallel_operand"
13938 [(return)
13939 (clobber (match_operand:P 1 "register_operand" "=l"))
13940 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13941 (use (reg:P 1))
13942 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13943 (match_operand:DF 4 "memory_operand" "m"))])]
13944 ""
13945 "b %2"
13946 [(set_attr "type" "branch")
13947 (set_attr "length" "4")])
13949 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13950 [(match_parallel 0 "any_parallel_operand"
13951 [(return)
13952 (use (match_operand:P 1 "register_operand" "l"))
13953 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13954 (use (reg:P 11))
13955 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13956 (match_operand:DF 4 "memory_operand" "m"))])]
13957 ""
13958 "b %2"
13959 [(set_attr "type" "branch")
13960 (set_attr "length" "4")])
13962 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13963 [(match_parallel 0 "any_parallel_operand"
13964 [(return)
13965 (use (match_operand:P 1 "register_operand" "l"))
13966 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13967 (use (reg:P 1))
13968 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13969 (match_operand:DF 4 "memory_operand" "m"))])]
13970 ""
13971 "b %2"
13972 [(set_attr "type" "branch")
13973 (set_attr "length" "4")])
13975 ; This is used in compiling the unwind routines.
13976 (define_expand "eh_return"
13977 [(use (match_operand 0 "general_operand" ""))]
13978 ""
13979 "
13980 {
13981 if (TARGET_32BIT)
13982 emit_insn (gen_eh_set_lr_si (operands[0]));
13983 else
13984 emit_insn (gen_eh_set_lr_di (operands[0]));
13985 DONE;
13986 }")
13988 ; We can't expand this before we know where the link register is stored.
13989 (define_insn "eh_set_lr_<mode>"
13990 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13991 UNSPECV_EH_RR)
13992 (clobber (match_scratch:P 1 "=&b"))]
13993 ""
13994 "#")
13996 (define_split
13997 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13998 (clobber (match_scratch 1 ""))]
13999 "reload_completed"
14000 [(const_int 0)]
14001 "
14002 {
14003 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14004 DONE;
14005 }")
14007 (define_insn "prefetch"
14008 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14009 (match_operand:SI 1 "const_int_operand" "n")
14010 (match_operand:SI 2 "const_int_operand" "n"))]
14011 ""
14012 "*
14013 {
14014 if (GET_CODE (operands[0]) == REG)
14015 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14016 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14017 }"
14018 [(set_attr "type" "load")])
14019 \f
14020 (define_insn "bpermd_<mode>"
14021 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14022 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14023 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14024 "TARGET_POPCNTD"
14025 "bpermd %0,%1,%2"
14026 [(set_attr "type" "popcnt")])
14028 \f
14029 ;; Builtin fma support. Handle
14030 ;; Note that the conditions for expansion are in the FMA_F iterator.
14032 (define_expand "fma<mode>4"
14033 [(set (match_operand:FMA_F 0 "register_operand" "")
14034 (fma:FMA_F
14035 (match_operand:FMA_F 1 "register_operand" "")
14036 (match_operand:FMA_F 2 "register_operand" "")
14037 (match_operand:FMA_F 3 "register_operand" "")))]
14038 ""
14039 "")
14041 (define_insn "*fma<mode>4_fpr"
14042 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14043 (fma:SFDF
14044 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14045 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14046 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14047 "TARGET_<MODE>_FPR"
14048 "@
14049 fmadd<Ftrad> %0,%1,%2,%3
14050 xsmadda<Fvsx> %x0,%x1,%x2
14051 xsmaddm<Fvsx> %x0,%x1,%x3"
14052 [(set_attr "type" "fp")
14053 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14055 ; Altivec only has fma and nfms.
14056 (define_expand "fms<mode>4"
14057 [(set (match_operand:FMA_F 0 "register_operand" "")
14058 (fma:FMA_F
14059 (match_operand:FMA_F 1 "register_operand" "")
14060 (match_operand:FMA_F 2 "register_operand" "")
14061 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14062 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14063 "")
14065 (define_insn "*fms<mode>4_fpr"
14066 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14067 (fma:SFDF
14068 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14069 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14070 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14071 "TARGET_<MODE>_FPR"
14072 "@
14073 fmsub<Ftrad> %0,%1,%2,%3
14074 xsmsuba<Fvsx> %x0,%x1,%x2
14075 xsmsubm<Fvsx> %x0,%x1,%x3"
14076 [(set_attr "type" "fp")
14077 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14079 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14080 (define_expand "fnma<mode>4"
14081 [(set (match_operand:FMA_F 0 "register_operand" "")
14082 (neg:FMA_F
14083 (fma:FMA_F
14084 (match_operand:FMA_F 1 "register_operand" "")
14085 (match_operand:FMA_F 2 "register_operand" "")
14086 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14087 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14088 "")
14090 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14091 (define_expand "fnms<mode>4"
14092 [(set (match_operand:FMA_F 0 "register_operand" "")
14093 (neg:FMA_F
14094 (fma:FMA_F
14095 (match_operand:FMA_F 1 "register_operand" "")
14096 (match_operand:FMA_F 2 "register_operand" "")
14097 (match_operand:FMA_F 3 "register_operand" ""))))]
14098 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14099 "")
14101 ; Not an official optab name, but used from builtins.
14102 (define_expand "nfma<mode>4"
14103 [(set (match_operand:FMA_F 0 "register_operand" "")
14104 (neg:FMA_F
14105 (fma:FMA_F
14106 (match_operand:FMA_F 1 "register_operand" "")
14107 (match_operand:FMA_F 2 "register_operand" "")
14108 (match_operand:FMA_F 3 "register_operand" ""))))]
14109 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14110 "")
14112 (define_insn "*nfma<mode>4_fpr"
14113 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14114 (neg:SFDF
14115 (fma:SFDF
14116 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14117 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14118 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14119 "TARGET_<MODE>_FPR"
14120 "@
14121 fnmadd<Ftrad> %0,%1,%2,%3
14122 xsnmadda<Fvsx> %x0,%x1,%x2
14123 xsnmaddm<Fvsx> %x0,%x1,%x3"
14124 [(set_attr "type" "fp")
14125 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14127 ; Not an official optab name, but used from builtins.
14128 (define_expand "nfms<mode>4"
14129 [(set (match_operand:FMA_F 0 "register_operand" "")
14130 (neg:FMA_F
14131 (fma:FMA_F
14132 (match_operand:FMA_F 1 "register_operand" "")
14133 (match_operand:FMA_F 2 "register_operand" "")
14134 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14135 ""
14136 "")
14138 (define_insn "*nfmssf4_fpr"
14139 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14140 (neg:SFDF
14141 (fma:SFDF
14142 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14143 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14144 (neg:SFDF
14145 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14146 "TARGET_<MODE>_FPR"
14147 "@
14148 fnmsub<Ftrad> %0,%1,%2,%3
14149 xsnmsuba<Fvsx> %x0,%x1,%x2
14150 xsnmsubm<Fvsx> %x0,%x1,%x3"
14151 [(set_attr "type" "fp")
14152 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14154 \f
14155 (define_expand "rs6000_get_timebase"
14156 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14157 ""
14158 {
14159 if (TARGET_POWERPC64)
14160 emit_insn (gen_rs6000_mftb_di (operands[0]));
14161 else
14162 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14163 DONE;
14164 })
14166 (define_insn "rs6000_get_timebase_ppc32"
14167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14168 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14169 (clobber (match_scratch:SI 1 "=r"))
14170 (clobber (match_scratch:CC 2 "=y"))]
14171 "!TARGET_POWERPC64"
14172 {
14173 if (WORDS_BIG_ENDIAN)
14174 if (TARGET_MFCRF)
14175 {
14176 return "mfspr %0,269\;"
14177 "mfspr %L0,268\;"
14178 "mfspr %1,269\;"
14179 "cmpw %2,%0,%1\;"
14180 "bne- %2,$-16";
14181 }
14182 else
14183 {
14184 return "mftbu %0\;"
14185 "mftb %L0\;"
14186 "mftbu %1\;"
14187 "cmpw %2,%0,%1\;"
14188 "bne- %2,$-16";
14189 }
14190 else
14191 if (TARGET_MFCRF)
14192 {
14193 return "mfspr %L0,269\;"
14194 "mfspr %0,268\;"
14195 "mfspr %1,269\;"
14196 "cmpw %2,%L0,%1\;"
14197 "bne- %2,$-16";
14198 }
14199 else
14200 {
14201 return "mftbu %L0\;"
14202 "mftb %0\;"
14203 "mftbu %1\;"
14204 "cmpw %2,%L0,%1\;"
14205 "bne- %2,$-16";
14206 }
14207 }
14208 [(set_attr "length" "20")])
14210 (define_insn "rs6000_mftb_<mode>"
14211 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14212 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
14213 ""
14214 {
14215 if (TARGET_MFCRF)
14216 return "mfspr %0,268";
14217 else
14218 return "mftb %0";
14219 })
14221 \f
14222 (define_insn "rs6000_mffs"
14223 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14224 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14225 "TARGET_HARD_FLOAT && TARGET_FPRS"
14226 "mffs %0")
14228 (define_insn "rs6000_mtfsf"
14229 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14230 (match_operand:DF 1 "gpc_reg_operand" "d")]
14231 UNSPECV_MTFSF)]
14232 "TARGET_HARD_FLOAT && TARGET_FPRS"
14233 "mtfsf %0,%1")
14235 \f
14236 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14237 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14238 ;; register that is being loaded. The fused ops must be physically adjacent.
14240 ;; We use define_peephole for the actual addis/load, and the register used to
14241 ;; hold the addis value must be the same as the register being loaded. We use
14242 ;; define_peephole2 to change the register used for addis to be the register
14243 ;; being loaded, since we can look at whether it is dead after the load insn.
14245 (define_peephole
14246 [(set (match_operand:P 0 "base_reg_operand" "")
14247 (match_operand:P 1 "fusion_gpr_addis" ""))
14248 (set (match_operand:INT1 2 "base_reg_operand" "")
14249 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14250 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
14251 {
14252 return emit_fusion_gpr_load (operands);
14253 }
14254 [(set_attr "type" "load")
14255 (set_attr "length" "8")])
14257 (define_peephole2
14258 [(set (match_operand:P 0 "base_reg_operand" "")
14259 (match_operand:P 1 "fusion_gpr_addis" ""))
14260 (set (match_operand:INT1 2 "base_reg_operand" "")
14261 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14262 "TARGET_P8_FUSION
14263 && (REGNO (operands[0]) != REGNO (operands[2])
14264 || GET_CODE (operands[3]) == SIGN_EXTEND)
14265 && fusion_gpr_load_p (operands, true)"
14266 [(const_int 0)]
14267 {
14268 expand_fusion_gpr_load (operands);
14269 DONE;
14270 })
14272 \f
14273 ;; Miscellaneous ISA 2.06 (power7) instructions
14274 (define_insn "addg6s"
14275 [(set (match_operand:SI 0 "register_operand" "=r")
14276 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14277 (match_operand:SI 2 "register_operand" "r")]
14278 UNSPEC_ADDG6S))]
14279 "TARGET_POPCNTD"
14280 "addg6s %0,%1,%2"
14281 [(set_attr "type" "integer")
14282 (set_attr "length" "4")])
14284 (define_insn "cdtbcd"
14285 [(set (match_operand:SI 0 "register_operand" "=r")
14286 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14287 UNSPEC_CDTBCD))]
14288 "TARGET_POPCNTD"
14289 "cdtbcd %0,%1"
14290 [(set_attr "type" "integer")
14291 (set_attr "length" "4")])
14293 (define_insn "cbcdtd"
14294 [(set (match_operand:SI 0 "register_operand" "=r")
14295 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14296 UNSPEC_CBCDTD))]
14297 "TARGET_POPCNTD"
14298 "cbcdtd %0,%1"
14299 [(set_attr "type" "integer")
14300 (set_attr "length" "4")])
14302 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14303 UNSPEC_DIVEO
14304 UNSPEC_DIVEU
14305 UNSPEC_DIVEUO])
14307 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14308 (UNSPEC_DIVEO "eo")
14309 (UNSPEC_DIVEU "eu")
14310 (UNSPEC_DIVEUO "euo")])
14312 (define_insn "div<div_extend>_<mode>"
14313 [(set (match_operand:GPR 0 "register_operand" "=r")
14314 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14315 (match_operand:GPR 2 "register_operand" "r")]
14316 UNSPEC_DIV_EXTEND))]
14317 "TARGET_POPCNTD"
14318 "div<wd><div_extend> %0,%1,%2"
14319 [(set_attr "type" "div")
14320 (set_attr "size" "<bits>")])
14322 \f
14323 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14325 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14326 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14328 (define_expand "unpack<mode>"
14329 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14330 (unspec:<FP128_64>
14331 [(match_operand:FMOVE128 1 "register_operand" "")
14332 (match_operand:QI 2 "const_0_to_1_operand" "")]
14333 UNSPEC_UNPACK_128BIT))]
14334 ""
14335 "")
14337 (define_insn_and_split "unpack<mode>_dm"
14338 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14339 (unspec:<FP128_64>
14340 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14341 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14342 UNSPEC_UNPACK_128BIT))]
14343 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14344 "#"
14345 "&& reload_completed"
14346 [(set (match_dup 0) (match_dup 3))]
14347 {
14348 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14350 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14351 {
14352 emit_note (NOTE_INSN_DELETED);
14353 DONE;
14354 }
14356 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14357 }
14358 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14359 (set_attr "length" "4")])
14361 (define_insn_and_split "unpack<mode>_nodm"
14362 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14363 (unspec:<FP128_64>
14364 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14365 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14366 UNSPEC_UNPACK_128BIT))]
14367 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14368 "#"
14369 "&& reload_completed"
14370 [(set (match_dup 0) (match_dup 3))]
14371 {
14372 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14374 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14375 {
14376 emit_note (NOTE_INSN_DELETED);
14377 DONE;
14378 }
14380 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14381 }
14382 [(set_attr "type" "fp,fpstore")
14383 (set_attr "length" "4")])
14385 (define_insn_and_split "pack<mode>"
14386 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14387 (unspec:FMOVE128
14388 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14389 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14390 UNSPEC_PACK_128BIT))]
14391 ""
14392 "@
14393 fmr %L0,%2
14394 #"
14395 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14396 [(set (match_dup 3) (match_dup 1))
14397 (set (match_dup 4) (match_dup 2))]
14398 {
14399 unsigned dest_hi = REGNO (operands[0]);
14400 unsigned dest_lo = dest_hi + 1;
14402 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14403 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14405 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14406 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14407 }
14408 [(set_attr "type" "fp,fp")
14409 (set_attr "length" "4,8")])
14411 (define_insn "unpackv1ti"
14412 [(set (match_operand:DI 0 "register_operand" "=d,d")
14413 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14414 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14415 UNSPEC_UNPACK_128BIT))]
14416 "TARGET_VSX"
14417 {
14418 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14419 return ASM_COMMENT_START " xxpermdi to same register";
14421 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14422 return "xxpermdi %x0,%x1,%x1,%3";
14423 }
14424 [(set_attr "type" "vecperm")
14425 (set_attr "length" "4")])
14427 (define_insn "packv1ti"
14428 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14429 (unspec:V1TI
14430 [(match_operand:DI 1 "register_operand" "d")
14431 (match_operand:DI 2 "register_operand" "d")]
14432 UNSPEC_PACK_128BIT))]
14433 "TARGET_VSX"
14434 "xxpermdi %x0,%x1,%x2,0"
14435 [(set_attr "type" "vecperm")
14436 (set_attr "length" "4")])
14438 \f
14440 (include "sync.md")
14441 (include "vector.md")
14442 (include "vsx.md")
14443 (include "altivec.md")
14444 (include "spe.md")
14445 (include "dfp.md")
14446 (include "paired.md")
14447 (include "crypto.md")
14448 (include "htm.md")