1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
83 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts
;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges
;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras
;
108 /* Number of instructions combined in this function. */
110 static int combine_successes
;
112 /* Totals over entire compilation. */
114 static int total_attempts
, total_merges
, total_extras
, total_successes
;
117 /* Vector mapping INSN_UIDs to cuids.
118 The cuids are like uids but increase monotonically always.
119 Combine always uses cuids so that it can compare them.
120 But actually renumbering the uids, which we used to do,
121 proves to be a bad idea because it makes it hard to compare
122 the dumps produced by earlier passes with those from later passes. */
124 static int *uid_cuid
;
125 static int max_uid_cuid
;
127 /* Get the cuid of an insn. */
129 #define INSN_CUID(INSN) \
130 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
132 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
133 BITS_PER_WORD would invoke undefined behavior. Work around it. */
135 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
136 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
138 #define nonzero_bits(X, M) \
139 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
141 #define num_sign_bit_copies(X, M) \
142 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno
;
148 /* Record last point of death of (hard or pseudo) register n. */
150 static rtx
*reg_last_death
;
152 /* Record last point of modification of (hard or pseudo) register n. */
154 static rtx
*reg_last_set
;
156 /* Record the cuid of the last insn that invalidated memory
157 (anything that writes memory, and subroutine calls, but not pushes). */
159 static int mem_last_set
;
161 /* Record the cuid of the last CALL_INSN
162 so we can tell whether a potential combination crosses any calls. */
164 static int last_call_cuid
;
166 /* When `subst' is called, this is the insn that is being modified
167 (by combining in a previous insn). The PATTERN of this insn
168 is still the old pattern partially modified and it should not be
169 looked at, but this may be used to examine the successors of the insn
170 to judge whether a simplification is valid. */
172 static rtx subst_insn
;
174 /* This is the lowest CUID that `subst' is currently dealing with.
175 get_last_value will not return a value if the register was set at or
176 after this CUID. If not for this mechanism, we could get confused if
177 I2 or I1 in try_combine were an insn that used the old value of a register
178 to obtain a new value. In that case, we might erroneously get the
179 new value of the register when we wanted the old one. */
181 static int subst_low_cuid
;
183 /* This contains any hard registers that are used in newpat; reg_dead_at_p
184 must consider all these registers to be always live. */
186 static HARD_REG_SET newpat_used_regs
;
188 /* This is an insn to which a LOG_LINKS entry has been added. If this
189 insn is the earlier than I2 or I3, combine should rescan starting at
192 static rtx added_links_insn
;
194 /* Basic block in which we are performing combines. */
195 static basic_block this_basic_block
;
197 /* A bitmap indicating which blocks had registers go dead at entry.
198 After combine, we'll need to re-do global life analysis with
199 those blocks as starting points. */
200 static sbitmap refresh_blocks
;
202 /* The next group of arrays allows the recording of the last value assigned
203 to (hard or pseudo) register n. We use this information to see if an
204 operation being processed is redundant given a prior operation performed
205 on the register. For example, an `and' with a constant is redundant if
206 all the zero bits are already known to be turned off.
208 We use an approach similar to that used by cse, but change it in the
211 (1) We do not want to reinitialize at each label.
212 (2) It is useful, but not critical, to know the actual value assigned
213 to a register. Often just its form is helpful.
215 Therefore, we maintain the following arrays:
217 reg_last_set_value the last value assigned
218 reg_last_set_label records the value of label_tick when the
219 register was assigned
220 reg_last_set_table_tick records the value of label_tick when a
221 value using the register is assigned
222 reg_last_set_invalid set to nonzero when it is not valid
223 to use the value of this register in some
226 To understand the usage of these tables, it is important to understand
227 the distinction between the value in reg_last_set_value being valid
228 and the register being validly contained in some other expression in the
231 Entry I in reg_last_set_value is valid if it is nonzero, and either
232 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
234 Register I may validly appear in any expression returned for the value
235 of another register if reg_n_sets[i] is 1. It may also appear in the
236 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
237 reg_last_set_invalid[j] is zero.
239 If an expression is found in the table containing a register which may
240 not validly appear in an expression, the register is replaced by
241 something that won't match, (clobber (const_int 0)).
243 reg_last_set_invalid[i] is set nonzero when register I is being assigned
244 to and reg_last_set_table_tick[i] == label_tick. */
246 /* Record last value assigned to (hard or pseudo) register n. */
248 static rtx
*reg_last_set_value
;
250 /* Record the value of label_tick when the value for register n is placed in
251 reg_last_set_value[n]. */
253 static int *reg_last_set_label
;
255 /* Record the value of label_tick when an expression involving register n
256 is placed in reg_last_set_value. */
258 static int *reg_last_set_table_tick
;
260 /* Set nonzero if references to register n in expressions should not be
263 static char *reg_last_set_invalid
;
265 /* Incremented for each label. */
267 static int label_tick
;
269 /* Some registers that are set more than once and used in more than one
270 basic block are nevertheless always set in similar ways. For example,
271 a QImode register may be loaded from memory in two places on a machine
272 where byte loads zero extend.
274 We record in the following array what we know about the nonzero
275 bits of a register, specifically which bits are known to be zero.
277 If an entry is zero, it means that we don't know anything special. */
279 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
281 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
282 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
284 static enum machine_mode nonzero_bits_mode
;
286 /* Nonzero if we know that a register has some leading bits that are always
287 equal to the sign bit. */
289 static unsigned char *reg_sign_bit_copies
;
291 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
292 It is zero while computing them and after combine has completed. This
293 former test prevents propagating values based on previously set values,
294 which can be incorrect if a variable is modified in a loop. */
296 static int nonzero_sign_valid
;
298 /* These arrays are maintained in parallel with reg_last_set_value
299 and are used to store the mode in which the register was last set,
300 the bits that were known to be zero when it was last set, and the
301 number of sign bits copies it was known to have when it was last set. */
303 static enum machine_mode
*reg_last_set_mode
;
304 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
305 static char *reg_last_set_sign_bit_copies
;
307 /* Record one modification to rtl structure
308 to be undone by storing old_contents into *where.
309 is_int is 1 if the contents are an int. */
315 union {rtx r
; int i
;} old_contents
;
316 union {rtx
*r
; int *i
;} where
;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too. */
332 static struct undobuf undobuf
;
334 /* Number of times the pseudo being substituted for
335 was found and replaced. */
337 static int n_occurrences
;
339 static void do_SUBST (rtx
*, rtx
);
340 static void do_SUBST_INT (int *, int);
341 static void init_reg_last_arrays (void);
342 static void setup_incoming_promotions (void);
343 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
344 static int cant_combine_insn_p (rtx
);
345 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
346 static int sets_function_arg_p (rtx
);
347 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
348 static int contains_muldiv (rtx
);
349 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx
*find_split_point (rtx
*, rtx
);
353 static rtx
subst (rtx
, rtx
, rtx
, int, int);
354 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
355 static rtx
simplify_if_then_else (rtx
);
356 static rtx
simplify_set (rtx
);
357 static rtx
simplify_logical (rtx
, int);
358 static rtx
expand_compound_operation (rtx
);
359 static rtx
expand_field_assignment (rtx
);
360 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
361 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
362 static rtx
extract_left_shift (rtx
, int);
363 static rtx
make_compound_operation (rtx
, enum rtx_code
);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
365 unsigned HOST_WIDE_INT
*);
366 static rtx
force_to_mode (rtx
, enum machine_mode
,
367 unsigned HOST_WIDE_INT
, rtx
, int);
368 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
369 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
370 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
371 static rtx
make_field_assignment (rtx
);
372 static rtx
apply_distributive_law (rtx
);
373 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
374 unsigned HOST_WIDE_INT
);
375 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
376 rtx
, enum machine_mode
,
377 unsigned HOST_WIDE_INT
);
378 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
380 unsigned HOST_WIDE_INT
);
381 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
384 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
385 enum machine_mode
, unsigned int);
386 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
387 HOST_WIDE_INT
, enum machine_mode
, int *);
388 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
390 static int recog_for_combine (rtx
*, rtx
, rtx
*);
391 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
392 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
393 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
394 static void update_table_tick (rtx
);
395 static void record_value_for_reg (rtx
, rtx
, rtx
);
396 static void check_promoted_subreg (rtx
, rtx
);
397 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
398 static void record_dead_and_set_regs (rtx
);
399 static int get_last_value_validate (rtx
*, rtx
, int, int);
400 static rtx
get_last_value (rtx
);
401 static int use_crosses_set_p (rtx
, int);
402 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
403 static int reg_dead_at_p (rtx
, rtx
);
404 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
405 static int reg_bitfield_target_p (rtx
, rtx
);
406 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
407 static void distribute_links (rtx
);
408 static void mark_used_regs_combine (rtx
);
409 static int insn_cuid (rtx
);
410 static void record_promoted_value (rtx
, rtx
);
411 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
412 static enum rtx_code
combine_reversed_comparison_code (rtx
);
414 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
415 insn. The substitution can be undone by undo_all. If INTO is already
416 set to NEWVAL, do not record this change. Because computing NEWVAL might
417 also call SUBST, we have to compute it before we put anything into
421 do_SUBST (rtx
*into
, rtx newval
)
426 if (oldval
== newval
)
429 /* We'd like to catch as many invalid transformations here as
430 possible. Unfortunately, there are way too many mode changes
431 that are perfectly valid, so we'd waste too much effort for
432 little gain doing the checks here. Focus on catching invalid
433 transformations involving integer constants. */
434 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
435 && GET_CODE (newval
) == CONST_INT
)
437 /* Sanity check that we're replacing oldval with a CONST_INT
438 that is a valid sign-extension for the original mode. */
439 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
443 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
444 CONST_INT is not valid, because after the replacement, the
445 original mode would be gone. Unfortunately, we can't tell
446 when do_SUBST is called to replace the operand thereof, so we
447 perform this test on oldval instead, checking whether an
448 invalid replacement took place before we got here. */
449 if ((GET_CODE (oldval
) == SUBREG
450 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
451 || (GET_CODE (oldval
) == ZERO_EXTEND
452 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.r
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
471 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
472 for the value of a HOST_WIDE_INT value (including CONST_INT) is
476 do_SUBST_INT (int *into
, int newval
)
481 if (oldval
== newval
)
485 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
487 buf
= xmalloc (sizeof (struct undo
));
491 buf
->old_contents
.i
= oldval
;
494 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return nonzero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (rtx f
, unsigned int nregs
)
512 rtx links
, nextlinks
;
514 int new_direct_jump_p
= 0;
516 combine_attempts
= 0;
519 combine_successes
= 0;
521 combine_max_regno
= nregs
;
523 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
524 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
526 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
527 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
530 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
532 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
533 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
534 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
536 init_reg_last_arrays ();
538 init_recog_no_volatile ();
540 /* Compute maximum uid value so uid_cuid can be allocated. */
542 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
543 if (INSN_UID (insn
) > i
)
546 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
549 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
551 /* Don't use reg_nonzero_bits when computing it. This can cause problems
552 when, for example, we have j <<= 1 in a loop. */
554 nonzero_sign_valid
= 0;
556 /* Compute the mapping from uids to cuids.
557 Cuids are numbers assigned to insns, like uids,
558 except that cuids increase monotonically through the code.
560 Scan all SETs and see if we can deduce anything about what
561 bits are known to be zero for some registers and how many copies
562 of the sign bit are known to exist for those registers.
564 Also set any known values so that we can use it while searching
565 for what bits are known to be set. */
569 setup_incoming_promotions ();
571 refresh_blocks
= sbitmap_alloc (last_basic_block
);
572 sbitmap_zero (refresh_blocks
);
574 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
576 uid_cuid
[INSN_UID (insn
)] = ++i
;
582 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
584 record_dead_and_set_regs (insn
);
587 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
588 if (REG_NOTE_KIND (links
) == REG_INC
)
589 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
594 if (GET_CODE (insn
) == CODE_LABEL
)
598 nonzero_sign_valid
= 1;
600 /* Now scan all the insns in forward order. */
605 init_reg_last_arrays ();
606 setup_incoming_promotions ();
608 FOR_EACH_BB (this_basic_block
)
610 for (insn
= this_basic_block
->head
;
611 insn
!= NEXT_INSN (this_basic_block
->end
);
612 insn
= next
? next
: NEXT_INSN (insn
))
616 if (GET_CODE (insn
) == CODE_LABEL
)
619 else if (INSN_P (insn
))
621 /* See if we know about function return values before this
622 insn based upon SUBREG flags. */
623 check_promoted_subreg (insn
, PATTERN (insn
));
625 /* Try this insn with each insn it links back to. */
627 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
628 if ((next
= try_combine (insn
, XEXP (links
, 0),
629 NULL_RTX
, &new_direct_jump_p
)) != 0)
632 /* Try each sequence of three linked insns ending with this one. */
634 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
636 rtx link
= XEXP (links
, 0);
638 /* If the linked insn has been replaced by a note, then there
639 is no point in pursuing this chain any further. */
640 if (GET_CODE (link
) == NOTE
)
643 for (nextlinks
= LOG_LINKS (link
);
645 nextlinks
= XEXP (nextlinks
, 1))
646 if ((next
= try_combine (insn
, link
,
648 &new_direct_jump_p
)) != 0)
653 /* Try to combine a jump insn that uses CC0
654 with a preceding insn that sets CC0, and maybe with its
655 logical predecessor as well.
656 This is how we make decrement-and-branch insns.
657 We need this special code because data flow connections
658 via CC0 do not get entered in LOG_LINKS. */
660 if (GET_CODE (insn
) == JUMP_INSN
661 && (prev
= prev_nonnote_insn (insn
)) != 0
662 && GET_CODE (prev
) == INSN
663 && sets_cc0_p (PATTERN (prev
)))
665 if ((next
= try_combine (insn
, prev
,
666 NULL_RTX
, &new_direct_jump_p
)) != 0)
669 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
670 nextlinks
= XEXP (nextlinks
, 1))
671 if ((next
= try_combine (insn
, prev
,
673 &new_direct_jump_p
)) != 0)
677 /* Do the same for an insn that explicitly references CC0. */
678 if (GET_CODE (insn
) == INSN
679 && (prev
= prev_nonnote_insn (insn
)) != 0
680 && GET_CODE (prev
) == INSN
681 && sets_cc0_p (PATTERN (prev
))
682 && GET_CODE (PATTERN (insn
)) == SET
683 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
685 if ((next
= try_combine (insn
, prev
,
686 NULL_RTX
, &new_direct_jump_p
)) != 0)
689 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
690 nextlinks
= XEXP (nextlinks
, 1))
691 if ((next
= try_combine (insn
, prev
,
693 &new_direct_jump_p
)) != 0)
697 /* Finally, see if any of the insns that this insn links to
698 explicitly references CC0. If so, try this insn, that insn,
699 and its predecessor if it sets CC0. */
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 if (GET_CODE (XEXP (links
, 0)) == INSN
702 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
703 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
704 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
705 && GET_CODE (prev
) == INSN
706 && sets_cc0_p (PATTERN (prev
))
707 && (next
= try_combine (insn
, XEXP (links
, 0),
708 prev
, &new_direct_jump_p
)) != 0)
712 /* Try combining an insn with two different insns whose results it
714 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
715 for (nextlinks
= XEXP (links
, 1); nextlinks
;
716 nextlinks
= XEXP (nextlinks
, 1))
717 if ((next
= try_combine (insn
, XEXP (links
, 0),
719 &new_direct_jump_p
)) != 0)
722 if (GET_CODE (insn
) != NOTE
)
723 record_dead_and_set_regs (insn
);
732 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
733 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
734 new_direct_jump_p
|= purge_all_dead_edges (0);
735 delete_noop_moves (f
);
737 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
738 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
739 | PROP_KILL_DEAD_CODE
);
742 sbitmap_free (refresh_blocks
);
743 free (reg_nonzero_bits
);
744 free (reg_sign_bit_copies
);
745 free (reg_last_death
);
747 free (reg_last_set_value
);
748 free (reg_last_set_table_tick
);
749 free (reg_last_set_label
);
750 free (reg_last_set_invalid
);
751 free (reg_last_set_mode
);
752 free (reg_last_set_nonzero_bits
);
753 free (reg_last_set_sign_bit_copies
);
757 struct undo
*undo
, *next
;
758 for (undo
= undobuf
.frees
; undo
; undo
= next
)
766 total_attempts
+= combine_attempts
;
767 total_merges
+= combine_merges
;
768 total_extras
+= combine_extras
;
769 total_successes
+= combine_successes
;
771 nonzero_sign_valid
= 0;
773 /* Make recognizer allow volatile MEMs again. */
776 return new_direct_jump_p
;
779 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
782 init_reg_last_arrays (void)
784 unsigned int nregs
= combine_max_regno
;
786 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
787 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
788 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
790 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
791 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
792 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
793 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
794 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
797 /* Set up any promoted values for incoming argument registers. */
800 setup_incoming_promotions (void)
802 #ifdef PROMOTE_FUNCTION_ARGS
805 enum machine_mode mode
;
807 rtx first
= get_insns ();
809 #ifndef OUTGOING_REGNO
810 #define OUTGOING_REGNO(N) N
812 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
817 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
820 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode
, const0_rtx
)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
841 void *data ATTRIBUTE_UNUSED
)
845 if (GET_CODE (x
) == REG
846 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
847 /* If this register is undefined at the start of the file, we can't
848 say what its contents were. */
849 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
850 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
852 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
854 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
855 reg_sign_bit_copies
[REGNO (x
)] = 1;
859 /* If this is a complex assignment, see if we can convert it into a
860 simple assignment. */
861 set
= expand_field_assignment (set
);
863 /* If this is a simple assignment, or we have a paradoxical SUBREG,
864 set what we know about X. */
866 if (SET_DEST (set
) == x
867 || (GET_CODE (SET_DEST (set
)) == SUBREG
868 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
870 && SUBREG_REG (SET_DEST (set
)) == x
))
872 rtx src
= SET_SRC (set
);
874 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
875 /* If X is narrower than a word and SRC is a non-negative
876 constant that would appear negative in the mode of X,
877 sign-extend it for use in reg_nonzero_bits because some
878 machines (maybe most) will actually do the sign-extension
879 and this is the conservative approach.
881 ??? For 2.5, try to tighten up the MD files in this regard
882 instead of this kludge. */
884 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
885 && GET_CODE (src
) == CONST_INT
887 && 0 != (INTVAL (src
)
889 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
890 src
= GEN_INT (INTVAL (src
)
891 | ((HOST_WIDE_INT
) (-1)
892 << GET_MODE_BITSIZE (GET_MODE (x
))));
895 /* Don't call nonzero_bits if it cannot change anything. */
896 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
897 reg_nonzero_bits
[REGNO (x
)]
898 |= nonzero_bits (src
, nonzero_bits_mode
);
899 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
900 if (reg_sign_bit_copies
[REGNO (x
)] == 0
901 || reg_sign_bit_copies
[REGNO (x
)] > num
)
902 reg_sign_bit_copies
[REGNO (x
)] = num
;
906 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
907 reg_sign_bit_copies
[REGNO (x
)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
924 rtx
*pdest
, rtx
*psrc
)
927 rtx set
= 0, src
, dest
;
932 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
933 && next_active_insn (succ
) == i3
)
934 : next_active_insn (insn
) == i3
);
936 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
937 or a PARALLEL consisting of such a SET and CLOBBERs.
939 If INSN has CLOBBER parallel parts, ignore them for our processing.
940 By definition, these happen during the execution of the insn. When it
941 is merged with another insn, all bets are off. If they are, in fact,
942 needed and aren't also supplied in I3, they may be added by
943 recog_for_combine. Otherwise, it won't match.
945 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
948 Get the source and destination of INSN. If more than one, can't
951 if (GET_CODE (PATTERN (insn
)) == SET
)
952 set
= PATTERN (insn
);
953 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
954 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
956 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
958 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
960 switch (GET_CODE (elt
))
962 /* This is important to combine floating point insns
965 /* Combining an isolated USE doesn't make sense.
966 We depend here on combinable_i3pat to reject them. */
967 /* The code below this loop only verifies that the inputs of
968 the SET in INSN do not change. We call reg_set_between_p
969 to verify that the REG in the USE does not change between
971 If the USE in INSN was for a pseudo register, the matching
972 insn pattern will likely match any register; combining this
973 with any other USE would only be safe if we knew that the
974 used registers have identical values, or if there was
975 something to tell them apart, e.g. different modes. For
976 now, we forgo such complicated tests and simply disallow
977 combining of USES of pseudo registers with any other USE. */
978 if (GET_CODE (XEXP (elt
, 0)) == REG
979 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
981 rtx i3pat
= PATTERN (i3
);
982 int i
= XVECLEN (i3pat
, 0) - 1;
983 unsigned int regno
= REGNO (XEXP (elt
, 0));
987 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
989 if (GET_CODE (i3elt
) == USE
990 && GET_CODE (XEXP (i3elt
, 0)) == REG
991 && (REGNO (XEXP (i3elt
, 0)) == regno
992 ? reg_set_between_p (XEXP (elt
, 0),
993 PREV_INSN (insn
), i3
)
994 : regno
>= FIRST_PSEUDO_REGISTER
))
1001 /* We can ignore CLOBBERs. */
1006 /* Ignore SETs whose result isn't used but not those that
1007 have side-effects. */
1008 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1009 && ! side_effects_p (elt
))
1012 /* If we have already found a SET, this is a second one and
1013 so we cannot combine with this insn. */
1021 /* Anything else means we can't combine. */
1027 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1028 so don't do anything with it. */
1029 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1038 set
= expand_field_assignment (set
);
1039 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1041 /* Don't eliminate a store in the stack pointer. */
1042 if (dest
== stack_pointer_rtx
1043 /* Don't combine with an insn that sets a register to itself if it has
1044 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1045 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1046 /* Can't merge an ASM_OPERANDS. */
1047 || GET_CODE (src
) == ASM_OPERANDS
1048 /* Can't merge a function call. */
1049 || GET_CODE (src
) == CALL
1050 /* Don't eliminate a function call argument. */
1051 || (GET_CODE (i3
) == CALL_INSN
1052 && (find_reg_fusage (i3
, USE
, dest
)
1053 || (GET_CODE (dest
) == REG
1054 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1055 && global_regs
[REGNO (dest
)])))
1056 /* Don't substitute into an incremented register. */
1057 || FIND_REG_INC_NOTE (i3
, dest
)
1058 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1060 /* Don't combine the end of a libcall into anything. */
1061 /* ??? This gives worse code, and appears to be unnecessary, since no
1062 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1063 use REG_RETVAL notes for noconflict blocks, but other code here
1064 makes sure that those insns don't disappear. */
1065 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1067 /* Make sure that DEST is not used after SUCC but before I3. */
1068 || (succ
&& ! all_adjacent
1069 && reg_used_between_p (dest
, succ
, i3
))
1070 /* Make sure that the value that is to be substituted for the register
1071 does not use any registers whose values alter in between. However,
1072 If the insns are adjacent, a use can't cross a set even though we
1073 think it might (this can happen for a sequence of insns each setting
1074 the same destination; reg_last_set of that register might point to
1075 a NOTE). If INSN has a REG_EQUIV note, the register is always
1076 equivalent to the memory so the substitution is valid even if there
1077 are intervening stores. Also, don't move a volatile asm or
1078 UNSPEC_VOLATILE across any other insns. */
1080 && (((GET_CODE (src
) != MEM
1081 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1082 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1083 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1084 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1085 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1086 better register allocation by not doing the combine. */
1087 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1088 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1089 /* Don't combine across a CALL_INSN, because that would possibly
1090 change whether the life span of some REGs crosses calls or not,
1091 and it is a pain to update that information.
1092 Exception: if source is a constant, moving it later can't hurt.
1093 Accept that special case, because it helps -fforce-addr a lot. */
1094 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1097 /* DEST must either be a REG or CC0. */
1098 if (GET_CODE (dest
) == REG
)
1100 /* If register alignment is being enforced for multi-word items in all
1101 cases except for parameters, it is possible to have a register copy
1102 insn referencing a hard register that is not allowed to contain the
1103 mode being copied and which would not be valid as an operand of most
1104 insns. Eliminate this problem by not combining with such an insn.
1106 Also, on some machines we don't want to extend the life of a hard
1109 if (GET_CODE (src
) == REG
1110 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1111 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1112 /* Don't extend the life of a hard register unless it is
1113 user variable (if we have few registers) or it can't
1114 fit into the desired register (meaning something special
1116 Also avoid substituting a return register into I3, because
1117 reload can't handle a conflict with constraints of other
1119 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1123 else if (GET_CODE (dest
) != CC0
)
1126 /* Don't substitute for a register intended as a clobberable operand.
1127 Similarly, don't substitute an expression containing a register that
1128 will be clobbered in I3. */
1129 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1130 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1131 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1132 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1134 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1137 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1138 or not), reject, unless nothing volatile comes between it and I3 */
1140 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1142 /* Make sure succ doesn't contain a volatile reference. */
1143 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1146 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1147 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1151 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1152 to be an explicit register variable, and was chosen for a reason. */
1154 if (GET_CODE (src
) == ASM_OPERANDS
1155 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1158 /* If there are any volatile insns between INSN and I3, reject, because
1159 they might affect machine state. */
1161 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1162 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1165 /* If INSN or I2 contains an autoincrement or autodecrement,
1166 make sure that register is not used between there and I3,
1167 and not already used in I3 either.
1168 Also insist that I3 not be a jump; if it were one
1169 and the incremented register were spilled, we would lose. */
1172 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1173 if (REG_NOTE_KIND (link
) == REG_INC
1174 && (GET_CODE (i3
) == JUMP_INSN
1175 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1176 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1181 /* Don't combine an insn that follows a CC0-setting insn.
1182 An insn that uses CC0 must not be separated from the one that sets it.
1183 We do, however, allow I2 to follow a CC0-setting insn if that insn
1184 is passed as I1; in that case it will be deleted also.
1185 We also allow combining in this case if all the insns are adjacent
1186 because that would leave the two CC0 insns adjacent as well.
1187 It would be more logical to test whether CC0 occurs inside I1 or I2,
1188 but that would be much slower, and this ought to be equivalent. */
1190 p
= prev_nonnote_insn (insn
);
1191 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1196 /* If we get here, we have passed all the tests and the combination is
1205 /* Check if PAT is an insn - or a part of it - used to set up an
1206 argument for a function in a hard register. */
1209 sets_function_arg_p (rtx pat
)
1214 switch (GET_CODE (pat
))
1217 return sets_function_arg_p (PATTERN (pat
));
1220 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1221 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1227 inner_dest
= SET_DEST (pat
);
1228 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1229 || GET_CODE (inner_dest
) == SUBREG
1230 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1231 inner_dest
= XEXP (inner_dest
, 0);
1233 return (GET_CODE (inner_dest
) == REG
1234 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1235 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1244 /* LOC is the location within I3 that contains its pattern or the component
1245 of a PARALLEL of the pattern. We validate that it is valid for combining.
1247 One problem is if I3 modifies its output, as opposed to replacing it
1248 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1249 so would produce an insn that is not equivalent to the original insns.
1253 (set (reg:DI 101) (reg:DI 100))
1254 (set (subreg:SI (reg:DI 101) 0) <foo>)
1256 This is NOT equivalent to:
1258 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1259 (set (reg:DI 101) (reg:DI 100))])
1261 Not only does this modify 100 (in which case it might still be valid
1262 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1264 We can also run into a problem if I2 sets a register that I1
1265 uses and I1 gets directly substituted into I3 (not via I2). In that
1266 case, we would be getting the wrong value of I2DEST into I3, so we
1267 must reject the combination. This case occurs when I2 and I1 both
1268 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1269 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1270 of a SET must prevent combination from occurring.
1272 Before doing the above check, we first try to expand a field assignment
1273 into a set of logical operations.
1275 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1276 we place a register that is both set and used within I3. If more than one
1277 such register is detected, we fail.
1279 Return 1 if the combination is valid, zero otherwise. */
1282 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1283 int i1_not_in_src
, rtx
*pi3dest_killed
)
1287 if (GET_CODE (x
) == SET
)
1290 rtx dest
= SET_DEST (set
);
1291 rtx src
= SET_SRC (set
);
1292 rtx inner_dest
= dest
;
1294 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1295 || GET_CODE (inner_dest
) == SUBREG
1296 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1297 inner_dest
= XEXP (inner_dest
, 0);
1299 /* Check for the case where I3 modifies its output, as discussed
1300 above. We don't want to prevent pseudos from being combined
1301 into the address of a MEM, so only prevent the combination if
1302 i1 or i2 set the same MEM. */
1303 if ((inner_dest
!= dest
&&
1304 (GET_CODE (inner_dest
) != MEM
1305 || rtx_equal_p (i2dest
, inner_dest
)
1306 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1307 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1308 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1310 /* This is the same test done in can_combine_p except we can't test
1311 all_adjacent; we don't have to, since this instruction will stay
1312 in place, thus we are not considering increasing the lifetime of
1315 Also, if this insn sets a function argument, combining it with
1316 something that might need a spill could clobber a previous
1317 function argument; the all_adjacent test in can_combine_p also
1318 checks this; here, we do a more specific test for this case. */
1320 || (GET_CODE (inner_dest
) == REG
1321 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1322 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1323 GET_MODE (inner_dest
))))
1324 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1327 /* If DEST is used in I3, it is being killed in this insn,
1328 so record that for later.
1329 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1330 STACK_POINTER_REGNUM, since these are always considered to be
1331 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1332 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1333 && reg_referenced_p (dest
, PATTERN (i3
))
1334 && REGNO (dest
) != FRAME_POINTER_REGNUM
1335 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1336 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1338 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && (REGNO (dest
) != ARG_POINTER_REGNUM
1340 || ! fixed_regs
[REGNO (dest
)])
1342 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1344 if (*pi3dest_killed
)
1347 *pi3dest_killed
= dest
;
1351 else if (GET_CODE (x
) == PARALLEL
)
1355 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1356 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1357 i1_not_in_src
, pi3dest_killed
))
1364 /* Return 1 if X is an arithmetic expression that contains a multiplication
1365 and division. We don't count multiplications by powers of two here. */
1368 contains_muldiv (rtx x
)
1370 switch (GET_CODE (x
))
1372 case MOD
: case DIV
: case UMOD
: case UDIV
:
1376 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1377 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1379 switch (GET_RTX_CLASS (GET_CODE (x
)))
1381 case 'c': case '<': case '2':
1382 return contains_muldiv (XEXP (x
, 0))
1383 || contains_muldiv (XEXP (x
, 1));
1386 return contains_muldiv (XEXP (x
, 0));
1394 /* Determine whether INSN can be used in a combination. Return nonzero if
1395 not. This is used in try_combine to detect early some cases where we
1396 can't perform combinations. */
1399 cant_combine_insn_p (rtx insn
)
1404 /* If this isn't really an insn, we can't do anything.
1405 This can occur when flow deletes an insn that it has merged into an
1406 auto-increment address. */
1407 if (! INSN_P (insn
))
1410 /* Never combine loads and stores involving hard regs that are likely
1411 to be spilled. The register allocator can usually handle such
1412 reg-reg moves by tying. If we allow the combiner to make
1413 substitutions of likely-spilled regs, we may abort in reload.
1414 As an exception, we allow combinations involving fixed regs; these are
1415 not available to the register allocator so there's no risk involved. */
1417 set
= single_set (insn
);
1420 src
= SET_SRC (set
);
1421 dest
= SET_DEST (set
);
1422 if (GET_CODE (src
) == SUBREG
)
1423 src
= SUBREG_REG (src
);
1424 if (GET_CODE (dest
) == SUBREG
)
1425 dest
= SUBREG_REG (dest
);
1426 if (REG_P (src
) && REG_P (dest
)
1427 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1428 && ! fixed_regs
[REGNO (src
)]
1429 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1430 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs
[REGNO (dest
)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1438 /* Try to combine the insns I1 and I2 into I3.
1439 Here I1 and I2 appear earlier than I3.
1440 I1 can be zero; then we combine just I2 into I3.
1442 If we are combining three insns and the resulting insn is not recognized,
1443 try splitting it into two insns. If that happens, I2 and I3 are retained
1444 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1447 Return 0 if the combination does not work. Then nothing is changed.
1448 If we did the combination, return the insn at which combine should
1451 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1452 new direct jump instruction. */
1455 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1457 /* New patterns for I3 and I2, respectively. */
1458 rtx newpat
, newi2pat
= 0;
1459 int substed_i2
= 0, substed_i1
= 0;
1460 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1461 int added_sets_1
, added_sets_2
;
1462 /* Total number of SETs to put into I3. */
1464 /* Nonzero is I2's body now appears in I3. */
1466 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1467 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1468 /* Contains I3 if the destination of I3 is used in its source, which means
1469 that the old life of I3 is being killed. If that usage is placed into
1470 I2 and not in I3, a REG_DEAD note must be made. */
1471 rtx i3dest_killed
= 0;
1472 /* SET_DEST and SET_SRC of I2 and I1. */
1473 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1474 /* PATTERN (I2), or a copy of it in certain cases. */
1476 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1477 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1478 int i1_feeds_i3
= 0;
1479 /* Notes that must be added to REG_NOTES in I3 and I2. */
1480 rtx new_i3_notes
, new_i2_notes
;
1481 /* Notes that we substituted I3 into I2 instead of the normal case. */
1482 int i3_subst_into_i2
= 0;
1483 /* Notes that I1, I2 or I3 is a MULT operation. */
1491 /* Exit early if one of the insns involved can't be used for
1493 if (cant_combine_insn_p (i3
)
1494 || cant_combine_insn_p (i2
)
1495 || (i1
&& cant_combine_insn_p (i1
))
1496 /* We also can't do anything if I3 has a
1497 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1500 /* ??? This gives worse code, and appears to be unnecessary, since no
1501 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1502 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1508 undobuf
.other_insn
= 0;
1510 /* Reset the hard register usage information. */
1511 CLEAR_HARD_REG_SET (newpat_used_regs
);
1513 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1514 code below, set I1 to be the earlier of the two insns. */
1515 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1516 temp
= i1
, i1
= i2
, i2
= temp
;
1518 added_links_insn
= 0;
1520 /* First check for one important special-case that the code below will
1521 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1522 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1523 we may be able to replace that destination with the destination of I3.
1524 This occurs in the common code where we compute both a quotient and
1525 remainder into a structure, in which case we want to do the computation
1526 directly into the structure to avoid register-register copies.
1528 Note that this case handles both multiple sets in I2 and also
1529 cases where I2 has a number of CLOBBER or PARALLELs.
1531 We make very conservative checks below and only try to handle the
1532 most common cases of this. For example, we only handle the case
1533 where I2 and I3 are adjacent to avoid making difficult register
1536 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1537 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1538 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1539 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1540 && GET_CODE (PATTERN (i2
)) == PARALLEL
1541 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1542 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1543 below would need to check what is inside (and reg_overlap_mentioned_p
1544 doesn't support those codes anyway). Don't allow those destinations;
1545 the resulting insn isn't likely to be recognized anyway. */
1546 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1547 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1548 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1549 SET_DEST (PATTERN (i3
)))
1550 && next_real_insn (i2
) == i3
)
1552 rtx p2
= PATTERN (i2
);
1554 /* Make sure that the destination of I3,
1555 which we are going to substitute into one output of I2,
1556 is not used within another output of I2. We must avoid making this:
1557 (parallel [(set (mem (reg 69)) ...)
1558 (set (reg 69) ...)])
1559 which is not well-defined as to order of actions.
1560 (Besides, reload can't handle output reloads for this.)
1562 The problem can also happen if the dest of I3 is a memory ref,
1563 if another dest in I2 is an indirect memory ref. */
1564 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1565 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1566 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1567 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1568 SET_DEST (XVECEXP (p2
, 0, i
))))
1571 if (i
== XVECLEN (p2
, 0))
1572 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1573 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1574 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1575 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1580 subst_low_cuid
= INSN_CUID (i2
);
1582 added_sets_2
= added_sets_1
= 0;
1583 i2dest
= SET_SRC (PATTERN (i3
));
1585 /* Replace the dest in I2 with our dest and make the resulting
1586 insn the new pattern for I3. Then skip to where we
1587 validate the pattern. Everything was set up above. */
1588 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1589 SET_DEST (PATTERN (i3
)));
1592 i3_subst_into_i2
= 1;
1593 goto validate_replacement
;
1597 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1598 one of those words to another constant, merge them by making a new
1601 && (temp
= single_set (i2
)) != 0
1602 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1603 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1604 && GET_CODE (SET_DEST (temp
)) == REG
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1607 && GET_CODE (PATTERN (i3
)) == SET
1608 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1609 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1610 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1611 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1612 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1614 HOST_WIDE_INT lo
, hi
;
1616 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1617 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1620 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1621 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1624 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1626 /* We don't handle the case of the target word being wider
1627 than a host wide int. */
1628 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1631 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1632 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1633 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1635 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1636 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1637 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1639 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1640 >> (HOST_BITS_PER_WIDE_INT
- 1));
1642 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1643 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1644 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1645 (INTVAL (SET_SRC (PATTERN (i3
)))));
1647 hi
= lo
< 0 ? -1 : 0;
1650 /* We don't handle the case of the higher word not fitting
1651 entirely in either hi or lo. */
1656 subst_low_cuid
= INSN_CUID (i2
);
1657 added_sets_2
= added_sets_1
= 0;
1658 i2dest
= SET_DEST (temp
);
1660 SUBST (SET_SRC (temp
),
1661 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1663 newpat
= PATTERN (i2
);
1664 goto validate_replacement
;
1668 /* If we have no I1 and I2 looks like:
1669 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1671 make up a dummy I1 that is
1674 (set (reg:CC X) (compare:CC Y (const_int 0)))
1676 (We can ignore any trailing CLOBBERs.)
1678 This undoes a previous combination and allows us to match a branch-and-
1681 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1682 && XVECLEN (PATTERN (i2
), 0) >= 2
1683 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1684 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1686 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1687 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1688 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1689 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1690 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1691 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1693 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1694 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1699 /* We make I1 with the same INSN_UID as I2. This gives it
1700 the same INSN_CUID for value tracking. Our fake I1 will
1701 never appear in the insn stream so giving it the same INSN_UID
1702 as I2 will not cause a problem. */
1704 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1705 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1706 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1709 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1710 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1711 SET_DEST (PATTERN (i1
)));
1716 /* Verify that I2 and I1 are valid for combining. */
1717 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1718 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1724 /* Record whether I2DEST is used in I2SRC and similarly for the other
1725 cases. Knowing this will help in register status updating below. */
1726 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1727 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1728 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1732 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1734 /* Ensure that I3's pattern can be the destination of combines. */
1735 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1736 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1743 /* See if any of the insns is a MULT operation. Unless one is, we will
1744 reject a combination that is, since it must be slower. Be conservative
1746 if (GET_CODE (i2src
) == MULT
1747 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1748 || (GET_CODE (PATTERN (i3
)) == SET
1749 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1753 We used to do this EXCEPT in one case: I3 has a post-inc in an
1754 output operand. However, that exception can give rise to insns like
1756 which is a famous insn on the PDP-11 where the value of r3 used as the
1757 source was model-dependent. Avoid this sort of thing. */
1760 if (!(GET_CODE (PATTERN (i3
)) == SET
1761 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1762 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1765 /* It's not the exception. */
1768 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1769 if (REG_NOTE_KIND (link
) == REG_INC
1770 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1772 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1779 /* See if the SETs in I1 or I2 need to be kept around in the merged
1780 instruction: whenever the value set there is still needed past I3.
1781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1783 For the SET in I1, we have two cases: If I1 and I2 independently
1784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1786 in I1 needs to be kept around unless I1DEST dies or is set in either
1787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1788 I1DEST. If so, we know I1 feeds into I2. */
1790 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1793 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1794 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1796 /* If the set in I2 needs to be kept around, we must make a copy of
1797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1798 PATTERN (I2), we are only substituting for the original I1DEST, not into
1799 an already-substituted copy. This also prevents making self-referential
1800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1803 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1804 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1808 i2pat
= copy_rtx (i2pat
);
1812 /* Substitute in the latest insn for the regs set by the earlier ones. */
1814 maxreg
= max_reg_num ();
1818 /* It is possible that the source of I2 or I1 may be performing an
1819 unneeded operation, such as a ZERO_EXTEND of something that is known
1820 to have the high part zero. Handle that case by letting subst look at
1821 the innermost one of them.
1823 Another way to do this would be to have a function that tries to
1824 simplify a single insn instead of merging two or more insns. We don't
1825 do this because of the potential of infinite loops and because
1826 of the potential extra memory required. However, doing it the way
1827 we are is a bit of a kludge and doesn't catch all cases.
1829 But only do this if -fexpensive-optimizations since it slows things down
1830 and doesn't usually win. */
1832 if (flag_expensive_optimizations
)
1834 /* Pass pc_rtx so no substitutions are done, just simplifications.
1835 The cases that we are interested in here do not involve the few
1836 cases were is_replaced is checked. */
1839 subst_low_cuid
= INSN_CUID (i1
);
1840 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1844 subst_low_cuid
= INSN_CUID (i2
);
1845 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1850 /* Many machines that don't use CC0 have insns that can both perform an
1851 arithmetic operation and set the condition code. These operations will
1852 be represented as a PARALLEL with the first element of the vector
1853 being a COMPARE of an arithmetic operation with the constant zero.
1854 The second element of the vector will set some pseudo to the result
1855 of the same arithmetic operation. If we simplify the COMPARE, we won't
1856 match such a pattern and so will generate an extra insn. Here we test
1857 for this case, where both the comparison and the operation result are
1858 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1859 I2SRC. Later we will make the PARALLEL that contains I2. */
1861 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1862 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1863 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1864 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1866 #ifdef EXTRA_CC_MODES
1868 enum machine_mode compare_mode
;
1871 newpat
= PATTERN (i3
);
1872 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1876 #ifdef EXTRA_CC_MODES
1877 /* See if a COMPARE with the operand we substituted in should be done
1878 with the mode that is currently being used. If not, do the same
1879 processing we do in `subst' for a SET; namely, if the destination
1880 is used only once, try to replace it with a register of the proper
1881 mode and also replace the COMPARE. */
1882 if (undobuf
.other_insn
== 0
1883 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1884 &undobuf
.other_insn
))
1885 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1887 != GET_MODE (SET_DEST (newpat
))))
1889 unsigned int regno
= REGNO (SET_DEST (newpat
));
1890 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1892 if (regno
< FIRST_PSEUDO_REGISTER
1893 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1894 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1896 if (regno
>= FIRST_PSEUDO_REGISTER
)
1897 SUBST (regno_reg_rtx
[regno
], new_dest
);
1899 SUBST (SET_DEST (newpat
), new_dest
);
1900 SUBST (XEXP (*cc_use
, 0), new_dest
);
1901 SUBST (SET_SRC (newpat
),
1902 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1905 undobuf
.other_insn
= 0;
1912 n_occurrences
= 0; /* `subst' counts here */
1914 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1915 need to make a unique copy of I2SRC each time we substitute it
1916 to avoid self-referential rtl. */
1918 subst_low_cuid
= INSN_CUID (i2
);
1919 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1920 ! i1_feeds_i3
&& i1dest_in_i1src
);
1923 /* Record whether i2's body now appears within i3's body. */
1924 i2_is_used
= n_occurrences
;
1927 /* If we already got a failure, don't try to do more. Otherwise,
1928 try to substitute in I1 if we have it. */
1930 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1932 /* Before we can do this substitution, we must redo the test done
1933 above (see detailed comments there) that ensures that I1DEST
1934 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1936 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1944 subst_low_cuid
= INSN_CUID (i1
);
1945 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1949 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1950 to count all the ways that I2SRC and I1SRC can be used. */
1951 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1952 && i2_is_used
+ added_sets_2
> 1)
1953 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1954 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1956 /* Fail if we tried to make a new register (we used to abort, but there's
1957 really no reason to). */
1958 || max_reg_num () != maxreg
1959 /* Fail if we couldn't do something and have a CLOBBER. */
1960 || GET_CODE (newpat
) == CLOBBER
1961 /* Fail if this new pattern is a MULT and we didn't have one before
1962 at the outer level. */
1963 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1970 /* If the actions of the earlier insns must be kept
1971 in addition to substituting them into the latest one,
1972 we must make a new PARALLEL for the latest insn
1973 to hold additional the SETs. */
1975 if (added_sets_1
|| added_sets_2
)
1979 if (GET_CODE (newpat
) == PARALLEL
)
1981 rtvec old
= XVEC (newpat
, 0);
1982 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1983 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1984 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1985 sizeof (old
->elem
[0]) * old
->num_elem
);
1990 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1991 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1992 XVECEXP (newpat
, 0, 0) = old
;
1996 XVECEXP (newpat
, 0, --total_sets
)
1997 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1998 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2002 /* If there is no I1, use I2's body as is. We used to also not do
2003 the subst call below if I2 was substituted into I3,
2004 but that could lose a simplification. */
2006 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2008 /* See comment where i2pat is assigned. */
2009 XVECEXP (newpat
, 0, --total_sets
)
2010 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2014 /* We come here when we are replacing a destination in I2 with the
2015 destination of I3. */
2016 validate_replacement
:
2018 /* Note which hard regs this insn has as inputs. */
2019 mark_used_regs_combine (newpat
);
2021 /* Is the result of combination a valid instruction? */
2022 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2024 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2025 the second SET's destination is a register that is unused. In that case,
2026 we just need the first SET. This can occur when simplifying a divmod
2027 insn. We *must* test for this case here because the code below that
2028 splits two independent SETs doesn't handle this case correctly when it
2029 updates the register status. Also check the case where the first
2030 SET's destination is unused. That would not cause incorrect code, but
2031 does cause an unneeded insn to remain. */
2033 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2034 && XVECLEN (newpat
, 0) == 2
2035 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2036 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2037 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2038 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2039 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2040 && asm_noperands (newpat
) < 0)
2042 newpat
= XVECEXP (newpat
, 0, 0);
2043 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2046 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2047 && XVECLEN (newpat
, 0) == 2
2048 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2049 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2051 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2052 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2053 && asm_noperands (newpat
) < 0)
2055 newpat
= XVECEXP (newpat
, 0, 1);
2056 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2059 /* If we were combining three insns and the result is a simple SET
2060 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2061 insns. There are two ways to do this. It can be split using a
2062 machine-specific method (like when you have an addition of a large
2063 constant) or by combine in the function find_split_point. */
2065 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2066 && asm_noperands (newpat
) < 0)
2068 rtx m_split
, *split
;
2069 rtx ni2dest
= i2dest
;
2071 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2072 use I2DEST as a scratch register will help. In the latter case,
2073 convert I2DEST to the mode of the source of NEWPAT if we can. */
2075 m_split
= split_insns (newpat
, i3
);
2077 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2078 inputs of NEWPAT. */
2080 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2081 possible to try that as a scratch reg. This would require adding
2082 more code to make it work though. */
2084 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2086 /* If I2DEST is a hard register or the only use of a pseudo,
2087 we can change its mode. */
2088 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2089 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2090 && GET_CODE (i2dest
) == REG
2091 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2092 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2093 && ! REG_USERVAR_P (i2dest
))))
2094 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2097 m_split
= split_insns (gen_rtx_PARALLEL
2099 gen_rtvec (2, newpat
,
2100 gen_rtx_CLOBBER (VOIDmode
,
2103 /* If the split with the mode-changed register didn't work, try
2104 the original register. */
2105 if (! m_split
&& ni2dest
!= i2dest
)
2108 m_split
= split_insns (gen_rtx_PARALLEL
2110 gen_rtvec (2, newpat
,
2111 gen_rtx_CLOBBER (VOIDmode
,
2117 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2119 m_split
= PATTERN (m_split
);
2120 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2121 if (insn_code_number
>= 0)
2124 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2125 && (next_real_insn (i2
) == i3
2126 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2129 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2130 newi2pat
= PATTERN (m_split
);
2132 i3set
= single_set (NEXT_INSN (m_split
));
2133 i2set
= single_set (m_split
);
2135 /* In case we changed the mode of I2DEST, replace it in the
2136 pseudo-register table here. We can't do it above in case this
2137 code doesn't get executed and we do a split the other way. */
2139 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2140 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2142 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2144 /* If I2 or I3 has multiple SETs, we won't know how to track
2145 register status, so don't use these insns. If I2's destination
2146 is used between I2 and I3, we also can't use these insns. */
2148 if (i2_code_number
>= 0 && i2set
&& i3set
2149 && (next_real_insn (i2
) == i3
2150 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2151 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2153 if (insn_code_number
>= 0)
2156 /* It is possible that both insns now set the destination of I3.
2157 If so, we must show an extra use of it. */
2159 if (insn_code_number
>= 0)
2161 rtx new_i3_dest
= SET_DEST (i3set
);
2162 rtx new_i2_dest
= SET_DEST (i2set
);
2164 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2165 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2166 || GET_CODE (new_i3_dest
) == SUBREG
)
2167 new_i3_dest
= XEXP (new_i3_dest
, 0);
2169 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2170 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2171 || GET_CODE (new_i2_dest
) == SUBREG
)
2172 new_i2_dest
= XEXP (new_i2_dest
, 0);
2174 if (GET_CODE (new_i3_dest
) == REG
2175 && GET_CODE (new_i2_dest
) == REG
2176 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2177 REG_N_SETS (REGNO (new_i2_dest
))++;
2181 /* If we can split it and use I2DEST, go ahead and see if that
2182 helps things be recognized. Verify that none of the registers
2183 are set between I2 and I3. */
2184 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2186 && GET_CODE (i2dest
) == REG
2188 /* We need I2DEST in the proper mode. If it is a hard register
2189 or the only use of a pseudo, we can change its mode. */
2190 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2191 || GET_MODE (*split
) == VOIDmode
2192 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2193 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2194 && ! REG_USERVAR_P (i2dest
)))
2195 && (next_real_insn (i2
) == i3
2196 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2197 /* We can't overwrite I2DEST if its value is still used by
2199 && ! reg_referenced_p (i2dest
, newpat
))
2201 rtx newdest
= i2dest
;
2202 enum rtx_code split_code
= GET_CODE (*split
);
2203 enum machine_mode split_mode
= GET_MODE (*split
);
2205 /* Get NEWDEST as a register in the proper mode. We have already
2206 validated that we can do this. */
2207 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2209 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2211 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2212 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2215 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2216 an ASHIFT. This can occur if it was inside a PLUS and hence
2217 appeared to be a memory address. This is a kludge. */
2218 if (split_code
== MULT
2219 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2220 && INTVAL (XEXP (*split
, 1)) > 0
2221 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2223 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2224 XEXP (*split
, 0), GEN_INT (i
)));
2225 /* Update split_code because we may not have a multiply
2227 split_code
= GET_CODE (*split
);
2230 #ifdef INSN_SCHEDULING
2231 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2232 be written as a ZERO_EXTEND. */
2233 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2235 #ifdef LOAD_EXTEND_OP
2236 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2237 what it really is. */
2238 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2240 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2241 SUBREG_REG (*split
)));
2244 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2245 SUBREG_REG (*split
)));
2249 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2250 SUBST (*split
, newdest
);
2251 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2253 /* If the split point was a MULT and we didn't have one before,
2254 don't use one now. */
2255 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2256 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2260 /* Check for a case where we loaded from memory in a narrow mode and
2261 then sign extended it, but we need both registers. In that case,
2262 we have a PARALLEL with both loads from the same memory location.
2263 We can split this into a load from memory followed by a register-register
2264 copy. This saves at least one insn, more if register allocation can
2267 We cannot do this if the destination of the first assignment is a
2268 condition code register or cc0. We eliminate this case by making sure
2269 the SET_DEST and SET_SRC have the same mode.
2271 We cannot do this if the destination of the second assignment is
2272 a register that we have already assumed is zero-extended. Similarly
2273 for a SUBREG of such a register. */
2275 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2276 && GET_CODE (newpat
) == PARALLEL
2277 && XVECLEN (newpat
, 0) == 2
2278 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2279 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2280 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2281 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2282 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2290 (GET_CODE (temp
) == REG
2291 && reg_nonzero_bits
[REGNO (temp
)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits
[REGNO (temp
)]
2295 != GET_MODE_MASK (word_mode
))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2297 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2298 (GET_CODE (temp
) == REG
2299 && reg_nonzero_bits
[REGNO (temp
)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits
[REGNO (temp
)]
2303 != GET_MODE_MASK (word_mode
)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2305 SET_SRC (XVECEXP (newpat
, 0, 1)))
2306 && ! find_reg_note (i3
, REG_UNUSED
,
2307 SET_DEST (XVECEXP (newpat
, 0, 0))))
2311 newi2pat
= XVECEXP (newpat
, 0, 0);
2312 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2313 newpat
= XVECEXP (newpat
, 0, 1);
2314 SUBST (SET_SRC (newpat
),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2316 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2318 if (i2_code_number
>= 0)
2319 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2321 if (insn_code_number
>= 0)
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3
) = newpat
;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn
= NEXT_INSN (i3
);
2348 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2349 || insn
!= this_basic_block
->next_bb
->head
);
2350 insn
= NEXT_INSN (insn
))
2352 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2354 for (link
= LOG_LINKS (insn
); link
;
2355 link
= XEXP (link
, 1))
2356 if (XEXP (link
, 0) == i3
)
2357 XEXP (link
, 0) = i1
;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2371 && GET_CODE (newpat
) == PARALLEL
2372 && XVECLEN (newpat
, 0) == 2
2373 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2385 XVECEXP (newpat
, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2387 XVECEXP (newpat
, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2395 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2397 newi2pat
= XVECEXP (newpat
, 0, 0);
2398 newpat
= XVECEXP (newpat
, 0, 1);
2403 newi2pat
= XVECEXP (newpat
, 0, 1);
2404 newpat
= XVECEXP (newpat
, 0, 0);
2407 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2409 if (i2_code_number
>= 0)
2410 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2413 /* If it still isn't recognized, fail and change things back the way they
2415 if ((insn_code_number
< 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf
.other_insn
)
2426 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2427 rtx new_other_notes
;
2430 CLEAR_HARD_REG_SET (newpat_used_regs
);
2432 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2435 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2441 PATTERN (undobuf
.other_insn
) = other_pat
;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2448 next
= XEXP (note
, 1);
2450 if (REG_NOTE_KIND (note
) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2453 if (GET_CODE (XEXP (note
, 0)) == REG
)
2454 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2456 remove_note (undobuf
.other_insn
, note
);
2460 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2461 if (GET_CODE (XEXP (note
, 0)) == REG
)
2462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2464 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2465 undobuf
.other_insn
, NULL_RTX
);
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p
= prev_nonnote_insn (i3
);
2472 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2473 && sets_cc0_p (newi2pat
))
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes
, i2notes
, i1notes
= 0;
2486 rtx i3links
, i2links
, i1links
= 0;
2490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2492 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2493 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2495 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2497 /* Ensure that we do not have something that should not be shared but
2498 occurs multiple times in the new insns. Check this by first
2499 resetting all the `used' flags and then copying anything is shared. */
2501 reset_used_flags (i3notes
);
2502 reset_used_flags (i2notes
);
2503 reset_used_flags (i1notes
);
2504 reset_used_flags (newpat
);
2505 reset_used_flags (newi2pat
);
2506 if (undobuf
.other_insn
)
2507 reset_used_flags (PATTERN (undobuf
.other_insn
));
2509 i3notes
= copy_rtx_if_shared (i3notes
);
2510 i2notes
= copy_rtx_if_shared (i2notes
);
2511 i1notes
= copy_rtx_if_shared (i1notes
);
2512 newpat
= copy_rtx_if_shared (newpat
);
2513 newi2pat
= copy_rtx_if_shared (newi2pat
);
2514 if (undobuf
.other_insn
)
2515 reset_used_flags (PATTERN (undobuf
.other_insn
));
2517 INSN_CODE (i3
) = insn_code_number
;
2518 PATTERN (i3
) = newpat
;
2520 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2522 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2524 reset_used_flags (call_usage
);
2525 call_usage
= copy_rtx (call_usage
);
2528 replace_rtx (call_usage
, i2dest
, i2src
);
2531 replace_rtx (call_usage
, i1dest
, i1src
);
2533 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2536 if (undobuf
.other_insn
)
2537 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2539 /* We had one special case above where I2 had more than one set and
2540 we replaced a destination of one of those sets with the destination
2541 of I3. In that case, we have to update LOG_LINKS of insns later
2542 in this basic block. Note that this (expensive) case is rare.
2544 Also, in this case, we must pretend that all REG_NOTEs for I2
2545 actually came from I3, so that REG_UNUSED notes from I2 will be
2546 properly handled. */
2548 if (i3_subst_into_i2
)
2550 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2551 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2552 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2553 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2554 && ! find_reg_note (i2
, REG_UNUSED
,
2555 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2556 for (temp
= NEXT_INSN (i2
);
2557 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2558 || this_basic_block
->head
!= temp
);
2559 temp
= NEXT_INSN (temp
))
2560 if (temp
!= i3
&& INSN_P (temp
))
2561 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2562 if (XEXP (link
, 0) == i2
)
2563 XEXP (link
, 0) = i3
;
2568 while (XEXP (link
, 1))
2569 link
= XEXP (link
, 1);
2570 XEXP (link
, 1) = i2notes
;
2584 INSN_CODE (i2
) = i2_code_number
;
2585 PATTERN (i2
) = newi2pat
;
2589 PUT_CODE (i2
, NOTE
);
2590 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2591 NOTE_SOURCE_FILE (i2
) = 0;
2598 PUT_CODE (i1
, NOTE
);
2599 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2600 NOTE_SOURCE_FILE (i1
) = 0;
2603 /* Get death notes for everything that is now used in either I3 or
2604 I2 and used to die in a previous insn. If we built two new
2605 patterns, move from I1 to I2 then I2 to I3 so that we get the
2606 proper movement on registers that I2 modifies. */
2610 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2611 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2614 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2617 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2619 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2621 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2623 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2625 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2627 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2628 know these are REG_UNUSED and want them to go to the desired insn,
2629 so we always pass it as i3. We have not counted the notes in
2630 reg_n_deaths yet, so we need to do so now. */
2632 if (newi2pat
&& new_i2_notes
)
2634 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2635 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2636 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2638 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2643 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2644 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2645 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2647 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2650 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2651 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2652 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2653 in that case, it might delete I2. Similarly for I2 and I1.
2654 Show an additional death due to the REG_DEAD note we make here. If
2655 we discard it in distribute_notes, we will decrement it again. */
2659 if (GET_CODE (i3dest_killed
) == REG
)
2660 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2662 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2665 NULL_RTX
, i2
, NULL_RTX
);
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2669 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2672 if (i2dest_in_i2src
)
2674 if (GET_CODE (i2dest
) == REG
)
2675 REG_N_DEATHS (REGNO (i2dest
))++;
2677 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i2
, NULL_RTX
);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2685 if (i1dest_in_i1src
)
2687 if (GET_CODE (i1dest
) == REG
)
2688 REG_N_DEATHS (REGNO (i1dest
))++;
2690 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2691 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2692 NULL_RTX
, i2
, NULL_RTX
);
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2695 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2698 distribute_links (i3links
);
2699 distribute_links (i2links
);
2700 distribute_links (i1links
);
2702 if (GET_CODE (i2dest
) == REG
)
2705 rtx i2_insn
= 0, i2_val
= 0, set
;
2707 /* The insn that used to set this register doesn't exist, and
2708 this life of the register may not exist either. See if one of
2709 I3's links points to an insn that sets I2DEST. If it does,
2710 that is now the last known value for I2DEST. If we don't update
2711 this and I2 set the register to a value that depended on its old
2712 contents, we will get confused. If this insn is used, thing
2713 will be set correctly in combine_instructions. */
2715 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2716 if ((set
= single_set (XEXP (link
, 0))) != 0
2717 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2718 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2720 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2722 /* If the reg formerly set in I2 died only once and that was in I3,
2723 zero its use count so it won't make `reload' do any work. */
2725 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2726 && ! i2dest_in_i2src
)
2728 regno
= REGNO (i2dest
);
2729 REG_N_SETS (regno
)--;
2733 if (i1
&& GET_CODE (i1dest
) == REG
)
2736 rtx i1_insn
= 0, i1_val
= 0, set
;
2738 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2739 if ((set
= single_set (XEXP (link
, 0))) != 0
2740 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2741 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2743 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2745 regno
= REGNO (i1dest
);
2746 if (! added_sets_1
&& ! i1dest_in_i1src
)
2747 REG_N_SETS (regno
)--;
2750 /* Update reg_nonzero_bits et al for any changes that may have been made
2751 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2752 important. Because newi2pat can affect nonzero_bits of newpat */
2754 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2755 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 /* Set new_direct_jump_p if a new return or simple jump instruction
2760 If I3 is now an unconditional jump, ensure that it has a
2761 BARRIER following it since it may have initially been a
2762 conditional jump. It may also be the last nonnote insn. */
2764 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2766 *new_direct_jump_p
= 1;
2768 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2769 || GET_CODE (temp
) != BARRIER
)
2770 emit_barrier_after (i3
);
2773 if (undobuf
.other_insn
!= NULL_RTX
2774 && (returnjump_p (undobuf
.other_insn
)
2775 || any_uncondjump_p (undobuf
.other_insn
)))
2777 *new_direct_jump_p
= 1;
2779 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2780 || GET_CODE (temp
) != BARRIER
)
2781 emit_barrier_after (undobuf
.other_insn
);
2784 /* An NOOP jump does not need barrier, but it does need cleaning up
2786 if (GET_CODE (newpat
) == SET
2787 && SET_SRC (newpat
) == pc_rtx
2788 && SET_DEST (newpat
) == pc_rtx
)
2789 *new_direct_jump_p
= 1;
2792 combine_successes
++;
2795 if (added_links_insn
2796 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2797 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2798 return added_links_insn
;
2800 return newi2pat
? i2
: i3
;
2803 /* Undo all the modifications recorded in undobuf. */
2808 struct undo
*undo
, *next
;
2810 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2814 *undo
->where
.i
= undo
->old_contents
.i
;
2816 *undo
->where
.r
= undo
->old_contents
.r
;
2818 undo
->next
= undobuf
.frees
;
2819 undobuf
.frees
= undo
;
2825 /* We've committed to accepting the changes we made. Move all
2826 of the undos to the free list. */
2831 struct undo
*undo
, *next
;
2833 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2836 undo
->next
= undobuf
.frees
;
2837 undobuf
.frees
= undo
;
2843 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2844 where we have an arithmetic expression and return that point. LOC will
2847 try_combine will call this function to see if an insn can be split into
2851 find_split_point (rtx
*loc
, rtx insn
)
2854 enum rtx_code code
= GET_CODE (x
);
2856 unsigned HOST_WIDE_INT len
= 0;
2857 HOST_WIDE_INT pos
= 0;
2859 rtx inner
= NULL_RTX
;
2861 /* First special-case some codes. */
2865 #ifdef INSN_SCHEDULING
2866 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2868 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2871 return find_split_point (&SUBREG_REG (x
), insn
);
2875 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2876 using LO_SUM and HIGH. */
2877 if (GET_CODE (XEXP (x
, 0)) == CONST
2878 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2881 gen_rtx_LO_SUM (Pmode
,
2882 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2884 return &XEXP (XEXP (x
, 0), 0);
2888 /* If we have a PLUS whose second operand is a constant and the
2889 address is not valid, perhaps will can split it up using
2890 the machine-specific way to split large constants. We use
2891 the first pseudo-reg (one of the virtual regs) as a placeholder;
2892 it will not remain in the result. */
2893 if (GET_CODE (XEXP (x
, 0)) == PLUS
2894 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2895 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2897 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2898 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2901 /* This should have produced two insns, each of which sets our
2902 placeholder. If the source of the second is a valid address,
2903 we can make put both sources together and make a split point
2907 && NEXT_INSN (seq
) != NULL_RTX
2908 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2909 && GET_CODE (seq
) == INSN
2910 && GET_CODE (PATTERN (seq
)) == SET
2911 && SET_DEST (PATTERN (seq
)) == reg
2912 && ! reg_mentioned_p (reg
,
2913 SET_SRC (PATTERN (seq
)))
2914 && GET_CODE (NEXT_INSN (seq
)) == INSN
2915 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2916 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2917 && memory_address_p (GET_MODE (x
),
2918 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2920 rtx src1
= SET_SRC (PATTERN (seq
));
2921 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2923 /* Replace the placeholder in SRC2 with SRC1. If we can
2924 find where in SRC2 it was placed, that can become our
2925 split point and we can replace this address with SRC2.
2926 Just try two obvious places. */
2928 src2
= replace_rtx (src2
, reg
, src1
);
2930 if (XEXP (src2
, 0) == src1
)
2931 split
= &XEXP (src2
, 0);
2932 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2933 && XEXP (XEXP (src2
, 0), 0) == src1
)
2934 split
= &XEXP (XEXP (src2
, 0), 0);
2938 SUBST (XEXP (x
, 0), src2
);
2943 /* If that didn't work, perhaps the first operand is complex and
2944 needs to be computed separately, so make a split point there.
2945 This will occur on machines that just support REG + CONST
2946 and have a constant moved through some previous computation. */
2948 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2949 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2950 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2952 return &XEXP (XEXP (x
, 0), 0);
2958 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2959 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2960 we need to put the operand into a register. So split at that
2963 if (SET_DEST (x
) == cc0_rtx
2964 && GET_CODE (SET_SRC (x
)) != COMPARE
2965 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2966 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2967 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2968 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2969 return &SET_SRC (x
);
2972 /* See if we can split SET_SRC as it stands. */
2973 split
= find_split_point (&SET_SRC (x
), insn
);
2974 if (split
&& split
!= &SET_SRC (x
))
2977 /* See if we can split SET_DEST as it stands. */
2978 split
= find_split_point (&SET_DEST (x
), insn
);
2979 if (split
&& split
!= &SET_DEST (x
))
2982 /* See if this is a bitfield assignment with everything constant. If
2983 so, this is an IOR of an AND, so split it into that. */
2984 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2985 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2986 <= HOST_BITS_PER_WIDE_INT
)
2987 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2988 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2989 && GET_CODE (SET_SRC (x
)) == CONST_INT
2990 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2991 + INTVAL (XEXP (SET_DEST (x
), 2)))
2992 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2993 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2995 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2996 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2997 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2998 rtx dest
= XEXP (SET_DEST (x
), 0);
2999 enum machine_mode mode
= GET_MODE (dest
);
3000 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3002 if (BITS_BIG_ENDIAN
)
3003 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3007 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3010 gen_binary (IOR
, mode
,
3011 gen_binary (AND
, mode
, dest
,
3012 gen_int_mode (~(mask
<< pos
),
3014 GEN_INT (src
<< pos
)));
3016 SUBST (SET_DEST (x
), dest
);
3018 split
= find_split_point (&SET_SRC (x
), insn
);
3019 if (split
&& split
!= &SET_SRC (x
))
3023 /* Otherwise, see if this is an operation that we can split into two.
3024 If so, try to split that. */
3025 code
= GET_CODE (SET_SRC (x
));
3030 /* If we are AND'ing with a large constant that is only a single
3031 bit and the result is only being used in a context where we
3032 need to know if it is zero or nonzero, replace it with a bit
3033 extraction. This will avoid the large constant, which might
3034 have taken more than one insn to make. If the constant were
3035 not a valid argument to the AND but took only one insn to make,
3036 this is no worse, but if it took more than one insn, it will
3039 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3040 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3041 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3042 && GET_CODE (SET_DEST (x
)) == REG
3043 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3044 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3045 && XEXP (*split
, 0) == SET_DEST (x
)
3046 && XEXP (*split
, 1) == const0_rtx
)
3048 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3049 XEXP (SET_SRC (x
), 0),
3050 pos
, NULL_RTX
, 1, 1, 0, 0);
3051 if (extraction
!= 0)
3053 SUBST (SET_SRC (x
), extraction
);
3054 return find_split_point (loc
, insn
);
3060 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3061 is known to be on, this can be converted into a NEG of a shift. */
3062 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3063 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3064 && 1 <= (pos
= exact_log2
3065 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3066 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3068 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3072 gen_rtx_LSHIFTRT (mode
,
3073 XEXP (SET_SRC (x
), 0),
3076 split
= find_split_point (&SET_SRC (x
), insn
);
3077 if (split
&& split
!= &SET_SRC (x
))
3083 inner
= XEXP (SET_SRC (x
), 0);
3085 /* We can't optimize if either mode is a partial integer
3086 mode as we don't know how many bits are significant
3088 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3089 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3093 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3099 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3100 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3102 inner
= XEXP (SET_SRC (x
), 0);
3103 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3104 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3106 if (BITS_BIG_ENDIAN
)
3107 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3108 unsignedp
= (code
== ZERO_EXTRACT
);
3116 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3118 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3120 /* For unsigned, we have a choice of a shift followed by an
3121 AND or two shifts. Use two shifts for field sizes where the
3122 constant might be too large. We assume here that we can
3123 always at least get 8-bit constants in an AND insn, which is
3124 true for every current RISC. */
3126 if (unsignedp
&& len
<= 8)
3131 (mode
, gen_lowpart_for_combine (mode
, inner
),
3133 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3135 split
= find_split_point (&SET_SRC (x
), insn
);
3136 if (split
&& split
!= &SET_SRC (x
))
3143 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3144 gen_rtx_ASHIFT (mode
,
3145 gen_lowpart_for_combine (mode
, inner
),
3146 GEN_INT (GET_MODE_BITSIZE (mode
)
3148 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3150 split
= find_split_point (&SET_SRC (x
), insn
);
3151 if (split
&& split
!= &SET_SRC (x
))
3156 /* See if this is a simple operation with a constant as the second
3157 operand. It might be that this constant is out of range and hence
3158 could be used as a split point. */
3159 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3160 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3161 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3162 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3163 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3164 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3165 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3167 return &XEXP (SET_SRC (x
), 1);
3169 /* Finally, see if this is a simple operation with its first operand
3170 not in a register. The operation might require this operand in a
3171 register, so return it as a split point. We can always do this
3172 because if the first operand were another operation, we would have
3173 already found it as a split point. */
3174 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3175 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3178 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3179 return &XEXP (SET_SRC (x
), 0);
3185 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3186 it is better to write this as (not (ior A B)) so we can split it.
3187 Similarly for IOR. */
3188 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3191 gen_rtx_NOT (GET_MODE (x
),
3192 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3194 XEXP (XEXP (x
, 0), 0),
3195 XEXP (XEXP (x
, 1), 0))));
3196 return find_split_point (loc
, insn
);
3199 /* Many RISC machines have a large set of logical insns. If the
3200 second operand is a NOT, put it first so we will try to split the
3201 other operand first. */
3202 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3204 rtx tem
= XEXP (x
, 0);
3205 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3206 SUBST (XEXP (x
, 1), tem
);
3214 /* Otherwise, select our actions depending on our rtx class. */
3215 switch (GET_RTX_CLASS (code
))
3217 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3219 split
= find_split_point (&XEXP (x
, 2), insn
);
3222 /* ... fall through ... */
3226 split
= find_split_point (&XEXP (x
, 1), insn
);
3229 /* ... fall through ... */
3231 /* Some machines have (and (shift ...) ...) insns. If X is not
3232 an AND, but XEXP (X, 0) is, use it as our split point. */
3233 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3234 return &XEXP (x
, 0);
3236 split
= find_split_point (&XEXP (x
, 0), insn
);
3242 /* Otherwise, we don't have a split point. */
3246 /* Throughout X, replace FROM with TO, and return the result.
3247 The result is TO if X is FROM;
3248 otherwise the result is X, but its contents may have been modified.
3249 If they were modified, a record was made in undobuf so that
3250 undo_all will (among other things) return X to its original state.
3252 If the number of changes necessary is too much to record to undo,
3253 the excess changes are not made, so the result is invalid.
3254 The changes already made can still be undone.
3255 undobuf.num_undo is incremented for such changes, so by testing that
3256 the caller can tell whether the result is valid.
3258 `n_occurrences' is incremented each time FROM is replaced.
3260 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3262 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3263 by copying if `n_occurrences' is nonzero. */
3266 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3268 enum rtx_code code
= GET_CODE (x
);
3269 enum machine_mode op0_mode
= VOIDmode
;
3274 /* Two expressions are equal if they are identical copies of a shared
3275 RTX or if they are both registers with the same register number
3278 #define COMBINE_RTX_EQUAL_P(X,Y) \
3280 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3281 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3283 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3286 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3289 /* If X and FROM are the same register but different modes, they will
3290 not have been seen as equal above. However, flow.c will make a
3291 LOG_LINKS entry for that case. If we do nothing, we will try to
3292 rerecognize our original insn and, when it succeeds, we will
3293 delete the feeding insn, which is incorrect.
3295 So force this insn not to match in this (rare) case. */
3296 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3297 && REGNO (x
) == REGNO (from
))
3298 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3300 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3301 of which may contain things that can be combined. */
3302 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3305 /* It is possible to have a subexpression appear twice in the insn.
3306 Suppose that FROM is a register that appears within TO.
3307 Then, after that subexpression has been scanned once by `subst',
3308 the second time it is scanned, TO may be found. If we were
3309 to scan TO here, we would find FROM within it and create a
3310 self-referent rtl structure which is completely wrong. */
3311 if (COMBINE_RTX_EQUAL_P (x
, to
))
3314 /* Parallel asm_operands need special attention because all of the
3315 inputs are shared across the arms. Furthermore, unsharing the
3316 rtl results in recognition failures. Failure to handle this case
3317 specially can result in circular rtl.
3319 Solve this by doing a normal pass across the first entry of the
3320 parallel, and only processing the SET_DESTs of the subsequent
3323 if (code
== PARALLEL
3324 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3325 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3327 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3329 /* If this substitution failed, this whole thing fails. */
3330 if (GET_CODE (new) == CLOBBER
3331 && XEXP (new, 0) == const0_rtx
)
3334 SUBST (XVECEXP (x
, 0, 0), new);
3336 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3338 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3340 if (GET_CODE (dest
) != REG
3341 && GET_CODE (dest
) != CC0
3342 && GET_CODE (dest
) != PC
)
3344 new = subst (dest
, from
, to
, 0, unique_copy
);
3346 /* If this substitution failed, this whole thing fails. */
3347 if (GET_CODE (new) == CLOBBER
3348 && XEXP (new, 0) == const0_rtx
)
3351 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3357 len
= GET_RTX_LENGTH (code
);
3358 fmt
= GET_RTX_FORMAT (code
);
3360 /* We don't need to process a SET_DEST that is a register, CC0,
3361 or PC, so set up to skip this common case. All other cases
3362 where we want to suppress replacing something inside a
3363 SET_SRC are handled via the IN_DEST operand. */
3365 && (GET_CODE (SET_DEST (x
)) == REG
3366 || GET_CODE (SET_DEST (x
)) == CC0
3367 || GET_CODE (SET_DEST (x
)) == PC
))
3370 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3373 op0_mode
= GET_MODE (XEXP (x
, 0));
3375 for (i
= 0; i
< len
; i
++)
3380 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3382 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3384 new = (unique_copy
&& n_occurrences
3385 ? copy_rtx (to
) : to
);
3390 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3393 /* If this substitution failed, this whole thing
3395 if (GET_CODE (new) == CLOBBER
3396 && XEXP (new, 0) == const0_rtx
)
3400 SUBST (XVECEXP (x
, i
, j
), new);
3403 else if (fmt
[i
] == 'e')
3405 /* If this is a register being set, ignore it. */
3408 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3409 || code
== ZERO_EXTRACT
)
3411 && GET_CODE (new) == REG
)
3414 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3416 /* In general, don't install a subreg involving two
3417 modes not tieable. It can worsen register
3418 allocation, and can even make invalid reload
3419 insns, since the reg inside may need to be copied
3420 from in the outside mode, and that may be invalid
3421 if it is an fp reg copied in integer mode.
3423 We allow two exceptions to this: It is valid if
3424 it is inside another SUBREG and the mode of that
3425 SUBREG and the mode of the inside of TO is
3426 tieable and it is valid if X is a SET that copies
3429 if (GET_CODE (to
) == SUBREG
3430 && ! MODES_TIEABLE_P (GET_MODE (to
),
3431 GET_MODE (SUBREG_REG (to
)))
3432 && ! (code
== SUBREG
3433 && MODES_TIEABLE_P (GET_MODE (x
),
3434 GET_MODE (SUBREG_REG (to
))))
3436 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3439 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3441 #ifdef CANNOT_CHANGE_MODE_CLASS
3443 && GET_CODE (to
) == REG
3444 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3445 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3448 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3451 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3455 /* If we are in a SET_DEST, suppress most cases unless we
3456 have gone inside a MEM, in which case we want to
3457 simplify the address. We assume here that things that
3458 are actually part of the destination have their inner
3459 parts in the first expression. This is true for SUBREG,
3460 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3461 things aside from REG and MEM that should appear in a
3463 new = subst (XEXP (x
, i
), from
, to
,
3465 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3466 || code
== ZERO_EXTRACT
))
3468 && i
== 0), unique_copy
);
3470 /* If we found that we will have to reject this combination,
3471 indicate that by returning the CLOBBER ourselves, rather than
3472 an expression containing it. This will speed things up as
3473 well as prevent accidents where two CLOBBERs are considered
3474 to be equal, thus producing an incorrect simplification. */
3476 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3479 if (GET_CODE (x
) == SUBREG
3480 && (GET_CODE (new) == CONST_INT
3481 || GET_CODE (new) == CONST_DOUBLE
))
3483 enum machine_mode mode
= GET_MODE (x
);
3485 x
= simplify_subreg (GET_MODE (x
), new,
3486 GET_MODE (SUBREG_REG (x
)),
3489 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3491 else if (GET_CODE (new) == CONST_INT
3492 && GET_CODE (x
) == ZERO_EXTEND
)
3494 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3495 new, GET_MODE (XEXP (x
, 0)));
3500 SUBST (XEXP (x
, i
), new);
3505 /* Try to simplify X. If the simplification changed the code, it is likely
3506 that further simplification will help, so loop, but limit the number
3507 of repetitions that will be performed. */
3509 for (i
= 0; i
< 4; i
++)
3511 /* If X is sufficiently simple, don't bother trying to do anything
3513 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3514 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3516 if (GET_CODE (x
) == code
)
3519 code
= GET_CODE (x
);
3521 /* We no longer know the original mode of operand 0 since we
3522 have changed the form of X) */
3523 op0_mode
= VOIDmode
;
3529 /* Simplify X, a piece of RTL. We just operate on the expression at the
3530 outer level; call `subst' to simplify recursively. Return the new
3533 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3534 will be the iteration even if an expression with a code different from
3535 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3538 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3541 enum rtx_code code
= GET_CODE (x
);
3542 enum machine_mode mode
= GET_MODE (x
);
3547 /* If this is a commutative operation, put a constant last and a complex
3548 expression first. We don't need to do this for comparisons here. */
3549 if (GET_RTX_CLASS (code
) == 'c'
3550 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3553 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3554 SUBST (XEXP (x
, 1), temp
);
3557 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3558 sign extension of a PLUS with a constant, reverse the order of the sign
3559 extension and the addition. Note that this not the same as the original
3560 code, but overflow is undefined for signed values. Also note that the
3561 PLUS will have been partially moved "inside" the sign-extension, so that
3562 the first operand of X will really look like:
3563 (ashiftrt (plus (ashift A C4) C5) C4).
3565 (plus (ashiftrt (ashift A C4) C2) C4)
3566 and replace the first operand of X with that expression. Later parts
3567 of this function may simplify the expression further.
3569 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3570 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3571 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3573 We do this to simplify address expressions. */
3575 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3576 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3577 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3578 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3579 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3580 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3581 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3582 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3583 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3584 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3585 XEXP (XEXP (x
, 0), 1))) != 0)
3588 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3589 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3590 INTVAL (XEXP (XEXP (x
, 0), 1)));
3592 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3593 INTVAL (XEXP (XEXP (x
, 0), 1)));
3595 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3598 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3599 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3600 things. Check for cases where both arms are testing the same
3603 Don't do anything if all operands are very simple. */
3605 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3606 || GET_RTX_CLASS (code
) == '<')
3607 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3608 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3609 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3611 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3612 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3613 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3615 || (GET_RTX_CLASS (code
) == '1'
3616 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3617 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3618 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3621 rtx cond
, true_rtx
, false_rtx
;
3623 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3625 /* If everything is a comparison, what we have is highly unlikely
3626 to be simpler, so don't use it. */
3627 && ! (GET_RTX_CLASS (code
) == '<'
3628 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3629 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3631 rtx cop1
= const0_rtx
;
3632 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3634 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3637 /* Simplify the alternative arms; this may collapse the true and
3638 false arms to store-flag values. */
3639 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3640 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3642 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3643 is unlikely to be simpler. */
3644 if (general_operand (true_rtx
, VOIDmode
)
3645 && general_operand (false_rtx
, VOIDmode
))
3647 enum rtx_code reversed
;
3649 /* Restarting if we generate a store-flag expression will cause
3650 us to loop. Just drop through in this case. */
3652 /* If the result values are STORE_FLAG_VALUE and zero, we can
3653 just make the comparison operation. */
3654 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3655 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3656 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3657 && ((reversed
= reversed_comparison_code_parts
3658 (cond_code
, cond
, cop1
, NULL
))
3660 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3662 /* Likewise, we can make the negate of a comparison operation
3663 if the result values are - STORE_FLAG_VALUE and zero. */
3664 else if (GET_CODE (true_rtx
) == CONST_INT
3665 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3666 && false_rtx
== const0_rtx
)
3667 x
= simplify_gen_unary (NEG
, mode
,
3668 gen_binary (cond_code
, mode
, cond
,
3671 else if (GET_CODE (false_rtx
) == CONST_INT
3672 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3673 && true_rtx
== const0_rtx
3674 && ((reversed
= reversed_comparison_code_parts
3675 (cond_code
, cond
, cop1
, NULL
))
3677 x
= simplify_gen_unary (NEG
, mode
,
3678 gen_binary (reversed
, mode
,
3682 return gen_rtx_IF_THEN_ELSE (mode
,
3683 gen_binary (cond_code
, VOIDmode
,
3685 true_rtx
, false_rtx
);
3687 code
= GET_CODE (x
);
3688 op0_mode
= VOIDmode
;
3693 /* Try to fold this expression in case we have constants that weren't
3696 switch (GET_RTX_CLASS (code
))
3699 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3703 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3704 if (cmp_mode
== VOIDmode
)
3706 cmp_mode
= GET_MODE (XEXP (x
, 1));
3707 if (cmp_mode
== VOIDmode
)
3708 cmp_mode
= op0_mode
;
3710 temp
= simplify_relational_operation (code
, cmp_mode
,
3711 XEXP (x
, 0), XEXP (x
, 1));
3713 #ifdef FLOAT_STORE_FLAG_VALUE
3714 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3716 if (temp
== const0_rtx
)
3717 temp
= CONST0_RTX (mode
);
3719 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3726 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3730 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3731 XEXP (x
, 1), XEXP (x
, 2));
3738 code
= GET_CODE (temp
);
3739 op0_mode
= VOIDmode
;
3740 mode
= GET_MODE (temp
);
3743 /* First see if we can apply the inverse distributive law. */
3744 if (code
== PLUS
|| code
== MINUS
3745 || code
== AND
|| code
== IOR
|| code
== XOR
)
3747 x
= apply_distributive_law (x
);
3748 code
= GET_CODE (x
);
3749 op0_mode
= VOIDmode
;
3752 /* If CODE is an associative operation not otherwise handled, see if we
3753 can associate some operands. This can win if they are constants or
3754 if they are logically related (i.e. (a & b) & a). */
3755 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3756 || code
== AND
|| code
== IOR
|| code
== XOR
3757 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3758 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3759 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3761 if (GET_CODE (XEXP (x
, 0)) == code
)
3763 rtx other
= XEXP (XEXP (x
, 0), 0);
3764 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3765 rtx inner_op1
= XEXP (x
, 1);
3768 /* Make sure we pass the constant operand if any as the second
3769 one if this is a commutative operation. */
3770 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3772 rtx tem
= inner_op0
;
3773 inner_op0
= inner_op1
;
3776 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3777 : code
== DIV
? MULT
3779 mode
, inner_op0
, inner_op1
);
3781 /* For commutative operations, try the other pair if that one
3783 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3785 other
= XEXP (XEXP (x
, 0), 1);
3786 inner
= simplify_binary_operation (code
, mode
,
3787 XEXP (XEXP (x
, 0), 0),
3792 return gen_binary (code
, mode
, other
, inner
);
3796 /* A little bit of algebraic simplification here. */
3800 /* Ensure that our address has any ASHIFTs converted to MULT in case
3801 address-recognizing predicates are called later. */
3802 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3803 SUBST (XEXP (x
, 0), temp
);
3807 if (op0_mode
== VOIDmode
)
3808 op0_mode
= GET_MODE (SUBREG_REG (x
));
3810 /* simplify_subreg can't use gen_lowpart_for_combine. */
3811 if (CONSTANT_P (SUBREG_REG (x
))
3812 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3813 /* Don't call gen_lowpart_for_combine if the inner mode
3814 is VOIDmode and we cannot simplify it, as SUBREG without
3815 inner mode is invalid. */
3816 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3817 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3818 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3820 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3824 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3830 /* Don't change the mode of the MEM if that would change the meaning
3832 if (GET_CODE (SUBREG_REG (x
)) == MEM
3833 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3834 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3835 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3837 /* Note that we cannot do any narrowing for non-constants since
3838 we might have been counting on using the fact that some bits were
3839 zero. We now do this in the SET. */
3844 /* (not (plus X -1)) can become (neg X). */
3845 if (GET_CODE (XEXP (x
, 0)) == PLUS
3846 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3847 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3849 /* Similarly, (not (neg X)) is (plus X -1). */
3850 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3851 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3853 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3854 if (GET_CODE (XEXP (x
, 0)) == XOR
3855 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3856 && (temp
= simplify_unary_operation (NOT
, mode
,
3857 XEXP (XEXP (x
, 0), 1),
3859 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3861 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3862 other than 1, but that is not valid. We could do a similar
3863 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3864 but this doesn't seem common enough to bother with. */
3865 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3866 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3867 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3869 XEXP (XEXP (x
, 0), 1));
3871 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3872 && subreg_lowpart_p (XEXP (x
, 0))
3873 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3874 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3875 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3876 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3878 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3880 x
= gen_rtx_ROTATE (inner_mode
,
3881 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3883 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3884 return gen_lowpart_for_combine (mode
, x
);
3887 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3888 reversing the comparison code if valid. */
3889 if (STORE_FLAG_VALUE
== -1
3890 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3891 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3892 XEXP (XEXP (x
, 0), 1))))
3895 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3896 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3897 perform the above simplification. */
3899 if (STORE_FLAG_VALUE
== -1
3900 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3901 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3902 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3903 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3905 /* Apply De Morgan's laws to reduce number of patterns for machines
3906 with negating logical insns (and-not, nand, etc.). If result has
3907 only one NOT, put it first, since that is how the patterns are
3910 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3912 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3913 enum machine_mode op_mode
;
3915 op_mode
= GET_MODE (in1
);
3916 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3918 op_mode
= GET_MODE (in2
);
3919 if (op_mode
== VOIDmode
)
3921 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3923 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3926 in2
= in1
; in1
= tem
;
3929 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3935 /* (neg (plus X 1)) can become (not X). */
3936 if (GET_CODE (XEXP (x
, 0)) == PLUS
3937 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3938 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3940 /* Similarly, (neg (not X)) is (plus X 1). */
3941 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3942 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3944 /* (neg (minus X Y)) can become (minus Y X). This transformation
3945 isn't safe for modes with signed zeros, since if X and Y are
3946 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3947 mode is towards +infinity (or -infinity) then the two expressions
3948 will be rounded differently. */
3949 if (GET_CODE (XEXP (x
, 0)) == MINUS
3950 && !HONOR_SIGNED_ZEROS (mode
)
3951 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
3952 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3953 XEXP (XEXP (x
, 0), 0));
3955 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
3956 if (GET_CODE (XEXP (x
, 0)) == PLUS
3957 && !HONOR_SIGNED_ZEROS (mode
)
3958 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
3960 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
3961 temp
= combine_simplify_rtx (temp
, mode
, last
, in_dest
);
3962 return gen_binary (MINUS
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3965 /* (neg (mult A B)) becomes (mult (neg A) B).
3966 This works even for floating-point values. */
3967 if (GET_CODE (XEXP (x
, 0)) == MULT
)
3969 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
3970 return gen_binary (MULT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3973 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3974 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3975 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3976 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3978 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3979 if we can then eliminate the NEG (e.g.,
3980 if the operand is a constant). */
3982 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3984 temp
= simplify_unary_operation (NEG
, mode
,
3985 XEXP (XEXP (x
, 0), 0), mode
);
3987 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3990 temp
= expand_compound_operation (XEXP (x
, 0));
3992 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3993 replaced by (lshiftrt X C). This will convert
3994 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3996 if (GET_CODE (temp
) == ASHIFTRT
3997 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3998 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3999 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4000 INTVAL (XEXP (temp
, 1)));
4002 /* If X has only a single bit that might be nonzero, say, bit I, convert
4003 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4004 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4005 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4006 or a SUBREG of one since we'd be making the expression more
4007 complex if it was just a register. */
4009 if (GET_CODE (temp
) != REG
4010 && ! (GET_CODE (temp
) == SUBREG
4011 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4012 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4014 rtx temp1
= simplify_shift_const
4015 (NULL_RTX
, ASHIFTRT
, mode
,
4016 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4017 GET_MODE_BITSIZE (mode
) - 1 - i
),
4018 GET_MODE_BITSIZE (mode
) - 1 - i
);
4020 /* If all we did was surround TEMP with the two shifts, we
4021 haven't improved anything, so don't use it. Otherwise,
4022 we are better off with TEMP1. */
4023 if (GET_CODE (temp1
) != ASHIFTRT
4024 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4025 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4031 /* We can't handle truncation to a partial integer mode here
4032 because we don't know the real bitsize of the partial
4034 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4037 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4038 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4039 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4041 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4042 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4044 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4045 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4046 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4047 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4048 return XEXP (XEXP (x
, 0), 0);
4050 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4051 (OP:SI foo:SI) if OP is NEG or ABS. */
4052 if ((GET_CODE (XEXP (x
, 0)) == ABS
4053 || GET_CODE (XEXP (x
, 0)) == NEG
)
4054 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4055 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4056 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4057 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4058 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4060 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4062 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4063 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4064 && subreg_lowpart_p (XEXP (x
, 0)))
4065 return SUBREG_REG (XEXP (x
, 0));
4067 /* If we know that the value is already truncated, we can
4068 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4069 is nonzero for the corresponding modes. But don't do this
4070 for an (LSHIFTRT (MULT ...)) since this will cause problems
4071 with the umulXi3_highpart patterns. */
4072 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4073 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4074 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4075 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4076 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4077 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4078 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4080 /* A truncate of a comparison can be replaced with a subreg if
4081 STORE_FLAG_VALUE permits. This is like the previous test,
4082 but it works even if the comparison is done in a mode larger
4083 than HOST_BITS_PER_WIDE_INT. */
4084 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4085 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4086 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4087 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4089 /* Similarly, a truncate of a register whose value is a
4090 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4092 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4093 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4094 && (temp
= get_last_value (XEXP (x
, 0)))
4095 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4096 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4100 case FLOAT_TRUNCATE
:
4101 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4102 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4103 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4104 return XEXP (XEXP (x
, 0), 0);
4106 /* (float_truncate:SF (float_truncate:DF foo:XF))
4107 = (float_truncate:SF foo:XF).
4108 This may eliminate double rounding, so it is unsafe.
4110 (float_truncate:SF (float_extend:XF foo:DF))
4111 = (float_truncate:SF foo:DF).
4113 (float_truncate:DF (float_extend:XF foo:SF))
4114 = (float_extend:SF foo:DF). */
4115 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4116 && flag_unsafe_math_optimizations
)
4117 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4118 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4120 > GET_MODE_SIZE (mode
)
4121 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4123 XEXP (XEXP (x
, 0), 0), mode
);
4125 /* (float_truncate (float x)) is (float x) */
4126 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4127 && (flag_unsafe_math_optimizations
4128 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4129 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4130 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4131 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4132 return simplify_gen_unary (FLOAT
, mode
,
4133 XEXP (XEXP (x
, 0), 0),
4134 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4136 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4137 (OP:SF foo:SF) if OP is NEG or ABS. */
4138 if ((GET_CODE (XEXP (x
, 0)) == ABS
4139 || GET_CODE (XEXP (x
, 0)) == NEG
)
4140 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4141 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4142 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4143 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4145 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4146 is (float_truncate:SF x). */
4147 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4148 && subreg_lowpart_p (XEXP (x
, 0))
4149 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4150 return SUBREG_REG (XEXP (x
, 0));
4153 /* (float_extend (float_extend x)) is (float_extend x)
4155 (float_extend (float x)) is (float x) assuming that double
4156 rounding can't happen.
4158 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4159 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4160 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4161 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4162 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4163 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4164 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4165 XEXP (XEXP (x
, 0), 0),
4166 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4171 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4172 using cc0, in which case we want to leave it as a COMPARE
4173 so we can distinguish it from a register-register-copy. */
4174 if (XEXP (x
, 1) == const0_rtx
)
4177 /* x - 0 is the same as x unless x's mode has signed zeros and
4178 allows rounding towards -infinity. Under those conditions,
4180 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4181 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4182 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4188 /* (const (const X)) can become (const X). Do it this way rather than
4189 returning the inner CONST since CONST can be shared with a
4191 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4192 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4197 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4198 can add in an offset. find_split_point will split this address up
4199 again if it doesn't match. */
4200 if (GET_CODE (XEXP (x
, 0)) == HIGH
4201 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4207 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4209 if (GET_CODE (XEXP (x
, 0)) == MULT
4210 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4214 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4215 in2
= XEXP (XEXP (x
, 0), 1);
4216 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4217 gen_binary (MULT
, mode
, in1
, in2
));
4220 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4221 outermost. That's because that's the way indexed addresses are
4222 supposed to appear. This code used to check many more cases, but
4223 they are now checked elsewhere. */
4224 if (GET_CODE (XEXP (x
, 0)) == PLUS
4225 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4226 return gen_binary (PLUS
, mode
,
4227 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4229 XEXP (XEXP (x
, 0), 1));
4231 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4232 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4233 bit-field and can be replaced by either a sign_extend or a
4234 sign_extract. The `and' may be a zero_extend and the two
4235 <c>, -<c> constants may be reversed. */
4236 if (GET_CODE (XEXP (x
, 0)) == XOR
4237 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4238 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4239 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4240 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4241 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4242 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4243 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4244 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4245 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4246 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4247 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4248 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4249 == (unsigned int) i
+ 1))))
4250 return simplify_shift_const
4251 (NULL_RTX
, ASHIFTRT
, mode
,
4252 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4253 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4254 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4255 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4257 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4258 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4259 is 1. This produces better code than the alternative immediately
4261 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4262 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4263 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4264 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4265 XEXP (XEXP (x
, 0), 0),
4266 XEXP (XEXP (x
, 0), 1))))
4268 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4270 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4271 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4272 the bitsize of the mode - 1. This allows simplification of
4273 "a = (b & 8) == 0;" */
4274 if (XEXP (x
, 1) == constm1_rtx
4275 && GET_CODE (XEXP (x
, 0)) != REG
4276 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4277 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4278 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4279 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4280 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4281 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4282 GET_MODE_BITSIZE (mode
) - 1),
4283 GET_MODE_BITSIZE (mode
) - 1);
4285 /* If we are adding two things that have no bits in common, convert
4286 the addition into an IOR. This will often be further simplified,
4287 for example in cases like ((a & 1) + (a & 2)), which can
4290 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4291 && (nonzero_bits (XEXP (x
, 0), mode
)
4292 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4294 /* Try to simplify the expression further. */
4295 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4296 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4298 /* If we could, great. If not, do not go ahead with the IOR
4299 replacement, since PLUS appears in many special purpose
4300 address arithmetic instructions. */
4301 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4307 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4308 by reversing the comparison code if valid. */
4309 if (STORE_FLAG_VALUE
== 1
4310 && XEXP (x
, 0) == const1_rtx
4311 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4312 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4313 XEXP (XEXP (x
, 1), 0),
4314 XEXP (XEXP (x
, 1), 1))))
4317 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4318 (and <foo> (const_int pow2-1)) */
4319 if (GET_CODE (XEXP (x
, 1)) == AND
4320 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4321 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4322 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4323 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4324 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4326 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4328 if (GET_CODE (XEXP (x
, 1)) == MULT
4329 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4333 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4334 in2
= XEXP (XEXP (x
, 1), 1);
4335 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4339 /* Canonicalize (minus (neg A) (mult B C)) to
4340 (minus (mult (neg B) C) A). */
4341 if (GET_CODE (XEXP (x
, 1)) == MULT
4342 && GET_CODE (XEXP (x
, 0)) == NEG
)
4346 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4347 in2
= XEXP (XEXP (x
, 1), 1);
4348 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4349 XEXP (XEXP (x
, 0), 0));
4352 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4354 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4355 return gen_binary (MINUS
, mode
,
4356 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4357 XEXP (XEXP (x
, 1), 0)),
4358 XEXP (XEXP (x
, 1), 1));
4362 /* If we have (mult (plus A B) C), apply the distributive law and then
4363 the inverse distributive law to see if things simplify. This
4364 occurs mostly in addresses, often when unrolling loops. */
4366 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4368 x
= apply_distributive_law
4369 (gen_binary (PLUS
, mode
,
4370 gen_binary (MULT
, mode
,
4371 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4372 gen_binary (MULT
, mode
,
4373 XEXP (XEXP (x
, 0), 1),
4374 copy_rtx (XEXP (x
, 1)))));
4376 if (GET_CODE (x
) != MULT
)
4379 /* Try simplify a*(b/c) as (a*b)/c. */
4380 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4381 && GET_CODE (XEXP (x
, 0)) == DIV
)
4383 rtx tem
= simplify_binary_operation (MULT
, mode
,
4384 XEXP (XEXP (x
, 0), 0),
4387 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4392 /* If this is a divide by a power of two, treat it as a shift if
4393 its first operand is a shift. */
4394 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4395 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4396 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4397 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4398 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4399 || GET_CODE (XEXP (x
, 0)) == ROTATE
4400 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4401 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4405 case GT
: case GTU
: case GE
: case GEU
:
4406 case LT
: case LTU
: case LE
: case LEU
:
4407 case UNEQ
: case LTGT
:
4408 case UNGT
: case UNGE
:
4409 case UNLT
: case UNLE
:
4410 case UNORDERED
: case ORDERED
:
4411 /* If the first operand is a condition code, we can't do anything
4413 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4414 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4415 && ! CC0_P (XEXP (x
, 0))))
4417 rtx op0
= XEXP (x
, 0);
4418 rtx op1
= XEXP (x
, 1);
4419 enum rtx_code new_code
;
4421 if (GET_CODE (op0
) == COMPARE
)
4422 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4424 /* Simplify our comparison, if possible. */
4425 new_code
= simplify_comparison (code
, &op0
, &op1
);
4427 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4428 if only the low-order bit is possibly nonzero in X (such as when
4429 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4430 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4431 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4434 Remove any ZERO_EXTRACT we made when thinking this was a
4435 comparison. It may now be simpler to use, e.g., an AND. If a
4436 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4437 the call to make_compound_operation in the SET case. */
4439 if (STORE_FLAG_VALUE
== 1
4440 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4441 && op1
== const0_rtx
4442 && mode
== GET_MODE (op0
)
4443 && nonzero_bits (op0
, mode
) == 1)
4444 return gen_lowpart_for_combine (mode
,
4445 expand_compound_operation (op0
));
4447 else if (STORE_FLAG_VALUE
== 1
4448 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4449 && op1
== const0_rtx
4450 && mode
== GET_MODE (op0
)
4451 && (num_sign_bit_copies (op0
, mode
)
4452 == GET_MODE_BITSIZE (mode
)))
4454 op0
= expand_compound_operation (op0
);
4455 return simplify_gen_unary (NEG
, mode
,
4456 gen_lowpart_for_combine (mode
, op0
),
4460 else if (STORE_FLAG_VALUE
== 1
4461 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4462 && op1
== const0_rtx
4463 && mode
== GET_MODE (op0
)
4464 && nonzero_bits (op0
, mode
) == 1)
4466 op0
= expand_compound_operation (op0
);
4467 return gen_binary (XOR
, mode
,
4468 gen_lowpart_for_combine (mode
, op0
),
4472 else if (STORE_FLAG_VALUE
== 1
4473 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4474 && op1
== const0_rtx
4475 && mode
== GET_MODE (op0
)
4476 && (num_sign_bit_copies (op0
, mode
)
4477 == GET_MODE_BITSIZE (mode
)))
4479 op0
= expand_compound_operation (op0
);
4480 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4483 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4485 if (STORE_FLAG_VALUE
== -1
4486 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4487 && op1
== const0_rtx
4488 && (num_sign_bit_copies (op0
, mode
)
4489 == GET_MODE_BITSIZE (mode
)))
4490 return gen_lowpart_for_combine (mode
,
4491 expand_compound_operation (op0
));
4493 else if (STORE_FLAG_VALUE
== -1
4494 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4495 && op1
== const0_rtx
4496 && mode
== GET_MODE (op0
)
4497 && nonzero_bits (op0
, mode
) == 1)
4499 op0
= expand_compound_operation (op0
);
4500 return simplify_gen_unary (NEG
, mode
,
4501 gen_lowpart_for_combine (mode
, op0
),
4505 else if (STORE_FLAG_VALUE
== -1
4506 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4507 && op1
== const0_rtx
4508 && mode
== GET_MODE (op0
)
4509 && (num_sign_bit_copies (op0
, mode
)
4510 == GET_MODE_BITSIZE (mode
)))
4512 op0
= expand_compound_operation (op0
);
4513 return simplify_gen_unary (NOT
, mode
,
4514 gen_lowpart_for_combine (mode
, op0
),
4518 /* If X is 0/1, (eq X 0) is X-1. */
4519 else if (STORE_FLAG_VALUE
== -1
4520 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4521 && op1
== const0_rtx
4522 && mode
== GET_MODE (op0
)
4523 && nonzero_bits (op0
, mode
) == 1)
4525 op0
= expand_compound_operation (op0
);
4526 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4529 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4530 one bit that might be nonzero, we can convert (ne x 0) to
4531 (ashift x c) where C puts the bit in the sign bit. Remove any
4532 AND with STORE_FLAG_VALUE when we are done, since we are only
4533 going to test the sign bit. */
4534 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4535 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4536 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4537 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4538 && op1
== const0_rtx
4539 && mode
== GET_MODE (op0
)
4540 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4542 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4543 expand_compound_operation (op0
),
4544 GET_MODE_BITSIZE (mode
) - 1 - i
);
4545 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4551 /* If the code changed, return a whole new comparison. */
4552 if (new_code
!= code
)
4553 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4555 /* Otherwise, keep this operation, but maybe change its operands.
4556 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4557 SUBST (XEXP (x
, 0), op0
);
4558 SUBST (XEXP (x
, 1), op1
);
4563 return simplify_if_then_else (x
);
4569 /* If we are processing SET_DEST, we are done. */
4573 return expand_compound_operation (x
);
4576 return simplify_set (x
);
4581 return simplify_logical (x
, last
);
4584 /* (abs (neg <foo>)) -> (abs <foo>) */
4585 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4586 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4588 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4590 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4593 /* If operand is something known to be positive, ignore the ABS. */
4594 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4595 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4596 <= HOST_BITS_PER_WIDE_INT
)
4597 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4598 & ((HOST_WIDE_INT
) 1
4599 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4603 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4604 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4605 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4610 /* (ffs (*_extend <X>)) = (ffs <X>) */
4611 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4612 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4613 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4618 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4619 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4620 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4624 /* (float (sign_extend <X>)) = (float <X>). */
4625 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4626 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4634 /* If this is a shift by a constant amount, simplify it. */
4635 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4636 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4637 INTVAL (XEXP (x
, 1)));
4639 #ifdef SHIFT_COUNT_TRUNCATED
4640 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4642 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4644 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4653 rtx op0
= XEXP (x
, 0);
4654 rtx op1
= XEXP (x
, 1);
4657 if (GET_CODE (op1
) != PARALLEL
)
4659 len
= XVECLEN (op1
, 0);
4661 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4662 && GET_CODE (op0
) == VEC_CONCAT
)
4664 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4666 /* Try to find the element in the VEC_CONCAT. */
4669 if (GET_MODE (op0
) == GET_MODE (x
))
4671 if (GET_CODE (op0
) == VEC_CONCAT
)
4673 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4674 if (op0_size
< offset
)
4675 op0
= XEXP (op0
, 0);
4679 op0
= XEXP (op0
, 1);
4697 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4700 simplify_if_then_else (rtx x
)
4702 enum machine_mode mode
= GET_MODE (x
);
4703 rtx cond
= XEXP (x
, 0);
4704 rtx true_rtx
= XEXP (x
, 1);
4705 rtx false_rtx
= XEXP (x
, 2);
4706 enum rtx_code true_code
= GET_CODE (cond
);
4707 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4710 enum rtx_code false_code
;
4713 /* Simplify storing of the truth value. */
4714 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4715 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4717 /* Also when the truth value has to be reversed. */
4719 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4720 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4724 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4725 in it is being compared against certain values. Get the true and false
4726 comparisons and see if that says anything about the value of each arm. */
4729 && ((false_code
= combine_reversed_comparison_code (cond
))
4731 && GET_CODE (XEXP (cond
, 0)) == REG
)
4734 rtx from
= XEXP (cond
, 0);
4735 rtx true_val
= XEXP (cond
, 1);
4736 rtx false_val
= true_val
;
4739 /* If FALSE_CODE is EQ, swap the codes and arms. */
4741 if (false_code
== EQ
)
4743 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4744 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4747 /* If we are comparing against zero and the expression being tested has
4748 only a single bit that might be nonzero, that is its value when it is
4749 not equal to zero. Similarly if it is known to be -1 or 0. */
4751 if (true_code
== EQ
&& true_val
== const0_rtx
4752 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4753 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4754 else if (true_code
== EQ
&& true_val
== const0_rtx
4755 && (num_sign_bit_copies (from
, GET_MODE (from
))
4756 == GET_MODE_BITSIZE (GET_MODE (from
))))
4757 false_code
= EQ
, false_val
= constm1_rtx
;
4759 /* Now simplify an arm if we know the value of the register in the
4760 branch and it is used in the arm. Be careful due to the potential
4761 of locally-shared RTL. */
4763 if (reg_mentioned_p (from
, true_rtx
))
4764 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4766 pc_rtx
, pc_rtx
, 0, 0);
4767 if (reg_mentioned_p (from
, false_rtx
))
4768 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4770 pc_rtx
, pc_rtx
, 0, 0);
4772 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4773 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4775 true_rtx
= XEXP (x
, 1);
4776 false_rtx
= XEXP (x
, 2);
4777 true_code
= GET_CODE (cond
);
4780 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4781 reversed, do so to avoid needing two sets of patterns for
4782 subtract-and-branch insns. Similarly if we have a constant in the true
4783 arm, the false arm is the same as the first operand of the comparison, or
4784 the false arm is more complicated than the true arm. */
4787 && combine_reversed_comparison_code (cond
) != UNKNOWN
4788 && (true_rtx
== pc_rtx
4789 || (CONSTANT_P (true_rtx
)
4790 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4791 || true_rtx
== const0_rtx
4792 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4793 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4794 || (GET_CODE (true_rtx
) == SUBREG
4795 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4796 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4797 || reg_mentioned_p (true_rtx
, false_rtx
)
4798 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4800 true_code
= reversed_comparison_code (cond
, NULL
);
4802 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4805 SUBST (XEXP (x
, 1), false_rtx
);
4806 SUBST (XEXP (x
, 2), true_rtx
);
4808 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4811 /* It is possible that the conditional has been simplified out. */
4812 true_code
= GET_CODE (cond
);
4813 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4816 /* If the two arms are identical, we don't need the comparison. */
4818 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4821 /* Convert a == b ? b : a to "a". */
4822 if (true_code
== EQ
&& ! side_effects_p (cond
)
4823 && !HONOR_NANS (mode
)
4824 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4825 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4827 else if (true_code
== NE
&& ! side_effects_p (cond
)
4828 && !HONOR_NANS (mode
)
4829 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4830 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4833 /* Look for cases where we have (abs x) or (neg (abs X)). */
4835 if (GET_MODE_CLASS (mode
) == MODE_INT
4836 && GET_CODE (false_rtx
) == NEG
4837 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4839 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4840 && ! side_effects_p (true_rtx
))
4845 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4849 simplify_gen_unary (NEG
, mode
,
4850 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4856 /* Look for MIN or MAX. */
4858 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4860 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4861 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4862 && ! side_effects_p (cond
))
4867 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4870 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4873 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4876 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4881 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4882 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4883 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4884 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4885 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4886 neither 1 or -1, but it isn't worth checking for. */
4888 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4890 && GET_MODE_CLASS (mode
) == MODE_INT
4891 && ! side_effects_p (x
))
4893 rtx t
= make_compound_operation (true_rtx
, SET
);
4894 rtx f
= make_compound_operation (false_rtx
, SET
);
4895 rtx cond_op0
= XEXP (cond
, 0);
4896 rtx cond_op1
= XEXP (cond
, 1);
4897 enum rtx_code op
= NIL
, extend_op
= NIL
;
4898 enum machine_mode m
= mode
;
4899 rtx z
= 0, c1
= NULL_RTX
;
4901 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4902 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4903 || GET_CODE (t
) == ASHIFT
4904 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4905 && rtx_equal_p (XEXP (t
, 0), f
))
4906 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4908 /* If an identity-zero op is commutative, check whether there
4909 would be a match if we swapped the operands. */
4910 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4911 || GET_CODE (t
) == XOR
)
4912 && rtx_equal_p (XEXP (t
, 1), f
))
4913 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4914 else if (GET_CODE (t
) == SIGN_EXTEND
4915 && (GET_CODE (XEXP (t
, 0)) == PLUS
4916 || GET_CODE (XEXP (t
, 0)) == MINUS
4917 || GET_CODE (XEXP (t
, 0)) == IOR
4918 || GET_CODE (XEXP (t
, 0)) == XOR
4919 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4920 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4921 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4922 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4923 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4924 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4925 && (num_sign_bit_copies (f
, GET_MODE (f
))
4927 (GET_MODE_BITSIZE (mode
)
4928 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4930 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4931 extend_op
= SIGN_EXTEND
;
4932 m
= GET_MODE (XEXP (t
, 0));
4934 else if (GET_CODE (t
) == SIGN_EXTEND
4935 && (GET_CODE (XEXP (t
, 0)) == PLUS
4936 || GET_CODE (XEXP (t
, 0)) == IOR
4937 || GET_CODE (XEXP (t
, 0)) == XOR
)
4938 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4939 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4940 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4941 && (num_sign_bit_copies (f
, GET_MODE (f
))
4943 (GET_MODE_BITSIZE (mode
)
4944 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4946 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4947 extend_op
= SIGN_EXTEND
;
4948 m
= GET_MODE (XEXP (t
, 0));
4950 else if (GET_CODE (t
) == ZERO_EXTEND
4951 && (GET_CODE (XEXP (t
, 0)) == PLUS
4952 || GET_CODE (XEXP (t
, 0)) == MINUS
4953 || GET_CODE (XEXP (t
, 0)) == IOR
4954 || GET_CODE (XEXP (t
, 0)) == XOR
4955 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4956 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4957 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4958 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4959 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4960 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4961 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4962 && ((nonzero_bits (f
, GET_MODE (f
))
4963 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4966 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4967 extend_op
= ZERO_EXTEND
;
4968 m
= GET_MODE (XEXP (t
, 0));
4970 else if (GET_CODE (t
) == ZERO_EXTEND
4971 && (GET_CODE (XEXP (t
, 0)) == PLUS
4972 || GET_CODE (XEXP (t
, 0)) == IOR
4973 || GET_CODE (XEXP (t
, 0)) == XOR
)
4974 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4975 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4976 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4977 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4978 && ((nonzero_bits (f
, GET_MODE (f
))
4979 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4982 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4983 extend_op
= ZERO_EXTEND
;
4984 m
= GET_MODE (XEXP (t
, 0));
4989 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4990 pc_rtx
, pc_rtx
, 0, 0);
4991 temp
= gen_binary (MULT
, m
, temp
,
4992 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4993 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4994 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4996 if (extend_op
!= NIL
)
4997 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5003 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5004 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5005 negation of a single bit, we can convert this operation to a shift. We
5006 can actually do this more generally, but it doesn't seem worth it. */
5008 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5009 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5010 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5011 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5012 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5013 == GET_MODE_BITSIZE (mode
))
5014 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5016 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5017 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
5019 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5020 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5021 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5022 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5023 == nonzero_bits (XEXP (cond
, 0), mode
)
5024 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5025 return XEXP (cond
, 0);
5030 /* Simplify X, a SET expression. Return the new expression. */
5033 simplify_set (rtx x
)
5035 rtx src
= SET_SRC (x
);
5036 rtx dest
= SET_DEST (x
);
5037 enum machine_mode mode
5038 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5042 /* (set (pc) (return)) gets written as (return). */
5043 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5046 /* Now that we know for sure which bits of SRC we are using, see if we can
5047 simplify the expression for the object knowing that we only need the
5050 if (GET_MODE_CLASS (mode
) == MODE_INT
5051 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5053 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5054 SUBST (SET_SRC (x
), src
);
5057 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5058 the comparison result and try to simplify it unless we already have used
5059 undobuf.other_insn. */
5060 if ((GET_MODE_CLASS (mode
) == MODE_CC
5061 || GET_CODE (src
) == COMPARE
5063 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5064 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5065 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5066 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5068 enum rtx_code old_code
= GET_CODE (*cc_use
);
5069 enum rtx_code new_code
;
5071 int other_changed
= 0;
5072 enum machine_mode compare_mode
= GET_MODE (dest
);
5073 enum machine_mode tmp_mode
;
5075 if (GET_CODE (src
) == COMPARE
)
5076 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5078 op0
= src
, op1
= const0_rtx
;
5080 /* Check whether the comparison is known at compile time. */
5081 if (GET_MODE (op0
) != VOIDmode
)
5082 tmp_mode
= GET_MODE (op0
);
5083 else if (GET_MODE (op1
) != VOIDmode
)
5084 tmp_mode
= GET_MODE (op1
);
5086 tmp_mode
= compare_mode
;
5087 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5088 if (tmp
!= NULL_RTX
)
5090 rtx pat
= PATTERN (other_insn
);
5091 undobuf
.other_insn
= other_insn
;
5092 SUBST (*cc_use
, tmp
);
5094 /* Attempt to simplify CC user. */
5095 if (GET_CODE (pat
) == SET
)
5097 rtx
new = simplify_rtx (SET_SRC (pat
));
5098 if (new != NULL_RTX
)
5099 SUBST (SET_SRC (pat
), new);
5102 /* Convert X into a no-op move. */
5103 SUBST (SET_DEST (x
), pc_rtx
);
5104 SUBST (SET_SRC (x
), pc_rtx
);
5108 /* Simplify our comparison, if possible. */
5109 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5111 #ifdef EXTRA_CC_MODES
5112 /* If this machine has CC modes other than CCmode, check to see if we
5113 need to use a different CC mode here. */
5114 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5115 #endif /* EXTRA_CC_MODES */
5117 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5118 /* If the mode changed, we have to change SET_DEST, the mode in the
5119 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5120 a hard register, just build new versions with the proper mode. If it
5121 is a pseudo, we lose unless it is only time we set the pseudo, in
5122 which case we can safely change its mode. */
5123 if (compare_mode
!= GET_MODE (dest
))
5125 unsigned int regno
= REGNO (dest
);
5126 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5128 if (regno
< FIRST_PSEUDO_REGISTER
5129 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5131 if (regno
>= FIRST_PSEUDO_REGISTER
)
5132 SUBST (regno_reg_rtx
[regno
], new_dest
);
5134 SUBST (SET_DEST (x
), new_dest
);
5135 SUBST (XEXP (*cc_use
, 0), new_dest
);
5143 /* If the code changed, we have to build a new comparison in
5144 undobuf.other_insn. */
5145 if (new_code
!= old_code
)
5147 unsigned HOST_WIDE_INT mask
;
5149 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5152 /* If the only change we made was to change an EQ into an NE or
5153 vice versa, OP0 has only one bit that might be nonzero, and OP1
5154 is zero, check if changing the user of the condition code will
5155 produce a valid insn. If it won't, we can keep the original code
5156 in that insn by surrounding our operation with an XOR. */
5158 if (((old_code
== NE
&& new_code
== EQ
)
5159 || (old_code
== EQ
&& new_code
== NE
))
5160 && ! other_changed
&& op1
== const0_rtx
5161 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5162 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5164 rtx pat
= PATTERN (other_insn
), note
= 0;
5166 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5167 && ! check_asm_operands (pat
)))
5169 PUT_CODE (*cc_use
, old_code
);
5172 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5180 undobuf
.other_insn
= other_insn
;
5183 /* If we are now comparing against zero, change our source if
5184 needed. If we do not use cc0, we always have a COMPARE. */
5185 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5187 SUBST (SET_SRC (x
), op0
);
5193 /* Otherwise, if we didn't previously have a COMPARE in the
5194 correct mode, we need one. */
5195 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5197 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5202 /* Otherwise, update the COMPARE if needed. */
5203 SUBST (XEXP (src
, 0), op0
);
5204 SUBST (XEXP (src
, 1), op1
);
5209 /* Get SET_SRC in a form where we have placed back any
5210 compound expressions. Then do the checks below. */
5211 src
= make_compound_operation (src
, SET
);
5212 SUBST (SET_SRC (x
), src
);
5215 #ifdef WORD_REGISTER_OPERATIONS
5216 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5217 and X being a REG or (subreg (reg)), we may be able to convert this to
5218 (set (subreg:m2 x) (op)).
5220 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5221 transformation is safe as long as M1 and M2 have the same number
5224 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5225 we cannot apply this transformation because it would create a
5226 paradoxical subreg in SET_DEST. */
5228 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5229 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5230 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5232 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5233 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5234 #ifdef CANNOT_CHANGE_MODE_CLASS
5235 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5236 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5237 GET_MODE (SUBREG_REG (src
)),
5240 && (GET_CODE (dest
) == REG
5241 || (GET_CODE (dest
) == SUBREG
5242 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5244 SUBST (SET_DEST (x
),
5245 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5247 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5249 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5254 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5257 && GET_CODE (src
) == SUBREG
5258 && subreg_lowpart_p (src
)
5259 && (GET_MODE_BITSIZE (GET_MODE (src
))
5260 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5262 rtx inner
= SUBREG_REG (src
);
5263 enum machine_mode inner_mode
= GET_MODE (inner
);
5265 /* Here we make sure that we don't have a sign bit on. */
5266 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5267 && (nonzero_bits (inner
, inner_mode
)
5268 < ((unsigned HOST_WIDE_INT
) 1
5269 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5271 SUBST (SET_SRC (x
), inner
);
5277 #ifdef LOAD_EXTEND_OP
5278 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5279 would require a paradoxical subreg. Replace the subreg with a
5280 zero_extend to avoid the reload that would otherwise be required. */
5282 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5283 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5284 && SUBREG_BYTE (src
) == 0
5285 && (GET_MODE_SIZE (GET_MODE (src
))
5286 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5287 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5290 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5291 GET_MODE (src
), SUBREG_REG (src
)));
5297 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5298 are comparing an item known to be 0 or -1 against 0, use a logical
5299 operation instead. Check for one of the arms being an IOR of the other
5300 arm with some value. We compute three terms to be IOR'ed together. In
5301 practice, at most two will be nonzero. Then we do the IOR's. */
5303 if (GET_CODE (dest
) != PC
5304 && GET_CODE (src
) == IF_THEN_ELSE
5305 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5306 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5307 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5308 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5309 #ifdef HAVE_conditional_move
5310 && ! can_conditionally_move_p (GET_MODE (src
))
5312 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5313 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5314 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5315 && ! side_effects_p (src
))
5317 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5318 ? XEXP (src
, 1) : XEXP (src
, 2));
5319 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5320 ? XEXP (src
, 2) : XEXP (src
, 1));
5321 rtx term1
= const0_rtx
, term2
, term3
;
5323 if (GET_CODE (true_rtx
) == IOR
5324 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5325 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5326 else if (GET_CODE (true_rtx
) == IOR
5327 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5328 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5329 else if (GET_CODE (false_rtx
) == IOR
5330 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5331 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5332 else if (GET_CODE (false_rtx
) == IOR
5333 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5334 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5336 term2
= gen_binary (AND
, GET_MODE (src
),
5337 XEXP (XEXP (src
, 0), 0), true_rtx
);
5338 term3
= gen_binary (AND
, GET_MODE (src
),
5339 simplify_gen_unary (NOT
, GET_MODE (src
),
5340 XEXP (XEXP (src
, 0), 0),
5345 gen_binary (IOR
, GET_MODE (src
),
5346 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5352 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5353 whole thing fail. */
5354 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5356 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5359 /* Convert this into a field assignment operation, if possible. */
5360 return make_field_assignment (x
);
5363 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5364 result. LAST is nonzero if this is the last retry. */
5367 simplify_logical (rtx x
, int last
)
5369 enum machine_mode mode
= GET_MODE (x
);
5370 rtx op0
= XEXP (x
, 0);
5371 rtx op1
= XEXP (x
, 1);
5374 switch (GET_CODE (x
))
5377 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5378 insn (and may simplify more). */
5379 if (GET_CODE (op0
) == XOR
5380 && rtx_equal_p (XEXP (op0
, 0), op1
)
5381 && ! side_effects_p (op1
))
5382 x
= gen_binary (AND
, mode
,
5383 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5386 if (GET_CODE (op0
) == XOR
5387 && rtx_equal_p (XEXP (op0
, 1), op1
)
5388 && ! side_effects_p (op1
))
5389 x
= gen_binary (AND
, mode
,
5390 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5393 /* Similarly for (~(A ^ B)) & A. */
5394 if (GET_CODE (op0
) == NOT
5395 && GET_CODE (XEXP (op0
, 0)) == XOR
5396 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5397 && ! side_effects_p (op1
))
5398 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5400 if (GET_CODE (op0
) == NOT
5401 && GET_CODE (XEXP (op0
, 0)) == XOR
5402 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5403 && ! side_effects_p (op1
))
5404 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5406 /* We can call simplify_and_const_int only if we don't lose
5407 any (sign) bits when converting INTVAL (op1) to
5408 "unsigned HOST_WIDE_INT". */
5409 if (GET_CODE (op1
) == CONST_INT
5410 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5411 || INTVAL (op1
) > 0))
5413 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5415 /* If we have (ior (and (X C1) C2)) and the next restart would be
5416 the last, simplify this by making C1 as small as possible
5419 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5420 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5421 && GET_CODE (op1
) == CONST_INT
)
5422 return gen_binary (IOR
, mode
,
5423 gen_binary (AND
, mode
, XEXP (op0
, 0),
5424 GEN_INT (INTVAL (XEXP (op0
, 1))
5425 & ~INTVAL (op1
))), op1
);
5427 if (GET_CODE (x
) != AND
)
5430 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5431 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5432 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5435 /* Convert (A | B) & A to A. */
5436 if (GET_CODE (op0
) == IOR
5437 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5438 || rtx_equal_p (XEXP (op0
, 1), op1
))
5439 && ! side_effects_p (XEXP (op0
, 0))
5440 && ! side_effects_p (XEXP (op0
, 1)))
5443 /* In the following group of tests (and those in case IOR below),
5444 we start with some combination of logical operations and apply
5445 the distributive law followed by the inverse distributive law.
5446 Most of the time, this results in no change. However, if some of
5447 the operands are the same or inverses of each other, simplifications
5450 For example, (and (ior A B) (not B)) can occur as the result of
5451 expanding a bit field assignment. When we apply the distributive
5452 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5453 which then simplifies to (and (A (not B))).
5455 If we have (and (ior A B) C), apply the distributive law and then
5456 the inverse distributive law to see if things simplify. */
5458 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5460 x
= apply_distributive_law
5461 (gen_binary (GET_CODE (op0
), mode
,
5462 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5463 gen_binary (AND
, mode
, XEXP (op0
, 1),
5465 if (GET_CODE (x
) != AND
)
5469 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5470 return apply_distributive_law
5471 (gen_binary (GET_CODE (op1
), mode
,
5472 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5473 gen_binary (AND
, mode
, XEXP (op1
, 1),
5476 /* Similarly, taking advantage of the fact that
5477 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5479 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5480 return apply_distributive_law
5481 (gen_binary (XOR
, mode
,
5482 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5483 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5486 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5487 return apply_distributive_law
5488 (gen_binary (XOR
, mode
,
5489 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5490 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5494 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5495 if (GET_CODE (op1
) == CONST_INT
5496 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5497 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5500 /* Convert (A & B) | A to A. */
5501 if (GET_CODE (op0
) == AND
5502 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5503 || rtx_equal_p (XEXP (op0
, 1), op1
))
5504 && ! side_effects_p (XEXP (op0
, 0))
5505 && ! side_effects_p (XEXP (op0
, 1)))
5508 /* If we have (ior (and A B) C), apply the distributive law and then
5509 the inverse distributive law to see if things simplify. */
5511 if (GET_CODE (op0
) == AND
)
5513 x
= apply_distributive_law
5514 (gen_binary (AND
, mode
,
5515 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5516 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5519 if (GET_CODE (x
) != IOR
)
5523 if (GET_CODE (op1
) == AND
)
5525 x
= apply_distributive_law
5526 (gen_binary (AND
, mode
,
5527 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5528 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5531 if (GET_CODE (x
) != IOR
)
5535 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5536 mode size to (rotate A CX). */
5538 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5539 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5540 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5541 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5542 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5543 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5544 == GET_MODE_BITSIZE (mode
)))
5545 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5546 (GET_CODE (op0
) == ASHIFT
5547 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5549 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5550 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5551 does not affect any of the bits in OP1, it can really be done
5552 as a PLUS and we can associate. We do this by seeing if OP1
5553 can be safely shifted left C bits. */
5554 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5555 && GET_CODE (XEXP (op0
, 0)) == PLUS
5556 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5557 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5558 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5560 int count
= INTVAL (XEXP (op0
, 1));
5561 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5563 if (mask
>> count
== INTVAL (op1
)
5564 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5566 SUBST (XEXP (XEXP (op0
, 0), 1),
5567 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5574 /* If we are XORing two things that have no bits in common,
5575 convert them into an IOR. This helps to detect rotation encoded
5576 using those methods and possibly other simplifications. */
5578 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5579 && (nonzero_bits (op0
, mode
)
5580 & nonzero_bits (op1
, mode
)) == 0)
5581 return (gen_binary (IOR
, mode
, op0
, op1
));
5583 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5584 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5587 int num_negated
= 0;
5589 if (GET_CODE (op0
) == NOT
)
5590 num_negated
++, op0
= XEXP (op0
, 0);
5591 if (GET_CODE (op1
) == NOT
)
5592 num_negated
++, op1
= XEXP (op1
, 0);
5594 if (num_negated
== 2)
5596 SUBST (XEXP (x
, 0), op0
);
5597 SUBST (XEXP (x
, 1), op1
);
5599 else if (num_negated
== 1)
5601 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5605 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5606 correspond to a machine insn or result in further simplifications
5607 if B is a constant. */
5609 if (GET_CODE (op0
) == AND
5610 && rtx_equal_p (XEXP (op0
, 1), op1
)
5611 && ! side_effects_p (op1
))
5612 return gen_binary (AND
, mode
,
5613 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5616 else if (GET_CODE (op0
) == AND
5617 && rtx_equal_p (XEXP (op0
, 0), op1
)
5618 && ! side_effects_p (op1
))
5619 return gen_binary (AND
, mode
,
5620 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5623 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5624 comparison if STORE_FLAG_VALUE is 1. */
5625 if (STORE_FLAG_VALUE
== 1
5626 && op1
== const1_rtx
5627 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5628 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5632 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5633 is (lt foo (const_int 0)), so we can perform the above
5634 simplification if STORE_FLAG_VALUE is 1. */
5636 if (STORE_FLAG_VALUE
== 1
5637 && op1
== const1_rtx
5638 && GET_CODE (op0
) == LSHIFTRT
5639 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5640 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5641 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5643 /* (xor (comparison foo bar) (const_int sign-bit))
5644 when STORE_FLAG_VALUE is the sign bit. */
5645 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5646 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5647 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5648 && op1
== const_true_rtx
5649 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5650 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5663 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5664 operations" because they can be replaced with two more basic operations.
5665 ZERO_EXTEND is also considered "compound" because it can be replaced with
5666 an AND operation, which is simpler, though only one operation.
5668 The function expand_compound_operation is called with an rtx expression
5669 and will convert it to the appropriate shifts and AND operations,
5670 simplifying at each stage.
5672 The function make_compound_operation is called to convert an expression
5673 consisting of shifts and ANDs into the equivalent compound expression.
5674 It is the inverse of this function, loosely speaking. */
5677 expand_compound_operation (rtx x
)
5679 unsigned HOST_WIDE_INT pos
= 0, len
;
5681 unsigned int modewidth
;
5684 switch (GET_CODE (x
))
5689 /* We can't necessarily use a const_int for a multiword mode;
5690 it depends on implicitly extending the value.
5691 Since we don't know the right way to extend it,
5692 we can't tell whether the implicit way is right.
5694 Even for a mode that is no wider than a const_int,
5695 we can't win, because we need to sign extend one of its bits through
5696 the rest of it, and we don't know which bit. */
5697 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5700 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5701 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5702 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5703 reloaded. If not for that, MEM's would very rarely be safe.
5705 Reject MODEs bigger than a word, because we might not be able
5706 to reference a two-register group starting with an arbitrary register
5707 (and currently gen_lowpart might crash for a SUBREG). */
5709 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5712 /* Reject MODEs that aren't scalar integers because turning vector
5713 or complex modes into shifts causes problems. */
5715 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5718 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5719 /* If the inner object has VOIDmode (the only way this can happen
5720 is if it is an ASM_OPERANDS), we can't do anything since we don't
5721 know how much masking to do. */
5730 /* If the operand is a CLOBBER, just return it. */
5731 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5734 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5735 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5736 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5739 /* Reject MODEs that aren't scalar integers because turning vector
5740 or complex modes into shifts causes problems. */
5742 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5745 len
= INTVAL (XEXP (x
, 1));
5746 pos
= INTVAL (XEXP (x
, 2));
5748 /* If this goes outside the object being extracted, replace the object
5749 with a (use (mem ...)) construct that only combine understands
5750 and is used only for this purpose. */
5751 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5752 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5754 if (BITS_BIG_ENDIAN
)
5755 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5762 /* Convert sign extension to zero extension, if we know that the high
5763 bit is not set, as this is easier to optimize. It will be converted
5764 back to cheaper alternative in make_extraction. */
5765 if (GET_CODE (x
) == SIGN_EXTEND
5766 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5767 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5768 & ~(((unsigned HOST_WIDE_INT
)
5769 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5773 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5774 rtx temp2
= expand_compound_operation (temp
);
5776 /* Make sure this is a profitable operation. */
5777 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5779 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5785 /* We can optimize some special cases of ZERO_EXTEND. */
5786 if (GET_CODE (x
) == ZERO_EXTEND
)
5788 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5789 know that the last value didn't have any inappropriate bits
5791 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5792 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5793 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5794 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5795 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5796 return XEXP (XEXP (x
, 0), 0);
5798 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5799 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5800 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5801 && subreg_lowpart_p (XEXP (x
, 0))
5802 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5803 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5804 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5805 return SUBREG_REG (XEXP (x
, 0));
5807 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5808 is a comparison and STORE_FLAG_VALUE permits. This is like
5809 the first case, but it works even when GET_MODE (x) is larger
5810 than HOST_WIDE_INT. */
5811 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5812 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5813 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5814 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5815 <= HOST_BITS_PER_WIDE_INT
)
5816 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5817 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5818 return XEXP (XEXP (x
, 0), 0);
5820 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5821 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5822 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5823 && subreg_lowpart_p (XEXP (x
, 0))
5824 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5825 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5826 <= HOST_BITS_PER_WIDE_INT
)
5827 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5828 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5829 return SUBREG_REG (XEXP (x
, 0));
5833 /* If we reach here, we want to return a pair of shifts. The inner
5834 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5835 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5836 logical depending on the value of UNSIGNEDP.
5838 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5839 converted into an AND of a shift.
5841 We must check for the case where the left shift would have a negative
5842 count. This can happen in a case like (x >> 31) & 255 on machines
5843 that can't shift by a constant. On those machines, we would first
5844 combine the shift with the AND to produce a variable-position
5845 extraction. Then the constant of 31 would be substituted in to produce
5846 a such a position. */
5848 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5849 if (modewidth
+ len
>= pos
)
5850 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5852 simplify_shift_const (NULL_RTX
, ASHIFT
,
5855 modewidth
- pos
- len
),
5858 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5859 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5860 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5863 ((HOST_WIDE_INT
) 1 << len
) - 1);
5865 /* Any other cases we can't handle. */
5868 /* If we couldn't do this for some reason, return the original
5870 if (GET_CODE (tem
) == CLOBBER
)
5876 /* X is a SET which contains an assignment of one object into
5877 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5878 or certain SUBREGS). If possible, convert it into a series of
5881 We half-heartedly support variable positions, but do not at all
5882 support variable lengths. */
5885 expand_field_assignment (rtx x
)
5888 rtx pos
; /* Always counts from low bit. */
5891 enum machine_mode compute_mode
;
5893 /* Loop until we find something we can't simplify. */
5896 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5897 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5899 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5900 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5901 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5903 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5904 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5906 inner
= XEXP (SET_DEST (x
), 0);
5907 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5908 pos
= XEXP (SET_DEST (x
), 2);
5910 /* If the position is constant and spans the width of INNER,
5911 surround INNER with a USE to indicate this. */
5912 if (GET_CODE (pos
) == CONST_INT
5913 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5914 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5916 if (BITS_BIG_ENDIAN
)
5918 if (GET_CODE (pos
) == CONST_INT
)
5919 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5921 else if (GET_CODE (pos
) == MINUS
5922 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5923 && (INTVAL (XEXP (pos
, 1))
5924 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5925 /* If position is ADJUST - X, new position is X. */
5926 pos
= XEXP (pos
, 0);
5928 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5929 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5935 /* A SUBREG between two modes that occupy the same numbers of words
5936 can be done by moving the SUBREG to the source. */
5937 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5938 /* We need SUBREGs to compute nonzero_bits properly. */
5939 && nonzero_sign_valid
5940 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5941 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5942 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5943 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5945 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5946 gen_lowpart_for_combine
5947 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5954 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5955 inner
= SUBREG_REG (inner
);
5957 compute_mode
= GET_MODE (inner
);
5959 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5960 if (! SCALAR_INT_MODE_P (compute_mode
))
5962 enum machine_mode imode
;
5964 /* Don't do anything for vector or complex integral types. */
5965 if (! FLOAT_MODE_P (compute_mode
))
5968 /* Try to find an integral mode to pun with. */
5969 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5970 if (imode
== BLKmode
)
5973 compute_mode
= imode
;
5974 inner
= gen_lowpart_for_combine (imode
, inner
);
5977 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5978 if (len
< HOST_BITS_PER_WIDE_INT
)
5979 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5983 /* Now compute the equivalent expression. Make a copy of INNER
5984 for the SET_DEST in case it is a MEM into which we will substitute;
5985 we don't want shared RTL in that case. */
5987 (VOIDmode
, copy_rtx (inner
),
5988 gen_binary (IOR
, compute_mode
,
5989 gen_binary (AND
, compute_mode
,
5990 simplify_gen_unary (NOT
, compute_mode
,
5996 gen_binary (ASHIFT
, compute_mode
,
5997 gen_binary (AND
, compute_mode
,
5998 gen_lowpart_for_combine
5999 (compute_mode
, SET_SRC (x
)),
6007 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6008 it is an RTX that represents a variable starting position; otherwise,
6009 POS is the (constant) starting bit position (counted from the LSB).
6011 INNER may be a USE. This will occur when we started with a bitfield
6012 that went outside the boundary of the object in memory, which is
6013 allowed on most machines. To isolate this case, we produce a USE
6014 whose mode is wide enough and surround the MEM with it. The only
6015 code that understands the USE is this routine. If it is not removed,
6016 it will cause the resulting insn not to match.
6018 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6021 IN_DEST is nonzero if this is a reference in the destination of a
6022 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6023 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6026 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6027 ZERO_EXTRACT should be built even for bits starting at bit 0.
6029 MODE is the desired mode of the result (if IN_DEST == 0).
6031 The result is an RTX for the extraction or NULL_RTX if the target
6035 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6036 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6037 int in_dest
, int in_compare
)
6039 /* This mode describes the size of the storage area
6040 to fetch the overall value from. Within that, we
6041 ignore the POS lowest bits, etc. */
6042 enum machine_mode is_mode
= GET_MODE (inner
);
6043 enum machine_mode inner_mode
;
6044 enum machine_mode wanted_inner_mode
= byte_mode
;
6045 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6046 enum machine_mode pos_mode
= word_mode
;
6047 enum machine_mode extraction_mode
= word_mode
;
6048 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6051 rtx orig_pos_rtx
= pos_rtx
;
6052 HOST_WIDE_INT orig_pos
;
6054 /* Get some information about INNER and get the innermost object. */
6055 if (GET_CODE (inner
) == USE
)
6056 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6057 /* We don't need to adjust the position because we set up the USE
6058 to pretend that it was a full-word object. */
6059 spans_byte
= 1, inner
= XEXP (inner
, 0);
6060 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6062 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6063 consider just the QI as the memory to extract from.
6064 The subreg adds or removes high bits; its mode is
6065 irrelevant to the meaning of this extraction,
6066 since POS and LEN count from the lsb. */
6067 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6068 is_mode
= GET_MODE (SUBREG_REG (inner
));
6069 inner
= SUBREG_REG (inner
);
6071 else if (GET_CODE (inner
) == ASHIFT
6072 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6073 && pos_rtx
== 0 && pos
== 0
6074 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6076 /* We're extracting the least significant bits of an rtx
6077 (ashift X (const_int C)), where LEN > C. Extract the
6078 least significant (LEN - C) bits of X, giving an rtx
6079 whose mode is MODE, then shift it left C times. */
6080 new = make_extraction (mode
, XEXP (inner
, 0),
6081 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6082 unsignedp
, in_dest
, in_compare
);
6084 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6087 inner_mode
= GET_MODE (inner
);
6089 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6090 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6092 /* See if this can be done without an extraction. We never can if the
6093 width of the field is not the same as that of some integer mode. For
6094 registers, we can only avoid the extraction if the position is at the
6095 low-order bit and this is either not in the destination or we have the
6096 appropriate STRICT_LOW_PART operation available.
6098 For MEM, we can avoid an extract if the field starts on an appropriate
6099 boundary and we can change the mode of the memory reference. However,
6100 we cannot directly access the MEM if we have a USE and the underlying
6101 MEM is not TMODE. This combination means that MEM was being used in a
6102 context where bits outside its mode were being referenced; that is only
6103 valid in bit-field insns. */
6105 if (tmode
!= BLKmode
6106 && ! (spans_byte
&& inner_mode
!= tmode
)
6107 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6108 && GET_CODE (inner
) != MEM
6110 || (GET_CODE (inner
) == REG
6111 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6112 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6114 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6115 : BITS_PER_UNIT
)) == 0
6116 /* We can't do this if we are widening INNER_MODE (it
6117 may not be aligned, for one thing). */
6118 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6119 && (inner_mode
== tmode
6120 || (! mode_dependent_address_p (XEXP (inner
, 0))
6121 && ! MEM_VOLATILE_P (inner
))))))
6123 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6124 field. If the original and current mode are the same, we need not
6125 adjust the offset. Otherwise, we do if bytes big endian.
6127 If INNER is not a MEM, get a piece consisting of just the field
6128 of interest (in this case POS % BITS_PER_WORD must be 0). */
6130 if (GET_CODE (inner
) == MEM
)
6132 HOST_WIDE_INT offset
;
6134 /* POS counts from lsb, but make OFFSET count in memory order. */
6135 if (BYTES_BIG_ENDIAN
)
6136 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6138 offset
= pos
/ BITS_PER_UNIT
;
6140 new = adjust_address_nv (inner
, tmode
, offset
);
6142 else if (GET_CODE (inner
) == REG
)
6144 if (tmode
!= inner_mode
)
6148 /* We can't call gen_lowpart_for_combine here since we always want
6149 a SUBREG and it would sometimes return a new hard register. */
6150 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6152 if (WORDS_BIG_ENDIAN
6153 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6154 final_word
= ((GET_MODE_SIZE (inner_mode
)
6155 - GET_MODE_SIZE (tmode
))
6156 / UNITS_PER_WORD
) - final_word
;
6158 final_word
*= UNITS_PER_WORD
;
6159 if (BYTES_BIG_ENDIAN
&&
6160 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6161 final_word
+= (GET_MODE_SIZE (inner_mode
)
6162 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6164 /* Avoid creating invalid subregs, for example when
6165 simplifying (x>>32)&255. */
6166 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6169 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6172 new = gen_lowpart_for_combine (tmode
, inner
);
6178 new = force_to_mode (inner
, tmode
,
6179 len
>= HOST_BITS_PER_WIDE_INT
6180 ? ~(unsigned HOST_WIDE_INT
) 0
6181 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6184 /* If this extraction is going into the destination of a SET,
6185 make a STRICT_LOW_PART unless we made a MEM. */
6188 return (GET_CODE (new) == MEM
? new
6189 : (GET_CODE (new) != SUBREG
6190 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6191 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6196 if (GET_CODE (new) == CONST_INT
)
6197 return gen_int_mode (INTVAL (new), mode
);
6199 /* If we know that no extraneous bits are set, and that the high
6200 bit is not set, convert the extraction to the cheaper of
6201 sign and zero extension, that are equivalent in these cases. */
6202 if (flag_expensive_optimizations
6203 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6204 && ((nonzero_bits (new, tmode
)
6205 & ~(((unsigned HOST_WIDE_INT
)
6206 GET_MODE_MASK (tmode
))
6210 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6211 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6213 /* Prefer ZERO_EXTENSION, since it gives more information to
6215 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6220 /* Otherwise, sign- or zero-extend unless we already are in the
6223 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6227 /* Unless this is a COMPARE or we have a funny memory reference,
6228 don't do anything with zero-extending field extracts starting at
6229 the low-order bit since they are simple AND operations. */
6230 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6231 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6234 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6235 we would be spanning bytes or if the position is not a constant and the
6236 length is not 1. In all other cases, we would only be going outside
6237 our object in cases when an original shift would have been
6239 if (! spans_byte
&& GET_CODE (inner
) == MEM
6240 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6241 || (pos_rtx
!= 0 && len
!= 1)))
6244 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6245 and the mode for the result. */
6246 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6248 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6249 pos_mode
= mode_for_extraction (EP_insv
, 2);
6250 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6253 if (! in_dest
&& unsignedp
6254 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6256 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6257 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6258 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6261 if (! in_dest
&& ! unsignedp
6262 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6264 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6265 pos_mode
= mode_for_extraction (EP_extv
, 3);
6266 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6269 /* Never narrow an object, since that might not be safe. */
6271 if (mode
!= VOIDmode
6272 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6273 extraction_mode
= mode
;
6275 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6276 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6277 pos_mode
= GET_MODE (pos_rtx
);
6279 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6280 if we have to change the mode of memory and cannot, the desired mode is
6282 if (GET_CODE (inner
) != MEM
)
6283 wanted_inner_mode
= wanted_inner_reg_mode
;
6284 else if (inner_mode
!= wanted_inner_mode
6285 && (mode_dependent_address_p (XEXP (inner
, 0))
6286 || MEM_VOLATILE_P (inner
)))
6287 wanted_inner_mode
= extraction_mode
;
6291 if (BITS_BIG_ENDIAN
)
6293 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6294 BITS_BIG_ENDIAN style. If position is constant, compute new
6295 position. Otherwise, build subtraction.
6296 Note that POS is relative to the mode of the original argument.
6297 If it's a MEM we need to recompute POS relative to that.
6298 However, if we're extracting from (or inserting into) a register,
6299 we want to recompute POS relative to wanted_inner_mode. */
6300 int width
= (GET_CODE (inner
) == MEM
6301 ? GET_MODE_BITSIZE (is_mode
)
6302 : GET_MODE_BITSIZE (wanted_inner_mode
));
6305 pos
= width
- len
- pos
;
6308 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6309 /* POS may be less than 0 now, but we check for that below.
6310 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6313 /* If INNER has a wider mode, make it smaller. If this is a constant
6314 extract, try to adjust the byte to point to the byte containing
6316 if (wanted_inner_mode
!= VOIDmode
6317 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6318 && ((GET_CODE (inner
) == MEM
6319 && (inner_mode
== wanted_inner_mode
6320 || (! mode_dependent_address_p (XEXP (inner
, 0))
6321 && ! MEM_VOLATILE_P (inner
))))))
6325 /* The computations below will be correct if the machine is big
6326 endian in both bits and bytes or little endian in bits and bytes.
6327 If it is mixed, we must adjust. */
6329 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6330 adjust OFFSET to compensate. */
6331 if (BYTES_BIG_ENDIAN
6333 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6334 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6336 /* If this is a constant position, we can move to the desired byte. */
6339 offset
+= pos
/ BITS_PER_UNIT
;
6340 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6343 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6345 && is_mode
!= wanted_inner_mode
)
6346 offset
= (GET_MODE_SIZE (is_mode
)
6347 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6349 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6350 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6353 /* If INNER is not memory, we can always get it into the proper mode. If we
6354 are changing its mode, POS must be a constant and smaller than the size
6356 else if (GET_CODE (inner
) != MEM
)
6358 if (GET_MODE (inner
) != wanted_inner_mode
6360 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6363 inner
= force_to_mode (inner
, wanted_inner_mode
,
6365 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6366 ? ~(unsigned HOST_WIDE_INT
) 0
6367 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6372 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6373 have to zero extend. Otherwise, we can just use a SUBREG. */
6375 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6377 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6379 /* If we know that no extraneous bits are set, and that the high
6380 bit is not set, convert extraction to cheaper one - either
6381 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6383 if (flag_expensive_optimizations
6384 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6385 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6386 & ~(((unsigned HOST_WIDE_INT
)
6387 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6391 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6393 /* Prefer ZERO_EXTENSION, since it gives more information to
6395 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6400 else if (pos_rtx
!= 0
6401 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6402 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6404 /* Make POS_RTX unless we already have it and it is correct. If we don't
6405 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6407 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6408 pos_rtx
= orig_pos_rtx
;
6410 else if (pos_rtx
== 0)
6411 pos_rtx
= GEN_INT (pos
);
6413 /* Make the required operation. See if we can use existing rtx. */
6414 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6415 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6417 new = gen_lowpart_for_combine (mode
, new);
6422 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6423 with any other operations in X. Return X without that shift if so. */
6426 extract_left_shift (rtx x
, int count
)
6428 enum rtx_code code
= GET_CODE (x
);
6429 enum machine_mode mode
= GET_MODE (x
);
6435 /* This is the shift itself. If it is wide enough, we will return
6436 either the value being shifted if the shift count is equal to
6437 COUNT or a shift for the difference. */
6438 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6439 && INTVAL (XEXP (x
, 1)) >= count
)
6440 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6441 INTVAL (XEXP (x
, 1)) - count
);
6445 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6446 return simplify_gen_unary (code
, mode
, tem
, mode
);
6450 case PLUS
: case IOR
: case XOR
: case AND
:
6451 /* If we can safely shift this constant and we find the inner shift,
6452 make a new operation. */
6453 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6454 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6455 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6456 return gen_binary (code
, mode
, tem
,
6457 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6468 /* Look at the expression rooted at X. Look for expressions
6469 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6470 Form these expressions.
6472 Return the new rtx, usually just X.
6474 Also, for machines like the VAX that don't have logical shift insns,
6475 try to convert logical to arithmetic shift operations in cases where
6476 they are equivalent. This undoes the canonicalizations to logical
6477 shifts done elsewhere.
6479 We try, as much as possible, to re-use rtl expressions to save memory.
6481 IN_CODE says what kind of expression we are processing. Normally, it is
6482 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6483 being kludges), it is MEM. When processing the arguments of a comparison
6484 or a COMPARE against zero, it is COMPARE. */
6487 make_compound_operation (rtx x
, enum rtx_code in_code
)
6489 enum rtx_code code
= GET_CODE (x
);
6490 enum machine_mode mode
= GET_MODE (x
);
6491 int mode_width
= GET_MODE_BITSIZE (mode
);
6493 enum rtx_code next_code
;
6499 /* Select the code to be used in recursive calls. Once we are inside an
6500 address, we stay there. If we have a comparison, set to COMPARE,
6501 but once inside, go back to our default of SET. */
6503 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6504 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6505 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6506 : in_code
== COMPARE
? SET
: in_code
);
6508 /* Process depending on the code of this operation. If NEW is set
6509 nonzero, it will be returned. */
6514 /* Convert shifts by constants into multiplications if inside
6516 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6517 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6518 && INTVAL (XEXP (x
, 1)) >= 0)
6520 new = make_compound_operation (XEXP (x
, 0), next_code
);
6521 new = gen_rtx_MULT (mode
, new,
6522 GEN_INT ((HOST_WIDE_INT
) 1
6523 << INTVAL (XEXP (x
, 1))));
6528 /* If the second operand is not a constant, we can't do anything
6530 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6533 /* If the constant is a power of two minus one and the first operand
6534 is a logical right shift, make an extraction. */
6535 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6536 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6538 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6539 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6540 0, in_code
== COMPARE
);
6543 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6544 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6545 && subreg_lowpart_p (XEXP (x
, 0))
6546 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6547 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6549 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6551 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6552 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6553 0, in_code
== COMPARE
);
6555 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6556 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6557 || GET_CODE (XEXP (x
, 0)) == IOR
)
6558 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6559 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6560 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6562 /* Apply the distributive law, and then try to make extractions. */
6563 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6564 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6566 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6568 new = make_compound_operation (new, in_code
);
6571 /* If we are have (and (rotate X C) M) and C is larger than the number
6572 of bits in M, this is an extraction. */
6574 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6575 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6576 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6577 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6579 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6580 new = make_extraction (mode
, new,
6581 (GET_MODE_BITSIZE (mode
)
6582 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6583 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6586 /* On machines without logical shifts, if the operand of the AND is
6587 a logical shift and our mask turns off all the propagated sign
6588 bits, we can replace the logical shift with an arithmetic shift. */
6589 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6590 && !have_insn_for (LSHIFTRT
, mode
)
6591 && have_insn_for (ASHIFTRT
, mode
)
6592 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6593 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6594 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6595 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6597 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6599 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6600 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6602 gen_rtx_ASHIFTRT (mode
,
6603 make_compound_operation
6604 (XEXP (XEXP (x
, 0), 0), next_code
),
6605 XEXP (XEXP (x
, 0), 1)));
6608 /* If the constant is one less than a power of two, this might be
6609 representable by an extraction even if no shift is present.
6610 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6611 we are in a COMPARE. */
6612 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6613 new = make_extraction (mode
,
6614 make_compound_operation (XEXP (x
, 0),
6616 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6618 /* If we are in a comparison and this is an AND with a power of two,
6619 convert this into the appropriate bit extract. */
6620 else if (in_code
== COMPARE
6621 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6622 new = make_extraction (mode
,
6623 make_compound_operation (XEXP (x
, 0),
6625 i
, NULL_RTX
, 1, 1, 0, 1);
6630 /* If the sign bit is known to be zero, replace this with an
6631 arithmetic shift. */
6632 if (have_insn_for (ASHIFTRT
, mode
)
6633 && ! have_insn_for (LSHIFTRT
, mode
)
6634 && mode_width
<= HOST_BITS_PER_WIDE_INT
6635 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6637 new = gen_rtx_ASHIFTRT (mode
,
6638 make_compound_operation (XEXP (x
, 0),
6644 /* ... fall through ... */
6650 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6651 this is a SIGN_EXTRACT. */
6652 if (GET_CODE (rhs
) == CONST_INT
6653 && GET_CODE (lhs
) == ASHIFT
6654 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6655 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6657 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6658 new = make_extraction (mode
, new,
6659 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6660 NULL_RTX
, mode_width
- INTVAL (rhs
),
6661 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6665 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6666 If so, try to merge the shifts into a SIGN_EXTEND. We could
6667 also do this for some cases of SIGN_EXTRACT, but it doesn't
6668 seem worth the effort; the case checked for occurs on Alpha. */
6670 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6671 && ! (GET_CODE (lhs
) == SUBREG
6672 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6673 && GET_CODE (rhs
) == CONST_INT
6674 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6675 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6676 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6677 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6678 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6683 /* Call ourselves recursively on the inner expression. If we are
6684 narrowing the object and it has a different RTL code from
6685 what it originally did, do this SUBREG as a force_to_mode. */
6687 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6688 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6689 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6690 && subreg_lowpart_p (x
))
6692 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6695 /* If we have something other than a SUBREG, we might have
6696 done an expansion, so rerun ourselves. */
6697 if (GET_CODE (newer
) != SUBREG
)
6698 newer
= make_compound_operation (newer
, in_code
);
6703 /* If this is a paradoxical subreg, and the new code is a sign or
6704 zero extension, omit the subreg and widen the extension. If it
6705 is a regular subreg, we can still get rid of the subreg by not
6706 widening so much, or in fact removing the extension entirely. */
6707 if ((GET_CODE (tem
) == SIGN_EXTEND
6708 || GET_CODE (tem
) == ZERO_EXTEND
)
6709 && subreg_lowpart_p (x
))
6711 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6712 || (GET_MODE_SIZE (mode
) >
6713 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6715 if (! SCALAR_INT_MODE_P (mode
))
6717 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6720 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6731 x
= gen_lowpart_for_combine (mode
, new);
6732 code
= GET_CODE (x
);
6735 /* Now recursively process each operand of this operation. */
6736 fmt
= GET_RTX_FORMAT (code
);
6737 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6740 new = make_compound_operation (XEXP (x
, i
), next_code
);
6741 SUBST (XEXP (x
, i
), new);
6747 /* Given M see if it is a value that would select a field of bits
6748 within an item, but not the entire word. Return -1 if not.
6749 Otherwise, return the starting position of the field, where 0 is the
6752 *PLEN is set to the length of the field. */
6755 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6757 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6758 int pos
= exact_log2 (m
& -m
);
6764 /* Now shift off the low-order zero bits and see if we have a power of
6766 len
= exact_log2 ((m
>> pos
) + 1);
6775 /* See if X can be simplified knowing that we will only refer to it in
6776 MODE and will only refer to those bits that are nonzero in MASK.
6777 If other bits are being computed or if masking operations are done
6778 that select a superset of the bits in MASK, they can sometimes be
6781 Return a possibly simplified expression, but always convert X to
6782 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6784 Also, if REG is nonzero and X is a register equal in value to REG,
6787 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6788 are all off in X. This is used when X will be complemented, by either
6789 NOT, NEG, or XOR. */
6792 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6793 rtx reg
, int just_select
)
6795 enum rtx_code code
= GET_CODE (x
);
6796 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6797 enum machine_mode op_mode
;
6798 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6801 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6802 code below will do the wrong thing since the mode of such an
6803 expression is VOIDmode.
6805 Also do nothing if X is a CLOBBER; this can happen if X was
6806 the return value from a call to gen_lowpart_for_combine. */
6807 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6810 /* We want to perform the operation is its present mode unless we know
6811 that the operation is valid in MODE, in which case we do the operation
6813 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6814 && have_insn_for (code
, mode
))
6815 ? mode
: GET_MODE (x
));
6817 /* It is not valid to do a right-shift in a narrower mode
6818 than the one it came in with. */
6819 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6820 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6821 op_mode
= GET_MODE (x
);
6823 /* Truncate MASK to fit OP_MODE. */
6825 mask
&= GET_MODE_MASK (op_mode
);
6827 /* When we have an arithmetic operation, or a shift whose count we
6828 do not know, we need to assume that all bit the up to the highest-order
6829 bit in MASK will be needed. This is how we form such a mask. */
6831 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6832 ? GET_MODE_MASK (op_mode
)
6833 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6836 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6838 /* Determine what bits of X are guaranteed to be (non)zero. */
6839 nonzero
= nonzero_bits (x
, mode
);
6841 /* If none of the bits in X are needed, return a zero. */
6842 if (! just_select
&& (nonzero
& mask
) == 0)
6845 /* If X is a CONST_INT, return a new one. Do this here since the
6846 test below will fail. */
6847 if (GET_CODE (x
) == CONST_INT
)
6849 if (SCALAR_INT_MODE_P (mode
))
6850 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6853 x
= GEN_INT (INTVAL (x
) & mask
);
6854 return gen_lowpart_common (mode
, x
);
6858 /* If X is narrower than MODE and we want all the bits in X's mode, just
6859 get X in the proper mode. */
6860 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6861 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6862 return gen_lowpart_for_combine (mode
, x
);
6864 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6865 MASK are already known to be zero in X, we need not do anything. */
6866 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6872 /* If X is a (clobber (const_int)), return it since we know we are
6873 generating something that won't match. */
6877 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6878 spanned the boundary of the MEM. If we are now masking so it is
6879 within that boundary, we don't need the USE any more. */
6880 if (! BITS_BIG_ENDIAN
6881 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6882 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6889 x
= expand_compound_operation (x
);
6890 if (GET_CODE (x
) != code
)
6891 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6895 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6896 || rtx_equal_p (reg
, get_last_value (x
))))
6901 if (subreg_lowpart_p (x
)
6902 /* We can ignore the effect of this SUBREG if it narrows the mode or
6903 if the constant masks to zero all the bits the mode doesn't
6905 && ((GET_MODE_SIZE (GET_MODE (x
))
6906 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6908 & GET_MODE_MASK (GET_MODE (x
))
6909 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6910 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6914 /* If this is an AND with a constant, convert it into an AND
6915 whose constant is the AND of that constant with MASK. If it
6916 remains an AND of MASK, delete it since it is redundant. */
6918 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6920 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6921 mask
& INTVAL (XEXP (x
, 1)));
6923 /* If X is still an AND, see if it is an AND with a mask that
6924 is just some low-order bits. If so, and it is MASK, we don't
6927 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6928 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6932 /* If it remains an AND, try making another AND with the bits
6933 in the mode mask that aren't in MASK turned on. If the
6934 constant in the AND is wide enough, this might make a
6935 cheaper constant. */
6937 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6938 && GET_MODE_MASK (GET_MODE (x
)) != mask
6939 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6941 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6942 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6943 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6946 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6947 number, sign extend it. */
6948 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6949 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6950 cval
|= (HOST_WIDE_INT
) -1 << width
;
6952 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6953 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6963 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6964 low-order bits (as in an alignment operation) and FOO is already
6965 aligned to that boundary, mask C1 to that boundary as well.
6966 This may eliminate that PLUS and, later, the AND. */
6969 unsigned int width
= GET_MODE_BITSIZE (mode
);
6970 unsigned HOST_WIDE_INT smask
= mask
;
6972 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6973 number, sign extend it. */
6975 if (width
< HOST_BITS_PER_WIDE_INT
6976 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6977 smask
|= (HOST_WIDE_INT
) -1 << width
;
6979 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6980 && exact_log2 (- smask
) >= 0
6981 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6982 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6983 return force_to_mode (plus_constant (XEXP (x
, 0),
6984 (INTVAL (XEXP (x
, 1)) & smask
)),
6985 mode
, smask
, reg
, next_select
);
6988 /* ... fall through ... */
6991 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6992 most significant bit in MASK since carries from those bits will
6993 affect the bits we are interested in. */
6998 /* If X is (minus C Y) where C's least set bit is larger than any bit
6999 in the mask, then we may replace with (neg Y). */
7000 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7001 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7002 & -INTVAL (XEXP (x
, 0))))
7005 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7007 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7010 /* Similarly, if C contains every bit in the fuller_mask, then we may
7011 replace with (not Y). */
7012 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7013 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7014 == INTVAL (XEXP (x
, 0))))
7016 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7017 XEXP (x
, 1), GET_MODE (x
));
7018 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7026 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7027 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7028 operation which may be a bitfield extraction. Ensure that the
7029 constant we form is not wider than the mode of X. */
7031 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7032 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7033 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7034 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7035 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7036 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7037 + floor_log2 (INTVAL (XEXP (x
, 1))))
7038 < GET_MODE_BITSIZE (GET_MODE (x
)))
7039 && (INTVAL (XEXP (x
, 1))
7040 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7042 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7043 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7044 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7045 XEXP (XEXP (x
, 0), 0), temp
);
7046 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7047 XEXP (XEXP (x
, 0), 1));
7048 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7052 /* For most binary operations, just propagate into the operation and
7053 change the mode if we have an operation of that mode. */
7055 op0
= gen_lowpart_for_combine (op_mode
,
7056 force_to_mode (XEXP (x
, 0), mode
, mask
,
7058 op1
= gen_lowpart_for_combine (op_mode
,
7059 force_to_mode (XEXP (x
, 1), mode
, mask
,
7062 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7063 x
= gen_binary (code
, op_mode
, op0
, op1
);
7067 /* For left shifts, do the same, but just for the first operand.
7068 However, we cannot do anything with shifts where we cannot
7069 guarantee that the counts are smaller than the size of the mode
7070 because such a count will have a different meaning in a
7073 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7074 && INTVAL (XEXP (x
, 1)) >= 0
7075 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7076 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7077 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7078 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7081 /* If the shift count is a constant and we can do arithmetic in
7082 the mode of the shift, refine which bits we need. Otherwise, use the
7083 conservative form of the mask. */
7084 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7085 && INTVAL (XEXP (x
, 1)) >= 0
7086 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7087 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7088 mask
>>= INTVAL (XEXP (x
, 1));
7092 op0
= gen_lowpart_for_combine (op_mode
,
7093 force_to_mode (XEXP (x
, 0), op_mode
,
7094 mask
, reg
, next_select
));
7096 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7097 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7101 /* Here we can only do something if the shift count is a constant,
7102 this shift constant is valid for the host, and we can do arithmetic
7105 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7106 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7107 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7109 rtx inner
= XEXP (x
, 0);
7110 unsigned HOST_WIDE_INT inner_mask
;
7112 /* Select the mask of the bits we need for the shift operand. */
7113 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7115 /* We can only change the mode of the shift if we can do arithmetic
7116 in the mode of the shift and INNER_MASK is no wider than the
7117 width of OP_MODE. */
7118 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7119 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7120 op_mode
= GET_MODE (x
);
7122 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7124 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7125 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7128 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7129 shift and AND produces only copies of the sign bit (C2 is one less
7130 than a power of two), we can do this with just a shift. */
7132 if (GET_CODE (x
) == LSHIFTRT
7133 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7134 /* The shift puts one of the sign bit copies in the least significant
7136 && ((INTVAL (XEXP (x
, 1))
7137 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7138 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7139 && exact_log2 (mask
+ 1) >= 0
7140 /* Number of bits left after the shift must be more than the mask
7142 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7143 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7144 /* Must be more sign bit copies than the mask needs. */
7145 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7146 >= exact_log2 (mask
+ 1)))
7147 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7148 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7149 - exact_log2 (mask
+ 1)));
7154 /* If we are just looking for the sign bit, we don't need this shift at
7155 all, even if it has a variable count. */
7156 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7157 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7158 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7159 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7161 /* If this is a shift by a constant, get a mask that contains those bits
7162 that are not copies of the sign bit. We then have two cases: If
7163 MASK only includes those bits, this can be a logical shift, which may
7164 allow simplifications. If MASK is a single-bit field not within
7165 those bits, we are requesting a copy of the sign bit and hence can
7166 shift the sign bit to the appropriate location. */
7168 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7169 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7173 /* If the considered data is wider than HOST_WIDE_INT, we can't
7174 represent a mask for all its bits in a single scalar.
7175 But we only care about the lower bits, so calculate these. */
7177 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7179 nonzero
= ~(HOST_WIDE_INT
) 0;
7181 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7182 is the number of bits a full-width mask would have set.
7183 We need only shift if these are fewer than nonzero can
7184 hold. If not, we must keep all bits set in nonzero. */
7186 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7187 < HOST_BITS_PER_WIDE_INT
)
7188 nonzero
>>= INTVAL (XEXP (x
, 1))
7189 + HOST_BITS_PER_WIDE_INT
7190 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7194 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7195 nonzero
>>= INTVAL (XEXP (x
, 1));
7198 if ((mask
& ~nonzero
) == 0
7199 || (i
= exact_log2 (mask
)) >= 0)
7201 x
= simplify_shift_const
7202 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7203 i
< 0 ? INTVAL (XEXP (x
, 1))
7204 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7206 if (GET_CODE (x
) != ASHIFTRT
)
7207 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7211 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7212 even if the shift count isn't a constant. */
7214 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7218 /* If this is a zero- or sign-extension operation that just affects bits
7219 we don't care about, remove it. Be sure the call above returned
7220 something that is still a shift. */
7222 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7223 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7224 && INTVAL (XEXP (x
, 1)) >= 0
7225 && (INTVAL (XEXP (x
, 1))
7226 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7227 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7228 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7229 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7236 /* If the shift count is constant and we can do computations
7237 in the mode of X, compute where the bits we care about are.
7238 Otherwise, we can't do anything. Don't change the mode of
7239 the shift or propagate MODE into the shift, though. */
7240 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7241 && INTVAL (XEXP (x
, 1)) >= 0)
7243 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7244 GET_MODE (x
), GEN_INT (mask
),
7246 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7248 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7249 INTVAL (temp
), reg
, next_select
));
7254 /* If we just want the low-order bit, the NEG isn't needed since it
7255 won't change the low-order bit. */
7257 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7259 /* We need any bits less significant than the most significant bit in
7260 MASK since carries from those bits will affect the bits we are
7266 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7267 same as the XOR case above. Ensure that the constant we form is not
7268 wider than the mode of X. */
7270 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7271 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7272 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7273 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7274 < GET_MODE_BITSIZE (GET_MODE (x
)))
7275 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7277 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7279 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7280 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7282 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7285 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7286 use the full mask inside the NOT. */
7290 op0
= gen_lowpart_for_combine (op_mode
,
7291 force_to_mode (XEXP (x
, 0), mode
, mask
,
7293 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7294 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7298 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7299 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7300 which is equal to STORE_FLAG_VALUE. */
7301 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7302 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7303 && (nonzero_bits (XEXP (x
, 0), mode
)
7304 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7305 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7310 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7311 written in a narrower mode. We play it safe and do not do so. */
7314 gen_lowpart_for_combine (GET_MODE (x
),
7315 force_to_mode (XEXP (x
, 1), mode
,
7316 mask
, reg
, next_select
)));
7318 gen_lowpart_for_combine (GET_MODE (x
),
7319 force_to_mode (XEXP (x
, 2), mode
,
7320 mask
, reg
, next_select
)));
7327 /* Ensure we return a value of the proper mode. */
7328 return gen_lowpart_for_combine (mode
, x
);
7331 /* Return nonzero if X is an expression that has one of two values depending on
7332 whether some other value is zero or nonzero. In that case, we return the
7333 value that is being tested, *PTRUE is set to the value if the rtx being
7334 returned has a nonzero value, and *PFALSE is set to the other alternative.
7336 If we return zero, we set *PTRUE and *PFALSE to X. */
7339 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7341 enum machine_mode mode
= GET_MODE (x
);
7342 enum rtx_code code
= GET_CODE (x
);
7343 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7344 unsigned HOST_WIDE_INT nz
;
7346 /* If we are comparing a value against zero, we are done. */
7347 if ((code
== NE
|| code
== EQ
)
7348 && XEXP (x
, 1) == const0_rtx
)
7350 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7351 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7355 /* If this is a unary operation whose operand has one of two values, apply
7356 our opcode to compute those values. */
7357 else if (GET_RTX_CLASS (code
) == '1'
7358 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7360 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7361 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7362 GET_MODE (XEXP (x
, 0)));
7366 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7367 make can't possibly match and would suppress other optimizations. */
7368 else if (code
== COMPARE
)
7371 /* If this is a binary operation, see if either side has only one of two
7372 values. If either one does or if both do and they are conditional on
7373 the same value, compute the new true and false values. */
7374 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7375 || GET_RTX_CLASS (code
) == '<')
7377 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7378 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7380 if ((cond0
!= 0 || cond1
!= 0)
7381 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7383 /* If if_then_else_cond returned zero, then true/false are the
7384 same rtl. We must copy one of them to prevent invalid rtl
7387 true0
= copy_rtx (true0
);
7388 else if (cond1
== 0)
7389 true1
= copy_rtx (true1
);
7391 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7392 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7393 return cond0
? cond0
: cond1
;
7396 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7397 operands is zero when the other is nonzero, and vice-versa,
7398 and STORE_FLAG_VALUE is 1 or -1. */
7400 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7401 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7403 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7405 rtx op0
= XEXP (XEXP (x
, 0), 1);
7406 rtx op1
= XEXP (XEXP (x
, 1), 1);
7408 cond0
= XEXP (XEXP (x
, 0), 0);
7409 cond1
= XEXP (XEXP (x
, 1), 0);
7411 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7412 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7413 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7414 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7415 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7416 || ((swap_condition (GET_CODE (cond0
))
7417 == combine_reversed_comparison_code (cond1
))
7418 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7419 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7420 && ! side_effects_p (x
))
7422 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7423 *pfalse
= gen_binary (MULT
, mode
,
7425 ? simplify_gen_unary (NEG
, mode
, op1
,
7433 /* Similarly for MULT, AND and UMIN, except that for these the result
7435 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7436 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7437 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7439 cond0
= XEXP (XEXP (x
, 0), 0);
7440 cond1
= XEXP (XEXP (x
, 1), 0);
7442 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7443 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7444 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7445 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7446 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7447 || ((swap_condition (GET_CODE (cond0
))
7448 == combine_reversed_comparison_code (cond1
))
7449 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7450 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7451 && ! side_effects_p (x
))
7453 *ptrue
= *pfalse
= const0_rtx
;
7459 else if (code
== IF_THEN_ELSE
)
7461 /* If we have IF_THEN_ELSE already, extract the condition and
7462 canonicalize it if it is NE or EQ. */
7463 cond0
= XEXP (x
, 0);
7464 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7465 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7466 return XEXP (cond0
, 0);
7467 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7469 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7470 return XEXP (cond0
, 0);
7476 /* If X is a SUBREG, we can narrow both the true and false values
7477 if the inner expression, if there is a condition. */
7478 else if (code
== SUBREG
7479 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7482 *ptrue
= simplify_gen_subreg (mode
, true0
,
7483 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7484 *pfalse
= simplify_gen_subreg (mode
, false0
,
7485 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7490 /* If X is a constant, this isn't special and will cause confusions
7491 if we treat it as such. Likewise if it is equivalent to a constant. */
7492 else if (CONSTANT_P (x
)
7493 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7496 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7497 will be least confusing to the rest of the compiler. */
7498 else if (mode
== BImode
)
7500 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7504 /* If X is known to be either 0 or -1, those are the true and
7505 false values when testing X. */
7506 else if (x
== constm1_rtx
|| x
== const0_rtx
7507 || (mode
!= VOIDmode
7508 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7510 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7514 /* Likewise for 0 or a single bit. */
7515 else if (mode
!= VOIDmode
7516 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7517 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7519 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7523 /* Otherwise fail; show no condition with true and false values the same. */
7524 *ptrue
= *pfalse
= x
;
7528 /* Return the value of expression X given the fact that condition COND
7529 is known to be true when applied to REG as its first operand and VAL
7530 as its second. X is known to not be shared and so can be modified in
7533 We only handle the simplest cases, and specifically those cases that
7534 arise with IF_THEN_ELSE expressions. */
7537 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7539 enum rtx_code code
= GET_CODE (x
);
7544 if (side_effects_p (x
))
7547 /* If either operand of the condition is a floating point value,
7548 then we have to avoid collapsing an EQ comparison. */
7550 && rtx_equal_p (x
, reg
)
7551 && ! FLOAT_MODE_P (GET_MODE (x
))
7552 && ! FLOAT_MODE_P (GET_MODE (val
)))
7555 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7558 /* If X is (abs REG) and we know something about REG's relationship
7559 with zero, we may be able to simplify this. */
7561 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7564 case GE
: case GT
: case EQ
:
7567 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7569 GET_MODE (XEXP (x
, 0)));
7574 /* The only other cases we handle are MIN, MAX, and comparisons if the
7575 operands are the same as REG and VAL. */
7577 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7579 if (rtx_equal_p (XEXP (x
, 0), val
))
7580 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7582 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7584 if (GET_RTX_CLASS (code
) == '<')
7586 if (comparison_dominates_p (cond
, code
))
7587 return const_true_rtx
;
7589 code
= combine_reversed_comparison_code (x
);
7591 && comparison_dominates_p (cond
, code
))
7596 else if (code
== SMAX
|| code
== SMIN
7597 || code
== UMIN
|| code
== UMAX
)
7599 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7601 /* Do not reverse the condition when it is NE or EQ.
7602 This is because we cannot conclude anything about
7603 the value of 'SMAX (x, y)' when x is not equal to y,
7604 but we can when x equals y. */
7605 if ((code
== SMAX
|| code
== UMAX
)
7606 && ! (cond
== EQ
|| cond
== NE
))
7607 cond
= reverse_condition (cond
);
7612 return unsignedp
? x
: XEXP (x
, 1);
7614 return unsignedp
? x
: XEXP (x
, 0);
7616 return unsignedp
? XEXP (x
, 1) : x
;
7618 return unsignedp
? XEXP (x
, 0) : x
;
7625 else if (code
== SUBREG
)
7627 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7628 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7630 if (SUBREG_REG (x
) != r
)
7632 /* We must simplify subreg here, before we lose track of the
7633 original inner_mode. */
7634 new = simplify_subreg (GET_MODE (x
), r
,
7635 inner_mode
, SUBREG_BYTE (x
));
7639 SUBST (SUBREG_REG (x
), r
);
7644 /* We don't have to handle SIGN_EXTEND here, because even in the
7645 case of replacing something with a modeless CONST_INT, a
7646 CONST_INT is already (supposed to be) a valid sign extension for
7647 its narrower mode, which implies it's already properly
7648 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7649 story is different. */
7650 else if (code
== ZERO_EXTEND
)
7652 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7653 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7655 if (XEXP (x
, 0) != r
)
7657 /* We must simplify the zero_extend here, before we lose
7658 track of the original inner_mode. */
7659 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7664 SUBST (XEXP (x
, 0), r
);
7670 fmt
= GET_RTX_FORMAT (code
);
7671 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7674 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7675 else if (fmt
[i
] == 'E')
7676 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7677 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7684 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7685 assignment as a field assignment. */
7688 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7690 if (x
== y
|| rtx_equal_p (x
, y
))
7693 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7696 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7697 Note that all SUBREGs of MEM are paradoxical; otherwise they
7698 would have been rewritten. */
7699 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7700 && GET_CODE (SUBREG_REG (y
)) == MEM
7701 && rtx_equal_p (SUBREG_REG (y
),
7702 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7705 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7706 && GET_CODE (SUBREG_REG (x
)) == MEM
7707 && rtx_equal_p (SUBREG_REG (x
),
7708 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7711 /* We used to see if get_last_value of X and Y were the same but that's
7712 not correct. In one direction, we'll cause the assignment to have
7713 the wrong destination and in the case, we'll import a register into this
7714 insn that might have already have been dead. So fail if none of the
7715 above cases are true. */
7719 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7720 Return that assignment if so.
7722 We only handle the most common cases. */
7725 make_field_assignment (rtx x
)
7727 rtx dest
= SET_DEST (x
);
7728 rtx src
= SET_SRC (x
);
7733 unsigned HOST_WIDE_INT len
;
7735 enum machine_mode mode
;
7737 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7738 a clear of a one-bit field. We will have changed it to
7739 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7742 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7743 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7744 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7745 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7747 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7750 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7754 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7755 && subreg_lowpart_p (XEXP (src
, 0))
7756 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7757 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7758 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7759 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7760 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7762 assign
= make_extraction (VOIDmode
, dest
, 0,
7763 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7766 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7770 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7772 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7773 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7774 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7776 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7779 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7783 /* The other case we handle is assignments into a constant-position
7784 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7785 a mask that has all one bits except for a group of zero bits and
7786 OTHER is known to have zeros where C1 has ones, this is such an
7787 assignment. Compute the position and length from C1. Shift OTHER
7788 to the appropriate position, force it to the required mode, and
7789 make the extraction. Check for the AND in both operands. */
7791 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7794 rhs
= expand_compound_operation (XEXP (src
, 0));
7795 lhs
= expand_compound_operation (XEXP (src
, 1));
7797 if (GET_CODE (rhs
) == AND
7798 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7799 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7800 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7801 else if (GET_CODE (lhs
) == AND
7802 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7803 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7804 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7808 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7809 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7810 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7811 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7814 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7818 /* The mode to use for the source is the mode of the assignment, or of
7819 what is inside a possible STRICT_LOW_PART. */
7820 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7821 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7823 /* Shift OTHER right POS places and make it the source, restricting it
7824 to the proper length and mode. */
7826 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7827 GET_MODE (src
), other
, pos
),
7829 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7830 ? ~(unsigned HOST_WIDE_INT
) 0
7831 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7834 /* If SRC is masked by an AND that does not make a difference in
7835 the value being stored, strip it. */
7836 if (GET_CODE (assign
) == ZERO_EXTRACT
7837 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7838 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7839 && GET_CODE (src
) == AND
7840 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7841 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7842 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7843 src
= XEXP (src
, 0);
7845 return gen_rtx_SET (VOIDmode
, assign
, src
);
7848 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7852 apply_distributive_law (rtx x
)
7854 enum rtx_code code
= GET_CODE (x
);
7855 rtx lhs
, rhs
, other
;
7857 enum rtx_code inner_code
;
7859 /* Distributivity is not true for floating point.
7860 It can change the value. So don't do it.
7861 -- rms and moshier@world.std.com. */
7862 if (FLOAT_MODE_P (GET_MODE (x
)))
7865 /* The outer operation can only be one of the following: */
7866 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7867 && code
!= PLUS
&& code
!= MINUS
)
7870 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7872 /* If either operand is a primitive we can't do anything, so get out
7874 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7875 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7878 lhs
= expand_compound_operation (lhs
);
7879 rhs
= expand_compound_operation (rhs
);
7880 inner_code
= GET_CODE (lhs
);
7881 if (inner_code
!= GET_CODE (rhs
))
7884 /* See if the inner and outer operations distribute. */
7891 /* These all distribute except over PLUS. */
7892 if (code
== PLUS
|| code
== MINUS
)
7897 if (code
!= PLUS
&& code
!= MINUS
)
7902 /* This is also a multiply, so it distributes over everything. */
7906 /* Non-paradoxical SUBREGs distributes over all operations, provided
7907 the inner modes and byte offsets are the same, this is an extraction
7908 of a low-order part, we don't convert an fp operation to int or
7909 vice versa, and we would not be converting a single-word
7910 operation into a multi-word operation. The latter test is not
7911 required, but it prevents generating unneeded multi-word operations.
7912 Some of the previous tests are redundant given the latter test, but
7913 are retained because they are required for correctness.
7915 We produce the result slightly differently in this case. */
7917 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7918 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7919 || ! subreg_lowpart_p (lhs
)
7920 || (GET_MODE_CLASS (GET_MODE (lhs
))
7921 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7922 || (GET_MODE_SIZE (GET_MODE (lhs
))
7923 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7924 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7927 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7928 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7929 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7935 /* Set LHS and RHS to the inner operands (A and B in the example
7936 above) and set OTHER to the common operand (C in the example).
7937 These is only one way to do this unless the inner operation is
7939 if (GET_RTX_CLASS (inner_code
) == 'c'
7940 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7941 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7942 else if (GET_RTX_CLASS (inner_code
) == 'c'
7943 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7944 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7945 else if (GET_RTX_CLASS (inner_code
) == 'c'
7946 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7947 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7948 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7949 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7953 /* Form the new inner operation, seeing if it simplifies first. */
7954 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7956 /* There is one exception to the general way of distributing:
7957 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7958 if (code
== XOR
&& inner_code
== IOR
)
7961 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7964 /* We may be able to continuing distributing the result, so call
7965 ourselves recursively on the inner operation before forming the
7966 outer operation, which we return. */
7967 return gen_binary (inner_code
, GET_MODE (x
),
7968 apply_distributive_law (tem
), other
);
7971 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7974 Return an equivalent form, if different from X. Otherwise, return X. If
7975 X is zero, we are to always construct the equivalent form. */
7978 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7979 unsigned HOST_WIDE_INT constop
)
7981 unsigned HOST_WIDE_INT nonzero
;
7984 /* Simplify VAROP knowing that we will be only looking at some of the
7987 Note by passing in CONSTOP, we guarantee that the bits not set in
7988 CONSTOP are not significant and will never be examined. We must
7989 ensure that is the case by explicitly masking out those bits
7990 before returning. */
7991 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7993 /* If VAROP is a CLOBBER, we will fail so return it. */
7994 if (GET_CODE (varop
) == CLOBBER
)
7997 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7998 to VAROP and return the new constant. */
7999 if (GET_CODE (varop
) == CONST_INT
)
8000 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8002 /* See what bits may be nonzero in VAROP. Unlike the general case of
8003 a call to nonzero_bits, here we don't care about bits outside
8006 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8008 /* Turn off all bits in the constant that are known to already be zero.
8009 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8010 which is tested below. */
8014 /* If we don't have any bits left, return zero. */
8018 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8019 a power of two, we can replace this with an ASHIFT. */
8020 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8021 && (i
= exact_log2 (constop
)) >= 0)
8022 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8024 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8025 or XOR, then try to apply the distributive law. This may eliminate
8026 operations if either branch can be simplified because of the AND.
8027 It may also make some cases more complex, but those cases probably
8028 won't match a pattern either with or without this. */
8030 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8032 gen_lowpart_for_combine
8034 apply_distributive_law
8035 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8036 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8037 XEXP (varop
, 0), constop
),
8038 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8039 XEXP (varop
, 1), constop
))));
8041 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8042 the AND and see if one of the operands simplifies to zero. If so, we
8043 may eliminate it. */
8045 if (GET_CODE (varop
) == PLUS
8046 && exact_log2 (constop
+ 1) >= 0)
8050 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8051 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8052 if (o0
== const0_rtx
)
8054 if (o1
== const0_rtx
)
8058 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8059 if we already had one (just check for the simplest cases). */
8060 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8061 && GET_MODE (XEXP (x
, 0)) == mode
8062 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8063 varop
= XEXP (x
, 0);
8065 varop
= gen_lowpart_for_combine (mode
, varop
);
8067 /* If we can't make the SUBREG, try to return what we were given. */
8068 if (GET_CODE (varop
) == CLOBBER
)
8069 return x
? x
: varop
;
8071 /* If we are only masking insignificant bits, return VAROP. */
8072 if (constop
== nonzero
)
8076 /* Otherwise, return an AND. */
8077 constop
= trunc_int_for_mode (constop
, mode
);
8078 /* See how much, if any, of X we can use. */
8079 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8080 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8084 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8085 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8086 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8088 SUBST (XEXP (x
, 0), varop
);
8095 #define nonzero_bits_with_known(X, MODE) \
8096 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8098 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8099 It avoids exponential behavior in nonzero_bits1 when X has
8100 identical subexpressions on the first or the second level. */
8102 static unsigned HOST_WIDE_INT
8103 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8104 enum machine_mode known_mode
,
8105 unsigned HOST_WIDE_INT known_ret
)
8107 if (x
== known_x
&& mode
== known_mode
)
8110 /* Try to find identical subexpressions. If found call
8111 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8112 precomputed value for the subexpression as KNOWN_RET. */
8114 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8115 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8117 rtx x0
= XEXP (x
, 0);
8118 rtx x1
= XEXP (x
, 1);
8120 /* Check the first level. */
8122 return nonzero_bits1 (x
, mode
, x0
, mode
,
8123 nonzero_bits_with_known (x0
, mode
));
8125 /* Check the second level. */
8126 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8127 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8128 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8129 return nonzero_bits1 (x
, mode
, x1
, mode
,
8130 nonzero_bits_with_known (x1
, mode
));
8132 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8133 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8134 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8135 return nonzero_bits1 (x
, mode
, x0
, mode
,
8136 nonzero_bits_with_known (x0
, mode
));
8139 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8142 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8143 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8144 is less useful. We can't allow both, because that results in exponential
8145 run time recursion. There is a nullstone testcase that triggered
8146 this. This macro avoids accidental uses of num_sign_bit_copies. */
8147 #define cached_num_sign_bit_copies()
8149 /* Given an expression, X, compute which bits in X can be nonzero.
8150 We don't care about bits outside of those defined in MODE.
8152 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8153 a shift, AND, or zero_extract, we can do better. */
8155 static unsigned HOST_WIDE_INT
8156 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8157 enum machine_mode known_mode
,
8158 unsigned HOST_WIDE_INT known_ret
)
8160 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8161 unsigned HOST_WIDE_INT inner_nz
;
8163 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8166 /* For floating-point values, assume all bits are needed. */
8167 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8170 /* If X is wider than MODE, use its mode instead. */
8171 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8173 mode
= GET_MODE (x
);
8174 nonzero
= GET_MODE_MASK (mode
);
8175 mode_width
= GET_MODE_BITSIZE (mode
);
8178 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8179 /* Our only callers in this case look for single bit values. So
8180 just return the mode mask. Those tests will then be false. */
8183 #ifndef WORD_REGISTER_OPERATIONS
8184 /* If MODE is wider than X, but both are a single word for both the host
8185 and target machines, we can compute this from which bits of the
8186 object might be nonzero in its own mode, taking into account the fact
8187 that on many CISC machines, accessing an object in a wider mode
8188 causes the high-order bits to become undefined. So they are
8189 not known to be zero. */
8191 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8192 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8193 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8194 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8196 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8197 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8202 code
= GET_CODE (x
);
8206 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8207 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8208 all the bits above ptr_mode are known to be zero. */
8209 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8211 nonzero
&= GET_MODE_MASK (ptr_mode
);
8214 /* Include declared information about alignment of pointers. */
8215 /* ??? We don't properly preserve REG_POINTER changes across
8216 pointer-to-integer casts, so we can't trust it except for
8217 things that we know must be pointers. See execute/960116-1.c. */
8218 if ((x
== stack_pointer_rtx
8219 || x
== frame_pointer_rtx
8220 || x
== arg_pointer_rtx
)
8221 && REGNO_POINTER_ALIGN (REGNO (x
)))
8223 unsigned HOST_WIDE_INT alignment
8224 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8226 #ifdef PUSH_ROUNDING
8227 /* If PUSH_ROUNDING is defined, it is possible for the
8228 stack to be momentarily aligned only to that amount,
8229 so we pick the least alignment. */
8230 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8231 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8235 nonzero
&= ~(alignment
- 1);
8238 /* If X is a register whose nonzero bits value is current, use it.
8239 Otherwise, if X is a register whose value we can find, use that
8240 value. Otherwise, use the previously-computed global nonzero bits
8241 for this register. */
8243 if (reg_last_set_value
[REGNO (x
)] != 0
8244 && (reg_last_set_mode
[REGNO (x
)] == mode
8245 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8246 && GET_MODE_CLASS (mode
) == MODE_INT
))
8247 && (reg_last_set_label
[REGNO (x
)] == label_tick
8248 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8249 && REG_N_SETS (REGNO (x
)) == 1
8250 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8252 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8253 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8255 tem
= get_last_value (x
);
8259 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8260 /* If X is narrower than MODE and TEM is a non-negative
8261 constant that would appear negative in the mode of X,
8262 sign-extend it for use in reg_nonzero_bits because some
8263 machines (maybe most) will actually do the sign-extension
8264 and this is the conservative approach.
8266 ??? For 2.5, try to tighten up the MD files in this regard
8267 instead of this kludge. */
8269 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8270 && GET_CODE (tem
) == CONST_INT
8272 && 0 != (INTVAL (tem
)
8273 & ((HOST_WIDE_INT
) 1
8274 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8275 tem
= GEN_INT (INTVAL (tem
)
8276 | ((HOST_WIDE_INT
) (-1)
8277 << GET_MODE_BITSIZE (GET_MODE (x
))));
8279 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8281 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8283 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8285 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8286 /* We don't know anything about the upper bits. */
8287 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8288 return nonzero
& mask
;
8294 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8295 /* If X is negative in MODE, sign-extend the value. */
8296 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8297 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8298 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8304 #ifdef LOAD_EXTEND_OP
8305 /* In many, if not most, RISC machines, reading a byte from memory
8306 zeros the rest of the register. Noticing that fact saves a lot
8307 of extra zero-extends. */
8308 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8309 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8314 case UNEQ
: case LTGT
:
8315 case GT
: case GTU
: case UNGT
:
8316 case LT
: case LTU
: case UNLT
:
8317 case GE
: case GEU
: case UNGE
:
8318 case LE
: case LEU
: case UNLE
:
8319 case UNORDERED
: case ORDERED
:
8321 /* If this produces an integer result, we know which bits are set.
8322 Code here used to clear bits outside the mode of X, but that is
8325 if (GET_MODE_CLASS (mode
) == MODE_INT
8326 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8327 nonzero
= STORE_FLAG_VALUE
;
8332 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8333 and num_sign_bit_copies. */
8334 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8335 == GET_MODE_BITSIZE (GET_MODE (x
)))
8339 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8340 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8345 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8346 and num_sign_bit_copies. */
8347 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8348 == GET_MODE_BITSIZE (GET_MODE (x
)))
8354 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8355 & GET_MODE_MASK (mode
));
8359 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8360 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8361 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8365 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8366 Otherwise, show all the bits in the outer mode but not the inner
8368 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8369 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8371 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8373 & (((HOST_WIDE_INT
) 1
8374 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8375 inner_nz
|= (GET_MODE_MASK (mode
)
8376 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8379 nonzero
&= inner_nz
;
8383 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8384 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8388 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8390 unsigned HOST_WIDE_INT nonzero0
=
8391 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8393 /* Don't call nonzero_bits for the second time if it cannot change
8395 if ((nonzero
& nonzero0
) != nonzero
)
8396 nonzero
&= (nonzero0
8397 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8401 case PLUS
: case MINUS
:
8403 case DIV
: case UDIV
:
8404 case MOD
: case UMOD
:
8405 /* We can apply the rules of arithmetic to compute the number of
8406 high- and low-order zero bits of these operations. We start by
8407 computing the width (position of the highest-order nonzero bit)
8408 and the number of low-order zero bits for each value. */
8410 unsigned HOST_WIDE_INT nz0
=
8411 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8412 unsigned HOST_WIDE_INT nz1
=
8413 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8414 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8415 int width0
= floor_log2 (nz0
) + 1;
8416 int width1
= floor_log2 (nz1
) + 1;
8417 int low0
= floor_log2 (nz0
& -nz0
);
8418 int low1
= floor_log2 (nz1
& -nz1
);
8419 HOST_WIDE_INT op0_maybe_minusp
8420 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8421 HOST_WIDE_INT op1_maybe_minusp
8422 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8423 unsigned int result_width
= mode_width
;
8429 result_width
= MAX (width0
, width1
) + 1;
8430 result_low
= MIN (low0
, low1
);
8433 result_low
= MIN (low0
, low1
);
8436 result_width
= width0
+ width1
;
8437 result_low
= low0
+ low1
;
8442 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8443 result_width
= width0
;
8448 result_width
= width0
;
8453 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8454 result_width
= MIN (width0
, width1
);
8455 result_low
= MIN (low0
, low1
);
8460 result_width
= MIN (width0
, width1
);
8461 result_low
= MIN (low0
, low1
);
8467 if (result_width
< mode_width
)
8468 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8471 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8473 #ifdef POINTERS_EXTEND_UNSIGNED
8474 /* If pointers extend unsigned and this is an addition or subtraction
8475 to a pointer in Pmode, all the bits above ptr_mode are known to be
8477 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8478 && (code
== PLUS
|| code
== MINUS
)
8479 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8480 nonzero
&= GET_MODE_MASK (ptr_mode
);
8486 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8487 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8488 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8492 /* If this is a SUBREG formed for a promoted variable that has
8493 been zero-extended, we know that at least the high-order bits
8494 are zero, though others might be too. */
8496 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8497 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8498 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8500 /* If the inner mode is a single word for both the host and target
8501 machines, we can compute this from which bits of the inner
8502 object might be nonzero. */
8503 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8504 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8505 <= HOST_BITS_PER_WIDE_INT
))
8507 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8509 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8510 /* If this is a typical RISC machine, we only have to worry
8511 about the way loads are extended. */
8512 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8514 & (((unsigned HOST_WIDE_INT
) 1
8515 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8517 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8518 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8521 /* On many CISC machines, accessing an object in a wider mode
8522 causes the high-order bits to become undefined. So they are
8523 not known to be zero. */
8524 if (GET_MODE_SIZE (GET_MODE (x
))
8525 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8526 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8527 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8536 /* The nonzero bits are in two classes: any bits within MODE
8537 that aren't in GET_MODE (x) are always significant. The rest of the
8538 nonzero bits are those that are significant in the operand of
8539 the shift when shifted the appropriate number of bits. This
8540 shows that high-order bits are cleared by the right shift and
8541 low-order bits by left shifts. */
8542 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8543 && INTVAL (XEXP (x
, 1)) >= 0
8544 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8546 enum machine_mode inner_mode
= GET_MODE (x
);
8547 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8548 int count
= INTVAL (XEXP (x
, 1));
8549 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8550 unsigned HOST_WIDE_INT op_nonzero
=
8551 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8552 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8553 unsigned HOST_WIDE_INT outer
= 0;
8555 if (mode_width
> width
)
8556 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8558 if (code
== LSHIFTRT
)
8560 else if (code
== ASHIFTRT
)
8564 /* If the sign bit may have been nonzero before the shift, we
8565 need to mark all the places it could have been copied to
8566 by the shift as possibly nonzero. */
8567 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8568 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8570 else if (code
== ASHIFT
)
8573 inner
= ((inner
<< (count
% width
)
8574 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8576 nonzero
&= (outer
| inner
);
8582 /* This is at most the number of bits in the mode. */
8583 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8587 /* If CLZ has a known value at zero, then the nonzero bits are
8588 that value, plus the number of bits in the mode minus one. */
8589 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8590 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8596 /* If CTZ has a known value at zero, then the nonzero bits are
8597 that value, plus the number of bits in the mode minus one. */
8598 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8599 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8609 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8610 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8620 /* See the macro definition above. */
8621 #undef cached_num_sign_bit_copies
8623 #define num_sign_bit_copies_with_known(X, M) \
8624 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8626 /* The function cached_num_sign_bit_copies is a wrapper around
8627 num_sign_bit_copies1. It avoids exponential behavior in
8628 num_sign_bit_copies1 when X has identical subexpressions on the
8629 first or the second level. */
8632 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8633 enum machine_mode known_mode
,
8634 unsigned int known_ret
)
8636 if (x
== known_x
&& mode
== known_mode
)
8639 /* Try to find identical subexpressions. If found call
8640 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8641 the precomputed value for the subexpression as KNOWN_RET. */
8643 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8644 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8646 rtx x0
= XEXP (x
, 0);
8647 rtx x1
= XEXP (x
, 1);
8649 /* Check the first level. */
8652 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8653 num_sign_bit_copies_with_known (x0
, mode
));
8655 /* Check the second level. */
8656 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8657 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8658 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8660 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8661 num_sign_bit_copies_with_known (x1
, mode
));
8663 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8664 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8665 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8667 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8668 num_sign_bit_copies_with_known (x0
, mode
));
8671 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8674 /* Return the number of bits at the high-order end of X that are known to
8675 be equal to the sign bit. X will be used in mode MODE; if MODE is
8676 VOIDmode, X will be used in its own mode. The returned value will always
8677 be between 1 and the number of bits in MODE. */
8680 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8681 enum machine_mode known_mode
,
8682 unsigned int known_ret
)
8684 enum rtx_code code
= GET_CODE (x
);
8685 unsigned int bitwidth
;
8686 int num0
, num1
, result
;
8687 unsigned HOST_WIDE_INT nonzero
;
8690 /* If we weren't given a mode, use the mode of X. If the mode is still
8691 VOIDmode, we don't know anything. Likewise if one of the modes is
8694 if (mode
== VOIDmode
)
8695 mode
= GET_MODE (x
);
8697 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8700 bitwidth
= GET_MODE_BITSIZE (mode
);
8702 /* For a smaller object, just ignore the high bits. */
8703 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8705 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8707 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8710 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8712 #ifndef WORD_REGISTER_OPERATIONS
8713 /* If this machine does not do all register operations on the entire
8714 register and MODE is wider than the mode of X, we can say nothing
8715 at all about the high-order bits. */
8718 /* Likewise on machines that do, if the mode of the object is smaller
8719 than a word and loads of that size don't sign extend, we can say
8720 nothing about the high order bits. */
8721 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8722 #ifdef LOAD_EXTEND_OP
8723 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8734 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8735 /* If pointers extend signed and this is a pointer in Pmode, say that
8736 all the bits above ptr_mode are known to be sign bit copies. */
8737 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8739 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8742 if (reg_last_set_value
[REGNO (x
)] != 0
8743 && reg_last_set_mode
[REGNO (x
)] == mode
8744 && (reg_last_set_label
[REGNO (x
)] == label_tick
8745 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8746 && REG_N_SETS (REGNO (x
)) == 1
8747 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8749 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8750 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8752 tem
= get_last_value (x
);
8754 return num_sign_bit_copies_with_known (tem
, mode
);
8756 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8757 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8758 return reg_sign_bit_copies
[REGNO (x
)];
8762 #ifdef LOAD_EXTEND_OP
8763 /* Some RISC machines sign-extend all loads of smaller than a word. */
8764 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8765 return MAX (1, ((int) bitwidth
8766 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8771 /* If the constant is negative, take its 1's complement and remask.
8772 Then see how many zero bits we have. */
8773 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8774 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8775 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8776 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8778 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8781 /* If this is a SUBREG for a promoted object that is sign-extended
8782 and we are looking at it in a wider mode, we know that at least the
8783 high-order bits are known to be sign bit copies. */
8785 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8787 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8788 return MAX ((int) bitwidth
8789 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8793 /* For a smaller object, just ignore the high bits. */
8794 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8796 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8797 return MAX (1, (num0
8798 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8802 #ifdef WORD_REGISTER_OPERATIONS
8803 #ifdef LOAD_EXTEND_OP
8804 /* For paradoxical SUBREGs on machines where all register operations
8805 affect the entire register, just look inside. Note that we are
8806 passing MODE to the recursive call, so the number of sign bit copies
8807 will remain relative to that mode, not the inner mode. */
8809 /* This works only if loads sign extend. Otherwise, if we get a
8810 reload for the inner part, it may be loaded from the stack, and
8811 then we lose all sign bit copies that existed before the store
8814 if ((GET_MODE_SIZE (GET_MODE (x
))
8815 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8816 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8817 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8818 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8824 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8825 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8829 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8830 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8833 /* For a smaller object, just ignore the high bits. */
8834 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8835 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8839 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8841 case ROTATE
: case ROTATERT
:
8842 /* If we are rotating left by a number of bits less than the number
8843 of sign bit copies, we can just subtract that amount from the
8845 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8846 && INTVAL (XEXP (x
, 1)) >= 0
8847 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8849 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8850 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8851 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8856 /* In general, this subtracts one sign bit copy. But if the value
8857 is known to be positive, the number of sign bit copies is the
8858 same as that of the input. Finally, if the input has just one bit
8859 that might be nonzero, all the bits are copies of the sign bit. */
8860 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8861 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8862 return num0
> 1 ? num0
- 1 : 1;
8864 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8869 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8874 case IOR
: case AND
: case XOR
:
8875 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8876 /* Logical operations will preserve the number of sign-bit copies.
8877 MIN and MAX operations always return one of the operands. */
8878 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8879 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8880 return MIN (num0
, num1
);
8882 case PLUS
: case MINUS
:
8883 /* For addition and subtraction, we can have a 1-bit carry. However,
8884 if we are subtracting 1 from a positive number, there will not
8885 be such a carry. Furthermore, if the positive number is known to
8886 be 0 or 1, we know the result is either -1 or 0. */
8888 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8889 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8891 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8892 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8893 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8894 : bitwidth
- floor_log2 (nonzero
) - 1);
8897 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8898 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8899 result
= MAX (1, MIN (num0
, num1
) - 1);
8901 #ifdef POINTERS_EXTEND_UNSIGNED
8902 /* If pointers extend signed and this is an addition or subtraction
8903 to a pointer in Pmode, all the bits above ptr_mode are known to be
8905 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8906 && (code
== PLUS
|| code
== MINUS
)
8907 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8908 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8909 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8915 /* The number of bits of the product is the sum of the number of
8916 bits of both terms. However, unless one of the terms if known
8917 to be positive, we must allow for an additional bit since negating
8918 a negative number can remove one sign bit copy. */
8920 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8921 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8923 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8925 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8926 || (((nonzero_bits (XEXP (x
, 0), mode
)
8927 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8928 && ((nonzero_bits (XEXP (x
, 1), mode
)
8929 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8932 return MAX (1, result
);
8935 /* The result must be <= the first operand. If the first operand
8936 has the high bit set, we know nothing about the number of sign
8938 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8940 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8941 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8944 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8947 /* The result must be <= the second operand. */
8948 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8951 /* Similar to unsigned division, except that we have to worry about
8952 the case where the divisor is negative, in which case we have
8954 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8956 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8957 || (nonzero_bits (XEXP (x
, 1), mode
)
8958 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8964 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8966 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8967 || (nonzero_bits (XEXP (x
, 1), mode
)
8968 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8974 /* Shifts by a constant add to the number of bits equal to the
8976 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8977 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8978 && INTVAL (XEXP (x
, 1)) > 0)
8979 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8984 /* Left shifts destroy copies. */
8985 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8986 || INTVAL (XEXP (x
, 1)) < 0
8987 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8990 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8991 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8994 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8995 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8996 return MIN (num0
, num1
);
8998 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8999 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
9000 case GEU
: case GTU
: case LEU
: case LTU
:
9001 case UNORDERED
: case ORDERED
:
9002 /* If the constant is negative, take its 1's complement and remask.
9003 Then see how many zero bits we have. */
9004 nonzero
= STORE_FLAG_VALUE
;
9005 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
9006 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
9007 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
9009 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
9016 /* If we haven't been able to figure it out by one of the above rules,
9017 see if some of the high-order bits are known to be zero. If so,
9018 count those bits and return one less than that amount. If we can't
9019 safely compute the mask for this mode, always return BITWIDTH. */
9021 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
9024 nonzero
= nonzero_bits (x
, mode
);
9025 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
9026 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
9029 /* Return the number of "extended" bits there are in X, when interpreted
9030 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9031 unsigned quantities, this is the number of high-order zero bits.
9032 For signed quantities, this is the number of copies of the sign bit
9033 minus 1. In both case, this function returns the number of "spare"
9034 bits. For example, if two quantities for which this function returns
9035 at least 1 are added, the addition is known not to overflow.
9037 This function will always return 0 unless called during combine, which
9038 implies that it must be called from a define_split. */
9041 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
9043 if (nonzero_sign_valid
== 0)
9047 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9048 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9049 - floor_log2 (nonzero_bits (x
, mode
)))
9051 : num_sign_bit_copies (x
, mode
) - 1);
9054 /* This function is called from `simplify_shift_const' to merge two
9055 outer operations. Specifically, we have already found that we need
9056 to perform operation *POP0 with constant *PCONST0 at the outermost
9057 position. We would now like to also perform OP1 with constant CONST1
9058 (with *POP0 being done last).
9060 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9061 the resulting operation. *PCOMP_P is set to 1 if we would need to
9062 complement the innermost operand, otherwise it is unchanged.
9064 MODE is the mode in which the operation will be done. No bits outside
9065 the width of this mode matter. It is assumed that the width of this mode
9066 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9068 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9069 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9070 result is simply *PCONST0.
9072 If the resulting operation cannot be expressed as one operation, we
9073 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9076 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9078 enum rtx_code op0
= *pop0
;
9079 HOST_WIDE_INT const0
= *pconst0
;
9081 const0
&= GET_MODE_MASK (mode
);
9082 const1
&= GET_MODE_MASK (mode
);
9084 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9088 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9091 if (op1
== NIL
|| op0
== SET
)
9094 else if (op0
== NIL
)
9095 op0
= op1
, const0
= const1
;
9097 else if (op0
== op1
)
9121 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9122 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9125 /* If the two constants aren't the same, we can't do anything. The
9126 remaining six cases can all be done. */
9127 else if (const0
!= const1
)
9135 /* (a & b) | b == b */
9137 else /* op1 == XOR */
9138 /* (a ^ b) | b == a | b */
9144 /* (a & b) ^ b == (~a) & b */
9145 op0
= AND
, *pcomp_p
= 1;
9146 else /* op1 == IOR */
9147 /* (a | b) ^ b == a & ~b */
9148 op0
= AND
, const0
= ~const0
;
9153 /* (a | b) & b == b */
9155 else /* op1 == XOR */
9156 /* (a ^ b) & b) == (~a) & b */
9163 /* Check for NO-OP cases. */
9164 const0
&= GET_MODE_MASK (mode
);
9166 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9168 else if (const0
== 0 && op0
== AND
)
9170 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9174 /* ??? Slightly redundant with the above mask, but not entirely.
9175 Moving this above means we'd have to sign-extend the mode mask
9176 for the final test. */
9177 const0
= trunc_int_for_mode (const0
, mode
);
9185 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9186 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9187 that we started with.
9189 The shift is normally computed in the widest mode we find in VAROP, as
9190 long as it isn't a different number of words than RESULT_MODE. Exceptions
9191 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9194 simplify_shift_const (rtx x
, enum rtx_code code
,
9195 enum machine_mode result_mode
, rtx varop
,
9198 enum rtx_code orig_code
= code
;
9201 enum machine_mode mode
= result_mode
;
9202 enum machine_mode shift_mode
, tmode
;
9203 unsigned int mode_words
9204 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9205 /* We form (outer_op (code varop count) (outer_const)). */
9206 enum rtx_code outer_op
= NIL
;
9207 HOST_WIDE_INT outer_const
= 0;
9209 int complement_p
= 0;
9212 /* Make sure and truncate the "natural" shift on the way in. We don't
9213 want to do this inside the loop as it makes it more difficult to
9215 #ifdef SHIFT_COUNT_TRUNCATED
9216 if (SHIFT_COUNT_TRUNCATED
)
9217 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9220 /* If we were given an invalid count, don't do anything except exactly
9221 what was requested. */
9223 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9228 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9233 /* Unless one of the branches of the `if' in this loop does a `continue',
9234 we will `break' the loop after the `if'. */
9238 /* If we have an operand of (clobber (const_int 0)), just return that
9240 if (GET_CODE (varop
) == CLOBBER
)
9243 /* If we discovered we had to complement VAROP, leave. Making a NOT
9244 here would cause an infinite loop. */
9248 /* Convert ROTATERT to ROTATE. */
9249 if (code
== ROTATERT
)
9251 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9253 if (VECTOR_MODE_P (result_mode
))
9254 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9256 count
= bitsize
- count
;
9259 /* We need to determine what mode we will do the shift in. If the
9260 shift is a right shift or a ROTATE, we must always do it in the mode
9261 it was originally done in. Otherwise, we can do it in MODE, the
9262 widest mode encountered. */
9264 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9265 ? result_mode
: mode
);
9267 /* Handle cases where the count is greater than the size of the mode
9268 minus 1. For ASHIFT, use the size minus one as the count (this can
9269 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9270 take the count modulo the size. For other shifts, the result is
9273 Since these shifts are being produced by the compiler by combining
9274 multiple operations, each of which are defined, we know what the
9275 result is supposed to be. */
9277 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9279 if (code
== ASHIFTRT
)
9280 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9281 else if (code
== ROTATE
|| code
== ROTATERT
)
9282 count
%= GET_MODE_BITSIZE (shift_mode
);
9285 /* We can't simply return zero because there may be an
9293 /* An arithmetic right shift of a quantity known to be -1 or 0
9295 if (code
== ASHIFTRT
9296 && (num_sign_bit_copies (varop
, shift_mode
)
9297 == GET_MODE_BITSIZE (shift_mode
)))
9303 /* If we are doing an arithmetic right shift and discarding all but
9304 the sign bit copies, this is equivalent to doing a shift by the
9305 bitsize minus one. Convert it into that shift because it will often
9306 allow other simplifications. */
9308 if (code
== ASHIFTRT
9309 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9310 >= GET_MODE_BITSIZE (shift_mode
)))
9311 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9313 /* We simplify the tests below and elsewhere by converting
9314 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9315 `make_compound_operation' will convert it to an ASHIFTRT for
9316 those machines (such as VAX) that don't have an LSHIFTRT. */
9317 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9319 && ((nonzero_bits (varop
, shift_mode
)
9320 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9324 if (code
== LSHIFTRT
9325 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9326 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9329 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9330 && !((nonzero_bits (varop
, shift_mode
) << count
)
9331 & GET_MODE_MASK (shift_mode
)))
9334 switch (GET_CODE (varop
))
9340 new = expand_compound_operation (varop
);
9349 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9350 minus the width of a smaller mode, we can do this with a
9351 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9352 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9353 && ! mode_dependent_address_p (XEXP (varop
, 0))
9354 && ! MEM_VOLATILE_P (varop
)
9355 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9356 MODE_INT
, 1)) != BLKmode
)
9358 new = adjust_address_nv (varop
, tmode
,
9359 BYTES_BIG_ENDIAN
? 0
9360 : count
/ BITS_PER_UNIT
);
9362 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9363 : ZERO_EXTEND
, mode
, new);
9370 /* Similar to the case above, except that we can only do this if
9371 the resulting mode is the same as that of the underlying
9372 MEM and adjust the address depending on the *bits* endianness
9373 because of the way that bit-field extract insns are defined. */
9374 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9375 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9376 MODE_INT
, 1)) != BLKmode
9377 && tmode
== GET_MODE (XEXP (varop
, 0)))
9379 if (BITS_BIG_ENDIAN
)
9380 new = XEXP (varop
, 0);
9383 new = copy_rtx (XEXP (varop
, 0));
9384 SUBST (XEXP (new, 0),
9385 plus_constant (XEXP (new, 0),
9386 count
/ BITS_PER_UNIT
));
9389 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9390 : ZERO_EXTEND
, mode
, new);
9397 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9398 the same number of words as what we've seen so far. Then store
9399 the widest mode in MODE. */
9400 if (subreg_lowpart_p (varop
)
9401 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9402 > GET_MODE_SIZE (GET_MODE (varop
)))
9403 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9404 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9407 varop
= SUBREG_REG (varop
);
9408 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9409 mode
= GET_MODE (varop
);
9415 /* Some machines use MULT instead of ASHIFT because MULT
9416 is cheaper. But it is still better on those machines to
9417 merge two shifts into one. */
9418 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9419 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9422 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9423 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9429 /* Similar, for when divides are cheaper. */
9430 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9431 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9434 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9435 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9441 /* If we are extracting just the sign bit of an arithmetic
9442 right shift, that shift is not needed. However, the sign
9443 bit of a wider mode may be different from what would be
9444 interpreted as the sign bit in a narrower mode, so, if
9445 the result is narrower, don't discard the shift. */
9446 if (code
== LSHIFTRT
9447 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9448 && (GET_MODE_BITSIZE (result_mode
)
9449 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9451 varop
= XEXP (varop
, 0);
9455 /* ... fall through ... */
9460 /* Here we have two nested shifts. The result is usually the
9461 AND of a new shift with a mask. We compute the result below. */
9462 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9463 && INTVAL (XEXP (varop
, 1)) >= 0
9464 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9465 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9466 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9468 enum rtx_code first_code
= GET_CODE (varop
);
9469 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9470 unsigned HOST_WIDE_INT mask
;
9473 /* We have one common special case. We can't do any merging if
9474 the inner code is an ASHIFTRT of a smaller mode. However, if
9475 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9476 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9477 we can convert it to
9478 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9479 This simplifies certain SIGN_EXTEND operations. */
9480 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9481 && count
== (unsigned int)
9482 (GET_MODE_BITSIZE (result_mode
)
9483 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9485 /* C3 has the low-order C1 bits zero. */
9487 mask
= (GET_MODE_MASK (mode
)
9488 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9490 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9491 XEXP (varop
, 0), mask
);
9492 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9494 count
= first_count
;
9499 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9500 than C1 high-order bits equal to the sign bit, we can convert
9501 this to either an ASHIFT or an ASHIFTRT depending on the
9504 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9506 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9507 && GET_MODE (varop
) == shift_mode
9508 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9511 varop
= XEXP (varop
, 0);
9513 signed_count
= count
- first_count
;
9514 if (signed_count
< 0)
9515 count
= -signed_count
, code
= ASHIFT
;
9517 count
= signed_count
;
9522 /* There are some cases we can't do. If CODE is ASHIFTRT,
9523 we can only do this if FIRST_CODE is also ASHIFTRT.
9525 We can't do the case when CODE is ROTATE and FIRST_CODE is
9528 If the mode of this shift is not the mode of the outer shift,
9529 we can't do this if either shift is a right shift or ROTATE.
9531 Finally, we can't do any of these if the mode is too wide
9532 unless the codes are the same.
9534 Handle the case where the shift codes are the same
9537 if (code
== first_code
)
9539 if (GET_MODE (varop
) != result_mode
9540 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9544 count
+= first_count
;
9545 varop
= XEXP (varop
, 0);
9549 if (code
== ASHIFTRT
9550 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9551 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9552 || (GET_MODE (varop
) != result_mode
9553 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9554 || first_code
== ROTATE
9555 || code
== ROTATE
)))
9558 /* To compute the mask to apply after the shift, shift the
9559 nonzero bits of the inner shift the same way the
9560 outer shift will. */
9562 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9565 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9568 /* Give up if we can't compute an outer operation to use. */
9570 || GET_CODE (mask_rtx
) != CONST_INT
9571 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9573 result_mode
, &complement_p
))
9576 /* If the shifts are in the same direction, we add the
9577 counts. Otherwise, we subtract them. */
9578 signed_count
= count
;
9579 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9580 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9581 signed_count
+= first_count
;
9583 signed_count
-= first_count
;
9585 /* If COUNT is positive, the new shift is usually CODE,
9586 except for the two exceptions below, in which case it is
9587 FIRST_CODE. If the count is negative, FIRST_CODE should
9589 if (signed_count
> 0
9590 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9591 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9592 code
= first_code
, count
= signed_count
;
9593 else if (signed_count
< 0)
9594 code
= first_code
, count
= -signed_count
;
9596 count
= signed_count
;
9598 varop
= XEXP (varop
, 0);
9602 /* If we have (A << B << C) for any shift, we can convert this to
9603 (A << C << B). This wins if A is a constant. Only try this if
9604 B is not a constant. */
9606 else if (GET_CODE (varop
) == code
9607 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9609 = simplify_binary_operation (code
, mode
,
9613 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9620 /* Make this fit the case below. */
9621 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9622 GEN_INT (GET_MODE_MASK (mode
)));
9628 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9629 with C the size of VAROP - 1 and the shift is logical if
9630 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9631 we have an (le X 0) operation. If we have an arithmetic shift
9632 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9633 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9635 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9636 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9637 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9638 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9639 && count
== (unsigned int)
9640 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9641 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9644 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9647 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9648 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9653 /* If we have (shift (logical)), move the logical to the outside
9654 to allow it to possibly combine with another logical and the
9655 shift to combine with another shift. This also canonicalizes to
9656 what a ZERO_EXTRACT looks like. Also, some machines have
9657 (and (shift)) insns. */
9659 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9660 && (new = simplify_binary_operation (code
, result_mode
,
9662 GEN_INT (count
))) != 0
9663 && GET_CODE (new) == CONST_INT
9664 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9665 INTVAL (new), result_mode
, &complement_p
))
9667 varop
= XEXP (varop
, 0);
9671 /* If we can't do that, try to simplify the shift in each arm of the
9672 logical expression, make a new logical expression, and apply
9673 the inverse distributive law. */
9675 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9676 XEXP (varop
, 0), count
);
9677 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9678 XEXP (varop
, 1), count
);
9680 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9681 varop
= apply_distributive_law (varop
);
9688 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9689 says that the sign bit can be tested, FOO has mode MODE, C is
9690 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9691 that may be nonzero. */
9692 if (code
== LSHIFTRT
9693 && XEXP (varop
, 1) == const0_rtx
9694 && GET_MODE (XEXP (varop
, 0)) == result_mode
9695 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9696 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9697 && ((STORE_FLAG_VALUE
9698 & ((HOST_WIDE_INT
) 1
9699 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9700 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9701 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9702 (HOST_WIDE_INT
) 1, result_mode
,
9705 varop
= XEXP (varop
, 0);
9712 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9713 than the number of bits in the mode is equivalent to A. */
9714 if (code
== LSHIFTRT
9715 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9716 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9718 varop
= XEXP (varop
, 0);
9723 /* NEG commutes with ASHIFT since it is multiplication. Move the
9724 NEG outside to allow shifts to combine. */
9726 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9727 (HOST_WIDE_INT
) 0, result_mode
,
9730 varop
= XEXP (varop
, 0);
9736 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9737 is one less than the number of bits in the mode is
9738 equivalent to (xor A 1). */
9739 if (code
== LSHIFTRT
9740 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9741 && XEXP (varop
, 1) == constm1_rtx
9742 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9743 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9744 (HOST_WIDE_INT
) 1, result_mode
,
9748 varop
= XEXP (varop
, 0);
9752 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9753 that might be nonzero in BAR are those being shifted out and those
9754 bits are known zero in FOO, we can replace the PLUS with FOO.
9755 Similarly in the other operand order. This code occurs when
9756 we are computing the size of a variable-size array. */
9758 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9759 && count
< HOST_BITS_PER_WIDE_INT
9760 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9761 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9762 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9764 varop
= XEXP (varop
, 0);
9767 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9768 && count
< HOST_BITS_PER_WIDE_INT
9769 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9770 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9772 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9773 & nonzero_bits (XEXP (varop
, 1),
9776 varop
= XEXP (varop
, 1);
9780 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9782 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9783 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9785 GEN_INT (count
))) != 0
9786 && GET_CODE (new) == CONST_INT
9787 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9788 INTVAL (new), result_mode
, &complement_p
))
9790 varop
= XEXP (varop
, 0);
9796 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9797 with C the size of VAROP - 1 and the shift is logical if
9798 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9799 we have a (gt X 0) operation. If the shift is arithmetic with
9800 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9801 we have a (neg (gt X 0)) operation. */
9803 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9804 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9805 && count
== (unsigned int)
9806 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9807 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9808 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9809 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9811 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9814 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9817 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9818 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9825 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9826 if the truncate does not affect the value. */
9827 if (code
== LSHIFTRT
9828 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9829 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9830 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9831 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9832 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9834 rtx varop_inner
= XEXP (varop
, 0);
9837 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9838 XEXP (varop_inner
, 0),
9840 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9841 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9854 /* We need to determine what mode to do the shift in. If the shift is
9855 a right shift or ROTATE, we must always do it in the mode it was
9856 originally done in. Otherwise, we can do it in MODE, the widest mode
9857 encountered. The code we care about is that of the shift that will
9858 actually be done, not the shift that was originally requested. */
9860 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9861 ? result_mode
: mode
);
9863 /* We have now finished analyzing the shift. The result should be
9864 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9865 OUTER_OP is non-NIL, it is an operation that needs to be applied
9866 to the result of the shift. OUTER_CONST is the relevant constant,
9867 but we must turn off all bits turned off in the shift.
9869 If we were passed a value for X, see if we can use any pieces of
9870 it. If not, make new rtx. */
9872 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9873 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9874 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9875 const_rtx
= XEXP (x
, 1);
9877 const_rtx
= GEN_INT (count
);
9879 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9880 && GET_MODE (XEXP (x
, 0)) == shift_mode
9881 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9882 varop
= XEXP (x
, 0);
9883 else if (GET_MODE (varop
) != shift_mode
)
9884 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9886 /* If we can't make the SUBREG, try to return what we were given. */
9887 if (GET_CODE (varop
) == CLOBBER
)
9888 return x
? x
: varop
;
9890 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9894 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9896 /* If we have an outer operation and we just made a shift, it is
9897 possible that we could have simplified the shift were it not
9898 for the outer operation. So try to do the simplification
9901 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9902 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9903 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9904 INTVAL (XEXP (x
, 1)));
9906 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9907 turn off all the bits that the shift would have turned off. */
9908 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9909 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9910 GET_MODE_MASK (result_mode
) >> orig_count
);
9912 /* Do the remainder of the processing in RESULT_MODE. */
9913 x
= gen_lowpart_for_combine (result_mode
, x
);
9915 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9918 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9920 if (outer_op
!= NIL
)
9922 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9923 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9925 if (outer_op
== AND
)
9926 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9927 else if (outer_op
== SET
)
9928 /* This means that we have determined that the result is
9929 equivalent to a constant. This should be rare. */
9930 x
= GEN_INT (outer_const
);
9931 else if (GET_RTX_CLASS (outer_op
) == '1')
9932 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9934 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9940 /* Like recog, but we receive the address of a pointer to a new pattern.
9941 We try to match the rtx that the pointer points to.
9942 If that fails, we may try to modify or replace the pattern,
9943 storing the replacement into the same pointer object.
9945 Modifications include deletion or addition of CLOBBERs.
9947 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9948 the CLOBBERs are placed.
9950 The value is the final insn code from the pattern ultimately matched,
9954 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9957 int insn_code_number
;
9958 int num_clobbers_to_add
= 0;
9963 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9964 we use to indicate that something didn't match. If we find such a
9965 thing, force rejection. */
9966 if (GET_CODE (pat
) == PARALLEL
)
9967 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9968 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9969 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9972 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9973 instruction for pattern recognition. */
9974 dummy_insn
= shallow_copy_rtx (insn
);
9975 PATTERN (dummy_insn
) = pat
;
9976 REG_NOTES (dummy_insn
) = 0;
9978 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9980 /* If it isn't, there is the possibility that we previously had an insn
9981 that clobbered some register as a side effect, but the combined
9982 insn doesn't need to do that. So try once more without the clobbers
9983 unless this represents an ASM insn. */
9985 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9986 && GET_CODE (pat
) == PARALLEL
)
9990 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9991 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9994 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9998 SUBST_INT (XVECLEN (pat
, 0), pos
);
10001 pat
= XVECEXP (pat
, 0, 0);
10003 PATTERN (dummy_insn
) = pat
;
10004 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
10007 /* Recognize all noop sets, these will be killed by followup pass. */
10008 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10009 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10011 /* If we had any clobbers to add, make a new pattern than contains
10012 them. Then check to make sure that all of them are dead. */
10013 if (num_clobbers_to_add
)
10015 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10016 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10017 ? (XVECLEN (pat
, 0)
10018 + num_clobbers_to_add
)
10019 : num_clobbers_to_add
+ 1));
10021 if (GET_CODE (pat
) == PARALLEL
)
10022 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10023 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10025 XVECEXP (newpat
, 0, 0) = pat
;
10027 add_clobbers (newpat
, insn_code_number
);
10029 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10030 i
< XVECLEN (newpat
, 0); i
++)
10032 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
10033 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10035 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
10036 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10044 return insn_code_number
;
10047 /* Like gen_lowpart but for use by combine. In combine it is not possible
10048 to create any new pseudoregs. However, it is safe to create
10049 invalid memory addresses, because combine will try to recognize
10050 them and all they will do is make the combine attempt fail.
10052 If for some reason this cannot do its job, an rtx
10053 (clobber (const_int 0)) is returned.
10054 An insn containing that will not be recognized. */
10059 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
10063 if (GET_MODE (x
) == mode
)
10066 /* Return identity if this is a CONST or symbolic
10069 && (GET_CODE (x
) == CONST
10070 || GET_CODE (x
) == SYMBOL_REF
10071 || GET_CODE (x
) == LABEL_REF
))
10074 /* We can only support MODE being wider than a word if X is a
10075 constant integer or has a mode the same size. */
10077 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10078 && ! ((GET_MODE (x
) == VOIDmode
10079 && (GET_CODE (x
) == CONST_INT
10080 || GET_CODE (x
) == CONST_DOUBLE
))
10081 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10082 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10084 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10085 won't know what to do. So we will strip off the SUBREG here and
10086 process normally. */
10087 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10089 x
= SUBREG_REG (x
);
10090 if (GET_MODE (x
) == mode
)
10094 result
= gen_lowpart_common (mode
, x
);
10095 #ifdef CANNOT_CHANGE_MODE_CLASS
10097 && GET_CODE (result
) == SUBREG
10098 && GET_CODE (SUBREG_REG (result
)) == REG
10099 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10100 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10102 + GET_MODE (result
));
10108 if (GET_CODE (x
) == MEM
)
10112 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10114 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10115 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10117 /* If we want to refer to something bigger than the original memref,
10118 generate a perverse subreg instead. That will force a reload
10119 of the original memref X. */
10120 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10121 return gen_rtx_SUBREG (mode
, x
, 0);
10123 if (WORDS_BIG_ENDIAN
)
10124 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10125 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10127 if (BYTES_BIG_ENDIAN
)
10129 /* Adjust the address so that the address-after-the-data is
10131 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10132 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10135 return adjust_address_nv (x
, mode
, offset
);
10138 /* If X is a comparison operator, rewrite it in a new mode. This
10139 probably won't match, but may allow further simplifications. */
10140 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10141 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10143 /* If we couldn't simplify X any other way, just enclose it in a
10144 SUBREG. Normally, this SUBREG won't match, but some patterns may
10145 include an explicit SUBREG or we may simplify it further in combine. */
10150 enum machine_mode sub_mode
= GET_MODE (x
);
10152 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10153 if (sub_mode
== VOIDmode
)
10155 sub_mode
= int_mode_for_mode (mode
);
10156 x
= gen_lowpart_common (sub_mode
, x
);
10158 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10160 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10163 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10167 /* These routines make binary and unary operations by first seeing if they
10168 fold; if not, a new expression is allocated. */
10171 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10176 if (GET_CODE (op0
) == CLOBBER
)
10178 else if (GET_CODE (op1
) == CLOBBER
)
10181 if (GET_RTX_CLASS (code
) == 'c'
10182 && swap_commutative_operands_p (op0
, op1
))
10183 tem
= op0
, op0
= op1
, op1
= tem
;
10185 if (GET_RTX_CLASS (code
) == '<')
10187 enum machine_mode op_mode
= GET_MODE (op0
);
10189 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10190 just (REL_OP X Y). */
10191 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10193 op1
= XEXP (op0
, 1);
10194 op0
= XEXP (op0
, 0);
10195 op_mode
= GET_MODE (op0
);
10198 if (op_mode
== VOIDmode
)
10199 op_mode
= GET_MODE (op1
);
10200 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10203 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10208 /* Put complex operands first and constants second. */
10209 if (GET_RTX_CLASS (code
) == 'c'
10210 && swap_commutative_operands_p (op0
, op1
))
10211 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10213 /* If we are turning off bits already known off in OP0, we need not do
10215 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10216 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10217 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10220 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10223 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10224 comparison code that will be tested.
10226 The result is a possibly different comparison code to use. *POP0 and
10227 *POP1 may be updated.
10229 It is possible that we might detect that a comparison is either always
10230 true or always false. However, we do not perform general constant
10231 folding in combine, so this knowledge isn't useful. Such tautologies
10232 should have been detected earlier. Hence we ignore all such cases. */
10234 static enum rtx_code
10235 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10241 enum machine_mode mode
, tmode
;
10243 /* Try a few ways of applying the same transformation to both operands. */
10246 #ifndef WORD_REGISTER_OPERATIONS
10247 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10248 so check specially. */
10249 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10250 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10251 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10252 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10253 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10254 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10255 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10256 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10257 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10258 && XEXP (op0
, 1) == XEXP (op1
, 1)
10259 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10260 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10261 && (INTVAL (XEXP (op0
, 1))
10262 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10263 - (GET_MODE_BITSIZE
10264 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10266 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10267 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10271 /* If both operands are the same constant shift, see if we can ignore the
10272 shift. We can if the shift is a rotate or if the bits shifted out of
10273 this shift are known to be zero for both inputs and if the type of
10274 comparison is compatible with the shift. */
10275 if (GET_CODE (op0
) == GET_CODE (op1
)
10276 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10277 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10278 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10279 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10280 || (GET_CODE (op0
) == ASHIFTRT
10281 && (code
!= GTU
&& code
!= LTU
10282 && code
!= GEU
&& code
!= LEU
)))
10283 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10284 && INTVAL (XEXP (op0
, 1)) >= 0
10285 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10286 && XEXP (op0
, 1) == XEXP (op1
, 1))
10288 enum machine_mode mode
= GET_MODE (op0
);
10289 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10290 int shift_count
= INTVAL (XEXP (op0
, 1));
10292 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10293 mask
&= (mask
>> shift_count
) << shift_count
;
10294 else if (GET_CODE (op0
) == ASHIFT
)
10295 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10297 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10298 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10299 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10304 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10305 SUBREGs are of the same mode, and, in both cases, the AND would
10306 be redundant if the comparison was done in the narrower mode,
10307 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10308 and the operand's possibly nonzero bits are 0xffffff01; in that case
10309 if we only care about QImode, we don't need the AND). This case
10310 occurs if the output mode of an scc insn is not SImode and
10311 STORE_FLAG_VALUE == 1 (e.g., the 386).
10313 Similarly, check for a case where the AND's are ZERO_EXTEND
10314 operations from some narrower mode even though a SUBREG is not
10317 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10318 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10319 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10321 rtx inner_op0
= XEXP (op0
, 0);
10322 rtx inner_op1
= XEXP (op1
, 0);
10323 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10324 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10327 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10328 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10329 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10330 && (GET_MODE (SUBREG_REG (inner_op0
))
10331 == GET_MODE (SUBREG_REG (inner_op1
)))
10332 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10333 <= HOST_BITS_PER_WIDE_INT
)
10334 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10335 GET_MODE (SUBREG_REG (inner_op0
)))))
10336 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10337 GET_MODE (SUBREG_REG (inner_op1
))))))
10339 op0
= SUBREG_REG (inner_op0
);
10340 op1
= SUBREG_REG (inner_op1
);
10342 /* The resulting comparison is always unsigned since we masked
10343 off the original sign bit. */
10344 code
= unsigned_condition (code
);
10350 for (tmode
= GET_CLASS_NARROWEST_MODE
10351 (GET_MODE_CLASS (GET_MODE (op0
)));
10352 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10353 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10355 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10356 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10357 code
= unsigned_condition (code
);
10366 /* If both operands are NOT, we can strip off the outer operation
10367 and adjust the comparison code for swapped operands; similarly for
10368 NEG, except that this must be an equality comparison. */
10369 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10370 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10371 && (code
== EQ
|| code
== NE
)))
10372 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10378 /* If the first operand is a constant, swap the operands and adjust the
10379 comparison code appropriately, but don't do this if the second operand
10380 is already a constant integer. */
10381 if (swap_commutative_operands_p (op0
, op1
))
10383 tem
= op0
, op0
= op1
, op1
= tem
;
10384 code
= swap_condition (code
);
10387 /* We now enter a loop during which we will try to simplify the comparison.
10388 For the most part, we only are concerned with comparisons with zero,
10389 but some things may really be comparisons with zero but not start
10390 out looking that way. */
10392 while (GET_CODE (op1
) == CONST_INT
)
10394 enum machine_mode mode
= GET_MODE (op0
);
10395 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10396 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10397 int equality_comparison_p
;
10398 int sign_bit_comparison_p
;
10399 int unsigned_comparison_p
;
10400 HOST_WIDE_INT const_op
;
10402 /* We only want to handle integral modes. This catches VOIDmode,
10403 CCmode, and the floating-point modes. An exception is that we
10404 can handle VOIDmode if OP0 is a COMPARE or a comparison
10407 if (GET_MODE_CLASS (mode
) != MODE_INT
10408 && ! (mode
== VOIDmode
10409 && (GET_CODE (op0
) == COMPARE
10410 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10413 /* Get the constant we are comparing against and turn off all bits
10414 not on in our mode. */
10415 const_op
= INTVAL (op1
);
10416 if (mode
!= VOIDmode
)
10417 const_op
= trunc_int_for_mode (const_op
, mode
);
10418 op1
= GEN_INT (const_op
);
10420 /* If we are comparing against a constant power of two and the value
10421 being compared can only have that single bit nonzero (e.g., it was
10422 `and'ed with that bit), we can replace this with a comparison
10425 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10426 || code
== LT
|| code
== LTU
)
10427 && mode_width
<= HOST_BITS_PER_WIDE_INT
10428 && exact_log2 (const_op
) >= 0
10429 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10431 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10432 op1
= const0_rtx
, const_op
= 0;
10435 /* Similarly, if we are comparing a value known to be either -1 or
10436 0 with -1, change it to the opposite comparison against zero. */
10439 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10440 || code
== GEU
|| code
== LTU
)
10441 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10443 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10444 op1
= const0_rtx
, const_op
= 0;
10447 /* Do some canonicalizations based on the comparison code. We prefer
10448 comparisons against zero and then prefer equality comparisons.
10449 If we can reduce the size of a constant, we will do that too. */
10454 /* < C is equivalent to <= (C - 1) */
10458 op1
= GEN_INT (const_op
);
10460 /* ... fall through to LE case below. */
10466 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10470 op1
= GEN_INT (const_op
);
10474 /* If we are doing a <= 0 comparison on a value known to have
10475 a zero sign bit, we can replace this with == 0. */
10476 else if (const_op
== 0
10477 && mode_width
<= HOST_BITS_PER_WIDE_INT
10478 && (nonzero_bits (op0
, mode
)
10479 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10484 /* >= C is equivalent to > (C - 1). */
10488 op1
= GEN_INT (const_op
);
10490 /* ... fall through to GT below. */
10496 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10500 op1
= GEN_INT (const_op
);
10504 /* If we are doing a > 0 comparison on a value known to have
10505 a zero sign bit, we can replace this with != 0. */
10506 else if (const_op
== 0
10507 && mode_width
<= HOST_BITS_PER_WIDE_INT
10508 && (nonzero_bits (op0
, mode
)
10509 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10514 /* < C is equivalent to <= (C - 1). */
10518 op1
= GEN_INT (const_op
);
10520 /* ... fall through ... */
10523 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10524 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10525 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10527 const_op
= 0, op1
= const0_rtx
;
10535 /* unsigned <= 0 is equivalent to == 0 */
10539 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10540 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10541 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10543 const_op
= 0, op1
= const0_rtx
;
10549 /* >= C is equivalent to < (C - 1). */
10553 op1
= GEN_INT (const_op
);
10555 /* ... fall through ... */
10558 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10559 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10560 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10562 const_op
= 0, op1
= const0_rtx
;
10570 /* unsigned > 0 is equivalent to != 0 */
10574 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10575 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10576 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10578 const_op
= 0, op1
= const0_rtx
;
10587 /* Compute some predicates to simplify code below. */
10589 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10590 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10591 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10594 /* If this is a sign bit comparison and we can do arithmetic in
10595 MODE, say that we will only be needing the sign bit of OP0. */
10596 if (sign_bit_comparison_p
10597 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10598 op0
= force_to_mode (op0
, mode
,
10600 << (GET_MODE_BITSIZE (mode
) - 1)),
10603 /* Now try cases based on the opcode of OP0. If none of the cases
10604 does a "continue", we exit this loop immediately after the
10607 switch (GET_CODE (op0
))
10610 /* If we are extracting a single bit from a variable position in
10611 a constant that has only a single bit set and are comparing it
10612 with zero, we can convert this into an equality comparison
10613 between the position and the location of the single bit. */
10615 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10616 && XEXP (op0
, 1) == const1_rtx
10617 && equality_comparison_p
&& const_op
== 0
10618 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10620 if (BITS_BIG_ENDIAN
)
10622 enum machine_mode new_mode
10623 = mode_for_extraction (EP_extzv
, 1);
10624 if (new_mode
== MAX_MACHINE_MODE
)
10625 i
= BITS_PER_WORD
- 1 - i
;
10629 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10633 op0
= XEXP (op0
, 2);
10637 /* Result is nonzero iff shift count is equal to I. */
10638 code
= reverse_condition (code
);
10642 /* ... fall through ... */
10645 tem
= expand_compound_operation (op0
);
10654 /* If testing for equality, we can take the NOT of the constant. */
10655 if (equality_comparison_p
10656 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10658 op0
= XEXP (op0
, 0);
10663 /* If just looking at the sign bit, reverse the sense of the
10665 if (sign_bit_comparison_p
)
10667 op0
= XEXP (op0
, 0);
10668 code
= (code
== GE
? LT
: GE
);
10674 /* If testing for equality, we can take the NEG of the constant. */
10675 if (equality_comparison_p
10676 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10678 op0
= XEXP (op0
, 0);
10683 /* The remaining cases only apply to comparisons with zero. */
10687 /* When X is ABS or is known positive,
10688 (neg X) is < 0 if and only if X != 0. */
10690 if (sign_bit_comparison_p
10691 && (GET_CODE (XEXP (op0
, 0)) == ABS
10692 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10693 && (nonzero_bits (XEXP (op0
, 0), mode
)
10694 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10696 op0
= XEXP (op0
, 0);
10697 code
= (code
== LT
? NE
: EQ
);
10701 /* If we have NEG of something whose two high-order bits are the
10702 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10703 if (num_sign_bit_copies (op0
, mode
) >= 2)
10705 op0
= XEXP (op0
, 0);
10706 code
= swap_condition (code
);
10712 /* If we are testing equality and our count is a constant, we
10713 can perform the inverse operation on our RHS. */
10714 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10715 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10716 op1
, XEXP (op0
, 1))) != 0)
10718 op0
= XEXP (op0
, 0);
10723 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10724 a particular bit. Convert it to an AND of a constant of that
10725 bit. This will be converted into a ZERO_EXTRACT. */
10726 if (const_op
== 0 && sign_bit_comparison_p
10727 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10728 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10730 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10733 - INTVAL (XEXP (op0
, 1)))));
10734 code
= (code
== LT
? NE
: EQ
);
10738 /* Fall through. */
10741 /* ABS is ignorable inside an equality comparison with zero. */
10742 if (const_op
== 0 && equality_comparison_p
)
10744 op0
= XEXP (op0
, 0);
10750 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10751 to (compare FOO CONST) if CONST fits in FOO's mode and we
10752 are either testing inequality or have an unsigned comparison
10753 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10754 if (! unsigned_comparison_p
10755 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10756 <= HOST_BITS_PER_WIDE_INT
)
10757 && ((unsigned HOST_WIDE_INT
) const_op
10758 < (((unsigned HOST_WIDE_INT
) 1
10759 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10761 op0
= XEXP (op0
, 0);
10767 /* Check for the case where we are comparing A - C1 with C2,
10768 both constants are smaller than 1/2 the maximum positive
10769 value in MODE, and the comparison is equality or unsigned.
10770 In that case, if A is either zero-extended to MODE or has
10771 sufficient sign bits so that the high-order bit in MODE
10772 is a copy of the sign in the inner mode, we can prove that it is
10773 safe to do the operation in the wider mode. This simplifies
10774 many range checks. */
10776 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10777 && subreg_lowpart_p (op0
)
10778 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10779 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10780 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10781 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10782 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10783 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10784 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10785 GET_MODE (SUBREG_REG (op0
)))
10786 & ~GET_MODE_MASK (mode
))
10787 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10788 GET_MODE (SUBREG_REG (op0
)))
10790 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10791 - GET_MODE_BITSIZE (mode
)))))
10793 op0
= SUBREG_REG (op0
);
10797 /* If the inner mode is narrower and we are extracting the low part,
10798 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10799 if (subreg_lowpart_p (op0
)
10800 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10801 /* Fall through */ ;
10805 /* ... fall through ... */
10808 if ((unsigned_comparison_p
|| equality_comparison_p
)
10809 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10810 <= HOST_BITS_PER_WIDE_INT
)
10811 && ((unsigned HOST_WIDE_INT
) const_op
10812 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10814 op0
= XEXP (op0
, 0);
10820 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10821 this for equality comparisons due to pathological cases involving
10823 if (equality_comparison_p
10824 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10825 op1
, XEXP (op0
, 1))))
10827 op0
= XEXP (op0
, 0);
10832 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10833 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10834 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10836 op0
= XEXP (XEXP (op0
, 0), 0);
10837 code
= (code
== LT
? EQ
: NE
);
10843 /* We used to optimize signed comparisons against zero, but that
10844 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10845 arrive here as equality comparisons, or (GEU, LTU) are
10846 optimized away. No need to special-case them. */
10848 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10849 (eq B (minus A C)), whichever simplifies. We can only do
10850 this for equality comparisons due to pathological cases involving
10852 if (equality_comparison_p
10853 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10854 XEXP (op0
, 1), op1
)))
10856 op0
= XEXP (op0
, 0);
10861 if (equality_comparison_p
10862 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10863 XEXP (op0
, 0), op1
)))
10865 op0
= XEXP (op0
, 1);
10870 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10871 of bits in X minus 1, is one iff X > 0. */
10872 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10873 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10874 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10876 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10878 op0
= XEXP (op0
, 1);
10879 code
= (code
== GE
? LE
: GT
);
10885 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10886 if C is zero or B is a constant. */
10887 if (equality_comparison_p
10888 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10889 XEXP (op0
, 1), op1
)))
10891 op0
= XEXP (op0
, 0);
10898 case UNEQ
: case LTGT
:
10899 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10900 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10901 case UNORDERED
: case ORDERED
:
10902 /* We can't do anything if OP0 is a condition code value, rather
10903 than an actual data value. */
10905 || CC0_P (XEXP (op0
, 0))
10906 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10909 /* Get the two operands being compared. */
10910 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10911 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10913 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10915 /* Check for the cases where we simply want the result of the
10916 earlier test or the opposite of that result. */
10917 if (code
== NE
|| code
== EQ
10918 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10919 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10920 && (STORE_FLAG_VALUE
10921 & (((HOST_WIDE_INT
) 1
10922 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10923 && (code
== LT
|| code
== GE
)))
10925 enum rtx_code new_code
;
10926 if (code
== LT
|| code
== NE
)
10927 new_code
= GET_CODE (op0
);
10929 new_code
= combine_reversed_comparison_code (op0
);
10931 if (new_code
!= UNKNOWN
)
10942 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10944 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10945 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10946 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10948 op0
= XEXP (op0
, 1);
10949 code
= (code
== GE
? GT
: LE
);
10955 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10956 will be converted to a ZERO_EXTRACT later. */
10957 if (const_op
== 0 && equality_comparison_p
10958 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10959 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10961 op0
= simplify_and_const_int
10962 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10964 XEXP (XEXP (op0
, 0), 1)),
10965 (HOST_WIDE_INT
) 1);
10969 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10970 zero and X is a comparison and C1 and C2 describe only bits set
10971 in STORE_FLAG_VALUE, we can compare with X. */
10972 if (const_op
== 0 && equality_comparison_p
10973 && mode_width
<= HOST_BITS_PER_WIDE_INT
10974 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10975 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10976 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10977 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10978 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10980 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10981 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10982 if ((~STORE_FLAG_VALUE
& mask
) == 0
10983 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10984 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10985 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10987 op0
= XEXP (XEXP (op0
, 0), 0);
10992 /* If we are doing an equality comparison of an AND of a bit equal
10993 to the sign bit, replace this with a LT or GE comparison of
10994 the underlying value. */
10995 if (equality_comparison_p
10997 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10998 && mode_width
<= HOST_BITS_PER_WIDE_INT
10999 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11000 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11002 op0
= XEXP (op0
, 0);
11003 code
= (code
== EQ
? GE
: LT
);
11007 /* If this AND operation is really a ZERO_EXTEND from a narrower
11008 mode, the constant fits within that mode, and this is either an
11009 equality or unsigned comparison, try to do this comparison in
11010 the narrower mode. */
11011 if ((equality_comparison_p
|| unsigned_comparison_p
)
11012 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11013 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11014 & GET_MODE_MASK (mode
))
11016 && const_op
>> i
== 0
11017 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
11019 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
11023 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11024 fits in both M1 and M2 and the SUBREG is either paradoxical
11025 or represents the low part, permute the SUBREG and the AND
11027 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11029 unsigned HOST_WIDE_INT c1
;
11030 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11031 /* Require an integral mode, to avoid creating something like
11033 if (SCALAR_INT_MODE_P (tmode
)
11034 /* It is unsafe to commute the AND into the SUBREG if the
11035 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11036 not defined. As originally written the upper bits
11037 have a defined value due to the AND operation.
11038 However, if we commute the AND inside the SUBREG then
11039 they no longer have defined values and the meaning of
11040 the code has been changed. */
11042 #ifdef WORD_REGISTER_OPERATIONS
11043 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11044 && mode_width
<= BITS_PER_WORD
)
11046 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11047 && subreg_lowpart_p (XEXP (op0
, 0))))
11048 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11049 && mode_width
<= HOST_BITS_PER_WIDE_INT
11050 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11051 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11052 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11054 && c1
!= GET_MODE_MASK (tmode
))
11056 op0
= gen_binary (AND
, tmode
,
11057 SUBREG_REG (XEXP (op0
, 0)),
11058 gen_int_mode (c1
, tmode
));
11059 op0
= gen_lowpart_for_combine (mode
, op0
);
11064 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11065 if (const_op
== 0 && equality_comparison_p
11066 && XEXP (op0
, 1) == const1_rtx
11067 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11069 op0
= simplify_and_const_int
11070 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11071 code
= (code
== NE
? EQ
: NE
);
11075 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11076 (eq (and (lshiftrt X) 1) 0). */
11077 if (const_op
== 0 && equality_comparison_p
11078 && XEXP (op0
, 1) == const1_rtx
11079 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11080 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
11082 op0
= simplify_and_const_int
11084 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
11085 XEXP (XEXP (op0
, 0), 1)),
11086 (HOST_WIDE_INT
) 1);
11087 code
= (code
== NE
? EQ
: NE
);
11093 /* If we have (compare (ashift FOO N) (const_int C)) and
11094 the high order N bits of FOO (N+1 if an inequality comparison)
11095 are known to be zero, we can do this by comparing FOO with C
11096 shifted right N bits so long as the low-order N bits of C are
11098 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11099 && INTVAL (XEXP (op0
, 1)) >= 0
11100 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11101 < HOST_BITS_PER_WIDE_INT
)
11103 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11104 && mode_width
<= HOST_BITS_PER_WIDE_INT
11105 && (nonzero_bits (XEXP (op0
, 0), mode
)
11106 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11107 + ! equality_comparison_p
))) == 0)
11109 /* We must perform a logical shift, not an arithmetic one,
11110 as we want the top N bits of C to be zero. */
11111 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11113 temp
>>= INTVAL (XEXP (op0
, 1));
11114 op1
= gen_int_mode (temp
, mode
);
11115 op0
= XEXP (op0
, 0);
11119 /* If we are doing a sign bit comparison, it means we are testing
11120 a particular bit. Convert it to the appropriate AND. */
11121 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11122 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11124 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11127 - INTVAL (XEXP (op0
, 1)))));
11128 code
= (code
== LT
? NE
: EQ
);
11132 /* If this an equality comparison with zero and we are shifting
11133 the low bit to the sign bit, we can convert this to an AND of the
11135 if (const_op
== 0 && equality_comparison_p
11136 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11137 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11140 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11141 (HOST_WIDE_INT
) 1);
11147 /* If this is an equality comparison with zero, we can do this
11148 as a logical shift, which might be much simpler. */
11149 if (equality_comparison_p
&& const_op
== 0
11150 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11152 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11154 INTVAL (XEXP (op0
, 1)));
11158 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11159 do the comparison in a narrower mode. */
11160 if (! unsigned_comparison_p
11161 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11162 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11163 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11164 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11165 MODE_INT
, 1)) != BLKmode
11166 && (((unsigned HOST_WIDE_INT
) const_op
11167 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11168 <= GET_MODE_MASK (tmode
)))
11170 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11174 /* Likewise if OP0 is a PLUS of a sign extension with a
11175 constant, which is usually represented with the PLUS
11176 between the shifts. */
11177 if (! unsigned_comparison_p
11178 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11179 && GET_CODE (XEXP (op0
, 0)) == PLUS
11180 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11181 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11182 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11183 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11184 MODE_INT
, 1)) != BLKmode
11185 && (((unsigned HOST_WIDE_INT
) const_op
11186 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11187 <= GET_MODE_MASK (tmode
)))
11189 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11190 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11191 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11194 op0
= gen_binary (PLUS
, tmode
,
11195 gen_lowpart_for_combine (tmode
, inner
),
11200 /* ... fall through ... */
11202 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11203 the low order N bits of FOO are known to be zero, we can do this
11204 by comparing FOO with C shifted left N bits so long as no
11205 overflow occurs. */
11206 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11207 && INTVAL (XEXP (op0
, 1)) >= 0
11208 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11209 && mode_width
<= HOST_BITS_PER_WIDE_INT
11210 && (nonzero_bits (XEXP (op0
, 0), mode
)
11211 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11212 && (((unsigned HOST_WIDE_INT
) const_op
11213 + (GET_CODE (op0
) != LSHIFTRT
11214 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11217 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11219 /* If the shift was logical, then we must make the condition
11221 if (GET_CODE (op0
) == LSHIFTRT
)
11222 code
= unsigned_condition (code
);
11224 const_op
<<= INTVAL (XEXP (op0
, 1));
11225 op1
= GEN_INT (const_op
);
11226 op0
= XEXP (op0
, 0);
11230 /* If we are using this shift to extract just the sign bit, we
11231 can replace this with an LT or GE comparison. */
11233 && (equality_comparison_p
|| sign_bit_comparison_p
)
11234 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11235 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11238 op0
= XEXP (op0
, 0);
11239 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11251 /* Now make any compound operations involved in this comparison. Then,
11252 check for an outmost SUBREG on OP0 that is not doing anything or is
11253 paradoxical. The latter transformation must only be performed when
11254 it is known that the "extra" bits will be the same in op0 and op1 or
11255 that they don't matter. There are three cases to consider:
11257 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11258 care bits and we can assume they have any convenient value. So
11259 making the transformation is safe.
11261 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11262 In this case the upper bits of op0 are undefined. We should not make
11263 the simplification in that case as we do not know the contents of
11266 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11267 NIL. In that case we know those bits are zeros or ones. We must
11268 also be sure that they are the same as the upper bits of op1.
11270 We can never remove a SUBREG for a non-equality comparison because
11271 the sign bit is in a different place in the underlying object. */
11273 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11274 op1
= make_compound_operation (op1
, SET
);
11276 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11277 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11279 && GET_CODE (SUBREG_REG (op0
)) == REG
11280 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11281 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11282 && (code
== NE
|| code
== EQ
))
11284 if (GET_MODE_SIZE (GET_MODE (op0
))
11285 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11287 op0
= SUBREG_REG (op0
);
11288 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11290 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11291 <= HOST_BITS_PER_WIDE_INT
)
11292 && (nonzero_bits (SUBREG_REG (op0
),
11293 GET_MODE (SUBREG_REG (op0
)))
11294 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11296 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11298 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11299 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11300 op0
= SUBREG_REG (op0
), op1
= tem
;
11304 /* We now do the opposite procedure: Some machines don't have compare
11305 insns in all modes. If OP0's mode is an integer mode smaller than a
11306 word and we can't do a compare in that mode, see if there is a larger
11307 mode for which we can do the compare. There are a number of cases in
11308 which we can use the wider mode. */
11310 mode
= GET_MODE (op0
);
11311 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11312 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11313 && ! have_insn_for (COMPARE
, mode
))
11314 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11316 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11317 tmode
= GET_MODE_WIDER_MODE (tmode
))
11318 if (have_insn_for (COMPARE
, tmode
))
11322 /* If the only nonzero bits in OP0 and OP1 are those in the
11323 narrower mode and this is an equality or unsigned comparison,
11324 we can use the wider mode. Similarly for sign-extended
11325 values, in which case it is true for all comparisons. */
11326 zero_extended
= ((code
== EQ
|| code
== NE
11327 || code
== GEU
|| code
== GTU
11328 || code
== LEU
|| code
== LTU
)
11329 && (nonzero_bits (op0
, tmode
)
11330 & ~GET_MODE_MASK (mode
)) == 0
11331 && ((GET_CODE (op1
) == CONST_INT
11332 || (nonzero_bits (op1
, tmode
)
11333 & ~GET_MODE_MASK (mode
)) == 0)));
11336 || ((num_sign_bit_copies (op0
, tmode
)
11337 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11338 - GET_MODE_BITSIZE (mode
)))
11339 && (num_sign_bit_copies (op1
, tmode
)
11340 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11341 - GET_MODE_BITSIZE (mode
)))))
11343 /* If OP0 is an AND and we don't have an AND in MODE either,
11344 make a new AND in the proper mode. */
11345 if (GET_CODE (op0
) == AND
11346 && !have_insn_for (AND
, mode
))
11347 op0
= gen_binary (AND
, tmode
,
11348 gen_lowpart_for_combine (tmode
,
11350 gen_lowpart_for_combine (tmode
,
11353 op0
= gen_lowpart_for_combine (tmode
, op0
);
11354 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11355 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11356 op1
= gen_lowpart_for_combine (tmode
, op1
);
11360 /* If this is a test for negative, we can make an explicit
11361 test of the sign bit. */
11363 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11364 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11366 op0
= gen_binary (AND
, tmode
,
11367 gen_lowpart_for_combine (tmode
, op0
),
11368 GEN_INT ((HOST_WIDE_INT
) 1
11369 << (GET_MODE_BITSIZE (mode
) - 1)));
11370 code
= (code
== LT
) ? NE
: EQ
;
11375 #ifdef CANONICALIZE_COMPARISON
11376 /* If this machine only supports a subset of valid comparisons, see if we
11377 can convert an unsupported one into a supported one. */
11378 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11387 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11388 searching backward. */
11389 static enum rtx_code
11390 combine_reversed_comparison_code (rtx exp
)
11392 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11395 if (code1
!= UNKNOWN
11396 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11398 /* Otherwise try and find where the condition codes were last set and
11400 x
= get_last_value (XEXP (exp
, 0));
11401 if (!x
|| GET_CODE (x
) != COMPARE
)
11403 return reversed_comparison_code_parts (GET_CODE (exp
),
11404 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11407 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11408 Return NULL_RTX in case we fail to do the reversal. */
11410 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11412 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11413 if (reversed_code
== UNKNOWN
)
11416 return gen_binary (reversed_code
, mode
, op0
, op1
);
11419 /* Utility function for following routine. Called when X is part of a value
11420 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11421 for each register mentioned. Similar to mention_regs in cse.c */
11424 update_table_tick (rtx x
)
11426 enum rtx_code code
= GET_CODE (x
);
11427 const char *fmt
= GET_RTX_FORMAT (code
);
11432 unsigned int regno
= REGNO (x
);
11433 unsigned int endregno
11434 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11435 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11438 for (r
= regno
; r
< endregno
; r
++)
11439 reg_last_set_table_tick
[r
] = label_tick
;
11444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11445 /* Note that we can't have an "E" in values stored; see
11446 get_last_value_validate. */
11449 /* Check for identical subexpressions. If x contains
11450 identical subexpression we only have to traverse one of
11453 && (GET_RTX_CLASS (code
) == '2'
11454 || GET_RTX_CLASS (code
) == 'c'))
11456 /* Note that at this point x1 has already been
11458 rtx x0
= XEXP (x
, 0);
11459 rtx x1
= XEXP (x
, 1);
11461 /* If x0 and x1 are identical then there is no need to
11466 /* If x0 is identical to a subexpression of x1 then while
11467 processing x1, x0 has already been processed. Thus we
11468 are done with x. */
11469 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11470 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11471 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11474 /* If x1 is identical to a subexpression of x0 then we
11475 still have to process the rest of x0. */
11476 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11477 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11478 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11480 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11485 update_table_tick (XEXP (x
, i
));
11489 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11490 are saying that the register is clobbered and we no longer know its
11491 value. If INSN is zero, don't update reg_last_set; this is only permitted
11492 with VALUE also zero and is used to invalidate the register. */
11495 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11497 unsigned int regno
= REGNO (reg
);
11498 unsigned int endregno
11499 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11500 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11503 /* If VALUE contains REG and we have a previous value for REG, substitute
11504 the previous value. */
11505 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11509 /* Set things up so get_last_value is allowed to see anything set up to
11511 subst_low_cuid
= INSN_CUID (insn
);
11512 tem
= get_last_value (reg
);
11514 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11515 it isn't going to be useful and will take a lot of time to process,
11516 so just use the CLOBBER. */
11520 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11521 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11522 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11523 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11524 tem
= XEXP (tem
, 0);
11526 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11530 /* For each register modified, show we don't know its value, that
11531 we don't know about its bitwise content, that its value has been
11532 updated, and that we don't know the location of the death of the
11534 for (i
= regno
; i
< endregno
; i
++)
11537 reg_last_set
[i
] = insn
;
11539 reg_last_set_value
[i
] = 0;
11540 reg_last_set_mode
[i
] = 0;
11541 reg_last_set_nonzero_bits
[i
] = 0;
11542 reg_last_set_sign_bit_copies
[i
] = 0;
11543 reg_last_death
[i
] = 0;
11546 /* Mark registers that are being referenced in this value. */
11548 update_table_tick (value
);
11550 /* Now update the status of each register being set.
11551 If someone is using this register in this block, set this register
11552 to invalid since we will get confused between the two lives in this
11553 basic block. This makes using this register always invalid. In cse, we
11554 scan the table to invalidate all entries using this register, but this
11555 is too much work for us. */
11557 for (i
= regno
; i
< endregno
; i
++)
11559 reg_last_set_label
[i
] = label_tick
;
11560 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11561 reg_last_set_invalid
[i
] = 1;
11563 reg_last_set_invalid
[i
] = 0;
11566 /* The value being assigned might refer to X (like in "x++;"). In that
11567 case, we must replace it with (clobber (const_int 0)) to prevent
11569 if (value
&& ! get_last_value_validate (&value
, insn
,
11570 reg_last_set_label
[regno
], 0))
11572 value
= copy_rtx (value
);
11573 if (! get_last_value_validate (&value
, insn
,
11574 reg_last_set_label
[regno
], 1))
11578 /* For the main register being modified, update the value, the mode, the
11579 nonzero bits, and the number of sign bit copies. */
11581 reg_last_set_value
[regno
] = value
;
11585 enum machine_mode mode
= GET_MODE (reg
);
11586 subst_low_cuid
= INSN_CUID (insn
);
11587 reg_last_set_mode
[regno
] = mode
;
11588 if (GET_MODE_CLASS (mode
) == MODE_INT
11589 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11590 mode
= nonzero_bits_mode
;
11591 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11592 reg_last_set_sign_bit_copies
[regno
]
11593 = num_sign_bit_copies (value
, GET_MODE (reg
));
11597 /* Called via note_stores from record_dead_and_set_regs to handle one
11598 SET or CLOBBER in an insn. DATA is the instruction in which the
11599 set is occurring. */
11602 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11604 rtx record_dead_insn
= (rtx
) data
;
11606 if (GET_CODE (dest
) == SUBREG
)
11607 dest
= SUBREG_REG (dest
);
11609 if (GET_CODE (dest
) == REG
)
11611 /* If we are setting the whole register, we know its value. Otherwise
11612 show that we don't know the value. We can handle SUBREG in
11614 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11615 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11616 else if (GET_CODE (setter
) == SET
11617 && GET_CODE (SET_DEST (setter
)) == SUBREG
11618 && SUBREG_REG (SET_DEST (setter
)) == dest
11619 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11620 && subreg_lowpart_p (SET_DEST (setter
)))
11621 record_value_for_reg (dest
, record_dead_insn
,
11622 gen_lowpart_for_combine (GET_MODE (dest
),
11623 SET_SRC (setter
)));
11625 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11627 else if (GET_CODE (dest
) == MEM
11628 /* Ignore pushes, they clobber nothing. */
11629 && ! push_operand (dest
, GET_MODE (dest
)))
11630 mem_last_set
= INSN_CUID (record_dead_insn
);
11633 /* Update the records of when each REG was most recently set or killed
11634 for the things done by INSN. This is the last thing done in processing
11635 INSN in the combiner loop.
11637 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11638 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11639 and also the similar information mem_last_set (which insn most recently
11640 modified memory) and last_call_cuid (which insn was the most recent
11641 subroutine call). */
11644 record_dead_and_set_regs (rtx insn
)
11649 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11651 if (REG_NOTE_KIND (link
) == REG_DEAD
11652 && GET_CODE (XEXP (link
, 0)) == REG
)
11654 unsigned int regno
= REGNO (XEXP (link
, 0));
11655 unsigned int endregno
11656 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11657 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11660 for (i
= regno
; i
< endregno
; i
++)
11661 reg_last_death
[i
] = insn
;
11663 else if (REG_NOTE_KIND (link
) == REG_INC
)
11664 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11667 if (GET_CODE (insn
) == CALL_INSN
)
11669 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11670 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11672 reg_last_set_value
[i
] = 0;
11673 reg_last_set_mode
[i
] = 0;
11674 reg_last_set_nonzero_bits
[i
] = 0;
11675 reg_last_set_sign_bit_copies
[i
] = 0;
11676 reg_last_death
[i
] = 0;
11679 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11681 /* Don't bother recording what this insn does. It might set the
11682 return value register, but we can't combine into a call
11683 pattern anyway, so there's no point trying (and it may cause
11684 a crash, if e.g. we wind up asking for last_set_value of a
11685 SUBREG of the return value register). */
11689 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11692 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11693 register present in the SUBREG, so for each such SUBREG go back and
11694 adjust nonzero and sign bit information of the registers that are
11695 known to have some zero/sign bits set.
11697 This is needed because when combine blows the SUBREGs away, the
11698 information on zero/sign bits is lost and further combines can be
11699 missed because of that. */
11702 record_promoted_value (rtx insn
, rtx subreg
)
11705 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11706 enum machine_mode mode
= GET_MODE (subreg
);
11708 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11711 for (links
= LOG_LINKS (insn
); links
;)
11713 insn
= XEXP (links
, 0);
11714 set
= single_set (insn
);
11716 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11717 || REGNO (SET_DEST (set
)) != regno
11718 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11720 links
= XEXP (links
, 1);
11724 if (reg_last_set
[regno
] == insn
)
11726 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11727 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11730 if (GET_CODE (SET_SRC (set
)) == REG
)
11732 regno
= REGNO (SET_SRC (set
));
11733 links
= LOG_LINKS (insn
);
11740 /* Scan X for promoted SUBREGs. For each one found,
11741 note what it implies to the registers used in it. */
11744 check_promoted_subreg (rtx insn
, rtx x
)
11746 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11747 && GET_CODE (SUBREG_REG (x
)) == REG
)
11748 record_promoted_value (insn
, x
);
11751 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11754 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11758 check_promoted_subreg (insn
, XEXP (x
, i
));
11762 if (XVEC (x
, i
) != 0)
11763 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11764 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11770 /* Utility routine for the following function. Verify that all the registers
11771 mentioned in *LOC are valid when *LOC was part of a value set when
11772 label_tick == TICK. Return 0 if some are not.
11774 If REPLACE is nonzero, replace the invalid reference with
11775 (clobber (const_int 0)) and return 1. This replacement is useful because
11776 we often can get useful information about the form of a value (e.g., if
11777 it was produced by a shift that always produces -1 or 0) even though
11778 we don't know exactly what registers it was produced from. */
11781 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11784 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11785 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11788 if (GET_CODE (x
) == REG
)
11790 unsigned int regno
= REGNO (x
);
11791 unsigned int endregno
11792 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11793 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11796 for (j
= regno
; j
< endregno
; j
++)
11797 if (reg_last_set_invalid
[j
]
11798 /* If this is a pseudo-register that was only set once and not
11799 live at the beginning of the function, it is always valid. */
11800 || (! (regno
>= FIRST_PSEUDO_REGISTER
11801 && REG_N_SETS (regno
) == 1
11802 && (! REGNO_REG_SET_P
11803 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11804 && reg_last_set_label
[j
] > tick
))
11807 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11813 /* If this is a memory reference, make sure that there were
11814 no stores after it that might have clobbered the value. We don't
11815 have alias info, so we assume any store invalidates it. */
11816 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11817 && INSN_CUID (insn
) <= mem_last_set
)
11820 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11824 for (i
= 0; i
< len
; i
++)
11828 /* Check for identical subexpressions. If x contains
11829 identical subexpression we only have to traverse one of
11832 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11833 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11835 /* Note that at this point x0 has already been checked
11836 and found valid. */
11837 rtx x0
= XEXP (x
, 0);
11838 rtx x1
= XEXP (x
, 1);
11840 /* If x0 and x1 are identical then x is also valid. */
11844 /* If x1 is identical to a subexpression of x0 then
11845 while checking x0, x1 has already been checked. Thus
11846 it is valid and so as x. */
11847 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11848 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11849 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11852 /* If x0 is identical to a subexpression of x1 then x is
11853 valid iff the rest of x1 is valid. */
11854 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11855 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11856 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11858 get_last_value_validate (&XEXP (x1
,
11859 x0
== XEXP (x1
, 0) ? 1 : 0),
11860 insn
, tick
, replace
);
11863 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11867 /* Don't bother with these. They shouldn't occur anyway. */
11868 else if (fmt
[i
] == 'E')
11872 /* If we haven't found a reason for it to be invalid, it is valid. */
11876 /* Get the last value assigned to X, if known. Some registers
11877 in the value may be replaced with (clobber (const_int 0)) if their value
11878 is known longer known reliably. */
11881 get_last_value (rtx x
)
11883 unsigned int regno
;
11886 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11887 then convert it to the desired mode. If this is a paradoxical SUBREG,
11888 we cannot predict what values the "extra" bits might have. */
11889 if (GET_CODE (x
) == SUBREG
11890 && subreg_lowpart_p (x
)
11891 && (GET_MODE_SIZE (GET_MODE (x
))
11892 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11893 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11894 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11896 if (GET_CODE (x
) != REG
)
11900 value
= reg_last_set_value
[regno
];
11902 /* If we don't have a value, or if it isn't for this basic block and
11903 it's either a hard register, set more than once, or it's a live
11904 at the beginning of the function, return 0.
11906 Because if it's not live at the beginning of the function then the reg
11907 is always set before being used (is never used without being set).
11908 And, if it's set only once, and it's always set before use, then all
11909 uses must have the same last value, even if it's not from this basic
11913 || (reg_last_set_label
[regno
] != label_tick
11914 && (regno
< FIRST_PSEUDO_REGISTER
11915 || REG_N_SETS (regno
) != 1
11916 || (REGNO_REG_SET_P
11917 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11920 /* If the value was set in a later insn than the ones we are processing,
11921 we can't use it even if the register was only set once. */
11922 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11925 /* If the value has all its registers valid, return it. */
11926 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11927 reg_last_set_label
[regno
], 0))
11930 /* Otherwise, make a copy and replace any invalid register with
11931 (clobber (const_int 0)). If that fails for some reason, return 0. */
11933 value
= copy_rtx (value
);
11934 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11935 reg_last_set_label
[regno
], 1))
11941 /* Return nonzero if expression X refers to a REG or to memory
11942 that is set in an instruction more recent than FROM_CUID. */
11945 use_crosses_set_p (rtx x
, int from_cuid
)
11949 enum rtx_code code
= GET_CODE (x
);
11953 unsigned int regno
= REGNO (x
);
11954 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11955 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11957 #ifdef PUSH_ROUNDING
11958 /* Don't allow uses of the stack pointer to be moved,
11959 because we don't know whether the move crosses a push insn. */
11960 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11963 for (; regno
< endreg
; regno
++)
11964 if (reg_last_set
[regno
]
11965 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11970 if (code
== MEM
&& mem_last_set
> from_cuid
)
11973 fmt
= GET_RTX_FORMAT (code
);
11975 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11980 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11981 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11984 else if (fmt
[i
] == 'e'
11985 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11991 /* Define three variables used for communication between the following
11994 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11995 static int reg_dead_flag
;
11997 /* Function called via note_stores from reg_dead_at_p.
11999 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12000 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12003 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
12005 unsigned int regno
, endregno
;
12007 if (GET_CODE (dest
) != REG
)
12010 regno
= REGNO (dest
);
12011 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
12012 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
12014 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12015 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12018 /* Return nonzero if REG is known to be dead at INSN.
12020 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12021 referencing REG, it is dead. If we hit a SET referencing REG, it is
12022 live. Otherwise, see if it is live or dead at the start of the basic
12023 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12024 must be assumed to be always live. */
12027 reg_dead_at_p (rtx reg
, rtx insn
)
12032 /* Set variables for reg_dead_at_p_1. */
12033 reg_dead_regno
= REGNO (reg
);
12034 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
12035 ? HARD_REGNO_NREGS (reg_dead_regno
,
12041 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12042 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12044 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12045 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12049 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12050 beginning of function. */
12051 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12052 insn
= prev_nonnote_insn (insn
))
12054 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12056 return reg_dead_flag
== 1 ? 1 : 0;
12058 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12062 /* Get the basic block that we were in. */
12064 block
= ENTRY_BLOCK_PTR
->next_bb
;
12067 FOR_EACH_BB (block
)
12068 if (insn
== block
->head
)
12071 if (block
== EXIT_BLOCK_PTR
)
12075 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12076 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12082 /* Note hard registers in X that are used. This code is similar to
12083 that in flow.c, but much simpler since we don't care about pseudos. */
12086 mark_used_regs_combine (rtx x
)
12088 RTX_CODE code
= GET_CODE (x
);
12089 unsigned int regno
;
12102 case ADDR_DIFF_VEC
:
12105 /* CC0 must die in the insn after it is set, so we don't need to take
12106 special note of it here. */
12112 /* If we are clobbering a MEM, mark any hard registers inside the
12113 address as used. */
12114 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12115 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12120 /* A hard reg in a wide mode may really be multiple registers.
12121 If so, mark all of them just like the first. */
12122 if (regno
< FIRST_PSEUDO_REGISTER
)
12124 unsigned int endregno
, r
;
12126 /* None of this applies to the stack, frame or arg pointers. */
12127 if (regno
== STACK_POINTER_REGNUM
12128 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12129 || regno
== HARD_FRAME_POINTER_REGNUM
12131 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12132 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12134 || regno
== FRAME_POINTER_REGNUM
)
12137 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12138 for (r
= regno
; r
< endregno
; r
++)
12139 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12145 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12147 rtx testreg
= SET_DEST (x
);
12149 while (GET_CODE (testreg
) == SUBREG
12150 || GET_CODE (testreg
) == ZERO_EXTRACT
12151 || GET_CODE (testreg
) == SIGN_EXTRACT
12152 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12153 testreg
= XEXP (testreg
, 0);
12155 if (GET_CODE (testreg
) == MEM
)
12156 mark_used_regs_combine (XEXP (testreg
, 0));
12158 mark_used_regs_combine (SET_SRC (x
));
12166 /* Recursively scan the operands of this expression. */
12169 const char *fmt
= GET_RTX_FORMAT (code
);
12171 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12174 mark_used_regs_combine (XEXP (x
, i
));
12175 else if (fmt
[i
] == 'E')
12179 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12180 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12186 /* Remove register number REGNO from the dead registers list of INSN.
12188 Return the note used to record the death, if there was one. */
12191 remove_death (unsigned int regno
, rtx insn
)
12193 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12197 REG_N_DEATHS (regno
)--;
12198 remove_note (insn
, note
);
12204 /* For each register (hardware or pseudo) used within expression X, if its
12205 death is in an instruction with cuid between FROM_CUID (inclusive) and
12206 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12207 list headed by PNOTES.
12209 That said, don't move registers killed by maybe_kill_insn.
12211 This is done when X is being merged by combination into TO_INSN. These
12212 notes will then be distributed as needed. */
12215 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12220 enum rtx_code code
= GET_CODE (x
);
12224 unsigned int regno
= REGNO (x
);
12225 rtx where_dead
= reg_last_death
[regno
];
12226 rtx before_dead
, after_dead
;
12228 /* Don't move the register if it gets killed in between from and to. */
12229 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12230 && ! reg_referenced_p (x
, maybe_kill_insn
))
12233 /* WHERE_DEAD could be a USE insn made by combine, so first we
12234 make sure that we have insns with valid INSN_CUID values. */
12235 before_dead
= where_dead
;
12236 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12237 before_dead
= PREV_INSN (before_dead
);
12239 after_dead
= where_dead
;
12240 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12241 after_dead
= NEXT_INSN (after_dead
);
12243 if (before_dead
&& after_dead
12244 && INSN_CUID (before_dead
) >= from_cuid
12245 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12246 || (where_dead
!= after_dead
12247 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12249 rtx note
= remove_death (regno
, where_dead
);
12251 /* It is possible for the call above to return 0. This can occur
12252 when reg_last_death points to I2 or I1 that we combined with.
12253 In that case make a new note.
12255 We must also check for the case where X is a hard register
12256 and NOTE is a death note for a range of hard registers
12257 including X. In that case, we must put REG_DEAD notes for
12258 the remaining registers in place of NOTE. */
12260 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12261 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12262 > GET_MODE_SIZE (GET_MODE (x
))))
12264 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12265 unsigned int deadend
12266 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12267 GET_MODE (XEXP (note
, 0))));
12268 unsigned int ourend
12269 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12272 for (i
= deadregno
; i
< deadend
; i
++)
12273 if (i
< regno
|| i
>= ourend
)
12274 REG_NOTES (where_dead
)
12275 = gen_rtx_EXPR_LIST (REG_DEAD
,
12277 REG_NOTES (where_dead
));
12280 /* If we didn't find any note, or if we found a REG_DEAD note that
12281 covers only part of the given reg, and we have a multi-reg hard
12282 register, then to be safe we must check for REG_DEAD notes
12283 for each register other than the first. They could have
12284 their own REG_DEAD notes lying around. */
12285 else if ((note
== 0
12287 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12288 < GET_MODE_SIZE (GET_MODE (x
)))))
12289 && regno
< FIRST_PSEUDO_REGISTER
12290 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12292 unsigned int ourend
12293 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12294 unsigned int i
, offset
;
12298 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12302 for (i
= regno
+ offset
; i
< ourend
; i
++)
12303 move_deaths (regno_reg_rtx
[i
],
12304 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12307 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12309 XEXP (note
, 1) = *pnotes
;
12313 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12315 REG_N_DEATHS (regno
)++;
12321 else if (GET_CODE (x
) == SET
)
12323 rtx dest
= SET_DEST (x
);
12325 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12327 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12328 that accesses one word of a multi-word item, some
12329 piece of everything register in the expression is used by
12330 this insn, so remove any old death. */
12331 /* ??? So why do we test for equality of the sizes? */
12333 if (GET_CODE (dest
) == ZERO_EXTRACT
12334 || GET_CODE (dest
) == STRICT_LOW_PART
12335 || (GET_CODE (dest
) == SUBREG
12336 && (((GET_MODE_SIZE (GET_MODE (dest
))
12337 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12338 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12339 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12341 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12345 /* If this is some other SUBREG, we know it replaces the entire
12346 value, so use that as the destination. */
12347 if (GET_CODE (dest
) == SUBREG
)
12348 dest
= SUBREG_REG (dest
);
12350 /* If this is a MEM, adjust deaths of anything used in the address.
12351 For a REG (the only other possibility), the entire value is
12352 being replaced so the old value is not used in this insn. */
12354 if (GET_CODE (dest
) == MEM
)
12355 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12360 else if (GET_CODE (x
) == CLOBBER
)
12363 len
= GET_RTX_LENGTH (code
);
12364 fmt
= GET_RTX_FORMAT (code
);
12366 for (i
= 0; i
< len
; i
++)
12371 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12372 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12375 else if (fmt
[i
] == 'e')
12376 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12380 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12381 pattern of an insn. X must be a REG. */
12384 reg_bitfield_target_p (rtx x
, rtx body
)
12388 if (GET_CODE (body
) == SET
)
12390 rtx dest
= SET_DEST (body
);
12392 unsigned int regno
, tregno
, endregno
, endtregno
;
12394 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12395 target
= XEXP (dest
, 0);
12396 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12397 target
= SUBREG_REG (XEXP (dest
, 0));
12401 if (GET_CODE (target
) == SUBREG
)
12402 target
= SUBREG_REG (target
);
12404 if (GET_CODE (target
) != REG
)
12407 tregno
= REGNO (target
), regno
= REGNO (x
);
12408 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12409 return target
== x
;
12411 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12412 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12414 return endregno
> tregno
&& regno
< endtregno
;
12417 else if (GET_CODE (body
) == PARALLEL
)
12418 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12419 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12425 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12426 as appropriate. I3 and I2 are the insns resulting from the combination
12427 insns including FROM (I2 may be zero).
12429 Each note in the list is either ignored or placed on some insns, depending
12430 on the type of note. */
12433 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12435 rtx note
, next_note
;
12438 for (note
= notes
; note
; note
= next_note
)
12440 rtx place
= 0, place2
= 0;
12442 /* If this NOTE references a pseudo register, ensure it references
12443 the latest copy of that register. */
12444 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12445 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12446 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12448 next_note
= XEXP (note
, 1);
12449 switch (REG_NOTE_KIND (note
))
12453 /* Doesn't matter much where we put this, as long as it's somewhere.
12454 It is preferable to keep these notes on branches, which is most
12455 likely to be i3. */
12459 case REG_VTABLE_REF
:
12460 /* ??? Should remain with *a particular* memory load. Given the
12461 nature of vtable data, the last insn seems relatively safe. */
12465 case REG_NON_LOCAL_GOTO
:
12466 if (GET_CODE (i3
) == JUMP_INSN
)
12468 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12474 case REG_EH_REGION
:
12475 /* These notes must remain with the call or trapping instruction. */
12476 if (GET_CODE (i3
) == CALL_INSN
)
12478 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12480 else if (flag_non_call_exceptions
)
12482 if (may_trap_p (i3
))
12484 else if (i2
&& may_trap_p (i2
))
12486 /* ??? Otherwise assume we've combined things such that we
12487 can now prove that the instructions can't trap. Drop the
12488 note in this case. */
12496 /* These notes must remain with the call. It should not be
12497 possible for both I2 and I3 to be a call. */
12498 if (GET_CODE (i3
) == CALL_INSN
)
12500 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12507 /* Any clobbers for i3 may still exist, and so we must process
12508 REG_UNUSED notes from that insn.
12510 Any clobbers from i2 or i1 can only exist if they were added by
12511 recog_for_combine. In that case, recog_for_combine created the
12512 necessary REG_UNUSED notes. Trying to keep any original
12513 REG_UNUSED notes from these insns can cause incorrect output
12514 if it is for the same register as the original i3 dest.
12515 In that case, we will notice that the register is set in i3,
12516 and then add a REG_UNUSED note for the destination of i3, which
12517 is wrong. However, it is possible to have REG_UNUSED notes from
12518 i2 or i1 for register which were both used and clobbered, so
12519 we keep notes from i2 or i1 if they will turn into REG_DEAD
12522 /* If this register is set or clobbered in I3, put the note there
12523 unless there is one already. */
12524 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12526 if (from_insn
!= i3
)
12529 if (! (GET_CODE (XEXP (note
, 0)) == REG
12530 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12531 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12534 /* Otherwise, if this register is used by I3, then this register
12535 now dies here, so we must put a REG_DEAD note here unless there
12537 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12538 && ! (GET_CODE (XEXP (note
, 0)) == REG
12539 ? find_regno_note (i3
, REG_DEAD
,
12540 REGNO (XEXP (note
, 0)))
12541 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12543 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12551 /* These notes say something about results of an insn. We can
12552 only support them if they used to be on I3 in which case they
12553 remain on I3. Otherwise they are ignored.
12555 If the note refers to an expression that is not a constant, we
12556 must also ignore the note since we cannot tell whether the
12557 equivalence is still true. It might be possible to do
12558 slightly better than this (we only have a problem if I2DEST
12559 or I1DEST is present in the expression), but it doesn't
12560 seem worth the trouble. */
12562 if (from_insn
== i3
12563 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12568 case REG_NO_CONFLICT
:
12569 /* These notes say something about how a register is used. They must
12570 be present on any use of the register in I2 or I3. */
12571 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12574 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12584 /* This can show up in several ways -- either directly in the
12585 pattern, or hidden off in the constant pool with (or without?)
12586 a REG_EQUAL note. */
12587 /* ??? Ignore the without-reg_equal-note problem for now. */
12588 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12589 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12590 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12591 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12595 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12596 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12597 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12598 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12606 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12607 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12608 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12610 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12612 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12613 LABEL_NUSES (JUMP_LABEL (place
))--;
12616 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12618 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12620 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12621 LABEL_NUSES (JUMP_LABEL (place2
))--;
12627 /* This note says something about the value of a register prior
12628 to the execution of an insn. It is too much trouble to see
12629 if the note is still correct in all situations. It is better
12630 to simply delete it. */
12634 /* If the insn previously containing this note still exists,
12635 put it back where it was. Otherwise move it to the previous
12636 insn. Adjust the corresponding REG_LIBCALL note. */
12637 if (GET_CODE (from_insn
) != NOTE
)
12641 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12642 place
= prev_real_insn (from_insn
);
12644 XEXP (tem
, 0) = place
;
12645 /* If we're deleting the last remaining instruction of a
12646 libcall sequence, don't add the notes. */
12647 else if (XEXP (note
, 0) == from_insn
)
12653 /* This is handled similarly to REG_RETVAL. */
12654 if (GET_CODE (from_insn
) != NOTE
)
12658 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12659 place
= next_real_insn (from_insn
);
12661 XEXP (tem
, 0) = place
;
12662 /* If we're deleting the last remaining instruction of a
12663 libcall sequence, don't add the notes. */
12664 else if (XEXP (note
, 0) == from_insn
)
12670 /* If the register is used as an input in I3, it dies there.
12671 Similarly for I2, if it is nonzero and adjacent to I3.
12673 If the register is not used as an input in either I3 or I2
12674 and it is not one of the registers we were supposed to eliminate,
12675 there are two possibilities. We might have a non-adjacent I2
12676 or we might have somehow eliminated an additional register
12677 from a computation. For example, we might have had A & B where
12678 we discover that B will always be zero. In this case we will
12679 eliminate the reference to A.
12681 In both cases, we must search to see if we can find a previous
12682 use of A and put the death note there. */
12685 && GET_CODE (from_insn
) == CALL_INSN
12686 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12688 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12690 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12691 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12696 basic_block bb
= this_basic_block
;
12698 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12700 if (! INSN_P (tem
))
12702 if (tem
== bb
->head
)
12707 /* If the register is being set at TEM, see if that is all
12708 TEM is doing. If so, delete TEM. Otherwise, make this
12709 into a REG_UNUSED note instead. */
12710 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12712 rtx set
= single_set (tem
);
12713 rtx inner_dest
= 0;
12715 rtx cc0_setter
= NULL_RTX
;
12719 for (inner_dest
= SET_DEST (set
);
12720 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12721 || GET_CODE (inner_dest
) == SUBREG
12722 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12723 inner_dest
= XEXP (inner_dest
, 0))
12726 /* Verify that it was the set, and not a clobber that
12727 modified the register.
12729 CC0 targets must be careful to maintain setter/user
12730 pairs. If we cannot delete the setter due to side
12731 effects, mark the user with an UNUSED note instead
12734 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12735 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12737 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12738 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12739 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12743 /* Move the notes and links of TEM elsewhere.
12744 This might delete other dead insns recursively.
12745 First set the pattern to something that won't use
12748 PATTERN (tem
) = pc_rtx
;
12750 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12752 distribute_links (LOG_LINKS (tem
));
12754 PUT_CODE (tem
, NOTE
);
12755 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12756 NOTE_SOURCE_FILE (tem
) = 0;
12759 /* Delete the setter too. */
12762 PATTERN (cc0_setter
) = pc_rtx
;
12764 distribute_notes (REG_NOTES (cc0_setter
),
12765 cc0_setter
, cc0_setter
,
12767 distribute_links (LOG_LINKS (cc0_setter
));
12769 PUT_CODE (cc0_setter
, NOTE
);
12770 NOTE_LINE_NUMBER (cc0_setter
)
12771 = NOTE_INSN_DELETED
;
12772 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12776 /* If the register is both set and used here, put the
12777 REG_DEAD note here, but place a REG_UNUSED note
12778 here too unless there already is one. */
12779 else if (reg_referenced_p (XEXP (note
, 0),
12784 if (! find_regno_note (tem
, REG_UNUSED
,
12785 REGNO (XEXP (note
, 0))))
12787 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12792 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12794 /* If there isn't already a REG_UNUSED note, put one
12796 if (! find_regno_note (tem
, REG_UNUSED
,
12797 REGNO (XEXP (note
, 0))))
12802 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12803 || (GET_CODE (tem
) == CALL_INSN
12804 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12808 /* If we are doing a 3->2 combination, and we have a
12809 register which formerly died in i3 and was not used
12810 by i2, which now no longer dies in i3 and is used in
12811 i2 but does not die in i2, and place is between i2
12812 and i3, then we may need to move a link from place to
12814 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12815 && INSN_CUID (place
) > INSN_CUID (i2
)
12817 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12818 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12820 rtx links
= LOG_LINKS (place
);
12821 LOG_LINKS (place
) = 0;
12822 distribute_links (links
);
12827 if (tem
== bb
->head
)
12831 /* We haven't found an insn for the death note and it
12832 is still a REG_DEAD note, but we have hit the beginning
12833 of the block. If the existing life info says the reg
12834 was dead, there's nothing left to do. Otherwise, we'll
12835 need to do a global life update after combine. */
12836 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12837 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12838 REGNO (XEXP (note
, 0))))
12839 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12842 /* If the register is set or already dead at PLACE, we needn't do
12843 anything with this note if it is still a REG_DEAD note.
12844 We can here if it is set at all, not if is it totally replace,
12845 which is what `dead_or_set_p' checks, so also check for it being
12848 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12850 unsigned int regno
= REGNO (XEXP (note
, 0));
12852 /* Similarly, if the instruction on which we want to place
12853 the note is a noop, we'll need do a global live update
12854 after we remove them in delete_noop_moves. */
12855 if (noop_move_p (place
))
12856 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12858 if (dead_or_set_p (place
, XEXP (note
, 0))
12859 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12861 /* Unless the register previously died in PLACE, clear
12862 reg_last_death. [I no longer understand why this is
12864 if (reg_last_death
[regno
] != place
)
12865 reg_last_death
[regno
] = 0;
12869 reg_last_death
[regno
] = place
;
12871 /* If this is a death note for a hard reg that is occupying
12872 multiple registers, ensure that we are still using all
12873 parts of the object. If we find a piece of the object
12874 that is unused, we must arrange for an appropriate REG_DEAD
12875 note to be added for it. However, we can't just emit a USE
12876 and tag the note to it, since the register might actually
12877 be dead; so we recourse, and the recursive call then finds
12878 the previous insn that used this register. */
12880 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12881 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12883 unsigned int endregno
12884 = regno
+ HARD_REGNO_NREGS (regno
,
12885 GET_MODE (XEXP (note
, 0)));
12889 for (i
= regno
; i
< endregno
; i
++)
12890 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12891 && ! find_regno_fusage (place
, USE
, i
))
12892 || dead_or_set_regno_p (place
, i
))
12897 /* Put only REG_DEAD notes for pieces that are
12898 not already dead or set. */
12900 for (i
= regno
; i
< endregno
;
12901 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12903 rtx piece
= regno_reg_rtx
[i
];
12904 basic_block bb
= this_basic_block
;
12906 if (! dead_or_set_p (place
, piece
)
12907 && ! reg_bitfield_target_p (piece
,
12911 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12913 distribute_notes (new_note
, place
, place
,
12916 else if (! refers_to_regno_p (i
, i
+ 1,
12917 PATTERN (place
), 0)
12918 && ! find_regno_fusage (place
, USE
, i
))
12919 for (tem
= PREV_INSN (place
); ;
12920 tem
= PREV_INSN (tem
))
12922 if (! INSN_P (tem
))
12924 if (tem
== bb
->head
)
12926 SET_BIT (refresh_blocks
,
12927 this_basic_block
->index
);
12932 if (dead_or_set_p (tem
, piece
)
12933 || reg_bitfield_target_p (piece
,
12937 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12952 /* Any other notes should not be present at this point in the
12959 XEXP (note
, 1) = REG_NOTES (place
);
12960 REG_NOTES (place
) = note
;
12962 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12963 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12964 && GET_CODE (XEXP (note
, 0)) == REG
)
12965 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12969 if ((REG_NOTE_KIND (note
) == REG_DEAD
12970 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12971 && GET_CODE (XEXP (note
, 0)) == REG
)
12972 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12974 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12975 REG_NOTE_KIND (note
),
12977 REG_NOTES (place2
));
12982 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12983 I3, I2, and I1 to new locations. This is also called in one case to
12984 add a link pointing at I3 when I3's destination is changed. */
12987 distribute_links (rtx links
)
12989 rtx link
, next_link
;
12991 for (link
= links
; link
; link
= next_link
)
12997 next_link
= XEXP (link
, 1);
12999 /* If the insn that this link points to is a NOTE or isn't a single
13000 set, ignore it. In the latter case, it isn't clear what we
13001 can do other than ignore the link, since we can't tell which
13002 register it was for. Such links wouldn't be used by combine
13005 It is not possible for the destination of the target of the link to
13006 have been changed by combine. The only potential of this is if we
13007 replace I3, I2, and I1 by I3 and I2. But in that case the
13008 destination of I2 also remains unchanged. */
13010 if (GET_CODE (XEXP (link
, 0)) == NOTE
13011 || (set
= single_set (XEXP (link
, 0))) == 0)
13014 reg
= SET_DEST (set
);
13015 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13016 || GET_CODE (reg
) == SIGN_EXTRACT
13017 || GET_CODE (reg
) == STRICT_LOW_PART
)
13018 reg
= XEXP (reg
, 0);
13020 /* A LOG_LINK is defined as being placed on the first insn that uses
13021 a register and points to the insn that sets the register. Start
13022 searching at the next insn after the target of the link and stop
13023 when we reach a set of the register or the end of the basic block.
13025 Note that this correctly handles the link that used to point from
13026 I3 to I2. Also note that not much searching is typically done here
13027 since most links don't point very far away. */
13029 for (insn
= NEXT_INSN (XEXP (link
, 0));
13030 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13031 || this_basic_block
->next_bb
->head
!= insn
));
13032 insn
= NEXT_INSN (insn
))
13033 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13035 if (reg_referenced_p (reg
, PATTERN (insn
)))
13039 else if (GET_CODE (insn
) == CALL_INSN
13040 && find_reg_fusage (insn
, USE
, reg
))
13046 /* If we found a place to put the link, place it there unless there
13047 is already a link to the same insn as LINK at that point. */
13053 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13054 if (XEXP (link2
, 0) == XEXP (link
, 0))
13059 XEXP (link
, 1) = LOG_LINKS (place
);
13060 LOG_LINKS (place
) = link
;
13062 /* Set added_links_insn to the earliest insn we added a
13064 if (added_links_insn
== 0
13065 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13066 added_links_insn
= place
;
13072 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13075 insn_cuid (rtx insn
)
13077 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13078 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13079 insn
= NEXT_INSN (insn
);
13081 if (INSN_UID (insn
) > max_uid_cuid
)
13084 return INSN_CUID (insn
);
13088 dump_combine_stats (FILE *file
)
13092 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13093 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13097 dump_combine_total_stats (FILE *file
)
13101 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13102 total_attempts
, total_merges
, total_extras
, total_successes
);