1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx
*reg_last_reload_reg
;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload
;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload
;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx
*reg_equiv_constant
;
99 /* Element N is an invariant value to which pseudo reg N is equivalent.
100 eliminate_regs_in_insn uses this to replace pseudos in particular
102 rtx
*reg_equiv_invariant
;
104 /* Element N is a memory location to which pseudo reg N is equivalent,
105 prior to any register elimination (such as frame pointer to stack
106 pointer). Depending on whether or not it is a valid address, this value
107 is transferred to either reg_equiv_address or reg_equiv_mem. */
108 rtx
*reg_equiv_memory_loc
;
110 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
111 collector can keep track of what is inside. */
112 varray_type reg_equiv_memory_loc_varray
;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx
*reg_equiv_address
;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width
;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
129 int reg_equiv_init_size
;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber
;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
146 static HARD_REG_SET reg_reloaded_valid
;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead
;
151 /* Indicate whether the register's current value is one that is not
152 safe to retain across a call, even for registers that are normally
154 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
156 /* Number of spill-regs so far; number of valid elements of spill_regs. */
159 /* In parallel with spill_regs, contains REG rtx's for those regs.
160 Holds the last rtx used for any given reg, or 0 if it has never
161 been used for spilling yet. This rtx is reused, provided it has
163 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
165 /* In parallel with spill_regs, contains nonzero for a spill reg
166 that was stored after the last time it was used.
167 The precise value is the insn generated to do the store. */
168 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
170 /* This is the register that was stored with spill_reg_store. This is a
171 copy of reload_out / reload_out_reg when the value was stored; if
172 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
173 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
175 /* This table is the inverse mapping of spill_regs:
176 indexed by hard reg number,
177 it contains the position of that reg in spill_regs,
178 or -1 for something that is not in spill_regs.
180 ?!? This is no longer accurate. */
181 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
183 /* This reg set indicates registers that can't be used as spill registers for
184 the currently processed insn. These are the hard registers which are live
185 during the insn, but not allocated to pseudos, as well as fixed
187 static HARD_REG_SET bad_spill_regs
;
189 /* These are the hard registers that can't be used as spill register for any
190 insn. This includes registers used for user variables and registers that
191 we can't eliminate. A register that appears in this set also can't be used
192 to retry register allocation. */
193 static HARD_REG_SET bad_spill_regs_global
;
195 /* Describes order of use of registers for reloading
196 of spilled pseudo-registers. `n_spills' is the number of
197 elements that are actually valid; new ones are added at the end.
199 Both spill_regs and spill_reg_order are used on two occasions:
200 once during find_reload_regs, where they keep track of the spill registers
201 for a single insn, but also during reload_as_needed where they show all
202 the registers ever used by reload. For the latter case, the information
203 is calculated during finish_spills. */
204 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
206 /* This vector of reg sets indicates, for each pseudo, which hard registers
207 may not be used for retrying global allocation because the register was
208 formerly spilled from one of them. If we allowed reallocating a pseudo to
209 a register that it was already allocated to, reload might not
211 static HARD_REG_SET
*pseudo_previous_regs
;
213 /* This vector of reg sets indicates, for each pseudo, which hard
214 registers may not be used for retrying global allocation because they
215 are used as spill registers during one of the insns in which the
217 static HARD_REG_SET
*pseudo_forbidden_regs
;
219 /* All hard regs that have been used as spill registers for any insn are
220 marked in this set. */
221 static HARD_REG_SET used_spill_regs
;
223 /* Index of last register assigned as a spill register. We allocate in
224 a round-robin fashion. */
225 static int last_spill_reg
;
227 /* Nonzero if indirect addressing is supported on the machine; this means
228 that spilling (REG n) does not require reloading it into a register in
229 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
230 value indicates the level of indirect addressing supported, e.g., two
231 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
233 static char spill_indirect_levels
;
235 /* Nonzero if indirect addressing is supported when the innermost MEM is
236 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
237 which these are valid is the same as spill_indirect_levels, above. */
238 char indirect_symref_ok
;
240 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
241 char double_reg_address_ok
;
243 /* Record the stack slot for each spilled hard register. */
244 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
246 /* Width allocated so far for that stack slot. */
247 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
249 /* Record which pseudos needed to be spilled. */
250 static regset_head spilled_pseudos
;
252 /* Used for communication between order_regs_for_reload and count_pseudo.
253 Used to avoid counting one pseudo twice. */
254 static regset_head pseudos_counted
;
256 /* First uid used by insns created by reload in this function.
257 Used in find_equiv_reg. */
258 int reload_first_uid
;
260 /* Flag set by local-alloc or global-alloc if anything is live in
261 a call-clobbered reg across calls. */
262 int caller_save_needed
;
264 /* Set to 1 while reload_as_needed is operating.
265 Required by some machines to handle any generated moves differently. */
266 int reload_in_progress
= 0;
268 /* These arrays record the insn_code of insns that may be needed to
269 perform input and output reloads of special objects. They provide a
270 place to pass a scratch register. */
271 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
272 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
274 /* This obstack is used for allocation of rtl during register elimination.
275 The allocated storage can be freed once find_reloads has processed the
277 static struct obstack reload_obstack
;
279 /* Points to the beginning of the reload_obstack. All insn_chain structures
280 are allocated first. */
281 static char *reload_startobj
;
283 /* The point after all insn_chain structures. Used to quickly deallocate
284 memory allocated in copy_reloads during calculate_needs_all_insns. */
285 static char *reload_firstobj
;
287 /* This points before all local rtl generated by register elimination.
288 Used to quickly free all memory after processing one insn. */
289 static char *reload_insn_firstobj
;
291 /* List of insn_chain instructions, one for every insn that reload needs to
293 struct insn_chain
*reload_insn_chain
;
295 /* List of all insns needing reloads. */
296 static struct insn_chain
*insns_need_reload
;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from
; /* Register number to be eliminated. */
306 int to
; /* Register number used as replacement. */
307 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
308 int can_eliminate
; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
312 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
313 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx
; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx
; /* REG rtx for the replacement. */
322 static struct elim_table
*reg_eliminate
= 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1
[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset
;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable
;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants
;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num
;
365 static char *offsets_known_at
;
366 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
368 /* Number of labels in the current function. */
370 static int num_labels
;
372 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
373 static void maybe_fix_stack_asms (void);
374 static void copy_reloads (struct insn_chain
*);
375 static void calculate_needs_all_insns (int);
376 static int find_reg (struct insn_chain
*, int);
377 static void find_reload_regs (struct insn_chain
*);
378 static void select_reload_regs (void);
379 static void delete_caller_save_insns (void);
381 static void spill_failure (rtx
, enum reg_class
);
382 static void count_spilled_pseudo (int, int, int);
383 static void delete_dead_insn (rtx
);
384 static void alter_reg (int, int);
385 static void set_label_offsets (rtx
, rtx
, int);
386 static void check_eliminable_occurrences (rtx
);
387 static void elimination_effects (rtx
, enum machine_mode
);
388 static int eliminate_regs_in_insn (rtx
, int);
389 static void update_eliminable_offsets (void);
390 static void mark_not_eliminable (rtx
, rtx
, void *);
391 static void set_initial_elim_offsets (void);
392 static bool verify_initial_elim_offsets (void);
393 static void set_initial_label_offsets (void);
394 static void set_offsets_for_label (rtx
);
395 static void init_elim_table (void);
396 static void update_eliminables (HARD_REG_SET
*);
397 static void spill_hard_reg (unsigned int, int);
398 static int finish_spills (int);
399 static void scan_paradoxical_subregs (rtx
);
400 static void count_pseudo (int);
401 static void order_regs_for_reload (struct insn_chain
*);
402 static void reload_as_needed (int);
403 static void forget_old_reloads_1 (rtx
, rtx
, void *);
404 static int reload_reg_class_lower (const void *, const void *);
405 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
407 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
409 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
410 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
412 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
414 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
415 static int allocate_reload_reg (struct insn_chain
*, int, int);
416 static int conflicts_with_override (rtx
);
417 static void failed_reload (rtx
, int);
418 static int set_reload_reg (int, int);
419 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
420 static void choose_reload_regs (struct insn_chain
*);
421 static void merge_assigned_reloads (rtx
);
422 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
424 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
426 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
427 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
428 static bool inherit_piecemeal_p (int, int);
429 static void emit_reload_insns (struct insn_chain
*);
430 static void delete_output_reload (rtx
, int, int);
431 static void delete_address_reloads (rtx
, rtx
);
432 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
433 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
435 static void add_auto_inc_notes (rtx
, rtx
);
437 static void copy_eh_notes (rtx
, rtx
);
438 static int reloads_conflict (int, int);
439 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
440 static rtx
emit_insn_if_valid_for_reload (rtx
);
442 /* Initialize the reload pass once per compilation. */
449 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
450 Set spill_indirect_levels to the number of levels such addressing is
451 permitted, zero if it is not permitted at all. */
454 = gen_rtx_MEM (Pmode
,
457 LAST_VIRTUAL_REGISTER
+ 1),
459 spill_indirect_levels
= 0;
461 while (memory_address_p (QImode
, tem
))
463 spill_indirect_levels
++;
464 tem
= gen_rtx_MEM (Pmode
, tem
);
467 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
469 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
470 indirect_symref_ok
= memory_address_p (QImode
, tem
);
472 /* See if reg+reg is a valid (and offsettable) address. */
474 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
476 tem
= gen_rtx_PLUS (Pmode
,
477 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
478 gen_rtx_REG (Pmode
, i
));
480 /* This way, we make sure that reg+reg is an offsettable address. */
481 tem
= plus_constant (tem
, 4);
483 if (memory_address_p (QImode
, tem
))
485 double_reg_address_ok
= 1;
490 /* Initialize obstack for our rtl allocation. */
491 gcc_obstack_init (&reload_obstack
);
492 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
494 INIT_REG_SET (&spilled_pseudos
);
495 INIT_REG_SET (&pseudos_counted
);
496 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray
, 0, "reg_equiv_memory_loc");
499 /* List of insn chains that are currently unused. */
500 static struct insn_chain
*unused_insn_chains
= 0;
502 /* Allocate an empty insn_chain structure. */
504 new_insn_chain (void)
506 struct insn_chain
*c
;
508 if (unused_insn_chains
== 0)
510 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
511 INIT_REG_SET (&c
->live_throughout
);
512 INIT_REG_SET (&c
->dead_or_set
);
516 c
= unused_insn_chains
;
517 unused_insn_chains
= c
->next
;
519 c
->is_caller_save_insn
= 0;
520 c
->need_operand_change
= 0;
526 /* Small utility function to set all regs in hard reg set TO which are
527 allocated to pseudos in regset FROM. */
530 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
533 reg_set_iterator rsi
;
535 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
537 int r
= reg_renumber
[regno
];
542 /* reload_combine uses the information from
543 BASIC_BLOCK->global_live_at_start, which might still
544 contain registers that have not actually been allocated
545 since they have an equivalence. */
546 gcc_assert (reload_completed
);
550 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (regno
)];
552 SET_HARD_REG_BIT (*to
, r
+ nregs
);
557 /* Replace all pseudos found in LOC with their corresponding
561 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
574 unsigned int regno
= REGNO (x
);
576 if (regno
< FIRST_PSEUDO_REGISTER
)
579 x
= eliminate_regs (x
, mem_mode
, usage
);
583 replace_pseudos_in (loc
, mem_mode
, usage
);
587 if (reg_equiv_constant
[regno
])
588 *loc
= reg_equiv_constant
[regno
];
589 else if (reg_equiv_mem
[regno
])
590 *loc
= reg_equiv_mem
[regno
];
591 else if (reg_equiv_address
[regno
])
592 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
595 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
596 || REGNO (regno_reg_rtx
[regno
]) != regno
);
597 *loc
= regno_reg_rtx
[regno
];
602 else if (code
== MEM
)
604 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
608 /* Process each of our operands recursively. */
609 fmt
= GET_RTX_FORMAT (code
);
610 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
612 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
613 else if (*fmt
== 'E')
614 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
615 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
619 /* Global variables used by reload and its subroutines. */
621 /* Set during calculate_needs if an insn needs register elimination. */
622 static int something_needs_elimination
;
623 /* Set during calculate_needs if an insn needs an operand changed. */
624 static int something_needs_operands_changed
;
626 /* Nonzero means we couldn't get enough spill regs. */
629 /* Main entry point for the reload pass.
631 FIRST is the first insn of the function being compiled.
633 GLOBAL nonzero means we were called from global_alloc
634 and should attempt to reallocate any pseudoregs that we
635 displace from hard regs we will use for reloads.
636 If GLOBAL is zero, we do not have enough information to do that,
637 so any pseudo reg that is spilled must go to the stack.
639 Return value is nonzero if reload failed
640 and we must not do any more for this function. */
643 reload (rtx first
, int global
)
647 struct elim_table
*ep
;
650 /* Make sure even insns with volatile mem refs are recognizable. */
655 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
657 /* Make sure that the last insn in the chain
658 is not something that needs reloading. */
659 emit_note (NOTE_INSN_DELETED
);
661 /* Enable find_equiv_reg to distinguish insns made by reload. */
662 reload_first_uid
= get_max_uid ();
664 #ifdef SECONDARY_MEMORY_NEEDED
665 /* Initialize the secondary memory table. */
666 clear_secondary_mem ();
669 /* We don't have a stack slot for any spill reg yet. */
670 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
671 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
673 /* Initialize the save area information for caller-save, in case some
677 /* Compute which hard registers are now in use
678 as homes for pseudo registers.
679 This is done here rather than (eg) in global_alloc
680 because this point is reached even if not optimizing. */
681 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
684 /* A function that receives a nonlocal goto must save all call-saved
686 if (current_function_has_nonlocal_label
)
687 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
688 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
689 regs_ever_live
[i
] = 1;
691 /* Find all the pseudo registers that didn't get hard regs
692 but do have known equivalent constants or memory slots.
693 These include parameters (known equivalent to parameter slots)
694 and cse'd or loop-moved constant memory addresses.
696 Record constant equivalents in reg_equiv_constant
697 so they will be substituted by find_reloads.
698 Record memory equivalents in reg_mem_equiv so they can
699 be substituted eventually by altering the REG-rtx's. */
701 reg_equiv_constant
= xcalloc (max_regno
, sizeof (rtx
));
702 reg_equiv_invariant
= xcalloc (max_regno
, sizeof (rtx
));
703 reg_equiv_mem
= xcalloc (max_regno
, sizeof (rtx
));
704 reg_equiv_address
= xcalloc (max_regno
, sizeof (rtx
));
705 reg_max_ref_width
= xcalloc (max_regno
, sizeof (int));
706 reg_old_renumber
= xcalloc (max_regno
, sizeof (short));
707 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
708 pseudo_forbidden_regs
= xmalloc (max_regno
* sizeof (HARD_REG_SET
));
709 pseudo_previous_regs
= xcalloc (max_regno
, sizeof (HARD_REG_SET
));
711 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
713 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
714 to. Also find all paradoxical subregs and find largest such for
717 num_eliminable_invariants
= 0;
718 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
720 rtx set
= single_set (insn
);
722 /* We may introduce USEs that we want to remove at the end, so
723 we'll mark them with QImode. Make sure there are no
724 previously-marked insns left by say regmove. */
725 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
726 && GET_MODE (insn
) != VOIDmode
)
727 PUT_MODE (insn
, VOIDmode
);
730 scan_paradoxical_subregs (PATTERN (insn
));
732 if (set
!= 0 && REG_P (SET_DEST (set
)))
734 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
740 i
= REGNO (SET_DEST (set
));
743 if (i
<= LAST_VIRTUAL_REGISTER
)
746 if (! function_invariant_p (x
)
748 /* A function invariant is often CONSTANT_P but may
749 include a register. We promise to only pass
750 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
752 && LEGITIMATE_PIC_OPERAND_P (x
)))
754 /* It can happen that a REG_EQUIV note contains a MEM
755 that is not a legitimate memory operand. As later
756 stages of reload assume that all addresses found
757 in the reg_equiv_* arrays were originally legitimate,
758 we ignore such REG_EQUIV notes. */
759 if (memory_operand (x
, VOIDmode
))
761 /* Always unshare the equivalence, so we can
762 substitute into this insn without touching the
764 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
766 else if (function_invariant_p (x
))
768 if (GET_CODE (x
) == PLUS
)
770 /* This is PLUS of frame pointer and a constant,
771 and might be shared. Unshare it. */
772 reg_equiv_invariant
[i
] = copy_rtx (x
);
773 num_eliminable_invariants
++;
775 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
777 reg_equiv_invariant
[i
] = x
;
778 num_eliminable_invariants
++;
780 else if (LEGITIMATE_CONSTANT_P (x
))
781 reg_equiv_constant
[i
] = x
;
784 reg_equiv_memory_loc
[i
]
785 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
786 if (! reg_equiv_memory_loc
[i
])
787 reg_equiv_init
[i
] = NULL_RTX
;
792 reg_equiv_init
[i
] = NULL_RTX
;
797 reg_equiv_init
[i
] = NULL_RTX
;
802 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
803 if (reg_equiv_init
[i
])
805 fprintf (dump_file
, "init_insns for %u: ", i
);
806 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
807 fprintf (dump_file
, "\n");
812 first_label_num
= get_first_label_num ();
813 num_labels
= max_label_num () - first_label_num
;
815 /* Allocate the tables used to store offset information at labels. */
816 /* We used to use alloca here, but the size of what it would try to
817 allocate would occasionally cause it to exceed the stack limit and
818 cause a core dump. */
819 offsets_known_at
= xmalloc (num_labels
);
820 offsets_at
= xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
822 /* Alter each pseudo-reg rtx to contain its hard reg number.
823 Assign stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
829 /* If we have some registers we think can be eliminated, scan all insns to
830 see if there is an insn that sets one of these registers to something
831 other than itself plus a constant. If so, the register cannot be
832 eliminated. Doing this scan here eliminates an extra pass through the
833 main reload loop in the most common case where register elimination
835 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
837 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
839 maybe_fix_stack_asms ();
841 insns_need_reload
= 0;
842 something_needs_elimination
= 0;
844 /* Initialize to -1, which means take the first spill register. */
847 /* Spill any hard regs that we know we can't eliminate. */
848 CLEAR_HARD_REG_SET (used_spill_regs
);
849 /* There can be multiple ways to eliminate a register;
850 they should be listed adjacently.
851 Elimination for any register fails only if all possible ways fail. */
852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
855 int can_eliminate
= 0;
858 can_eliminate
|= ep
->can_eliminate
;
861 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
863 spill_hard_reg (from
, 1);
866 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
867 if (frame_pointer_needed
)
868 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
870 finish_spills (global
);
872 /* From now on, we may need to generate moves differently. We may also
873 allow modifications of insns which cause them to not be recognized.
874 Any such modifications will be cleaned up during reload itself. */
875 reload_in_progress
= 1;
877 /* This loop scans the entire function each go-round
878 and repeats until one repetition spills no additional hard regs. */
881 int something_changed
;
884 HOST_WIDE_INT starting_frame_size
;
886 /* Round size of stack frame to stack_alignment_needed. This must be done
887 here because the stack size may be a part of the offset computation
888 for register elimination, and there might have been new stack slots
889 created in the last iteration of this loop. */
890 if (cfun
->stack_alignment_needed
)
891 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
893 starting_frame_size
= get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
923 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
925 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
929 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
930 else if (CONSTANT_P (XEXP (x
, 0))
931 || (REG_P (XEXP (x
, 0))
932 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
933 || (GET_CODE (XEXP (x
, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x
, 0), 0))
935 && (REGNO (XEXP (XEXP (x
, 0), 0))
936 < FIRST_PSEUDO_REGISTER
)
937 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
938 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc
[i
] = 0;
948 reg_equiv_init
[i
] = 0;
953 if (caller_save_needed
)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size
!= get_frame_size ())
960 if (caller_save_needed
)
962 save_call_clobbered_regs ();
963 /* That might have allocated new insn_chain structures. */
964 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
967 calculate_needs_all_insns (global
);
969 CLEAR_REG_SET (&spilled_pseudos
);
972 something_changed
= 0;
974 /* If we allocated any new memory locations, make another pass
975 since it might have changed elimination offsets. */
976 if (starting_frame_size
!= get_frame_size ())
977 something_changed
= 1;
979 /* Even if the frame size remained the same, we might still have
980 changed elimination offsets, e.g. if find_reloads called
981 force_const_mem requiring the back end to allocate a constant
982 pool base register that needs to be saved on the stack. */
983 else if (!verify_initial_elim_offsets ())
984 something_changed
= 1;
987 HARD_REG_SET to_spill
;
988 CLEAR_HARD_REG_SET (to_spill
);
989 update_eliminables (&to_spill
);
990 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
991 if (TEST_HARD_REG_BIT (to_spill
, i
))
993 spill_hard_reg (i
, 1);
996 /* Regardless of the state of spills, if we previously had
997 a register that we thought we could eliminate, but now can
998 not eliminate, we must run another pass.
1000 Consider pseudos which have an entry in reg_equiv_* which
1001 reference an eliminable register. We must make another pass
1002 to update reg_equiv_* so that we do not substitute in the
1003 old value from when we thought the elimination could be
1005 something_changed
= 1;
1009 select_reload_regs ();
1013 if (insns_need_reload
!= 0 || did_spill
)
1014 something_changed
|= finish_spills (global
);
1016 if (! something_changed
)
1019 if (caller_save_needed
)
1020 delete_caller_save_insns ();
1022 obstack_free (&reload_obstack
, reload_firstobj
);
1025 /* If global-alloc was run, notify it of any register eliminations we have
1028 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1029 if (ep
->can_eliminate
)
1030 mark_elimination (ep
->from
, ep
->to
);
1032 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1033 If that insn didn't set the register (i.e., it copied the register to
1034 memory), just delete that insn instead of the equivalencing insn plus
1035 anything now dead. If we call delete_dead_insn on that insn, we may
1036 delete the insn that actually sets the register if the register dies
1037 there and that is incorrect. */
1039 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1041 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1044 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1046 rtx equiv_insn
= XEXP (list
, 0);
1048 /* If we already deleted the insn or if it may trap, we can't
1049 delete it. The latter case shouldn't happen, but can
1050 if an insn has a variable address, gets a REG_EH_REGION
1051 note added to it, and then gets converted into a load
1052 from a constant address. */
1053 if (NOTE_P (equiv_insn
)
1054 || can_throw_internal (equiv_insn
))
1056 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1057 delete_dead_insn (equiv_insn
);
1059 SET_INSN_DELETED (equiv_insn
);
1064 /* Use the reload registers where necessary
1065 by generating move instructions to move the must-be-register
1066 values into or out of the reload registers. */
1068 if (insns_need_reload
!= 0 || something_needs_elimination
1069 || something_needs_operands_changed
)
1071 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1073 reload_as_needed (global
);
1075 gcc_assert (old_frame_size
== get_frame_size ());
1077 gcc_assert (verify_initial_elim_offsets ());
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed
)
1088 CLEAR_REGNO_REG_SET (bb
->il
.rtl
->global_live_at_start
,
1089 HARD_FRAME_POINTER_REGNUM
);
1091 /* Come here (with failure set nonzero) if we can't get enough spill
1095 CLEAR_REG_SET (&spilled_pseudos
);
1096 reload_in_progress
= 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1112 if (reg_equiv_mem
[i
])
1113 addr
= XEXP (reg_equiv_mem
[i
], 0);
1115 if (reg_equiv_address
[i
])
1116 addr
= reg_equiv_address
[i
];
1120 if (reg_renumber
[i
] < 0)
1122 rtx reg
= regno_reg_rtx
[i
];
1124 REG_USERVAR_P (reg
) = 0;
1125 PUT_CODE (reg
, MEM
);
1126 XEXP (reg
, 0) = addr
;
1127 if (reg_equiv_memory_loc
[i
])
1128 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1131 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1132 MEM_ATTRS (reg
) = 0;
1134 MEM_NOTRAP_P (reg
) = 1;
1136 else if (reg_equiv_mem
[i
])
1137 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1141 /* We must set reload_completed now since the cleanup_subreg_operands call
1142 below will re-recognize each insn and reload may have generated insns
1143 which are only valid during and after reload. */
1144 reload_completed
= 1;
1146 /* Make a pass over all the insns and delete all USEs which we inserted
1147 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1148 notes. Delete all CLOBBER insns, except those that refer to the return
1149 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1150 from misarranging variable-array code, and simplify (subreg (reg))
1151 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1152 are no longer useful or accurate. Strip and regenerate REG_INC notes
1153 that may have been moved around. */
1155 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1161 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1162 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1164 if ((GET_CODE (PATTERN (insn
)) == USE
1165 /* We mark with QImode USEs introduced by reload itself. */
1166 && (GET_MODE (insn
) == QImode
1167 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1168 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1169 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1170 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1171 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1172 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1173 != stack_pointer_rtx
))
1174 && (!REG_P (XEXP (PATTERN (insn
), 0))
1175 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1181 /* Some CLOBBERs may survive until here and still reference unassigned
1182 pseudos with const equivalent, which may in turn cause ICE in later
1183 passes if the reference remains in place. */
1184 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1185 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1186 VOIDmode
, PATTERN (insn
));
1188 /* Discard obvious no-ops, even without -O. This optimization
1189 is fast and doesn't interfere with debugging. */
1190 if (NONJUMP_INSN_P (insn
)
1191 && GET_CODE (PATTERN (insn
)) == SET
1192 && REG_P (SET_SRC (PATTERN (insn
)))
1193 && REG_P (SET_DEST (PATTERN (insn
)))
1194 && (REGNO (SET_SRC (PATTERN (insn
)))
1195 == REGNO (SET_DEST (PATTERN (insn
)))))
1201 pnote
= ®_NOTES (insn
);
1204 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1205 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1206 || REG_NOTE_KIND (*pnote
) == REG_INC
1207 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1208 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1209 *pnote
= XEXP (*pnote
, 1);
1211 pnote
= &XEXP (*pnote
, 1);
1215 add_auto_inc_notes (insn
, PATTERN (insn
));
1218 /* And simplify (subreg (reg)) if it appears as an operand. */
1219 cleanup_subreg_operands (insn
);
1222 /* If we are doing stack checking, give a warning if this function's
1223 frame size is larger than we expect. */
1224 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1226 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1227 static int verbose_warned
= 0;
1229 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1230 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1231 size
+= UNITS_PER_WORD
;
1233 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1235 warning (0, "frame size too large for reliable stack checking");
1236 if (! verbose_warned
)
1238 warning (0, "try reducing the number of local variables");
1244 /* Indicate that we no longer have known memory locations or constants. */
1245 if (reg_equiv_constant
)
1246 free (reg_equiv_constant
);
1247 if (reg_equiv_invariant
)
1248 free (reg_equiv_invariant
);
1249 reg_equiv_constant
= 0;
1250 reg_equiv_invariant
= 0;
1251 VARRAY_GROW (reg_equiv_memory_loc_varray
, 0);
1252 reg_equiv_memory_loc
= 0;
1254 if (offsets_known_at
)
1255 free (offsets_known_at
);
1259 free (reg_equiv_mem
);
1261 free (reg_equiv_address
);
1262 free (reg_max_ref_width
);
1263 free (reg_old_renumber
);
1264 free (pseudo_previous_regs
);
1265 free (pseudo_forbidden_regs
);
1267 CLEAR_HARD_REG_SET (used_spill_regs
);
1268 for (i
= 0; i
< n_spills
; i
++)
1269 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1271 /* Free all the insn_chain structures at once. */
1272 obstack_free (&reload_obstack
, reload_startobj
);
1273 unused_insn_chains
= 0;
1274 fixup_abnormal_edges ();
1276 /* Replacing pseudos with their memory equivalents might have
1277 created shared rtx. Subsequent passes would get confused
1278 by this, so unshare everything here. */
1279 unshare_all_rtl_again (first
);
1281 #ifdef STACK_BOUNDARY
1282 /* init_emit has set the alignment of the hard frame pointer
1283 to STACK_BOUNDARY. It is very likely no longer valid if
1284 the hard frame pointer was used for register allocation. */
1285 if (!frame_pointer_needed
)
1286 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1292 /* Yet another special case. Unfortunately, reg-stack forces people to
1293 write incorrect clobbers in asm statements. These clobbers must not
1294 cause the register to appear in bad_spill_regs, otherwise we'll call
1295 fatal_insn later. We clear the corresponding regnos in the live
1296 register sets to avoid this.
1297 The whole thing is rather sick, I'm afraid. */
1300 maybe_fix_stack_asms (void)
1303 const char *constraints
[MAX_RECOG_OPERANDS
];
1304 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1305 struct insn_chain
*chain
;
1307 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1310 HARD_REG_SET clobbered
, allowed
;
1313 if (! INSN_P (chain
->insn
)
1314 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1316 pat
= PATTERN (chain
->insn
);
1317 if (GET_CODE (pat
) != PARALLEL
)
1320 CLEAR_HARD_REG_SET (clobbered
);
1321 CLEAR_HARD_REG_SET (allowed
);
1323 /* First, make a mask of all stack regs that are clobbered. */
1324 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1326 rtx t
= XVECEXP (pat
, 0, i
);
1327 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1328 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1331 /* Get the operand values and constraints out of the insn. */
1332 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1333 constraints
, operand_mode
);
1335 /* For every operand, see what registers are allowed. */
1336 for (i
= 0; i
< noperands
; i
++)
1338 const char *p
= constraints
[i
];
1339 /* For every alternative, we compute the class of registers allowed
1340 for reloading in CLS, and merge its contents into the reg set
1342 int cls
= (int) NO_REGS
;
1348 if (c
== '\0' || c
== ',' || c
== '#')
1350 /* End of one alternative - mark the regs in the current
1351 class, and reset the class. */
1352 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1358 } while (c
!= '\0' && c
!= ',');
1366 case '=': case '+': case '*': case '%': case '?': case '!':
1367 case '0': case '1': case '2': case '3': case '4': case 'm':
1368 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1369 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1370 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1375 cls
= (int) reg_class_subunion
[cls
]
1376 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1381 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1385 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1386 cls
= (int) reg_class_subunion
[cls
]
1387 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1389 cls
= (int) reg_class_subunion
[cls
]
1390 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1392 p
+= CONSTRAINT_LEN (c
, p
);
1395 /* Those of the registers which are clobbered, but allowed by the
1396 constraints, must be usable as reload registers. So clear them
1397 out of the life information. */
1398 AND_HARD_REG_SET (allowed
, clobbered
);
1399 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1400 if (TEST_HARD_REG_BIT (allowed
, i
))
1402 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1403 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1410 /* Copy the global variables n_reloads and rld into the corresponding elts
1413 copy_reloads (struct insn_chain
*chain
)
1415 chain
->n_reloads
= n_reloads
;
1416 chain
->rld
= obstack_alloc (&reload_obstack
,
1417 n_reloads
* sizeof (struct reload
));
1418 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1419 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1422 /* Walk the chain of insns, and determine for each whether it needs reloads
1423 and/or eliminations. Build the corresponding insns_need_reload list, and
1424 set something_needs_elimination as appropriate. */
1426 calculate_needs_all_insns (int global
)
1428 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1429 struct insn_chain
*chain
, *next
= 0;
1431 something_needs_elimination
= 0;
1433 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1434 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1436 rtx insn
= chain
->insn
;
1440 /* Clear out the shortcuts. */
1441 chain
->n_reloads
= 0;
1442 chain
->need_elim
= 0;
1443 chain
->need_reload
= 0;
1444 chain
->need_operand_change
= 0;
1446 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1447 include REG_LABEL), we need to see what effects this has on the
1448 known offsets at labels. */
1450 if (LABEL_P (insn
) || JUMP_P (insn
)
1451 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1452 set_label_offsets (insn
, insn
, 0);
1456 rtx old_body
= PATTERN (insn
);
1457 int old_code
= INSN_CODE (insn
);
1458 rtx old_notes
= REG_NOTES (insn
);
1459 int did_elimination
= 0;
1460 int operands_changed
= 0;
1461 rtx set
= single_set (insn
);
1463 /* Skip insns that only set an equivalence. */
1464 if (set
&& REG_P (SET_DEST (set
))
1465 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1466 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1467 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1468 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1471 /* If needed, eliminate any eliminable registers. */
1472 if (num_eliminable
|| num_eliminable_invariants
)
1473 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1475 /* Analyze the instruction. */
1476 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1477 global
, spill_reg_order
);
1479 /* If a no-op set needs more than one reload, this is likely
1480 to be something that needs input address reloads. We
1481 can't get rid of this cleanly later, and it is of no use
1482 anyway, so discard it now.
1483 We only do this when expensive_optimizations is enabled,
1484 since this complements reload inheritance / output
1485 reload deletion, and it can make debugging harder. */
1486 if (flag_expensive_optimizations
&& n_reloads
> 1)
1488 rtx set
= single_set (insn
);
1490 && SET_SRC (set
) == SET_DEST (set
)
1491 && REG_P (SET_SRC (set
))
1492 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1495 /* Delete it from the reload chain. */
1497 chain
->prev
->next
= next
;
1499 reload_insn_chain
= next
;
1501 next
->prev
= chain
->prev
;
1502 chain
->next
= unused_insn_chains
;
1503 unused_insn_chains
= chain
;
1508 update_eliminable_offsets ();
1510 /* Remember for later shortcuts which insns had any reloads or
1511 register eliminations. */
1512 chain
->need_elim
= did_elimination
;
1513 chain
->need_reload
= n_reloads
> 0;
1514 chain
->need_operand_change
= operands_changed
;
1516 /* Discard any register replacements done. */
1517 if (did_elimination
)
1519 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1520 PATTERN (insn
) = old_body
;
1521 INSN_CODE (insn
) = old_code
;
1522 REG_NOTES (insn
) = old_notes
;
1523 something_needs_elimination
= 1;
1526 something_needs_operands_changed
|= operands_changed
;
1530 copy_reloads (chain
);
1531 *pprev_reload
= chain
;
1532 pprev_reload
= &chain
->next_need_reload
;
1539 /* Comparison function for qsort to decide which of two reloads
1540 should be handled first. *P1 and *P2 are the reload numbers. */
1543 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1545 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1548 /* Consider required reloads before optional ones. */
1549 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1553 /* Count all solitary classes before non-solitary ones. */
1554 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1555 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1559 /* Aside from solitaires, consider all multi-reg groups first. */
1560 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1564 /* Consider reloads in order of increasing reg-class number. */
1565 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1569 /* If reloads are equally urgent, sort by reload number,
1570 so that the results of qsort leave nothing to chance. */
1574 /* The cost of spilling each hard reg. */
1575 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1577 /* When spilling multiple hard registers, we use SPILL_COST for the first
1578 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1579 only the first hard reg for a multi-reg pseudo. */
1580 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1582 /* Update the spill cost arrays, considering that pseudo REG is live. */
1585 count_pseudo (int reg
)
1587 int freq
= REG_FREQ (reg
);
1588 int r
= reg_renumber
[reg
];
1591 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1592 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1595 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1597 gcc_assert (r
>= 0);
1599 spill_add_cost
[r
] += freq
;
1601 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1603 spill_cost
[r
+ nregs
] += freq
;
1606 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1607 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1610 order_regs_for_reload (struct insn_chain
*chain
)
1613 HARD_REG_SET used_by_pseudos
;
1614 HARD_REG_SET used_by_pseudos2
;
1615 reg_set_iterator rsi
;
1617 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1619 memset (spill_cost
, 0, sizeof spill_cost
);
1620 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1622 /* Count number of uses of each hard reg by pseudo regs allocated to it
1623 and then order them by decreasing use. First exclude hard registers
1624 that are live in or across this insn. */
1626 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1628 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1629 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1631 /* Now find out which pseudos are allocated to it, and update
1633 CLEAR_REG_SET (&pseudos_counted
);
1635 EXECUTE_IF_SET_IN_REG_SET
1636 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1640 EXECUTE_IF_SET_IN_REG_SET
1641 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1645 CLEAR_REG_SET (&pseudos_counted
);
1648 /* Vector of reload-numbers showing the order in which the reloads should
1650 static short reload_order
[MAX_RELOADS
];
1652 /* This is used to keep track of the spill regs used in one insn. */
1653 static HARD_REG_SET used_spill_regs_local
;
1655 /* We decided to spill hard register SPILLED, which has a size of
1656 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1657 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1658 update SPILL_COST/SPILL_ADD_COST. */
1661 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1663 int r
= reg_renumber
[reg
];
1664 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1666 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1667 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1670 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1672 spill_add_cost
[r
] -= REG_FREQ (reg
);
1674 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1677 /* Find reload register to use for reload number ORDER. */
1680 find_reg (struct insn_chain
*chain
, int order
)
1682 int rnum
= reload_order
[order
];
1683 struct reload
*rl
= rld
+ rnum
;
1684 int best_cost
= INT_MAX
;
1688 HARD_REG_SET not_usable
;
1689 HARD_REG_SET used_by_other_reload
;
1690 reg_set_iterator rsi
;
1692 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1693 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1694 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1696 CLEAR_HARD_REG_SET (used_by_other_reload
);
1697 for (k
= 0; k
< order
; k
++)
1699 int other
= reload_order
[k
];
1701 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1702 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1703 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1706 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1708 unsigned int regno
= i
;
1710 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1711 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1712 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1714 int this_cost
= spill_cost
[regno
];
1716 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1718 for (j
= 1; j
< this_nregs
; j
++)
1720 this_cost
+= spill_add_cost
[regno
+ j
];
1721 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1722 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1727 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1729 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1731 if (this_cost
< best_cost
1732 /* Among registers with equal cost, prefer caller-saved ones, or
1733 use REG_ALLOC_ORDER if it is defined. */
1734 || (this_cost
== best_cost
1735 #ifdef REG_ALLOC_ORDER
1736 && (inv_reg_alloc_order
[regno
]
1737 < inv_reg_alloc_order
[best_reg
])
1739 && call_used_regs
[regno
]
1740 && ! call_used_regs
[best_reg
]
1745 best_cost
= this_cost
;
1753 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1755 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1756 rl
->regno
= best_reg
;
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1761 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1764 EXECUTE_IF_SET_IN_REG_SET
1765 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1767 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1770 for (i
= 0; i
< rl
->nregs
; i
++)
1772 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1773 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1774 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1779 /* Find more reload regs to satisfy the remaining need of an insn, which
1781 Do it by ascending class number, since otherwise a reg
1782 might be spilled for a big class and might fail to count
1783 for a smaller class even though it belongs to that class. */
1786 find_reload_regs (struct insn_chain
*chain
)
1790 /* In order to be certain of getting the registers we need,
1791 we must sort the reloads into order of increasing register class.
1792 Then our grabbing of reload registers will parallel the process
1793 that provided the reload registers. */
1794 for (i
= 0; i
< chain
->n_reloads
; i
++)
1796 /* Show whether this reload already has a hard reg. */
1797 if (chain
->rld
[i
].reg_rtx
)
1799 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1800 chain
->rld
[i
].regno
= regno
;
1802 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1805 chain
->rld
[i
].regno
= -1;
1806 reload_order
[i
] = i
;
1809 n_reloads
= chain
->n_reloads
;
1810 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1812 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1815 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1817 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1819 /* Compute the order of preference for hard registers to spill. */
1821 order_regs_for_reload (chain
);
1823 for (i
= 0; i
< n_reloads
; i
++)
1825 int r
= reload_order
[i
];
1827 /* Ignore reloads that got marked inoperative. */
1828 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1829 && ! rld
[r
].optional
1830 && rld
[r
].regno
== -1)
1831 if (! find_reg (chain
, i
))
1833 spill_failure (chain
->insn
, rld
[r
].class);
1839 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1840 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1842 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1846 select_reload_regs (void)
1848 struct insn_chain
*chain
;
1850 /* Try to satisfy the needs for each insn. */
1851 for (chain
= insns_need_reload
; chain
!= 0;
1852 chain
= chain
->next_need_reload
)
1853 find_reload_regs (chain
);
1856 /* Delete all insns that were inserted by emit_caller_save_insns during
1859 delete_caller_save_insns (void)
1861 struct insn_chain
*c
= reload_insn_chain
;
1865 while (c
!= 0 && c
->is_caller_save_insn
)
1867 struct insn_chain
*next
= c
->next
;
1870 if (c
== reload_insn_chain
)
1871 reload_insn_chain
= next
;
1875 next
->prev
= c
->prev
;
1877 c
->prev
->next
= next
;
1878 c
->next
= unused_insn_chains
;
1879 unused_insn_chains
= c
;
1887 /* Handle the failure to find a register to spill.
1888 INSN should be one of the insns which needed this particular spill reg. */
1891 spill_failure (rtx insn
, enum reg_class
class)
1893 if (asm_noperands (PATTERN (insn
)) >= 0)
1894 error_for_asm (insn
, "can't find a register in class %qs while "
1895 "reloading %<asm%>",
1896 reg_class_names
[class]);
1899 error ("unable to find a register to spill in class %qs",
1900 reg_class_names
[class]);
1901 fatal_insn ("this is the insn:", insn
);
1905 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1906 data that is dead in INSN. */
1909 delete_dead_insn (rtx insn
)
1911 rtx prev
= prev_real_insn (insn
);
1914 /* If the previous insn sets a register that dies in our insn, delete it
1916 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1917 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
1918 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1919 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1920 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1921 delete_dead_insn (prev
);
1923 SET_INSN_DELETED (insn
);
1926 /* Modify the home of pseudo-reg I.
1927 The new home is present in reg_renumber[I].
1929 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1930 or it may be -1, meaning there is none or it is not relevant.
1931 This is used so that all pseudos spilled from a given hard reg
1932 can share one stack slot. */
1935 alter_reg (int i
, int from_reg
)
1937 /* When outputting an inline function, this can happen
1938 for a reg that isn't actually used. */
1939 if (regno_reg_rtx
[i
] == 0)
1942 /* If the reg got changed to a MEM at rtl-generation time,
1944 if (!REG_P (regno_reg_rtx
[i
]))
1947 /* Modify the reg-rtx to contain the new hard reg
1948 number or else to contain its pseudo reg number. */
1949 REGNO (regno_reg_rtx
[i
])
1950 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1952 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1953 allocate a stack slot for it. */
1955 if (reg_renumber
[i
] < 0
1956 && REG_N_REFS (i
) > 0
1957 && reg_equiv_constant
[i
] == 0
1958 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
1959 && reg_equiv_memory_loc
[i
] == 0)
1962 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1963 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1966 /* Each pseudo reg has an inherent size which comes from its own mode,
1967 and a total size which provides room for paradoxical subregs
1968 which refer to the pseudo reg in wider modes.
1970 We can use a slot already allocated if it provides both
1971 enough inherent space and enough total space.
1972 Otherwise, we allocate a new slot, making sure that it has no less
1973 inherent space, and no less total space, then the previous slot. */
1976 /* No known place to spill from => no slot to reuse. */
1977 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1978 inherent_size
== total_size
? 0 : -1);
1979 if (BYTES_BIG_ENDIAN
)
1980 /* Cancel the big-endian correction done in assign_stack_local.
1981 Get the address of the beginning of the slot.
1982 This is so we can do a big-endian correction unconditionally
1984 adjust
= inherent_size
- total_size
;
1986 /* Nothing can alias this slot except this pseudo. */
1987 set_mem_alias_set (x
, new_alias_set ());
1990 /* Reuse a stack slot if possible. */
1991 else if (spill_stack_slot
[from_reg
] != 0
1992 && spill_stack_slot_width
[from_reg
] >= total_size
1993 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1995 x
= spill_stack_slot
[from_reg
];
1997 /* Allocate a bigger slot. */
2000 /* Compute maximum size needed, both for inherent size
2001 and for total size. */
2002 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2005 if (spill_stack_slot
[from_reg
])
2007 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2009 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2010 if (spill_stack_slot_width
[from_reg
] > total_size
)
2011 total_size
= spill_stack_slot_width
[from_reg
];
2014 /* Make a slot with that size. */
2015 x
= assign_stack_local (mode
, total_size
,
2016 inherent_size
== total_size
? 0 : -1);
2019 /* All pseudos mapped to this slot can alias each other. */
2020 if (spill_stack_slot
[from_reg
])
2021 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2023 set_mem_alias_set (x
, new_alias_set ());
2025 if (BYTES_BIG_ENDIAN
)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2034 = adjust_address_nv (x
, mode_for_size (total_size
2040 spill_stack_slot
[from_reg
] = stack_slot
;
2041 spill_stack_slot_width
[from_reg
] = total_size
;
2044 /* On a big endian machine, the "address" of the slot
2045 is the address of the low part that fits its inherent mode. */
2046 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2047 adjust
+= (total_size
- inherent_size
);
2049 /* If we have any adjustment to make, or if the stack slot is the
2050 wrong mode, make a new stack slot. */
2051 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2053 /* If we have a decl for the original register, set it for the
2054 memory. If this is a shared MEM, make a copy. */
2055 if (REG_EXPR (regno_reg_rtx
[i
])
2056 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2058 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2060 /* We can do this only for the DECLs home pseudo, not for
2061 any copies of it, since otherwise when the stack slot
2062 is reused, nonoverlapping_memrefs_p might think they
2064 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2066 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2069 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2073 /* Save the stack slot for later. */
2074 reg_equiv_memory_loc
[i
] = x
;
2078 /* Mark the slots in regs_ever_live for the hard regs
2079 used by pseudo-reg number REGNO. */
2082 mark_home_live (int regno
)
2086 i
= reg_renumber
[regno
];
2089 lim
= i
+ hard_regno_nregs
[i
][PSEUDO_REGNO_MODE (regno
)];
2091 regs_ever_live
[i
++] = 1;
2094 /* This function handles the tracking of elimination offsets around branches.
2096 X is a piece of RTL being scanned.
2098 INSN is the insn that it came from, if any.
2100 INITIAL_P is nonzero if we are to set the offset to be the initial
2101 offset and zero if we are setting the offset of the label to be the
2105 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2107 enum rtx_code code
= GET_CODE (x
);
2110 struct elim_table
*p
;
2115 if (LABEL_REF_NONLOCAL_P (x
))
2120 /* ... fall through ... */
2123 /* If we know nothing about this label, set the desired offsets. Note
2124 that this sets the offset at a label to be the offset before a label
2125 if we don't know anything about the label. This is not correct for
2126 the label after a BARRIER, but is the best guess we can make. If
2127 we guessed wrong, we will suppress an elimination that might have
2128 been possible had we been able to guess correctly. */
2130 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2132 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2133 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2134 = (initial_p
? reg_eliminate
[i
].initial_offset
2135 : reg_eliminate
[i
].offset
);
2136 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2139 /* Otherwise, if this is the definition of a label and it is
2140 preceded by a BARRIER, set our offsets to the known offset of
2144 && (tem
= prev_nonnote_insn (insn
)) != 0
2146 set_offsets_for_label (insn
);
2148 /* If neither of the above cases is true, compare each offset
2149 with those previously recorded and suppress any eliminations
2150 where the offsets disagree. */
2152 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2153 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2154 != (initial_p
? reg_eliminate
[i
].initial_offset
2155 : reg_eliminate
[i
].offset
))
2156 reg_eliminate
[i
].can_eliminate
= 0;
2161 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2163 /* ... fall through ... */
2167 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2168 and hence must have all eliminations at their initial offsets. */
2169 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2170 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2171 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2177 /* Each of the labels in the parallel or address vector must be
2178 at their initial offsets. We want the first field for PARALLEL
2179 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2181 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2182 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2187 /* We only care about setting PC. If the source is not RETURN,
2188 IF_THEN_ELSE, or a label, disable any eliminations not at
2189 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2190 isn't one of those possibilities. For branches to a label,
2191 call ourselves recursively.
2193 Note that this can disable elimination unnecessarily when we have
2194 a non-local goto since it will look like a non-constant jump to
2195 someplace in the current function. This isn't a significant
2196 problem since such jumps will normally be when all elimination
2197 pairs are back to their initial offsets. */
2199 if (SET_DEST (x
) != pc_rtx
)
2202 switch (GET_CODE (SET_SRC (x
)))
2209 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2213 tem
= XEXP (SET_SRC (x
), 1);
2214 if (GET_CODE (tem
) == LABEL_REF
)
2215 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2216 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2219 tem
= XEXP (SET_SRC (x
), 2);
2220 if (GET_CODE (tem
) == LABEL_REF
)
2221 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2222 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2230 /* If we reach here, all eliminations must be at their initial
2231 offset because we are doing a jump to a variable address. */
2232 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2233 if (p
->offset
!= p
->initial_offset
)
2234 p
->can_eliminate
= 0;
2242 /* Scan X and replace any eliminable registers (such as fp) with a
2243 replacement (such as sp), plus an offset.
2245 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2246 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2247 MEM, we are allowed to replace a sum of a register and the constant zero
2248 with the register, which we cannot do outside a MEM. In addition, we need
2249 to record the fact that a register is referenced outside a MEM.
2251 If INSN is an insn, it is the insn containing X. If we replace a REG
2252 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2253 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2254 the REG is being modified.
2256 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2257 That's used when we eliminate in expressions stored in notes.
2258 This means, do not set ref_outside_mem even if the reference
2261 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2262 replacements done assuming all offsets are at their initial values. If
2263 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2264 encounter, return the actual location so that find_reloads will do
2265 the proper thing. */
2268 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2269 bool may_use_invariant
)
2271 enum rtx_code code
= GET_CODE (x
);
2272 struct elim_table
*ep
;
2279 if (! current_function_decl
)
2301 /* First handle the case where we encounter a bare register that
2302 is eliminable. Replace it with a PLUS. */
2303 if (regno
< FIRST_PSEUDO_REGISTER
)
2305 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2307 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2308 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2311 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2312 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2314 if (may_use_invariant
)
2315 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2316 mem_mode
, insn
, true);
2317 /* There exists at least one use of REGNO that cannot be
2318 eliminated. Prevent the defining insn from being deleted. */
2319 reg_equiv_init
[regno
] = NULL_RTX
;
2320 alter_reg (regno
, -1);
2324 /* You might think handling MINUS in a manner similar to PLUS is a
2325 good idea. It is not. It has been tried multiple times and every
2326 time the change has had to have been reverted.
2328 Other parts of reload know a PLUS is special (gen_reload for example)
2329 and require special code to handle code a reloaded PLUS operand.
2331 Also consider backends where the flags register is clobbered by a
2332 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2333 lea instruction comes to mind). If we try to reload a MINUS, we
2334 may kill the flags register that was holding a useful value.
2336 So, please before trying to handle MINUS, consider reload as a
2337 whole instead of this little section as well as the backend issues. */
2339 /* If this is the sum of an eliminable register and a constant, rework
2341 if (REG_P (XEXP (x
, 0))
2342 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2343 && CONSTANT_P (XEXP (x
, 1)))
2345 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2347 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2349 /* The only time we want to replace a PLUS with a REG (this
2350 occurs when the constant operand of the PLUS is the negative
2351 of the offset) is when we are inside a MEM. We won't want
2352 to do so at other times because that would change the
2353 structure of the insn in a way that reload can't handle.
2354 We special-case the commonest situation in
2355 eliminate_regs_in_insn, so just replace a PLUS with a
2356 PLUS here, unless inside a MEM. */
2357 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2358 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2361 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2362 plus_constant (XEXP (x
, 1),
2363 ep
->previous_offset
));
2366 /* If the register is not eliminable, we are done since the other
2367 operand is a constant. */
2371 /* If this is part of an address, we want to bring any constant to the
2372 outermost PLUS. We will do this by doing register replacement in
2373 our operands and seeing if a constant shows up in one of them.
2375 Note that there is no risk of modifying the structure of the insn,
2376 since we only get called for its operands, thus we are either
2377 modifying the address inside a MEM, or something like an address
2378 operand of a load-address insn. */
2381 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2382 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2384 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2386 /* If one side is a PLUS and the other side is a pseudo that
2387 didn't get a hard register but has a reg_equiv_constant,
2388 we must replace the constant here since it may no longer
2389 be in the position of any operand. */
2390 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2391 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber
[REGNO (new1
)] < 0
2393 && reg_equiv_constant
!= 0
2394 && reg_equiv_constant
[REGNO (new1
)] != 0)
2395 new1
= reg_equiv_constant
[REGNO (new1
)];
2396 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2397 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2398 && reg_renumber
[REGNO (new0
)] < 0
2399 && reg_equiv_constant
[REGNO (new0
)] != 0)
2400 new0
= reg_equiv_constant
[REGNO (new0
)];
2402 new = form_sum (new0
, new1
);
2404 /* As above, if we are not inside a MEM we do not want to
2405 turn a PLUS into something else. We might try to do so here
2406 for an addition of 0 if we aren't optimizing. */
2407 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2408 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2416 /* If this is the product of an eliminable register and a
2417 constant, apply the distribute law and move the constant out
2418 so that we have (plus (mult ..) ..). This is needed in order
2419 to keep load-address insns valid. This case is pathological.
2420 We ignore the possibility of overflow here. */
2421 if (REG_P (XEXP (x
, 0))
2422 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2423 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2424 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2426 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2429 /* Refs inside notes don't count for this purpose. */
2430 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2431 || GET_CODE (insn
) == INSN_LIST
)))
2432 ep
->ref_outside_mem
= 1;
2435 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2436 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2439 /* ... fall through ... */
2443 /* See comments before PLUS about handling MINUS. */
2445 case DIV
: case UDIV
:
2446 case MOD
: case UMOD
:
2447 case AND
: case IOR
: case XOR
:
2448 case ROTATERT
: case ROTATE
:
2449 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2451 case GE
: case GT
: case GEU
: case GTU
:
2452 case LE
: case LT
: case LEU
: case LTU
:
2454 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2455 rtx new1
= XEXP (x
, 1)
2456 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false) : 0;
2458 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2459 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2464 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2467 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2468 if (new != XEXP (x
, 0))
2470 /* If this is a REG_DEAD note, it is not valid anymore.
2471 Using the eliminated version could result in creating a
2472 REG_DEAD note for the stack or frame pointer. */
2473 if (GET_MODE (x
) == REG_DEAD
)
2475 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true)
2478 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2482 /* ... fall through ... */
2485 /* Now do eliminations in the rest of the chain. If this was
2486 an EXPR_LIST, this might result in allocating more memory than is
2487 strictly needed, but it simplifies the code. */
2490 new = eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2491 if (new != XEXP (x
, 1))
2493 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2501 case STRICT_LOW_PART
:
2503 case SIGN_EXTEND
: case ZERO_EXTEND
:
2504 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2505 case FLOAT
: case FIX
:
2506 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2514 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2515 if (new != XEXP (x
, 0))
2516 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2520 /* Similar to above processing, but preserve SUBREG_BYTE.
2521 Convert (subreg (mem)) to (mem) if not paradoxical.
2522 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2523 pseudo didn't get a hard reg, we must replace this with the
2524 eliminated version of the memory location because push_reload
2525 may do the replacement in certain circumstances. */
2526 if (REG_P (SUBREG_REG (x
))
2527 && (GET_MODE_SIZE (GET_MODE (x
))
2528 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2529 && reg_equiv_memory_loc
!= 0
2530 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2532 new = SUBREG_REG (x
);
2535 new = eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false);
2537 if (new != SUBREG_REG (x
))
2539 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2540 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2543 && ((x_size
< new_size
2544 #ifdef WORD_REGISTER_OPERATIONS
2545 /* On these machines, combine can create rtl of the form
2546 (set (subreg:m1 (reg:m2 R) 0) ...)
2547 where m1 < m2, and expects something interesting to
2548 happen to the entire word. Moreover, it will use the
2549 (reg:m2 R) later, expecting all bits to be preserved.
2550 So if the number of words is the same, preserve the
2551 subreg so that push_reload can see it. */
2552 && ! ((x_size
- 1) / UNITS_PER_WORD
2553 == (new_size
-1 ) / UNITS_PER_WORD
)
2556 || x_size
== new_size
)
2558 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2560 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2566 /* Our only special processing is to pass the mode of the MEM to our
2567 recursive call and copy the flags. While we are here, handle this
2568 case more efficiently. */
2570 replace_equiv_address_nv (x
,
2571 eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
),
2575 /* Handle insn_list USE that a call to a pure function may generate. */
2576 new = eliminate_regs_1 (XEXP (x
, 0), 0, insn
, false);
2577 if (new != XEXP (x
, 0))
2578 return gen_rtx_USE (GET_MODE (x
), new);
2590 /* Process each of our operands recursively. If any have changed, make a
2592 fmt
= GET_RTX_FORMAT (code
);
2593 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2597 new = eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false);
2598 if (new != XEXP (x
, i
) && ! copied
)
2600 rtx new_x
= rtx_alloc (code
);
2601 memcpy (new_x
, x
, RTX_SIZE (code
));
2607 else if (*fmt
== 'E')
2610 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2612 new = eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false);
2613 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2615 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2619 rtx new_x
= rtx_alloc (code
);
2620 memcpy (new_x
, x
, RTX_SIZE (code
));
2624 XVEC (x
, i
) = new_v
;
2627 XVECEXP (x
, i
, j
) = new;
2636 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2638 return eliminate_regs_1 (x
, mem_mode
, insn
, false);
2641 /* Scan rtx X for modifications of elimination target registers. Update
2642 the table of eliminables to reflect the changed state. MEM_MODE is
2643 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2646 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2648 enum rtx_code code
= GET_CODE (x
);
2649 struct elim_table
*ep
;
2673 /* First handle the case where we encounter a bare register that
2674 is eliminable. Replace it with a PLUS. */
2675 if (regno
< FIRST_PSEUDO_REGISTER
)
2677 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2679 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2682 ep
->ref_outside_mem
= 1;
2687 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2688 && reg_equiv_constant
[regno
]
2689 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2690 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2699 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2700 if (ep
->to_rtx
== XEXP (x
, 0))
2702 int size
= GET_MODE_SIZE (mem_mode
);
2704 /* If more bytes than MEM_MODE are pushed, account for them. */
2705 #ifdef PUSH_ROUNDING
2706 if (ep
->to_rtx
== stack_pointer_rtx
)
2707 size
= PUSH_ROUNDING (size
);
2709 if (code
== PRE_DEC
|| code
== POST_DEC
)
2711 else if (code
== PRE_INC
|| code
== POST_INC
)
2713 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2714 && GET_CODE (XEXP (x
, 1)) == PLUS
2715 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2716 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2717 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2720 /* These two aren't unary operators. */
2721 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2724 /* Fall through to generic unary operation case. */
2725 case STRICT_LOW_PART
:
2727 case SIGN_EXTEND
: case ZERO_EXTEND
:
2728 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2729 case FLOAT
: case FIX
:
2730 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2738 elimination_effects (XEXP (x
, 0), mem_mode
);
2742 if (REG_P (SUBREG_REG (x
))
2743 && (GET_MODE_SIZE (GET_MODE (x
))
2744 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2745 && reg_equiv_memory_loc
!= 0
2746 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2749 elimination_effects (SUBREG_REG (x
), mem_mode
);
2753 /* If using a register that is the source of an eliminate we still
2754 think can be performed, note it cannot be performed since we don't
2755 know how this register is used. */
2756 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2757 if (ep
->from_rtx
== XEXP (x
, 0))
2758 ep
->can_eliminate
= 0;
2760 elimination_effects (XEXP (x
, 0), mem_mode
);
2764 /* If clobbering a register that is the replacement register for an
2765 elimination we still think can be performed, note that it cannot
2766 be performed. Otherwise, we need not be concerned about it. */
2767 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2768 if (ep
->to_rtx
== XEXP (x
, 0))
2769 ep
->can_eliminate
= 0;
2771 elimination_effects (XEXP (x
, 0), mem_mode
);
2775 /* Check for setting a register that we know about. */
2776 if (REG_P (SET_DEST (x
)))
2778 /* See if this is setting the replacement register for an
2781 If DEST is the hard frame pointer, we do nothing because we
2782 assume that all assignments to the frame pointer are for
2783 non-local gotos and are being done at a time when they are valid
2784 and do not disturb anything else. Some machines want to
2785 eliminate a fake argument pointer (or even a fake frame pointer)
2786 with either the real frame or the stack pointer. Assignments to
2787 the hard frame pointer must not prevent this elimination. */
2789 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2791 if (ep
->to_rtx
== SET_DEST (x
)
2792 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2794 /* If it is being incremented, adjust the offset. Otherwise,
2795 this elimination can't be done. */
2796 rtx src
= SET_SRC (x
);
2798 if (GET_CODE (src
) == PLUS
2799 && XEXP (src
, 0) == SET_DEST (x
)
2800 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2801 ep
->offset
-= INTVAL (XEXP (src
, 1));
2803 ep
->can_eliminate
= 0;
2807 elimination_effects (SET_DEST (x
), 0);
2808 elimination_effects (SET_SRC (x
), 0);
2812 /* Our only special processing is to pass the mode of the MEM to our
2814 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2821 fmt
= GET_RTX_FORMAT (code
);
2822 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2825 elimination_effects (XEXP (x
, i
), mem_mode
);
2826 else if (*fmt
== 'E')
2827 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2828 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2832 /* Descend through rtx X and verify that no references to eliminable registers
2833 remain. If any do remain, mark the involved register as not
2837 check_eliminable_occurrences (rtx x
)
2846 code
= GET_CODE (x
);
2848 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2850 struct elim_table
*ep
;
2852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2853 if (ep
->from_rtx
== x
)
2854 ep
->can_eliminate
= 0;
2858 fmt
= GET_RTX_FORMAT (code
);
2859 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2862 check_eliminable_occurrences (XEXP (x
, i
));
2863 else if (*fmt
== 'E')
2866 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2867 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2872 /* Scan INSN and eliminate all eliminable registers in it.
2874 If REPLACE is nonzero, do the replacement destructively. Also
2875 delete the insn as dead it if it is setting an eliminable register.
2877 If REPLACE is zero, do all our allocations in reload_obstack.
2879 If no eliminations were done and this insn doesn't require any elimination
2880 processing (these are not identical conditions: it might be updating sp,
2881 but not referencing fp; this needs to be seen during reload_as_needed so
2882 that the offset between fp and sp can be taken into consideration), zero
2883 is returned. Otherwise, 1 is returned. */
2886 eliminate_regs_in_insn (rtx insn
, int replace
)
2888 int icode
= recog_memoized (insn
);
2889 rtx old_body
= PATTERN (insn
);
2890 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2891 rtx old_set
= single_set (insn
);
2895 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2896 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2897 struct elim_table
*ep
;
2898 rtx plus_src
, plus_cst_src
;
2900 if (! insn_is_asm
&& icode
< 0)
2902 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
2903 || GET_CODE (PATTERN (insn
)) == CLOBBER
2904 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2905 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2906 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
2910 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
2911 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2913 /* Check for setting an eliminable register. */
2914 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2915 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2917 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2918 /* If this is setting the frame pointer register to the
2919 hardware frame pointer register and this is an elimination
2920 that will be done (tested above), this insn is really
2921 adjusting the frame pointer downward to compensate for
2922 the adjustment done before a nonlocal goto. */
2923 if (ep
->from
== FRAME_POINTER_REGNUM
2924 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2926 rtx base
= SET_SRC (old_set
);
2927 rtx base_insn
= insn
;
2928 HOST_WIDE_INT offset
= 0;
2930 while (base
!= ep
->to_rtx
)
2932 rtx prev_insn
, prev_set
;
2934 if (GET_CODE (base
) == PLUS
2935 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
2937 offset
+= INTVAL (XEXP (base
, 1));
2938 base
= XEXP (base
, 0);
2940 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
2941 && (prev_set
= single_set (prev_insn
)) != 0
2942 && rtx_equal_p (SET_DEST (prev_set
), base
))
2944 base
= SET_SRC (prev_set
);
2945 base_insn
= prev_insn
;
2951 if (base
== ep
->to_rtx
)
2954 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2956 new_body
= old_body
;
2959 new_body
= copy_insn (old_body
);
2960 if (REG_NOTES (insn
))
2961 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2963 PATTERN (insn
) = new_body
;
2964 old_set
= single_set (insn
);
2966 /* First see if this insn remains valid when we
2967 make the change. If not, keep the INSN_CODE
2968 the same and let reload fit it up. */
2969 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2970 validate_change (insn
, &SET_DEST (old_set
),
2972 if (! apply_change_group ())
2974 SET_SRC (old_set
) = src
;
2975 SET_DEST (old_set
) = ep
->to_rtx
;
2984 /* In this case this insn isn't serving a useful purpose. We
2985 will delete it in reload_as_needed once we know that this
2986 elimination is, in fact, being done.
2988 If REPLACE isn't set, we can't delete this insn, but needn't
2989 process it since it won't be used unless something changes. */
2992 delete_dead_insn (insn
);
3000 /* We allow one special case which happens to work on all machines we
3001 currently support: a single set with the source or a REG_EQUAL
3002 note being a PLUS of an eliminable register and a constant. */
3003 plus_src
= plus_cst_src
= 0;
3004 if (old_set
&& REG_P (SET_DEST (old_set
)))
3006 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3007 plus_src
= SET_SRC (old_set
);
3008 /* First see if the source is of the form (plus (reg) CST). */
3010 && REG_P (XEXP (plus_src
, 0))
3011 && GET_CODE (XEXP (plus_src
, 1)) == CONST_INT
3012 && REGNO (XEXP (plus_src
, 0)) < FIRST_PSEUDO_REGISTER
)
3013 plus_cst_src
= plus_src
;
3014 else if (REG_P (SET_SRC (old_set
))
3017 /* Otherwise, see if we have a REG_EQUAL note of the form
3018 (plus (reg) CST). */
3020 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3022 if (REG_NOTE_KIND (links
) == REG_EQUAL
3023 && GET_CODE (XEXP (links
, 0)) == PLUS
3024 && REG_P (XEXP (XEXP (links
, 0), 0))
3025 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
3026 && REGNO (XEXP (XEXP (links
, 0), 0)) < FIRST_PSEUDO_REGISTER
)
3028 plus_cst_src
= XEXP (links
, 0);
3036 rtx reg
= XEXP (plus_cst_src
, 0);
3037 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3039 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3040 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3042 offset
+= ep
->offset
;
3047 /* We assume here that if we need a PARALLEL with
3048 CLOBBERs for this assignment, we can do with the
3049 MATCH_SCRATCHes that add_clobbers allocates.
3050 There's not much we can do if that doesn't work. */
3051 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3055 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3058 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3060 vec
->elem
[0] = PATTERN (insn
);
3061 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3062 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3064 gcc_assert (INSN_CODE (insn
) >= 0);
3066 /* If we have a nonzero offset, and the source is already
3067 a simple REG, the following transformation would
3068 increase the cost of the insn by replacing a simple REG
3069 with (plus (reg sp) CST). So try only when we already
3070 had a PLUS before. */
3073 new_body
= old_body
;
3076 new_body
= copy_insn (old_body
);
3077 if (REG_NOTES (insn
))
3078 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3080 PATTERN (insn
) = new_body
;
3081 old_set
= single_set (insn
);
3083 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3084 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3090 /* This can't have an effect on elimination offsets, so skip right
3096 /* Determine the effects of this insn on elimination offsets. */
3097 elimination_effects (old_body
, 0);
3099 /* Eliminate all eliminable registers occurring in operands that
3100 can be handled by reload. */
3101 extract_insn (insn
);
3102 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3104 orig_operand
[i
] = recog_data
.operand
[i
];
3105 substed_operand
[i
] = recog_data
.operand
[i
];
3107 /* For an asm statement, every operand is eliminable. */
3108 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3110 bool is_set_src
, in_plus
;
3112 /* Check for setting a register that we know about. */
3113 if (recog_data
.operand_type
[i
] != OP_IN
3114 && REG_P (orig_operand
[i
]))
3116 /* If we are assigning to a register that can be eliminated, it
3117 must be as part of a PARALLEL, since the code above handles
3118 single SETs. We must indicate that we can no longer
3119 eliminate this reg. */
3120 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3122 if (ep
->from_rtx
== orig_operand
[i
])
3123 ep
->can_eliminate
= 0;
3126 /* Companion to the above plus substitution, we can allow
3127 invariants as the source of a plain move. */
3129 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3133 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3134 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3138 = eliminate_regs_1 (recog_data
.operand
[i
], 0,
3139 replace
? insn
: NULL_RTX
,
3140 is_set_src
|| in_plus
);
3141 if (substed_operand
[i
] != orig_operand
[i
])
3143 /* Terminate the search in check_eliminable_occurrences at
3145 *recog_data
.operand_loc
[i
] = 0;
3147 /* If an output operand changed from a REG to a MEM and INSN is an
3148 insn, write a CLOBBER insn. */
3149 if (recog_data
.operand_type
[i
] != OP_IN
3150 && REG_P (orig_operand
[i
])
3151 && MEM_P (substed_operand
[i
])
3153 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3158 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3159 *recog_data
.dup_loc
[i
]
3160 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3162 /* If any eliminable remain, they aren't eliminable anymore. */
3163 check_eliminable_occurrences (old_body
);
3165 /* Substitute the operands; the new values are in the substed_operand
3167 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3168 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3169 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3170 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3172 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3173 re-recognize the insn. We do this in case we had a simple addition
3174 but now can do this as a load-address. This saves an insn in this
3176 If re-recognition fails, the old insn code number will still be used,
3177 and some register operands may have changed into PLUS expressions.
3178 These will be handled by find_reloads by loading them into a register
3183 /* If we aren't replacing things permanently and we changed something,
3184 make another copy to ensure that all the RTL is new. Otherwise
3185 things can go wrong if find_reload swaps commutative operands
3186 and one is inside RTL that has been copied while the other is not. */
3187 new_body
= old_body
;
3190 new_body
= copy_insn (old_body
);
3191 if (REG_NOTES (insn
))
3192 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3194 PATTERN (insn
) = new_body
;
3196 /* If we had a move insn but now we don't, rerecognize it. This will
3197 cause spurious re-recognition if the old move had a PARALLEL since
3198 the new one still will, but we can't call single_set without
3199 having put NEW_BODY into the insn and the re-recognition won't
3200 hurt in this rare case. */
3201 /* ??? Why this huge if statement - why don't we just rerecognize the
3205 && ((REG_P (SET_SRC (old_set
))
3206 && (GET_CODE (new_body
) != SET
3207 || !REG_P (SET_SRC (new_body
))))
3208 /* If this was a load from or store to memory, compare
3209 the MEM in recog_data.operand to the one in the insn.
3210 If they are not equal, then rerecognize the insn. */
3212 && ((MEM_P (SET_SRC (old_set
))
3213 && SET_SRC (old_set
) != recog_data
.operand
[1])
3214 || (MEM_P (SET_DEST (old_set
))
3215 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3216 /* If this was an add insn before, rerecognize. */
3217 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3219 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3221 INSN_CODE (insn
) = icode
;
3225 /* Restore the old body. If there were any changes to it, we made a copy
3226 of it while the changes were still in place, so we'll correctly return
3227 a modified insn below. */
3230 /* Restore the old body. */
3231 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3232 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3233 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3234 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3237 /* Update all elimination pairs to reflect the status after the current
3238 insn. The changes we make were determined by the earlier call to
3239 elimination_effects.
3241 We also detect cases where register elimination cannot be done,
3242 namely, if a register would be both changed and referenced outside a MEM
3243 in the resulting insn since such an insn is often undefined and, even if
3244 not, we cannot know what meaning will be given to it. Note that it is
3245 valid to have a register used in an address in an insn that changes it
3246 (presumably with a pre- or post-increment or decrement).
3248 If anything changes, return nonzero. */
3250 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3252 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3253 ep
->can_eliminate
= 0;
3255 ep
->ref_outside_mem
= 0;
3257 if (ep
->previous_offset
!= ep
->offset
)
3262 /* If we changed something, perform elimination in REG_NOTES. This is
3263 needed even when REPLACE is zero because a REG_DEAD note might refer
3264 to a register that we eliminate and could cause a different number
3265 of spill registers to be needed in the final reload pass than in
3267 if (val
&& REG_NOTES (insn
) != 0)
3269 = eliminate_regs_1 (REG_NOTES (insn
), 0, REG_NOTES (insn
), true);
3274 /* Loop through all elimination pairs.
3275 Recalculate the number not at initial offset.
3277 Compute the maximum offset (minimum offset if the stack does not
3278 grow downward) for each elimination pair. */
3281 update_eliminable_offsets (void)
3283 struct elim_table
*ep
;
3285 num_not_at_initial_offset
= 0;
3286 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3288 ep
->previous_offset
= ep
->offset
;
3289 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3290 num_not_at_initial_offset
++;
3294 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3295 replacement we currently believe is valid, mark it as not eliminable if X
3296 modifies DEST in any way other than by adding a constant integer to it.
3298 If DEST is the frame pointer, we do nothing because we assume that
3299 all assignments to the hard frame pointer are nonlocal gotos and are being
3300 done at a time when they are valid and do not disturb anything else.
3301 Some machines want to eliminate a fake argument pointer with either the
3302 frame or stack pointer. Assignments to the hard frame pointer must not
3303 prevent this elimination.
3305 Called via note_stores from reload before starting its passes to scan
3306 the insns of the function. */
3309 mark_not_eliminable (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
3313 /* A SUBREG of a hard register here is just changing its mode. We should
3314 not see a SUBREG of an eliminable hard register, but check just in
3316 if (GET_CODE (dest
) == SUBREG
)
3317 dest
= SUBREG_REG (dest
);
3319 if (dest
== hard_frame_pointer_rtx
)
3322 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3323 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3324 && (GET_CODE (x
) != SET
3325 || GET_CODE (SET_SRC (x
)) != PLUS
3326 || XEXP (SET_SRC (x
), 0) != dest
3327 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3329 reg_eliminate
[i
].can_eliminate_previous
3330 = reg_eliminate
[i
].can_eliminate
= 0;
3335 /* Verify that the initial elimination offsets did not change since the
3336 last call to set_initial_elim_offsets. This is used to catch cases
3337 where something illegal happened during reload_as_needed that could
3338 cause incorrect code to be generated if we did not check for it. */
3341 verify_initial_elim_offsets (void)
3345 if (!num_eliminable
)
3348 #ifdef ELIMINABLE_REGS
3350 struct elim_table
*ep
;
3352 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3354 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3355 if (t
!= ep
->initial_offset
)
3360 INITIAL_FRAME_POINTER_OFFSET (t
);
3361 if (t
!= reg_eliminate
[0].initial_offset
)
3368 /* Reset all offsets on eliminable registers to their initial values. */
3371 set_initial_elim_offsets (void)
3373 struct elim_table
*ep
= reg_eliminate
;
3375 #ifdef ELIMINABLE_REGS
3376 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3378 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3379 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3382 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3383 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3386 num_not_at_initial_offset
= 0;
3389 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3392 set_initial_eh_label_offset (rtx label
)
3394 set_label_offsets (label
, NULL_RTX
, 1);
3397 /* Initialize the known label offsets.
3398 Set a known offset for each forced label to be at the initial offset
3399 of each elimination. We do this because we assume that all
3400 computed jumps occur from a location where each elimination is
3401 at its initial offset.
3402 For all other labels, show that we don't know the offsets. */
3405 set_initial_label_offsets (void)
3408 memset (offsets_known_at
, 0, num_labels
);
3410 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3412 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3414 for_each_eh_label (set_initial_eh_label_offset
);
3417 /* Set all elimination offsets to the known values for the code label given
3421 set_offsets_for_label (rtx insn
)
3424 int label_nr
= CODE_LABEL_NUMBER (insn
);
3425 struct elim_table
*ep
;
3427 num_not_at_initial_offset
= 0;
3428 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3430 ep
->offset
= ep
->previous_offset
3431 = offsets_at
[label_nr
- first_label_num
][i
];
3432 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3433 num_not_at_initial_offset
++;
3437 /* See if anything that happened changes which eliminations are valid.
3438 For example, on the SPARC, whether or not the frame pointer can
3439 be eliminated can depend on what registers have been used. We need
3440 not check some conditions again (such as flag_omit_frame_pointer)
3441 since they can't have changed. */
3444 update_eliminables (HARD_REG_SET
*pset
)
3446 int previous_frame_pointer_needed
= frame_pointer_needed
;
3447 struct elim_table
*ep
;
3449 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3450 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3451 #ifdef ELIMINABLE_REGS
3452 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3455 ep
->can_eliminate
= 0;
3457 /* Look for the case where we have discovered that we can't replace
3458 register A with register B and that means that we will now be
3459 trying to replace register A with register C. This means we can
3460 no longer replace register C with register B and we need to disable
3461 such an elimination, if it exists. This occurs often with A == ap,
3462 B == sp, and C == fp. */
3464 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3466 struct elim_table
*op
;
3469 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3471 /* Find the current elimination for ep->from, if there is a
3473 for (op
= reg_eliminate
;
3474 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3475 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3481 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3483 for (op
= reg_eliminate
;
3484 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3485 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3486 op
->can_eliminate
= 0;
3490 /* See if any registers that we thought we could eliminate the previous
3491 time are no longer eliminable. If so, something has changed and we
3492 must spill the register. Also, recompute the number of eliminable
3493 registers and see if the frame pointer is needed; it is if there is
3494 no elimination of the frame pointer that we can perform. */
3496 frame_pointer_needed
= 1;
3497 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3499 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3500 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3501 frame_pointer_needed
= 0;
3503 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3505 ep
->can_eliminate_previous
= 0;
3506 SET_HARD_REG_BIT (*pset
, ep
->from
);
3511 /* If we didn't need a frame pointer last time, but we do now, spill
3512 the hard frame pointer. */
3513 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3514 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3517 /* Initialize the table of registers to eliminate. */
3520 init_elim_table (void)
3522 struct elim_table
*ep
;
3523 #ifdef ELIMINABLE_REGS
3524 const struct elim_table_1
*ep1
;
3528 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3530 /* Does this function require a frame pointer? */
3532 frame_pointer_needed
= (! flag_omit_frame_pointer
3533 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3534 and restore sp for alloca. So we can't eliminate
3535 the frame pointer in that case. At some point,
3536 we should improve this by emitting the
3537 sp-adjusting insns for this case. */
3538 || (current_function_calls_alloca
3539 && EXIT_IGNORE_STACK
)
3540 || current_function_accesses_prior_frames
3541 || FRAME_POINTER_REQUIRED
);
3545 #ifdef ELIMINABLE_REGS
3546 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3547 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3549 ep
->from
= ep1
->from
;
3551 ep
->can_eliminate
= ep
->can_eliminate_previous
3552 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3553 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3556 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3557 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3558 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3559 = ! frame_pointer_needed
;
3562 /* Count the number of eliminable registers and build the FROM and TO
3563 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3564 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3565 We depend on this. */
3566 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3568 num_eliminable
+= ep
->can_eliminate
;
3569 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3570 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3574 /* Kick all pseudos out of hard register REGNO.
3576 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3577 because we found we can't eliminate some register. In the case, no pseudos
3578 are allowed to be in the register, even if they are only in a block that
3579 doesn't require spill registers, unlike the case when we are spilling this
3580 hard reg to produce another spill register.
3582 Return nonzero if any pseudos needed to be kicked out. */
3585 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3591 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3592 regs_ever_live
[regno
] = 1;
3595 /* Spill every pseudo reg that was allocated to this reg
3596 or to something that overlaps this reg. */
3598 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3599 if (reg_renumber
[i
] >= 0
3600 && (unsigned int) reg_renumber
[i
] <= regno
3601 && ((unsigned int) reg_renumber
[i
]
3602 + hard_regno_nregs
[(unsigned int) reg_renumber
[i
]]
3603 [PSEUDO_REGNO_MODE (i
)]
3605 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3608 /* After find_reload_regs has been run for all insn that need reloads,
3609 and/or spill_hard_regs was called, this function is used to actually
3610 spill pseudo registers and try to reallocate them. It also sets up the
3611 spill_regs array for use by choose_reload_regs. */
3614 finish_spills (int global
)
3616 struct insn_chain
*chain
;
3617 int something_changed
= 0;
3619 reg_set_iterator rsi
;
3621 /* Build the spill_regs array for the function. */
3622 /* If there are some registers still to eliminate and one of the spill regs
3623 wasn't ever used before, additional stack space may have to be
3624 allocated to store this register. Thus, we may have changed the offset
3625 between the stack and frame pointers, so mark that something has changed.
3627 One might think that we need only set VAL to 1 if this is a call-used
3628 register. However, the set of registers that must be saved by the
3629 prologue is not identical to the call-used set. For example, the
3630 register used by the call insn for the return PC is a call-used register,
3631 but must be saved by the prologue. */
3634 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3635 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3637 spill_reg_order
[i
] = n_spills
;
3638 spill_regs
[n_spills
++] = i
;
3639 if (num_eliminable
&& ! regs_ever_live
[i
])
3640 something_changed
= 1;
3641 regs_ever_live
[i
] = 1;
3644 spill_reg_order
[i
] = -1;
3646 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3648 /* Record the current hard register the pseudo is allocated to in
3649 pseudo_previous_regs so we avoid reallocating it to the same
3650 hard reg in a later pass. */
3651 gcc_assert (reg_renumber
[i
] >= 0);
3653 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3654 /* Mark it as no longer having a hard register home. */
3655 reg_renumber
[i
] = -1;
3656 /* We will need to scan everything again. */
3657 something_changed
= 1;
3660 /* Retry global register allocation if possible. */
3663 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3664 /* For every insn that needs reloads, set the registers used as spill
3665 regs in pseudo_forbidden_regs for every pseudo live across the
3667 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3669 EXECUTE_IF_SET_IN_REG_SET
3670 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3672 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3673 chain
->used_spill_regs
);
3675 EXECUTE_IF_SET_IN_REG_SET
3676 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3678 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3679 chain
->used_spill_regs
);
3683 /* Retry allocating the spilled pseudos. For each reg, merge the
3684 various reg sets that indicate which hard regs can't be used,
3685 and call retry_global_alloc.
3686 We change spill_pseudos here to only contain pseudos that did not
3687 get a new hard register. */
3688 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3689 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3691 HARD_REG_SET forbidden
;
3692 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3693 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3694 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3695 retry_global_alloc (i
, forbidden
);
3696 if (reg_renumber
[i
] >= 0)
3697 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3701 /* Fix up the register information in the insn chain.
3702 This involves deleting those of the spilled pseudos which did not get
3703 a new hard register home from the live_{before,after} sets. */
3704 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3706 HARD_REG_SET used_by_pseudos
;
3707 HARD_REG_SET used_by_pseudos2
;
3709 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3710 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3712 /* Mark any unallocated hard regs as available for spills. That
3713 makes inheritance work somewhat better. */
3714 if (chain
->need_reload
)
3716 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3717 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3718 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3720 /* Save the old value for the sanity test below. */
3721 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3723 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3724 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3725 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3726 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3728 /* Make sure we only enlarge the set. */
3729 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3735 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3736 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3738 int regno
= reg_renumber
[i
];
3739 if (reg_old_renumber
[i
] == regno
)
3742 alter_reg (i
, reg_old_renumber
[i
]);
3743 reg_old_renumber
[i
] = regno
;
3747 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
3749 fprintf (dump_file
, " Register %d now in %d.\n\n",
3750 i
, reg_renumber
[i
]);
3754 return something_changed
;
3757 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3760 scan_paradoxical_subregs (rtx x
)
3764 enum rtx_code code
= GET_CODE (x
);
3774 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3782 if (REG_P (SUBREG_REG (x
))
3783 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3784 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3785 = GET_MODE_SIZE (GET_MODE (x
));
3792 fmt
= GET_RTX_FORMAT (code
);
3793 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3796 scan_paradoxical_subregs (XEXP (x
, i
));
3797 else if (fmt
[i
] == 'E')
3800 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3801 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3806 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3807 examine all of the reload insns between PREV and NEXT exclusive, and
3808 annotate all that may trap. */
3811 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
3813 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3814 unsigned int trap_count
;
3820 if (may_trap_p (PATTERN (insn
)))
3824 remove_note (insn
, note
);
3828 for (i
= NEXT_INSN (prev
); i
!= next
; i
= NEXT_INSN (i
))
3829 if (INSN_P (i
) && i
!= insn
&& may_trap_p (PATTERN (i
)))
3833 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (note
, 0), REG_NOTES (i
));
3837 /* Reload pseudo-registers into hard regs around each insn as needed.
3838 Additional register load insns are output before the insn that needs it
3839 and perhaps store insns after insns that modify the reloaded pseudo reg.
3841 reg_last_reload_reg and reg_reloaded_contents keep track of
3842 which registers are already available in reload registers.
3843 We update these for the reloads that we perform,
3844 as the insns are scanned. */
3847 reload_as_needed (int live_known
)
3849 struct insn_chain
*chain
;
3850 #if defined (AUTO_INC_DEC)
3855 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3856 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
3857 reg_last_reload_reg
= xcalloc (max_regno
, sizeof (rtx
));
3858 reg_has_output_reload
= xmalloc (max_regno
);
3859 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3860 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
3862 set_initial_elim_offsets ();
3864 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3867 rtx insn
= chain
->insn
;
3868 rtx old_next
= NEXT_INSN (insn
);
3870 /* If we pass a label, copy the offsets from the label information
3871 into the current offsets of each elimination. */
3873 set_offsets_for_label (insn
);
3875 else if (INSN_P (insn
))
3877 rtx oldpat
= copy_rtx (PATTERN (insn
));
3879 /* If this is a USE and CLOBBER of a MEM, ensure that any
3880 references to eliminable registers have been removed. */
3882 if ((GET_CODE (PATTERN (insn
)) == USE
3883 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3884 && MEM_P (XEXP (PATTERN (insn
), 0)))
3885 XEXP (XEXP (PATTERN (insn
), 0), 0)
3886 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3887 GET_MODE (XEXP (PATTERN (insn
), 0)),
3890 /* If we need to do register elimination processing, do so.
3891 This might delete the insn, in which case we are done. */
3892 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3894 eliminate_regs_in_insn (insn
, 1);
3897 update_eliminable_offsets ();
3902 /* If need_elim is nonzero but need_reload is zero, one might think
3903 that we could simply set n_reloads to 0. However, find_reloads
3904 could have done some manipulation of the insn (such as swapping
3905 commutative operands), and these manipulations are lost during
3906 the first pass for every insn that needs register elimination.
3907 So the actions of find_reloads must be redone here. */
3909 if (! chain
->need_elim
&& ! chain
->need_reload
3910 && ! chain
->need_operand_change
)
3912 /* First find the pseudo regs that must be reloaded for this insn.
3913 This info is returned in the tables reload_... (see reload.h).
3914 Also modify the body of INSN by substituting RELOAD
3915 rtx's for those pseudo regs. */
3918 memset (reg_has_output_reload
, 0, max_regno
);
3919 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3921 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3927 rtx next
= NEXT_INSN (insn
);
3930 prev
= PREV_INSN (insn
);
3932 /* Now compute which reload regs to reload them into. Perhaps
3933 reusing reload regs from previous insns, or else output
3934 load insns to reload them. Maybe output store insns too.
3935 Record the choices of reload reg in reload_reg_rtx. */
3936 choose_reload_regs (chain
);
3938 /* Merge any reloads that we didn't combine for fear of
3939 increasing the number of spill registers needed but now
3940 discover can be safely merged. */
3941 if (SMALL_REGISTER_CLASSES
)
3942 merge_assigned_reloads (insn
);
3944 /* Generate the insns to reload operands into or out of
3945 their reload regs. */
3946 emit_reload_insns (chain
);
3948 /* Substitute the chosen reload regs from reload_reg_rtx
3949 into the insn's body (or perhaps into the bodies of other
3950 load and store insn that we just made for reloading
3951 and that we moved the structure into). */
3952 subst_reloads (insn
);
3954 /* Adjust the exception region notes for loads and stores. */
3955 if (flag_non_call_exceptions
&& !CALL_P (insn
))
3956 fixup_eh_region_note (insn
, prev
, next
);
3958 /* If this was an ASM, make sure that all the reload insns
3959 we have generated are valid. If not, give an error
3961 if (asm_noperands (PATTERN (insn
)) >= 0)
3962 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3963 if (p
!= insn
&& INSN_P (p
)
3964 && GET_CODE (PATTERN (p
)) != USE
3965 && (recog_memoized (p
) < 0
3966 || (extract_insn (p
), ! constrain_operands (1))))
3968 error_for_asm (insn
,
3969 "%<asm%> operand requires "
3970 "impossible reload");
3975 if (num_eliminable
&& chain
->need_elim
)
3976 update_eliminable_offsets ();
3978 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3979 is no longer validly lying around to save a future reload.
3980 Note that this does not detect pseudos that were reloaded
3981 for this insn in order to be stored in
3982 (obeying register constraints). That is correct; such reload
3983 registers ARE still valid. */
3984 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3986 /* There may have been CLOBBER insns placed after INSN. So scan
3987 between INSN and NEXT and use them to forget old reloads. */
3988 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3989 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
3990 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3993 /* Likewise for regs altered by auto-increment in this insn.
3994 REG_INC notes have been changed by reloading:
3995 find_reloads_address_1 records substitutions for them,
3996 which have been performed by subst_reloads above. */
3997 for (i
= n_reloads
- 1; i
>= 0; i
--)
3999 rtx in_reg
= rld
[i
].in_reg
;
4002 enum rtx_code code
= GET_CODE (in_reg
);
4003 /* PRE_INC / PRE_DEC will have the reload register ending up
4004 with the same value as the stack slot, but that doesn't
4005 hold true for POST_INC / POST_DEC. Either we have to
4006 convert the memory access to a true POST_INC / POST_DEC,
4007 or we can't use the reload register for inheritance. */
4008 if ((code
== POST_INC
|| code
== POST_DEC
)
4009 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4010 REGNO (rld
[i
].reg_rtx
))
4011 /* Make sure it is the inc/dec pseudo, and not
4012 some other (e.g. output operand) pseudo. */
4013 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4014 == REGNO (XEXP (in_reg
, 0))))
4017 rtx reload_reg
= rld
[i
].reg_rtx
;
4018 enum machine_mode mode
= GET_MODE (reload_reg
);
4022 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4024 /* We really want to ignore REG_INC notes here, so
4025 use PATTERN (p) as argument to reg_set_p . */
4026 if (reg_set_p (reload_reg
, PATTERN (p
)))
4028 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4033 n
= validate_replace_rtx (reload_reg
,
4034 gen_rtx_fmt_e (code
,
4039 /* We must also verify that the constraints
4040 are met after the replacement. */
4043 n
= constrain_operands (1);
4047 /* If the constraints were not met, then
4048 undo the replacement. */
4051 validate_replace_rtx (gen_rtx_fmt_e (code
,
4064 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4066 /* Mark this as having an output reload so that the
4067 REG_INC processing code below won't invalidate
4068 the reload for inheritance. */
4069 SET_HARD_REG_BIT (reg_is_output_reload
,
4070 REGNO (reload_reg
));
4071 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4074 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4077 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4078 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4079 REGNO (rld
[i
].reg_rtx
))
4080 /* Make sure it is the inc/dec pseudo, and not
4081 some other (e.g. output operand) pseudo. */
4082 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4083 == REGNO (XEXP (in_reg
, 0))))
4085 SET_HARD_REG_BIT (reg_is_output_reload
,
4086 REGNO (rld
[i
].reg_rtx
));
4087 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4091 /* If a pseudo that got a hard register is auto-incremented,
4092 we must purge records of copying it into pseudos without
4094 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4095 if (REG_NOTE_KIND (x
) == REG_INC
)
4097 /* See if this pseudo reg was reloaded in this insn.
4098 If so, its last-reload info is still valid
4099 because it is based on this insn's reload. */
4100 for (i
= 0; i
< n_reloads
; i
++)
4101 if (rld
[i
].out
== XEXP (x
, 0))
4105 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4109 /* A reload reg's contents are unknown after a label. */
4111 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4113 /* Don't assume a reload reg is still good after a call insn
4114 if it is a call-used reg, or if it contains a value that will
4115 be partially clobbered by the call. */
4116 else if (CALL_P (insn
))
4118 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4119 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4124 free (reg_last_reload_reg
);
4125 free (reg_has_output_reload
);
4128 /* Discard all record of any value reloaded from X,
4129 or reloaded in X from someplace else;
4130 unless X is an output reload reg of the current insn.
4132 X may be a hard reg (the reload reg)
4133 or it may be a pseudo reg that was reloaded from. */
4136 forget_old_reloads_1 (rtx x
, rtx ignored ATTRIBUTE_UNUSED
,
4137 void *data ATTRIBUTE_UNUSED
)
4142 /* note_stores does give us subregs of hard regs,
4143 subreg_regno_offset requires a hard reg. */
4144 while (GET_CODE (x
) == SUBREG
)
4146 /* We ignore the subreg offset when calculating the regno,
4147 because we are using the entire underlying hard register
4157 if (regno
>= FIRST_PSEUDO_REGISTER
)
4163 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4164 /* Storing into a spilled-reg invalidates its contents.
4165 This can happen if a block-local pseudo is allocated to that reg
4166 and it wasn't spilled because this block's total need is 0.
4167 Then some insn might have an optional reload and use this reg. */
4168 for (i
= 0; i
< nr
; i
++)
4169 /* But don't do this if the reg actually serves as an output
4170 reload reg in the current instruction. */
4172 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4174 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4175 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, regno
+ i
);
4176 spill_reg_store
[regno
+ i
] = 0;
4180 /* Since value of X has changed,
4181 forget any value previously copied from it. */
4184 /* But don't forget a copy if this is the output reload
4185 that establishes the copy's validity. */
4186 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4187 reg_last_reload_reg
[regno
+ nr
] = 0;
4190 /* The following HARD_REG_SETs indicate when each hard register is
4191 used for a reload of various parts of the current insn. */
4193 /* If reg is unavailable for all reloads. */
4194 static HARD_REG_SET reload_reg_unavailable
;
4195 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4196 static HARD_REG_SET reload_reg_used
;
4197 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4198 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4199 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4200 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4201 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4202 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4203 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4204 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4205 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4206 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4207 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4208 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4209 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4210 static HARD_REG_SET reload_reg_used_in_op_addr
;
4211 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4212 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4213 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4214 static HARD_REG_SET reload_reg_used_in_insn
;
4215 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4216 static HARD_REG_SET reload_reg_used_in_other_addr
;
4218 /* If reg is in use as a reload reg for any sort of reload. */
4219 static HARD_REG_SET reload_reg_used_at_all
;
4221 /* If reg is use as an inherited reload. We just mark the first register
4223 static HARD_REG_SET reload_reg_used_for_inherit
;
4225 /* Records which hard regs are used in any way, either as explicit use or
4226 by being allocated to a pseudo during any point of the current insn. */
4227 static HARD_REG_SET reg_used_in_insn
;
4229 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4230 TYPE. MODE is used to indicate how many consecutive regs are
4234 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4235 enum machine_mode mode
)
4237 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4240 for (i
= regno
; i
< nregs
+ regno
; i
++)
4245 SET_HARD_REG_BIT (reload_reg_used
, i
);
4248 case RELOAD_FOR_INPUT_ADDRESS
:
4249 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4252 case RELOAD_FOR_INPADDR_ADDRESS
:
4253 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4256 case RELOAD_FOR_OUTPUT_ADDRESS
:
4257 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4260 case RELOAD_FOR_OUTADDR_ADDRESS
:
4261 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4264 case RELOAD_FOR_OPERAND_ADDRESS
:
4265 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4268 case RELOAD_FOR_OPADDR_ADDR
:
4269 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4272 case RELOAD_FOR_OTHER_ADDRESS
:
4273 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4276 case RELOAD_FOR_INPUT
:
4277 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4280 case RELOAD_FOR_OUTPUT
:
4281 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4284 case RELOAD_FOR_INSN
:
4285 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4289 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4293 /* Similarly, but show REGNO is no longer in use for a reload. */
4296 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4297 enum reload_type type
, enum machine_mode mode
)
4299 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4300 unsigned int start_regno
, end_regno
, r
;
4302 /* A complication is that for some reload types, inheritance might
4303 allow multiple reloads of the same types to share a reload register.
4304 We set check_opnum if we have to check only reloads with the same
4305 operand number, and check_any if we have to check all reloads. */
4306 int check_opnum
= 0;
4308 HARD_REG_SET
*used_in_set
;
4313 used_in_set
= &reload_reg_used
;
4316 case RELOAD_FOR_INPUT_ADDRESS
:
4317 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4320 case RELOAD_FOR_INPADDR_ADDRESS
:
4322 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4325 case RELOAD_FOR_OUTPUT_ADDRESS
:
4326 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4329 case RELOAD_FOR_OUTADDR_ADDRESS
:
4331 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4334 case RELOAD_FOR_OPERAND_ADDRESS
:
4335 used_in_set
= &reload_reg_used_in_op_addr
;
4338 case RELOAD_FOR_OPADDR_ADDR
:
4340 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4343 case RELOAD_FOR_OTHER_ADDRESS
:
4344 used_in_set
= &reload_reg_used_in_other_addr
;
4348 case RELOAD_FOR_INPUT
:
4349 used_in_set
= &reload_reg_used_in_input
[opnum
];
4352 case RELOAD_FOR_OUTPUT
:
4353 used_in_set
= &reload_reg_used_in_output
[opnum
];
4356 case RELOAD_FOR_INSN
:
4357 used_in_set
= &reload_reg_used_in_insn
;
4362 /* We resolve conflicts with remaining reloads of the same type by
4363 excluding the intervals of reload registers by them from the
4364 interval of freed reload registers. Since we only keep track of
4365 one set of interval bounds, we might have to exclude somewhat
4366 more than what would be necessary if we used a HARD_REG_SET here.
4367 But this should only happen very infrequently, so there should
4368 be no reason to worry about it. */
4370 start_regno
= regno
;
4371 end_regno
= regno
+ nregs
;
4372 if (check_opnum
|| check_any
)
4374 for (i
= n_reloads
- 1; i
>= 0; i
--)
4376 if (rld
[i
].when_needed
== type
4377 && (check_any
|| rld
[i
].opnum
== opnum
)
4380 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4381 unsigned int conflict_end
4383 + hard_regno_nregs
[conflict_start
][rld
[i
].mode
]);
4385 /* If there is an overlap with the first to-be-freed register,
4386 adjust the interval start. */
4387 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4388 start_regno
= conflict_end
;
4389 /* Otherwise, if there is a conflict with one of the other
4390 to-be-freed registers, adjust the interval end. */
4391 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4392 end_regno
= conflict_start
;
4397 for (r
= start_regno
; r
< end_regno
; r
++)
4398 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4401 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4402 specified by OPNUM and TYPE. */
4405 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4409 /* In use for a RELOAD_OTHER means it's not available for anything. */
4410 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4411 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4417 /* In use for anything means we can't use it for RELOAD_OTHER. */
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4419 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4420 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4421 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4424 for (i
= 0; i
< reload_n_operands
; i
++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4428 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4429 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4430 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4435 case RELOAD_FOR_INPUT
:
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4443 /* If it is used for some other input, can't use it. */
4444 for (i
= 0; i
< reload_n_operands
; i
++)
4445 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4448 /* If it is used in a later operand's address, can't use it. */
4449 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4456 case RELOAD_FOR_INPUT_ADDRESS
:
4457 /* Can't use a register if it is used for an input address for this
4458 operand or used as an input in an earlier one. */
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4463 for (i
= 0; i
< opnum
; i
++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4469 case RELOAD_FOR_INPADDR_ADDRESS
:
4470 /* Can't use a register if it is used for an input address
4471 for this operand or used as an input in an earlier
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4476 for (i
= 0; i
< opnum
; i
++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4482 case RELOAD_FOR_OUTPUT_ADDRESS
:
4483 /* Can't use a register if it is used for an output address for this
4484 operand or used as an output in this or a later operand. Note
4485 that multiple output operands are emitted in reverse order, so
4486 the conflicting ones are those with lower indices. */
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4490 for (i
= 0; i
<= opnum
; i
++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4496 case RELOAD_FOR_OUTADDR_ADDRESS
:
4497 /* Can't use a register if it is used for an output address
4498 for this operand or used as an output in this or a
4499 later operand. Note that multiple output operands are
4500 emitted in reverse order, so the conflicting ones are
4501 those with lower indices. */
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4505 for (i
= 0; i
<= opnum
; i
++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4511 case RELOAD_FOR_OPERAND_ADDRESS
:
4512 for (i
= 0; i
< reload_n_operands
; i
++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4516 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4517 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4519 case RELOAD_FOR_OPADDR_ADDR
:
4520 for (i
= 0; i
< reload_n_operands
; i
++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4524 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4526 case RELOAD_FOR_OUTPUT
:
4527 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4528 outputs, or an operand address for this or an earlier output.
4529 Note that multiple output operands are emitted in reverse order,
4530 so the conflicting ones are those with higher indices. */
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4534 for (i
= 0; i
< reload_n_operands
; i
++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4538 for (i
= opnum
; i
< reload_n_operands
; i
++)
4539 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4545 case RELOAD_FOR_INSN
:
4546 for (i
= 0; i
< reload_n_operands
; i
++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4551 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4552 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4554 case RELOAD_FOR_OTHER_ADDRESS
:
4555 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4562 /* Return 1 if the value in reload reg REGNO, as used by a reload
4563 needed for the part of the insn specified by OPNUM and TYPE,
4564 is still available in REGNO at the end of the insn.
4566 We can assume that the reload reg was already tested for availability
4567 at the time it is needed, and we should not check this again,
4568 in case the reg has already been marked in use. */
4571 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4578 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4579 its value must reach the end. */
4582 /* If this use is for part of the insn,
4583 its value reaches if no subsequent part uses the same register.
4584 Just like the above function, don't try to do this with lots
4587 case RELOAD_FOR_OTHER_ADDRESS
:
4588 /* Here we check for everything else, since these don't conflict
4589 with anything else and everything comes later. */
4591 for (i
= 0; i
< reload_n_operands
; i
++)
4592 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4593 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4600 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4601 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4602 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4603 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4605 case RELOAD_FOR_INPUT_ADDRESS
:
4606 case RELOAD_FOR_INPADDR_ADDRESS
:
4607 /* Similar, except that we check only for this and subsequent inputs
4608 and the address of only subsequent inputs and we do not need
4609 to check for RELOAD_OTHER objects since they are known not to
4612 for (i
= opnum
; i
< reload_n_operands
; i
++)
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4616 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4621 for (i
= 0; i
< reload_n_operands
; i
++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4630 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4631 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4632 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4634 case RELOAD_FOR_INPUT
:
4635 /* Similar to input address, except we start at the next operand for
4636 both input and input address and we do not check for
4637 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4640 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4646 /* ... fall through ... */
4648 case RELOAD_FOR_OPERAND_ADDRESS
:
4649 /* Check outputs and their addresses. */
4651 for (i
= 0; i
< reload_n_operands
; i
++)
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4657 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4659 case RELOAD_FOR_OPADDR_ADDR
:
4660 for (i
= 0; i
< reload_n_operands
; i
++)
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4663 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4666 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4667 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4668 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4670 case RELOAD_FOR_INSN
:
4671 /* These conflict with other outputs with RELOAD_OTHER. So
4672 we need only check for output addresses. */
4674 opnum
= reload_n_operands
;
4676 /* ... fall through ... */
4678 case RELOAD_FOR_OUTPUT
:
4679 case RELOAD_FOR_OUTPUT_ADDRESS
:
4680 case RELOAD_FOR_OUTADDR_ADDRESS
:
4681 /* We already know these can't conflict with a later output. So the
4682 only thing to check are later output addresses.
4683 Note that multiple output operands are emitted in reverse order,
4684 so the conflicting ones are those with lower indices. */
4685 for (i
= 0; i
< opnum
; i
++)
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4697 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4700 This function uses the same algorithm as reload_reg_free_p above. */
4703 reloads_conflict (int r1
, int r2
)
4705 enum reload_type r1_type
= rld
[r1
].when_needed
;
4706 enum reload_type r2_type
= rld
[r2
].when_needed
;
4707 int r1_opnum
= rld
[r1
].opnum
;
4708 int r2_opnum
= rld
[r2
].opnum
;
4710 /* RELOAD_OTHER conflicts with everything. */
4711 if (r2_type
== RELOAD_OTHER
)
4714 /* Otherwise, check conflicts differently for each type. */
4718 case RELOAD_FOR_INPUT
:
4719 return (r2_type
== RELOAD_FOR_INSN
4720 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4721 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4722 || r2_type
== RELOAD_FOR_INPUT
4723 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4724 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4725 && r2_opnum
> r1_opnum
));
4727 case RELOAD_FOR_INPUT_ADDRESS
:
4728 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4729 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4731 case RELOAD_FOR_INPADDR_ADDRESS
:
4732 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4733 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4735 case RELOAD_FOR_OUTPUT_ADDRESS
:
4736 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4737 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4739 case RELOAD_FOR_OUTADDR_ADDRESS
:
4740 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4741 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4743 case RELOAD_FOR_OPERAND_ADDRESS
:
4744 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4745 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4747 case RELOAD_FOR_OPADDR_ADDR
:
4748 return (r2_type
== RELOAD_FOR_INPUT
4749 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4751 case RELOAD_FOR_OUTPUT
:
4752 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4753 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4754 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4755 && r2_opnum
>= r1_opnum
));
4757 case RELOAD_FOR_INSN
:
4758 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4759 || r2_type
== RELOAD_FOR_INSN
4760 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4762 case RELOAD_FOR_OTHER_ADDRESS
:
4763 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4773 /* Indexed by reload number, 1 if incoming value
4774 inherited from previous insns. */
4775 static char reload_inherited
[MAX_RELOADS
];
4777 /* For an inherited reload, this is the insn the reload was inherited from,
4778 if we know it. Otherwise, this is 0. */
4779 static rtx reload_inheritance_insn
[MAX_RELOADS
];
4781 /* If nonzero, this is a place to get the value of the reload,
4782 rather than using reload_in. */
4783 static rtx reload_override_in
[MAX_RELOADS
];
4785 /* For each reload, the hard register number of the register used,
4786 or -1 if we did not need a register for this reload. */
4787 static int reload_spill_index
[MAX_RELOADS
];
4789 /* Subroutine of free_for_value_p, used to check a single register.
4790 START_REGNO is the starting regno of the full reload register
4791 (possibly comprising multiple hard registers) that we are considering. */
4794 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
4795 enum reload_type type
, rtx value
, rtx out
,
4796 int reloadnum
, int ignore_address_reloads
)
4799 /* Set if we see an input reload that must not share its reload register
4800 with any new earlyclobber, but might otherwise share the reload
4801 register with an output or input-output reload. */
4802 int check_earlyclobber
= 0;
4806 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4809 if (out
== const0_rtx
)
4815 /* We use some pseudo 'time' value to check if the lifetimes of the
4816 new register use would overlap with the one of a previous reload
4817 that is not read-only or uses a different value.
4818 The 'time' used doesn't have to be linear in any shape or form, just
4820 Some reload types use different 'buckets' for each operand.
4821 So there are MAX_RECOG_OPERANDS different time values for each
4823 We compute TIME1 as the time when the register for the prospective
4824 new reload ceases to be live, and TIME2 for each existing
4825 reload as the time when that the reload register of that reload
4827 Where there is little to be gained by exact lifetime calculations,
4828 we just make conservative assumptions, i.e. a longer lifetime;
4829 this is done in the 'default:' cases. */
4832 case RELOAD_FOR_OTHER_ADDRESS
:
4833 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4834 time1
= copy
? 0 : 1;
4837 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4839 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4840 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4841 respectively, to the time values for these, we get distinct time
4842 values. To get distinct time values for each operand, we have to
4843 multiply opnum by at least three. We round that up to four because
4844 multiply by four is often cheaper. */
4845 case RELOAD_FOR_INPADDR_ADDRESS
:
4846 time1
= opnum
* 4 + 2;
4848 case RELOAD_FOR_INPUT_ADDRESS
:
4849 time1
= opnum
* 4 + 3;
4851 case RELOAD_FOR_INPUT
:
4852 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4853 executes (inclusive). */
4854 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4856 case RELOAD_FOR_OPADDR_ADDR
:
4858 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4859 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4861 case RELOAD_FOR_OPERAND_ADDRESS
:
4862 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4864 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4866 case RELOAD_FOR_OUTADDR_ADDRESS
:
4867 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4869 case RELOAD_FOR_OUTPUT_ADDRESS
:
4870 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4873 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4876 for (i
= 0; i
< n_reloads
; i
++)
4878 rtx reg
= rld
[i
].reg_rtx
;
4879 if (reg
&& REG_P (reg
)
4880 && ((unsigned) regno
- true_regnum (reg
)
4881 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
4884 rtx other_input
= rld
[i
].in
;
4886 /* If the other reload loads the same input value, that
4887 will not cause a conflict only if it's loading it into
4888 the same register. */
4889 if (true_regnum (reg
) != start_regno
)
4890 other_input
= NULL_RTX
;
4891 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4892 || rld
[i
].out
|| out
)
4895 switch (rld
[i
].when_needed
)
4897 case RELOAD_FOR_OTHER_ADDRESS
:
4900 case RELOAD_FOR_INPADDR_ADDRESS
:
4901 /* find_reloads makes sure that a
4902 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4903 by at most one - the first -
4904 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4905 address reload is inherited, the address address reload
4906 goes away, so we can ignore this conflict. */
4907 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4908 && ignore_address_reloads
4909 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4910 Then the address address is still needed to store
4911 back the new address. */
4912 && ! rld
[reloadnum
].out
)
4914 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4915 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4917 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4918 && ignore_address_reloads
4919 /* Unless we are reloading an auto_inc expression. */
4920 && ! rld
[reloadnum
].out
)
4922 time2
= rld
[i
].opnum
* 4 + 2;
4924 case RELOAD_FOR_INPUT_ADDRESS
:
4925 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4926 && ignore_address_reloads
4927 && ! rld
[reloadnum
].out
)
4929 time2
= rld
[i
].opnum
* 4 + 3;
4931 case RELOAD_FOR_INPUT
:
4932 time2
= rld
[i
].opnum
* 4 + 4;
4933 check_earlyclobber
= 1;
4935 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4936 == MAX_RECOG_OPERAND * 4 */
4937 case RELOAD_FOR_OPADDR_ADDR
:
4938 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4939 && ignore_address_reloads
4940 && ! rld
[reloadnum
].out
)
4942 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4944 case RELOAD_FOR_OPERAND_ADDRESS
:
4945 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4946 check_earlyclobber
= 1;
4948 case RELOAD_FOR_INSN
:
4949 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4951 case RELOAD_FOR_OUTPUT
:
4952 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4953 instruction is executed. */
4954 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4956 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4957 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4959 case RELOAD_FOR_OUTADDR_ADDRESS
:
4960 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4961 && ignore_address_reloads
4962 && ! rld
[reloadnum
].out
)
4964 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4966 case RELOAD_FOR_OUTPUT_ADDRESS
:
4967 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4970 /* If there is no conflict in the input part, handle this
4971 like an output reload. */
4972 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4974 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4975 /* Earlyclobbered outputs must conflict with inputs. */
4976 if (earlyclobber_operand_p (rld
[i
].out
))
4977 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4982 /* RELOAD_OTHER might be live beyond instruction execution,
4983 but this is not obvious when we set time2 = 1. So check
4984 here if there might be a problem with the new reload
4985 clobbering the register used by the RELOAD_OTHER. */
4993 && (! rld
[i
].in
|| rld
[i
].out
4994 || ! rtx_equal_p (other_input
, value
)))
4995 || (out
&& rld
[reloadnum
].out_reg
4996 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5002 /* Earlyclobbered outputs must conflict with inputs. */
5003 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5009 /* Return 1 if the value in reload reg REGNO, as used by a reload
5010 needed for the part of the insn specified by OPNUM and TYPE,
5011 may be used to load VALUE into it.
5013 MODE is the mode in which the register is used, this is needed to
5014 determine how many hard regs to test.
5016 Other read-only reloads with the same value do not conflict
5017 unless OUT is nonzero and these other reloads have to live while
5018 output reloads live.
5019 If OUT is CONST0_RTX, this is a special case: it means that the
5020 test should not be for using register REGNO as reload register, but
5021 for copying from register REGNO into the reload register.
5023 RELOADNUM is the number of the reload we want to load this value for;
5024 a reload does not conflict with itself.
5026 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5027 reloads that load an address for the very reload we are considering.
5029 The caller has to make sure that there is no conflict with the return
5033 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5034 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5035 int ignore_address_reloads
)
5037 int nregs
= hard_regno_nregs
[regno
][mode
];
5039 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5040 value
, out
, reloadnum
,
5041 ignore_address_reloads
))
5046 /* Return nonzero if the rtx X is invariant over the current function. */
5047 /* ??? Actually, the places where we use this expect exactly what is
5048 tested here, and not everything that is function invariant. In
5049 particular, the frame pointer and arg pointer are special cased;
5050 pic_offset_table_rtx is not, and we must not spill these things to
5054 function_invariant_p (rtx x
)
5058 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5060 if (GET_CODE (x
) == PLUS
5061 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5062 && CONSTANT_P (XEXP (x
, 1)))
5067 /* Determine whether the reload reg X overlaps any rtx'es used for
5068 overriding inheritance. Return nonzero if so. */
5071 conflicts_with_override (rtx x
)
5074 for (i
= 0; i
< n_reloads
; i
++)
5075 if (reload_override_in
[i
]
5076 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5081 /* Give an error message saying we failed to find a reload for INSN,
5082 and clear out reload R. */
5084 failed_reload (rtx insn
, int r
)
5086 if (asm_noperands (PATTERN (insn
)) < 0)
5087 /* It's the compiler's fault. */
5088 fatal_insn ("could not find a spill register", insn
);
5090 /* It's the user's fault; the operand's mode and constraint
5091 don't match. Disable this reload so we don't crash in final. */
5092 error_for_asm (insn
,
5093 "%<asm%> operand constraint incompatible with operand size");
5097 rld
[r
].optional
= 1;
5098 rld
[r
].secondary_p
= 1;
5101 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5102 for reload R. If it's valid, get an rtx for it. Return nonzero if
5105 set_reload_reg (int i
, int r
)
5108 rtx reg
= spill_reg_rtx
[i
];
5110 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5111 spill_reg_rtx
[i
] = reg
5112 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5114 regno
= true_regnum (reg
);
5116 /* Detect when the reload reg can't hold the reload mode.
5117 This used to be one `if', but Sequent compiler can't handle that. */
5118 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5120 enum machine_mode test_mode
= VOIDmode
;
5122 test_mode
= GET_MODE (rld
[r
].in
);
5123 /* If rld[r].in has VOIDmode, it means we will load it
5124 in whatever mode the reload reg has: to wit, rld[r].mode.
5125 We have already tested that for validity. */
5126 /* Aside from that, we need to test that the expressions
5127 to reload from or into have modes which are valid for this
5128 reload register. Otherwise the reload insns would be invalid. */
5129 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5130 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5131 if (! (rld
[r
].out
!= 0
5132 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5134 /* The reg is OK. */
5137 /* Mark as in use for this insn the reload regs we use
5139 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5140 rld
[r
].when_needed
, rld
[r
].mode
);
5142 rld
[r
].reg_rtx
= reg
;
5143 reload_spill_index
[r
] = spill_regs
[i
];
5150 /* Find a spill register to use as a reload register for reload R.
5151 LAST_RELOAD is nonzero if this is the last reload for the insn being
5154 Set rld[R].reg_rtx to the register allocated.
5156 We return 1 if successful, or 0 if we couldn't find a spill reg and
5157 we didn't change anything. */
5160 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5165 /* If we put this reload ahead, thinking it is a group,
5166 then insist on finding a group. Otherwise we can grab a
5167 reg that some other reload needs.
5168 (That can happen when we have a 68000 DATA_OR_FP_REG
5169 which is a group of data regs or one fp reg.)
5170 We need not be so restrictive if there are no more reloads
5173 ??? Really it would be nicer to have smarter handling
5174 for that kind of reg class, where a problem like this is normal.
5175 Perhaps those classes should be avoided for reloading
5176 by use of more alternatives. */
5178 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5180 /* If we want a single register and haven't yet found one,
5181 take any reg in the right class and not in use.
5182 If we want a consecutive group, here is where we look for it.
5184 We use two passes so we can first look for reload regs to
5185 reuse, which are already in use for other reloads in this insn,
5186 and only then use additional registers.
5187 I think that maximizing reuse is needed to make sure we don't
5188 run out of reload regs. Suppose we have three reloads, and
5189 reloads A and B can share regs. These need two regs.
5190 Suppose A and B are given different regs.
5191 That leaves none for C. */
5192 for (pass
= 0; pass
< 2; pass
++)
5194 /* I is the index in spill_regs.
5195 We advance it round-robin between insns to use all spill regs
5196 equally, so that inherited reloads have a chance
5197 of leapfrogging each other. */
5201 for (count
= 0; count
< n_spills
; count
++)
5203 int class = (int) rld
[r
].class;
5209 regnum
= spill_regs
[i
];
5211 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5214 /* We check reload_reg_used to make sure we
5215 don't clobber the return register. */
5216 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5217 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5218 rld
[r
].when_needed
, rld
[r
].in
,
5220 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5221 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5222 /* Look first for regs to share, then for unshared. But
5223 don't share regs used for inherited reloads; they are
5224 the ones we want to preserve. */
5226 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5228 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5231 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5232 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5233 (on 68000) got us two FP regs. If NR is 1,
5234 we would reject both of them. */
5237 /* If we need only one reg, we have already won. */
5240 /* But reject a single reg if we demand a group. */
5245 /* Otherwise check that as many consecutive regs as we need
5246 are available here. */
5249 int regno
= regnum
+ nr
- 1;
5250 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5251 && spill_reg_order
[regno
] >= 0
5252 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5253 rld
[r
].when_needed
)))
5262 /* If we found something on pass 1, omit pass 2. */
5263 if (count
< n_spills
)
5267 /* We should have found a spill register by now. */
5268 if (count
>= n_spills
)
5271 /* I is the index in SPILL_REG_RTX of the reload register we are to
5272 allocate. Get an rtx for it and find its register number. */
5274 return set_reload_reg (i
, r
);
5277 /* Initialize all the tables needed to allocate reload registers.
5278 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5279 is the array we use to restore the reg_rtx field for every reload. */
5282 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5286 for (i
= 0; i
< n_reloads
; i
++)
5287 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5289 memset (reload_inherited
, 0, MAX_RELOADS
);
5290 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5291 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5293 CLEAR_HARD_REG_SET (reload_reg_used
);
5294 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5295 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5298 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5300 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5303 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5304 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5305 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5306 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5307 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5308 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5311 for (i
= 0; i
< reload_n_operands
; i
++)
5313 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5314 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5315 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5316 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5317 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5318 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5321 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5323 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5325 for (i
= 0; i
< n_reloads
; i
++)
5326 /* If we have already decided to use a certain register,
5327 don't use it in another way. */
5329 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5330 rld
[i
].when_needed
, rld
[i
].mode
);
5333 /* Assign hard reg targets for the pseudo-registers we must reload
5334 into hard regs for this insn.
5335 Also output the instructions to copy them in and out of the hard regs.
5337 For machines with register classes, we are responsible for
5338 finding a reload reg in the proper class. */
5341 choose_reload_regs (struct insn_chain
*chain
)
5343 rtx insn
= chain
->insn
;
5345 unsigned int max_group_size
= 1;
5346 enum reg_class group_class
= NO_REGS
;
5347 int pass
, win
, inheritance
;
5349 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5351 /* In order to be certain of getting the registers we need,
5352 we must sort the reloads into order of increasing register class.
5353 Then our grabbing of reload registers will parallel the process
5354 that provided the reload registers.
5356 Also note whether any of the reloads wants a consecutive group of regs.
5357 If so, record the maximum size of the group desired and what
5358 register class contains all the groups needed by this insn. */
5360 for (j
= 0; j
< n_reloads
; j
++)
5362 reload_order
[j
] = j
;
5363 reload_spill_index
[j
] = -1;
5365 if (rld
[j
].nregs
> 1)
5367 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5369 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5372 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5376 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5378 /* If -O, try first with inheritance, then turning it off.
5379 If not -O, don't do inheritance.
5380 Using inheritance when not optimizing leads to paradoxes
5381 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5382 because one side of the comparison might be inherited. */
5384 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5386 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5388 /* Process the reloads in order of preference just found.
5389 Beyond this point, subregs can be found in reload_reg_rtx.
5391 This used to look for an existing reloaded home for all of the
5392 reloads, and only then perform any new reloads. But that could lose
5393 if the reloads were done out of reg-class order because a later
5394 reload with a looser constraint might have an old home in a register
5395 needed by an earlier reload with a tighter constraint.
5397 To solve this, we make two passes over the reloads, in the order
5398 described above. In the first pass we try to inherit a reload
5399 from a previous insn. If there is a later reload that needs a
5400 class that is a proper subset of the class being processed, we must
5401 also allocate a spill register during the first pass.
5403 Then make a second pass over the reloads to allocate any reloads
5404 that haven't been given registers yet. */
5406 for (j
= 0; j
< n_reloads
; j
++)
5408 int r
= reload_order
[j
];
5409 rtx search_equiv
= NULL_RTX
;
5411 /* Ignore reloads that got marked inoperative. */
5412 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5413 && ! rld
[r
].secondary_p
)
5416 /* If find_reloads chose to use reload_in or reload_out as a reload
5417 register, we don't need to chose one. Otherwise, try even if it
5418 found one since we might save an insn if we find the value lying
5420 Try also when reload_in is a pseudo without a hard reg. */
5421 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5422 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5423 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5424 && !MEM_P (rld
[r
].in
)
5425 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5428 #if 0 /* No longer needed for correct operation.
5429 It might give better code, or might not; worth an experiment? */
5430 /* If this is an optional reload, we can't inherit from earlier insns
5431 until we are sure that any non-optional reloads have been allocated.
5432 The following code takes advantage of the fact that optional reloads
5433 are at the end of reload_order. */
5434 if (rld
[r
].optional
!= 0)
5435 for (i
= 0; i
< j
; i
++)
5436 if ((rld
[reload_order
[i
]].out
!= 0
5437 || rld
[reload_order
[i
]].in
!= 0
5438 || rld
[reload_order
[i
]].secondary_p
)
5439 && ! rld
[reload_order
[i
]].optional
5440 && rld
[reload_order
[i
]].reg_rtx
== 0)
5441 allocate_reload_reg (chain
, reload_order
[i
], 0);
5444 /* First see if this pseudo is already available as reloaded
5445 for a previous insn. We cannot try to inherit for reloads
5446 that are smaller than the maximum number of registers needed
5447 for groups unless the register we would allocate cannot be used
5450 We could check here to see if this is a secondary reload for
5451 an object that is already in a register of the desired class.
5452 This would avoid the need for the secondary reload register.
5453 But this is complex because we can't easily determine what
5454 objects might want to be loaded via this reload. So let a
5455 register be allocated here. In `emit_reload_insns' we suppress
5456 one of the loads in the case described above. */
5462 enum machine_mode mode
= VOIDmode
;
5466 else if (REG_P (rld
[r
].in
))
5468 regno
= REGNO (rld
[r
].in
);
5469 mode
= GET_MODE (rld
[r
].in
);
5471 else if (REG_P (rld
[r
].in_reg
))
5473 regno
= REGNO (rld
[r
].in_reg
);
5474 mode
= GET_MODE (rld
[r
].in_reg
);
5476 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5477 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
5479 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5480 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5481 if (regno
< FIRST_PSEUDO_REGISTER
)
5482 regno
= subreg_regno (rld
[r
].in_reg
);
5483 mode
= GET_MODE (rld
[r
].in_reg
);
5486 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5487 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5488 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5489 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5490 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
5492 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5493 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5494 rld
[r
].out
= rld
[r
].in
;
5498 /* This won't work, since REGNO can be a pseudo reg number.
5499 Also, it takes much more hair to keep track of all the things
5500 that can invalidate an inherited reload of part of a pseudoreg. */
5501 else if (GET_CODE (rld
[r
].in
) == SUBREG
5502 && REG_P (SUBREG_REG (rld
[r
].in
)))
5503 regno
= subreg_regno (rld
[r
].in
);
5506 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5508 enum reg_class
class = rld
[r
].class, last_class
;
5509 rtx last_reg
= reg_last_reload_reg
[regno
];
5510 enum machine_mode need_mode
;
5512 i
= REGNO (last_reg
);
5513 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5514 last_class
= REGNO_REG_CLASS (i
);
5520 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
5521 + byte
* BITS_PER_UNIT
,
5522 GET_MODE_CLASS (mode
));
5524 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5525 >= GET_MODE_SIZE (need_mode
))
5526 #ifdef CANNOT_CHANGE_MODE_CLASS
5527 /* Verify that the register in "i" can be obtained
5529 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg
),
5530 GET_MODE (last_reg
),
5533 && reg_reloaded_contents
[i
] == regno
5534 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5535 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5536 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5537 /* Even if we can't use this register as a reload
5538 register, we might use it for reload_override_in,
5539 if copying it to the desired class is cheap
5541 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5542 < MEMORY_MOVE_COST (mode
, class, 1))
5543 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5544 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5548 #ifdef SECONDARY_MEMORY_NEEDED
5549 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5554 && (rld
[r
].nregs
== max_group_size
5555 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5557 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5558 rld
[r
].when_needed
, rld
[r
].in
,
5561 /* If a group is needed, verify that all the subsequent
5562 registers still have their values intact. */
5563 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5566 for (k
= 1; k
< nr
; k
++)
5567 if (reg_reloaded_contents
[i
+ k
] != regno
5568 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5576 last_reg
= (GET_MODE (last_reg
) == mode
5577 ? last_reg
: gen_rtx_REG (mode
, i
));
5580 for (k
= 0; k
< nr
; k
++)
5581 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5584 /* We found a register that contains the
5585 value we need. If this register is the
5586 same as an `earlyclobber' operand of the
5587 current insn, just mark it as a place to
5588 reload from since we can't use it as the
5589 reload register itself. */
5591 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5592 if (reg_overlap_mentioned_for_reload_p
5593 (reg_last_reload_reg
[regno
],
5594 reload_earlyclobbers
[i1
]))
5597 if (i1
!= n_earlyclobbers
5598 || ! (free_for_value_p (i
, rld
[r
].mode
,
5600 rld
[r
].when_needed
, rld
[r
].in
,
5602 /* Don't use it if we'd clobber a pseudo reg. */
5603 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5605 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5606 /* Don't clobber the frame pointer. */
5607 || (i
== HARD_FRAME_POINTER_REGNUM
5608 && frame_pointer_needed
5610 /* Don't really use the inherited spill reg
5611 if we need it wider than we've got it. */
5612 || (GET_MODE_SIZE (rld
[r
].mode
)
5613 > GET_MODE_SIZE (mode
))
5616 /* If find_reloads chose reload_out as reload
5617 register, stay with it - that leaves the
5618 inherited register for subsequent reloads. */
5619 || (rld
[r
].out
&& rld
[r
].reg_rtx
5620 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5622 if (! rld
[r
].optional
)
5624 reload_override_in
[r
] = last_reg
;
5625 reload_inheritance_insn
[r
]
5626 = reg_reloaded_insn
[i
];
5632 /* We can use this as a reload reg. */
5633 /* Mark the register as in use for this part of
5635 mark_reload_reg_in_use (i
,
5639 rld
[r
].reg_rtx
= last_reg
;
5640 reload_inherited
[r
] = 1;
5641 reload_inheritance_insn
[r
]
5642 = reg_reloaded_insn
[i
];
5643 reload_spill_index
[r
] = i
;
5644 for (k
= 0; k
< nr
; k
++)
5645 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5653 /* Here's another way to see if the value is already lying around. */
5656 && ! reload_inherited
[r
]
5658 && (CONSTANT_P (rld
[r
].in
)
5659 || GET_CODE (rld
[r
].in
) == PLUS
5660 || REG_P (rld
[r
].in
)
5661 || MEM_P (rld
[r
].in
))
5662 && (rld
[r
].nregs
== max_group_size
5663 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5664 search_equiv
= rld
[r
].in
;
5665 /* If this is an output reload from a simple move insn, look
5666 if an equivalence for the input is available. */
5667 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5669 rtx set
= single_set (insn
);
5672 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5673 && CONSTANT_P (SET_SRC (set
)))
5674 search_equiv
= SET_SRC (set
);
5680 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5681 -1, NULL
, 0, rld
[r
].mode
);
5687 regno
= REGNO (equiv
);
5690 /* This must be a SUBREG of a hard register.
5691 Make a new REG since this might be used in an
5692 address and not all machines support SUBREGs
5694 gcc_assert (GET_CODE (equiv
) == SUBREG
);
5695 regno
= subreg_regno (equiv
);
5696 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5697 /* If we choose EQUIV as the reload register, but the
5698 loop below decides to cancel the inheritance, we'll
5699 end up reloading EQUIV in rld[r].mode, not the mode
5700 it had originally. That isn't safe when EQUIV isn't
5701 available as a spill register since its value might
5702 still be live at this point. */
5703 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
5704 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
5709 /* If we found a spill reg, reject it unless it is free
5710 and of the desired class. */
5714 int bad_for_class
= 0;
5715 int max_regno
= regno
+ rld
[r
].nregs
;
5717 for (i
= regno
; i
< max_regno
; i
++)
5719 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5721 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5726 && ! free_for_value_p (regno
, rld
[r
].mode
,
5727 rld
[r
].opnum
, rld
[r
].when_needed
,
5728 rld
[r
].in
, rld
[r
].out
, r
, 1))
5733 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5736 /* We found a register that contains the value we need.
5737 If this register is the same as an `earlyclobber' operand
5738 of the current insn, just mark it as a place to reload from
5739 since we can't use it as the reload register itself. */
5742 for (i
= 0; i
< n_earlyclobbers
; i
++)
5743 if (reg_overlap_mentioned_for_reload_p (equiv
,
5744 reload_earlyclobbers
[i
]))
5746 if (! rld
[r
].optional
)
5747 reload_override_in
[r
] = equiv
;
5752 /* If the equiv register we have found is explicitly clobbered
5753 in the current insn, it depends on the reload type if we
5754 can use it, use it for reload_override_in, or not at all.
5755 In particular, we then can't use EQUIV for a
5756 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5760 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5761 switch (rld
[r
].when_needed
)
5763 case RELOAD_FOR_OTHER_ADDRESS
:
5764 case RELOAD_FOR_INPADDR_ADDRESS
:
5765 case RELOAD_FOR_INPUT_ADDRESS
:
5766 case RELOAD_FOR_OPADDR_ADDR
:
5769 case RELOAD_FOR_INPUT
:
5770 case RELOAD_FOR_OPERAND_ADDRESS
:
5771 if (! rld
[r
].optional
)
5772 reload_override_in
[r
] = equiv
;
5778 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5779 switch (rld
[r
].when_needed
)
5781 case RELOAD_FOR_OTHER_ADDRESS
:
5782 case RELOAD_FOR_INPADDR_ADDRESS
:
5783 case RELOAD_FOR_INPUT_ADDRESS
:
5784 case RELOAD_FOR_OPADDR_ADDR
:
5785 case RELOAD_FOR_OPERAND_ADDRESS
:
5786 case RELOAD_FOR_INPUT
:
5789 if (! rld
[r
].optional
)
5790 reload_override_in
[r
] = equiv
;
5798 /* If we found an equivalent reg, say no code need be generated
5799 to load it, and use it as our reload reg. */
5801 && (regno
!= HARD_FRAME_POINTER_REGNUM
5802 || !frame_pointer_needed
))
5804 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
5806 rld
[r
].reg_rtx
= equiv
;
5807 reload_inherited
[r
] = 1;
5809 /* If reg_reloaded_valid is not set for this register,
5810 there might be a stale spill_reg_store lying around.
5811 We must clear it, since otherwise emit_reload_insns
5812 might delete the store. */
5813 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5814 spill_reg_store
[regno
] = NULL_RTX
;
5815 /* If any of the hard registers in EQUIV are spill
5816 registers, mark them as in use for this insn. */
5817 for (k
= 0; k
< nr
; k
++)
5819 i
= spill_reg_order
[regno
+ k
];
5822 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5825 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5832 /* If we found a register to use already, or if this is an optional
5833 reload, we are done. */
5834 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5838 /* No longer needed for correct operation. Might or might
5839 not give better code on the average. Want to experiment? */
5841 /* See if there is a later reload that has a class different from our
5842 class that intersects our class or that requires less register
5843 than our reload. If so, we must allocate a register to this
5844 reload now, since that reload might inherit a previous reload
5845 and take the only available register in our class. Don't do this
5846 for optional reloads since they will force all previous reloads
5847 to be allocated. Also don't do this for reloads that have been
5850 for (i
= j
+ 1; i
< n_reloads
; i
++)
5852 int s
= reload_order
[i
];
5854 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5855 && ! rld
[s
].secondary_p
)
5859 if ((rld
[s
].class != rld
[r
].class
5860 && reg_classes_intersect_p (rld
[r
].class,
5862 || rld
[s
].nregs
< rld
[r
].nregs
)
5869 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5873 /* Now allocate reload registers for anything non-optional that
5874 didn't get one yet. */
5875 for (j
= 0; j
< n_reloads
; j
++)
5877 int r
= reload_order
[j
];
5879 /* Ignore reloads that got marked inoperative. */
5880 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5883 /* Skip reloads that already have a register allocated or are
5885 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5888 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5892 /* If that loop got all the way, we have won. */
5899 /* Loop around and try without any inheritance. */
5904 /* First undo everything done by the failed attempt
5905 to allocate with inheritance. */
5906 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5908 /* Some sanity tests to verify that the reloads found in the first
5909 pass are identical to the ones we have now. */
5910 gcc_assert (chain
->n_reloads
== n_reloads
);
5912 for (i
= 0; i
< n_reloads
; i
++)
5914 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5916 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
5917 for (j
= 0; j
< n_spills
; j
++)
5918 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5919 if (! set_reload_reg (j
, i
))
5920 failed_reload (chain
->insn
, i
);
5924 /* If we thought we could inherit a reload, because it seemed that
5925 nothing else wanted the same reload register earlier in the insn,
5926 verify that assumption, now that all reloads have been assigned.
5927 Likewise for reloads where reload_override_in has been set. */
5929 /* If doing expensive optimizations, do one preliminary pass that doesn't
5930 cancel any inheritance, but removes reloads that have been needed only
5931 for reloads that we know can be inherited. */
5932 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5934 for (j
= 0; j
< n_reloads
; j
++)
5936 int r
= reload_order
[j
];
5938 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5939 check_reg
= rld
[r
].reg_rtx
;
5940 else if (reload_override_in
[r
]
5941 && (REG_P (reload_override_in
[r
])
5942 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5943 check_reg
= reload_override_in
[r
];
5946 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5947 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5948 (reload_inherited
[r
]
5949 ? rld
[r
].out
: const0_rtx
),
5954 reload_inherited
[r
] = 0;
5955 reload_override_in
[r
] = 0;
5957 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5958 reload_override_in, then we do not need its related
5959 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5960 likewise for other reload types.
5961 We handle this by removing a reload when its only replacement
5962 is mentioned in reload_in of the reload we are going to inherit.
5963 A special case are auto_inc expressions; even if the input is
5964 inherited, we still need the address for the output. We can
5965 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5966 If we succeeded removing some reload and we are doing a preliminary
5967 pass just to remove such reloads, make another pass, since the
5968 removal of one reload might allow us to inherit another one. */
5970 && rld
[r
].out
!= rld
[r
].in
5971 && remove_address_replacements (rld
[r
].in
) && pass
)
5976 /* Now that reload_override_in is known valid,
5977 actually override reload_in. */
5978 for (j
= 0; j
< n_reloads
; j
++)
5979 if (reload_override_in
[j
])
5980 rld
[j
].in
= reload_override_in
[j
];
5982 /* If this reload won't be done because it has been canceled or is
5983 optional and not inherited, clear reload_reg_rtx so other
5984 routines (such as subst_reloads) don't get confused. */
5985 for (j
= 0; j
< n_reloads
; j
++)
5986 if (rld
[j
].reg_rtx
!= 0
5987 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5988 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5989 && ! rld
[j
].secondary_p
)))
5991 int regno
= true_regnum (rld
[j
].reg_rtx
);
5993 if (spill_reg_order
[regno
] >= 0)
5994 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5995 rld
[j
].when_needed
, rld
[j
].mode
);
5997 reload_spill_index
[j
] = -1;
6000 /* Record which pseudos and which spill regs have output reloads. */
6001 for (j
= 0; j
< n_reloads
; j
++)
6003 int r
= reload_order
[j
];
6005 i
= reload_spill_index
[r
];
6007 /* I is nonneg if this reload uses a register.
6008 If rld[r].reg_rtx is 0, this is an optional reload
6009 that we opted to ignore. */
6010 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6011 && rld
[r
].reg_rtx
!= 0)
6013 int nregno
= REGNO (rld
[r
].out_reg
);
6016 if (nregno
< FIRST_PSEUDO_REGISTER
)
6017 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6020 reg_has_output_reload
[nregno
+ nr
] = 1;
6024 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6026 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6029 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6030 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6031 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6036 /* Deallocate the reload register for reload R. This is called from
6037 remove_address_replacements. */
6040 deallocate_reload_reg (int r
)
6044 if (! rld
[r
].reg_rtx
)
6046 regno
= true_regnum (rld
[r
].reg_rtx
);
6048 if (spill_reg_order
[regno
] >= 0)
6049 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6051 reload_spill_index
[r
] = -1;
6054 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6055 reloads of the same item for fear that we might not have enough reload
6056 registers. However, normally they will get the same reload register
6057 and hence actually need not be loaded twice.
6059 Here we check for the most common case of this phenomenon: when we have
6060 a number of reloads for the same object, each of which were allocated
6061 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6062 reload, and is not modified in the insn itself. If we find such,
6063 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6064 This will not increase the number of spill registers needed and will
6065 prevent redundant code. */
6068 merge_assigned_reloads (rtx insn
)
6072 /* Scan all the reloads looking for ones that only load values and
6073 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6074 assigned and not modified by INSN. */
6076 for (i
= 0; i
< n_reloads
; i
++)
6078 int conflicting_input
= 0;
6079 int max_input_address_opnum
= -1;
6080 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6082 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6083 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6084 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6087 /* Look at all other reloads. Ensure that the only use of this
6088 reload_reg_rtx is in a reload that just loads the same value
6089 as we do. Note that any secondary reloads must be of the identical
6090 class since the values, modes, and result registers are the
6091 same, so we need not do anything with any secondary reloads. */
6093 for (j
= 0; j
< n_reloads
; j
++)
6095 if (i
== j
|| rld
[j
].reg_rtx
== 0
6096 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6100 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6101 && rld
[j
].opnum
> max_input_address_opnum
)
6102 max_input_address_opnum
= rld
[j
].opnum
;
6104 /* If the reload regs aren't exactly the same (e.g, different modes)
6105 or if the values are different, we can't merge this reload.
6106 But if it is an input reload, we might still merge
6107 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6109 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6110 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6111 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6113 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6114 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6115 || rld
[i
].opnum
> rld
[j
].opnum
)
6116 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6118 conflicting_input
= 1;
6119 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6120 min_conflicting_input_opnum
= rld
[j
].opnum
;
6124 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6125 we, in fact, found any matching reloads. */
6128 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6130 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
6132 for (j
= 0; j
< n_reloads
; j
++)
6133 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6134 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6135 && (! conflicting_input
6136 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6137 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6139 rld
[i
].when_needed
= RELOAD_OTHER
;
6141 reload_spill_index
[j
] = -1;
6142 transfer_replacements (i
, j
);
6145 /* If this is now RELOAD_OTHER, look for any reloads that load
6146 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6147 if they were for inputs, RELOAD_OTHER for outputs. Note that
6148 this test is equivalent to looking for reloads for this operand
6150 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6151 share registers with a RELOAD_FOR_INPUT, so we can not change it
6152 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6153 do not modify RELOAD_FOR_OUTPUT. */
6155 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6156 for (j
= 0; j
< n_reloads
; j
++)
6158 && rld
[j
].when_needed
!= RELOAD_OTHER
6159 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6160 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
6161 && (! conflicting_input
6162 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6163 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6164 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6170 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6171 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6172 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6174 /* Check to see if we accidentally converted two
6175 reloads that use the same reload register with
6176 different inputs to the same type. If so, the
6177 resulting code won't work. */
6179 for (k
= 0; k
< j
; k
++)
6180 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6181 || rld
[k
].when_needed
!= rld
[j
].when_needed
6182 || !rtx_equal_p (rld
[k
].reg_rtx
,
6184 || rtx_equal_p (rld
[k
].in
,
6191 /* These arrays are filled by emit_reload_insns and its subroutines. */
6192 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6193 static rtx other_input_address_reload_insns
= 0;
6194 static rtx other_input_reload_insns
= 0;
6195 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6196 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6197 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6198 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6199 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6200 static rtx operand_reload_insns
= 0;
6201 static rtx other_operand_reload_insns
= 0;
6202 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6204 /* Values to be put in spill_reg_store are put here first. */
6205 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6206 static HARD_REG_SET reg_reloaded_died
;
6208 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6209 has the number J. OLD contains the value to be used as input. */
6212 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6215 rtx insn
= chain
->insn
;
6216 rtx reloadreg
= rl
->reg_rtx
;
6217 rtx oldequiv_reg
= 0;
6220 enum machine_mode mode
;
6223 /* Determine the mode to reload in.
6224 This is very tricky because we have three to choose from.
6225 There is the mode the insn operand wants (rl->inmode).
6226 There is the mode of the reload register RELOADREG.
6227 There is the intrinsic mode of the operand, which we could find
6228 by stripping some SUBREGs.
6229 It turns out that RELOADREG's mode is irrelevant:
6230 we can change that arbitrarily.
6232 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6233 then the reload reg may not support QImode moves, so use SImode.
6234 If foo is in memory due to spilling a pseudo reg, this is safe,
6235 because the QImode value is in the least significant part of a
6236 slot big enough for a SImode. If foo is some other sort of
6237 memory reference, then it is impossible to reload this case,
6238 so previous passes had better make sure this never happens.
6240 Then consider a one-word union which has SImode and one of its
6241 members is a float, being fetched as (SUBREG:SF union:SI).
6242 We must fetch that as SFmode because we could be loading into
6243 a float-only register. In this case OLD's mode is correct.
6245 Consider an immediate integer: it has VOIDmode. Here we need
6246 to get a mode from something else.
6248 In some cases, there is a fourth mode, the operand's
6249 containing mode. If the insn specifies a containing mode for
6250 this operand, it overrides all others.
6252 I am not sure whether the algorithm here is always right,
6253 but it does the right things in those cases. */
6255 mode
= GET_MODE (old
);
6256 if (mode
== VOIDmode
)
6259 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6260 /* If we need a secondary register for this operation, see if
6261 the value is already in a register in that class. Don't
6262 do this if the secondary register will be used as a scratch
6265 if (rl
->secondary_in_reload
>= 0
6266 && rl
->secondary_in_icode
== CODE_FOR_nothing
6269 = find_equiv_reg (old
, insn
,
6270 rld
[rl
->secondary_in_reload
].class,
6274 /* If reloading from memory, see if there is a register
6275 that already holds the same value. If so, reload from there.
6276 We can pass 0 as the reload_reg_p argument because
6277 any other reload has either already been emitted,
6278 in which case find_equiv_reg will see the reload-insn,
6279 or has yet to be emitted, in which case it doesn't matter
6280 because we will use this equiv reg right away. */
6282 if (oldequiv
== 0 && optimize
6285 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6286 && reg_renumber
[REGNO (old
)] < 0)))
6287 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6291 unsigned int regno
= true_regnum (oldequiv
);
6293 /* Don't use OLDEQUIV if any other reload changes it at an
6294 earlier stage of this insn or at this stage. */
6295 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6296 rl
->in
, const0_rtx
, j
, 0))
6299 /* If it is no cheaper to copy from OLDEQUIV into the
6300 reload register than it would be to move from memory,
6301 don't use it. Likewise, if we need a secondary register
6305 && (((enum reg_class
) REGNO_REG_CLASS (regno
) != rl
->class
6306 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6308 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6309 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6310 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6314 #ifdef SECONDARY_MEMORY_NEEDED
6315 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6323 /* delete_output_reload is only invoked properly if old contains
6324 the original pseudo register. Since this is replaced with a
6325 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6326 find the pseudo in RELOAD_IN_REG. */
6328 && reload_override_in
[j
]
6329 && REG_P (rl
->in_reg
))
6336 else if (REG_P (oldequiv
))
6337 oldequiv_reg
= oldequiv
;
6338 else if (GET_CODE (oldequiv
) == SUBREG
)
6339 oldequiv_reg
= SUBREG_REG (oldequiv
);
6341 /* If we are reloading from a register that was recently stored in
6342 with an output-reload, see if we can prove there was
6343 actually no need to store the old value in it. */
6345 if (optimize
&& REG_P (oldequiv
)
6346 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6347 && spill_reg_store
[REGNO (oldequiv
)]
6349 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6350 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6352 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6354 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6355 then load RELOADREG from OLDEQUIV. Note that we cannot use
6356 gen_lowpart_common since it can do the wrong thing when
6357 RELOADREG has a multi-word mode. Note that RELOADREG
6358 must always be a REG here. */
6360 if (GET_MODE (reloadreg
) != mode
)
6361 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6362 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6363 oldequiv
= SUBREG_REG (oldequiv
);
6364 if (GET_MODE (oldequiv
) != VOIDmode
6365 && mode
!= GET_MODE (oldequiv
))
6366 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6368 /* Switch to the right place to emit the reload insns. */
6369 switch (rl
->when_needed
)
6372 where
= &other_input_reload_insns
;
6374 case RELOAD_FOR_INPUT
:
6375 where
= &input_reload_insns
[rl
->opnum
];
6377 case RELOAD_FOR_INPUT_ADDRESS
:
6378 where
= &input_address_reload_insns
[rl
->opnum
];
6380 case RELOAD_FOR_INPADDR_ADDRESS
:
6381 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6383 case RELOAD_FOR_OUTPUT_ADDRESS
:
6384 where
= &output_address_reload_insns
[rl
->opnum
];
6386 case RELOAD_FOR_OUTADDR_ADDRESS
:
6387 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6389 case RELOAD_FOR_OPERAND_ADDRESS
:
6390 where
= &operand_reload_insns
;
6392 case RELOAD_FOR_OPADDR_ADDR
:
6393 where
= &other_operand_reload_insns
;
6395 case RELOAD_FOR_OTHER_ADDRESS
:
6396 where
= &other_input_address_reload_insns
;
6402 push_to_sequence (*where
);
6404 /* Auto-increment addresses must be reloaded in a special way. */
6405 if (rl
->out
&& ! rl
->out_reg
)
6407 /* We are not going to bother supporting the case where a
6408 incremented register can't be copied directly from
6409 OLDEQUIV since this seems highly unlikely. */
6410 gcc_assert (rl
->secondary_in_reload
< 0);
6412 if (reload_inherited
[j
])
6413 oldequiv
= reloadreg
;
6415 old
= XEXP (rl
->in_reg
, 0);
6417 if (optimize
&& REG_P (oldequiv
)
6418 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6419 && spill_reg_store
[REGNO (oldequiv
)]
6421 && (dead_or_set_p (insn
,
6422 spill_reg_stored_to
[REGNO (oldequiv
)])
6423 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6425 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6427 /* Prevent normal processing of this reload. */
6429 /* Output a special code sequence for this case. */
6430 new_spill_reg_store
[REGNO (reloadreg
)]
6431 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6435 /* If we are reloading a pseudo-register that was set by the previous
6436 insn, see if we can get rid of that pseudo-register entirely
6437 by redirecting the previous insn into our reload register. */
6439 else if (optimize
&& REG_P (old
)
6440 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6441 && dead_or_set_p (insn
, old
)
6442 /* This is unsafe if some other reload
6443 uses the same reg first. */
6444 && ! conflicts_with_override (reloadreg
)
6445 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6446 rl
->when_needed
, old
, rl
->out
, j
, 0))
6448 rtx temp
= PREV_INSN (insn
);
6449 while (temp
&& NOTE_P (temp
))
6450 temp
= PREV_INSN (temp
);
6452 && NONJUMP_INSN_P (temp
)
6453 && GET_CODE (PATTERN (temp
)) == SET
6454 && SET_DEST (PATTERN (temp
)) == old
6455 /* Make sure we can access insn_operand_constraint. */
6456 && asm_noperands (PATTERN (temp
)) < 0
6457 /* This is unsafe if operand occurs more than once in current
6458 insn. Perhaps some occurrences aren't reloaded. */
6459 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6461 rtx old
= SET_DEST (PATTERN (temp
));
6462 /* Store into the reload register instead of the pseudo. */
6463 SET_DEST (PATTERN (temp
)) = reloadreg
;
6465 /* Verify that resulting insn is valid. */
6466 extract_insn (temp
);
6467 if (constrain_operands (1))
6469 /* If the previous insn is an output reload, the source is
6470 a reload register, and its spill_reg_store entry will
6471 contain the previous destination. This is now
6473 if (REG_P (SET_SRC (PATTERN (temp
)))
6474 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6476 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6477 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6480 /* If these are the only uses of the pseudo reg,
6481 pretend for GDB it lives in the reload reg we used. */
6482 if (REG_N_DEATHS (REGNO (old
)) == 1
6483 && REG_N_SETS (REGNO (old
)) == 1)
6485 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6486 alter_reg (REGNO (old
), -1);
6492 SET_DEST (PATTERN (temp
)) = old
;
6497 /* We can't do that, so output an insn to load RELOADREG. */
6499 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6500 /* If we have a secondary reload, pick up the secondary register
6501 and icode, if any. If OLDEQUIV and OLD are different or
6502 if this is an in-out reload, recompute whether or not we
6503 still need a secondary register and what the icode should
6504 be. If we still need a secondary register and the class or
6505 icode is different, go back to reloading from OLD if using
6506 OLDEQUIV means that we got the wrong type of register. We
6507 cannot have different class or icode due to an in-out reload
6508 because we don't make such reloads when both the input and
6509 output need secondary reload registers. */
6511 if (! special
&& rl
->secondary_in_reload
>= 0)
6513 rtx second_reload_reg
= 0;
6514 int secondary_reload
= rl
->secondary_in_reload
;
6515 rtx real_oldequiv
= oldequiv
;
6518 enum insn_code icode
;
6520 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6521 and similarly for OLD.
6522 See comments in get_secondary_reload in reload.c. */
6523 /* If it is a pseudo that cannot be replaced with its
6524 equivalent MEM, we must fall back to reload_in, which
6525 will have all the necessary substitutions registered.
6526 Likewise for a pseudo that can't be replaced with its
6527 equivalent constant.
6529 Take extra care for subregs of such pseudos. Note that
6530 we cannot use reg_equiv_mem in this case because it is
6531 not in the right mode. */
6534 if (GET_CODE (tmp
) == SUBREG
)
6535 tmp
= SUBREG_REG (tmp
);
6537 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6538 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6539 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6541 if (! reg_equiv_mem
[REGNO (tmp
)]
6542 || num_not_at_initial_offset
6543 || GET_CODE (oldequiv
) == SUBREG
)
6544 real_oldequiv
= rl
->in
;
6546 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6550 if (GET_CODE (tmp
) == SUBREG
)
6551 tmp
= SUBREG_REG (tmp
);
6553 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6554 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6555 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6557 if (! reg_equiv_mem
[REGNO (tmp
)]
6558 || num_not_at_initial_offset
6559 || GET_CODE (old
) == SUBREG
)
6562 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6565 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6566 icode
= rl
->secondary_in_icode
;
6568 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6569 || (rl
->in
!= 0 && rl
->out
!= 0))
6571 enum reg_class new_class
6572 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6573 mode
, real_oldequiv
);
6575 if (new_class
== NO_REGS
)
6576 second_reload_reg
= 0;
6579 enum insn_code new_icode
;
6580 enum machine_mode new_mode
;
6582 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6583 REGNO (second_reload_reg
)))
6584 oldequiv
= old
, real_oldequiv
= real_old
;
6587 new_icode
= reload_in_optab
[(int) mode
];
6588 if (new_icode
!= CODE_FOR_nothing
6589 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6590 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6592 || (insn_data
[(int) new_icode
].operand
[1].predicate
6593 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6594 (real_oldequiv
, mode
)))))
6595 new_icode
= CODE_FOR_nothing
;
6597 if (new_icode
== CODE_FOR_nothing
)
6600 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6602 if (GET_MODE (second_reload_reg
) != new_mode
)
6604 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6606 oldequiv
= old
, real_oldequiv
= real_old
;
6609 = reload_adjust_reg_for_mode (second_reload_reg
,
6616 /* If we still need a secondary reload register, check
6617 to see if it is being used as a scratch or intermediate
6618 register and generate code appropriately. If we need
6619 a scratch register, use REAL_OLDEQUIV since the form of
6620 the insn may depend on the actual address if it is
6623 if (second_reload_reg
)
6625 if (icode
!= CODE_FOR_nothing
)
6627 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6628 second_reload_reg
));
6633 /* See if we need a scratch register to load the
6634 intermediate register (a tertiary reload). */
6635 enum insn_code tertiary_icode
6636 = rld
[secondary_reload
].secondary_in_icode
;
6638 if (tertiary_icode
!= CODE_FOR_nothing
)
6640 rtx third_reload_reg
6641 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6643 emit_insn ((GEN_FCN (tertiary_icode
)
6644 (second_reload_reg
, real_oldequiv
,
6645 third_reload_reg
)));
6648 gen_reload (second_reload_reg
, real_oldequiv
,
6652 oldequiv
= second_reload_reg
;
6658 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6660 rtx real_oldequiv
= oldequiv
;
6662 if ((REG_P (oldequiv
)
6663 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6664 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6665 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6666 || (GET_CODE (oldequiv
) == SUBREG
6667 && REG_P (SUBREG_REG (oldequiv
))
6668 && (REGNO (SUBREG_REG (oldequiv
))
6669 >= FIRST_PSEUDO_REGISTER
)
6670 && ((reg_equiv_memory_loc
6671 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6672 || (reg_equiv_constant
6673 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6674 || (CONSTANT_P (oldequiv
)
6675 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6676 REGNO_REG_CLASS (REGNO (reloadreg
)))
6678 real_oldequiv
= rl
->in
;
6679 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6683 if (flag_non_call_exceptions
)
6684 copy_eh_notes (insn
, get_insns ());
6686 /* End this sequence. */
6687 *where
= get_insns ();
6690 /* Update reload_override_in so that delete_address_reloads_1
6691 can see the actual register usage. */
6693 reload_override_in
[j
] = oldequiv
;
6696 /* Generate insns to for the output reload RL, which is for the insn described
6697 by CHAIN and has the number J. */
6699 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6702 rtx reloadreg
= rl
->reg_rtx
;
6703 rtx insn
= chain
->insn
;
6706 enum machine_mode mode
= GET_MODE (old
);
6709 if (rl
->when_needed
== RELOAD_OTHER
)
6712 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6714 /* Determine the mode to reload in.
6715 See comments above (for input reloading). */
6717 if (mode
== VOIDmode
)
6719 /* VOIDmode should never happen for an output. */
6720 if (asm_noperands (PATTERN (insn
)) < 0)
6721 /* It's the compiler's fault. */
6722 fatal_insn ("VOIDmode on an output", insn
);
6723 error_for_asm (insn
, "output operand is constant in %<asm%>");
6724 /* Prevent crash--use something we know is valid. */
6726 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6729 if (GET_MODE (reloadreg
) != mode
)
6730 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6732 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6734 /* If we need two reload regs, set RELOADREG to the intermediate
6735 one, since it will be stored into OLD. We might need a secondary
6736 register only for an input reload, so check again here. */
6738 if (rl
->secondary_out_reload
>= 0)
6742 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6743 && reg_equiv_mem
[REGNO (old
)] != 0)
6744 real_old
= reg_equiv_mem
[REGNO (old
)];
6746 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6750 rtx second_reloadreg
= reloadreg
;
6751 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6753 /* See if RELOADREG is to be used as a scratch register
6754 or as an intermediate register. */
6755 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6757 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6758 (real_old
, second_reloadreg
, reloadreg
)));
6763 /* See if we need both a scratch and intermediate reload
6766 int secondary_reload
= rl
->secondary_out_reload
;
6767 enum insn_code tertiary_icode
6768 = rld
[secondary_reload
].secondary_out_icode
;
6770 if (GET_MODE (reloadreg
) != mode
)
6771 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6773 if (tertiary_icode
!= CODE_FOR_nothing
)
6776 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6779 /* Copy primary reload reg to secondary reload reg.
6780 (Note that these have been swapped above, then
6781 secondary reload reg to OLD using our insn.) */
6783 /* If REAL_OLD is a paradoxical SUBREG, remove it
6784 and try to put the opposite SUBREG on
6786 if (GET_CODE (real_old
) == SUBREG
6787 && (GET_MODE_SIZE (GET_MODE (real_old
))
6788 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6789 && 0 != (tem
= gen_lowpart_common
6790 (GET_MODE (SUBREG_REG (real_old
)),
6792 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6794 gen_reload (reloadreg
, second_reloadreg
,
6795 rl
->opnum
, rl
->when_needed
);
6796 emit_insn ((GEN_FCN (tertiary_icode
)
6797 (real_old
, reloadreg
, third_reloadreg
)));
6802 /* Copy between the reload regs here and then to
6805 gen_reload (reloadreg
, second_reloadreg
,
6806 rl
->opnum
, rl
->when_needed
);
6812 /* Output the last reload insn. */
6817 /* Don't output the last reload if OLD is not the dest of
6818 INSN and is in the src and is clobbered by INSN. */
6819 if (! flag_expensive_optimizations
6821 || !(set
= single_set (insn
))
6822 || rtx_equal_p (old
, SET_DEST (set
))
6823 || !reg_mentioned_p (old
, SET_SRC (set
))
6824 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
6825 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
6826 gen_reload (old
, reloadreg
, rl
->opnum
,
6830 /* Look at all insns we emitted, just to be safe. */
6831 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6834 rtx pat
= PATTERN (p
);
6836 /* If this output reload doesn't come from a spill reg,
6837 clear any memory of reloaded copies of the pseudo reg.
6838 If this output reload comes from a spill reg,
6839 reg_has_output_reload will make this do nothing. */
6840 note_stores (pat
, forget_old_reloads_1
, NULL
);
6842 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6844 rtx set
= single_set (insn
);
6845 if (reload_spill_index
[j
] < 0
6847 && SET_SRC (set
) == rl
->reg_rtx
)
6849 int src
= REGNO (SET_SRC (set
));
6851 reload_spill_index
[j
] = src
;
6852 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6853 if (find_regno_note (insn
, REG_DEAD
, src
))
6854 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6856 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6858 int s
= rl
->secondary_out_reload
;
6859 set
= single_set (p
);
6860 /* If this reload copies only to the secondary reload
6861 register, the secondary reload does the actual
6863 if (s
>= 0 && set
== NULL_RTX
)
6864 /* We can't tell what function the secondary reload
6865 has and where the actual store to the pseudo is
6866 made; leave new_spill_reg_store alone. */
6869 && SET_SRC (set
) == rl
->reg_rtx
6870 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6872 /* Usually the next instruction will be the
6873 secondary reload insn; if we can confirm
6874 that it is, setting new_spill_reg_store to
6875 that insn will allow an extra optimization. */
6876 rtx s_reg
= rld
[s
].reg_rtx
;
6877 rtx next
= NEXT_INSN (p
);
6878 rld
[s
].out
= rl
->out
;
6879 rld
[s
].out_reg
= rl
->out_reg
;
6880 set
= single_set (next
);
6881 if (set
&& SET_SRC (set
) == s_reg
6882 && ! new_spill_reg_store
[REGNO (s_reg
)])
6884 SET_HARD_REG_BIT (reg_is_output_reload
,
6886 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6890 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6895 if (rl
->when_needed
== RELOAD_OTHER
)
6897 emit_insn (other_output_reload_insns
[rl
->opnum
]);
6898 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6901 output_reload_insns
[rl
->opnum
] = get_insns ();
6903 if (flag_non_call_exceptions
)
6904 copy_eh_notes (insn
, get_insns ());
6909 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6910 and has the number J. */
6912 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6914 rtx insn
= chain
->insn
;
6915 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
6916 ? rl
->in_reg
: rl
->in
);
6919 /* AUTO_INC reloads need to be handled even if inherited. We got an
6920 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6921 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6922 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6923 && rl
->reg_rtx
!= 0)
6924 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6926 /* When inheriting a wider reload, we have a MEM in rl->in,
6927 e.g. inheriting a SImode output reload for
6928 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6929 if (optimize
&& reload_inherited
[j
] && rl
->in
6931 && MEM_P (rl
->in_reg
)
6932 && reload_spill_index
[j
] >= 0
6933 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6934 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6936 /* If we are reloading a register that was recently stored in with an
6937 output-reload, see if we can prove there was
6938 actually no need to store the old value in it. */
6941 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6942 that there may be multiple uses of the previous output reload.
6943 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6944 && rl
->when_needed
== RELOAD_FOR_INPUT
6945 && (reload_inherited
[j
] || reload_override_in
[j
])
6947 && REG_P (rl
->reg_rtx
)
6948 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6950 /* There doesn't seem to be any reason to restrict this to pseudos
6951 and doing so loses in the case where we are copying from a
6952 register of the wrong class. */
6953 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6954 >= FIRST_PSEUDO_REGISTER
)
6956 /* The insn might have already some references to stackslots
6957 replaced by MEMs, while reload_out_reg still names the
6959 && (dead_or_set_p (insn
,
6960 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6961 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6963 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6966 /* Do output reloading for reload RL, which is for the insn described by
6967 CHAIN and has the number J.
6968 ??? At some point we need to support handling output reloads of
6969 JUMP_INSNs or insns that set cc0. */
6971 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6974 rtx insn
= chain
->insn
;
6975 /* If this is an output reload that stores something that is
6976 not loaded in this same reload, see if we can eliminate a previous
6978 rtx pseudo
= rl
->out_reg
;
6983 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6984 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6985 && reg_last_reload_reg
[REGNO (pseudo
)])
6987 int pseudo_no
= REGNO (pseudo
);
6988 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6990 /* We don't need to test full validity of last_regno for
6991 inherit here; we only want to know if the store actually
6992 matches the pseudo. */
6993 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6994 && reg_reloaded_contents
[last_regno
] == pseudo_no
6995 && spill_reg_store
[last_regno
]
6996 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6997 delete_output_reload (insn
, j
, last_regno
);
7002 || rl
->reg_rtx
== old
7003 || rl
->reg_rtx
== 0)
7006 /* An output operand that dies right away does need a reload,
7007 but need not be copied from it. Show the new location in the
7009 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7010 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7012 XEXP (note
, 0) = rl
->reg_rtx
;
7015 /* Likewise for a SUBREG of an operand that dies. */
7016 else if (GET_CODE (old
) == SUBREG
7017 && REG_P (SUBREG_REG (old
))
7018 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7021 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7025 else if (GET_CODE (old
) == SCRATCH
)
7026 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7027 but we don't want to make an output reload. */
7030 /* If is a JUMP_INSN, we can't support output reloads yet. */
7031 gcc_assert (!JUMP_P (insn
));
7033 emit_output_reload_insns (chain
, rld
+ j
, j
);
7036 /* Reload number R reloads from or to a group of hard registers starting at
7037 register REGNO. Return true if it can be treated for inheritance purposes
7038 like a group of reloads, each one reloading a single hard register.
7039 The caller has already checked that the spill register and REGNO use
7040 the same number of registers to store the reload value. */
7043 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED
, int regno ATTRIBUTE_UNUSED
)
7045 #ifdef CANNOT_CHANGE_MODE_CLASS
7046 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index
[r
],
7047 GET_MODE (rld
[r
].reg_rtx
),
7048 reg_raw_mode
[reload_spill_index
[r
]])
7049 && !REG_CANNOT_CHANGE_MODE_P (regno
,
7050 GET_MODE (rld
[r
].reg_rtx
),
7051 reg_raw_mode
[regno
]));
7057 /* Output insns to reload values in and out of the chosen reload regs. */
7060 emit_reload_insns (struct insn_chain
*chain
)
7062 rtx insn
= chain
->insn
;
7066 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7068 for (j
= 0; j
< reload_n_operands
; j
++)
7069 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7070 = inpaddr_address_reload_insns
[j
]
7071 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7072 = outaddr_address_reload_insns
[j
]
7073 = other_output_reload_insns
[j
] = 0;
7074 other_input_address_reload_insns
= 0;
7075 other_input_reload_insns
= 0;
7076 operand_reload_insns
= 0;
7077 other_operand_reload_insns
= 0;
7079 /* Dump reloads into the dump file. */
7082 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7083 debug_reload_to_stream (dump_file
);
7086 /* Now output the instructions to copy the data into and out of the
7087 reload registers. Do these in the order that the reloads were reported,
7088 since reloads of base and index registers precede reloads of operands
7089 and the operands may need the base and index registers reloaded. */
7091 for (j
= 0; j
< n_reloads
; j
++)
7094 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7095 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
7097 do_input_reload (chain
, rld
+ j
, j
);
7098 do_output_reload (chain
, rld
+ j
, j
);
7101 /* Now write all the insns we made for reloads in the order expected by
7102 the allocation functions. Prior to the insn being reloaded, we write
7103 the following reloads:
7105 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7107 RELOAD_OTHER reloads.
7109 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7110 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7111 RELOAD_FOR_INPUT reload for the operand.
7113 RELOAD_FOR_OPADDR_ADDRS reloads.
7115 RELOAD_FOR_OPERAND_ADDRESS reloads.
7117 After the insn being reloaded, we write the following:
7119 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7120 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7121 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7122 reloads for the operand. The RELOAD_OTHER output reloads are
7123 output in descending order by reload number. */
7125 emit_insn_before (other_input_address_reload_insns
, insn
);
7126 emit_insn_before (other_input_reload_insns
, insn
);
7128 for (j
= 0; j
< reload_n_operands
; j
++)
7130 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7131 emit_insn_before (input_address_reload_insns
[j
], insn
);
7132 emit_insn_before (input_reload_insns
[j
], insn
);
7135 emit_insn_before (other_operand_reload_insns
, insn
);
7136 emit_insn_before (operand_reload_insns
, insn
);
7138 for (j
= 0; j
< reload_n_operands
; j
++)
7140 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7141 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7142 x
= emit_insn_after (output_reload_insns
[j
], x
);
7143 emit_insn_after (other_output_reload_insns
[j
], x
);
7146 /* For all the spill regs newly reloaded in this instruction,
7147 record what they were reloaded from, so subsequent instructions
7148 can inherit the reloads.
7150 Update spill_reg_store for the reloads of this insn.
7151 Copy the elements that were updated in the loop above. */
7153 for (j
= 0; j
< n_reloads
; j
++)
7155 int r
= reload_order
[j
];
7156 int i
= reload_spill_index
[r
];
7158 /* If this is a non-inherited input reload from a pseudo, we must
7159 clear any memory of a previous store to the same pseudo. Only do
7160 something if there will not be an output reload for the pseudo
7162 if (rld
[r
].in_reg
!= 0
7163 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7165 rtx reg
= rld
[r
].in_reg
;
7167 if (GET_CODE (reg
) == SUBREG
)
7168 reg
= SUBREG_REG (reg
);
7171 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7172 && ! reg_has_output_reload
[REGNO (reg
)])
7174 int nregno
= REGNO (reg
);
7176 if (reg_last_reload_reg
[nregno
])
7178 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7180 if (reg_reloaded_contents
[last_regno
] == nregno
)
7181 spill_reg_store
[last_regno
] = 0;
7186 /* I is nonneg if this reload used a register.
7187 If rld[r].reg_rtx is 0, this is an optional reload
7188 that we opted to ignore. */
7190 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7192 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7194 int part_reaches_end
= 0;
7195 int all_reaches_end
= 1;
7197 /* For a multi register reload, we need to check if all or part
7198 of the value lives to the end. */
7199 for (k
= 0; k
< nr
; k
++)
7201 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7202 rld
[r
].when_needed
))
7203 part_reaches_end
= 1;
7205 all_reaches_end
= 0;
7208 /* Ignore reloads that don't reach the end of the insn in
7210 if (all_reaches_end
)
7212 /* First, clear out memory of what used to be in this spill reg.
7213 If consecutive registers are used, clear them all. */
7215 for (k
= 0; k
< nr
; k
++)
7217 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7218 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7221 /* Maybe the spill reg contains a copy of reload_out. */
7223 && (REG_P (rld
[r
].out
)
7227 || REG_P (rld
[r
].out_reg
)))
7229 rtx out
= (REG_P (rld
[r
].out
)
7233 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7234 int nregno
= REGNO (out
);
7235 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7236 : hard_regno_nregs
[nregno
]
7237 [GET_MODE (rld
[r
].reg_rtx
)]);
7240 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7241 spill_reg_stored_to
[i
] = out
;
7242 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7244 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7246 && inherit_piecemeal_p (r
, nregno
));
7248 /* If NREGNO is a hard register, it may occupy more than
7249 one register. If it does, say what is in the
7250 rest of the registers assuming that both registers
7251 agree on how many words the object takes. If not,
7252 invalidate the subsequent registers. */
7254 if (nregno
< FIRST_PSEUDO_REGISTER
)
7255 for (k
= 1; k
< nnr
; k
++)
7256 reg_last_reload_reg
[nregno
+ k
]
7258 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7261 /* Now do the inverse operation. */
7262 for (k
= 0; k
< nr
; k
++)
7264 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7265 reg_reloaded_contents
[i
+ k
]
7266 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7269 reg_reloaded_insn
[i
+ k
] = insn
;
7270 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7271 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (out
)))
7272 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7276 /* Maybe the spill reg contains a copy of reload_in. Only do
7277 something if there will not be an output reload for
7278 the register being reloaded. */
7279 else if (rld
[r
].out_reg
== 0
7281 && ((REG_P (rld
[r
].in
)
7282 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7283 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7284 || (REG_P (rld
[r
].in_reg
)
7285 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7286 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7293 if (REG_P (rld
[r
].in
)
7294 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7296 else if (REG_P (rld
[r
].in_reg
))
7299 in
= XEXP (rld
[r
].in_reg
, 0);
7300 nregno
= REGNO (in
);
7302 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7303 : hard_regno_nregs
[nregno
]
7304 [GET_MODE (rld
[r
].reg_rtx
)]);
7306 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7308 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7310 && inherit_piecemeal_p (r
, nregno
));
7312 if (nregno
< FIRST_PSEUDO_REGISTER
)
7313 for (k
= 1; k
< nnr
; k
++)
7314 reg_last_reload_reg
[nregno
+ k
]
7316 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7319 /* Unless we inherited this reload, show we haven't
7320 recently done a store.
7321 Previous stores of inherited auto_inc expressions
7322 also have to be discarded. */
7323 if (! reload_inherited
[r
]
7324 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7325 spill_reg_store
[i
] = 0;
7327 for (k
= 0; k
< nr
; k
++)
7329 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7330 reg_reloaded_contents
[i
+ k
]
7331 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7334 reg_reloaded_insn
[i
+ k
] = insn
;
7335 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7336 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (in
)))
7337 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7342 /* However, if part of the reload reaches the end, then we must
7343 invalidate the old info for the part that survives to the end. */
7344 else if (part_reaches_end
)
7346 for (k
= 0; k
< nr
; k
++)
7347 if (reload_reg_reaches_end_p (i
+ k
,
7349 rld
[r
].when_needed
))
7350 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7354 /* The following if-statement was #if 0'd in 1.34 (or before...).
7355 It's reenabled in 1.35 because supposedly nothing else
7356 deals with this problem. */
7358 /* If a register gets output-reloaded from a non-spill register,
7359 that invalidates any previous reloaded copy of it.
7360 But forget_old_reloads_1 won't get to see it, because
7361 it thinks only about the original insn. So invalidate it here. */
7362 if (i
< 0 && rld
[r
].out
!= 0
7363 && (REG_P (rld
[r
].out
)
7364 || (MEM_P (rld
[r
].out
)
7365 && REG_P (rld
[r
].out_reg
))))
7367 rtx out
= (REG_P (rld
[r
].out
)
7368 ? rld
[r
].out
: rld
[r
].out_reg
);
7369 int nregno
= REGNO (out
);
7370 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7372 rtx src_reg
, store_insn
= NULL_RTX
;
7374 reg_last_reload_reg
[nregno
] = 0;
7376 /* If we can find a hard register that is stored, record
7377 the storing insn so that we may delete this insn with
7378 delete_output_reload. */
7379 src_reg
= rld
[r
].reg_rtx
;
7381 /* If this is an optional reload, try to find the source reg
7382 from an input reload. */
7385 rtx set
= single_set (insn
);
7386 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7390 src_reg
= SET_SRC (set
);
7392 for (k
= 0; k
< n_reloads
; k
++)
7394 if (rld
[k
].in
== src_reg
)
7396 src_reg
= rld
[k
].reg_rtx
;
7403 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7404 if (src_reg
&& REG_P (src_reg
)
7405 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7407 int src_regno
= REGNO (src_reg
);
7408 int nr
= hard_regno_nregs
[src_regno
][rld
[r
].mode
];
7409 /* The place where to find a death note varies with
7410 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7411 necessarily checked exactly in the code that moves
7412 notes, so just check both locations. */
7413 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7414 if (! note
&& store_insn
)
7415 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7418 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7419 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7420 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7421 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7422 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7423 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7424 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ nr
,
7425 GET_MODE (src_reg
)))
7426 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7428 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7430 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7432 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7434 reg_last_reload_reg
[nregno
] = src_reg
;
7435 /* We have to set reg_has_output_reload here, or else
7436 forget_old_reloads_1 will clear reg_last_reload_reg
7438 reg_has_output_reload
[nregno
] = 1;
7443 int num_regs
= hard_regno_nregs
[nregno
][GET_MODE (rld
[r
].out
)];
7445 while (num_regs
-- > 0)
7446 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7450 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7453 /* Go through the motions to emit INSN and test if it is strictly valid.
7454 Return the emitted insn if valid, else return NULL. */
7457 emit_insn_if_valid_for_reload (rtx insn
)
7459 rtx last
= get_last_insn ();
7462 insn
= emit_insn (insn
);
7463 code
= recog_memoized (insn
);
7467 extract_insn (insn
);
7468 /* We want constrain operands to treat this insn strictly in its
7469 validity determination, i.e., the way it would after reload has
7471 if (constrain_operands (1))
7475 delete_insns_since (last
);
7479 /* Emit code to perform a reload from IN (which may be a reload register) to
7480 OUT (which may also be a reload register). IN or OUT is from operand
7481 OPNUM with reload type TYPE.
7483 Returns first insn emitted. */
7486 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7488 rtx last
= get_last_insn ();
7491 /* If IN is a paradoxical SUBREG, remove it and try to put the
7492 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7493 if (GET_CODE (in
) == SUBREG
7494 && (GET_MODE_SIZE (GET_MODE (in
))
7495 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7496 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7497 in
= SUBREG_REG (in
), out
= tem
;
7498 else if (GET_CODE (out
) == SUBREG
7499 && (GET_MODE_SIZE (GET_MODE (out
))
7500 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7501 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7502 out
= SUBREG_REG (out
), in
= tem
;
7504 /* How to do this reload can get quite tricky. Normally, we are being
7505 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7506 register that didn't get a hard register. In that case we can just
7507 call emit_move_insn.
7509 We can also be asked to reload a PLUS that adds a register or a MEM to
7510 another register, constant or MEM. This can occur during frame pointer
7511 elimination and while reloading addresses. This case is handled by
7512 trying to emit a single insn to perform the add. If it is not valid,
7513 we use a two insn sequence.
7515 Or we can be asked to reload an unary operand that was a fragment of
7516 an addressing mode, into a register. If it isn't recognized as-is,
7517 we try making the unop operand and the reload-register the same:
7518 (set reg:X (unop:X expr:Y))
7519 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7521 Finally, we could be called to handle an 'o' constraint by putting
7522 an address into a register. In that case, we first try to do this
7523 with a named pattern of "reload_load_address". If no such pattern
7524 exists, we just emit a SET insn and hope for the best (it will normally
7525 be valid on machines that use 'o').
7527 This entire process is made complex because reload will never
7528 process the insns we generate here and so we must ensure that
7529 they will fit their constraints and also by the fact that parts of
7530 IN might be being reloaded separately and replaced with spill registers.
7531 Because of this, we are, in some sense, just guessing the right approach
7532 here. The one listed above seems to work.
7534 ??? At some point, this whole thing needs to be rethought. */
7536 if (GET_CODE (in
) == PLUS
7537 && (REG_P (XEXP (in
, 0))
7538 || GET_CODE (XEXP (in
, 0)) == SUBREG
7539 || MEM_P (XEXP (in
, 0)))
7540 && (REG_P (XEXP (in
, 1))
7541 || GET_CODE (XEXP (in
, 1)) == SUBREG
7542 || CONSTANT_P (XEXP (in
, 1))
7543 || MEM_P (XEXP (in
, 1))))
7545 /* We need to compute the sum of a register or a MEM and another
7546 register, constant, or MEM, and put it into the reload
7547 register. The best possible way of doing this is if the machine
7548 has a three-operand ADD insn that accepts the required operands.
7550 The simplest approach is to try to generate such an insn and see if it
7551 is recognized and matches its constraints. If so, it can be used.
7553 It might be better not to actually emit the insn unless it is valid,
7554 but we need to pass the insn as an operand to `recog' and
7555 `extract_insn' and it is simpler to emit and then delete the insn if
7556 not valid than to dummy things up. */
7558 rtx op0
, op1
, tem
, insn
;
7561 op0
= find_replacement (&XEXP (in
, 0));
7562 op1
= find_replacement (&XEXP (in
, 1));
7564 /* Since constraint checking is strict, commutativity won't be
7565 checked, so we need to do that here to avoid spurious failure
7566 if the add instruction is two-address and the second operand
7567 of the add is the same as the reload reg, which is frequently
7568 the case. If the insn would be A = B + A, rearrange it so
7569 it will be A = A + B as constrain_operands expects. */
7571 if (REG_P (XEXP (in
, 1))
7572 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7573 tem
= op0
, op0
= op1
, op1
= tem
;
7575 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7576 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7578 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7582 /* If that failed, we must use a conservative two-insn sequence.
7584 Use a move to copy one operand into the reload register. Prefer
7585 to reload a constant, MEM or pseudo since the move patterns can
7586 handle an arbitrary operand. If OP1 is not a constant, MEM or
7587 pseudo and OP1 is not a valid operand for an add instruction, then
7590 After reloading one of the operands into the reload register, add
7591 the reload register to the output register.
7593 If there is another way to do this for a specific machine, a
7594 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7597 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7599 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
7601 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7602 || (code
!= CODE_FOR_nothing
7603 && ! ((*insn_data
[code
].operand
[2].predicate
)
7604 (op1
, insn_data
[code
].operand
[2].mode
))))
7605 tem
= op0
, op0
= op1
, op1
= tem
;
7607 gen_reload (out
, op0
, opnum
, type
);
7609 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7610 This fixes a problem on the 32K where the stack pointer cannot
7611 be used as an operand of an add insn. */
7613 if (rtx_equal_p (op0
, op1
))
7616 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
7619 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7621 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7625 /* If that failed, copy the address register to the reload register.
7626 Then add the constant to the reload register. */
7628 gen_reload (out
, op1
, opnum
, type
);
7629 insn
= emit_insn (gen_add2_insn (out
, op0
));
7630 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7633 #ifdef SECONDARY_MEMORY_NEEDED
7634 /* If we need a memory location to do the move, do it that way. */
7635 else if ((REG_P (in
) || GET_CODE (in
) == SUBREG
)
7636 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7637 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
7638 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7639 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7640 REGNO_REG_CLASS (reg_or_subregno (out
)),
7643 /* Get the memory to use and rewrite both registers to its mode. */
7644 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7646 if (GET_MODE (loc
) != GET_MODE (out
))
7647 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7649 if (GET_MODE (loc
) != GET_MODE (in
))
7650 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7652 gen_reload (loc
, in
, opnum
, type
);
7653 gen_reload (out
, loc
, opnum
, type
);
7656 else if (REG_P (out
) && UNARY_P (in
))
7663 /* First, try a plain SET. */
7664 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7668 /* If that failed, move the inner operand to the reload
7669 register, and try the same unop with the inner expression
7670 replaced with the reload register. */
7673 if (GET_MODE (op1
) != GET_MODE (out
))
7674 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
7678 gen_reload (out_moded
, op1
, opnum
, type
);
7681 = gen_rtx_SET (VOIDmode
, out
,
7682 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
7684 insn
= emit_insn_if_valid_for_reload (insn
);
7688 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7692 fatal_insn ("Failure trying to reload:", set
);
7694 /* If IN is a simple operand, use gen_move_insn. */
7695 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
7696 emit_insn (gen_move_insn (out
, in
));
7698 #ifdef HAVE_reload_load_address
7699 else if (HAVE_reload_load_address
)
7700 emit_insn (gen_reload_load_address (out
, in
));
7703 /* Otherwise, just write (set OUT IN) and hope for the best. */
7705 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7707 /* Return the first insn emitted.
7708 We can not just return get_last_insn, because there may have
7709 been multiple instructions emitted. Also note that gen_move_insn may
7710 emit more than one insn itself, so we can not assume that there is one
7711 insn emitted per emit_insn_before call. */
7713 return last
? NEXT_INSN (last
) : get_insns ();
7716 /* Delete a previously made output-reload whose result we now believe
7717 is not needed. First we double-check.
7719 INSN is the insn now being processed.
7720 LAST_RELOAD_REG is the hard register number for which we want to delete
7721 the last output reload.
7722 J is the reload-number that originally used REG. The caller has made
7723 certain that reload J doesn't use REG any longer for input. */
7726 delete_output_reload (rtx insn
, int j
, int last_reload_reg
)
7728 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7729 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7732 int n_inherited
= 0;
7736 /* It is possible that this reload has been only used to set another reload
7737 we eliminated earlier and thus deleted this instruction too. */
7738 if (INSN_DELETED_P (output_reload_insn
))
7741 /* Get the raw pseudo-register referred to. */
7743 while (GET_CODE (reg
) == SUBREG
)
7744 reg
= SUBREG_REG (reg
);
7745 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7747 /* This is unsafe if the operand occurs more often in the current
7748 insn than it is inherited. */
7749 for (k
= n_reloads
- 1; k
>= 0; k
--)
7751 rtx reg2
= rld
[k
].in
;
7754 if (MEM_P (reg2
) || reload_override_in
[k
])
7755 reg2
= rld
[k
].in_reg
;
7757 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7758 reg2
= XEXP (rld
[k
].in_reg
, 0);
7760 while (GET_CODE (reg2
) == SUBREG
)
7761 reg2
= SUBREG_REG (reg2
);
7762 if (rtx_equal_p (reg2
, reg
))
7764 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7767 reg2
= rld
[k
].out_reg
;
7770 while (GET_CODE (reg2
) == SUBREG
)
7771 reg2
= XEXP (reg2
, 0);
7772 if (rtx_equal_p (reg2
, reg
))
7779 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7781 n_occurrences
+= count_occurrences (PATTERN (insn
),
7782 eliminate_regs (substed
, 0,
7784 if (n_occurrences
> n_inherited
)
7787 /* If the pseudo-reg we are reloading is no longer referenced
7788 anywhere between the store into it and here,
7789 and we're within the same basic block, then the value can only
7790 pass through the reload reg and end up here.
7791 Otherwise, give up--return. */
7792 for (i1
= NEXT_INSN (output_reload_insn
);
7793 i1
!= insn
; i1
= NEXT_INSN (i1
))
7795 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
7797 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
7798 && reg_mentioned_p (reg
, PATTERN (i1
)))
7800 /* If this is USE in front of INSN, we only have to check that
7801 there are no more references than accounted for by inheritance. */
7802 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
7804 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7805 i1
= NEXT_INSN (i1
);
7807 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7813 /* We will be deleting the insn. Remove the spill reg information. */
7814 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
7816 spill_reg_store
[last_reload_reg
+ k
] = 0;
7817 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
7820 /* The caller has already checked that REG dies or is set in INSN.
7821 It has also checked that we are optimizing, and thus some
7822 inaccuracies in the debugging information are acceptable.
7823 So we could just delete output_reload_insn. But in some cases
7824 we can improve the debugging information without sacrificing
7825 optimization - maybe even improving the code: See if the pseudo
7826 reg has been completely replaced with reload regs. If so, delete
7827 the store insn and forget we had a stack slot for the pseudo. */
7828 if (rld
[j
].out
!= rld
[j
].in
7829 && REG_N_DEATHS (REGNO (reg
)) == 1
7830 && REG_N_SETS (REGNO (reg
)) == 1
7831 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7832 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7836 /* We know that it was used only between here and the beginning of
7837 the current basic block. (We also know that the last use before
7838 INSN was the output reload we are thinking of deleting, but never
7839 mind that.) Search that range; see if any ref remains. */
7840 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7842 rtx set
= single_set (i2
);
7844 /* Uses which just store in the pseudo don't count,
7845 since if they are the only uses, they are dead. */
7846 if (set
!= 0 && SET_DEST (set
) == reg
)
7851 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
7852 && reg_mentioned_p (reg
, PATTERN (i2
)))
7854 /* Some other ref remains; just delete the output reload we
7856 delete_address_reloads (output_reload_insn
, insn
);
7857 delete_insn (output_reload_insn
);
7862 /* Delete the now-dead stores into this pseudo. Note that this
7863 loop also takes care of deleting output_reload_insn. */
7864 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7866 rtx set
= single_set (i2
);
7868 if (set
!= 0 && SET_DEST (set
) == reg
)
7870 delete_address_reloads (i2
, insn
);
7878 /* For the debugging info, say the pseudo lives in this reload reg. */
7879 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7880 alter_reg (REGNO (reg
), -1);
7884 delete_address_reloads (output_reload_insn
, insn
);
7885 delete_insn (output_reload_insn
);
7889 /* We are going to delete DEAD_INSN. Recursively delete loads of
7890 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7891 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7893 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
7895 rtx set
= single_set (dead_insn
);
7896 rtx set2
, dst
, prev
, next
;
7899 rtx dst
= SET_DEST (set
);
7901 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7903 /* If we deleted the store from a reloaded post_{in,de}c expression,
7904 we can delete the matching adds. */
7905 prev
= PREV_INSN (dead_insn
);
7906 next
= NEXT_INSN (dead_insn
);
7907 if (! prev
|| ! next
)
7909 set
= single_set (next
);
7910 set2
= single_set (prev
);
7912 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7913 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7914 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7916 dst
= SET_DEST (set
);
7917 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7918 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7919 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7920 || (INTVAL (XEXP (SET_SRC (set
), 1))
7921 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7923 delete_related_insns (prev
);
7924 delete_related_insns (next
);
7927 /* Subfunction of delete_address_reloads: process registers found in X. */
7929 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
7931 rtx prev
, set
, dst
, i2
;
7933 enum rtx_code code
= GET_CODE (x
);
7937 const char *fmt
= GET_RTX_FORMAT (code
);
7938 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7941 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7942 else if (fmt
[i
] == 'E')
7944 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7945 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7952 if (spill_reg_order
[REGNO (x
)] < 0)
7955 /* Scan backwards for the insn that sets x. This might be a way back due
7957 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7959 code
= GET_CODE (prev
);
7960 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7964 if (reg_set_p (x
, PATTERN (prev
)))
7966 if (reg_referenced_p (x
, PATTERN (prev
)))
7969 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7971 /* Check that PREV only sets the reload register. */
7972 set
= single_set (prev
);
7975 dst
= SET_DEST (set
);
7977 || ! rtx_equal_p (dst
, x
))
7979 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7981 /* Check if DST was used in a later insn -
7982 it might have been inherited. */
7983 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7989 if (reg_referenced_p (dst
, PATTERN (i2
)))
7991 /* If there is a reference to the register in the current insn,
7992 it might be loaded in a non-inherited reload. If no other
7993 reload uses it, that means the register is set before
7995 if (i2
== current_insn
)
7997 for (j
= n_reloads
- 1; j
>= 0; j
--)
7998 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7999 || reload_override_in
[j
] == dst
)
8001 for (j
= n_reloads
- 1; j
>= 0; j
--)
8002 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8011 /* If DST is still live at CURRENT_INSN, check if it is used for
8012 any reload. Note that even if CURRENT_INSN sets DST, we still
8013 have to check the reloads. */
8014 if (i2
== current_insn
)
8016 for (j
= n_reloads
- 1; j
>= 0; j
--)
8017 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8018 || reload_override_in
[j
] == dst
)
8020 /* ??? We can't finish the loop here, because dst might be
8021 allocated to a pseudo in this block if no reload in this
8022 block needs any of the classes containing DST - see
8023 spill_hard_reg. There is no easy way to tell this, so we
8024 have to scan till the end of the basic block. */
8026 if (reg_set_p (dst
, PATTERN (i2
)))
8030 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8031 reg_reloaded_contents
[REGNO (dst
)] = -1;
8035 /* Output reload-insns to reload VALUE into RELOADREG.
8036 VALUE is an autoincrement or autodecrement RTX whose operand
8037 is a register or memory location;
8038 so reloading involves incrementing that location.
8039 IN is either identical to VALUE, or some cheaper place to reload from.
8041 INC_AMOUNT is the number to increment or decrement by (always positive).
8042 This cannot be deduced from VALUE.
8044 Return the instruction that stores into RELOADREG. */
8047 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8049 /* REG or MEM to be copied and incremented. */
8050 rtx incloc
= XEXP (value
, 0);
8051 /* Nonzero if increment after copying. */
8052 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8058 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8060 /* No hard register is equivalent to this register after
8061 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8062 we could inc/dec that register as well (maybe even using it for
8063 the source), but I'm not sure it's worth worrying about. */
8065 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8067 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8068 inc_amount
= -inc_amount
;
8070 inc
= GEN_INT (inc_amount
);
8072 /* If this is post-increment, first copy the location to the reload reg. */
8073 if (post
&& real_in
!= reloadreg
)
8074 emit_insn (gen_move_insn (reloadreg
, real_in
));
8078 /* See if we can directly increment INCLOC. Use a method similar to
8079 that in gen_reload. */
8081 last
= get_last_insn ();
8082 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8083 gen_rtx_PLUS (GET_MODE (incloc
),
8086 code
= recog_memoized (add_insn
);
8089 extract_insn (add_insn
);
8090 if (constrain_operands (1))
8092 /* If this is a pre-increment and we have incremented the value
8093 where it lives, copy the incremented value to RELOADREG to
8094 be used as an address. */
8097 emit_insn (gen_move_insn (reloadreg
, incloc
));
8102 delete_insns_since (last
);
8105 /* If couldn't do the increment directly, must increment in RELOADREG.
8106 The way we do this depends on whether this is pre- or post-increment.
8107 For pre-increment, copy INCLOC to the reload register, increment it
8108 there, then save back. */
8112 if (in
!= reloadreg
)
8113 emit_insn (gen_move_insn (reloadreg
, real_in
));
8114 emit_insn (gen_add2_insn (reloadreg
, inc
));
8115 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8120 Because this might be a jump insn or a compare, and because RELOADREG
8121 may not be available after the insn in an input reload, we must do
8122 the incrementation before the insn being reloaded for.
8124 We have already copied IN to RELOADREG. Increment the copy in
8125 RELOADREG, save that back, then decrement RELOADREG so it has
8126 the original value. */
8128 emit_insn (gen_add2_insn (reloadreg
, inc
));
8129 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8130 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8138 add_auto_inc_notes (rtx insn
, rtx x
)
8140 enum rtx_code code
= GET_CODE (x
);
8144 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8147 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
8151 /* Scan all the operand sub-expressions. */
8152 fmt
= GET_RTX_FORMAT (code
);
8153 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8156 add_auto_inc_notes (insn
, XEXP (x
, i
));
8157 else if (fmt
[i
] == 'E')
8158 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8159 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8164 /* Copy EH notes from an insn to its reloads. */
8166 copy_eh_notes (rtx insn
, rtx x
)
8168 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8171 for (; x
!= 0; x
= NEXT_INSN (x
))
8173 if (may_trap_p (PATTERN (x
)))
8175 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
8181 /* This is used by reload pass, that does emit some instructions after
8182 abnormal calls moving basic block end, but in fact it wants to emit
8183 them on the edge. Looks for abnormal call edges, find backward the
8184 proper call and fix the damage.
8186 Similar handle instructions throwing exceptions internally. */
8188 fixup_abnormal_edges (void)
8190 bool inserted
= false;
8198 /* Look for cases we are interested in - calls or instructions causing
8200 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8202 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8204 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8205 == (EDGE_ABNORMAL
| EDGE_EH
))
8208 if (e
&& !CALL_P (BB_END (bb
))
8209 && !can_throw_internal (BB_END (bb
)))
8213 /* Get past the new insns generated. Allow notes, as the insns
8214 may be already deleted. */
8216 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8217 && !can_throw_internal (insn
)
8218 && insn
!= BB_HEAD (bb
))
8219 insn
= PREV_INSN (insn
);
8221 if (CALL_P (insn
) || can_throw_internal (insn
))
8225 stop
= NEXT_INSN (BB_END (bb
));
8227 insn
= NEXT_INSN (insn
);
8229 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8230 if (e
->flags
& EDGE_FALLTHRU
)
8233 while (insn
&& insn
!= stop
)
8235 next
= NEXT_INSN (insn
);
8240 /* Sometimes there's still the return value USE.
8241 If it's placed after a trapping call (i.e. that
8242 call is the last insn anyway), we have no fallthru
8243 edge. Simply delete this use and don't try to insert
8244 on the non-existent edge. */
8245 if (GET_CODE (PATTERN (insn
)) != USE
)
8247 /* We're not deleting it, we're moving it. */
8248 INSN_DELETED_P (insn
) = 0;
8249 PREV_INSN (insn
) = NULL_RTX
;
8250 NEXT_INSN (insn
) = NULL_RTX
;
8252 insert_insn_on_edge (insn
, e
);
8260 /* It may be that we don't find any such trapping insn. In this
8261 case we discovered quite late that the insn that had been
8262 marked as can_throw_internal in fact couldn't trap at all.
8263 So we should in fact delete the EH edges out of the block. */
8265 purge_dead_edges (bb
);
8269 /* We've possibly turned single trapping insn into multiple ones. */
8270 if (flag_non_call_exceptions
)
8273 blocks
= sbitmap_alloc (last_basic_block
);
8274 sbitmap_ones (blocks
);
8275 find_many_sub_basic_blocks (blocks
);
8279 commit_edge_insertions ();
8281 #ifdef ENABLE_CHECKING
8282 /* Verify that we didn't turn one trapping insn into many, and that
8283 we found and corrected all of the problems wrt fixups on the
8285 verify_flow_info ();