* arm.c (arm_legitimate_index_p): For QImode the range of an offset
[official-gcc.git] / gcc / config / arm / arm.c
blob98c05cb6228c724fba652bd10bba3feab42960f8
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "obstack.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "reload.h"
41 #include "function.h"
42 #include "expr.h"
43 #include "optabs.h"
44 #include "toplev.h"
45 #include "recog.h"
46 #include "ggc.h"
47 #include "except.h"
48 #include "c-pragma.h"
49 #include "integrate.h"
50 #include "tm_p.h"
51 #include "target.h"
52 #include "target-def.h"
53 #include "debug.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static void arm_add_gc_roots (void);
63 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
64 rtx, rtx, int, int);
65 static unsigned bit_count (unsigned long);
66 static int arm_address_register_rtx_p (rtx, int);
67 static int arm_legitimate_index_p (enum machine_mode, rtx, int);
68 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
69 inline static int thumb_index_register_rtx_p (rtx, int);
70 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
71 static rtx emit_multi_reg_push (int);
72 static rtx emit_sfm (int, int);
73 #ifndef AOF_ASSEMBLER
74 static bool arm_assemble_integer (rtx, unsigned int, int);
75 #endif
76 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
77 static arm_cc get_arm_condition_code (rtx);
78 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
79 static rtx is_jump_table (rtx);
80 static const char *output_multi_immediate (rtx *, const char *, const char *,
81 int, HOST_WIDE_INT);
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx, HOST_WIDE_INT *);
84 static struct machine_function *arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree, rtx, rtx);
87 static void thumb_exit (FILE *, int, rtx);
88 static void thumb_pushpop (FILE *, int, int, int *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
102 rtx);
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
113 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
114 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static int arm_comp_type_attributes (tree, tree);
116 static void arm_set_default_type_attributes (tree);
117 static int arm_adjust_cost (rtx, rtx, rtx, int);
118 static int arm_use_dfa_pipeline_interface (void);
119 static int count_insns_for_constant (HOST_WIDE_INT, int);
120 static int arm_get_strip_length (int);
121 static bool arm_function_ok_for_sibcall (tree, tree);
122 static void arm_internal_label (FILE *, const char *, unsigned long);
123 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
124 tree);
125 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
126 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
127 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
128 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
129 static bool arm_9e_rtx_costs (rtx, int, int, int *);
130 static int arm_address_cost (rtx);
131 static bool arm_memory_load_p (rtx);
132 static bool arm_cirrus_insn_p (rtx);
133 static void cirrus_reorg (rtx);
134 static void arm_init_builtins (void);
135 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
136 static void arm_init_iwmmxt_builtins (void);
137 static rtx safe_vector_operand (rtx, enum machine_mode);
138 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
139 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
142 #ifdef OBJECT_FORMAT_ELF
143 static void arm_elf_asm_named_section (const char *, unsigned int);
144 #endif
145 #ifndef ARM_PE
146 static void arm_encode_section_info (tree, rtx, int);
147 #endif
148 #ifdef AOF_ASSEMBLER
149 static void aof_globalize_label (FILE *, const char *);
150 static void aof_dump_imports (FILE *);
151 static void aof_dump_pic_table (FILE *);
152 static void aof_file_start (void);
153 static void aof_file_end (void);
154 #endif
155 static rtx arm_struct_value_rtx (tree, int);
156 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
157 tree, int *, int);
160 /* Initialize the GCC target structure. */
161 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
162 #undef TARGET_MERGE_DECL_ATTRIBUTES
163 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
164 #endif
166 #undef TARGET_ATTRIBUTE_TABLE
167 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
169 #ifdef AOF_ASSEMBLER
170 #undef TARGET_ASM_BYTE_OP
171 #define TARGET_ASM_BYTE_OP "\tDCB\t"
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
176 #undef TARGET_ASM_GLOBALIZE_LABEL
177 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
178 #undef TARGET_ASM_FILE_START
179 #define TARGET_ASM_FILE_START aof_file_start
180 #undef TARGET_ASM_FILE_END
181 #define TARGET_ASM_FILE_END aof_file_end
182 #else
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP NULL
185 #undef TARGET_ASM_INTEGER
186 #define TARGET_ASM_INTEGER arm_assemble_integer
187 #endif
189 #undef TARGET_ASM_FUNCTION_PROLOGUE
190 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
192 #undef TARGET_ASM_FUNCTION_EPILOGUE
193 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
195 #undef TARGET_COMP_TYPE_ATTRIBUTES
196 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
198 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
199 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
201 #undef TARGET_SCHED_ADJUST_COST
202 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
204 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
205 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
207 #undef TARGET_ENCODE_SECTION_INFO
208 #ifdef ARM_PE
209 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
210 #else
211 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
212 #endif
214 #undef TARGET_STRIP_NAME_ENCODING
215 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
217 #undef TARGET_ASM_INTERNAL_LABEL
218 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
220 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
221 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
223 #undef TARGET_ASM_OUTPUT_MI_THUNK
224 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
225 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
226 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
228 /* This will be overridden in arm_override_options. */
229 #undef TARGET_RTX_COSTS
230 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
231 #undef TARGET_ADDRESS_COST
232 #define TARGET_ADDRESS_COST arm_address_cost
234 #undef TARGET_MACHINE_DEPENDENT_REORG
235 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
237 #undef TARGET_INIT_BUILTINS
238 #define TARGET_INIT_BUILTINS arm_init_builtins
239 #undef TARGET_EXPAND_BUILTIN
240 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
242 #undef TARGET_PROMOTE_FUNCTION_ARGS
243 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
244 #undef TARGET_PROMOTE_PROTOTYPES
245 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
247 #undef TARGET_STRUCT_VALUE_RTX
248 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
250 #undef TARGET_SETUP_INCOMING_VARARGS
251 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
253 struct gcc_target targetm = TARGET_INITIALIZER;
255 /* Obstack for minipool constant handling. */
256 static struct obstack minipool_obstack;
257 static char * minipool_startobj;
259 /* The maximum number of insns skipped which
260 will be conditionalised if possible. */
261 static int max_insns_skipped = 5;
263 extern FILE * asm_out_file;
265 /* True if we are currently building a constant table. */
266 int making_const_table;
268 /* Define the information needed to generate branch insns. This is
269 stored from the compare operation. */
270 rtx arm_compare_op0, arm_compare_op1;
272 /* The processor for which instructions should be scheduled. */
273 enum processor_type arm_tune = arm_none;
275 /* Which floating point model to use. */
276 enum arm_fp_model arm_fp_model;
278 /* Which floating point hardware is available. */
279 enum fputype arm_fpu_arch;
281 /* Which floating point hardware to schedule for. */
282 enum fputype arm_fpu_tune;
284 /* Whether to use floating point hardware. */
285 enum float_abi_type arm_float_abi;
287 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
288 enum prog_mode_type arm_prgmode;
290 /* Set by the -mfpu=... option. */
291 const char * target_fpu_name = NULL;
293 /* Set by the -mfpe=... option. */
294 const char * target_fpe_name = NULL;
296 /* Set by the -mfloat-abi=... option. */
297 const char * target_float_abi_name = NULL;
299 /* Used to parse -mstructure_size_boundary command line option. */
300 const char * structure_size_string = NULL;
301 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
303 /* Bit values used to identify processor capabilities. */
304 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
305 #define FL_ARCH3M (1 << 1) /* Extended multiply */
306 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
307 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
308 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
309 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
310 #define FL_THUMB (1 << 6) /* Thumb aware */
311 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
312 #define FL_STRONG (1 << 8) /* StrongARM */
313 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
314 #define FL_XSCALE (1 << 10) /* XScale */
315 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
316 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
317 media instructions. */
318 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
320 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
322 /* The bits in this mask specify which
323 instructions we are allowed to generate. */
324 static unsigned long insn_flags = 0;
326 /* The bits in this mask specify which instruction scheduling options should
327 be used. */
328 static unsigned long tune_flags = 0;
330 /* The following are used in the arm.md file as equivalents to bits
331 in the above two flag variables. */
333 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
334 int arm_arch3m = 0;
336 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
337 int arm_arch4 = 0;
339 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
340 int arm_arch5 = 0;
342 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
343 int arm_arch5e = 0;
345 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
346 int arm_arch6 = 0;
348 /* Nonzero if this chip can benefit from load scheduling. */
349 int arm_ld_sched = 0;
351 /* Nonzero if this chip is a StrongARM. */
352 int arm_is_strong = 0;
354 /* Nonzero if this chip supports Intel Wireless MMX technology. */
355 int arm_arch_iwmmxt = 0;
357 /* Nonzero if this chip is an XScale. */
358 int arm_arch_xscale = 0;
360 /* Nonzero if tuning for XScale */
361 int arm_tune_xscale = 0;
363 /* Nonzero if this chip is an ARM6 or an ARM7. */
364 int arm_is_6_or_7 = 0;
366 /* Nonzero if generating Thumb instructions. */
367 int thumb_code = 0;
369 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
370 must report the mode of the memory reference from PRINT_OPERAND to
371 PRINT_OPERAND_ADDRESS. */
372 enum machine_mode output_memory_reference_mode;
374 /* The register number to be used for the PIC offset register. */
375 const char * arm_pic_register_string = NULL;
376 int arm_pic_register = INVALID_REGNUM;
378 /* Set to 1 when a return insn is output, this means that the epilogue
379 is not needed. */
380 int return_used_this_function;
382 /* Set to 1 after arm_reorg has started. Reset to start at the start of
383 the next function. */
384 static int after_arm_reorg = 0;
386 /* The maximum number of insns to be used when loading a constant. */
387 static int arm_constant_limit = 3;
389 /* For an explanation of these variables, see final_prescan_insn below. */
390 int arm_ccfsm_state;
391 enum arm_cond_code arm_current_cc;
392 rtx arm_target_insn;
393 int arm_target_label;
395 /* The condition codes of the ARM, and the inverse function. */
396 static const char * const arm_condition_codes[] =
398 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
399 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
402 #define streq(string1, string2) (strcmp (string1, string2) == 0)
404 /* Initialization code. */
406 struct processors
408 const char *const name;
409 enum processor_type core;
410 const unsigned long flags;
411 bool (* rtx_costs) (rtx, int, int, int *);
414 /* Not all of these give usefully different compilation alternatives,
415 but there is no simple way of generalizing them. */
416 static const struct processors all_cores[] =
418 /* ARM Cores */
419 #define ARM_CORE(NAME, FLAGS, COSTS) \
420 {#NAME, arm_none, FLAGS, arm_##COSTS##_rtx_costs},
421 #include "arm-cores.def"
422 #undef ARM_CORE
423 {NULL, arm_none, 0, NULL}
426 static const struct processors all_architectures[] =
428 /* ARM Architectures */
429 /* We don't specify rtx_costs here as it will be figured out
430 from the core. */
432 { "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL},
433 { "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL},
434 { "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL},
435 { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M , NULL},
436 { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 , NULL},
437 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
438 implementations that support it, so we will leave it out for now. */
439 { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB , NULL},
440 { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
441 { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
442 { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL},
443 { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
444 { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
445 { "ep9312", ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL},
446 {"iwmmxt", iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL},
447 { NULL, arm_none, 0 , NULL}
450 /* This is a magic structure. The 'string' field is magically filled in
451 with a pointer to the value specified by the user on the command line
452 assuming that the user has specified such a value. */
454 struct arm_cpu_select arm_select[] =
456 /* string name processors */
457 { NULL, "-mcpu=", all_cores },
458 { NULL, "-march=", all_architectures },
459 { NULL, "-mtune=", all_cores }
462 struct fpu_desc
464 const char * name;
465 enum fputype fpu;
469 /* Available values for for -mfpu=. */
471 static const struct fpu_desc all_fpus[] =
473 {"fpa", FPUTYPE_FPA},
474 {"fpe2", FPUTYPE_FPA_EMU2},
475 {"fpe3", FPUTYPE_FPA_EMU2},
476 {"maverick", FPUTYPE_MAVERICK},
477 {"vfp", FPUTYPE_VFP}
481 /* Floating point models used by the different hardware.
482 See fputype in arm.h. */
484 static const enum fputype fp_model_for_fpu[] =
486 /* No FP hardware. */
487 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
488 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
489 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
490 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
491 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
492 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
496 struct float_abi
498 const char * name;
499 enum float_abi_type abi_type;
503 /* Available values for -mfloat-abi=. */
505 static const struct float_abi all_float_abis[] =
507 {"soft", ARM_FLOAT_ABI_SOFT},
508 {"softfp", ARM_FLOAT_ABI_SOFTFP},
509 {"hard", ARM_FLOAT_ABI_HARD}
513 /* Return the number of bits set in VALUE. */
514 static unsigned
515 bit_count (unsigned long value)
517 unsigned long count = 0;
519 while (value)
521 count++;
522 value &= value - 1; /* Clear the least-significant set bit. */
525 return count;
528 /* Fix up any incompatible options that the user has specified.
529 This has now turned into a maze. */
530 void
531 arm_override_options (void)
533 unsigned i;
535 /* Set up the flags based on the cpu/architecture selected by the user. */
536 for (i = ARRAY_SIZE (arm_select); i--;)
538 struct arm_cpu_select * ptr = arm_select + i;
540 if (ptr->string != NULL && ptr->string[0] != '\0')
542 const struct processors * sel;
544 for (sel = ptr->processors; sel->name != NULL; sel++)
545 if (streq (ptr->string, sel->name))
547 /* Determine the processor core for which we should
548 tune code-generation. */
549 if (/* -mcpu= is a sensible default. */
550 i == 0
551 /* If -march= is used, and -mcpu= has not been used,
552 assume that we should tune for a representative
553 CPU from that architecture. */
554 || i == 1
555 /* -mtune= overrides -mcpu= and -march=. */
556 || i == 2)
557 arm_tune = (enum processor_type) (sel - ptr->processors);
559 if (i != 2)
561 /* If we have been given an architecture and a processor
562 make sure that they are compatible. We only generate
563 a warning though, and we prefer the CPU over the
564 architecture. */
565 if (insn_flags != 0 && (insn_flags ^ sel->flags))
566 warning ("switch -mcpu=%s conflicts with -march= switch",
567 ptr->string);
569 insn_flags = sel->flags;
572 break;
575 if (sel->name == NULL)
576 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
580 /* If the user did not specify a processor, choose one for them. */
581 if (insn_flags == 0)
583 const struct processors * sel;
584 unsigned int sought;
585 static const struct cpu_default
587 const int cpu;
588 const char *const name;
590 cpu_defaults[] =
592 { TARGET_CPU_arm2, "arm2" },
593 { TARGET_CPU_arm6, "arm6" },
594 { TARGET_CPU_arm610, "arm610" },
595 { TARGET_CPU_arm710, "arm710" },
596 { TARGET_CPU_arm7m, "arm7m" },
597 { TARGET_CPU_arm7500fe, "arm7500fe" },
598 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
599 { TARGET_CPU_arm8, "arm8" },
600 { TARGET_CPU_arm810, "arm810" },
601 { TARGET_CPU_arm9, "arm9" },
602 { TARGET_CPU_strongarm, "strongarm" },
603 { TARGET_CPU_xscale, "xscale" },
604 { TARGET_CPU_ep9312, "ep9312" },
605 { TARGET_CPU_iwmmxt, "iwmmxt" },
606 { TARGET_CPU_arm926ejs, "arm926ejs" },
607 { TARGET_CPU_arm1026ejs, "arm1026ejs" },
608 { TARGET_CPU_arm1136js, "arm1136js" },
609 { TARGET_CPU_arm1136jfs, "arm1136jfs" },
610 { TARGET_CPU_generic, "arm" },
611 { 0, 0 }
613 const struct cpu_default * def;
615 /* Find the default. */
616 for (def = cpu_defaults; def->name; def++)
617 if (def->cpu == TARGET_CPU_DEFAULT)
618 break;
620 /* Make sure we found the default CPU. */
621 if (def->name == NULL)
622 abort ();
624 /* Find the default CPU's flags. */
625 for (sel = all_cores; sel->name != NULL; sel++)
626 if (streq (def->name, sel->name))
627 break;
629 if (sel->name == NULL)
630 abort ();
632 insn_flags = sel->flags;
634 /* Now check to see if the user has specified some command line
635 switch that require certain abilities from the cpu. */
636 sought = 0;
638 if (TARGET_INTERWORK || TARGET_THUMB)
640 sought |= (FL_THUMB | FL_MODE32);
642 /* Force apcs-32 to be used for interworking. */
643 target_flags |= ARM_FLAG_APCS_32;
645 /* There are no ARM processors that support both APCS-26 and
646 interworking. Therefore we force FL_MODE26 to be removed
647 from insn_flags here (if it was set), so that the search
648 below will always be able to find a compatible processor. */
649 insn_flags &= ~FL_MODE26;
651 else if (!TARGET_APCS_32)
652 sought |= FL_MODE26;
654 if (sought != 0 && ((sought & insn_flags) != sought))
656 /* Try to locate a CPU type that supports all of the abilities
657 of the default CPU, plus the extra abilities requested by
658 the user. */
659 for (sel = all_cores; sel->name != NULL; sel++)
660 if ((sel->flags & sought) == (sought | insn_flags))
661 break;
663 if (sel->name == NULL)
665 unsigned current_bit_count = 0;
666 const struct processors * best_fit = NULL;
668 /* Ideally we would like to issue an error message here
669 saying that it was not possible to find a CPU compatible
670 with the default CPU, but which also supports the command
671 line options specified by the programmer, and so they
672 ought to use the -mcpu=<name> command line option to
673 override the default CPU type.
675 Unfortunately this does not work with multilibing. We
676 need to be able to support multilibs for -mapcs-26 and for
677 -mthumb-interwork and there is no CPU that can support both
678 options. Instead if we cannot find a cpu that has both the
679 characteristics of the default cpu and the given command line
680 options we scan the array again looking for a best match. */
681 for (sel = all_cores; sel->name != NULL; sel++)
682 if ((sel->flags & sought) == sought)
684 unsigned count;
686 count = bit_count (sel->flags & insn_flags);
688 if (count >= current_bit_count)
690 best_fit = sel;
691 current_bit_count = count;
695 if (best_fit == NULL)
696 abort ();
697 else
698 sel = best_fit;
701 insn_flags = sel->flags;
703 if (arm_tune == arm_none)
704 arm_tune = (enum processor_type) (sel - all_cores);
707 /* The processor for which we should tune should now have been
708 chosen. */
709 if (arm_tune == arm_none)
710 abort ();
712 tune_flags = all_cores[(int)arm_tune].flags;
713 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
715 /* Make sure that the processor choice does not conflict with any of the
716 other command line choices. */
717 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
719 /* If APCS-32 was not the default then it must have been set by the
720 user, so issue a warning message. If the user has specified
721 "-mapcs-32 -mcpu=arm2" then we loose here. */
722 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
723 warning ("target CPU does not support APCS-32" );
724 target_flags &= ~ARM_FLAG_APCS_32;
726 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
728 warning ("target CPU does not support APCS-26" );
729 target_flags |= ARM_FLAG_APCS_32;
732 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
734 warning ("target CPU does not support interworking" );
735 target_flags &= ~ARM_FLAG_INTERWORK;
738 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
740 warning ("target CPU does not support THUMB instructions");
741 target_flags &= ~ARM_FLAG_THUMB;
744 if (TARGET_APCS_FRAME && TARGET_THUMB)
746 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
747 target_flags &= ~ARM_FLAG_APCS_FRAME;
750 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
751 from here where no function is being compiled currently. */
752 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
753 && TARGET_ARM)
754 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
756 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
757 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
759 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
760 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
762 /* If interworking is enabled then APCS-32 must be selected as well. */
763 if (TARGET_INTERWORK)
765 if (!TARGET_APCS_32)
766 warning ("interworking forces APCS-32 to be used" );
767 target_flags |= ARM_FLAG_APCS_32;
770 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
772 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
773 target_flags |= ARM_FLAG_APCS_FRAME;
776 if (TARGET_POKE_FUNCTION_NAME)
777 target_flags |= ARM_FLAG_APCS_FRAME;
779 if (TARGET_APCS_REENT && flag_pic)
780 error ("-fpic and -mapcs-reent are incompatible");
782 if (TARGET_APCS_REENT)
783 warning ("APCS reentrant code not supported. Ignored");
785 /* If this target is normally configured to use APCS frames, warn if they
786 are turned off and debugging is turned on. */
787 if (TARGET_ARM
788 && write_symbols != NO_DEBUG
789 && !TARGET_APCS_FRAME
790 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
791 warning ("-g with -mno-apcs-frame may not give sensible debugging");
793 /* If stack checking is disabled, we can use r10 as the PIC register,
794 which keeps r9 available. */
795 if (flag_pic)
796 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
798 if (TARGET_APCS_FLOAT)
799 warning ("passing floating point arguments in fp regs not yet supported");
801 /* Initialize boolean versions of the flags, for use in the arm.md file. */
802 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
803 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
804 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
805 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
806 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
807 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
809 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
810 arm_is_strong = (tune_flags & FL_STRONG) != 0;
811 thumb_code = (TARGET_ARM == 0);
812 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
813 && !(tune_flags & FL_ARCH4))) != 0;
814 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
815 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
817 if (TARGET_IWMMXT && (! TARGET_ATPCS))
818 target_flags |= ARM_FLAG_ATPCS;
820 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
821 if (target_fpu_name == NULL && target_fpe_name != NULL)
823 if (streq (target_fpe_name, "2"))
824 target_fpu_name = "fpe2";
825 else if (streq (target_fpe_name, "3"))
826 target_fpu_name = "fpe3";
827 else
828 error ("invalid floating point emulation option: -mfpe=%s",
829 target_fpe_name);
831 if (target_fpu_name != NULL)
833 /* The user specified a FPU. */
834 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
836 if (streq (all_fpus[i].name, target_fpu_name))
838 arm_fpu_arch = all_fpus[i].fpu;
839 arm_fpu_tune = arm_fpu_arch;
840 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
841 break;
844 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
845 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
847 else
849 #ifdef FPUTYPE_DEFAULT
850 /* Use the default is it is specified for this platform. */
851 arm_fpu_arch = FPUTYPE_DEFAULT;
852 arm_fpu_tune = FPUTYPE_DEFAULT;
853 #else
854 /* Pick one based on CPU type. */
855 if ((insn_flags & FL_VFP) != 0)
856 arm_fpu_arch = FPUTYPE_VFP;
857 else if (insn_flags & FL_CIRRUS)
858 arm_fpu_arch = FPUTYPE_MAVERICK;
859 else
860 arm_fpu_arch = FPUTYPE_FPA_EMU2;
861 #endif
862 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
863 arm_fpu_tune = FPUTYPE_FPA;
864 else
865 arm_fpu_tune = arm_fpu_arch;
866 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
867 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
868 abort ();
871 if (target_float_abi_name != NULL)
873 /* The user specified a FP ABI. */
874 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
876 if (streq (all_float_abis[i].name, target_float_abi_name))
878 arm_float_abi = all_float_abis[i].abi_type;
879 break;
882 if (i == ARRAY_SIZE (all_float_abis))
883 error ("invalid floating point abi: -mfloat-abi=%s",
884 target_float_abi_name);
886 else
888 /* Use soft-float target flag. */
889 if (target_flags & ARM_FLAG_SOFT_FLOAT)
890 arm_float_abi = ARM_FLOAT_ABI_SOFT;
891 else
892 arm_float_abi = ARM_FLOAT_ABI_HARD;
895 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
896 sorry ("-mfloat-abi=softfp");
897 /* If soft-float is specified then don't use FPU. */
898 if (TARGET_SOFT_FLOAT)
899 arm_fpu_arch = FPUTYPE_NONE;
901 /* For arm2/3 there is no need to do any scheduling if there is only
902 a floating point emulator, or we are doing software floating-point. */
903 if ((TARGET_SOFT_FLOAT
904 || arm_fpu_tune == FPUTYPE_FPA_EMU2
905 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
906 && (tune_flags & FL_MODE32) == 0)
907 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
909 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
911 if (structure_size_string != NULL)
913 int size = strtol (structure_size_string, NULL, 0);
915 if (size == 8 || size == 32)
916 arm_structure_size_boundary = size;
917 else
918 warning ("structure size boundary can only be set to 8 or 32");
921 if (arm_pic_register_string != NULL)
923 int pic_register = decode_reg_name (arm_pic_register_string);
925 if (!flag_pic)
926 warning ("-mpic-register= is useless without -fpic");
928 /* Prevent the user from choosing an obviously stupid PIC register. */
929 else if (pic_register < 0 || call_used_regs[pic_register]
930 || pic_register == HARD_FRAME_POINTER_REGNUM
931 || pic_register == STACK_POINTER_REGNUM
932 || pic_register >= PC_REGNUM)
933 error ("unable to use '%s' for PIC register", arm_pic_register_string);
934 else
935 arm_pic_register = pic_register;
938 if (TARGET_THUMB && flag_schedule_insns)
940 /* Don't warn since it's on by default in -O2. */
941 flag_schedule_insns = 0;
944 if (optimize_size)
946 /* There's some dispute as to whether this should be 1 or 2. However,
947 experiments seem to show that in pathological cases a setting of
948 1 degrades less severely than a setting of 2. This could change if
949 other parts of the compiler change their behavior. */
950 arm_constant_limit = 1;
952 /* If optimizing for size, bump the number of instructions that we
953 are prepared to conditionally execute (even on a StrongARM). */
954 max_insns_skipped = 6;
956 else
958 /* For processors with load scheduling, it never costs more than
959 2 cycles to load a constant, and the load scheduler may well
960 reduce that to 1. */
961 if (tune_flags & FL_LDSCHED)
962 arm_constant_limit = 1;
964 /* On XScale the longer latency of a load makes it more difficult
965 to achieve a good schedule, so it's faster to synthesize
966 constants that can be done in two insns. */
967 if (arm_tune_xscale)
968 arm_constant_limit = 2;
970 /* StrongARM has early execution of branches, so a sequence
971 that is worth skipping is shorter. */
972 if (arm_is_strong)
973 max_insns_skipped = 3;
976 /* Register global variables with the garbage collector. */
977 arm_add_gc_roots ();
980 static void
981 arm_add_gc_roots (void)
983 gcc_obstack_init(&minipool_obstack);
984 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
987 /* A table of known ARM exception types.
988 For use with the interrupt function attribute. */
990 typedef struct
992 const char *const arg;
993 const unsigned long return_value;
995 isr_attribute_arg;
997 static const isr_attribute_arg isr_attribute_args [] =
999 { "IRQ", ARM_FT_ISR },
1000 { "irq", ARM_FT_ISR },
1001 { "FIQ", ARM_FT_FIQ },
1002 { "fiq", ARM_FT_FIQ },
1003 { "ABORT", ARM_FT_ISR },
1004 { "abort", ARM_FT_ISR },
1005 { "ABORT", ARM_FT_ISR },
1006 { "abort", ARM_FT_ISR },
1007 { "UNDEF", ARM_FT_EXCEPTION },
1008 { "undef", ARM_FT_EXCEPTION },
1009 { "SWI", ARM_FT_EXCEPTION },
1010 { "swi", ARM_FT_EXCEPTION },
1011 { NULL, ARM_FT_NORMAL }
1014 /* Returns the (interrupt) function type of the current
1015 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1017 static unsigned long
1018 arm_isr_value (tree argument)
1020 const isr_attribute_arg * ptr;
1021 const char * arg;
1023 /* No argument - default to IRQ. */
1024 if (argument == NULL_TREE)
1025 return ARM_FT_ISR;
1027 /* Get the value of the argument. */
1028 if (TREE_VALUE (argument) == NULL_TREE
1029 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1030 return ARM_FT_UNKNOWN;
1032 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1034 /* Check it against the list of known arguments. */
1035 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1036 if (streq (arg, ptr->arg))
1037 return ptr->return_value;
1039 /* An unrecognized interrupt type. */
1040 return ARM_FT_UNKNOWN;
1043 /* Computes the type of the current function. */
1045 static unsigned long
1046 arm_compute_func_type (void)
1048 unsigned long type = ARM_FT_UNKNOWN;
1049 tree a;
1050 tree attr;
1052 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1053 abort ();
1055 /* Decide if the current function is volatile. Such functions
1056 never return, and many memory cycles can be saved by not storing
1057 register values that will never be needed again. This optimization
1058 was added to speed up context switching in a kernel application. */
1059 if (optimize > 0
1060 && current_function_nothrow
1061 && TREE_THIS_VOLATILE (current_function_decl))
1062 type |= ARM_FT_VOLATILE;
1064 if (current_function_needs_context)
1065 type |= ARM_FT_NESTED;
1067 attr = DECL_ATTRIBUTES (current_function_decl);
1069 a = lookup_attribute ("naked", attr);
1070 if (a != NULL_TREE)
1071 type |= ARM_FT_NAKED;
1073 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1074 type |= ARM_FT_EXCEPTION_HANDLER;
1075 else
1077 a = lookup_attribute ("isr", attr);
1078 if (a == NULL_TREE)
1079 a = lookup_attribute ("interrupt", attr);
1081 if (a == NULL_TREE)
1082 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1083 else
1084 type |= arm_isr_value (TREE_VALUE (a));
1087 return type;
1090 /* Returns the type of the current function. */
1092 unsigned long
1093 arm_current_func_type (void)
1095 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1096 cfun->machine->func_type = arm_compute_func_type ();
1098 return cfun->machine->func_type;
1101 /* Return 1 if it is possible to return using a single instruction.
1102 If SIBLING is non-null, this is a test for a return before a sibling
1103 call. SIBLING is the call insn, so we can examine its register usage. */
1106 use_return_insn (int iscond, rtx sibling)
1108 int regno;
1109 unsigned int func_type;
1110 unsigned long saved_int_regs;
1111 unsigned HOST_WIDE_INT stack_adjust;
1113 /* Never use a return instruction before reload has run. */
1114 if (!reload_completed)
1115 return 0;
1117 func_type = arm_current_func_type ();
1119 /* Naked functions and volatile functions need special
1120 consideration. */
1121 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1122 return 0;
1124 /* So do interrupt functions that use the frame pointer. */
1125 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1126 return 0;
1128 stack_adjust = arm_get_frame_size () + current_function_outgoing_args_size;
1130 /* As do variadic functions. */
1131 if (current_function_pretend_args_size
1132 || cfun->machine->uses_anonymous_args
1133 /* Or if the function calls __builtin_eh_return () */
1134 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1135 /* Or if the function calls alloca */
1136 || current_function_calls_alloca
1137 /* Or if there is a stack adjustment. However, if the stack pointer
1138 is saved on the stack, we can use a pre-incrementing stack load. */
1139 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1140 return 0;
1142 saved_int_regs = arm_compute_save_reg_mask ();
1144 /* Unfortunately, the insn
1146 ldmib sp, {..., sp, ...}
1148 triggers a bug on most SA-110 based devices, such that the stack
1149 pointer won't be correctly restored if the instruction takes a
1150 page fault. We work around this problem by popping r3 along with
1151 the other registers, since that is never slower than executing
1152 another instruction.
1154 We test for !arm_arch5 here, because code for any architecture
1155 less than this could potentially be run on one of the buggy
1156 chips. */
1157 if (stack_adjust == 4 && !arm_arch5)
1159 /* Validate that r3 is a call-clobbered register (always true in
1160 the default abi) ... */
1161 if (!call_used_regs[3])
1162 return 0;
1164 /* ... that it isn't being used for a return value (always true
1165 until we implement return-in-regs), or for a tail-call
1166 argument ... */
1167 if (sibling)
1169 if (GET_CODE (sibling) != CALL_INSN)
1170 abort ();
1172 if (find_regno_fusage (sibling, USE, 3))
1173 return 0;
1176 /* ... and that there are no call-saved registers in r0-r2
1177 (always true in the default ABI). */
1178 if (saved_int_regs & 0x7)
1179 return 0;
1182 /* Can't be done if interworking with Thumb, and any registers have been
1183 stacked. */
1184 if (TARGET_INTERWORK && saved_int_regs != 0)
1185 return 0;
1187 /* On StrongARM, conditional returns are expensive if they aren't
1188 taken and multiple registers have been stacked. */
1189 if (iscond && arm_is_strong)
1191 /* Conditional return when just the LR is stored is a simple
1192 conditional-load instruction, that's not expensive. */
1193 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1194 return 0;
1196 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1197 return 0;
1200 /* If there are saved registers but the LR isn't saved, then we need
1201 two instructions for the return. */
1202 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1203 return 0;
1205 /* Can't be done if any of the FPA regs are pushed,
1206 since this also requires an insn. */
1207 if (TARGET_HARD_FLOAT && TARGET_FPA)
1208 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1209 if (regs_ever_live[regno] && !call_used_regs[regno])
1210 return 0;
1212 /* Likewise VFP regs. */
1213 if (TARGET_HARD_FLOAT && TARGET_VFP)
1214 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1215 if (regs_ever_live[regno] && !call_used_regs[regno])
1216 return 0;
1218 if (TARGET_REALLY_IWMMXT)
1219 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1220 if (regs_ever_live[regno] && ! call_used_regs [regno])
1221 return 0;
1223 return 1;
1226 /* Return TRUE if int I is a valid immediate ARM constant. */
1229 const_ok_for_arm (HOST_WIDE_INT i)
1231 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1233 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1234 be all zero, or all one. */
1235 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1236 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1237 != ((~(unsigned HOST_WIDE_INT) 0)
1238 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1239 return FALSE;
1241 /* Fast return for 0 and powers of 2 */
1242 if ((i & (i - 1)) == 0)
1243 return TRUE;
1247 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1248 return TRUE;
1249 mask =
1250 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1251 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1253 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1255 return FALSE;
1258 /* Return true if I is a valid constant for the operation CODE. */
1259 static int
1260 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1262 if (const_ok_for_arm (i))
1263 return 1;
1265 switch (code)
1267 case PLUS:
1268 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1270 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1271 case XOR:
1272 case IOR:
1273 return 0;
1275 case AND:
1276 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1278 default:
1279 abort ();
1283 /* Emit a sequence of insns to handle a large constant.
1284 CODE is the code of the operation required, it can be any of SET, PLUS,
1285 IOR, AND, XOR, MINUS;
1286 MODE is the mode in which the operation is being performed;
1287 VAL is the integer to operate on;
1288 SOURCE is the other operand (a register, or a null-pointer for SET);
1289 SUBTARGETS means it is safe to create scratch registers if that will
1290 either produce a simpler sequence, or we will want to cse the values.
1291 Return value is the number of insns emitted. */
1294 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1295 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1297 if (subtargets || code == SET
1298 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1299 && REGNO (target) != REGNO (source)))
1301 /* After arm_reorg has been called, we can't fix up expensive
1302 constants by pushing them into memory so we must synthesize
1303 them in-line, regardless of the cost. This is only likely to
1304 be more costly on chips that have load delay slots and we are
1305 compiling without running the scheduler (so no splitting
1306 occurred before the final instruction emission).
1308 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1310 if (!after_arm_reorg
1311 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1312 > arm_constant_limit + (code != SET)))
1314 if (code == SET)
1316 /* Currently SET is the only monadic value for CODE, all
1317 the rest are diadic. */
1318 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1319 return 1;
1321 else
1323 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1325 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1326 /* For MINUS, the value is subtracted from, since we never
1327 have subtraction of a constant. */
1328 if (code == MINUS)
1329 emit_insn (gen_rtx_SET (VOIDmode, target,
1330 gen_rtx_MINUS (mode, temp, source)));
1331 else
1332 emit_insn (gen_rtx_SET (VOIDmode, target,
1333 gen_rtx_fmt_ee (code, mode, source, temp)));
1334 return 2;
1339 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1342 static int
1343 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1345 HOST_WIDE_INT temp1;
1346 int num_insns = 0;
1349 int end;
1351 if (i <= 0)
1352 i += 32;
1353 if (remainder & (3 << (i - 2)))
1355 end = i - 8;
1356 if (end < 0)
1357 end += 32;
1358 temp1 = remainder & ((0x0ff << end)
1359 | ((i < end) ? (0xff >> (32 - end)) : 0));
1360 remainder &= ~temp1;
1361 num_insns++;
1362 i -= 6;
1364 i -= 2;
1365 } while (remainder);
1366 return num_insns;
1369 /* As above, but extra parameter GENERATE which, if clear, suppresses
1370 RTL generation. */
1372 static int
1373 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1374 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1375 int generate)
1377 int can_invert = 0;
1378 int can_negate = 0;
1379 int can_negate_initial = 0;
1380 int can_shift = 0;
1381 int i;
1382 int num_bits_set = 0;
1383 int set_sign_bit_copies = 0;
1384 int clear_sign_bit_copies = 0;
1385 int clear_zero_bit_copies = 0;
1386 int set_zero_bit_copies = 0;
1387 int insns = 0;
1388 unsigned HOST_WIDE_INT temp1, temp2;
1389 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1391 /* Find out which operations are safe for a given CODE. Also do a quick
1392 check for degenerate cases; these can occur when DImode operations
1393 are split. */
1394 switch (code)
1396 case SET:
1397 can_invert = 1;
1398 can_shift = 1;
1399 can_negate = 1;
1400 break;
1402 case PLUS:
1403 can_negate = 1;
1404 can_negate_initial = 1;
1405 break;
1407 case IOR:
1408 if (remainder == 0xffffffff)
1410 if (generate)
1411 emit_insn (gen_rtx_SET (VOIDmode, target,
1412 GEN_INT (ARM_SIGN_EXTEND (val))));
1413 return 1;
1415 if (remainder == 0)
1417 if (reload_completed && rtx_equal_p (target, source))
1418 return 0;
1419 if (generate)
1420 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1421 return 1;
1423 break;
1425 case AND:
1426 if (remainder == 0)
1428 if (generate)
1429 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1430 return 1;
1432 if (remainder == 0xffffffff)
1434 if (reload_completed && rtx_equal_p (target, source))
1435 return 0;
1436 if (generate)
1437 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1438 return 1;
1440 can_invert = 1;
1441 break;
1443 case XOR:
1444 if (remainder == 0)
1446 if (reload_completed && rtx_equal_p (target, source))
1447 return 0;
1448 if (generate)
1449 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1450 return 1;
1452 if (remainder == 0xffffffff)
1454 if (generate)
1455 emit_insn (gen_rtx_SET (VOIDmode, target,
1456 gen_rtx_NOT (mode, source)));
1457 return 1;
1460 /* We don't know how to handle this yet below. */
1461 abort ();
1463 case MINUS:
1464 /* We treat MINUS as (val - source), since (source - val) is always
1465 passed as (source + (-val)). */
1466 if (remainder == 0)
1468 if (generate)
1469 emit_insn (gen_rtx_SET (VOIDmode, target,
1470 gen_rtx_NEG (mode, source)));
1471 return 1;
1473 if (const_ok_for_arm (val))
1475 if (generate)
1476 emit_insn (gen_rtx_SET (VOIDmode, target,
1477 gen_rtx_MINUS (mode, GEN_INT (val),
1478 source)));
1479 return 1;
1481 can_negate = 1;
1483 break;
1485 default:
1486 abort ();
1489 /* If we can do it in one insn get out quickly. */
1490 if (const_ok_for_arm (val)
1491 || (can_negate_initial && const_ok_for_arm (-val))
1492 || (can_invert && const_ok_for_arm (~val)))
1494 if (generate)
1495 emit_insn (gen_rtx_SET (VOIDmode, target,
1496 (source ? gen_rtx_fmt_ee (code, mode, source,
1497 GEN_INT (val))
1498 : GEN_INT (val))));
1499 return 1;
1502 /* Calculate a few attributes that may be useful for specific
1503 optimizations. */
1504 for (i = 31; i >= 0; i--)
1506 if ((remainder & (1 << i)) == 0)
1507 clear_sign_bit_copies++;
1508 else
1509 break;
1512 for (i = 31; i >= 0; i--)
1514 if ((remainder & (1 << i)) != 0)
1515 set_sign_bit_copies++;
1516 else
1517 break;
1520 for (i = 0; i <= 31; i++)
1522 if ((remainder & (1 << i)) == 0)
1523 clear_zero_bit_copies++;
1524 else
1525 break;
1528 for (i = 0; i <= 31; i++)
1530 if ((remainder & (1 << i)) != 0)
1531 set_zero_bit_copies++;
1532 else
1533 break;
1536 switch (code)
1538 case SET:
1539 /* See if we can do this by sign_extending a constant that is known
1540 to be negative. This is a good, way of doing it, since the shift
1541 may well merge into a subsequent insn. */
1542 if (set_sign_bit_copies > 1)
1544 if (const_ok_for_arm
1545 (temp1 = ARM_SIGN_EXTEND (remainder
1546 << (set_sign_bit_copies - 1))))
1548 if (generate)
1550 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1551 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1552 GEN_INT (temp1)));
1553 emit_insn (gen_ashrsi3 (target, new_src,
1554 GEN_INT (set_sign_bit_copies - 1)));
1556 return 2;
1558 /* For an inverted constant, we will need to set the low bits,
1559 these will be shifted out of harm's way. */
1560 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1561 if (const_ok_for_arm (~temp1))
1563 if (generate)
1565 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1566 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1567 GEN_INT (temp1)));
1568 emit_insn (gen_ashrsi3 (target, new_src,
1569 GEN_INT (set_sign_bit_copies - 1)));
1571 return 2;
1575 /* See if we can generate this by setting the bottom (or the top)
1576 16 bits, and then shifting these into the other half of the
1577 word. We only look for the simplest cases, to do more would cost
1578 too much. Be careful, however, not to generate this when the
1579 alternative would take fewer insns. */
1580 if (val & 0xffff0000)
1582 temp1 = remainder & 0xffff0000;
1583 temp2 = remainder & 0x0000ffff;
1585 /* Overlaps outside this range are best done using other methods. */
1586 for (i = 9; i < 24; i++)
1588 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1589 && !const_ok_for_arm (temp2))
1591 rtx new_src = (subtargets
1592 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1593 : target);
1594 insns = arm_gen_constant (code, mode, temp2, new_src,
1595 source, subtargets, generate);
1596 source = new_src;
1597 if (generate)
1598 emit_insn (gen_rtx_SET
1599 (VOIDmode, target,
1600 gen_rtx_IOR (mode,
1601 gen_rtx_ASHIFT (mode, source,
1602 GEN_INT (i)),
1603 source)));
1604 return insns + 1;
1608 /* Don't duplicate cases already considered. */
1609 for (i = 17; i < 24; i++)
1611 if (((temp1 | (temp1 >> i)) == remainder)
1612 && !const_ok_for_arm (temp1))
1614 rtx new_src = (subtargets
1615 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1616 : target);
1617 insns = arm_gen_constant (code, mode, temp1, new_src,
1618 source, subtargets, generate);
1619 source = new_src;
1620 if (generate)
1621 emit_insn
1622 (gen_rtx_SET (VOIDmode, target,
1623 gen_rtx_IOR
1624 (mode,
1625 gen_rtx_LSHIFTRT (mode, source,
1626 GEN_INT (i)),
1627 source)));
1628 return insns + 1;
1632 break;
1634 case IOR:
1635 case XOR:
1636 /* If we have IOR or XOR, and the constant can be loaded in a
1637 single instruction, and we can find a temporary to put it in,
1638 then this can be done in two instructions instead of 3-4. */
1639 if (subtargets
1640 /* TARGET can't be NULL if SUBTARGETS is 0 */
1641 || (reload_completed && !reg_mentioned_p (target, source)))
1643 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1645 if (generate)
1647 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1649 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1650 emit_insn (gen_rtx_SET (VOIDmode, target,
1651 gen_rtx_fmt_ee (code, mode, source, sub)));
1653 return 2;
1657 if (code == XOR)
1658 break;
1660 if (set_sign_bit_copies > 8
1661 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1663 if (generate)
1665 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1666 rtx shift = GEN_INT (set_sign_bit_copies);
1668 emit_insn (gen_rtx_SET (VOIDmode, sub,
1669 gen_rtx_NOT (mode,
1670 gen_rtx_ASHIFT (mode,
1671 source,
1672 shift))));
1673 emit_insn (gen_rtx_SET (VOIDmode, target,
1674 gen_rtx_NOT (mode,
1675 gen_rtx_LSHIFTRT (mode, sub,
1676 shift))));
1678 return 2;
1681 if (set_zero_bit_copies > 8
1682 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1684 if (generate)
1686 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1687 rtx shift = GEN_INT (set_zero_bit_copies);
1689 emit_insn (gen_rtx_SET (VOIDmode, sub,
1690 gen_rtx_NOT (mode,
1691 gen_rtx_LSHIFTRT (mode,
1692 source,
1693 shift))));
1694 emit_insn (gen_rtx_SET (VOIDmode, target,
1695 gen_rtx_NOT (mode,
1696 gen_rtx_ASHIFT (mode, sub,
1697 shift))));
1699 return 2;
1702 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1704 if (generate)
1706 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1707 emit_insn (gen_rtx_SET (VOIDmode, sub,
1708 gen_rtx_NOT (mode, source)));
1709 source = sub;
1710 if (subtargets)
1711 sub = gen_reg_rtx (mode);
1712 emit_insn (gen_rtx_SET (VOIDmode, sub,
1713 gen_rtx_AND (mode, source,
1714 GEN_INT (temp1))));
1715 emit_insn (gen_rtx_SET (VOIDmode, target,
1716 gen_rtx_NOT (mode, sub)));
1718 return 3;
1720 break;
1722 case AND:
1723 /* See if two shifts will do 2 or more insn's worth of work. */
1724 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1726 HOST_WIDE_INT shift_mask = ((0xffffffff
1727 << (32 - clear_sign_bit_copies))
1728 & 0xffffffff);
1730 if ((remainder | shift_mask) != 0xffffffff)
1732 if (generate)
1734 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1735 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1736 new_src, source, subtargets, 1);
1737 source = new_src;
1739 else
1741 rtx targ = subtargets ? NULL_RTX : target;
1742 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1743 targ, source, subtargets, 0);
1747 if (generate)
1749 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1750 rtx shift = GEN_INT (clear_sign_bit_copies);
1752 emit_insn (gen_ashlsi3 (new_src, source, shift));
1753 emit_insn (gen_lshrsi3 (target, new_src, shift));
1756 return insns + 2;
1759 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1761 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1763 if ((remainder | shift_mask) != 0xffffffff)
1765 if (generate)
1767 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1769 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1770 new_src, source, subtargets, 1);
1771 source = new_src;
1773 else
1775 rtx targ = subtargets ? NULL_RTX : target;
1777 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1778 targ, source, subtargets, 0);
1782 if (generate)
1784 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1785 rtx shift = GEN_INT (clear_zero_bit_copies);
1787 emit_insn (gen_lshrsi3 (new_src, source, shift));
1788 emit_insn (gen_ashlsi3 (target, new_src, shift));
1791 return insns + 2;
1794 break;
1796 default:
1797 break;
1800 for (i = 0; i < 32; i++)
1801 if (remainder & (1 << i))
1802 num_bits_set++;
1804 if (code == AND || (can_invert && num_bits_set > 16))
1805 remainder = (~remainder) & 0xffffffff;
1806 else if (code == PLUS && num_bits_set > 16)
1807 remainder = (-remainder) & 0xffffffff;
1808 else
1810 can_invert = 0;
1811 can_negate = 0;
1814 /* Now try and find a way of doing the job in either two or three
1815 instructions.
1816 We start by looking for the largest block of zeros that are aligned on
1817 a 2-bit boundary, we then fill up the temps, wrapping around to the
1818 top of the word when we drop off the bottom.
1819 In the worst case this code should produce no more than four insns. */
1821 int best_start = 0;
1822 int best_consecutive_zeros = 0;
1824 for (i = 0; i < 32; i += 2)
1826 int consecutive_zeros = 0;
1828 if (!(remainder & (3 << i)))
1830 while ((i < 32) && !(remainder & (3 << i)))
1832 consecutive_zeros += 2;
1833 i += 2;
1835 if (consecutive_zeros > best_consecutive_zeros)
1837 best_consecutive_zeros = consecutive_zeros;
1838 best_start = i - consecutive_zeros;
1840 i -= 2;
1844 /* So long as it won't require any more insns to do so, it's
1845 desirable to emit a small constant (in bits 0...9) in the last
1846 insn. This way there is more chance that it can be combined with
1847 a later addressing insn to form a pre-indexed load or store
1848 operation. Consider:
1850 *((volatile int *)0xe0000100) = 1;
1851 *((volatile int *)0xe0000110) = 2;
1853 We want this to wind up as:
1855 mov rA, #0xe0000000
1856 mov rB, #1
1857 str rB, [rA, #0x100]
1858 mov rB, #2
1859 str rB, [rA, #0x110]
1861 rather than having to synthesize both large constants from scratch.
1863 Therefore, we calculate how many insns would be required to emit
1864 the constant starting from `best_start', and also starting from
1865 zero (ie with bit 31 first to be output). If `best_start' doesn't
1866 yield a shorter sequence, we may as well use zero. */
1867 if (best_start != 0
1868 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1869 && (count_insns_for_constant (remainder, 0) <=
1870 count_insns_for_constant (remainder, best_start)))
1871 best_start = 0;
1873 /* Now start emitting the insns. */
1874 i = best_start;
1877 int end;
1879 if (i <= 0)
1880 i += 32;
1881 if (remainder & (3 << (i - 2)))
1883 end = i - 8;
1884 if (end < 0)
1885 end += 32;
1886 temp1 = remainder & ((0x0ff << end)
1887 | ((i < end) ? (0xff >> (32 - end)) : 0));
1888 remainder &= ~temp1;
1890 if (generate)
1892 rtx new_src, temp1_rtx;
1894 if (code == SET || code == MINUS)
1896 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1897 if (can_invert && code != MINUS)
1898 temp1 = ~temp1;
1900 else
1902 if (remainder && subtargets)
1903 new_src = gen_reg_rtx (mode);
1904 else
1905 new_src = target;
1906 if (can_invert)
1907 temp1 = ~temp1;
1908 else if (can_negate)
1909 temp1 = -temp1;
1912 temp1 = trunc_int_for_mode (temp1, mode);
1913 temp1_rtx = GEN_INT (temp1);
1915 if (code == SET)
1917 else if (code == MINUS)
1918 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1919 else
1920 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1922 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1923 source = new_src;
1926 if (code == SET)
1928 can_invert = 0;
1929 code = PLUS;
1931 else if (code == MINUS)
1932 code = PLUS;
1934 insns++;
1935 i -= 6;
1937 i -= 2;
1939 while (remainder);
1942 return insns;
1945 /* Canonicalize a comparison so that we are more likely to recognize it.
1946 This can be done for a few constant compares, where we can make the
1947 immediate value easier to load. */
1949 enum rtx_code
1950 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
1952 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1954 switch (code)
1956 case EQ:
1957 case NE:
1958 return code;
1960 case GT:
1961 case LE:
1962 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1963 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1965 *op1 = GEN_INT (i + 1);
1966 return code == GT ? GE : LT;
1968 break;
1970 case GE:
1971 case LT:
1972 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1973 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1975 *op1 = GEN_INT (i - 1);
1976 return code == GE ? GT : LE;
1978 break;
1980 case GTU:
1981 case LEU:
1982 if (i != ~((unsigned HOST_WIDE_INT) 0)
1983 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1985 *op1 = GEN_INT (i + 1);
1986 return code == GTU ? GEU : LTU;
1988 break;
1990 case GEU:
1991 case LTU:
1992 if (i != 0
1993 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1995 *op1 = GEN_INT (i - 1);
1996 return code == GEU ? GTU : LEU;
1998 break;
2000 default:
2001 abort ();
2004 return code;
2007 /* Decide whether a type should be returned in memory (true)
2008 or in a register (false). This is called by the macro
2009 RETURN_IN_MEMORY. */
2011 arm_return_in_memory (tree type)
2013 HOST_WIDE_INT size;
2015 if (!AGGREGATE_TYPE_P (type))
2016 /* All simple types are returned in registers. */
2017 return 0;
2019 size = int_size_in_bytes (type);
2021 if (TARGET_ATPCS)
2023 /* ATPCS returns aggregate types in memory only if they are
2024 larger than a word (or are variable size). */
2025 return (size < 0 || size > UNITS_PER_WORD);
2028 /* For the arm-wince targets we choose to be compatible with Microsoft's
2029 ARM and Thumb compilers, which always return aggregates in memory. */
2030 #ifndef ARM_WINCE
2031 /* All structures/unions bigger than one word are returned in memory.
2032 Also catch the case where int_size_in_bytes returns -1. In this case
2033 the aggregate is either huge or of variable size, and in either case
2034 we will want to return it via memory and not in a register. */
2035 if (size < 0 || size > UNITS_PER_WORD)
2036 return 1;
2038 if (TREE_CODE (type) == RECORD_TYPE)
2040 tree field;
2042 /* For a struct the APCS says that we only return in a register
2043 if the type is 'integer like' and every addressable element
2044 has an offset of zero. For practical purposes this means
2045 that the structure can have at most one non bit-field element
2046 and that this element must be the first one in the structure. */
2048 /* Find the first field, ignoring non FIELD_DECL things which will
2049 have been created by C++. */
2050 for (field = TYPE_FIELDS (type);
2051 field && TREE_CODE (field) != FIELD_DECL;
2052 field = TREE_CHAIN (field))
2053 continue;
2055 if (field == NULL)
2056 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2058 /* Check that the first field is valid for returning in a register. */
2060 /* ... Floats are not allowed */
2061 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2062 return 1;
2064 /* ... Aggregates that are not themselves valid for returning in
2065 a register are not allowed. */
2066 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2067 return 1;
2069 /* Now check the remaining fields, if any. Only bitfields are allowed,
2070 since they are not addressable. */
2071 for (field = TREE_CHAIN (field);
2072 field;
2073 field = TREE_CHAIN (field))
2075 if (TREE_CODE (field) != FIELD_DECL)
2076 continue;
2078 if (!DECL_BIT_FIELD_TYPE (field))
2079 return 1;
2082 return 0;
2085 if (TREE_CODE (type) == UNION_TYPE)
2087 tree field;
2089 /* Unions can be returned in registers if every element is
2090 integral, or can be returned in an integer register. */
2091 for (field = TYPE_FIELDS (type);
2092 field;
2093 field = TREE_CHAIN (field))
2095 if (TREE_CODE (field) != FIELD_DECL)
2096 continue;
2098 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2099 return 1;
2101 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2102 return 1;
2105 return 0;
2107 #endif /* not ARM_WINCE */
2109 /* Return all other types in memory. */
2110 return 1;
2113 /* Indicate whether or not words of a double are in big-endian order. */
2116 arm_float_words_big_endian (void)
2118 if (TARGET_MAVERICK)
2119 return 0;
2121 /* For FPA, float words are always big-endian. For VFP, floats words
2122 follow the memory system mode. */
2124 if (TARGET_FPA)
2126 return 1;
2129 if (TARGET_VFP)
2130 return (TARGET_BIG_END ? 1 : 0);
2132 return 1;
2135 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2136 for a call to a function whose data type is FNTYPE.
2137 For a library call, FNTYPE is NULL. */
2138 void
2139 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2140 rtx libname ATTRIBUTE_UNUSED,
2141 tree fndecl ATTRIBUTE_UNUSED)
2143 /* On the ARM, the offset starts at 0. */
2144 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2145 pcum->iwmmxt_nregs = 0;
2147 pcum->call_cookie = CALL_NORMAL;
2149 if (TARGET_LONG_CALLS)
2150 pcum->call_cookie = CALL_LONG;
2152 /* Check for long call/short call attributes. The attributes
2153 override any command line option. */
2154 if (fntype)
2156 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2157 pcum->call_cookie = CALL_SHORT;
2158 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2159 pcum->call_cookie = CALL_LONG;
2162 /* Varargs vectors are treated the same as long long.
2163 named_count avoids having to change the way arm handles 'named' */
2164 pcum->named_count = 0;
2165 pcum->nargs = 0;
2167 if (TARGET_REALLY_IWMMXT && fntype)
2169 tree fn_arg;
2171 for (fn_arg = TYPE_ARG_TYPES (fntype);
2172 fn_arg;
2173 fn_arg = TREE_CHAIN (fn_arg))
2174 pcum->named_count += 1;
2176 if (! pcum->named_count)
2177 pcum->named_count = INT_MAX;
2181 /* Determine where to put an argument to a function.
2182 Value is zero to push the argument on the stack,
2183 or a hard register in which to store the argument.
2185 MODE is the argument's machine mode.
2186 TYPE is the data type of the argument (as a tree).
2187 This is null for libcalls where that information may
2188 not be available.
2189 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2190 the preceding args and about the function being called.
2191 NAMED is nonzero if this argument is a named parameter
2192 (otherwise it is an extra parameter matching an ellipsis). */
2195 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2196 tree type ATTRIBUTE_UNUSED, int named)
2198 if (TARGET_REALLY_IWMMXT)
2200 if (VECTOR_MODE_SUPPORTED_P (mode))
2202 /* varargs vectors are treated the same as long long.
2203 named_count avoids having to change the way arm handles 'named' */
2204 if (pcum->named_count <= pcum->nargs + 1)
2206 if (pcum->nregs == 1)
2207 pcum->nregs += 1;
2208 if (pcum->nregs <= 2)
2209 return gen_rtx_REG (mode, pcum->nregs);
2210 else
2211 return NULL_RTX;
2213 else if (pcum->iwmmxt_nregs <= 9)
2214 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2215 else
2216 return NULL_RTX;
2218 else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1)
2219 pcum->nregs += 1;
2222 if (mode == VOIDmode)
2223 /* Compute operand 2 of the call insn. */
2224 return GEN_INT (pcum->call_cookie);
2226 if (!named || pcum->nregs >= NUM_ARG_REGS)
2227 return NULL_RTX;
2229 return gen_rtx_REG (mode, pcum->nregs);
2232 /* Variable sized types are passed by reference. This is a GCC
2233 extension to the ARM ABI. */
2236 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2237 enum machine_mode mode ATTRIBUTE_UNUSED,
2238 tree type, int named ATTRIBUTE_UNUSED)
2240 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2243 /* Implement va_arg. */
2246 arm_va_arg (tree valist, tree type)
2248 /* Variable sized types are passed by reference. */
2249 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2251 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2252 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2255 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT)
2257 tree minus_eight;
2258 tree t;
2260 /* Maintain 64-bit alignment of the valist pointer by
2261 constructing: valist = ((valist + (8 - 1)) & -8). */
2262 minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
2263 t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
2264 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2265 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight);
2266 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2267 TREE_SIDE_EFFECTS (t) = 1;
2268 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2270 /* This is to stop the combine pass optimizing
2271 away the alignment adjustment. */
2272 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2275 return std_expand_builtin_va_arg (valist, type);
2278 /* Encode the current state of the #pragma [no_]long_calls. */
2279 typedef enum
2281 OFF, /* No #pramgma [no_]long_calls is in effect. */
2282 LONG, /* #pragma long_calls is in effect. */
2283 SHORT /* #pragma no_long_calls is in effect. */
2284 } arm_pragma_enum;
2286 static arm_pragma_enum arm_pragma_long_calls = OFF;
2288 void
2289 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2291 arm_pragma_long_calls = LONG;
2294 void
2295 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2297 arm_pragma_long_calls = SHORT;
2300 void
2301 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2303 arm_pragma_long_calls = OFF;
2306 /* Table of machine attributes. */
2307 const struct attribute_spec arm_attribute_table[] =
2309 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2310 /* Function calls made to this symbol must be done indirectly, because
2311 it may lie outside of the 26 bit addressing range of a normal function
2312 call. */
2313 { "long_call", 0, 0, false, true, true, NULL },
2314 /* Whereas these functions are always known to reside within the 26 bit
2315 addressing range. */
2316 { "short_call", 0, 0, false, true, true, NULL },
2317 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2318 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2319 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2320 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2321 #ifdef ARM_PE
2322 /* ARM/PE has three new attributes:
2323 interfacearm - ?
2324 dllexport - for exporting a function/variable that will live in a dll
2325 dllimport - for importing a function/variable from a dll
2327 Microsoft allows multiple declspecs in one __declspec, separating
2328 them with spaces. We do NOT support this. Instead, use __declspec
2329 multiple times.
2331 { "dllimport", 0, 0, true, false, false, NULL },
2332 { "dllexport", 0, 0, true, false, false, NULL },
2333 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2334 #endif
2335 { NULL, 0, 0, false, false, false, NULL }
2338 /* Handle an attribute requiring a FUNCTION_DECL;
2339 arguments as in struct attribute_spec.handler. */
2340 static tree
2341 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2342 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2344 if (TREE_CODE (*node) != FUNCTION_DECL)
2346 warning ("`%s' attribute only applies to functions",
2347 IDENTIFIER_POINTER (name));
2348 *no_add_attrs = true;
2351 return NULL_TREE;
2354 /* Handle an "interrupt" or "isr" attribute;
2355 arguments as in struct attribute_spec.handler. */
2356 static tree
2357 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2358 bool *no_add_attrs)
2360 if (DECL_P (*node))
2362 if (TREE_CODE (*node) != FUNCTION_DECL)
2364 warning ("`%s' attribute only applies to functions",
2365 IDENTIFIER_POINTER (name));
2366 *no_add_attrs = true;
2368 /* FIXME: the argument if any is checked for type attributes;
2369 should it be checked for decl ones? */
2371 else
2373 if (TREE_CODE (*node) == FUNCTION_TYPE
2374 || TREE_CODE (*node) == METHOD_TYPE)
2376 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2378 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2379 *no_add_attrs = true;
2382 else if (TREE_CODE (*node) == POINTER_TYPE
2383 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2384 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2385 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2387 *node = build_type_copy (*node);
2388 TREE_TYPE (*node) = build_type_attribute_variant
2389 (TREE_TYPE (*node),
2390 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2391 *no_add_attrs = true;
2393 else
2395 /* Possibly pass this attribute on from the type to a decl. */
2396 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2397 | (int) ATTR_FLAG_FUNCTION_NEXT
2398 | (int) ATTR_FLAG_ARRAY_NEXT))
2400 *no_add_attrs = true;
2401 return tree_cons (name, args, NULL_TREE);
2403 else
2405 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2410 return NULL_TREE;
2413 /* Return 0 if the attributes for two types are incompatible, 1 if they
2414 are compatible, and 2 if they are nearly compatible (which causes a
2415 warning to be generated). */
2416 static int
2417 arm_comp_type_attributes (tree type1, tree type2)
2419 int l1, l2, s1, s2;
2421 /* Check for mismatch of non-default calling convention. */
2422 if (TREE_CODE (type1) != FUNCTION_TYPE)
2423 return 1;
2425 /* Check for mismatched call attributes. */
2426 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2427 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2428 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2429 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2431 /* Only bother to check if an attribute is defined. */
2432 if (l1 | l2 | s1 | s2)
2434 /* If one type has an attribute, the other must have the same attribute. */
2435 if ((l1 != l2) || (s1 != s2))
2436 return 0;
2438 /* Disallow mixed attributes. */
2439 if ((l1 & s2) || (l2 & s1))
2440 return 0;
2443 /* Check for mismatched ISR attribute. */
2444 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2445 if (! l1)
2446 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2447 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2448 if (! l2)
2449 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2450 if (l1 != l2)
2451 return 0;
2453 return 1;
2456 /* Encode long_call or short_call attribute by prefixing
2457 symbol name in DECL with a special character FLAG. */
2458 void
2459 arm_encode_call_attribute (tree decl, int flag)
2461 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2462 int len = strlen (str);
2463 char * newstr;
2465 /* Do not allow weak functions to be treated as short call. */
2466 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2467 return;
2469 newstr = alloca (len + 2);
2470 newstr[0] = flag;
2471 strcpy (newstr + 1, str);
2473 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2474 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2477 /* Assigns default attributes to newly defined type. This is used to
2478 set short_call/long_call attributes for function types of
2479 functions defined inside corresponding #pragma scopes. */
2480 static void
2481 arm_set_default_type_attributes (tree type)
2483 /* Add __attribute__ ((long_call)) to all functions, when
2484 inside #pragma long_calls or __attribute__ ((short_call)),
2485 when inside #pragma no_long_calls. */
2486 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2488 tree type_attr_list, attr_name;
2489 type_attr_list = TYPE_ATTRIBUTES (type);
2491 if (arm_pragma_long_calls == LONG)
2492 attr_name = get_identifier ("long_call");
2493 else if (arm_pragma_long_calls == SHORT)
2494 attr_name = get_identifier ("short_call");
2495 else
2496 return;
2498 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2499 TYPE_ATTRIBUTES (type) = type_attr_list;
2503 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2504 defined within the current compilation unit. If this cannot be
2505 determined, then 0 is returned. */
2506 static int
2507 current_file_function_operand (rtx sym_ref)
2509 /* This is a bit of a fib. A function will have a short call flag
2510 applied to its name if it has the short call attribute, or it has
2511 already been defined within the current compilation unit. */
2512 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2513 return 1;
2515 /* The current function is always defined within the current compilation
2516 unit. if it s a weak definition however, then this may not be the real
2517 definition of the function, and so we have to say no. */
2518 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2519 && !DECL_WEAK (current_function_decl))
2520 return 1;
2522 /* We cannot make the determination - default to returning 0. */
2523 return 0;
2526 /* Return nonzero if a 32 bit "long_call" should be generated for
2527 this call. We generate a long_call if the function:
2529 a. has an __attribute__((long call))
2530 or b. is within the scope of a #pragma long_calls
2531 or c. the -mlong-calls command line switch has been specified
2533 However we do not generate a long call if the function:
2535 d. has an __attribute__ ((short_call))
2536 or e. is inside the scope of a #pragma no_long_calls
2537 or f. has an __attribute__ ((section))
2538 or g. is defined within the current compilation unit.
2540 This function will be called by C fragments contained in the machine
2541 description file. CALL_REF and CALL_COOKIE correspond to the matched
2542 rtl operands. CALL_SYMBOL is used to distinguish between
2543 two different callers of the function. It is set to 1 in the
2544 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2545 and "call_value" patterns. This is because of the difference in the
2546 SYM_REFs passed by these patterns. */
2548 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2550 if (!call_symbol)
2552 if (GET_CODE (sym_ref) != MEM)
2553 return 0;
2555 sym_ref = XEXP (sym_ref, 0);
2558 if (GET_CODE (sym_ref) != SYMBOL_REF)
2559 return 0;
2561 if (call_cookie & CALL_SHORT)
2562 return 0;
2564 if (TARGET_LONG_CALLS && flag_function_sections)
2565 return 1;
2567 if (current_file_function_operand (sym_ref))
2568 return 0;
2570 return (call_cookie & CALL_LONG)
2571 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2572 || TARGET_LONG_CALLS;
2575 /* Return nonzero if it is ok to make a tail-call to DECL. */
2576 static bool
2577 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2579 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2581 if (cfun->machine->sibcall_blocked)
2582 return false;
2584 /* Never tailcall something for which we have no decl, or if we
2585 are in Thumb mode. */
2586 if (decl == NULL || TARGET_THUMB)
2587 return false;
2589 /* Get the calling method. */
2590 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2591 call_type = CALL_SHORT;
2592 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2593 call_type = CALL_LONG;
2595 /* Cannot tail-call to long calls, since these are out of range of
2596 a branch instruction. However, if not compiling PIC, we know
2597 we can reach the symbol if it is in this compilation unit. */
2598 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2599 return false;
2601 /* If we are interworking and the function is not declared static
2602 then we can't tail-call it unless we know that it exists in this
2603 compilation unit (since it might be a Thumb routine). */
2604 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2605 return false;
2607 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2608 if (IS_INTERRUPT (arm_current_func_type ()))
2609 return false;
2611 /* Everything else is ok. */
2612 return true;
2616 /* Addressing mode support functions. */
2618 /* Return nonzero if X is a legitimate immediate operand when compiling
2619 for PIC. */
2621 legitimate_pic_operand_p (rtx x)
2623 if (CONSTANT_P (x)
2624 && flag_pic
2625 && (GET_CODE (x) == SYMBOL_REF
2626 || (GET_CODE (x) == CONST
2627 && GET_CODE (XEXP (x, 0)) == PLUS
2628 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2629 return 0;
2631 return 1;
2635 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2637 if (GET_CODE (orig) == SYMBOL_REF
2638 || GET_CODE (orig) == LABEL_REF)
2640 #ifndef AOF_ASSEMBLER
2641 rtx pic_ref, address;
2642 #endif
2643 rtx insn;
2644 int subregs = 0;
2646 if (reg == 0)
2648 if (no_new_pseudos)
2649 abort ();
2650 else
2651 reg = gen_reg_rtx (Pmode);
2653 subregs = 1;
2656 #ifdef AOF_ASSEMBLER
2657 /* The AOF assembler can generate relocations for these directly, and
2658 understands that the PIC register has to be added into the offset. */
2659 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2660 #else
2661 if (subregs)
2662 address = gen_reg_rtx (Pmode);
2663 else
2664 address = reg;
2666 if (TARGET_ARM)
2667 emit_insn (gen_pic_load_addr_arm (address, orig));
2668 else
2669 emit_insn (gen_pic_load_addr_thumb (address, orig));
2671 if ((GET_CODE (orig) == LABEL_REF
2672 || (GET_CODE (orig) == SYMBOL_REF &&
2673 SYMBOL_REF_LOCAL_P (orig)))
2674 && NEED_GOT_RELOC)
2675 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2676 else
2678 pic_ref = gen_rtx_MEM (Pmode,
2679 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2680 address));
2681 RTX_UNCHANGING_P (pic_ref) = 1;
2684 insn = emit_move_insn (reg, pic_ref);
2685 #endif
2686 current_function_uses_pic_offset_table = 1;
2687 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2688 by loop. */
2689 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2690 REG_NOTES (insn));
2691 return reg;
2693 else if (GET_CODE (orig) == CONST)
2695 rtx base, offset;
2697 if (GET_CODE (XEXP (orig, 0)) == PLUS
2698 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2699 return orig;
2701 if (reg == 0)
2703 if (no_new_pseudos)
2704 abort ();
2705 else
2706 reg = gen_reg_rtx (Pmode);
2709 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2711 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2712 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2713 base == reg ? 0 : reg);
2715 else
2716 abort ();
2718 if (GET_CODE (offset) == CONST_INT)
2720 /* The base register doesn't really matter, we only want to
2721 test the index for the appropriate mode. */
2722 if (!arm_legitimate_index_p (mode, offset, 0))
2724 if (!no_new_pseudos)
2725 offset = force_reg (Pmode, offset);
2726 else
2727 abort ();
2730 if (GET_CODE (offset) == CONST_INT)
2731 return plus_constant (base, INTVAL (offset));
2734 if (GET_MODE_SIZE (mode) > 4
2735 && (GET_MODE_CLASS (mode) == MODE_INT
2736 || TARGET_SOFT_FLOAT))
2738 emit_insn (gen_addsi3 (reg, base, offset));
2739 return reg;
2742 return gen_rtx_PLUS (Pmode, base, offset);
2745 return orig;
2748 /* Generate code to load the PIC register. PROLOGUE is true if
2749 called from arm_expand_prologue (in which case we want the
2750 generated insns at the start of the function); false if called
2751 by an exception receiver that needs the PIC register reloaded
2752 (in which case the insns are just dumped at the current location). */
2753 void
2754 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2756 #ifndef AOF_ASSEMBLER
2757 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2758 rtx global_offset_table;
2760 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2761 return;
2763 if (!flag_pic)
2764 abort ();
2766 start_sequence ();
2767 l1 = gen_label_rtx ();
2769 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2770 /* On the ARM the PC register contains 'dot + 8' at the time of the
2771 addition, on the Thumb it is 'dot + 4'. */
2772 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2773 if (GOT_PCREL)
2774 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2775 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2776 else
2777 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2779 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2781 if (TARGET_ARM)
2783 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2784 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2786 else
2788 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2789 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2792 seq = get_insns ();
2793 end_sequence ();
2794 if (prologue)
2795 emit_insn_after (seq, get_insns ());
2796 else
2797 emit_insn (seq);
2799 /* Need to emit this whether or not we obey regdecls,
2800 since setjmp/longjmp can cause life info to screw up. */
2801 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2802 #endif /* AOF_ASSEMBLER */
2805 /* Return nonzero if X is valid as an ARM state addressing register. */
2806 static int
2807 arm_address_register_rtx_p (rtx x, int strict_p)
2809 int regno;
2811 if (GET_CODE (x) != REG)
2812 return 0;
2814 regno = REGNO (x);
2816 if (strict_p)
2817 return ARM_REGNO_OK_FOR_BASE_P (regno);
2819 return (regno <= LAST_ARM_REGNUM
2820 || regno >= FIRST_PSEUDO_REGISTER
2821 || regno == FRAME_POINTER_REGNUM
2822 || regno == ARG_POINTER_REGNUM);
2825 /* Return nonzero if X is a valid ARM state address operand. */
2827 arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2829 if (arm_address_register_rtx_p (x, strict_p))
2830 return 1;
2832 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2833 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2835 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2836 && GET_MODE_SIZE (mode) <= 4
2837 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2838 && GET_CODE (XEXP (x, 1)) == PLUS
2839 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2840 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2842 /* After reload constants split into minipools will have addresses
2843 from a LABEL_REF. */
2844 else if (reload_completed
2845 && (GET_CODE (x) == LABEL_REF
2846 || (GET_CODE (x) == CONST
2847 && GET_CODE (XEXP (x, 0)) == PLUS
2848 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2849 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2850 return 1;
2852 else if (mode == TImode)
2853 return 0;
2855 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2857 if (GET_CODE (x) == PLUS
2858 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2859 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2861 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2863 if (val == 4 || val == -4 || val == -8)
2864 return 1;
2868 else if (TARGET_HARD_FLOAT && TARGET_VFP && mode == DFmode)
2870 if (GET_CODE (x) == PLUS
2871 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2872 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2874 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2876 /* ??? valid arm offsets are a subset of VFP offsets.
2877 For now only allow this subset. Proper fix is to add an
2878 additional memory constraint for arm address modes.
2879 Alternatively allow full vfp addressing and let
2880 output_move_double fix it up with a sub-optimal sequence. */
2881 if (val == 4 || val == -4 || val == -8)
2882 return 1;
2886 else if (GET_CODE (x) == PLUS)
2888 rtx xop0 = XEXP (x, 0);
2889 rtx xop1 = XEXP (x, 1);
2891 return ((arm_address_register_rtx_p (xop0, strict_p)
2892 && arm_legitimate_index_p (mode, xop1, strict_p))
2893 || (arm_address_register_rtx_p (xop1, strict_p)
2894 && arm_legitimate_index_p (mode, xop0, strict_p)));
2897 #if 0
2898 /* Reload currently can't handle MINUS, so disable this for now */
2899 else if (GET_CODE (x) == MINUS)
2901 rtx xop0 = XEXP (x, 0);
2902 rtx xop1 = XEXP (x, 1);
2904 return (arm_address_register_rtx_p (xop0, strict_p)
2905 && arm_legitimate_index_p (mode, xop1, strict_p));
2907 #endif
2909 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2910 && GET_CODE (x) == SYMBOL_REF
2911 && CONSTANT_POOL_ADDRESS_P (x)
2912 && ! (flag_pic
2913 && symbol_mentioned_p (get_pool_constant (x))))
2914 return 1;
2916 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2917 && (GET_MODE_SIZE (mode) <= 4)
2918 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2919 return 1;
2921 return 0;
2924 /* Return nonzero if INDEX is valid for an address index operand in
2925 ARM state. */
2926 static int
2927 arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
2929 HOST_WIDE_INT range;
2930 enum rtx_code code = GET_CODE (index);
2932 if (TARGET_HARD_FLOAT && TARGET_FPA && GET_MODE_CLASS (mode) == MODE_FLOAT)
2933 return (code == CONST_INT && INTVAL (index) < 1024
2934 && INTVAL (index) > -1024
2935 && (INTVAL (index) & 3) == 0);
2937 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
2938 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2939 return (code == CONST_INT
2940 && INTVAL (index) < 255
2941 && INTVAL (index) > -255);
2943 if (arm_address_register_rtx_p (index, strict_p)
2944 && GET_MODE_SIZE (mode) <= 4)
2945 return 1;
2947 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
2948 return (code == CONST_INT
2949 && INTVAL (index) < 256
2950 && INTVAL (index) > -256);
2952 /* XXX What about ldrsb? */
2953 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2954 && (!arm_arch4 || (mode) != HImode))
2956 rtx xiop0 = XEXP (index, 0);
2957 rtx xiop1 = XEXP (index, 1);
2959 return ((arm_address_register_rtx_p (xiop0, strict_p)
2960 && power_of_two_operand (xiop1, SImode))
2961 || (arm_address_register_rtx_p (xiop1, strict_p)
2962 && power_of_two_operand (xiop0, SImode)));
2965 if (GET_MODE_SIZE (mode) <= 4
2966 && (code == LSHIFTRT || code == ASHIFTRT
2967 || code == ASHIFT || code == ROTATERT)
2968 && (!arm_arch4 || (mode) != HImode))
2970 rtx op = XEXP (index, 1);
2972 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2973 && GET_CODE (op) == CONST_INT
2974 && INTVAL (op) > 0
2975 && INTVAL (op) <= 31);
2978 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2979 load, but that has a restricted addressing range and we are unable
2980 to tell here whether that is the case. To be safe we restrict all
2981 loads to that range. */
2982 if (arm_arch4)
2983 range = (mode == HImode || mode == QImode) ? 256 : 4096;
2984 else
2985 range = (mode == HImode) ? 4095 : 4096;
2987 return (code == CONST_INT
2988 && INTVAL (index) < range
2989 && INTVAL (index) > -range);
2992 /* Return nonzero if X is valid as a Thumb state base register. */
2993 static int
2994 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
2996 int regno;
2998 if (GET_CODE (x) != REG)
2999 return 0;
3001 regno = REGNO (x);
3003 if (strict_p)
3004 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3006 return (regno <= LAST_LO_REGNUM
3007 || regno > LAST_VIRTUAL_REGISTER
3008 || regno == FRAME_POINTER_REGNUM
3009 || (GET_MODE_SIZE (mode) >= 4
3010 && (regno == STACK_POINTER_REGNUM
3011 || regno >= FIRST_PSEUDO_REGISTER
3012 || x == hard_frame_pointer_rtx
3013 || x == arg_pointer_rtx)));
3016 /* Return nonzero if x is a legitimate index register. This is the case
3017 for any base register that can access a QImode object. */
3018 inline static int
3019 thumb_index_register_rtx_p (rtx x, int strict_p)
3021 return thumb_base_register_rtx_p (x, QImode, strict_p);
3024 /* Return nonzero if x is a legitimate Thumb-state address.
3026 The AP may be eliminated to either the SP or the FP, so we use the
3027 least common denominator, e.g. SImode, and offsets from 0 to 64.
3029 ??? Verify whether the above is the right approach.
3031 ??? Also, the FP may be eliminated to the SP, so perhaps that
3032 needs special handling also.
3034 ??? Look at how the mips16 port solves this problem. It probably uses
3035 better ways to solve some of these problems.
3037 Although it is not incorrect, we don't accept QImode and HImode
3038 addresses based on the frame pointer or arg pointer until the
3039 reload pass starts. This is so that eliminating such addresses
3040 into stack based ones won't produce impossible code. */
3042 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3044 /* ??? Not clear if this is right. Experiment. */
3045 if (GET_MODE_SIZE (mode) < 4
3046 && !(reload_in_progress || reload_completed)
3047 && (reg_mentioned_p (frame_pointer_rtx, x)
3048 || reg_mentioned_p (arg_pointer_rtx, x)
3049 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3050 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3051 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3052 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3053 return 0;
3055 /* Accept any base register. SP only in SImode or larger. */
3056 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3057 return 1;
3059 /* This is PC relative data before arm_reorg runs. */
3060 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3061 && GET_CODE (x) == SYMBOL_REF
3062 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3063 return 1;
3065 /* This is PC relative data after arm_reorg runs. */
3066 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3067 && (GET_CODE (x) == LABEL_REF
3068 || (GET_CODE (x) == CONST
3069 && GET_CODE (XEXP (x, 0)) == PLUS
3070 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3071 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3072 return 1;
3074 /* Post-inc indexing only supported for SImode and larger. */
3075 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3076 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3077 return 1;
3079 else if (GET_CODE (x) == PLUS)
3081 /* REG+REG address can be any two index registers. */
3082 /* We disallow FRAME+REG addressing since we know that FRAME
3083 will be replaced with STACK, and SP relative addressing only
3084 permits SP+OFFSET. */
3085 if (GET_MODE_SIZE (mode) <= 4
3086 && XEXP (x, 0) != frame_pointer_rtx
3087 && XEXP (x, 1) != frame_pointer_rtx
3088 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3089 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3090 return 1;
3092 /* REG+const has 5-7 bit offset for non-SP registers. */
3093 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3094 || XEXP (x, 0) == arg_pointer_rtx)
3095 && GET_CODE (XEXP (x, 1)) == CONST_INT
3096 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3097 return 1;
3099 /* REG+const has 10 bit offset for SP, but only SImode and
3100 larger is supported. */
3101 /* ??? Should probably check for DI/DFmode overflow here
3102 just like GO_IF_LEGITIMATE_OFFSET does. */
3103 else if (GET_CODE (XEXP (x, 0)) == REG
3104 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3105 && GET_MODE_SIZE (mode) >= 4
3106 && GET_CODE (XEXP (x, 1)) == CONST_INT
3107 && INTVAL (XEXP (x, 1)) >= 0
3108 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3109 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3110 return 1;
3112 else if (GET_CODE (XEXP (x, 0)) == REG
3113 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3114 && GET_MODE_SIZE (mode) >= 4
3115 && GET_CODE (XEXP (x, 1)) == CONST_INT
3116 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3117 return 1;
3120 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3121 && GET_MODE_SIZE (mode) == 4
3122 && GET_CODE (x) == SYMBOL_REF
3123 && CONSTANT_POOL_ADDRESS_P (x)
3124 && !(flag_pic
3125 && symbol_mentioned_p (get_pool_constant (x))))
3126 return 1;
3128 return 0;
3131 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3132 instruction of mode MODE. */
3134 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3136 switch (GET_MODE_SIZE (mode))
3138 case 1:
3139 return val >= 0 && val < 32;
3141 case 2:
3142 return val >= 0 && val < 64 && (val & 1) == 0;
3144 default:
3145 return (val >= 0
3146 && (val + GET_MODE_SIZE (mode)) <= 128
3147 && (val & 3) == 0);
3151 /* Try machine-dependent ways of modifying an illegitimate address
3152 to be legitimate. If we find one, return the new, valid address. */
3154 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3156 if (GET_CODE (x) == PLUS)
3158 rtx xop0 = XEXP (x, 0);
3159 rtx xop1 = XEXP (x, 1);
3161 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3162 xop0 = force_reg (SImode, xop0);
3164 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3165 xop1 = force_reg (SImode, xop1);
3167 if (ARM_BASE_REGISTER_RTX_P (xop0)
3168 && GET_CODE (xop1) == CONST_INT)
3170 HOST_WIDE_INT n, low_n;
3171 rtx base_reg, val;
3172 n = INTVAL (xop1);
3174 /* VFP addressing modes actually allow greater offsets, but for
3175 now we just stick with the lowest common denominator. */
3176 if (mode == DImode
3177 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3179 low_n = n & 0x0f;
3180 n &= ~0x0f;
3181 if (low_n > 4)
3183 n += 16;
3184 low_n -= 16;
3187 else
3189 low_n = ((mode) == TImode ? 0
3190 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3191 n -= low_n;
3194 base_reg = gen_reg_rtx (SImode);
3195 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3196 GEN_INT (n)), NULL_RTX);
3197 emit_move_insn (base_reg, val);
3198 x = (low_n == 0 ? base_reg
3199 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3201 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3202 x = gen_rtx_PLUS (SImode, xop0, xop1);
3205 /* XXX We don't allow MINUS any more -- see comment in
3206 arm_legitimate_address_p (). */
3207 else if (GET_CODE (x) == MINUS)
3209 rtx xop0 = XEXP (x, 0);
3210 rtx xop1 = XEXP (x, 1);
3212 if (CONSTANT_P (xop0))
3213 xop0 = force_reg (SImode, xop0);
3215 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3216 xop1 = force_reg (SImode, xop1);
3218 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3219 x = gen_rtx_MINUS (SImode, xop0, xop1);
3222 if (flag_pic)
3224 /* We need to find and carefully transform any SYMBOL and LABEL
3225 references; so go back to the original address expression. */
3226 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3228 if (new_x != orig_x)
3229 x = new_x;
3232 return x;
3237 #define REG_OR_SUBREG_REG(X) \
3238 (GET_CODE (X) == REG \
3239 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3241 #define REG_OR_SUBREG_RTX(X) \
3242 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3244 #ifndef COSTS_N_INSNS
3245 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3246 #endif
3247 static inline int
3248 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3250 enum machine_mode mode = GET_MODE (x);
3252 switch (code)
3254 case ASHIFT:
3255 case ASHIFTRT:
3256 case LSHIFTRT:
3257 case ROTATERT:
3258 case PLUS:
3259 case MINUS:
3260 case COMPARE:
3261 case NEG:
3262 case NOT:
3263 return COSTS_N_INSNS (1);
3265 case MULT:
3266 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3268 int cycles = 0;
3269 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3271 while (i)
3273 i >>= 2;
3274 cycles++;
3276 return COSTS_N_INSNS (2) + cycles;
3278 return COSTS_N_INSNS (1) + 16;
3280 case SET:
3281 return (COSTS_N_INSNS (1)
3282 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3283 + GET_CODE (SET_DEST (x)) == MEM));
3285 case CONST_INT:
3286 if (outer == SET)
3288 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3289 return 0;
3290 if (thumb_shiftable_const (INTVAL (x)))
3291 return COSTS_N_INSNS (2);
3292 return COSTS_N_INSNS (3);
3294 else if ((outer == PLUS || outer == COMPARE)
3295 && INTVAL (x) < 256 && INTVAL (x) > -256)
3296 return 0;
3297 else if (outer == AND
3298 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3299 return COSTS_N_INSNS (1);
3300 else if (outer == ASHIFT || outer == ASHIFTRT
3301 || outer == LSHIFTRT)
3302 return 0;
3303 return COSTS_N_INSNS (2);
3305 case CONST:
3306 case CONST_DOUBLE:
3307 case LABEL_REF:
3308 case SYMBOL_REF:
3309 return COSTS_N_INSNS (3);
3311 case UDIV:
3312 case UMOD:
3313 case DIV:
3314 case MOD:
3315 return 100;
3317 case TRUNCATE:
3318 return 99;
3320 case AND:
3321 case XOR:
3322 case IOR:
3323 /* XXX guess. */
3324 return 8;
3326 case ADDRESSOF:
3327 case MEM:
3328 /* XXX another guess. */
3329 /* Memory costs quite a lot for the first word, but subsequent words
3330 load at the equivalent of a single insn each. */
3331 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3332 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3333 ? 4 : 0));
3335 case IF_THEN_ELSE:
3336 /* XXX a guess. */
3337 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3338 return 14;
3339 return 2;
3341 case ZERO_EXTEND:
3342 /* XXX still guessing. */
3343 switch (GET_MODE (XEXP (x, 0)))
3345 case QImode:
3346 return (1 + (mode == DImode ? 4 : 0)
3347 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3349 case HImode:
3350 return (4 + (mode == DImode ? 4 : 0)
3351 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3353 case SImode:
3354 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3356 default:
3357 return 99;
3360 default:
3361 return 99;
3366 /* Worker routine for arm_rtx_costs. */
3367 static inline int
3368 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3370 enum machine_mode mode = GET_MODE (x);
3371 enum rtx_code subcode;
3372 int extra_cost;
3374 switch (code)
3376 case MEM:
3377 /* Memory costs quite a lot for the first word, but subsequent words
3378 load at the equivalent of a single insn each. */
3379 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3380 + (GET_CODE (x) == SYMBOL_REF
3381 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3383 case DIV:
3384 case MOD:
3385 case UDIV:
3386 case UMOD:
3387 return optimize_size ? COSTS_N_INSNS (2) : 100;
3389 case ROTATE:
3390 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3391 return 4;
3392 /* Fall through */
3393 case ROTATERT:
3394 if (mode != SImode)
3395 return 8;
3396 /* Fall through */
3397 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3398 if (mode == DImode)
3399 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3400 + ((GET_CODE (XEXP (x, 0)) == REG
3401 || (GET_CODE (XEXP (x, 0)) == SUBREG
3402 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3403 ? 0 : 8));
3404 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3405 || (GET_CODE (XEXP (x, 0)) == SUBREG
3406 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3407 ? 0 : 4)
3408 + ((GET_CODE (XEXP (x, 1)) == REG
3409 || (GET_CODE (XEXP (x, 1)) == SUBREG
3410 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3411 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3412 ? 0 : 4));
3414 case MINUS:
3415 if (mode == DImode)
3416 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3417 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3418 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3419 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3420 ? 0 : 8));
3422 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3423 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3424 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3425 && arm_const_double_rtx (XEXP (x, 1))))
3426 ? 0 : 8)
3427 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3428 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3429 && arm_const_double_rtx (XEXP (x, 0))))
3430 ? 0 : 8));
3432 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3433 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3434 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3435 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3436 || subcode == ASHIFTRT || subcode == LSHIFTRT
3437 || subcode == ROTATE || subcode == ROTATERT
3438 || (subcode == MULT
3439 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3440 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3441 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3442 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3443 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3444 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3445 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3446 return 1;
3447 /* Fall through */
3449 case PLUS:
3450 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3451 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3452 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3453 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3454 && arm_const_double_rtx (XEXP (x, 1))))
3455 ? 0 : 8));
3457 /* Fall through */
3458 case AND: case XOR: case IOR:
3459 extra_cost = 0;
3461 /* Normally the frame registers will be spilt into reg+const during
3462 reload, so it is a bad idea to combine them with other instructions,
3463 since then they might not be moved outside of loops. As a compromise
3464 we allow integration with ops that have a constant as their second
3465 operand. */
3466 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3467 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3468 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3469 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3470 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3471 extra_cost = 4;
3473 if (mode == DImode)
3474 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3475 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3476 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3477 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3478 ? 0 : 8));
3480 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3481 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3482 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3483 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3484 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3485 ? 0 : 4));
3487 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3488 return (1 + extra_cost
3489 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3490 || subcode == LSHIFTRT || subcode == ASHIFTRT
3491 || subcode == ROTATE || subcode == ROTATERT
3492 || (subcode == MULT
3493 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3494 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3495 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3496 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3497 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3498 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3499 ? 0 : 4));
3501 return 8;
3503 case MULT:
3504 /* This should have been handled by the CPU specific routines. */
3505 abort ();
3507 case TRUNCATE:
3508 if (arm_arch3m && mode == SImode
3509 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3510 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3511 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3512 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3513 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3514 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3515 return 8;
3516 return 99;
3518 case NEG:
3519 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3520 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3521 /* Fall through */
3522 case NOT:
3523 if (mode == DImode)
3524 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3526 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3528 case IF_THEN_ELSE:
3529 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3530 return 14;
3531 return 2;
3533 case COMPARE:
3534 return 1;
3536 case ABS:
3537 return 4 + (mode == DImode ? 4 : 0);
3539 case SIGN_EXTEND:
3540 if (GET_MODE (XEXP (x, 0)) == QImode)
3541 return (4 + (mode == DImode ? 4 : 0)
3542 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3543 /* Fall through */
3544 case ZERO_EXTEND:
3545 switch (GET_MODE (XEXP (x, 0)))
3547 case QImode:
3548 return (1 + (mode == DImode ? 4 : 0)
3549 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3551 case HImode:
3552 return (4 + (mode == DImode ? 4 : 0)
3553 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3555 case SImode:
3556 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3558 case V8QImode:
3559 case V4HImode:
3560 case V2SImode:
3561 case V4QImode:
3562 case V2HImode:
3563 return 1;
3565 default:
3566 break;
3568 abort ();
3570 case CONST_INT:
3571 if (const_ok_for_arm (INTVAL (x)))
3572 return outer == SET ? 2 : -1;
3573 else if (outer == AND
3574 && const_ok_for_arm (~INTVAL (x)))
3575 return -1;
3576 else if ((outer == COMPARE
3577 || outer == PLUS || outer == MINUS)
3578 && const_ok_for_arm (-INTVAL (x)))
3579 return -1;
3580 else
3581 return 5;
3583 case CONST:
3584 case LABEL_REF:
3585 case SYMBOL_REF:
3586 return 6;
3588 case CONST_DOUBLE:
3589 if (arm_const_double_rtx (x))
3590 return outer == SET ? 2 : -1;
3591 else if ((outer == COMPARE || outer == PLUS)
3592 && neg_const_double_rtx_ok_for_fpa (x))
3593 return -1;
3594 return 7;
3596 default:
3597 return 99;
3601 /* RTX costs for cores with a slow MUL implementation. */
3603 static bool
3604 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3606 enum machine_mode mode = GET_MODE (x);
3608 if (TARGET_THUMB)
3610 *total = thumb_rtx_costs (x, code, outer_code);
3611 return true;
3614 switch (code)
3616 case MULT:
3617 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3618 || mode == DImode)
3620 *total = 30;
3621 return true;
3624 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3626 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3627 & (unsigned HOST_WIDE_INT) 0xffffffff);
3628 int cost, const_ok = const_ok_for_arm (i);
3629 int j, booth_unit_size;
3631 /* Tune as appropriate. */
3632 cost = const_ok ? 4 : 8;
3633 booth_unit_size = 2;
3634 for (j = 0; i && j < 32; j += booth_unit_size)
3636 i >>= booth_unit_size;
3637 cost += 2;
3640 *total = cost;
3641 return true;
3644 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3645 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3646 return true;
3648 default:
3649 *total = arm_rtx_costs_1 (x, code, outer_code);
3650 return true;
3655 /* RTX cost for cores with a fast multiply unit (M variants). */
3657 static bool
3658 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3660 enum machine_mode mode = GET_MODE (x);
3662 if (TARGET_THUMB)
3664 *total = thumb_rtx_costs (x, code, outer_code);
3665 return true;
3668 switch (code)
3670 case MULT:
3671 /* There is no point basing this on the tuning, since it is always the
3672 fast variant if it exists at all. */
3673 if (mode == DImode
3674 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3675 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3676 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3678 *total = 8;
3679 return true;
3683 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3684 || mode == DImode)
3686 *total = 30;
3687 return true;
3690 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3692 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3693 & (unsigned HOST_WIDE_INT) 0xffffffff);
3694 int cost, const_ok = const_ok_for_arm (i);
3695 int j, booth_unit_size;
3697 /* Tune as appropriate. */
3698 cost = const_ok ? 4 : 8;
3699 booth_unit_size = 8;
3700 for (j = 0; i && j < 32; j += booth_unit_size)
3702 i >>= booth_unit_size;
3703 cost += 2;
3706 *total = cost;
3707 return true;
3710 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3711 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3712 return true;
3714 default:
3715 *total = arm_rtx_costs_1 (x, code, outer_code);
3716 return true;
3721 /* RTX cost for XScale CPUs. */
3723 static bool
3724 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3726 enum machine_mode mode = GET_MODE (x);
3728 if (TARGET_THUMB)
3730 *total = thumb_rtx_costs (x, code, outer_code);
3731 return true;
3734 switch (code)
3736 case MULT:
3737 /* There is no point basing this on the tuning, since it is always the
3738 fast variant if it exists at all. */
3739 if (mode == DImode
3740 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3741 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3742 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3744 *total = 8;
3745 return true;
3749 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3750 || mode == DImode)
3752 *total = 30;
3753 return true;
3756 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3758 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3759 & (unsigned HOST_WIDE_INT) 0xffffffff);
3760 int cost, const_ok = const_ok_for_arm (i);
3761 unsigned HOST_WIDE_INT masked_const;
3763 /* The cost will be related to two insns.
3764 First a load of the constant (MOV or LDR), then a multiply. */
3765 cost = 2;
3766 if (! const_ok)
3767 cost += 1; /* LDR is probably more expensive because
3768 of longer result latency. */
3769 masked_const = i & 0xffff8000;
3770 if (masked_const != 0 && masked_const != 0xffff8000)
3772 masked_const = i & 0xf8000000;
3773 if (masked_const == 0 || masked_const == 0xf8000000)
3774 cost += 1;
3775 else
3776 cost += 2;
3778 *total = cost;
3779 return true;
3782 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3783 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3784 return true;
3786 default:
3787 *total = arm_rtx_costs_1 (x, code, outer_code);
3788 return true;
3793 /* RTX costs for 9e (and later) cores. */
3795 static bool
3796 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
3798 enum machine_mode mode = GET_MODE (x);
3799 int nonreg_cost;
3800 int cost;
3802 if (TARGET_THUMB)
3804 switch (code)
3806 case MULT:
3807 *total = COSTS_N_INSNS (3);
3808 return true;
3810 default:
3811 *total = thumb_rtx_costs (x, code, outer_code);
3812 return true;
3816 switch (code)
3818 case MULT:
3819 /* There is no point basing this on the tuning, since it is always the
3820 fast variant if it exists at all. */
3821 if (mode == DImode
3822 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3823 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3824 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3826 *total = 3;
3827 return true;
3831 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3833 *total = 30;
3834 return true;
3836 if (mode == DImode)
3838 cost = 7;
3839 nonreg_cost = 8;
3841 else
3843 cost = 2;
3844 nonreg_cost = 4;
3848 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
3849 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
3850 return true;
3852 default:
3853 *total = arm_rtx_costs_1 (x, code, outer_code);
3854 return true;
3857 /* All address computations that can be done are free, but rtx cost returns
3858 the same for practically all of them. So we weight the different types
3859 of address here in the order (most pref first):
3860 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3861 static inline int
3862 arm_arm_address_cost (rtx x)
3864 enum rtx_code c = GET_CODE (x);
3866 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
3867 return 0;
3868 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
3869 return 10;
3871 if (c == PLUS || c == MINUS)
3873 char cl0 = GET_RTX_CLASS (GET_CODE (XEXP (x, 0)));
3874 char cl1 = GET_RTX_CLASS (GET_CODE (XEXP (x, 1)));
3876 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3877 return 2;
3879 if (cl0 == '2' || cl0 == 'c' || cl1 == '2' || cl1 == 'c')
3880 return 3;
3882 return 4;
3885 return 6;
3888 static inline int
3889 arm_thumb_address_cost (rtx x)
3891 enum rtx_code c = GET_CODE (x);
3893 if (c == REG)
3894 return 1;
3895 if (c == PLUS
3896 && GET_CODE (XEXP (x, 0)) == REG
3897 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3898 return 1;
3900 return 2;
3903 static int
3904 arm_address_cost (rtx x)
3906 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
3909 static int
3910 arm_use_dfa_pipeline_interface (void)
3912 return true;
3915 static int
3916 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
3918 rtx i_pat, d_pat;
3920 /* Some true dependencies can have a higher cost depending
3921 on precisely how certain input operands are used. */
3922 if (arm_tune_xscale
3923 && REG_NOTE_KIND (link) == 0
3924 && recog_memoized (insn) >= 0
3925 && recog_memoized (dep) >= 0)
3927 int shift_opnum = get_attr_shift (insn);
3928 enum attr_type attr_type = get_attr_type (dep);
3930 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3931 operand for INSN. If we have a shifted input operand and the
3932 instruction we depend on is another ALU instruction, then we may
3933 have to account for an additional stall. */
3934 if (shift_opnum != 0
3935 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
3937 rtx shifted_operand;
3938 int opno;
3940 /* Get the shifted operand. */
3941 extract_insn (insn);
3942 shifted_operand = recog_data.operand[shift_opnum];
3944 /* Iterate over all the operands in DEP. If we write an operand
3945 that overlaps with SHIFTED_OPERAND, then we have increase the
3946 cost of this dependency. */
3947 extract_insn (dep);
3948 preprocess_constraints ();
3949 for (opno = 0; opno < recog_data.n_operands; opno++)
3951 /* We can ignore strict inputs. */
3952 if (recog_data.operand_type[opno] == OP_IN)
3953 continue;
3955 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3956 shifted_operand))
3957 return 2;
3962 /* XXX This is not strictly true for the FPA. */
3963 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3964 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3965 return 0;
3967 /* Call insns don't incur a stall, even if they follow a load. */
3968 if (REG_NOTE_KIND (link) == 0
3969 && GET_CODE (insn) == CALL_INSN)
3970 return 1;
3972 if ((i_pat = single_set (insn)) != NULL
3973 && GET_CODE (SET_SRC (i_pat)) == MEM
3974 && (d_pat = single_set (dep)) != NULL
3975 && GET_CODE (SET_DEST (d_pat)) == MEM)
3977 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3978 /* This is a load after a store, there is no conflict if the load reads
3979 from a cached area. Assume that loads from the stack, and from the
3980 constant pool are cached, and that others will miss. This is a
3981 hack. */
3983 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3984 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3985 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3986 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3987 return 1;
3990 return cost;
3993 static int fp_consts_inited = 0;
3995 /* Only zero is valid for VFP. Other values are also valid for FPA. */
3996 static const char * const strings_fp[8] =
3998 "0", "1", "2", "3",
3999 "4", "5", "0.5", "10"
4002 static REAL_VALUE_TYPE values_fp[8];
4004 static void
4005 init_fp_table (void)
4007 int i;
4008 REAL_VALUE_TYPE r;
4010 if (TARGET_VFP)
4011 fp_consts_inited = 1;
4012 else
4013 fp_consts_inited = 8;
4015 for (i = 0; i < fp_consts_inited; i++)
4017 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4018 values_fp[i] = r;
4022 /* Return TRUE if rtx X is a valid immediate FP constant. */
4024 arm_const_double_rtx (rtx x)
4026 REAL_VALUE_TYPE r;
4027 int i;
4029 if (!fp_consts_inited)
4030 init_fp_table ();
4032 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4033 if (REAL_VALUE_MINUS_ZERO (r))
4034 return 0;
4036 for (i = 0; i < fp_consts_inited; i++)
4037 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4038 return 1;
4040 return 0;
4043 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4045 neg_const_double_rtx_ok_for_fpa (rtx x)
4047 REAL_VALUE_TYPE r;
4048 int i;
4050 if (!fp_consts_inited)
4051 init_fp_table ();
4053 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4054 r = REAL_VALUE_NEGATE (r);
4055 if (REAL_VALUE_MINUS_ZERO (r))
4056 return 0;
4058 for (i = 0; i < 8; i++)
4059 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4060 return 1;
4062 return 0;
4065 /* Predicates for `match_operand' and `match_operator'. */
4067 /* s_register_operand is the same as register_operand, but it doesn't accept
4068 (SUBREG (MEM)...).
4070 This function exists because at the time it was put in it led to better
4071 code. SUBREG(MEM) always needs a reload in the places where
4072 s_register_operand is used, and this seemed to lead to excessive
4073 reloading. */
4075 s_register_operand (rtx op, enum machine_mode mode)
4077 if (GET_MODE (op) != mode && mode != VOIDmode)
4078 return 0;
4080 if (GET_CODE (op) == SUBREG)
4081 op = SUBREG_REG (op);
4083 /* We don't consider registers whose class is NO_REGS
4084 to be a register operand. */
4085 /* XXX might have to check for lo regs only for thumb ??? */
4086 return (GET_CODE (op) == REG
4087 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4088 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4091 /* A hard register operand (even before reload. */
4093 arm_hard_register_operand (rtx op, enum machine_mode mode)
4095 if (GET_MODE (op) != mode && mode != VOIDmode)
4096 return 0;
4098 return (GET_CODE (op) == REG
4099 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4102 /* An arm register operand. */
4104 arm_general_register_operand (rtx op, enum machine_mode mode)
4106 if (GET_MODE (op) != mode && mode != VOIDmode)
4107 return 0;
4109 if (GET_CODE (op) == SUBREG)
4110 op = SUBREG_REG (op);
4112 return (GET_CODE (op) == REG
4113 && (REGNO (op) <= LAST_ARM_REGNUM
4114 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4117 /* Only accept reg, subreg(reg), const_int. */
4119 reg_or_int_operand (rtx op, enum machine_mode mode)
4121 if (GET_CODE (op) == CONST_INT)
4122 return 1;
4124 if (GET_MODE (op) != mode && mode != VOIDmode)
4125 return 0;
4127 if (GET_CODE (op) == SUBREG)
4128 op = SUBREG_REG (op);
4130 /* We don't consider registers whose class is NO_REGS
4131 to be a register operand. */
4132 return (GET_CODE (op) == REG
4133 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4134 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4137 /* Return 1 if OP is an item in memory, given that we are in reload. */
4139 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4141 int regno = true_regnum (op);
4143 return (!CONSTANT_P (op)
4144 && (regno == -1
4145 || (GET_CODE (op) == REG
4146 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4149 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
4150 memory access (architecture V4).
4151 MODE is QImode if called when computing constraints, or VOIDmode when
4152 emitting patterns. In this latter case we cannot use memory_operand()
4153 because it will fail on badly formed MEMs, which is precisely what we are
4154 trying to catch. */
4156 bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4158 if (GET_CODE (op) != MEM)
4159 return 0;
4161 op = XEXP (op, 0);
4163 /* A sum of anything more complex than reg + reg or reg + const is bad. */
4164 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4165 && (!s_register_operand (XEXP (op, 0), VOIDmode)
4166 || (!s_register_operand (XEXP (op, 1), VOIDmode)
4167 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
4168 return 1;
4170 /* Big constants are also bad. */
4171 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
4172 && (INTVAL (XEXP (op, 1)) > 0xff
4173 || -INTVAL (XEXP (op, 1)) > 0xff))
4174 return 1;
4176 /* Everything else is good, or can will automatically be made so. */
4177 return 0;
4180 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4182 arm_rhs_operand (rtx op, enum machine_mode mode)
4184 return (s_register_operand (op, mode)
4185 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4188 /* Return TRUE for valid operands for the
4189 rhs of an ARM instruction, or a load. */
4191 arm_rhsm_operand (rtx op, enum machine_mode mode)
4193 return (s_register_operand (op, mode)
4194 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4195 || memory_operand (op, mode));
4198 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4199 constant that is valid when negated. */
4201 arm_add_operand (rtx op, enum machine_mode mode)
4203 if (TARGET_THUMB)
4204 return thumb_cmp_operand (op, mode);
4206 return (s_register_operand (op, mode)
4207 || (GET_CODE (op) == CONST_INT
4208 && (const_ok_for_arm (INTVAL (op))
4209 || const_ok_for_arm (-INTVAL (op)))));
4212 /* Return TRUE for valid ARM constants (or when valid if negated). */
4214 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4216 return (GET_CODE (op) == CONST_INT
4217 && (const_ok_for_arm (INTVAL (op))
4218 || const_ok_for_arm (-INTVAL (op))));
4222 arm_not_operand (rtx op, enum machine_mode mode)
4224 return (s_register_operand (op, mode)
4225 || (GET_CODE (op) == CONST_INT
4226 && (const_ok_for_arm (INTVAL (op))
4227 || const_ok_for_arm (~INTVAL (op)))));
4230 /* Return TRUE if the operand is a memory reference which contains an
4231 offsettable address. */
4233 offsettable_memory_operand (rtx op, enum machine_mode mode)
4235 if (mode == VOIDmode)
4236 mode = GET_MODE (op);
4238 return (mode == GET_MODE (op)
4239 && GET_CODE (op) == MEM
4240 && offsettable_address_p (reload_completed | reload_in_progress,
4241 mode, XEXP (op, 0)));
4244 /* Return TRUE if the operand is a memory reference which is, or can be
4245 made word aligned by adjusting the offset. */
4247 alignable_memory_operand (rtx op, enum machine_mode mode)
4249 rtx reg;
4251 if (mode == VOIDmode)
4252 mode = GET_MODE (op);
4254 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4255 return 0;
4257 op = XEXP (op, 0);
4259 return ((GET_CODE (reg = op) == REG
4260 || (GET_CODE (op) == SUBREG
4261 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4262 || (GET_CODE (op) == PLUS
4263 && GET_CODE (XEXP (op, 1)) == CONST_INT
4264 && (GET_CODE (reg = XEXP (op, 0)) == REG
4265 || (GET_CODE (XEXP (op, 0)) == SUBREG
4266 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4267 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4270 /* Similar to s_register_operand, but does not allow hard integer
4271 registers. */
4273 f_register_operand (rtx op, enum machine_mode mode)
4275 if (GET_MODE (op) != mode && mode != VOIDmode)
4276 return 0;
4278 if (GET_CODE (op) == SUBREG)
4279 op = SUBREG_REG (op);
4281 /* We don't consider registers whose class is NO_REGS
4282 to be a register operand. */
4283 return (GET_CODE (op) == REG
4284 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4285 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4288 /* Return TRUE for valid operands for the rhs of an floating point insns.
4289 Allows regs or certain consts on FPA, just regs for everything else. */
4291 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4293 if (s_register_operand (op, mode))
4294 return TRUE;
4296 if (GET_MODE (op) != mode && mode != VOIDmode)
4297 return FALSE;
4299 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4300 return arm_const_double_rtx (op);
4302 return FALSE;
4306 arm_float_add_operand (rtx op, enum machine_mode mode)
4308 if (s_register_operand (op, mode))
4309 return TRUE;
4311 if (GET_MODE (op) != mode && mode != VOIDmode)
4312 return FALSE;
4314 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4315 return (arm_const_double_rtx (op)
4316 || neg_const_double_rtx_ok_for_fpa (op));
4318 return FALSE;
4322 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4323 Depends which fpu we are targeting. */
4326 arm_float_compare_operand (rtx op, enum machine_mode mode)
4328 if (TARGET_VFP)
4329 return vfp_compare_operand (op, mode);
4330 else
4331 return arm_float_rhs_operand (op, mode);
4335 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4337 cirrus_memory_offset (rtx op)
4339 /* Reject eliminable registers. */
4340 if (! (reload_in_progress || reload_completed)
4341 && ( reg_mentioned_p (frame_pointer_rtx, op)
4342 || reg_mentioned_p (arg_pointer_rtx, op)
4343 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4344 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4345 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4346 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4347 return 0;
4349 if (GET_CODE (op) == MEM)
4351 rtx ind;
4353 ind = XEXP (op, 0);
4355 /* Match: (mem (reg)). */
4356 if (GET_CODE (ind) == REG)
4357 return 1;
4359 /* Match:
4360 (mem (plus (reg)
4361 (const))). */
4362 if (GET_CODE (ind) == PLUS
4363 && GET_CODE (XEXP (ind, 0)) == REG
4364 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4365 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4366 return 1;
4369 return 0;
4372 /* Return nonzero if OP is a Cirrus or general register. */
4374 cirrus_register_operand (rtx op, enum machine_mode mode)
4376 if (GET_MODE (op) != mode && mode != VOIDmode)
4377 return FALSE;
4379 if (GET_CODE (op) == SUBREG)
4380 op = SUBREG_REG (op);
4382 return (GET_CODE (op) == REG
4383 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4384 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4387 /* Return nonzero if OP is a cirrus FP register. */
4389 cirrus_fp_register (rtx op, enum machine_mode mode)
4391 if (GET_MODE (op) != mode && mode != VOIDmode)
4392 return FALSE;
4394 if (GET_CODE (op) == SUBREG)
4395 op = SUBREG_REG (op);
4397 return (GET_CODE (op) == REG
4398 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4399 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4402 /* Return nonzero if OP is a 6bit constant (0..63). */
4404 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4406 return (GET_CODE (op) == CONST_INT
4407 && INTVAL (op) >= 0
4408 && INTVAL (op) < 64);
4412 /* Return TRUE if OP is a valid VFP memory address pattern. */
4413 /* Copied from cirrus_memory_offset but with restricted offset range. */
4416 vfp_mem_operand (rtx op)
4418 /* Reject eliminable registers. */
4420 if (! (reload_in_progress || reload_completed)
4421 && ( reg_mentioned_p (frame_pointer_rtx, op)
4422 || reg_mentioned_p (arg_pointer_rtx, op)
4423 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4424 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4425 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4426 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4427 return FALSE;
4429 /* Constants are converted into offsets from labels. */
4430 if (GET_CODE (op) == MEM)
4432 rtx ind;
4434 ind = XEXP (op, 0);
4436 if (reload_completed
4437 && (GET_CODE (ind) == LABEL_REF
4438 || (GET_CODE (ind) == CONST
4439 && GET_CODE (XEXP (ind, 0)) == PLUS
4440 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4441 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4442 return TRUE;
4444 /* Match: (mem (reg)). */
4445 if (GET_CODE (ind) == REG)
4446 return arm_address_register_rtx_p (ind, 0);
4448 /* Match:
4449 (mem (plus (reg)
4450 (const))). */
4451 if (GET_CODE (ind) == PLUS
4452 && GET_CODE (XEXP (ind, 0)) == REG
4453 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4454 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4455 && INTVAL (XEXP (ind, 1)) > -1024
4456 && INTVAL (XEXP (ind, 1)) < 1024)
4457 return TRUE;
4460 return FALSE;
4464 /* Return TRUE if OP is a REG or constant zero. */
4466 vfp_compare_operand (rtx op, enum machine_mode mode)
4468 if (s_register_operand (op, mode))
4469 return TRUE;
4471 return (GET_CODE (op) == CONST_DOUBLE
4472 && arm_const_double_rtx (op));
4476 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4477 VFP registers. Otherwise return NO_REGS. */
4479 enum reg_class
4480 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4482 if (vfp_mem_operand (x) || s_register_operand (x, mode))
4483 return NO_REGS;
4485 return GENERAL_REGS;
4489 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4490 Use by the Cirrus Maverick code which has to workaround
4491 a hardware bug triggered by such instructions. */
4492 static bool
4493 arm_memory_load_p (rtx insn)
4495 rtx body, lhs, rhs;;
4497 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4498 return false;
4500 body = PATTERN (insn);
4502 if (GET_CODE (body) != SET)
4503 return false;
4505 lhs = XEXP (body, 0);
4506 rhs = XEXP (body, 1);
4508 lhs = REG_OR_SUBREG_RTX (lhs);
4510 /* If the destination is not a general purpose
4511 register we do not have to worry. */
4512 if (GET_CODE (lhs) != REG
4513 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4514 return false;
4516 /* As well as loads from memory we also have to react
4517 to loads of invalid constants which will be turned
4518 into loads from the minipool. */
4519 return (GET_CODE (rhs) == MEM
4520 || GET_CODE (rhs) == SYMBOL_REF
4521 || note_invalid_constants (insn, -1, false));
4524 /* Return TRUE if INSN is a Cirrus instruction. */
4525 static bool
4526 arm_cirrus_insn_p (rtx insn)
4528 enum attr_cirrus attr;
4530 /* get_attr aborts on USE and CLOBBER. */
4531 if (!insn
4532 || GET_CODE (insn) != INSN
4533 || GET_CODE (PATTERN (insn)) == USE
4534 || GET_CODE (PATTERN (insn)) == CLOBBER)
4535 return 0;
4537 attr = get_attr_cirrus (insn);
4539 return attr != CIRRUS_NOT;
4542 /* Cirrus reorg for invalid instruction combinations. */
4543 static void
4544 cirrus_reorg (rtx first)
4546 enum attr_cirrus attr;
4547 rtx body = PATTERN (first);
4548 rtx t;
4549 int nops;
4551 /* Any branch must be followed by 2 non Cirrus instructions. */
4552 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4554 nops = 0;
4555 t = next_nonnote_insn (first);
4557 if (arm_cirrus_insn_p (t))
4558 ++ nops;
4560 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4561 ++ nops;
4563 while (nops --)
4564 emit_insn_after (gen_nop (), first);
4566 return;
4569 /* (float (blah)) is in parallel with a clobber. */
4570 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4571 body = XVECEXP (body, 0, 0);
4573 if (GET_CODE (body) == SET)
4575 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4577 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4578 be followed by a non Cirrus insn. */
4579 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4581 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4582 emit_insn_after (gen_nop (), first);
4584 return;
4586 else if (arm_memory_load_p (first))
4588 unsigned int arm_regno;
4590 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4591 ldr/cfmv64hr combination where the Rd field is the same
4592 in both instructions must be split with a non Cirrus
4593 insn. Example:
4595 ldr r0, blah
4597 cfmvsr mvf0, r0. */
4599 /* Get Arm register number for ldr insn. */
4600 if (GET_CODE (lhs) == REG)
4601 arm_regno = REGNO (lhs);
4602 else if (GET_CODE (rhs) == REG)
4603 arm_regno = REGNO (rhs);
4604 else
4605 abort ();
4607 /* Next insn. */
4608 first = next_nonnote_insn (first);
4610 if (! arm_cirrus_insn_p (first))
4611 return;
4613 body = PATTERN (first);
4615 /* (float (blah)) is in parallel with a clobber. */
4616 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4617 body = XVECEXP (body, 0, 0);
4619 if (GET_CODE (body) == FLOAT)
4620 body = XEXP (body, 0);
4622 if (get_attr_cirrus (first) == CIRRUS_MOVE
4623 && GET_CODE (XEXP (body, 1)) == REG
4624 && arm_regno == REGNO (XEXP (body, 1)))
4625 emit_insn_after (gen_nop (), first);
4627 return;
4631 /* get_attr aborts on USE and CLOBBER. */
4632 if (!first
4633 || GET_CODE (first) != INSN
4634 || GET_CODE (PATTERN (first)) == USE
4635 || GET_CODE (PATTERN (first)) == CLOBBER)
4636 return;
4638 attr = get_attr_cirrus (first);
4640 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4641 must be followed by a non-coprocessor instruction. */
4642 if (attr == CIRRUS_COMPARE)
4644 nops = 0;
4646 t = next_nonnote_insn (first);
4648 if (arm_cirrus_insn_p (t))
4649 ++ nops;
4651 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4652 ++ nops;
4654 while (nops --)
4655 emit_insn_after (gen_nop (), first);
4657 return;
4661 /* Return nonzero if OP is a constant power of two. */
4663 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4665 if (GET_CODE (op) == CONST_INT)
4667 HOST_WIDE_INT value = INTVAL (op);
4669 return value != 0 && (value & (value - 1)) == 0;
4672 return FALSE;
4675 /* Return TRUE for a valid operand of a DImode operation.
4676 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4677 Note that this disallows MEM(REG+REG), but allows
4678 MEM(PRE/POST_INC/DEC(REG)). */
4680 di_operand (rtx op, enum machine_mode mode)
4682 if (s_register_operand (op, mode))
4683 return TRUE;
4685 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4686 return FALSE;
4688 if (GET_CODE (op) == SUBREG)
4689 op = SUBREG_REG (op);
4691 switch (GET_CODE (op))
4693 case CONST_DOUBLE:
4694 case CONST_INT:
4695 return TRUE;
4697 case MEM:
4698 return memory_address_p (DImode, XEXP (op, 0));
4700 default:
4701 return FALSE;
4705 /* Like di_operand, but don't accept constants. */
4707 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4709 if (s_register_operand (op, mode))
4710 return TRUE;
4712 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4713 return FALSE;
4715 if (GET_CODE (op) == SUBREG)
4716 op = SUBREG_REG (op);
4718 if (GET_CODE (op) == MEM)
4719 return memory_address_p (DImode, XEXP (op, 0));
4721 return FALSE;
4724 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4725 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4726 Note that this disallows MEM(REG+REG), but allows
4727 MEM(PRE/POST_INC/DEC(REG)). */
4729 soft_df_operand (rtx op, enum machine_mode mode)
4731 if (s_register_operand (op, mode))
4732 return TRUE;
4734 if (mode != VOIDmode && GET_MODE (op) != mode)
4735 return FALSE;
4737 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4738 return FALSE;
4740 if (GET_CODE (op) == SUBREG)
4741 op = SUBREG_REG (op);
4743 switch (GET_CODE (op))
4745 case CONST_DOUBLE:
4746 return TRUE;
4748 case MEM:
4749 return memory_address_p (DFmode, XEXP (op, 0));
4751 default:
4752 return FALSE;
4756 /* Like soft_df_operand, but don't accept constants. */
4758 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4760 if (s_register_operand (op, mode))
4761 return TRUE;
4763 if (mode != VOIDmode && GET_MODE (op) != mode)
4764 return FALSE;
4766 if (GET_CODE (op) == SUBREG)
4767 op = SUBREG_REG (op);
4769 if (GET_CODE (op) == MEM)
4770 return memory_address_p (DFmode, XEXP (op, 0));
4771 return FALSE;
4774 /* Return TRUE for valid index operands. */
4776 index_operand (rtx op, enum machine_mode mode)
4778 return (s_register_operand (op, mode)
4779 || (immediate_operand (op, mode)
4780 && (GET_CODE (op) != CONST_INT
4781 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4784 /* Return TRUE for valid shifts by a constant. This also accepts any
4785 power of two on the (somewhat overly relaxed) assumption that the
4786 shift operator in this case was a mult. */
4788 const_shift_operand (rtx op, enum machine_mode mode)
4790 return (power_of_two_operand (op, mode)
4791 || (immediate_operand (op, mode)
4792 && (GET_CODE (op) != CONST_INT
4793 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4796 /* Return TRUE for arithmetic operators which can be combined with a multiply
4797 (shift). */
4799 shiftable_operator (rtx x, enum machine_mode mode)
4801 enum rtx_code code;
4803 if (GET_MODE (x) != mode)
4804 return FALSE;
4806 code = GET_CODE (x);
4808 return (code == PLUS || code == MINUS
4809 || code == IOR || code == XOR || code == AND);
4812 /* Return TRUE for binary logical operators. */
4814 logical_binary_operator (rtx x, enum machine_mode mode)
4816 enum rtx_code code;
4818 if (GET_MODE (x) != mode)
4819 return FALSE;
4821 code = GET_CODE (x);
4823 return (code == IOR || code == XOR || code == AND);
4826 /* Return TRUE for shift operators. */
4828 shift_operator (rtx x,enum machine_mode mode)
4830 enum rtx_code code;
4832 if (GET_MODE (x) != mode)
4833 return FALSE;
4835 code = GET_CODE (x);
4837 if (code == MULT)
4838 return power_of_two_operand (XEXP (x, 1), mode);
4840 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4841 || code == ROTATERT);
4844 /* Return TRUE if x is EQ or NE. */
4846 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4848 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4851 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4853 arm_comparison_operator (rtx x, enum machine_mode mode)
4855 return (comparison_operator (x, mode)
4856 && GET_CODE (x) != LTGT
4857 && GET_CODE (x) != UNEQ);
4860 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4862 minmax_operator (rtx x, enum machine_mode mode)
4864 enum rtx_code code = GET_CODE (x);
4866 if (GET_MODE (x) != mode)
4867 return FALSE;
4869 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4872 /* Return TRUE if this is the condition code register, if we aren't given
4873 a mode, accept any class CCmode register. */
4875 cc_register (rtx x, enum machine_mode mode)
4877 if (mode == VOIDmode)
4879 mode = GET_MODE (x);
4881 if (GET_MODE_CLASS (mode) != MODE_CC)
4882 return FALSE;
4885 if ( GET_MODE (x) == mode
4886 && GET_CODE (x) == REG
4887 && REGNO (x) == CC_REGNUM)
4888 return TRUE;
4890 return FALSE;
4893 /* Return TRUE if this is the condition code register, if we aren't given
4894 a mode, accept any class CCmode register which indicates a dominance
4895 expression. */
4897 dominant_cc_register (rtx x, enum machine_mode mode)
4899 if (mode == VOIDmode)
4901 mode = GET_MODE (x);
4903 if (GET_MODE_CLASS (mode) != MODE_CC)
4904 return FALSE;
4907 if (mode != CC_DNEmode && mode != CC_DEQmode
4908 && mode != CC_DLEmode && mode != CC_DLTmode
4909 && mode != CC_DGEmode && mode != CC_DGTmode
4910 && mode != CC_DLEUmode && mode != CC_DLTUmode
4911 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4912 return FALSE;
4914 return cc_register (x, mode);
4917 /* Return TRUE if X references a SYMBOL_REF. */
4919 symbol_mentioned_p (rtx x)
4921 const char * fmt;
4922 int i;
4924 if (GET_CODE (x) == SYMBOL_REF)
4925 return 1;
4927 fmt = GET_RTX_FORMAT (GET_CODE (x));
4929 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4931 if (fmt[i] == 'E')
4933 int j;
4935 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4936 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4937 return 1;
4939 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4940 return 1;
4943 return 0;
4946 /* Return TRUE if X references a LABEL_REF. */
4948 label_mentioned_p (rtx x)
4950 const char * fmt;
4951 int i;
4953 if (GET_CODE (x) == LABEL_REF)
4954 return 1;
4956 fmt = GET_RTX_FORMAT (GET_CODE (x));
4957 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4959 if (fmt[i] == 'E')
4961 int j;
4963 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4964 if (label_mentioned_p (XVECEXP (x, i, j)))
4965 return 1;
4967 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4968 return 1;
4971 return 0;
4974 enum rtx_code
4975 minmax_code (rtx x)
4977 enum rtx_code code = GET_CODE (x);
4979 if (code == SMAX)
4980 return GE;
4981 else if (code == SMIN)
4982 return LE;
4983 else if (code == UMIN)
4984 return LEU;
4985 else if (code == UMAX)
4986 return GEU;
4988 abort ();
4991 /* Return 1 if memory locations are adjacent. */
4993 adjacent_mem_locations (rtx a, rtx b)
4995 if ((GET_CODE (XEXP (a, 0)) == REG
4996 || (GET_CODE (XEXP (a, 0)) == PLUS
4997 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4998 && (GET_CODE (XEXP (b, 0)) == REG
4999 || (GET_CODE (XEXP (b, 0)) == PLUS
5000 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5002 int val0 = 0, val1 = 0;
5003 int reg0, reg1;
5005 if (GET_CODE (XEXP (a, 0)) == PLUS)
5007 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5008 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5010 else
5011 reg0 = REGNO (XEXP (a, 0));
5013 if (GET_CODE (XEXP (b, 0)) == PLUS)
5015 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5016 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5018 else
5019 reg1 = REGNO (XEXP (b, 0));
5021 /* Don't accept any offset that will require multiple
5022 instructions to handle, since this would cause the
5023 arith_adjacentmem pattern to output an overlong sequence. */
5024 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5025 return 0;
5027 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5029 return 0;
5032 /* Return 1 if OP is a load multiple operation. It is known to be
5033 parallel and the first section will be tested. */
5035 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5037 HOST_WIDE_INT count = XVECLEN (op, 0);
5038 int dest_regno;
5039 rtx src_addr;
5040 HOST_WIDE_INT i = 1, base = 0;
5041 rtx elt;
5043 if (count <= 1
5044 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5045 return 0;
5047 /* Check to see if this might be a write-back. */
5048 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5050 i++;
5051 base = 1;
5053 /* Now check it more carefully. */
5054 if (GET_CODE (SET_DEST (elt)) != REG
5055 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5056 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5057 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5058 return 0;
5061 /* Perform a quick check so we don't blow up below. */
5062 if (count <= i
5063 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5064 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5065 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5066 return 0;
5068 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5069 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5071 for (; i < count; i++)
5073 elt = XVECEXP (op, 0, i);
5075 if (GET_CODE (elt) != SET
5076 || GET_CODE (SET_DEST (elt)) != REG
5077 || GET_MODE (SET_DEST (elt)) != SImode
5078 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5079 || GET_CODE (SET_SRC (elt)) != MEM
5080 || GET_MODE (SET_SRC (elt)) != SImode
5081 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5082 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5083 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5084 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5085 return 0;
5088 return 1;
5091 /* Return 1 if OP is a store multiple operation. It is known to be
5092 parallel and the first section will be tested. */
5094 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5096 HOST_WIDE_INT count = XVECLEN (op, 0);
5097 int src_regno;
5098 rtx dest_addr;
5099 HOST_WIDE_INT i = 1, base = 0;
5100 rtx elt;
5102 if (count <= 1
5103 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5104 return 0;
5106 /* Check to see if this might be a write-back. */
5107 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5109 i++;
5110 base = 1;
5112 /* Now check it more carefully. */
5113 if (GET_CODE (SET_DEST (elt)) != REG
5114 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5115 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5116 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5117 return 0;
5120 /* Perform a quick check so we don't blow up below. */
5121 if (count <= i
5122 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5123 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5124 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5125 return 0;
5127 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5128 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5130 for (; i < count; i++)
5132 elt = XVECEXP (op, 0, i);
5134 if (GET_CODE (elt) != SET
5135 || GET_CODE (SET_SRC (elt)) != REG
5136 || GET_MODE (SET_SRC (elt)) != SImode
5137 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5138 || GET_CODE (SET_DEST (elt)) != MEM
5139 || GET_MODE (SET_DEST (elt)) != SImode
5140 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5141 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5142 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5143 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5144 return 0;
5147 return 1;
5151 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5152 HOST_WIDE_INT *load_offset)
5154 int unsorted_regs[4];
5155 HOST_WIDE_INT unsorted_offsets[4];
5156 int order[4];
5157 int base_reg = -1;
5158 int i;
5160 /* Can only handle 2, 3, or 4 insns at present,
5161 though could be easily extended if required. */
5162 if (nops < 2 || nops > 4)
5163 abort ();
5165 /* Loop over the operands and check that the memory references are
5166 suitable (ie immediate offsets from the same base register). At
5167 the same time, extract the target register, and the memory
5168 offsets. */
5169 for (i = 0; i < nops; i++)
5171 rtx reg;
5172 rtx offset;
5174 /* Convert a subreg of a mem into the mem itself. */
5175 if (GET_CODE (operands[nops + i]) == SUBREG)
5176 operands[nops + i] = alter_subreg (operands + (nops + i));
5178 if (GET_CODE (operands[nops + i]) != MEM)
5179 abort ();
5181 /* Don't reorder volatile memory references; it doesn't seem worth
5182 looking for the case where the order is ok anyway. */
5183 if (MEM_VOLATILE_P (operands[nops + i]))
5184 return 0;
5186 offset = const0_rtx;
5188 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5189 || (GET_CODE (reg) == SUBREG
5190 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5191 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5192 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5193 == REG)
5194 || (GET_CODE (reg) == SUBREG
5195 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5196 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5197 == CONST_INT)))
5199 if (i == 0)
5201 base_reg = REGNO (reg);
5202 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5203 ? REGNO (operands[i])
5204 : REGNO (SUBREG_REG (operands[i])));
5205 order[0] = 0;
5207 else
5209 if (base_reg != (int) REGNO (reg))
5210 /* Not addressed from the same base register. */
5211 return 0;
5213 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5214 ? REGNO (operands[i])
5215 : REGNO (SUBREG_REG (operands[i])));
5216 if (unsorted_regs[i] < unsorted_regs[order[0]])
5217 order[0] = i;
5220 /* If it isn't an integer register, or if it overwrites the
5221 base register but isn't the last insn in the list, then
5222 we can't do this. */
5223 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5224 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5225 return 0;
5227 unsorted_offsets[i] = INTVAL (offset);
5229 else
5230 /* Not a suitable memory address. */
5231 return 0;
5234 /* All the useful information has now been extracted from the
5235 operands into unsorted_regs and unsorted_offsets; additionally,
5236 order[0] has been set to the lowest numbered register in the
5237 list. Sort the registers into order, and check that the memory
5238 offsets are ascending and adjacent. */
5240 for (i = 1; i < nops; i++)
5242 int j;
5244 order[i] = order[i - 1];
5245 for (j = 0; j < nops; j++)
5246 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5247 && (order[i] == order[i - 1]
5248 || unsorted_regs[j] < unsorted_regs[order[i]]))
5249 order[i] = j;
5251 /* Have we found a suitable register? if not, one must be used more
5252 than once. */
5253 if (order[i] == order[i - 1])
5254 return 0;
5256 /* Is the memory address adjacent and ascending? */
5257 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5258 return 0;
5261 if (base)
5263 *base = base_reg;
5265 for (i = 0; i < nops; i++)
5266 regs[i] = unsorted_regs[order[i]];
5268 *load_offset = unsorted_offsets[order[0]];
5271 if (unsorted_offsets[order[0]] == 0)
5272 return 1; /* ldmia */
5274 if (unsorted_offsets[order[0]] == 4)
5275 return 2; /* ldmib */
5277 if (unsorted_offsets[order[nops - 1]] == 0)
5278 return 3; /* ldmda */
5280 if (unsorted_offsets[order[nops - 1]] == -4)
5281 return 4; /* ldmdb */
5283 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5284 if the offset isn't small enough. The reason 2 ldrs are faster
5285 is because these ARMs are able to do more than one cache access
5286 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5287 whilst the ARM8 has a double bandwidth cache. This means that
5288 these cores can do both an instruction fetch and a data fetch in
5289 a single cycle, so the trick of calculating the address into a
5290 scratch register (one of the result regs) and then doing a load
5291 multiple actually becomes slower (and no smaller in code size).
5292 That is the transformation
5294 ldr rd1, [rbase + offset]
5295 ldr rd2, [rbase + offset + 4]
5299 add rd1, rbase, offset
5300 ldmia rd1, {rd1, rd2}
5302 produces worse code -- '3 cycles + any stalls on rd2' instead of
5303 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5304 access per cycle, the first sequence could never complete in less
5305 than 6 cycles, whereas the ldm sequence would only take 5 and
5306 would make better use of sequential accesses if not hitting the
5307 cache.
5309 We cheat here and test 'arm_ld_sched' which we currently know to
5310 only be true for the ARM8, ARM9 and StrongARM. If this ever
5311 changes, then the test below needs to be reworked. */
5312 if (nops == 2 && arm_ld_sched)
5313 return 0;
5315 /* Can't do it without setting up the offset, only do this if it takes
5316 no more than one insn. */
5317 return (const_ok_for_arm (unsorted_offsets[order[0]])
5318 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5321 const char *
5322 emit_ldm_seq (rtx *operands, int nops)
5324 int regs[4];
5325 int base_reg;
5326 HOST_WIDE_INT offset;
5327 char buf[100];
5328 int i;
5330 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5332 case 1:
5333 strcpy (buf, "ldm%?ia\t");
5334 break;
5336 case 2:
5337 strcpy (buf, "ldm%?ib\t");
5338 break;
5340 case 3:
5341 strcpy (buf, "ldm%?da\t");
5342 break;
5344 case 4:
5345 strcpy (buf, "ldm%?db\t");
5346 break;
5348 case 5:
5349 if (offset >= 0)
5350 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5351 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5352 (long) offset);
5353 else
5354 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5355 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5356 (long) -offset);
5357 output_asm_insn (buf, operands);
5358 base_reg = regs[0];
5359 strcpy (buf, "ldm%?ia\t");
5360 break;
5362 default:
5363 abort ();
5366 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5367 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5369 for (i = 1; i < nops; i++)
5370 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5371 reg_names[regs[i]]);
5373 strcat (buf, "}\t%@ phole ldm");
5375 output_asm_insn (buf, operands);
5376 return "";
5380 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5381 HOST_WIDE_INT * load_offset)
5383 int unsorted_regs[4];
5384 HOST_WIDE_INT unsorted_offsets[4];
5385 int order[4];
5386 int base_reg = -1;
5387 int i;
5389 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5390 extended if required. */
5391 if (nops < 2 || nops > 4)
5392 abort ();
5394 /* Loop over the operands and check that the memory references are
5395 suitable (ie immediate offsets from the same base register). At
5396 the same time, extract the target register, and the memory
5397 offsets. */
5398 for (i = 0; i < nops; i++)
5400 rtx reg;
5401 rtx offset;
5403 /* Convert a subreg of a mem into the mem itself. */
5404 if (GET_CODE (operands[nops + i]) == SUBREG)
5405 operands[nops + i] = alter_subreg (operands + (nops + i));
5407 if (GET_CODE (operands[nops + i]) != MEM)
5408 abort ();
5410 /* Don't reorder volatile memory references; it doesn't seem worth
5411 looking for the case where the order is ok anyway. */
5412 if (MEM_VOLATILE_P (operands[nops + i]))
5413 return 0;
5415 offset = const0_rtx;
5417 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5418 || (GET_CODE (reg) == SUBREG
5419 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5420 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5421 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5422 == REG)
5423 || (GET_CODE (reg) == SUBREG
5424 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5425 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5426 == CONST_INT)))
5428 if (i == 0)
5430 base_reg = REGNO (reg);
5431 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5432 ? REGNO (operands[i])
5433 : REGNO (SUBREG_REG (operands[i])));
5434 order[0] = 0;
5436 else
5438 if (base_reg != (int) REGNO (reg))
5439 /* Not addressed from the same base register. */
5440 return 0;
5442 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5443 ? REGNO (operands[i])
5444 : REGNO (SUBREG_REG (operands[i])));
5445 if (unsorted_regs[i] < unsorted_regs[order[0]])
5446 order[0] = i;
5449 /* If it isn't an integer register, then we can't do this. */
5450 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5451 return 0;
5453 unsorted_offsets[i] = INTVAL (offset);
5455 else
5456 /* Not a suitable memory address. */
5457 return 0;
5460 /* All the useful information has now been extracted from the
5461 operands into unsorted_regs and unsorted_offsets; additionally,
5462 order[0] has been set to the lowest numbered register in the
5463 list. Sort the registers into order, and check that the memory
5464 offsets are ascending and adjacent. */
5466 for (i = 1; i < nops; i++)
5468 int j;
5470 order[i] = order[i - 1];
5471 for (j = 0; j < nops; j++)
5472 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5473 && (order[i] == order[i - 1]
5474 || unsorted_regs[j] < unsorted_regs[order[i]]))
5475 order[i] = j;
5477 /* Have we found a suitable register? if not, one must be used more
5478 than once. */
5479 if (order[i] == order[i - 1])
5480 return 0;
5482 /* Is the memory address adjacent and ascending? */
5483 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5484 return 0;
5487 if (base)
5489 *base = base_reg;
5491 for (i = 0; i < nops; i++)
5492 regs[i] = unsorted_regs[order[i]];
5494 *load_offset = unsorted_offsets[order[0]];
5497 if (unsorted_offsets[order[0]] == 0)
5498 return 1; /* stmia */
5500 if (unsorted_offsets[order[0]] == 4)
5501 return 2; /* stmib */
5503 if (unsorted_offsets[order[nops - 1]] == 0)
5504 return 3; /* stmda */
5506 if (unsorted_offsets[order[nops - 1]] == -4)
5507 return 4; /* stmdb */
5509 return 0;
5512 const char *
5513 emit_stm_seq (rtx *operands, int nops)
5515 int regs[4];
5516 int base_reg;
5517 HOST_WIDE_INT offset;
5518 char buf[100];
5519 int i;
5521 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5523 case 1:
5524 strcpy (buf, "stm%?ia\t");
5525 break;
5527 case 2:
5528 strcpy (buf, "stm%?ib\t");
5529 break;
5531 case 3:
5532 strcpy (buf, "stm%?da\t");
5533 break;
5535 case 4:
5536 strcpy (buf, "stm%?db\t");
5537 break;
5539 default:
5540 abort ();
5543 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5544 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5546 for (i = 1; i < nops; i++)
5547 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5548 reg_names[regs[i]]);
5550 strcat (buf, "}\t%@ phole stm");
5552 output_asm_insn (buf, operands);
5553 return "";
5557 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5559 if (GET_CODE (op) != PARALLEL
5560 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5561 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5562 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5563 return 0;
5565 return 1;
5568 /* Routines for use in generating RTL. */
5571 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5572 int write_back, int unchanging_p, int in_struct_p,
5573 int scalar_p)
5575 int i = 0, j;
5576 rtx result;
5577 int sign = up ? 1 : -1;
5578 rtx mem;
5580 /* XScale has load-store double instructions, but they have stricter
5581 alignment requirements than load-store multiple, so we can not
5582 use them.
5584 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5585 the pipeline until completion.
5587 NREGS CYCLES
5593 An ldr instruction takes 1-3 cycles, but does not block the
5594 pipeline.
5596 NREGS CYCLES
5597 1 1-3
5598 2 2-6
5599 3 3-9
5600 4 4-12
5602 Best case ldr will always win. However, the more ldr instructions
5603 we issue, the less likely we are to be able to schedule them well.
5604 Using ldr instructions also increases code size.
5606 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5607 for counts of 3 or 4 regs. */
5608 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5610 rtx seq;
5612 start_sequence ();
5614 for (i = 0; i < count; i++)
5616 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5617 RTX_UNCHANGING_P (mem) = unchanging_p;
5618 MEM_IN_STRUCT_P (mem) = in_struct_p;
5619 MEM_SCALAR_P (mem) = scalar_p;
5620 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5623 if (write_back)
5624 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5626 seq = get_insns ();
5627 end_sequence ();
5629 return seq;
5632 result = gen_rtx_PARALLEL (VOIDmode,
5633 rtvec_alloc (count + (write_back ? 1 : 0)));
5634 if (write_back)
5636 XVECEXP (result, 0, 0)
5637 = gen_rtx_SET (GET_MODE (from), from,
5638 plus_constant (from, count * 4 * sign));
5639 i = 1;
5640 count++;
5643 for (j = 0; i < count; i++, j++)
5645 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5646 RTX_UNCHANGING_P (mem) = unchanging_p;
5647 MEM_IN_STRUCT_P (mem) = in_struct_p;
5648 MEM_SCALAR_P (mem) = scalar_p;
5649 XVECEXP (result, 0, i)
5650 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5653 return result;
5657 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5658 int write_back, int unchanging_p, int in_struct_p,
5659 int scalar_p)
5661 int i = 0, j;
5662 rtx result;
5663 int sign = up ? 1 : -1;
5664 rtx mem;
5666 /* See arm_gen_load_multiple for discussion of
5667 the pros/cons of ldm/stm usage for XScale. */
5668 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5670 rtx seq;
5672 start_sequence ();
5674 for (i = 0; i < count; i++)
5676 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5677 RTX_UNCHANGING_P (mem) = unchanging_p;
5678 MEM_IN_STRUCT_P (mem) = in_struct_p;
5679 MEM_SCALAR_P (mem) = scalar_p;
5680 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5683 if (write_back)
5684 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5686 seq = get_insns ();
5687 end_sequence ();
5689 return seq;
5692 result = gen_rtx_PARALLEL (VOIDmode,
5693 rtvec_alloc (count + (write_back ? 1 : 0)));
5694 if (write_back)
5696 XVECEXP (result, 0, 0)
5697 = gen_rtx_SET (GET_MODE (to), to,
5698 plus_constant (to, count * 4 * sign));
5699 i = 1;
5700 count++;
5703 for (j = 0; i < count; i++, j++)
5705 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5706 RTX_UNCHANGING_P (mem) = unchanging_p;
5707 MEM_IN_STRUCT_P (mem) = in_struct_p;
5708 MEM_SCALAR_P (mem) = scalar_p;
5710 XVECEXP (result, 0, i)
5711 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5714 return result;
5718 arm_gen_movstrqi (rtx *operands)
5720 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5721 int i;
5722 rtx src, dst;
5723 rtx st_src, st_dst, fin_src, fin_dst;
5724 rtx part_bytes_reg = NULL;
5725 rtx mem;
5726 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5727 int dst_scalar_p, src_scalar_p;
5729 if (GET_CODE (operands[2]) != CONST_INT
5730 || GET_CODE (operands[3]) != CONST_INT
5731 || INTVAL (operands[2]) > 64
5732 || INTVAL (operands[3]) & 3)
5733 return 0;
5735 st_dst = XEXP (operands[0], 0);
5736 st_src = XEXP (operands[1], 0);
5738 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5739 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5740 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5741 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5742 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5743 src_scalar_p = MEM_SCALAR_P (operands[1]);
5745 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5746 fin_src = src = copy_to_mode_reg (SImode, st_src);
5748 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5749 out_words_to_go = INTVAL (operands[2]) / 4;
5750 last_bytes = INTVAL (operands[2]) & 3;
5752 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5753 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5755 for (i = 0; in_words_to_go >= 2; i+=4)
5757 if (in_words_to_go > 4)
5758 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5759 src_unchanging_p,
5760 src_in_struct_p,
5761 src_scalar_p));
5762 else
5763 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5764 FALSE, src_unchanging_p,
5765 src_in_struct_p, src_scalar_p));
5767 if (out_words_to_go)
5769 if (out_words_to_go > 4)
5770 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5771 dst_unchanging_p,
5772 dst_in_struct_p,
5773 dst_scalar_p));
5774 else if (out_words_to_go != 1)
5775 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5776 dst, TRUE,
5777 (last_bytes == 0
5778 ? FALSE : TRUE),
5779 dst_unchanging_p,
5780 dst_in_struct_p,
5781 dst_scalar_p));
5782 else
5784 mem = gen_rtx_MEM (SImode, dst);
5785 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5786 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5787 MEM_SCALAR_P (mem) = dst_scalar_p;
5788 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5789 if (last_bytes != 0)
5790 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5794 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5795 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5798 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5799 if (out_words_to_go)
5801 rtx sreg;
5803 mem = gen_rtx_MEM (SImode, src);
5804 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5805 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5806 MEM_SCALAR_P (mem) = src_scalar_p;
5807 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5808 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5810 mem = gen_rtx_MEM (SImode, dst);
5811 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5812 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5813 MEM_SCALAR_P (mem) = dst_scalar_p;
5814 emit_move_insn (mem, sreg);
5815 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5816 in_words_to_go--;
5818 if (in_words_to_go) /* Sanity check */
5819 abort ();
5822 if (in_words_to_go)
5824 if (in_words_to_go < 0)
5825 abort ();
5827 mem = gen_rtx_MEM (SImode, src);
5828 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5829 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5830 MEM_SCALAR_P (mem) = src_scalar_p;
5831 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5834 if (last_bytes && part_bytes_reg == NULL)
5835 abort ();
5837 if (BYTES_BIG_ENDIAN && last_bytes)
5839 rtx tmp = gen_reg_rtx (SImode);
5841 /* The bytes we want are in the top end of the word. */
5842 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5843 GEN_INT (8 * (4 - last_bytes))));
5844 part_bytes_reg = tmp;
5846 while (last_bytes)
5848 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5849 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5850 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5851 MEM_SCALAR_P (mem) = dst_scalar_p;
5852 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5854 if (--last_bytes)
5856 tmp = gen_reg_rtx (SImode);
5857 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5858 part_bytes_reg = tmp;
5863 else
5865 if (last_bytes > 1)
5867 mem = gen_rtx_MEM (HImode, dst);
5868 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5869 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5870 MEM_SCALAR_P (mem) = dst_scalar_p;
5871 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5872 last_bytes -= 2;
5873 if (last_bytes)
5875 rtx tmp = gen_reg_rtx (SImode);
5877 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
5878 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5879 part_bytes_reg = tmp;
5883 if (last_bytes)
5885 mem = gen_rtx_MEM (QImode, dst);
5886 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5887 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5888 MEM_SCALAR_P (mem) = dst_scalar_p;
5889 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5893 return 1;
5896 /* Generate a memory reference for a half word, such that it will be loaded
5897 into the top 16 bits of the word. We can assume that the address is
5898 known to be alignable and of the form reg, or plus (reg, const). */
5901 arm_gen_rotated_half_load (rtx memref)
5903 HOST_WIDE_INT offset = 0;
5904 rtx base = XEXP (memref, 0);
5906 if (GET_CODE (base) == PLUS)
5908 offset = INTVAL (XEXP (base, 1));
5909 base = XEXP (base, 0);
5912 /* If we aren't allowed to generate unaligned addresses, then fail. */
5913 if (TARGET_MMU_TRAPS
5914 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5915 return NULL;
5917 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5919 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5920 return base;
5922 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5925 /* Select a dominance comparison mode if possible for a test of the general
5926 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5927 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5928 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5929 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5930 In all cases OP will be either EQ or NE, but we don't need to know which
5931 here. If we are unable to support a dominance comparison we return
5932 CC mode. This will then fail to match for the RTL expressions that
5933 generate this call. */
5934 enum machine_mode
5935 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5937 enum rtx_code cond1, cond2;
5938 int swapped = 0;
5940 /* Currently we will probably get the wrong result if the individual
5941 comparisons are not simple. This also ensures that it is safe to
5942 reverse a comparison if necessary. */
5943 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5944 != CCmode)
5945 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5946 != CCmode))
5947 return CCmode;
5949 /* The if_then_else variant of this tests the second condition if the
5950 first passes, but is true if the first fails. Reverse the first
5951 condition to get a true "inclusive-or" expression. */
5952 if (cond_or == DOM_CC_NX_OR_Y)
5953 cond1 = reverse_condition (cond1);
5955 /* If the comparisons are not equal, and one doesn't dominate the other,
5956 then we can't do this. */
5957 if (cond1 != cond2
5958 && !comparison_dominates_p (cond1, cond2)
5959 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5960 return CCmode;
5962 if (swapped)
5964 enum rtx_code temp = cond1;
5965 cond1 = cond2;
5966 cond2 = temp;
5969 switch (cond1)
5971 case EQ:
5972 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5973 return CC_DEQmode;
5975 switch (cond2)
5977 case LE: return CC_DLEmode;
5978 case LEU: return CC_DLEUmode;
5979 case GE: return CC_DGEmode;
5980 case GEU: return CC_DGEUmode;
5981 default: break;
5984 break;
5986 case LT:
5987 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5988 return CC_DLTmode;
5989 if (cond2 == LE)
5990 return CC_DLEmode;
5991 if (cond2 == NE)
5992 return CC_DNEmode;
5993 break;
5995 case GT:
5996 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5997 return CC_DGTmode;
5998 if (cond2 == GE)
5999 return CC_DGEmode;
6000 if (cond2 == NE)
6001 return CC_DNEmode;
6002 break;
6004 case LTU:
6005 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6006 return CC_DLTUmode;
6007 if (cond2 == LEU)
6008 return CC_DLEUmode;
6009 if (cond2 == NE)
6010 return CC_DNEmode;
6011 break;
6013 case GTU:
6014 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6015 return CC_DGTUmode;
6016 if (cond2 == GEU)
6017 return CC_DGEUmode;
6018 if (cond2 == NE)
6019 return CC_DNEmode;
6020 break;
6022 /* The remaining cases only occur when both comparisons are the
6023 same. */
6024 case NE:
6025 return CC_DNEmode;
6027 case LE:
6028 return CC_DLEmode;
6030 case GE:
6031 return CC_DGEmode;
6033 case LEU:
6034 return CC_DLEUmode;
6036 case GEU:
6037 return CC_DGEUmode;
6039 default:
6040 break;
6043 abort ();
6046 enum machine_mode
6047 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6049 /* All floating point compares return CCFP if it is an equality
6050 comparison, and CCFPE otherwise. */
6051 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6053 switch (op)
6055 case EQ:
6056 case NE:
6057 case UNORDERED:
6058 case ORDERED:
6059 case UNLT:
6060 case UNLE:
6061 case UNGT:
6062 case UNGE:
6063 case UNEQ:
6064 case LTGT:
6065 return CCFPmode;
6067 case LT:
6068 case LE:
6069 case GT:
6070 case GE:
6071 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6072 return CCFPmode;
6073 return CCFPEmode;
6075 default:
6076 abort ();
6080 /* A compare with a shifted operand. Because of canonicalization, the
6081 comparison will have to be swapped when we emit the assembler. */
6082 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6083 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6084 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6085 || GET_CODE (x) == ROTATERT))
6086 return CC_SWPmode;
6088 /* This is a special case that is used by combine to allow a
6089 comparison of a shifted byte load to be split into a zero-extend
6090 followed by a comparison of the shifted integer (only valid for
6091 equalities and unsigned inequalities). */
6092 if (GET_MODE (x) == SImode
6093 && GET_CODE (x) == ASHIFT
6094 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6095 && GET_CODE (XEXP (x, 0)) == SUBREG
6096 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6097 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6098 && (op == EQ || op == NE
6099 || op == GEU || op == GTU || op == LTU || op == LEU)
6100 && GET_CODE (y) == CONST_INT)
6101 return CC_Zmode;
6103 /* A construct for a conditional compare, if the false arm contains
6104 0, then both conditions must be true, otherwise either condition
6105 must be true. Not all conditions are possible, so CCmode is
6106 returned if it can't be done. */
6107 if (GET_CODE (x) == IF_THEN_ELSE
6108 && (XEXP (x, 2) == const0_rtx
6109 || XEXP (x, 2) == const1_rtx)
6110 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
6111 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
6112 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6113 INTVAL (XEXP (x, 2)));
6115 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6116 if (GET_CODE (x) == AND
6117 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
6118 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
6119 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6120 DOM_CC_X_AND_Y);
6122 if (GET_CODE (x) == IOR
6123 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
6124 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
6125 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6126 DOM_CC_X_OR_Y);
6128 /* An operation (on Thumb) where we want to test for a single bit.
6129 This is done by shifting that bit up into the top bit of a
6130 scratch register; we can then branch on the sign bit. */
6131 if (TARGET_THUMB
6132 && GET_MODE (x) == SImode
6133 && (op == EQ || op == NE)
6134 && (GET_CODE (x) == ZERO_EXTRACT))
6135 return CC_Nmode;
6137 /* An operation that sets the condition codes as a side-effect, the
6138 V flag is not set correctly, so we can only use comparisons where
6139 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6140 instead.) */
6141 if (GET_MODE (x) == SImode
6142 && y == const0_rtx
6143 && (op == EQ || op == NE || op == LT || op == GE)
6144 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6145 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6146 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6147 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6148 || GET_CODE (x) == LSHIFTRT
6149 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6150 || GET_CODE (x) == ROTATERT
6151 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6152 return CC_NOOVmode;
6154 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6155 return CC_Zmode;
6157 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6158 && GET_CODE (x) == PLUS
6159 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6160 return CC_Cmode;
6162 return CCmode;
6165 /* X and Y are two things to compare using CODE. Emit the compare insn and
6166 return the rtx for register 0 in the proper mode. FP means this is a
6167 floating point compare: I don't think that it is needed on the arm. */
6169 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6171 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6172 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6174 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6175 gen_rtx_COMPARE (mode, x, y)));
6177 return cc_reg;
6180 /* Generate a sequence of insns that will generate the correct return
6181 address mask depending on the physical architecture that the program
6182 is running on. */
6184 arm_gen_return_addr_mask (void)
6186 rtx reg = gen_reg_rtx (Pmode);
6188 emit_insn (gen_return_addr_mask (reg));
6189 return reg;
6192 void
6193 arm_reload_in_hi (rtx *operands)
6195 rtx ref = operands[1];
6196 rtx base, scratch;
6197 HOST_WIDE_INT offset = 0;
6199 if (GET_CODE (ref) == SUBREG)
6201 offset = SUBREG_BYTE (ref);
6202 ref = SUBREG_REG (ref);
6205 if (GET_CODE (ref) == REG)
6207 /* We have a pseudo which has been spilt onto the stack; there
6208 are two cases here: the first where there is a simple
6209 stack-slot replacement and a second where the stack-slot is
6210 out of range, or is used as a subreg. */
6211 if (reg_equiv_mem[REGNO (ref)])
6213 ref = reg_equiv_mem[REGNO (ref)];
6214 base = find_replacement (&XEXP (ref, 0));
6216 else
6217 /* The slot is out of range, or was dressed up in a SUBREG. */
6218 base = reg_equiv_address[REGNO (ref)];
6220 else
6221 base = find_replacement (&XEXP (ref, 0));
6223 /* Handle the case where the address is too complex to be offset by 1. */
6224 if (GET_CODE (base) == MINUS
6225 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6227 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6229 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6230 base = base_plus;
6232 else if (GET_CODE (base) == PLUS)
6234 /* The addend must be CONST_INT, or we would have dealt with it above. */
6235 HOST_WIDE_INT hi, lo;
6237 offset += INTVAL (XEXP (base, 1));
6238 base = XEXP (base, 0);
6240 /* Rework the address into a legal sequence of insns. */
6241 /* Valid range for lo is -4095 -> 4095 */
6242 lo = (offset >= 0
6243 ? (offset & 0xfff)
6244 : -((-offset) & 0xfff));
6246 /* Corner case, if lo is the max offset then we would be out of range
6247 once we have added the additional 1 below, so bump the msb into the
6248 pre-loading insn(s). */
6249 if (lo == 4095)
6250 lo &= 0x7ff;
6252 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6253 ^ (HOST_WIDE_INT) 0x80000000)
6254 - (HOST_WIDE_INT) 0x80000000);
6256 if (hi + lo != offset)
6257 abort ();
6259 if (hi != 0)
6261 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6263 /* Get the base address; addsi3 knows how to handle constants
6264 that require more than one insn. */
6265 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6266 base = base_plus;
6267 offset = lo;
6271 /* Operands[2] may overlap operands[0] (though it won't overlap
6272 operands[1]), that's why we asked for a DImode reg -- so we can
6273 use the bit that does not overlap. */
6274 if (REGNO (operands[2]) == REGNO (operands[0]))
6275 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6276 else
6277 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6279 emit_insn (gen_zero_extendqisi2 (scratch,
6280 gen_rtx_MEM (QImode,
6281 plus_constant (base,
6282 offset))));
6283 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6284 gen_rtx_MEM (QImode,
6285 plus_constant (base,
6286 offset + 1))));
6287 if (!BYTES_BIG_ENDIAN)
6288 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6289 gen_rtx_IOR (SImode,
6290 gen_rtx_ASHIFT
6291 (SImode,
6292 gen_rtx_SUBREG (SImode, operands[0], 0),
6293 GEN_INT (8)),
6294 scratch)));
6295 else
6296 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6297 gen_rtx_IOR (SImode,
6298 gen_rtx_ASHIFT (SImode, scratch,
6299 GEN_INT (8)),
6300 gen_rtx_SUBREG (SImode, operands[0],
6301 0))));
6304 /* Handle storing a half-word to memory during reload by synthesizing as two
6305 byte stores. Take care not to clobber the input values until after we
6306 have moved them somewhere safe. This code assumes that if the DImode
6307 scratch in operands[2] overlaps either the input value or output address
6308 in some way, then that value must die in this insn (we absolutely need
6309 two scratch registers for some corner cases). */
6310 void
6311 arm_reload_out_hi (rtx *operands)
6313 rtx ref = operands[0];
6314 rtx outval = operands[1];
6315 rtx base, scratch;
6316 HOST_WIDE_INT offset = 0;
6318 if (GET_CODE (ref) == SUBREG)
6320 offset = SUBREG_BYTE (ref);
6321 ref = SUBREG_REG (ref);
6324 if (GET_CODE (ref) == REG)
6326 /* We have a pseudo which has been spilt onto the stack; there
6327 are two cases here: the first where there is a simple
6328 stack-slot replacement and a second where the stack-slot is
6329 out of range, or is used as a subreg. */
6330 if (reg_equiv_mem[REGNO (ref)])
6332 ref = reg_equiv_mem[REGNO (ref)];
6333 base = find_replacement (&XEXP (ref, 0));
6335 else
6336 /* The slot is out of range, or was dressed up in a SUBREG. */
6337 base = reg_equiv_address[REGNO (ref)];
6339 else
6340 base = find_replacement (&XEXP (ref, 0));
6342 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6344 /* Handle the case where the address is too complex to be offset by 1. */
6345 if (GET_CODE (base) == MINUS
6346 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6348 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6350 /* Be careful not to destroy OUTVAL. */
6351 if (reg_overlap_mentioned_p (base_plus, outval))
6353 /* Updating base_plus might destroy outval, see if we can
6354 swap the scratch and base_plus. */
6355 if (!reg_overlap_mentioned_p (scratch, outval))
6357 rtx tmp = scratch;
6358 scratch = base_plus;
6359 base_plus = tmp;
6361 else
6363 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6365 /* Be conservative and copy OUTVAL into the scratch now,
6366 this should only be necessary if outval is a subreg
6367 of something larger than a word. */
6368 /* XXX Might this clobber base? I can't see how it can,
6369 since scratch is known to overlap with OUTVAL, and
6370 must be wider than a word. */
6371 emit_insn (gen_movhi (scratch_hi, outval));
6372 outval = scratch_hi;
6376 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6377 base = base_plus;
6379 else if (GET_CODE (base) == PLUS)
6381 /* The addend must be CONST_INT, or we would have dealt with it above. */
6382 HOST_WIDE_INT hi, lo;
6384 offset += INTVAL (XEXP (base, 1));
6385 base = XEXP (base, 0);
6387 /* Rework the address into a legal sequence of insns. */
6388 /* Valid range for lo is -4095 -> 4095 */
6389 lo = (offset >= 0
6390 ? (offset & 0xfff)
6391 : -((-offset) & 0xfff));
6393 /* Corner case, if lo is the max offset then we would be out of range
6394 once we have added the additional 1 below, so bump the msb into the
6395 pre-loading insn(s). */
6396 if (lo == 4095)
6397 lo &= 0x7ff;
6399 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6400 ^ (HOST_WIDE_INT) 0x80000000)
6401 - (HOST_WIDE_INT) 0x80000000);
6403 if (hi + lo != offset)
6404 abort ();
6406 if (hi != 0)
6408 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6410 /* Be careful not to destroy OUTVAL. */
6411 if (reg_overlap_mentioned_p (base_plus, outval))
6413 /* Updating base_plus might destroy outval, see if we
6414 can swap the scratch and base_plus. */
6415 if (!reg_overlap_mentioned_p (scratch, outval))
6417 rtx tmp = scratch;
6418 scratch = base_plus;
6419 base_plus = tmp;
6421 else
6423 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6425 /* Be conservative and copy outval into scratch now,
6426 this should only be necessary if outval is a
6427 subreg of something larger than a word. */
6428 /* XXX Might this clobber base? I can't see how it
6429 can, since scratch is known to overlap with
6430 outval. */
6431 emit_insn (gen_movhi (scratch_hi, outval));
6432 outval = scratch_hi;
6436 /* Get the base address; addsi3 knows how to handle constants
6437 that require more than one insn. */
6438 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6439 base = base_plus;
6440 offset = lo;
6444 if (BYTES_BIG_ENDIAN)
6446 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6447 plus_constant (base, offset + 1)),
6448 gen_lowpart (QImode, outval)));
6449 emit_insn (gen_lshrsi3 (scratch,
6450 gen_rtx_SUBREG (SImode, outval, 0),
6451 GEN_INT (8)));
6452 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6453 gen_lowpart (QImode, scratch)));
6455 else
6457 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6458 gen_lowpart (QImode, outval)));
6459 emit_insn (gen_lshrsi3 (scratch,
6460 gen_rtx_SUBREG (SImode, outval, 0),
6461 GEN_INT (8)));
6462 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6463 plus_constant (base, offset + 1)),
6464 gen_lowpart (QImode, scratch)));
6468 /* Print a symbolic form of X to the debug file, F. */
6469 static void
6470 arm_print_value (FILE *f, rtx x)
6472 switch (GET_CODE (x))
6474 case CONST_INT:
6475 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6476 return;
6478 case CONST_DOUBLE:
6479 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6480 return;
6482 case CONST_VECTOR:
6484 int i;
6486 fprintf (f, "<");
6487 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6489 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6490 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6491 fputc (',', f);
6493 fprintf (f, ">");
6495 return;
6497 case CONST_STRING:
6498 fprintf (f, "\"%s\"", XSTR (x, 0));
6499 return;
6501 case SYMBOL_REF:
6502 fprintf (f, "`%s'", XSTR (x, 0));
6503 return;
6505 case LABEL_REF:
6506 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6507 return;
6509 case CONST:
6510 arm_print_value (f, XEXP (x, 0));
6511 return;
6513 case PLUS:
6514 arm_print_value (f, XEXP (x, 0));
6515 fprintf (f, "+");
6516 arm_print_value (f, XEXP (x, 1));
6517 return;
6519 case PC:
6520 fprintf (f, "pc");
6521 return;
6523 default:
6524 fprintf (f, "????");
6525 return;
6529 /* Routines for manipulation of the constant pool. */
6531 /* Arm instructions cannot load a large constant directly into a
6532 register; they have to come from a pc relative load. The constant
6533 must therefore be placed in the addressable range of the pc
6534 relative load. Depending on the precise pc relative load
6535 instruction the range is somewhere between 256 bytes and 4k. This
6536 means that we often have to dump a constant inside a function, and
6537 generate code to branch around it.
6539 It is important to minimize this, since the branches will slow
6540 things down and make the code larger.
6542 Normally we can hide the table after an existing unconditional
6543 branch so that there is no interruption of the flow, but in the
6544 worst case the code looks like this:
6546 ldr rn, L1
6548 b L2
6549 align
6550 L1: .long value
6554 ldr rn, L3
6556 b L4
6557 align
6558 L3: .long value
6562 We fix this by performing a scan after scheduling, which notices
6563 which instructions need to have their operands fetched from the
6564 constant table and builds the table.
6566 The algorithm starts by building a table of all the constants that
6567 need fixing up and all the natural barriers in the function (places
6568 where a constant table can be dropped without breaking the flow).
6569 For each fixup we note how far the pc-relative replacement will be
6570 able to reach and the offset of the instruction into the function.
6572 Having built the table we then group the fixes together to form
6573 tables that are as large as possible (subject to addressing
6574 constraints) and emit each table of constants after the last
6575 barrier that is within range of all the instructions in the group.
6576 If a group does not contain a barrier, then we forcibly create one
6577 by inserting a jump instruction into the flow. Once the table has
6578 been inserted, the insns are then modified to reference the
6579 relevant entry in the pool.
6581 Possible enhancements to the algorithm (not implemented) are:
6583 1) For some processors and object formats, there may be benefit in
6584 aligning the pools to the start of cache lines; this alignment
6585 would need to be taken into account when calculating addressability
6586 of a pool. */
6588 /* These typedefs are located at the start of this file, so that
6589 they can be used in the prototypes there. This comment is to
6590 remind readers of that fact so that the following structures
6591 can be understood more easily.
6593 typedef struct minipool_node Mnode;
6594 typedef struct minipool_fixup Mfix; */
6596 struct minipool_node
6598 /* Doubly linked chain of entries. */
6599 Mnode * next;
6600 Mnode * prev;
6601 /* The maximum offset into the code that this entry can be placed. While
6602 pushing fixes for forward references, all entries are sorted in order
6603 of increasing max_address. */
6604 HOST_WIDE_INT max_address;
6605 /* Similarly for an entry inserted for a backwards ref. */
6606 HOST_WIDE_INT min_address;
6607 /* The number of fixes referencing this entry. This can become zero
6608 if we "unpush" an entry. In this case we ignore the entry when we
6609 come to emit the code. */
6610 int refcount;
6611 /* The offset from the start of the minipool. */
6612 HOST_WIDE_INT offset;
6613 /* The value in table. */
6614 rtx value;
6615 /* The mode of value. */
6616 enum machine_mode mode;
6617 /* The size of the value. With iWMMXt enabled
6618 sizes > 4 also imply an alignment of 8-bytes. */
6619 int fix_size;
6622 struct minipool_fixup
6624 Mfix * next;
6625 rtx insn;
6626 HOST_WIDE_INT address;
6627 rtx * loc;
6628 enum machine_mode mode;
6629 int fix_size;
6630 rtx value;
6631 Mnode * minipool;
6632 HOST_WIDE_INT forwards;
6633 HOST_WIDE_INT backwards;
6636 /* Fixes less than a word need padding out to a word boundary. */
6637 #define MINIPOOL_FIX_SIZE(mode) \
6638 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6640 static Mnode * minipool_vector_head;
6641 static Mnode * minipool_vector_tail;
6642 static rtx minipool_vector_label;
6644 /* The linked list of all minipool fixes required for this function. */
6645 Mfix * minipool_fix_head;
6646 Mfix * minipool_fix_tail;
6647 /* The fix entry for the current minipool, once it has been placed. */
6648 Mfix * minipool_barrier;
6650 /* Determines if INSN is the start of a jump table. Returns the end
6651 of the TABLE or NULL_RTX. */
6652 static rtx
6653 is_jump_table (rtx insn)
6655 rtx table;
6657 if (GET_CODE (insn) == JUMP_INSN
6658 && JUMP_LABEL (insn) != NULL
6659 && ((table = next_real_insn (JUMP_LABEL (insn)))
6660 == next_real_insn (insn))
6661 && table != NULL
6662 && GET_CODE (table) == JUMP_INSN
6663 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6664 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6665 return table;
6667 return NULL_RTX;
6670 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6671 #define JUMP_TABLES_IN_TEXT_SECTION 0
6672 #endif
6674 static HOST_WIDE_INT
6675 get_jump_table_size (rtx insn)
6677 /* ADDR_VECs only take room if read-only data does into the text
6678 section. */
6679 if (JUMP_TABLES_IN_TEXT_SECTION
6680 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6681 || 1
6682 #endif
6685 rtx body = PATTERN (insn);
6686 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6688 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6691 return 0;
6694 /* Move a minipool fix MP from its current location to before MAX_MP.
6695 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6696 constraints may need updating. */
6697 static Mnode *
6698 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6699 HOST_WIDE_INT max_address)
6701 /* This should never be true and the code below assumes these are
6702 different. */
6703 if (mp == max_mp)
6704 abort ();
6706 if (max_mp == NULL)
6708 if (max_address < mp->max_address)
6709 mp->max_address = max_address;
6711 else
6713 if (max_address > max_mp->max_address - mp->fix_size)
6714 mp->max_address = max_mp->max_address - mp->fix_size;
6715 else
6716 mp->max_address = max_address;
6718 /* Unlink MP from its current position. Since max_mp is non-null,
6719 mp->prev must be non-null. */
6720 mp->prev->next = mp->next;
6721 if (mp->next != NULL)
6722 mp->next->prev = mp->prev;
6723 else
6724 minipool_vector_tail = mp->prev;
6726 /* Re-insert it before MAX_MP. */
6727 mp->next = max_mp;
6728 mp->prev = max_mp->prev;
6729 max_mp->prev = mp;
6731 if (mp->prev != NULL)
6732 mp->prev->next = mp;
6733 else
6734 minipool_vector_head = mp;
6737 /* Save the new entry. */
6738 max_mp = mp;
6740 /* Scan over the preceding entries and adjust their addresses as
6741 required. */
6742 while (mp->prev != NULL
6743 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6745 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6746 mp = mp->prev;
6749 return max_mp;
6752 /* Add a constant to the minipool for a forward reference. Returns the
6753 node added or NULL if the constant will not fit in this pool. */
6754 static Mnode *
6755 add_minipool_forward_ref (Mfix *fix)
6757 /* If set, max_mp is the first pool_entry that has a lower
6758 constraint than the one we are trying to add. */
6759 Mnode * max_mp = NULL;
6760 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6761 Mnode * mp;
6763 /* If this fix's address is greater than the address of the first
6764 entry, then we can't put the fix in this pool. We subtract the
6765 size of the current fix to ensure that if the table is fully
6766 packed we still have enough room to insert this value by suffling
6767 the other fixes forwards. */
6768 if (minipool_vector_head &&
6769 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6770 return NULL;
6772 /* Scan the pool to see if a constant with the same value has
6773 already been added. While we are doing this, also note the
6774 location where we must insert the constant if it doesn't already
6775 exist. */
6776 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6778 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6779 && fix->mode == mp->mode
6780 && (GET_CODE (fix->value) != CODE_LABEL
6781 || (CODE_LABEL_NUMBER (fix->value)
6782 == CODE_LABEL_NUMBER (mp->value)))
6783 && rtx_equal_p (fix->value, mp->value))
6785 /* More than one fix references this entry. */
6786 mp->refcount++;
6787 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6790 /* Note the insertion point if necessary. */
6791 if (max_mp == NULL
6792 && mp->max_address > max_address)
6793 max_mp = mp;
6795 /* If we are inserting an 8-bytes aligned quantity and
6796 we have not already found an insertion point, then
6797 make sure that all such 8-byte aligned quantities are
6798 placed at the start of the pool. */
6799 if (TARGET_REALLY_IWMMXT
6800 && max_mp == NULL
6801 && fix->fix_size == 8
6802 && mp->fix_size != 8)
6804 max_mp = mp;
6805 max_address = mp->max_address;
6809 /* The value is not currently in the minipool, so we need to create
6810 a new entry for it. If MAX_MP is NULL, the entry will be put on
6811 the end of the list since the placement is less constrained than
6812 any existing entry. Otherwise, we insert the new fix before
6813 MAX_MP and, if necessary, adjust the constraints on the other
6814 entries. */
6815 mp = xmalloc (sizeof (* mp));
6816 mp->fix_size = fix->fix_size;
6817 mp->mode = fix->mode;
6818 mp->value = fix->value;
6819 mp->refcount = 1;
6820 /* Not yet required for a backwards ref. */
6821 mp->min_address = -65536;
6823 if (max_mp == NULL)
6825 mp->max_address = max_address;
6826 mp->next = NULL;
6827 mp->prev = minipool_vector_tail;
6829 if (mp->prev == NULL)
6831 minipool_vector_head = mp;
6832 minipool_vector_label = gen_label_rtx ();
6834 else
6835 mp->prev->next = mp;
6837 minipool_vector_tail = mp;
6839 else
6841 if (max_address > max_mp->max_address - mp->fix_size)
6842 mp->max_address = max_mp->max_address - mp->fix_size;
6843 else
6844 mp->max_address = max_address;
6846 mp->next = max_mp;
6847 mp->prev = max_mp->prev;
6848 max_mp->prev = mp;
6849 if (mp->prev != NULL)
6850 mp->prev->next = mp;
6851 else
6852 minipool_vector_head = mp;
6855 /* Save the new entry. */
6856 max_mp = mp;
6858 /* Scan over the preceding entries and adjust their addresses as
6859 required. */
6860 while (mp->prev != NULL
6861 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6863 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6864 mp = mp->prev;
6867 return max_mp;
6870 static Mnode *
6871 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6872 HOST_WIDE_INT min_address)
6874 HOST_WIDE_INT offset;
6876 /* This should never be true, and the code below assumes these are
6877 different. */
6878 if (mp == min_mp)
6879 abort ();
6881 if (min_mp == NULL)
6883 if (min_address > mp->min_address)
6884 mp->min_address = min_address;
6886 else
6888 /* We will adjust this below if it is too loose. */
6889 mp->min_address = min_address;
6891 /* Unlink MP from its current position. Since min_mp is non-null,
6892 mp->next must be non-null. */
6893 mp->next->prev = mp->prev;
6894 if (mp->prev != NULL)
6895 mp->prev->next = mp->next;
6896 else
6897 minipool_vector_head = mp->next;
6899 /* Reinsert it after MIN_MP. */
6900 mp->prev = min_mp;
6901 mp->next = min_mp->next;
6902 min_mp->next = mp;
6903 if (mp->next != NULL)
6904 mp->next->prev = mp;
6905 else
6906 minipool_vector_tail = mp;
6909 min_mp = mp;
6911 offset = 0;
6912 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6914 mp->offset = offset;
6915 if (mp->refcount > 0)
6916 offset += mp->fix_size;
6918 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6919 mp->next->min_address = mp->min_address + mp->fix_size;
6922 return min_mp;
6925 /* Add a constant to the minipool for a backward reference. Returns the
6926 node added or NULL if the constant will not fit in this pool.
6928 Note that the code for insertion for a backwards reference can be
6929 somewhat confusing because the calculated offsets for each fix do
6930 not take into account the size of the pool (which is still under
6931 construction. */
6932 static Mnode *
6933 add_minipool_backward_ref (Mfix *fix)
6935 /* If set, min_mp is the last pool_entry that has a lower constraint
6936 than the one we are trying to add. */
6937 Mnode *min_mp = NULL;
6938 /* This can be negative, since it is only a constraint. */
6939 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6940 Mnode *mp;
6942 /* If we can't reach the current pool from this insn, or if we can't
6943 insert this entry at the end of the pool without pushing other
6944 fixes out of range, then we don't try. This ensures that we
6945 can't fail later on. */
6946 if (min_address >= minipool_barrier->address
6947 || (minipool_vector_tail->min_address + fix->fix_size
6948 >= minipool_barrier->address))
6949 return NULL;
6951 /* Scan the pool to see if a constant with the same value has
6952 already been added. While we are doing this, also note the
6953 location where we must insert the constant if it doesn't already
6954 exist. */
6955 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6957 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6958 && fix->mode == mp->mode
6959 && (GET_CODE (fix->value) != CODE_LABEL
6960 || (CODE_LABEL_NUMBER (fix->value)
6961 == CODE_LABEL_NUMBER (mp->value)))
6962 && rtx_equal_p (fix->value, mp->value)
6963 /* Check that there is enough slack to move this entry to the
6964 end of the table (this is conservative). */
6965 && (mp->max_address
6966 > (minipool_barrier->address
6967 + minipool_vector_tail->offset
6968 + minipool_vector_tail->fix_size)))
6970 mp->refcount++;
6971 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6974 if (min_mp != NULL)
6975 mp->min_address += fix->fix_size;
6976 else
6978 /* Note the insertion point if necessary. */
6979 if (mp->min_address < min_address)
6981 /* For now, we do not allow the insertion of 8-byte alignment
6982 requiring nodes anywhere but at the start of the pool. */
6983 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8)
6984 return NULL;
6985 else
6986 min_mp = mp;
6988 else if (mp->max_address
6989 < minipool_barrier->address + mp->offset + fix->fix_size)
6991 /* Inserting before this entry would push the fix beyond
6992 its maximum address (which can happen if we have
6993 re-located a forwards fix); force the new fix to come
6994 after it. */
6995 min_mp = mp;
6996 min_address = mp->min_address + fix->fix_size;
6998 /* If we are inserting an 8-bytes aligned quantity and
6999 we have not already found an insertion point, then
7000 make sure that all such 8-byte aligned quantities are
7001 placed at the start of the pool. */
7002 else if (TARGET_REALLY_IWMMXT
7003 && min_mp == NULL
7004 && fix->fix_size == 8
7005 && mp->fix_size < 8)
7007 min_mp = mp;
7008 min_address = mp->min_address + fix->fix_size;
7013 /* We need to create a new entry. */
7014 mp = xmalloc (sizeof (* mp));
7015 mp->fix_size = fix->fix_size;
7016 mp->mode = fix->mode;
7017 mp->value = fix->value;
7018 mp->refcount = 1;
7019 mp->max_address = minipool_barrier->address + 65536;
7021 mp->min_address = min_address;
7023 if (min_mp == NULL)
7025 mp->prev = NULL;
7026 mp->next = minipool_vector_head;
7028 if (mp->next == NULL)
7030 minipool_vector_tail = mp;
7031 minipool_vector_label = gen_label_rtx ();
7033 else
7034 mp->next->prev = mp;
7036 minipool_vector_head = mp;
7038 else
7040 mp->next = min_mp->next;
7041 mp->prev = min_mp;
7042 min_mp->next = mp;
7044 if (mp->next != NULL)
7045 mp->next->prev = mp;
7046 else
7047 minipool_vector_tail = mp;
7050 /* Save the new entry. */
7051 min_mp = mp;
7053 if (mp->prev)
7054 mp = mp->prev;
7055 else
7056 mp->offset = 0;
7058 /* Scan over the following entries and adjust their offsets. */
7059 while (mp->next != NULL)
7061 if (mp->next->min_address < mp->min_address + mp->fix_size)
7062 mp->next->min_address = mp->min_address + mp->fix_size;
7064 if (mp->refcount)
7065 mp->next->offset = mp->offset + mp->fix_size;
7066 else
7067 mp->next->offset = mp->offset;
7069 mp = mp->next;
7072 return min_mp;
7075 static void
7076 assign_minipool_offsets (Mfix *barrier)
7078 HOST_WIDE_INT offset = 0;
7079 Mnode *mp;
7081 minipool_barrier = barrier;
7083 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7085 mp->offset = offset;
7087 if (mp->refcount > 0)
7088 offset += mp->fix_size;
7092 /* Output the literal table */
7093 static void
7094 dump_minipool (rtx scan)
7096 Mnode * mp;
7097 Mnode * nmp;
7098 int align64 = 0;
7100 if (TARGET_REALLY_IWMMXT)
7101 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7102 if (mp->refcount > 0 && mp->fix_size == 8)
7104 align64 = 1;
7105 break;
7108 if (dump_file)
7109 fprintf (dump_file,
7110 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7111 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7113 scan = emit_label_after (gen_label_rtx (), scan);
7114 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7115 scan = emit_label_after (minipool_vector_label, scan);
7117 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7119 if (mp->refcount > 0)
7121 if (dump_file)
7123 fprintf (dump_file,
7124 ";; Offset %u, min %ld, max %ld ",
7125 (unsigned) mp->offset, (unsigned long) mp->min_address,
7126 (unsigned long) mp->max_address);
7127 arm_print_value (dump_file, mp->value);
7128 fputc ('\n', dump_file);
7131 switch (mp->fix_size)
7133 #ifdef HAVE_consttable_1
7134 case 1:
7135 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7136 break;
7138 #endif
7139 #ifdef HAVE_consttable_2
7140 case 2:
7141 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7142 break;
7144 #endif
7145 #ifdef HAVE_consttable_4
7146 case 4:
7147 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7148 break;
7150 #endif
7151 #ifdef HAVE_consttable_8
7152 case 8:
7153 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7154 break;
7156 #endif
7157 default:
7158 abort ();
7159 break;
7163 nmp = mp->next;
7164 free (mp);
7167 minipool_vector_head = minipool_vector_tail = NULL;
7168 scan = emit_insn_after (gen_consttable_end (), scan);
7169 scan = emit_barrier_after (scan);
7172 /* Return the cost of forcibly inserting a barrier after INSN. */
7173 static int
7174 arm_barrier_cost (rtx insn)
7176 /* Basing the location of the pool on the loop depth is preferable,
7177 but at the moment, the basic block information seems to be
7178 corrupt by this stage of the compilation. */
7179 int base_cost = 50;
7180 rtx next = next_nonnote_insn (insn);
7182 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7183 base_cost -= 20;
7185 switch (GET_CODE (insn))
7187 case CODE_LABEL:
7188 /* It will always be better to place the table before the label, rather
7189 than after it. */
7190 return 50;
7192 case INSN:
7193 case CALL_INSN:
7194 return base_cost;
7196 case JUMP_INSN:
7197 return base_cost - 10;
7199 default:
7200 return base_cost + 10;
7204 /* Find the best place in the insn stream in the range
7205 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7206 Create the barrier by inserting a jump and add a new fix entry for
7207 it. */
7208 static Mfix *
7209 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7211 HOST_WIDE_INT count = 0;
7212 rtx barrier;
7213 rtx from = fix->insn;
7214 rtx selected = from;
7215 int selected_cost;
7216 HOST_WIDE_INT selected_address;
7217 Mfix * new_fix;
7218 HOST_WIDE_INT max_count = max_address - fix->address;
7219 rtx label = gen_label_rtx ();
7221 selected_cost = arm_barrier_cost (from);
7222 selected_address = fix->address;
7224 while (from && count < max_count)
7226 rtx tmp;
7227 int new_cost;
7229 /* This code shouldn't have been called if there was a natural barrier
7230 within range. */
7231 if (GET_CODE (from) == BARRIER)
7232 abort ();
7234 /* Count the length of this insn. */
7235 count += get_attr_length (from);
7237 /* If there is a jump table, add its length. */
7238 tmp = is_jump_table (from);
7239 if (tmp != NULL)
7241 count += get_jump_table_size (tmp);
7243 /* Jump tables aren't in a basic block, so base the cost on
7244 the dispatch insn. If we select this location, we will
7245 still put the pool after the table. */
7246 new_cost = arm_barrier_cost (from);
7248 if (count < max_count && new_cost <= selected_cost)
7250 selected = tmp;
7251 selected_cost = new_cost;
7252 selected_address = fix->address + count;
7255 /* Continue after the dispatch table. */
7256 from = NEXT_INSN (tmp);
7257 continue;
7260 new_cost = arm_barrier_cost (from);
7262 if (count < max_count && new_cost <= selected_cost)
7264 selected = from;
7265 selected_cost = new_cost;
7266 selected_address = fix->address + count;
7269 from = NEXT_INSN (from);
7272 /* Create a new JUMP_INSN that branches around a barrier. */
7273 from = emit_jump_insn_after (gen_jump (label), selected);
7274 JUMP_LABEL (from) = label;
7275 barrier = emit_barrier_after (from);
7276 emit_label_after (label, barrier);
7278 /* Create a minipool barrier entry for the new barrier. */
7279 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7280 new_fix->insn = barrier;
7281 new_fix->address = selected_address;
7282 new_fix->next = fix->next;
7283 fix->next = new_fix;
7285 return new_fix;
7288 /* Record that there is a natural barrier in the insn stream at
7289 ADDRESS. */
7290 static void
7291 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7293 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7295 fix->insn = insn;
7296 fix->address = address;
7298 fix->next = NULL;
7299 if (minipool_fix_head != NULL)
7300 minipool_fix_tail->next = fix;
7301 else
7302 minipool_fix_head = fix;
7304 minipool_fix_tail = fix;
7307 /* Record INSN, which will need fixing up to load a value from the
7308 minipool. ADDRESS is the offset of the insn since the start of the
7309 function; LOC is a pointer to the part of the insn which requires
7310 fixing; VALUE is the constant that must be loaded, which is of type
7311 MODE. */
7312 static void
7313 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7314 enum machine_mode mode, rtx value)
7316 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7318 #ifdef AOF_ASSEMBLER
7319 /* PIC symbol references need to be converted into offsets into the
7320 based area. */
7321 /* XXX This shouldn't be done here. */
7322 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7323 value = aof_pic_entry (value);
7324 #endif /* AOF_ASSEMBLER */
7326 fix->insn = insn;
7327 fix->address = address;
7328 fix->loc = loc;
7329 fix->mode = mode;
7330 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7331 fix->value = value;
7332 fix->forwards = get_attr_pool_range (insn);
7333 fix->backwards = get_attr_neg_pool_range (insn);
7334 fix->minipool = NULL;
7336 /* If an insn doesn't have a range defined for it, then it isn't
7337 expecting to be reworked by this code. Better to abort now than
7338 to generate duff assembly code. */
7339 if (fix->forwards == 0 && fix->backwards == 0)
7340 abort ();
7342 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7343 So there might be an empty word before the start of the pool.
7344 Hence we reduce the forward range by 4 to allow for this
7345 possibility. */
7346 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8)
7347 fix->forwards -= 4;
7349 if (dump_file)
7351 fprintf (dump_file,
7352 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7353 GET_MODE_NAME (mode),
7354 INSN_UID (insn), (unsigned long) address,
7355 -1 * (long)fix->backwards, (long)fix->forwards);
7356 arm_print_value (dump_file, fix->value);
7357 fprintf (dump_file, "\n");
7360 /* Add it to the chain of fixes. */
7361 fix->next = NULL;
7363 if (minipool_fix_head != NULL)
7364 minipool_fix_tail->next = fix;
7365 else
7366 minipool_fix_head = fix;
7368 minipool_fix_tail = fix;
7371 /* Scan INSN and note any of its operands that need fixing.
7372 If DO_PUSHES is false we do not actually push any of the fixups
7373 needed. The function returns TRUE is any fixups were needed/pushed.
7374 This is used by arm_memory_load_p() which needs to know about loads
7375 of constants that will be converted into minipool loads. */
7376 static bool
7377 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7379 bool result = false;
7380 int opno;
7382 extract_insn (insn);
7384 if (!constrain_operands (1))
7385 fatal_insn_not_found (insn);
7387 if (recog_data.n_alternatives == 0)
7388 return false;
7390 /* Fill in recog_op_alt with information about the constraints of this insn. */
7391 preprocess_constraints ();
7393 for (opno = 0; opno < recog_data.n_operands; opno++)
7395 /* Things we need to fix can only occur in inputs. */
7396 if (recog_data.operand_type[opno] != OP_IN)
7397 continue;
7399 /* If this alternative is a memory reference, then any mention
7400 of constants in this alternative is really to fool reload
7401 into allowing us to accept one there. We need to fix them up
7402 now so that we output the right code. */
7403 if (recog_op_alt[opno][which_alternative].memory_ok)
7405 rtx op = recog_data.operand[opno];
7407 if (CONSTANT_P (op))
7409 if (do_pushes)
7410 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7411 recog_data.operand_mode[opno], op);
7412 result = true;
7414 else if (GET_CODE (op) == MEM
7415 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7416 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7418 if (do_pushes)
7420 rtx cop = avoid_constant_pool_reference (op);
7422 /* Casting the address of something to a mode narrower
7423 than a word can cause avoid_constant_pool_reference()
7424 to return the pool reference itself. That's no good to
7425 us here. Lets just hope that we can use the
7426 constant pool value directly. */
7427 if (op == cop)
7428 cop = get_pool_constant (XEXP (op, 0));
7430 push_minipool_fix (insn, address,
7431 recog_data.operand_loc[opno],
7432 recog_data.operand_mode[opno], cop);
7435 result = true;
7440 return result;
7443 /* Gcc puts the pool in the wrong place for ARM, since we can only
7444 load addresses a limited distance around the pc. We do some
7445 special munging to move the constant pool values to the correct
7446 point in the code. */
7447 static void
7448 arm_reorg (void)
7450 rtx insn;
7451 HOST_WIDE_INT address = 0;
7452 Mfix * fix;
7454 minipool_fix_head = minipool_fix_tail = NULL;
7456 /* The first insn must always be a note, or the code below won't
7457 scan it properly. */
7458 insn = get_insns ();
7459 if (GET_CODE (insn) != NOTE)
7460 abort ();
7462 /* Scan all the insns and record the operands that will need fixing. */
7463 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7465 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7466 && (arm_cirrus_insn_p (insn)
7467 || GET_CODE (insn) == JUMP_INSN
7468 || arm_memory_load_p (insn)))
7469 cirrus_reorg (insn);
7471 if (GET_CODE (insn) == BARRIER)
7472 push_minipool_barrier (insn, address);
7473 else if (INSN_P (insn))
7475 rtx table;
7477 note_invalid_constants (insn, address, true);
7478 address += get_attr_length (insn);
7480 /* If the insn is a vector jump, add the size of the table
7481 and skip the table. */
7482 if ((table = is_jump_table (insn)) != NULL)
7484 address += get_jump_table_size (table);
7485 insn = table;
7490 fix = minipool_fix_head;
7492 /* Now scan the fixups and perform the required changes. */
7493 while (fix)
7495 Mfix * ftmp;
7496 Mfix * fdel;
7497 Mfix * last_added_fix;
7498 Mfix * last_barrier = NULL;
7499 Mfix * this_fix;
7501 /* Skip any further barriers before the next fix. */
7502 while (fix && GET_CODE (fix->insn) == BARRIER)
7503 fix = fix->next;
7505 /* No more fixes. */
7506 if (fix == NULL)
7507 break;
7509 last_added_fix = NULL;
7511 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7513 if (GET_CODE (ftmp->insn) == BARRIER)
7515 if (ftmp->address >= minipool_vector_head->max_address)
7516 break;
7518 last_barrier = ftmp;
7520 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7521 break;
7523 last_added_fix = ftmp; /* Keep track of the last fix added. */
7526 /* If we found a barrier, drop back to that; any fixes that we
7527 could have reached but come after the barrier will now go in
7528 the next mini-pool. */
7529 if (last_barrier != NULL)
7531 /* Reduce the refcount for those fixes that won't go into this
7532 pool after all. */
7533 for (fdel = last_barrier->next;
7534 fdel && fdel != ftmp;
7535 fdel = fdel->next)
7537 fdel->minipool->refcount--;
7538 fdel->minipool = NULL;
7541 ftmp = last_barrier;
7543 else
7545 /* ftmp is first fix that we can't fit into this pool and
7546 there no natural barriers that we could use. Insert a
7547 new barrier in the code somewhere between the previous
7548 fix and this one, and arrange to jump around it. */
7549 HOST_WIDE_INT max_address;
7551 /* The last item on the list of fixes must be a barrier, so
7552 we can never run off the end of the list of fixes without
7553 last_barrier being set. */
7554 if (ftmp == NULL)
7555 abort ();
7557 max_address = minipool_vector_head->max_address;
7558 /* Check that there isn't another fix that is in range that
7559 we couldn't fit into this pool because the pool was
7560 already too large: we need to put the pool before such an
7561 instruction. */
7562 if (ftmp->address < max_address)
7563 max_address = ftmp->address;
7565 last_barrier = create_fix_barrier (last_added_fix, max_address);
7568 assign_minipool_offsets (last_barrier);
7570 while (ftmp)
7572 if (GET_CODE (ftmp->insn) != BARRIER
7573 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7574 == NULL))
7575 break;
7577 ftmp = ftmp->next;
7580 /* Scan over the fixes we have identified for this pool, fixing them
7581 up and adding the constants to the pool itself. */
7582 for (this_fix = fix; this_fix && ftmp != this_fix;
7583 this_fix = this_fix->next)
7584 if (GET_CODE (this_fix->insn) != BARRIER)
7586 rtx addr
7587 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7588 minipool_vector_label),
7589 this_fix->minipool->offset);
7590 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7593 dump_minipool (last_barrier->insn);
7594 fix = ftmp;
7597 /* From now on we must synthesize any constants that we can't handle
7598 directly. This can happen if the RTL gets split during final
7599 instruction generation. */
7600 after_arm_reorg = 1;
7602 /* Free the minipool memory. */
7603 obstack_free (&minipool_obstack, minipool_startobj);
7606 /* Routines to output assembly language. */
7608 /* If the rtx is the correct value then return the string of the number.
7609 In this way we can ensure that valid double constants are generated even
7610 when cross compiling. */
7611 const char *
7612 fp_immediate_constant (rtx x)
7614 REAL_VALUE_TYPE r;
7615 int i;
7617 if (!fp_consts_inited)
7618 init_fp_table ();
7620 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7621 for (i = 0; i < 8; i++)
7622 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7623 return strings_fp[i];
7625 abort ();
7628 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7629 static const char *
7630 fp_const_from_val (REAL_VALUE_TYPE *r)
7632 int i;
7634 if (!fp_consts_inited)
7635 init_fp_table ();
7637 for (i = 0; i < 8; i++)
7638 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7639 return strings_fp[i];
7641 abort ();
7644 /* Output the operands of a LDM/STM instruction to STREAM.
7645 MASK is the ARM register set mask of which only bits 0-15 are important.
7646 REG is the base register, either the frame pointer or the stack pointer,
7647 INSTR is the possibly suffixed load or store instruction. */
7648 static void
7649 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7651 int i;
7652 int not_first = FALSE;
7654 fputc ('\t', stream);
7655 asm_fprintf (stream, instr, reg);
7656 fputs (", {", stream);
7658 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7659 if (mask & (1 << i))
7661 if (not_first)
7662 fprintf (stream, ", ");
7664 asm_fprintf (stream, "%r", i);
7665 not_first = TRUE;
7668 fprintf (stream, "}");
7670 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7671 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7672 Strictly speaking the instruction would be unpredicatble only if
7673 we were writing back the base register as well, but since we never
7674 want to generate an LDM type 2 instruction (register bank switching)
7675 which is what you get if the PC is not being loaded, we do not need
7676 to check for writeback. */
7677 if (! TARGET_APCS_32
7678 && ((mask & (1 << PC_REGNUM)) != 0))
7679 fprintf (stream, "^");
7681 fprintf (stream, "\n");
7685 /* Output the operands of a FLDM/FSTM instruction to STREAM.
7686 REG is the base register,
7687 INSTR is the possibly suffixed load or store instruction.
7688 FMT specifies now to print the register name.
7689 START and COUNT specify the register range. */
7691 static void
7692 vfp_print_multi (FILE *stream, const char *instr, int reg,
7693 const char * fmt, int start, int count)
7695 int i;
7697 fputc ('\t', stream);
7698 asm_fprintf (stream, instr, reg);
7699 fputs (", {", stream);
7701 for (i = start; i < start + count; i++)
7703 if (i > start)
7704 fputs (", ", stream);
7705 asm_fprintf (stream, fmt, i);
7707 fputs ("}\n", stream);
7711 /* Output the assembly for a store multiple. */
7713 const char *
7714 vfp_output_fstmx (rtx * operands)
7716 char pattern[100];
7717 int p;
7718 int base;
7719 int i;
7721 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7722 p = strlen (pattern);
7724 if (GET_CODE (operands[1]) != REG)
7725 abort ();
7727 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7728 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7730 p += sprintf (&pattern[p], ", d%d", base + i);
7732 strcpy (&pattern[p], "}");
7734 output_asm_insn (pattern, operands);
7735 return "";
7739 /* Emit RTL to save block of VFP register pairs to the stack. */
7741 static rtx
7742 vfp_emit_fstmx (int base_reg, int count)
7744 rtx par;
7745 rtx dwarf;
7746 rtx tmp, reg;
7747 int i;
7749 /* ??? The frame layout is implementation defined. We describe
7750 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7751 We really need some way of representing the whole block so that the
7752 unwinder can figure it out at runtime. */
7753 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7754 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7756 reg = gen_rtx_REG (DFmode, base_reg);
7757 base_reg += 2;
7759 XVECEXP (par, 0, 0)
7760 = gen_rtx_SET (VOIDmode,
7761 gen_rtx_MEM (BLKmode,
7762 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7763 gen_rtx_UNSPEC (BLKmode,
7764 gen_rtvec (1, reg),
7765 UNSPEC_PUSH_MULT));
7767 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7768 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7769 GEN_INT (-(count * 8 + 4))));
7770 RTX_FRAME_RELATED_P (tmp) = 1;
7771 XVECEXP (dwarf, 0, 0) = tmp;
7773 tmp = gen_rtx_SET (VOIDmode,
7774 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7775 reg);
7776 RTX_FRAME_RELATED_P (tmp) = 1;
7777 XVECEXP (dwarf, 0, 1) = tmp;
7779 for (i = 1; i < count; i++)
7781 reg = gen_rtx_REG (DFmode, base_reg);
7782 base_reg += 2;
7783 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7785 tmp = gen_rtx_SET (VOIDmode,
7786 gen_rtx_MEM (DFmode,
7787 gen_rtx_PLUS (SImode,
7788 stack_pointer_rtx,
7789 GEN_INT (i * 8))),
7790 reg);
7791 RTX_FRAME_RELATED_P (tmp) = 1;
7792 XVECEXP (dwarf, 0, i + 1) = tmp;
7795 par = emit_insn (par);
7796 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7797 REG_NOTES (par));
7798 return par;
7802 /* Output a 'call' insn. */
7803 const char *
7804 output_call (rtx *operands)
7806 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7808 if (REGNO (operands[0]) == LR_REGNUM)
7810 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7811 output_asm_insn ("mov%?\t%0, %|lr", operands);
7814 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7816 if (TARGET_INTERWORK)
7817 output_asm_insn ("bx%?\t%0", operands);
7818 else
7819 output_asm_insn ("mov%?\t%|pc, %0", operands);
7821 return "";
7824 /* Output a 'call' insn that is a reference in memory. */
7825 const char *
7826 output_call_mem (rtx *operands)
7828 if (TARGET_INTERWORK)
7830 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7831 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7832 output_asm_insn ("bx%?\t%|ip", operands);
7834 else if (regno_use_in (LR_REGNUM, operands[0]))
7836 /* LR is used in the memory address. We load the address in the
7837 first instruction. It's safe to use IP as the target of the
7838 load since the call will kill it anyway. */
7839 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7840 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7841 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7843 else
7845 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7846 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7849 return "";
7853 /* Output a move from arm registers to an fpa registers.
7854 OPERANDS[0] is an fpa register.
7855 OPERANDS[1] is the first registers of an arm register pair. */
7856 const char *
7857 output_mov_long_double_fpa_from_arm (rtx *operands)
7859 int arm_reg0 = REGNO (operands[1]);
7860 rtx ops[3];
7862 if (arm_reg0 == IP_REGNUM)
7863 abort ();
7865 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7866 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7867 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7869 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7870 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7872 return "";
7875 /* Output a move from an fpa register to arm registers.
7876 OPERANDS[0] is the first registers of an arm register pair.
7877 OPERANDS[1] is an fpa register. */
7878 const char *
7879 output_mov_long_double_arm_from_fpa (rtx *operands)
7881 int arm_reg0 = REGNO (operands[0]);
7882 rtx ops[3];
7884 if (arm_reg0 == IP_REGNUM)
7885 abort ();
7887 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7888 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7889 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7891 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7892 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7893 return "";
7896 /* Output a move from arm registers to arm registers of a long double
7897 OPERANDS[0] is the destination.
7898 OPERANDS[1] is the source. */
7899 const char *
7900 output_mov_long_double_arm_from_arm (rtx *operands)
7902 /* We have to be careful here because the two might overlap. */
7903 int dest_start = REGNO (operands[0]);
7904 int src_start = REGNO (operands[1]);
7905 rtx ops[2];
7906 int i;
7908 if (dest_start < src_start)
7910 for (i = 0; i < 3; i++)
7912 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7913 ops[1] = gen_rtx_REG (SImode, src_start + i);
7914 output_asm_insn ("mov%?\t%0, %1", ops);
7917 else
7919 for (i = 2; i >= 0; i--)
7921 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7922 ops[1] = gen_rtx_REG (SImode, src_start + i);
7923 output_asm_insn ("mov%?\t%0, %1", ops);
7927 return "";
7931 /* Output a move from arm registers to an fpa registers.
7932 OPERANDS[0] is an fpa register.
7933 OPERANDS[1] is the first registers of an arm register pair. */
7934 const char *
7935 output_mov_double_fpa_from_arm (rtx *operands)
7937 int arm_reg0 = REGNO (operands[1]);
7938 rtx ops[2];
7940 if (arm_reg0 == IP_REGNUM)
7941 abort ();
7943 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7944 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7945 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7946 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7947 return "";
7950 /* Output a move from an fpa register to arm registers.
7951 OPERANDS[0] is the first registers of an arm register pair.
7952 OPERANDS[1] is an fpa register. */
7953 const char *
7954 output_mov_double_arm_from_fpa (rtx *operands)
7956 int arm_reg0 = REGNO (operands[0]);
7957 rtx ops[2];
7959 if (arm_reg0 == IP_REGNUM)
7960 abort ();
7962 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7963 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7964 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7965 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7966 return "";
7969 /* Output a move between double words.
7970 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7971 or MEM<-REG and all MEMs must be offsettable addresses. */
7972 const char *
7973 output_move_double (rtx *operands)
7975 enum rtx_code code0 = GET_CODE (operands[0]);
7976 enum rtx_code code1 = GET_CODE (operands[1]);
7977 rtx otherops[3];
7979 if (code0 == REG)
7981 int reg0 = REGNO (operands[0]);
7983 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7985 if (code1 == REG)
7987 int reg1 = REGNO (operands[1]);
7988 if (reg1 == IP_REGNUM)
7989 abort ();
7991 /* Ensure the second source is not overwritten. */
7992 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7993 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7994 else
7995 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7997 else if (code1 == CONST_VECTOR)
7999 HOST_WIDE_INT hint = 0;
8001 switch (GET_MODE (operands[1]))
8003 case V2SImode:
8004 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8005 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8006 break;
8008 case V4HImode:
8009 if (BYTES_BIG_ENDIAN)
8011 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8012 hint <<= 16;
8013 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8015 else
8017 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8018 hint <<= 16;
8019 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8022 otherops[1] = GEN_INT (hint);
8023 hint = 0;
8025 if (BYTES_BIG_ENDIAN)
8027 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8028 hint <<= 16;
8029 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8031 else
8033 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8034 hint <<= 16;
8035 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8038 operands[1] = GEN_INT (hint);
8039 break;
8041 case V8QImode:
8042 if (BYTES_BIG_ENDIAN)
8044 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8045 hint <<= 8;
8046 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8047 hint <<= 8;
8048 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8049 hint <<= 8;
8050 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8052 else
8054 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8055 hint <<= 8;
8056 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8057 hint <<= 8;
8058 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8059 hint <<= 8;
8060 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8063 otherops[1] = GEN_INT (hint);
8064 hint = 0;
8066 if (BYTES_BIG_ENDIAN)
8068 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8069 hint <<= 8;
8070 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8071 hint <<= 8;
8072 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8073 hint <<= 8;
8074 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8076 else
8078 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8079 hint <<= 8;
8080 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8081 hint <<= 8;
8082 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8083 hint <<= 8;
8084 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8087 operands[1] = GEN_INT (hint);
8088 break;
8090 default:
8091 abort ();
8093 output_mov_immediate (operands);
8094 output_mov_immediate (otherops);
8096 else if (code1 == CONST_DOUBLE)
8098 if (GET_MODE (operands[1]) == DFmode)
8100 REAL_VALUE_TYPE r;
8101 long l[2];
8103 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8104 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8105 otherops[1] = GEN_INT (l[1]);
8106 operands[1] = GEN_INT (l[0]);
8108 else if (GET_MODE (operands[1]) != VOIDmode)
8109 abort ();
8110 else if (WORDS_BIG_ENDIAN)
8112 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8113 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8115 else
8117 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8118 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8121 output_mov_immediate (operands);
8122 output_mov_immediate (otherops);
8124 else if (code1 == CONST_INT)
8126 #if HOST_BITS_PER_WIDE_INT > 32
8127 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8128 what the upper word is. */
8129 if (WORDS_BIG_ENDIAN)
8131 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8132 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8134 else
8136 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8137 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8139 #else
8140 /* Sign extend the intval into the high-order word. */
8141 if (WORDS_BIG_ENDIAN)
8143 otherops[1] = operands[1];
8144 operands[1] = (INTVAL (operands[1]) < 0
8145 ? constm1_rtx : const0_rtx);
8147 else
8148 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8149 #endif
8150 output_mov_immediate (otherops);
8151 output_mov_immediate (operands);
8153 else if (code1 == MEM)
8155 switch (GET_CODE (XEXP (operands[1], 0)))
8157 case REG:
8158 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8159 break;
8161 case PRE_INC:
8162 abort (); /* Should never happen now. */
8163 break;
8165 case PRE_DEC:
8166 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8167 break;
8169 case POST_INC:
8170 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8171 break;
8173 case POST_DEC:
8174 abort (); /* Should never happen now. */
8175 break;
8177 case LABEL_REF:
8178 case CONST:
8179 output_asm_insn ("adr%?\t%0, %1", operands);
8180 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8181 break;
8183 default:
8184 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8185 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8187 otherops[0] = operands[0];
8188 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8189 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8191 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8193 if (GET_CODE (otherops[2]) == CONST_INT)
8195 switch ((int) INTVAL (otherops[2]))
8197 case -8:
8198 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8199 return "";
8200 case -4:
8201 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8202 return "";
8203 case 4:
8204 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8205 return "";
8208 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8209 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8210 else
8211 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8213 else
8214 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8216 else
8217 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8219 return "ldm%?ia\t%0, %M0";
8221 else
8223 otherops[1] = adjust_address (operands[1], SImode, 4);
8224 /* Take care of overlapping base/data reg. */
8225 if (reg_mentioned_p (operands[0], operands[1]))
8227 output_asm_insn ("ldr%?\t%0, %1", otherops);
8228 output_asm_insn ("ldr%?\t%0, %1", operands);
8230 else
8232 output_asm_insn ("ldr%?\t%0, %1", operands);
8233 output_asm_insn ("ldr%?\t%0, %1", otherops);
8238 else
8239 abort (); /* Constraints should prevent this. */
8241 else if (code0 == MEM && code1 == REG)
8243 if (REGNO (operands[1]) == IP_REGNUM)
8244 abort ();
8246 switch (GET_CODE (XEXP (operands[0], 0)))
8248 case REG:
8249 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8250 break;
8252 case PRE_INC:
8253 abort (); /* Should never happen now. */
8254 break;
8256 case PRE_DEC:
8257 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8258 break;
8260 case POST_INC:
8261 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8262 break;
8264 case POST_DEC:
8265 abort (); /* Should never happen now. */
8266 break;
8268 case PLUS:
8269 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
8271 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8273 case -8:
8274 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8275 return "";
8277 case -4:
8278 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8279 return "";
8281 case 4:
8282 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8283 return "";
8286 /* Fall through */
8288 default:
8289 otherops[0] = adjust_address (operands[0], SImode, 4);
8290 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8291 output_asm_insn ("str%?\t%1, %0", operands);
8292 output_asm_insn ("str%?\t%1, %0", otherops);
8295 else
8296 /* Constraints should prevent this. */
8297 abort ();
8299 return "";
8303 /* Output an arbitrary MOV reg, #n.
8304 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8305 const char *
8306 output_mov_immediate (rtx *operands)
8308 HOST_WIDE_INT n = INTVAL (operands[1]);
8310 /* Try to use one MOV. */
8311 if (const_ok_for_arm (n))
8312 output_asm_insn ("mov%?\t%0, %1", operands);
8314 /* Try to use one MVN. */
8315 else if (const_ok_for_arm (~n))
8317 operands[1] = GEN_INT (~n);
8318 output_asm_insn ("mvn%?\t%0, %1", operands);
8320 else
8322 int n_ones = 0;
8323 int i;
8325 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8326 for (i = 0; i < 32; i++)
8327 if (n & 1 << i)
8328 n_ones++;
8330 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8331 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8332 else
8333 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8336 return "";
8339 /* Output an ADD r, s, #n where n may be too big for one instruction.
8340 If adding zero to one register, output nothing. */
8341 const char *
8342 output_add_immediate (rtx *operands)
8344 HOST_WIDE_INT n = INTVAL (operands[2]);
8346 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8348 if (n < 0)
8349 output_multi_immediate (operands,
8350 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8351 -n);
8352 else
8353 output_multi_immediate (operands,
8354 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8358 return "";
8361 /* Output a multiple immediate operation.
8362 OPERANDS is the vector of operands referred to in the output patterns.
8363 INSTR1 is the output pattern to use for the first constant.
8364 INSTR2 is the output pattern to use for subsequent constants.
8365 IMMED_OP is the index of the constant slot in OPERANDS.
8366 N is the constant value. */
8367 static const char *
8368 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8369 int immed_op, HOST_WIDE_INT n)
8371 #if HOST_BITS_PER_WIDE_INT > 32
8372 n &= 0xffffffff;
8373 #endif
8375 if (n == 0)
8377 /* Quick and easy output. */
8378 operands[immed_op] = const0_rtx;
8379 output_asm_insn (instr1, operands);
8381 else
8383 int i;
8384 const char * instr = instr1;
8386 /* Note that n is never zero here (which would give no output). */
8387 for (i = 0; i < 32; i += 2)
8389 if (n & (3 << i))
8391 operands[immed_op] = GEN_INT (n & (255 << i));
8392 output_asm_insn (instr, operands);
8393 instr = instr2;
8394 i += 6;
8399 return "";
8402 /* Return the appropriate ARM instruction for the operation code.
8403 The returned result should not be overwritten. OP is the rtx of the
8404 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8405 was shifted. */
8406 const char *
8407 arithmetic_instr (rtx op, int shift_first_arg)
8409 switch (GET_CODE (op))
8411 case PLUS:
8412 return "add";
8414 case MINUS:
8415 return shift_first_arg ? "rsb" : "sub";
8417 case IOR:
8418 return "orr";
8420 case XOR:
8421 return "eor";
8423 case AND:
8424 return "and";
8426 default:
8427 abort ();
8431 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8432 for the operation code. The returned result should not be overwritten.
8433 OP is the rtx code of the shift.
8434 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8435 shift. */
8436 static const char *
8437 shift_op (rtx op, HOST_WIDE_INT *amountp)
8439 const char * mnem;
8440 enum rtx_code code = GET_CODE (op);
8442 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8443 *amountp = -1;
8444 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8445 *amountp = INTVAL (XEXP (op, 1));
8446 else
8447 abort ();
8449 switch (code)
8451 case ASHIFT:
8452 mnem = "asl";
8453 break;
8455 case ASHIFTRT:
8456 mnem = "asr";
8457 break;
8459 case LSHIFTRT:
8460 mnem = "lsr";
8461 break;
8463 case ROTATERT:
8464 mnem = "ror";
8465 break;
8467 case MULT:
8468 /* We never have to worry about the amount being other than a
8469 power of 2, since this case can never be reloaded from a reg. */
8470 if (*amountp != -1)
8471 *amountp = int_log2 (*amountp);
8472 else
8473 abort ();
8474 return "asl";
8476 default:
8477 abort ();
8480 if (*amountp != -1)
8482 /* This is not 100% correct, but follows from the desire to merge
8483 multiplication by a power of 2 with the recognizer for a
8484 shift. >=32 is not a valid shift for "asl", so we must try and
8485 output a shift that produces the correct arithmetical result.
8486 Using lsr #32 is identical except for the fact that the carry bit
8487 is not set correctly if we set the flags; but we never use the
8488 carry bit from such an operation, so we can ignore that. */
8489 if (code == ROTATERT)
8490 /* Rotate is just modulo 32. */
8491 *amountp &= 31;
8492 else if (*amountp != (*amountp & 31))
8494 if (code == ASHIFT)
8495 mnem = "lsr";
8496 *amountp = 32;
8499 /* Shifts of 0 are no-ops. */
8500 if (*amountp == 0)
8501 return NULL;
8504 return mnem;
8507 /* Obtain the shift from the POWER of two. */
8509 static HOST_WIDE_INT
8510 int_log2 (HOST_WIDE_INT power)
8512 HOST_WIDE_INT shift = 0;
8514 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8516 if (shift > 31)
8517 abort ();
8518 shift++;
8521 return shift;
8524 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8525 /bin/as is horribly restrictive. */
8526 #define MAX_ASCII_LEN 51
8528 void
8529 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8531 int i;
8532 int len_so_far = 0;
8534 fputs ("\t.ascii\t\"", stream);
8536 for (i = 0; i < len; i++)
8538 int c = p[i];
8540 if (len_so_far >= MAX_ASCII_LEN)
8542 fputs ("\"\n\t.ascii\t\"", stream);
8543 len_so_far = 0;
8546 switch (c)
8548 case TARGET_TAB:
8549 fputs ("\\t", stream);
8550 len_so_far += 2;
8551 break;
8553 case TARGET_FF:
8554 fputs ("\\f", stream);
8555 len_so_far += 2;
8556 break;
8558 case TARGET_BS:
8559 fputs ("\\b", stream);
8560 len_so_far += 2;
8561 break;
8563 case TARGET_CR:
8564 fputs ("\\r", stream);
8565 len_so_far += 2;
8566 break;
8568 case TARGET_NEWLINE:
8569 fputs ("\\n", stream);
8570 c = p [i + 1];
8571 if ((c >= ' ' && c <= '~')
8572 || c == TARGET_TAB)
8573 /* This is a good place for a line break. */
8574 len_so_far = MAX_ASCII_LEN;
8575 else
8576 len_so_far += 2;
8577 break;
8579 case '\"':
8580 case '\\':
8581 putc ('\\', stream);
8582 len_so_far++;
8583 /* Drop through. */
8585 default:
8586 if (c >= ' ' && c <= '~')
8588 putc (c, stream);
8589 len_so_far++;
8591 else
8593 fprintf (stream, "\\%03o", c);
8594 len_so_far += 4;
8596 break;
8600 fputs ("\"\n", stream);
8603 /* Compute the register sabe mask for registers 0 through 12
8604 inclusive. This code is used by both arm_compute_save_reg_mask
8605 and arm_compute_initial_elimination_offset. */
8606 static unsigned long
8607 arm_compute_save_reg0_reg12_mask (void)
8609 unsigned long func_type = arm_current_func_type ();
8610 unsigned int save_reg_mask = 0;
8611 unsigned int reg;
8613 if (IS_INTERRUPT (func_type))
8615 unsigned int max_reg;
8616 /* Interrupt functions must not corrupt any registers,
8617 even call clobbered ones. If this is a leaf function
8618 we can just examine the registers used by the RTL, but
8619 otherwise we have to assume that whatever function is
8620 called might clobber anything, and so we have to save
8621 all the call-clobbered registers as well. */
8622 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8623 /* FIQ handlers have registers r8 - r12 banked, so
8624 we only need to check r0 - r7, Normal ISRs only
8625 bank r14 and r15, so we must check up to r12.
8626 r13 is the stack pointer which is always preserved,
8627 so we do not need to consider it here. */
8628 max_reg = 7;
8629 else
8630 max_reg = 12;
8632 for (reg = 0; reg <= max_reg; reg++)
8633 if (regs_ever_live[reg]
8634 || (! current_function_is_leaf && call_used_regs [reg]))
8635 save_reg_mask |= (1 << reg);
8637 else
8639 /* In the normal case we only need to save those registers
8640 which are call saved and which are used by this function. */
8641 for (reg = 0; reg <= 10; reg++)
8642 if (regs_ever_live[reg] && ! call_used_regs [reg])
8643 save_reg_mask |= (1 << reg);
8645 /* Handle the frame pointer as a special case. */
8646 if (! TARGET_APCS_FRAME
8647 && ! frame_pointer_needed
8648 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8649 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8650 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8652 /* If we aren't loading the PIC register,
8653 don't stack it even though it may be live. */
8654 if (flag_pic
8655 && ! TARGET_SINGLE_PIC_BASE
8656 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8657 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8660 return save_reg_mask;
8663 /* Compute a bit mask of which registers need to be
8664 saved on the stack for the current function. */
8666 static unsigned long
8667 arm_compute_save_reg_mask (void)
8669 unsigned int save_reg_mask = 0;
8670 unsigned long func_type = arm_current_func_type ();
8672 if (IS_NAKED (func_type))
8673 /* This should never really happen. */
8674 return 0;
8676 /* If we are creating a stack frame, then we must save the frame pointer,
8677 IP (which will hold the old stack pointer), LR and the PC. */
8678 if (frame_pointer_needed)
8679 save_reg_mask |=
8680 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8681 | (1 << IP_REGNUM)
8682 | (1 << LR_REGNUM)
8683 | (1 << PC_REGNUM);
8685 /* Volatile functions do not return, so there
8686 is no need to save any other registers. */
8687 if (IS_VOLATILE (func_type))
8688 return save_reg_mask;
8690 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8692 /* Decide if we need to save the link register.
8693 Interrupt routines have their own banked link register,
8694 so they never need to save it.
8695 Otherwise if we do not use the link register we do not need to save
8696 it. If we are pushing other registers onto the stack however, we
8697 can save an instruction in the epilogue by pushing the link register
8698 now and then popping it back into the PC. This incurs extra memory
8699 accesses though, so we only do it when optimizing for size, and only
8700 if we know that we will not need a fancy return sequence. */
8701 if (regs_ever_live [LR_REGNUM]
8702 || (save_reg_mask
8703 && optimize_size
8704 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8705 save_reg_mask |= 1 << LR_REGNUM;
8707 if (cfun->machine->lr_save_eliminated)
8708 save_reg_mask &= ~ (1 << LR_REGNUM);
8710 if (TARGET_REALLY_IWMMXT
8711 && ((bit_count (save_reg_mask)
8712 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8714 unsigned int reg;
8716 /* The total number of registers that are going to be pushed
8717 onto the stack is odd. We need to ensure that the stack
8718 is 64-bit aligned before we start to save iWMMXt registers,
8719 and also before we start to create locals. (A local variable
8720 might be a double or long long which we will load/store using
8721 an iWMMXt instruction). Therefore we need to push another
8722 ARM register, so that the stack will be 64-bit aligned. We
8723 try to avoid using the arg registers (r0 -r3) as they might be
8724 used to pass values in a tail call. */
8725 for (reg = 4; reg <= 12; reg++)
8726 if ((save_reg_mask & (1 << reg)) == 0)
8727 break;
8729 if (reg <= 12)
8730 save_reg_mask |= (1 << reg);
8731 else
8733 cfun->machine->sibcall_blocked = 1;
8734 save_reg_mask |= (1 << 3);
8738 return save_reg_mask;
8741 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8742 everything bar the final return instruction. */
8743 const char *
8744 output_return_instruction (rtx operand, int really_return, int reverse)
8746 char conditional[10];
8747 char instr[100];
8748 int reg;
8749 unsigned long live_regs_mask;
8750 unsigned long func_type;
8752 func_type = arm_current_func_type ();
8754 if (IS_NAKED (func_type))
8755 return "";
8757 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8759 /* If this function was declared non-returning, and we have
8760 found a tail call, then we have to trust that the called
8761 function won't return. */
8762 if (really_return)
8764 rtx ops[2];
8766 /* Otherwise, trap an attempted return by aborting. */
8767 ops[0] = operand;
8768 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8769 : "abort");
8770 assemble_external_libcall (ops[1]);
8771 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8774 return "";
8777 if (current_function_calls_alloca && !really_return)
8778 abort ();
8780 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8782 return_used_this_function = 1;
8784 live_regs_mask = arm_compute_save_reg_mask ();
8786 if (live_regs_mask)
8788 const char * return_reg;
8790 /* If we do not have any special requirements for function exit
8791 (eg interworking, or ISR) then we can load the return address
8792 directly into the PC. Otherwise we must load it into LR. */
8793 if (really_return
8794 && ! TARGET_INTERWORK)
8795 return_reg = reg_names[PC_REGNUM];
8796 else
8797 return_reg = reg_names[LR_REGNUM];
8799 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8801 /* There are three possible reasons for the IP register
8802 being saved. 1) a stack frame was created, in which case
8803 IP contains the old stack pointer, or 2) an ISR routine
8804 corrupted it, or 3) it was saved to align the stack on
8805 iWMMXt. In case 1, restore IP into SP, otherwise just
8806 restore IP. */
8807 if (frame_pointer_needed)
8809 live_regs_mask &= ~ (1 << IP_REGNUM);
8810 live_regs_mask |= (1 << SP_REGNUM);
8812 else
8814 if (! IS_INTERRUPT (func_type)
8815 && ! TARGET_REALLY_IWMMXT)
8816 abort ();
8820 /* On some ARM architectures it is faster to use LDR rather than
8821 LDM to load a single register. On other architectures, the
8822 cost is the same. In 26 bit mode, or for exception handlers,
8823 we have to use LDM to load the PC so that the CPSR is also
8824 restored. */
8825 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8827 if (live_regs_mask == (unsigned int)(1 << reg))
8828 break;
8830 if (reg <= LAST_ARM_REGNUM
8831 && (reg != LR_REGNUM
8832 || ! really_return
8833 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8835 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8836 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8838 else
8840 char *p;
8841 int first = 1;
8843 /* Generate the load multiple instruction to restore the
8844 registers. Note we can get here, even if
8845 frame_pointer_needed is true, but only if sp already
8846 points to the base of the saved core registers. */
8847 if (live_regs_mask & (1 << SP_REGNUM))
8849 unsigned HOST_WIDE_INT stack_adjust =
8850 arm_get_frame_size () + current_function_outgoing_args_size;
8852 if (stack_adjust != 0 && stack_adjust != 4)
8853 abort ();
8855 if (stack_adjust && arm_arch5)
8856 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
8857 else
8859 /* If we can't use ldmib (SA110 bug), then try to pop r3
8860 instead. */
8861 if (stack_adjust)
8862 live_regs_mask |= 1 << 3;
8863 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8866 else
8867 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8869 p = instr + strlen (instr);
8871 for (reg = 0; reg <= SP_REGNUM; reg++)
8872 if (live_regs_mask & (1 << reg))
8874 int l = strlen (reg_names[reg]);
8876 if (first)
8877 first = 0;
8878 else
8880 memcpy (p, ", ", 2);
8881 p += 2;
8884 memcpy (p, "%|", 2);
8885 memcpy (p + 2, reg_names[reg], l);
8886 p += l + 2;
8889 if (live_regs_mask & (1 << LR_REGNUM))
8891 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8892 /* Decide if we need to add the ^ symbol to the end of the
8893 register list. This causes the saved condition codes
8894 register to be copied into the current condition codes
8895 register. We do the copy if we are conforming to the 32-bit
8896 ABI and this is an interrupt function, or if we are
8897 conforming to the 26-bit ABI. There is a special case for
8898 the 26-bit ABI however, which is if we are writing back the
8899 stack pointer but not loading the PC. In this case adding
8900 the ^ symbol would create a type 2 LDM instruction, where
8901 writeback is UNPREDICTABLE. We are safe in leaving the ^
8902 character off in this case however, since the actual return
8903 instruction will be a MOVS which will restore the CPSR. */
8904 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
8905 || (! TARGET_APCS_32 && really_return))
8906 strcat (p, "^");
8908 else
8909 strcpy (p, "}");
8912 output_asm_insn (instr, & operand);
8914 /* See if we need to generate an extra instruction to
8915 perform the actual function return. */
8916 if (really_return
8917 && func_type != ARM_FT_INTERWORKED
8918 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8920 /* The return has already been handled
8921 by loading the LR into the PC. */
8922 really_return = 0;
8926 if (really_return)
8928 switch ((int) ARM_FUNC_TYPE (func_type))
8930 case ARM_FT_ISR:
8931 case ARM_FT_FIQ:
8932 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8933 break;
8935 case ARM_FT_INTERWORKED:
8936 sprintf (instr, "bx%s\t%%|lr", conditional);
8937 break;
8939 case ARM_FT_EXCEPTION:
8940 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8941 break;
8943 default:
8944 /* ARMv5 implementations always provide BX, so interworking
8945 is the default unless APCS-26 is in use. */
8946 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8947 sprintf (instr, "bx%s\t%%|lr", conditional);
8948 else
8949 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8950 conditional, TARGET_APCS_32 ? "" : "s");
8951 break;
8954 output_asm_insn (instr, & operand);
8957 return "";
8960 /* Write the function name into the code section, directly preceding
8961 the function prologue.
8963 Code will be output similar to this:
8965 .ascii "arm_poke_function_name", 0
8966 .align
8968 .word 0xff000000 + (t1 - t0)
8969 arm_poke_function_name
8970 mov ip, sp
8971 stmfd sp!, {fp, ip, lr, pc}
8972 sub fp, ip, #4
8974 When performing a stack backtrace, code can inspect the value
8975 of 'pc' stored at 'fp' + 0. If the trace function then looks
8976 at location pc - 12 and the top 8 bits are set, then we know
8977 that there is a function name embedded immediately preceding this
8978 location and has length ((pc[-3]) & 0xff000000).
8980 We assume that pc is declared as a pointer to an unsigned long.
8982 It is of no benefit to output the function name if we are assembling
8983 a leaf function. These function types will not contain a stack
8984 backtrace structure, therefore it is not possible to determine the
8985 function name. */
8986 void
8987 arm_poke_function_name (FILE *stream, const char *name)
8989 unsigned long alignlength;
8990 unsigned long length;
8991 rtx x;
8993 length = strlen (name) + 1;
8994 alignlength = ROUND_UP_WORD (length);
8996 ASM_OUTPUT_ASCII (stream, name, length);
8997 ASM_OUTPUT_ALIGN (stream, 2);
8998 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8999 assemble_aligned_integer (UNITS_PER_WORD, x);
9002 /* Place some comments into the assembler stream
9003 describing the current function. */
9004 static void
9005 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9007 unsigned long func_type;
9009 if (!TARGET_ARM)
9011 thumb_output_function_prologue (f, frame_size);
9012 return;
9015 /* Sanity check. */
9016 if (arm_ccfsm_state || arm_target_insn)
9017 abort ();
9019 func_type = arm_current_func_type ();
9021 switch ((int) ARM_FUNC_TYPE (func_type))
9023 default:
9024 case ARM_FT_NORMAL:
9025 break;
9026 case ARM_FT_INTERWORKED:
9027 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9028 break;
9029 case ARM_FT_EXCEPTION_HANDLER:
9030 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9031 break;
9032 case ARM_FT_ISR:
9033 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9034 break;
9035 case ARM_FT_FIQ:
9036 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9037 break;
9038 case ARM_FT_EXCEPTION:
9039 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9040 break;
9043 if (IS_NAKED (func_type))
9044 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9046 if (IS_VOLATILE (func_type))
9047 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9049 if (IS_NESTED (func_type))
9050 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9052 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9053 current_function_args_size,
9054 current_function_pretend_args_size, frame_size);
9056 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9057 frame_pointer_needed,
9058 cfun->machine->uses_anonymous_args);
9060 if (cfun->machine->lr_save_eliminated)
9061 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9063 #ifdef AOF_ASSEMBLER
9064 if (flag_pic)
9065 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9066 #endif
9068 return_used_this_function = 0;
9071 const char *
9072 arm_output_epilogue (rtx sibling)
9074 int reg;
9075 unsigned long saved_regs_mask;
9076 unsigned long func_type;
9077 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9078 frame that is $fp + 4 for a non-variadic function. */
9079 int floats_offset = 0;
9080 rtx operands[3];
9081 int frame_size = arm_get_frame_size ();
9082 FILE * f = asm_out_file;
9083 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9084 unsigned int lrm_count = 0;
9085 int really_return = (sibling == NULL);
9086 int start_reg;
9088 /* If we have already generated the return instruction
9089 then it is futile to generate anything else. */
9090 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9091 return "";
9093 func_type = arm_current_func_type ();
9095 if (IS_NAKED (func_type))
9096 /* Naked functions don't have epilogues. */
9097 return "";
9099 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9101 rtx op;
9103 /* A volatile function should never return. Call abort. */
9104 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9105 assemble_external_libcall (op);
9106 output_asm_insn ("bl\t%a0", &op);
9108 return "";
9111 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9112 && ! really_return)
9113 /* If we are throwing an exception, then we really must
9114 be doing a return, so we can't tail-call. */
9115 abort ();
9117 saved_regs_mask = arm_compute_save_reg_mask ();
9119 if (TARGET_IWMMXT)
9120 lrm_count = bit_count (saved_regs_mask);
9122 /* XXX We should adjust floats_offset for any anonymous args, and then
9123 re-adjust vfp_offset below to compensate. */
9125 /* Compute how far away the floats will be. */
9126 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9127 if (saved_regs_mask & (1 << reg))
9128 floats_offset += 4;
9130 if (frame_pointer_needed)
9132 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9133 int vfp_offset = 4;
9135 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9137 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9138 if (regs_ever_live[reg] && !call_used_regs[reg])
9140 floats_offset += 12;
9141 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9142 reg, FP_REGNUM, floats_offset - vfp_offset);
9145 else
9147 start_reg = LAST_FPA_REGNUM;
9149 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9151 if (regs_ever_live[reg] && !call_used_regs[reg])
9153 floats_offset += 12;
9155 /* We can't unstack more than four registers at once. */
9156 if (start_reg - reg == 3)
9158 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9159 reg, FP_REGNUM, floats_offset - vfp_offset);
9160 start_reg = reg - 1;
9163 else
9165 if (reg != start_reg)
9166 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9167 reg + 1, start_reg - reg,
9168 FP_REGNUM, floats_offset - vfp_offset);
9169 start_reg = reg - 1;
9173 /* Just in case the last register checked also needs unstacking. */
9174 if (reg != start_reg)
9175 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9176 reg + 1, start_reg - reg,
9177 FP_REGNUM, floats_offset - vfp_offset);
9180 if (TARGET_HARD_FLOAT && TARGET_VFP)
9182 int nregs = 0;
9184 /* We save regs in pairs. */
9185 /* A special insn for saving/restoring VFP registers. This does
9186 not have base+offset addressing modes, so we use IP to
9187 hold the address. Each block requires nregs*2+1 words. */
9188 start_reg = FIRST_VFP_REGNUM;
9189 /* Count how many blocks of registers need saving. */
9190 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9192 if ((!regs_ever_live[reg] || call_used_regs[reg])
9193 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9195 if (start_reg != reg)
9196 floats_offset += 4;
9197 start_reg = reg + 2;
9199 else
9201 floats_offset += 8;
9202 nregs++;
9205 if (start_reg != reg)
9206 floats_offset += 4;
9208 if (nregs > 0)
9210 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9211 FP_REGNUM, floats_offset - vfp_offset);
9213 start_reg = FIRST_VFP_REGNUM;
9214 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9216 if ((!regs_ever_live[reg] || call_used_regs[reg])
9217 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9219 if (start_reg != reg)
9221 vfp_print_multi (f, "fldmfdx\t%r!", IP_REGNUM, "d%d",
9222 (start_reg - FIRST_VFP_REGNUM) / 2,
9223 (reg - start_reg) / 2);
9225 start_reg = reg + 2;
9228 if (start_reg != reg)
9230 vfp_print_multi (f, "fldmfdx\t%r!", IP_REGNUM, "d%d",
9231 (start_reg - FIRST_VFP_REGNUM) / 2,
9232 (reg - start_reg) / 2);
9236 if (TARGET_IWMMXT)
9238 /* The frame pointer is guaranteed to be non-double-word aligned.
9239 This is because it is set to (old_stack_pointer - 4) and the
9240 old_stack_pointer was double word aligned. Thus the offset to
9241 the iWMMXt registers to be loaded must also be non-double-word
9242 sized, so that the resultant address *is* double-word aligned.
9243 We can ignore floats_offset since that was already included in
9244 the live_regs_mask. */
9245 lrm_count += (lrm_count % 2 ? 2 : 1);
9247 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9248 if (regs_ever_live[reg] && !call_used_regs[reg])
9250 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9251 reg, FP_REGNUM, lrm_count * 4);
9252 lrm_count += 2;
9256 /* saved_regs_mask should contain the IP, which at the time of stack
9257 frame generation actually contains the old stack pointer. So a
9258 quick way to unwind the stack is just pop the IP register directly
9259 into the stack pointer. */
9260 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9261 abort ();
9262 saved_regs_mask &= ~ (1 << IP_REGNUM);
9263 saved_regs_mask |= (1 << SP_REGNUM);
9265 /* There are two registers left in saved_regs_mask - LR and PC. We
9266 only need to restore the LR register (the return address), but to
9267 save time we can load it directly into the PC, unless we need a
9268 special function exit sequence, or we are not really returning. */
9269 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9270 /* Delete the LR from the register mask, so that the LR on
9271 the stack is loaded into the PC in the register mask. */
9272 saved_regs_mask &= ~ (1 << LR_REGNUM);
9273 else
9274 saved_regs_mask &= ~ (1 << PC_REGNUM);
9276 /* We must use SP as the base register, because SP is one of the
9277 registers being restored. If an interrupt or page fault
9278 happens in the ldm instruction, the SP might or might not
9279 have been restored. That would be bad, as then SP will no
9280 longer indicate the safe area of stack, and we can get stack
9281 corruption. Using SP as the base register means that it will
9282 be reset correctly to the original value, should an interrupt
9283 occur. If the stack pointer already points at the right
9284 place, then omit the subtraction. */
9285 if (((frame_size + current_function_outgoing_args_size + floats_offset)
9286 != 4 * (1 + (int) bit_count (saved_regs_mask)))
9287 || current_function_calls_alloca)
9288 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9289 4 * bit_count (saved_regs_mask));
9290 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9292 if (IS_INTERRUPT (func_type))
9293 /* Interrupt handlers will have pushed the
9294 IP onto the stack, so restore it now. */
9295 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9297 else
9299 /* Restore stack pointer if necessary. */
9300 if (frame_size + current_function_outgoing_args_size != 0)
9302 operands[0] = operands[1] = stack_pointer_rtx;
9303 operands[2] = GEN_INT (frame_size
9304 + current_function_outgoing_args_size);
9305 output_add_immediate (operands);
9308 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9310 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9311 if (regs_ever_live[reg] && !call_used_regs[reg])
9312 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9313 reg, SP_REGNUM);
9315 else
9317 start_reg = FIRST_FPA_REGNUM;
9319 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9321 if (regs_ever_live[reg] && !call_used_regs[reg])
9323 if (reg - start_reg == 3)
9325 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9326 start_reg, SP_REGNUM);
9327 start_reg = reg + 1;
9330 else
9332 if (reg != start_reg)
9333 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9334 start_reg, reg - start_reg,
9335 SP_REGNUM);
9337 start_reg = reg + 1;
9341 /* Just in case the last register checked also needs unstacking. */
9342 if (reg != start_reg)
9343 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9344 start_reg, reg - start_reg, SP_REGNUM);
9347 if (TARGET_HARD_FLOAT && TARGET_VFP)
9349 start_reg = FIRST_VFP_REGNUM;
9350 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9352 if ((!regs_ever_live[reg] || call_used_regs[reg])
9353 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9355 if (start_reg != reg)
9357 vfp_print_multi (f, "fldmfdx\t%r!", SP_REGNUM, "d%d",
9358 (start_reg - FIRST_VFP_REGNUM) / 2,
9359 (reg - start_reg) / 2);
9361 start_reg = reg + 2;
9364 if (start_reg != reg)
9366 vfp_print_multi (f, "fldmfdx\t%r!", SP_REGNUM, "d%d",
9367 (start_reg - FIRST_VFP_REGNUM) / 2,
9368 (reg - start_reg) / 2);
9371 if (TARGET_IWMMXT)
9372 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9373 if (regs_ever_live[reg] && !call_used_regs[reg])
9374 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
9376 /* If we can, restore the LR into the PC. */
9377 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9378 && really_return
9379 && current_function_pretend_args_size == 0
9380 && saved_regs_mask & (1 << LR_REGNUM))
9382 saved_regs_mask &= ~ (1 << LR_REGNUM);
9383 saved_regs_mask |= (1 << PC_REGNUM);
9386 /* Load the registers off the stack. If we only have one register
9387 to load use the LDR instruction - it is faster. */
9388 if (saved_regs_mask == (1 << LR_REGNUM))
9390 /* The exception handler ignores the LR, so we do
9391 not really need to load it off the stack. */
9392 if (eh_ofs)
9393 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9394 else
9395 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9397 else if (saved_regs_mask)
9399 if (saved_regs_mask & (1 << SP_REGNUM))
9400 /* Note - write back to the stack register is not enabled
9401 (ie "ldmfd sp!..."). We know that the stack pointer is
9402 in the list of registers and if we add writeback the
9403 instruction becomes UNPREDICTABLE. */
9404 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9405 else
9406 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9409 if (current_function_pretend_args_size)
9411 /* Unwind the pre-pushed regs. */
9412 operands[0] = operands[1] = stack_pointer_rtx;
9413 operands[2] = GEN_INT (current_function_pretend_args_size);
9414 output_add_immediate (operands);
9418 if (! really_return
9419 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9420 && current_function_pretend_args_size == 0
9421 && saved_regs_mask & (1 << PC_REGNUM)))
9422 return "";
9424 /* Generate the return instruction. */
9425 switch ((int) ARM_FUNC_TYPE (func_type))
9427 case ARM_FT_EXCEPTION_HANDLER:
9428 /* Even in 26-bit mode we do a mov (rather than a movs)
9429 because we don't have the PSR bits set in the address. */
9430 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9431 break;
9433 case ARM_FT_ISR:
9434 case ARM_FT_FIQ:
9435 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9436 break;
9438 case ARM_FT_EXCEPTION:
9439 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9440 break;
9442 case ARM_FT_INTERWORKED:
9443 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9444 break;
9446 default:
9447 if (frame_pointer_needed)
9448 /* If we used the frame pointer then the return address
9449 will have been loaded off the stack directly into the
9450 PC, so there is no need to issue a MOV instruction
9451 here. */
9453 else if (current_function_pretend_args_size == 0
9454 && (saved_regs_mask & (1 << LR_REGNUM)))
9455 /* Similarly we may have been able to load LR into the PC
9456 even if we did not create a stack frame. */
9458 else if (TARGET_APCS_32)
9459 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9460 else
9461 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9462 break;
9465 return "";
9468 static void
9469 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9470 HOST_WIDE_INT frame_size)
9472 if (TARGET_THUMB)
9474 /* ??? Probably not safe to set this here, since it assumes that a
9475 function will be emitted as assembly immediately after we generate
9476 RTL for it. This does not happen for inline functions. */
9477 return_used_this_function = 0;
9479 else
9481 /* We need to take into account any stack-frame rounding. */
9482 frame_size = arm_get_frame_size ();
9484 if (use_return_insn (FALSE, NULL)
9485 && return_used_this_function
9486 && (frame_size + current_function_outgoing_args_size) != 0
9487 && !frame_pointer_needed)
9488 abort ();
9490 /* Reset the ARM-specific per-function variables. */
9491 after_arm_reorg = 0;
9495 /* Generate and emit an insn that we will recognize as a push_multi.
9496 Unfortunately, since this insn does not reflect very well the actual
9497 semantics of the operation, we need to annotate the insn for the benefit
9498 of DWARF2 frame unwind information. */
9499 static rtx
9500 emit_multi_reg_push (int mask)
9502 int num_regs = 0;
9503 int num_dwarf_regs;
9504 int i, j;
9505 rtx par;
9506 rtx dwarf;
9507 int dwarf_par_index;
9508 rtx tmp, reg;
9510 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9511 if (mask & (1 << i))
9512 num_regs++;
9514 if (num_regs == 0 || num_regs > 16)
9515 abort ();
9517 /* We don't record the PC in the dwarf frame information. */
9518 num_dwarf_regs = num_regs;
9519 if (mask & (1 << PC_REGNUM))
9520 num_dwarf_regs--;
9522 /* For the body of the insn we are going to generate an UNSPEC in
9523 parallel with several USEs. This allows the insn to be recognized
9524 by the push_multi pattern in the arm.md file. The insn looks
9525 something like this:
9527 (parallel [
9528 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9529 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9530 (use (reg:SI 11 fp))
9531 (use (reg:SI 12 ip))
9532 (use (reg:SI 14 lr))
9533 (use (reg:SI 15 pc))
9536 For the frame note however, we try to be more explicit and actually
9537 show each register being stored into the stack frame, plus a (single)
9538 decrement of the stack pointer. We do it this way in order to be
9539 friendly to the stack unwinding code, which only wants to see a single
9540 stack decrement per instruction. The RTL we generate for the note looks
9541 something like this:
9543 (sequence [
9544 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9545 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9546 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9547 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9548 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9551 This sequence is used both by the code to support stack unwinding for
9552 exceptions handlers and the code to generate dwarf2 frame debugging. */
9554 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9555 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9556 dwarf_par_index = 1;
9558 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9560 if (mask & (1 << i))
9562 reg = gen_rtx_REG (SImode, i);
9564 XVECEXP (par, 0, 0)
9565 = gen_rtx_SET (VOIDmode,
9566 gen_rtx_MEM (BLKmode,
9567 gen_rtx_PRE_DEC (BLKmode,
9568 stack_pointer_rtx)),
9569 gen_rtx_UNSPEC (BLKmode,
9570 gen_rtvec (1, reg),
9571 UNSPEC_PUSH_MULT));
9573 if (i != PC_REGNUM)
9575 tmp = gen_rtx_SET (VOIDmode,
9576 gen_rtx_MEM (SImode, stack_pointer_rtx),
9577 reg);
9578 RTX_FRAME_RELATED_P (tmp) = 1;
9579 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9580 dwarf_par_index++;
9583 break;
9587 for (j = 1, i++; j < num_regs; i++)
9589 if (mask & (1 << i))
9591 reg = gen_rtx_REG (SImode, i);
9593 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9595 if (i != PC_REGNUM)
9597 tmp = gen_rtx_SET (VOIDmode,
9598 gen_rtx_MEM (SImode,
9599 plus_constant (stack_pointer_rtx,
9600 4 * j)),
9601 reg);
9602 RTX_FRAME_RELATED_P (tmp) = 1;
9603 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9606 j++;
9610 par = emit_insn (par);
9612 tmp = gen_rtx_SET (SImode,
9613 stack_pointer_rtx,
9614 gen_rtx_PLUS (SImode,
9615 stack_pointer_rtx,
9616 GEN_INT (-4 * num_regs)));
9617 RTX_FRAME_RELATED_P (tmp) = 1;
9618 XVECEXP (dwarf, 0, 0) = tmp;
9620 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9621 REG_NOTES (par));
9622 return par;
9625 static rtx
9626 emit_sfm (int base_reg, int count)
9628 rtx par;
9629 rtx dwarf;
9630 rtx tmp, reg;
9631 int i;
9633 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9634 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9636 reg = gen_rtx_REG (XFmode, base_reg++);
9638 XVECEXP (par, 0, 0)
9639 = gen_rtx_SET (VOIDmode,
9640 gen_rtx_MEM (BLKmode,
9641 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9642 gen_rtx_UNSPEC (BLKmode,
9643 gen_rtvec (1, reg),
9644 UNSPEC_PUSH_MULT));
9646 = gen_rtx_SET (VOIDmode,
9647 gen_rtx_MEM (XFmode,
9648 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9649 reg);
9650 RTX_FRAME_RELATED_P (tmp) = 1;
9651 XVECEXP (dwarf, 0, count - 1) = tmp;
9653 for (i = 1; i < count; i++)
9655 reg = gen_rtx_REG (XFmode, base_reg++);
9656 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9658 tmp = gen_rtx_SET (VOIDmode,
9659 gen_rtx_MEM (XFmode,
9660 gen_rtx_PRE_DEC (BLKmode,
9661 stack_pointer_rtx)),
9662 reg);
9663 RTX_FRAME_RELATED_P (tmp) = 1;
9664 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9667 par = emit_insn (par);
9668 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9669 REG_NOTES (par));
9670 return par;
9674 /* Compute the distance from register FROM to register TO.
9675 These can be the arg pointer (26), the soft frame pointer (25),
9676 the stack pointer (13) or the hard frame pointer (11).
9677 Typical stack layout looks like this:
9679 old stack pointer -> | |
9680 ----
9681 | | \
9682 | | saved arguments for
9683 | | vararg functions
9684 | | /
9686 hard FP & arg pointer -> | | \
9687 | | stack
9688 | | frame
9689 | | /
9691 | | \
9692 | | call saved
9693 | | registers
9694 soft frame pointer -> | | /
9696 | | \
9697 | | local
9698 | | variables
9699 | | /
9701 | | \
9702 | | outgoing
9703 | | arguments
9704 current stack pointer -> | | /
9707 For a given function some or all of these stack components
9708 may not be needed, giving rise to the possibility of
9709 eliminating some of the registers.
9711 The values returned by this function must reflect the behavior
9712 of arm_expand_prologue() and arm_compute_save_reg_mask().
9714 The sign of the number returned reflects the direction of stack
9715 growth, so the values are positive for all eliminations except
9716 from the soft frame pointer to the hard frame pointer. */
9717 unsigned int
9718 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
9720 unsigned int local_vars = arm_get_frame_size ();
9721 unsigned int outgoing_args = current_function_outgoing_args_size;
9722 unsigned int stack_frame;
9723 unsigned int call_saved_registers;
9724 unsigned long func_type;
9726 func_type = arm_current_func_type ();
9728 /* Volatile functions never return, so there is
9729 no need to save call saved registers. */
9730 call_saved_registers = 0;
9731 if (! IS_VOLATILE (func_type))
9733 unsigned int reg_mask;
9734 unsigned int reg;
9735 bool new_block;
9737 /* Make sure that we compute which registers will be saved
9738 on the stack using the same algorithm that is used by
9739 the prologue creation code. */
9740 reg_mask = arm_compute_save_reg_mask ();
9742 /* Now count the number of bits set in save_reg_mask.
9743 If we have already counted the registers in the stack
9744 frame, do not count them again. Non call-saved registers
9745 might be saved in the call-save area of the stack, if
9746 doing so will preserve the stack's alignment. Hence we
9747 must count them here. For each set bit we need 4 bytes
9748 of stack space. */
9749 if (frame_pointer_needed)
9750 reg_mask &= 0x07ff;
9751 call_saved_registers += 4 * bit_count (reg_mask);
9753 /* If the hard floating point registers are going to be
9754 used then they must be saved on the stack as well.
9755 Each register occupies 12 bytes of stack space. */
9756 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9757 if (regs_ever_live[reg] && ! call_used_regs[reg])
9758 call_saved_registers += 12;
9760 /* Likewise VFP regs. */
9761 if (TARGET_HARD_FLOAT && TARGET_VFP)
9763 new_block = TRUE;
9764 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9766 if ((regs_ever_live[reg] && !call_used_regs[reg])
9767 || (regs_ever_live[reg + 1] && !call_used_regs[reg + 1]))
9769 if (new_block)
9771 call_saved_registers += 4;
9772 new_block = FALSE;
9774 call_saved_registers += 8;
9776 else
9777 new_block = TRUE;
9781 if (TARGET_REALLY_IWMMXT)
9782 /* Check for the call-saved iWMMXt registers. */
9783 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9784 if (regs_ever_live[reg] && ! call_used_regs [reg])
9785 call_saved_registers += 8;
9788 /* The stack frame contains 4 registers - the old frame pointer,
9789 the old stack pointer, the return address and PC of the start
9790 of the function. */
9791 stack_frame = frame_pointer_needed ? 16 : 0;
9793 /* OK, now we have enough information to compute the distances.
9794 There must be an entry in these switch tables for each pair
9795 of registers in ELIMINABLE_REGS, even if some of the entries
9796 seem to be redundant or useless. */
9797 switch (from)
9799 case ARG_POINTER_REGNUM:
9800 switch (to)
9802 case THUMB_HARD_FRAME_POINTER_REGNUM:
9803 return 0;
9805 case FRAME_POINTER_REGNUM:
9806 /* This is the reverse of the soft frame pointer
9807 to hard frame pointer elimination below. */
9808 if (call_saved_registers == 0 && stack_frame == 0)
9809 return 0;
9810 return (call_saved_registers + stack_frame - 4);
9812 case ARM_HARD_FRAME_POINTER_REGNUM:
9813 /* If there is no stack frame then the hard
9814 frame pointer and the arg pointer coincide. */
9815 if (stack_frame == 0 && call_saved_registers != 0)
9816 return 0;
9817 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9818 return (frame_pointer_needed
9819 && current_function_needs_context
9820 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9822 case STACK_POINTER_REGNUM:
9823 /* If nothing has been pushed on the stack at all
9824 then this will return -4. This *is* correct! */
9825 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9827 default:
9828 abort ();
9830 break;
9832 case FRAME_POINTER_REGNUM:
9833 switch (to)
9835 case THUMB_HARD_FRAME_POINTER_REGNUM:
9836 return 0;
9838 case ARM_HARD_FRAME_POINTER_REGNUM:
9839 /* The hard frame pointer points to the top entry in the
9840 stack frame. The soft frame pointer to the bottom entry
9841 in the stack frame. If there is no stack frame at all,
9842 then they are identical. */
9843 if (call_saved_registers == 0 && stack_frame == 0)
9844 return 0;
9845 return - (call_saved_registers + stack_frame - 4);
9847 case STACK_POINTER_REGNUM:
9848 return local_vars + outgoing_args;
9850 default:
9851 abort ();
9853 break;
9855 default:
9856 /* You cannot eliminate from the stack pointer.
9857 In theory you could eliminate from the hard frame
9858 pointer to the stack pointer, but this will never
9859 happen, since if a stack frame is not needed the
9860 hard frame pointer will never be used. */
9861 abort ();
9865 /* Calculate the size of the stack frame, taking into account any
9866 padding that is required to ensure stack-alignment. */
9867 HOST_WIDE_INT
9868 arm_get_frame_size (void)
9870 int regno;
9872 int base_size = ROUND_UP_WORD (get_frame_size ());
9873 int entry_size = 0;
9874 unsigned long func_type = arm_current_func_type ();
9875 int leaf;
9876 bool new_block;
9878 if (! TARGET_ARM)
9879 abort();
9881 if (! TARGET_ATPCS)
9882 return base_size;
9884 /* We need to know if we are a leaf function. Unfortunately, it
9885 is possible to be called after start_sequence has been called,
9886 which causes get_insns to return the insns for the sequence,
9887 not the function, which will cause leaf_function_p to return
9888 the incorrect result.
9890 To work around this, we cache the computed frame size. This
9891 works because we will only be calling RTL expanders that need
9892 to know about leaf functions once reload has completed, and the
9893 frame size cannot be changed after that time, so we can safely
9894 use the cached value. */
9896 if (reload_completed)
9897 return cfun->machine->frame_size;
9899 leaf = leaf_function_p ();
9901 /* A leaf function does not need any stack alignment if it has nothing
9902 on the stack. */
9903 if (leaf && base_size == 0)
9905 cfun->machine->frame_size = 0;
9906 return 0;
9909 /* We know that SP will be word aligned on entry, and we must
9910 preserve that condition at any subroutine call. But those are
9911 the only constraints. */
9913 /* Space for variadic functions. */
9914 if (current_function_pretend_args_size)
9915 entry_size += current_function_pretend_args_size;
9917 /* Space for saved registers. */
9918 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9920 if (! IS_VOLATILE (func_type))
9922 /* Space for saved FPA registers. */
9923 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
9924 if (regs_ever_live[regno] && ! call_used_regs[regno])
9925 entry_size += 12;
9927 /* Space for saved VFP registers. */
9928 if (TARGET_HARD_FLOAT && TARGET_VFP)
9930 new_block = TRUE;
9931 for (regno = FIRST_VFP_REGNUM; regno < LAST_VFP_REGNUM; regno += 2)
9933 if ((regs_ever_live[regno] && !call_used_regs[regno])
9934 || (regs_ever_live[regno + 1] && !call_used_regs[regno + 1]))
9936 if (new_block)
9938 entry_size += 4;
9939 new_block = FALSE;
9941 entry_size += 8;
9943 else
9944 new_block = TRUE;
9949 if (TARGET_REALLY_IWMMXT)
9951 /* Check for the call-saved iWMMXt registers. */
9952 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
9953 if (regs_ever_live [regno] && ! call_used_regs [regno])
9954 entry_size += 8;
9957 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9958 base_size += 4;
9959 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9960 abort ();
9962 cfun->machine->frame_size = base_size;
9964 return base_size;
9967 /* Generate the prologue instructions for entry into an ARM function. */
9968 void
9969 arm_expand_prologue (void)
9971 int reg;
9972 rtx amount;
9973 rtx insn;
9974 rtx ip_rtx;
9975 unsigned long live_regs_mask;
9976 unsigned long func_type;
9977 int fp_offset = 0;
9978 int saved_pretend_args = 0;
9979 unsigned int args_to_push;
9981 func_type = arm_current_func_type ();
9983 /* Naked functions don't have prologues. */
9984 if (IS_NAKED (func_type))
9985 return;
9987 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9988 args_to_push = current_function_pretend_args_size;
9990 /* Compute which register we will have to save onto the stack. */
9991 live_regs_mask = arm_compute_save_reg_mask ();
9993 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9995 if (frame_pointer_needed)
9997 if (IS_INTERRUPT (func_type))
9999 /* Interrupt functions must not corrupt any registers.
10000 Creating a frame pointer however, corrupts the IP
10001 register, so we must push it first. */
10002 insn = emit_multi_reg_push (1 << IP_REGNUM);
10004 /* Do not set RTX_FRAME_RELATED_P on this insn.
10005 The dwarf stack unwinding code only wants to see one
10006 stack decrement per function, and this is not it. If
10007 this instruction is labeled as being part of the frame
10008 creation sequence then dwarf2out_frame_debug_expr will
10009 abort when it encounters the assignment of IP to FP
10010 later on, since the use of SP here establishes SP as
10011 the CFA register and not IP.
10013 Anyway this instruction is not really part of the stack
10014 frame creation although it is part of the prologue. */
10016 else if (IS_NESTED (func_type))
10018 /* The Static chain register is the same as the IP register
10019 used as a scratch register during stack frame creation.
10020 To get around this need to find somewhere to store IP
10021 whilst the frame is being created. We try the following
10022 places in order:
10024 1. The last argument register.
10025 2. A slot on the stack above the frame. (This only
10026 works if the function is not a varargs function).
10027 3. Register r3, after pushing the argument registers
10028 onto the stack.
10030 Note - we only need to tell the dwarf2 backend about the SP
10031 adjustment in the second variant; the static chain register
10032 doesn't need to be unwound, as it doesn't contain a value
10033 inherited from the caller. */
10035 if (regs_ever_live[3] == 0)
10037 insn = gen_rtx_REG (SImode, 3);
10038 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10039 insn = emit_insn (insn);
10041 else if (args_to_push == 0)
10043 rtx dwarf;
10044 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10045 insn = gen_rtx_MEM (SImode, insn);
10046 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10047 insn = emit_insn (insn);
10049 fp_offset = 4;
10051 /* Just tell the dwarf backend that we adjusted SP. */
10052 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10053 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10054 GEN_INT (-fp_offset)));
10055 RTX_FRAME_RELATED_P (insn) = 1;
10056 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10057 dwarf, REG_NOTES (insn));
10059 else
10061 /* Store the args on the stack. */
10062 if (cfun->machine->uses_anonymous_args)
10063 insn = emit_multi_reg_push
10064 ((0xf0 >> (args_to_push / 4)) & 0xf);
10065 else
10066 insn = emit_insn
10067 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10068 GEN_INT (- args_to_push)));
10070 RTX_FRAME_RELATED_P (insn) = 1;
10072 saved_pretend_args = 1;
10073 fp_offset = args_to_push;
10074 args_to_push = 0;
10076 /* Now reuse r3 to preserve IP. */
10077 insn = gen_rtx_REG (SImode, 3);
10078 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10079 (void) emit_insn (insn);
10083 if (fp_offset)
10085 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10086 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10088 else
10089 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10091 insn = emit_insn (insn);
10092 RTX_FRAME_RELATED_P (insn) = 1;
10095 if (args_to_push)
10097 /* Push the argument registers, or reserve space for them. */
10098 if (cfun->machine->uses_anonymous_args)
10099 insn = emit_multi_reg_push
10100 ((0xf0 >> (args_to_push / 4)) & 0xf);
10101 else
10102 insn = emit_insn
10103 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10104 GEN_INT (- args_to_push)));
10105 RTX_FRAME_RELATED_P (insn) = 1;
10108 /* If this is an interrupt service routine, and the link register
10109 is going to be pushed, and we are not creating a stack frame,
10110 (which would involve an extra push of IP and a pop in the epilogue)
10111 subtracting four from LR now will mean that the function return
10112 can be done with a single instruction. */
10113 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10114 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10115 && ! frame_pointer_needed)
10116 emit_insn (gen_rtx_SET (SImode,
10117 gen_rtx_REG (SImode, LR_REGNUM),
10118 gen_rtx_PLUS (SImode,
10119 gen_rtx_REG (SImode, LR_REGNUM),
10120 GEN_INT (-4))));
10122 if (live_regs_mask)
10124 insn = emit_multi_reg_push (live_regs_mask);
10125 RTX_FRAME_RELATED_P (insn) = 1;
10128 if (TARGET_IWMMXT)
10129 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10130 if (regs_ever_live[reg] && ! call_used_regs [reg])
10132 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10133 insn = gen_rtx_MEM (V2SImode, insn);
10134 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10135 gen_rtx_REG (V2SImode, reg)));
10136 RTX_FRAME_RELATED_P (insn) = 1;
10139 if (! IS_VOLATILE (func_type))
10141 int start_reg;
10143 /* Save any floating point call-saved registers used by this
10144 function. */
10145 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10147 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10148 if (regs_ever_live[reg] && !call_used_regs[reg])
10150 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10151 insn = gen_rtx_MEM (XFmode, insn);
10152 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10153 gen_rtx_REG (XFmode, reg)));
10154 RTX_FRAME_RELATED_P (insn) = 1;
10157 else
10159 start_reg = LAST_FPA_REGNUM;
10161 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10163 if (regs_ever_live[reg] && !call_used_regs[reg])
10165 if (start_reg - reg == 3)
10167 insn = emit_sfm (reg, 4);
10168 RTX_FRAME_RELATED_P (insn) = 1;
10169 start_reg = reg - 1;
10172 else
10174 if (start_reg != reg)
10176 insn = emit_sfm (reg + 1, start_reg - reg);
10177 RTX_FRAME_RELATED_P (insn) = 1;
10179 start_reg = reg - 1;
10183 if (start_reg != reg)
10185 insn = emit_sfm (reg + 1, start_reg - reg);
10186 RTX_FRAME_RELATED_P (insn) = 1;
10189 if (TARGET_HARD_FLOAT && TARGET_VFP)
10191 start_reg = FIRST_VFP_REGNUM;
10193 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10195 if ((!regs_ever_live[reg] || call_used_regs[reg])
10196 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10198 if (start_reg != reg)
10200 insn = vfp_emit_fstmx (start_reg,
10201 (reg - start_reg) / 2);
10202 RTX_FRAME_RELATED_P (insn) = 1;
10204 start_reg = reg + 2;
10207 if (start_reg != reg)
10209 insn = vfp_emit_fstmx (start_reg,
10210 (reg - start_reg) / 2);
10211 RTX_FRAME_RELATED_P (insn) = 1;
10216 if (frame_pointer_needed)
10218 /* Create the new frame pointer. */
10219 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10220 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10221 RTX_FRAME_RELATED_P (insn) = 1;
10223 if (IS_NESTED (func_type))
10225 /* Recover the static chain register. */
10226 if (regs_ever_live [3] == 0
10227 || saved_pretend_args)
10228 insn = gen_rtx_REG (SImode, 3);
10229 else /* if (current_function_pretend_args_size == 0) */
10231 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10232 GEN_INT (4));
10233 insn = gen_rtx_MEM (SImode, insn);
10236 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10237 /* Add a USE to stop propagate_one_insn() from barfing. */
10238 emit_insn (gen_prologue_use (ip_rtx));
10242 amount = GEN_INT (-(arm_get_frame_size ()
10243 + current_function_outgoing_args_size));
10245 if (amount != const0_rtx)
10247 /* This add can produce multiple insns for a large constant, so we
10248 need to get tricky. */
10249 rtx last = get_last_insn ();
10250 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10251 amount));
10254 last = last ? NEXT_INSN (last) : get_insns ();
10255 RTX_FRAME_RELATED_P (last) = 1;
10257 while (last != insn);
10259 /* If the frame pointer is needed, emit a special barrier that
10260 will prevent the scheduler from moving stores to the frame
10261 before the stack adjustment. */
10262 if (frame_pointer_needed)
10263 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10264 hard_frame_pointer_rtx));
10267 /* If we are profiling, make sure no instructions are scheduled before
10268 the call to mcount. Similarly if the user has requested no
10269 scheduling in the prolog. */
10270 if (current_function_profile || TARGET_NO_SCHED_PRO)
10271 emit_insn (gen_blockage ());
10273 /* If the link register is being kept alive, with the return address in it,
10274 then make sure that it does not get reused by the ce2 pass. */
10275 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10277 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10278 cfun->machine->lr_save_eliminated = 1;
10282 /* If CODE is 'd', then the X is a condition operand and the instruction
10283 should only be executed if the condition is true.
10284 if CODE is 'D', then the X is a condition operand and the instruction
10285 should only be executed if the condition is false: however, if the mode
10286 of the comparison is CCFPEmode, then always execute the instruction -- we
10287 do this because in these circumstances !GE does not necessarily imply LT;
10288 in these cases the instruction pattern will take care to make sure that
10289 an instruction containing %d will follow, thereby undoing the effects of
10290 doing this instruction unconditionally.
10291 If CODE is 'N' then X is a floating point operand that must be negated
10292 before output.
10293 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10294 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10295 void
10296 arm_print_operand (FILE *stream, rtx x, int code)
10298 switch (code)
10300 case '@':
10301 fputs (ASM_COMMENT_START, stream);
10302 return;
10304 case '_':
10305 fputs (user_label_prefix, stream);
10306 return;
10308 case '|':
10309 fputs (REGISTER_PREFIX, stream);
10310 return;
10312 case '?':
10313 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10315 if (TARGET_THUMB || current_insn_predicate != NULL)
10316 abort ();
10318 fputs (arm_condition_codes[arm_current_cc], stream);
10320 else if (current_insn_predicate)
10322 enum arm_cond_code code;
10324 if (TARGET_THUMB)
10325 abort ();
10327 code = get_arm_condition_code (current_insn_predicate);
10328 fputs (arm_condition_codes[code], stream);
10330 return;
10332 case 'N':
10334 REAL_VALUE_TYPE r;
10335 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10336 r = REAL_VALUE_NEGATE (r);
10337 fprintf (stream, "%s", fp_const_from_val (&r));
10339 return;
10341 case 'B':
10342 if (GET_CODE (x) == CONST_INT)
10344 HOST_WIDE_INT val;
10345 val = ARM_SIGN_EXTEND (~INTVAL (x));
10346 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10348 else
10350 putc ('~', stream);
10351 output_addr_const (stream, x);
10353 return;
10355 case 'i':
10356 fprintf (stream, "%s", arithmetic_instr (x, 1));
10357 return;
10359 /* Truncate Cirrus shift counts. */
10360 case 's':
10361 if (GET_CODE (x) == CONST_INT)
10363 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10364 return;
10366 arm_print_operand (stream, x, 0);
10367 return;
10369 case 'I':
10370 fprintf (stream, "%s", arithmetic_instr (x, 0));
10371 return;
10373 case 'S':
10375 HOST_WIDE_INT val;
10376 const char * shift = shift_op (x, &val);
10378 if (shift)
10380 fprintf (stream, ", %s ", shift_op (x, &val));
10381 if (val == -1)
10382 arm_print_operand (stream, XEXP (x, 1), 0);
10383 else
10384 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10387 return;
10389 /* An explanation of the 'Q', 'R' and 'H' register operands:
10391 In a pair of registers containing a DI or DF value the 'Q'
10392 operand returns the register number of the register containing
10393 the least significant part of the value. The 'R' operand returns
10394 the register number of the register containing the most
10395 significant part of the value.
10397 The 'H' operand returns the higher of the two register numbers.
10398 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10399 same as the 'Q' operand, since the most significant part of the
10400 value is held in the lower number register. The reverse is true
10401 on systems where WORDS_BIG_ENDIAN is false.
10403 The purpose of these operands is to distinguish between cases
10404 where the endian-ness of the values is important (for example
10405 when they are added together), and cases where the endian-ness
10406 is irrelevant, but the order of register operations is important.
10407 For example when loading a value from memory into a register
10408 pair, the endian-ness does not matter. Provided that the value
10409 from the lower memory address is put into the lower numbered
10410 register, and the value from the higher address is put into the
10411 higher numbered register, the load will work regardless of whether
10412 the value being loaded is big-wordian or little-wordian. The
10413 order of the two register loads can matter however, if the address
10414 of the memory location is actually held in one of the registers
10415 being overwritten by the load. */
10416 case 'Q':
10417 if (REGNO (x) > LAST_ARM_REGNUM)
10418 abort ();
10419 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10420 return;
10422 case 'R':
10423 if (REGNO (x) > LAST_ARM_REGNUM)
10424 abort ();
10425 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10426 return;
10428 case 'H':
10429 if (REGNO (x) > LAST_ARM_REGNUM)
10430 abort ();
10431 asm_fprintf (stream, "%r", REGNO (x) + 1);
10432 return;
10434 case 'm':
10435 asm_fprintf (stream, "%r",
10436 GET_CODE (XEXP (x, 0)) == REG
10437 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10438 return;
10440 case 'M':
10441 asm_fprintf (stream, "{%r-%r}",
10442 REGNO (x),
10443 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10444 return;
10446 case 'd':
10447 /* CONST_TRUE_RTX means always -- that's the default. */
10448 if (x == const_true_rtx)
10449 return;
10451 fputs (arm_condition_codes[get_arm_condition_code (x)],
10452 stream);
10453 return;
10455 case 'D':
10456 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10457 want to do that. */
10458 if (x == const_true_rtx)
10459 abort ();
10461 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10462 (get_arm_condition_code (x))],
10463 stream);
10464 return;
10466 /* Cirrus registers can be accessed in a variety of ways:
10467 single floating point (f)
10468 double floating point (d)
10469 32bit integer (fx)
10470 64bit integer (dx). */
10471 case 'W': /* Cirrus register in F mode. */
10472 case 'X': /* Cirrus register in D mode. */
10473 case 'Y': /* Cirrus register in FX mode. */
10474 case 'Z': /* Cirrus register in DX mode. */
10475 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10476 abort ();
10478 fprintf (stream, "mv%s%s",
10479 code == 'W' ? "f"
10480 : code == 'X' ? "d"
10481 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10483 return;
10485 /* Print cirrus register in the mode specified by the register's mode. */
10486 case 'V':
10488 int mode = GET_MODE (x);
10490 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10491 abort ();
10493 fprintf (stream, "mv%s%s",
10494 mode == DFmode ? "d"
10495 : mode == SImode ? "fx"
10496 : mode == DImode ? "dx"
10497 : "f", reg_names[REGNO (x)] + 2);
10499 return;
10502 case 'U':
10503 if (GET_CODE (x) != REG
10504 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10505 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10506 /* Bad value for wCG register number. */
10507 abort ();
10508 else
10509 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10510 return;
10512 /* Print an iWMMXt control register name. */
10513 case 'w':
10514 if (GET_CODE (x) != CONST_INT
10515 || INTVAL (x) < 0
10516 || INTVAL (x) >= 16)
10517 /* Bad value for wC register number. */
10518 abort ();
10519 else
10521 static const char * wc_reg_names [16] =
10523 "wCID", "wCon", "wCSSF", "wCASF",
10524 "wC4", "wC5", "wC6", "wC7",
10525 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10526 "wC12", "wC13", "wC14", "wC15"
10529 fprintf (stream, wc_reg_names [INTVAL (x)]);
10531 return;
10533 /* Print a VFP double precision register name. */
10534 case 'P':
10536 int mode = GET_MODE (x);
10537 int num;
10539 if (mode != DImode && mode != DFmode)
10540 abort ();
10542 if (GET_CODE (x) != REG
10543 || !IS_VFP_REGNUM (REGNO (x)))
10544 abort ();
10546 num = REGNO(x) - FIRST_VFP_REGNUM;
10547 if (num & 1)
10548 abort ();
10550 fprintf (stream, "d%d", num >> 1);
10552 return;
10554 default:
10555 if (x == 0)
10556 abort ();
10558 if (GET_CODE (x) == REG)
10559 asm_fprintf (stream, "%r", REGNO (x));
10560 else if (GET_CODE (x) == MEM)
10562 output_memory_reference_mode = GET_MODE (x);
10563 output_address (XEXP (x, 0));
10565 else if (GET_CODE (x) == CONST_DOUBLE)
10566 fprintf (stream, "#%s", fp_immediate_constant (x));
10567 else if (GET_CODE (x) == NEG)
10568 abort (); /* This should never happen now. */
10569 else
10571 fputc ('#', stream);
10572 output_addr_const (stream, x);
10577 #ifndef AOF_ASSEMBLER
10578 /* Target hook for assembling integer objects. The ARM version needs to
10579 handle word-sized values specially. */
10580 static bool
10581 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10583 if (size == UNITS_PER_WORD && aligned_p)
10585 fputs ("\t.word\t", asm_out_file);
10586 output_addr_const (asm_out_file, x);
10588 /* Mark symbols as position independent. We only do this in the
10589 .text segment, not in the .data segment. */
10590 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10591 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10593 if (GET_CODE (x) == SYMBOL_REF
10594 && (CONSTANT_POOL_ADDRESS_P (x)
10595 || SYMBOL_REF_LOCAL_P (x)))
10596 fputs ("(GOTOFF)", asm_out_file);
10597 else if (GET_CODE (x) == LABEL_REF)
10598 fputs ("(GOTOFF)", asm_out_file);
10599 else
10600 fputs ("(GOT)", asm_out_file);
10602 fputc ('\n', asm_out_file);
10603 return true;
10606 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10608 int i, units;
10610 if (GET_CODE (x) != CONST_VECTOR)
10611 abort ();
10613 units = CONST_VECTOR_NUNITS (x);
10615 switch (GET_MODE (x))
10617 case V2SImode: size = 4; break;
10618 case V4HImode: size = 2; break;
10619 case V8QImode: size = 1; break;
10620 default:
10621 abort ();
10624 for (i = 0; i < units; i++)
10626 rtx elt;
10628 elt = CONST_VECTOR_ELT (x, i);
10629 assemble_integer
10630 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10633 return true;
10636 return default_assemble_integer (x, size, aligned_p);
10638 #endif
10640 /* A finite state machine takes care of noticing whether or not instructions
10641 can be conditionally executed, and thus decrease execution time and code
10642 size by deleting branch instructions. The fsm is controlled by
10643 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10645 /* The state of the fsm controlling condition codes are:
10646 0: normal, do nothing special
10647 1: make ASM_OUTPUT_OPCODE not output this instruction
10648 2: make ASM_OUTPUT_OPCODE not output this instruction
10649 3: make instructions conditional
10650 4: make instructions conditional
10652 State transitions (state->state by whom under condition):
10653 0 -> 1 final_prescan_insn if the `target' is a label
10654 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10655 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10656 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10657 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10658 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10659 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10660 (the target insn is arm_target_insn).
10662 If the jump clobbers the conditions then we use states 2 and 4.
10664 A similar thing can be done with conditional return insns.
10666 XXX In case the `target' is an unconditional branch, this conditionalising
10667 of the instructions always reduces code size, but not always execution
10668 time. But then, I want to reduce the code size to somewhere near what
10669 /bin/cc produces. */
10671 /* Returns the index of the ARM condition code string in
10672 `arm_condition_codes'. COMPARISON should be an rtx like
10673 `(eq (...) (...))'. */
10674 static enum arm_cond_code
10675 get_arm_condition_code (rtx comparison)
10677 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10678 int code;
10679 enum rtx_code comp_code = GET_CODE (comparison);
10681 if (GET_MODE_CLASS (mode) != MODE_CC)
10682 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10683 XEXP (comparison, 1));
10685 switch (mode)
10687 case CC_DNEmode: code = ARM_NE; goto dominance;
10688 case CC_DEQmode: code = ARM_EQ; goto dominance;
10689 case CC_DGEmode: code = ARM_GE; goto dominance;
10690 case CC_DGTmode: code = ARM_GT; goto dominance;
10691 case CC_DLEmode: code = ARM_LE; goto dominance;
10692 case CC_DLTmode: code = ARM_LT; goto dominance;
10693 case CC_DGEUmode: code = ARM_CS; goto dominance;
10694 case CC_DGTUmode: code = ARM_HI; goto dominance;
10695 case CC_DLEUmode: code = ARM_LS; goto dominance;
10696 case CC_DLTUmode: code = ARM_CC;
10698 dominance:
10699 if (comp_code != EQ && comp_code != NE)
10700 abort ();
10702 if (comp_code == EQ)
10703 return ARM_INVERSE_CONDITION_CODE (code);
10704 return code;
10706 case CC_NOOVmode:
10707 switch (comp_code)
10709 case NE: return ARM_NE;
10710 case EQ: return ARM_EQ;
10711 case GE: return ARM_PL;
10712 case LT: return ARM_MI;
10713 default: abort ();
10716 case CC_Zmode:
10717 switch (comp_code)
10719 case NE: return ARM_NE;
10720 case EQ: return ARM_EQ;
10721 default: abort ();
10724 case CC_Nmode:
10725 switch (comp_code)
10727 case NE: return ARM_MI;
10728 case EQ: return ARM_PL;
10729 default: abort ();
10732 case CCFPEmode:
10733 case CCFPmode:
10734 /* These encodings assume that AC=1 in the FPA system control
10735 byte. This allows us to handle all cases except UNEQ and
10736 LTGT. */
10737 switch (comp_code)
10739 case GE: return ARM_GE;
10740 case GT: return ARM_GT;
10741 case LE: return ARM_LS;
10742 case LT: return ARM_MI;
10743 case NE: return ARM_NE;
10744 case EQ: return ARM_EQ;
10745 case ORDERED: return ARM_VC;
10746 case UNORDERED: return ARM_VS;
10747 case UNLT: return ARM_LT;
10748 case UNLE: return ARM_LE;
10749 case UNGT: return ARM_HI;
10750 case UNGE: return ARM_PL;
10751 /* UNEQ and LTGT do not have a representation. */
10752 case UNEQ: /* Fall through. */
10753 case LTGT: /* Fall through. */
10754 default: abort ();
10757 case CC_SWPmode:
10758 switch (comp_code)
10760 case NE: return ARM_NE;
10761 case EQ: return ARM_EQ;
10762 case GE: return ARM_LE;
10763 case GT: return ARM_LT;
10764 case LE: return ARM_GE;
10765 case LT: return ARM_GT;
10766 case GEU: return ARM_LS;
10767 case GTU: return ARM_CC;
10768 case LEU: return ARM_CS;
10769 case LTU: return ARM_HI;
10770 default: abort ();
10773 case CC_Cmode:
10774 switch (comp_code)
10776 case LTU: return ARM_CS;
10777 case GEU: return ARM_CC;
10778 default: abort ();
10781 case CCmode:
10782 switch (comp_code)
10784 case NE: return ARM_NE;
10785 case EQ: return ARM_EQ;
10786 case GE: return ARM_GE;
10787 case GT: return ARM_GT;
10788 case LE: return ARM_LE;
10789 case LT: return ARM_LT;
10790 case GEU: return ARM_CS;
10791 case GTU: return ARM_HI;
10792 case LEU: return ARM_LS;
10793 case LTU: return ARM_CC;
10794 default: abort ();
10797 default: abort ();
10800 abort ();
10803 void
10804 arm_final_prescan_insn (rtx insn)
10806 /* BODY will hold the body of INSN. */
10807 rtx body = PATTERN (insn);
10809 /* This will be 1 if trying to repeat the trick, and things need to be
10810 reversed if it appears to fail. */
10811 int reverse = 0;
10813 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10814 taken are clobbered, even if the rtl suggests otherwise. It also
10815 means that we have to grub around within the jump expression to find
10816 out what the conditions are when the jump isn't taken. */
10817 int jump_clobbers = 0;
10819 /* If we start with a return insn, we only succeed if we find another one. */
10820 int seeking_return = 0;
10822 /* START_INSN will hold the insn from where we start looking. This is the
10823 first insn after the following code_label if REVERSE is true. */
10824 rtx start_insn = insn;
10826 /* If in state 4, check if the target branch is reached, in order to
10827 change back to state 0. */
10828 if (arm_ccfsm_state == 4)
10830 if (insn == arm_target_insn)
10832 arm_target_insn = NULL;
10833 arm_ccfsm_state = 0;
10835 return;
10838 /* If in state 3, it is possible to repeat the trick, if this insn is an
10839 unconditional branch to a label, and immediately following this branch
10840 is the previous target label which is only used once, and the label this
10841 branch jumps to is not too far off. */
10842 if (arm_ccfsm_state == 3)
10844 if (simplejump_p (insn))
10846 start_insn = next_nonnote_insn (start_insn);
10847 if (GET_CODE (start_insn) == BARRIER)
10849 /* XXX Isn't this always a barrier? */
10850 start_insn = next_nonnote_insn (start_insn);
10852 if (GET_CODE (start_insn) == CODE_LABEL
10853 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10854 && LABEL_NUSES (start_insn) == 1)
10855 reverse = TRUE;
10856 else
10857 return;
10859 else if (GET_CODE (body) == RETURN)
10861 start_insn = next_nonnote_insn (start_insn);
10862 if (GET_CODE (start_insn) == BARRIER)
10863 start_insn = next_nonnote_insn (start_insn);
10864 if (GET_CODE (start_insn) == CODE_LABEL
10865 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10866 && LABEL_NUSES (start_insn) == 1)
10868 reverse = TRUE;
10869 seeking_return = 1;
10871 else
10872 return;
10874 else
10875 return;
10878 if (arm_ccfsm_state != 0 && !reverse)
10879 abort ();
10880 if (GET_CODE (insn) != JUMP_INSN)
10881 return;
10883 /* This jump might be paralleled with a clobber of the condition codes
10884 the jump should always come first */
10885 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10886 body = XVECEXP (body, 0, 0);
10888 if (reverse
10889 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10890 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10892 int insns_skipped;
10893 int fail = FALSE, succeed = FALSE;
10894 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10895 int then_not_else = TRUE;
10896 rtx this_insn = start_insn, label = 0;
10898 /* If the jump cannot be done with one instruction, we cannot
10899 conditionally execute the instruction in the inverse case. */
10900 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10902 jump_clobbers = 1;
10903 return;
10906 /* Register the insn jumped to. */
10907 if (reverse)
10909 if (!seeking_return)
10910 label = XEXP (SET_SRC (body), 0);
10912 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10913 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10914 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10916 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10917 then_not_else = FALSE;
10919 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10920 seeking_return = 1;
10921 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10923 seeking_return = 1;
10924 then_not_else = FALSE;
10926 else
10927 abort ();
10929 /* See how many insns this branch skips, and what kind of insns. If all
10930 insns are okay, and the label or unconditional branch to the same
10931 label is not too far away, succeed. */
10932 for (insns_skipped = 0;
10933 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10935 rtx scanbody;
10937 this_insn = next_nonnote_insn (this_insn);
10938 if (!this_insn)
10939 break;
10941 switch (GET_CODE (this_insn))
10943 case CODE_LABEL:
10944 /* Succeed if it is the target label, otherwise fail since
10945 control falls in from somewhere else. */
10946 if (this_insn == label)
10948 if (jump_clobbers)
10950 arm_ccfsm_state = 2;
10951 this_insn = next_nonnote_insn (this_insn);
10953 else
10954 arm_ccfsm_state = 1;
10955 succeed = TRUE;
10957 else
10958 fail = TRUE;
10959 break;
10961 case BARRIER:
10962 /* Succeed if the following insn is the target label.
10963 Otherwise fail.
10964 If return insns are used then the last insn in a function
10965 will be a barrier. */
10966 this_insn = next_nonnote_insn (this_insn);
10967 if (this_insn && this_insn == label)
10969 if (jump_clobbers)
10971 arm_ccfsm_state = 2;
10972 this_insn = next_nonnote_insn (this_insn);
10974 else
10975 arm_ccfsm_state = 1;
10976 succeed = TRUE;
10978 else
10979 fail = TRUE;
10980 break;
10982 case CALL_INSN:
10983 /* If using 32-bit addresses the cc is not preserved over
10984 calls. */
10985 if (TARGET_APCS_32)
10987 /* Succeed if the following insn is the target label,
10988 or if the following two insns are a barrier and
10989 the target label. */
10990 this_insn = next_nonnote_insn (this_insn);
10991 if (this_insn && GET_CODE (this_insn) == BARRIER)
10992 this_insn = next_nonnote_insn (this_insn);
10994 if (this_insn && this_insn == label
10995 && insns_skipped < max_insns_skipped)
10997 if (jump_clobbers)
10999 arm_ccfsm_state = 2;
11000 this_insn = next_nonnote_insn (this_insn);
11002 else
11003 arm_ccfsm_state = 1;
11004 succeed = TRUE;
11006 else
11007 fail = TRUE;
11009 break;
11011 case JUMP_INSN:
11012 /* If this is an unconditional branch to the same label, succeed.
11013 If it is to another label, do nothing. If it is conditional,
11014 fail. */
11015 /* XXX Probably, the tests for SET and the PC are
11016 unnecessary. */
11018 scanbody = PATTERN (this_insn);
11019 if (GET_CODE (scanbody) == SET
11020 && GET_CODE (SET_DEST (scanbody)) == PC)
11022 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11023 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11025 arm_ccfsm_state = 2;
11026 succeed = TRUE;
11028 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11029 fail = TRUE;
11031 /* Fail if a conditional return is undesirable (eg on a
11032 StrongARM), but still allow this if optimizing for size. */
11033 else if (GET_CODE (scanbody) == RETURN
11034 && !use_return_insn (TRUE, NULL)
11035 && !optimize_size)
11036 fail = TRUE;
11037 else if (GET_CODE (scanbody) == RETURN
11038 && seeking_return)
11040 arm_ccfsm_state = 2;
11041 succeed = TRUE;
11043 else if (GET_CODE (scanbody) == PARALLEL)
11045 switch (get_attr_conds (this_insn))
11047 case CONDS_NOCOND:
11048 break;
11049 default:
11050 fail = TRUE;
11051 break;
11054 else
11055 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11057 break;
11059 case INSN:
11060 /* Instructions using or affecting the condition codes make it
11061 fail. */
11062 scanbody = PATTERN (this_insn);
11063 if (!(GET_CODE (scanbody) == SET
11064 || GET_CODE (scanbody) == PARALLEL)
11065 || get_attr_conds (this_insn) != CONDS_NOCOND)
11066 fail = TRUE;
11068 /* A conditional cirrus instruction must be followed by
11069 a non Cirrus instruction. However, since we
11070 conditionalize instructions in this function and by
11071 the time we get here we can't add instructions
11072 (nops), because shorten_branches() has already been
11073 called, we will disable conditionalizing Cirrus
11074 instructions to be safe. */
11075 if (GET_CODE (scanbody) != USE
11076 && GET_CODE (scanbody) != CLOBBER
11077 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11078 fail = TRUE;
11079 break;
11081 default:
11082 break;
11085 if (succeed)
11087 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11088 arm_target_label = CODE_LABEL_NUMBER (label);
11089 else if (seeking_return || arm_ccfsm_state == 2)
11091 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11093 this_insn = next_nonnote_insn (this_insn);
11094 if (this_insn && (GET_CODE (this_insn) == BARRIER
11095 || GET_CODE (this_insn) == CODE_LABEL))
11096 abort ();
11098 if (!this_insn)
11100 /* Oh, dear! we ran off the end.. give up. */
11101 recog (PATTERN (insn), insn, NULL);
11102 arm_ccfsm_state = 0;
11103 arm_target_insn = NULL;
11104 return;
11106 arm_target_insn = this_insn;
11108 else
11109 abort ();
11110 if (jump_clobbers)
11112 if (reverse)
11113 abort ();
11114 arm_current_cc =
11115 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11116 0), 0), 1));
11117 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11118 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11119 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11120 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11122 else
11124 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11125 what it was. */
11126 if (!reverse)
11127 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11128 0));
11131 if (reverse || then_not_else)
11132 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11135 /* Restore recog_data (getting the attributes of other insns can
11136 destroy this array, but final.c assumes that it remains intact
11137 across this call; since the insn has been recognized already we
11138 call recog direct). */
11139 recog (PATTERN (insn), insn, NULL);
11143 /* Returns true if REGNO is a valid register
11144 for holding a quantity of tyoe MODE. */
11146 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11148 if (GET_MODE_CLASS (mode) == MODE_CC)
11149 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11151 if (TARGET_THUMB)
11152 /* For the Thumb we only allow values bigger than SImode in
11153 registers 0 - 6, so that there is always a second low
11154 register available to hold the upper part of the value.
11155 We probably we ought to ensure that the register is the
11156 start of an even numbered register pair. */
11157 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11159 if (IS_CIRRUS_REGNUM (regno))
11160 /* We have outlawed SI values in Cirrus registers because they
11161 reside in the lower 32 bits, but SF values reside in the
11162 upper 32 bits. This causes gcc all sorts of grief. We can't
11163 even split the registers into pairs because Cirrus SI values
11164 get sign extended to 64bits-- aldyh. */
11165 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11167 if (IS_VFP_REGNUM (regno))
11169 if (mode == SFmode || mode == SImode)
11170 return TRUE;
11172 /* DFmode values are only valid in even register pairs. */
11173 if (mode == DFmode)
11174 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11175 return FALSE;
11178 if (IS_IWMMXT_GR_REGNUM (regno))
11179 return mode == SImode;
11181 if (IS_IWMMXT_REGNUM (regno))
11182 return VALID_IWMMXT_REG_MODE (mode);
11184 if (regno <= LAST_ARM_REGNUM)
11185 /* We allow any value to be stored in the general registers. */
11186 return 1;
11188 if ( regno == FRAME_POINTER_REGNUM
11189 || regno == ARG_POINTER_REGNUM)
11190 /* We only allow integers in the fake hard registers. */
11191 return GET_MODE_CLASS (mode) == MODE_INT;
11193 /* The only registers left are the FPA registers
11194 which we only allow to hold FP values. */
11195 return GET_MODE_CLASS (mode) == MODE_FLOAT
11196 && regno >= FIRST_FPA_REGNUM
11197 && regno <= LAST_FPA_REGNUM;
11201 arm_regno_class (int regno)
11203 if (TARGET_THUMB)
11205 if (regno == STACK_POINTER_REGNUM)
11206 return STACK_REG;
11207 if (regno == CC_REGNUM)
11208 return CC_REG;
11209 if (regno < 8)
11210 return LO_REGS;
11211 return HI_REGS;
11214 if ( regno <= LAST_ARM_REGNUM
11215 || regno == FRAME_POINTER_REGNUM
11216 || regno == ARG_POINTER_REGNUM)
11217 return GENERAL_REGS;
11219 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11220 return NO_REGS;
11222 if (IS_CIRRUS_REGNUM (regno))
11223 return CIRRUS_REGS;
11225 if (IS_VFP_REGNUM (regno))
11226 return VFP_REGS;
11228 if (IS_IWMMXT_REGNUM (regno))
11229 return IWMMXT_REGS;
11231 if (IS_IWMMXT_GR_REGNUM (regno))
11232 return IWMMXT_GR_REGS;
11234 return FPA_REGS;
11237 /* Handle a special case when computing the offset
11238 of an argument from the frame pointer. */
11240 arm_debugger_arg_offset (int value, rtx addr)
11242 rtx insn;
11244 /* We are only interested if dbxout_parms() failed to compute the offset. */
11245 if (value != 0)
11246 return 0;
11248 /* We can only cope with the case where the address is held in a register. */
11249 if (GET_CODE (addr) != REG)
11250 return 0;
11252 /* If we are using the frame pointer to point at the argument, then
11253 an offset of 0 is correct. */
11254 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11255 return 0;
11257 /* If we are using the stack pointer to point at the
11258 argument, then an offset of 0 is correct. */
11259 if ((TARGET_THUMB || !frame_pointer_needed)
11260 && REGNO (addr) == SP_REGNUM)
11261 return 0;
11263 /* Oh dear. The argument is pointed to by a register rather
11264 than being held in a register, or being stored at a known
11265 offset from the frame pointer. Since GDB only understands
11266 those two kinds of argument we must translate the address
11267 held in the register into an offset from the frame pointer.
11268 We do this by searching through the insns for the function
11269 looking to see where this register gets its value. If the
11270 register is initialized from the frame pointer plus an offset
11271 then we are in luck and we can continue, otherwise we give up.
11273 This code is exercised by producing debugging information
11274 for a function with arguments like this:
11276 double func (double a, double b, int c, double d) {return d;}
11278 Without this code the stab for parameter 'd' will be set to
11279 an offset of 0 from the frame pointer, rather than 8. */
11281 /* The if() statement says:
11283 If the insn is a normal instruction
11284 and if the insn is setting the value in a register
11285 and if the register being set is the register holding the address of the argument
11286 and if the address is computing by an addition
11287 that involves adding to a register
11288 which is the frame pointer
11289 a constant integer
11291 then... */
11293 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11295 if ( GET_CODE (insn) == INSN
11296 && GET_CODE (PATTERN (insn)) == SET
11297 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11298 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11299 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11300 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11301 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11304 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11306 break;
11310 if (value == 0)
11312 debug_rtx (addr);
11313 warning ("unable to compute real location of stacked parameter");
11314 value = 8; /* XXX magic hack */
11317 return value;
11320 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11321 do \
11323 if ((MASK) & insn_flags) \
11324 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11326 while (0)
11328 struct builtin_description
11330 const unsigned int mask;
11331 const enum insn_code icode;
11332 const char * const name;
11333 const enum arm_builtins code;
11334 const enum rtx_code comparison;
11335 const unsigned int flag;
11338 static const struct builtin_description bdesc_2arg[] =
11340 #define IWMMXT_BUILTIN(code, string, builtin) \
11341 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11342 ARM_BUILTIN_##builtin, 0, 0 },
11344 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11345 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11346 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11347 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11348 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11349 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11350 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11351 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11352 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11353 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11354 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11355 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11356 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11357 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11358 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11359 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11360 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11361 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11362 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11363 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11364 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11365 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11366 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11367 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11368 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11369 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11370 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11371 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11372 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11373 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11374 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11375 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11376 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11377 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11378 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11379 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11380 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11381 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11382 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11383 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11384 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11385 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11386 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11387 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11388 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11389 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11390 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11391 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11392 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11393 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11394 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11395 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11396 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11397 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11398 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11399 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11400 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11401 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11403 #define IWMMXT_BUILTIN2(code, builtin) \
11404 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11406 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11407 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11408 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11409 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11410 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11411 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11412 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11413 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11414 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11415 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11416 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11417 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11418 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11419 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11420 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11421 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11422 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11423 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11424 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11425 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11426 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11427 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11428 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11429 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11430 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11431 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11432 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11433 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11434 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11435 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11436 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11437 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11440 static const struct builtin_description bdesc_1arg[] =
11442 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11443 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11444 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11445 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11446 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11447 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11448 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11449 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11450 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11451 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11452 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11453 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11454 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11455 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11456 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11457 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11458 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11459 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11462 /* Set up all the iWMMXt builtins. This is
11463 not called if TARGET_IWMMXT is zero. */
11465 static void
11466 arm_init_iwmmxt_builtins (void)
11468 const struct builtin_description * d;
11469 size_t i;
11470 tree endlink = void_list_node;
11472 tree int_ftype_int
11473 = build_function_type (integer_type_node,
11474 tree_cons (NULL_TREE, integer_type_node, endlink));
11475 tree v8qi_ftype_v8qi_v8qi_int
11476 = build_function_type (V8QI_type_node,
11477 tree_cons (NULL_TREE, V8QI_type_node,
11478 tree_cons (NULL_TREE, V8QI_type_node,
11479 tree_cons (NULL_TREE,
11480 integer_type_node,
11481 endlink))));
11482 tree v4hi_ftype_v4hi_int
11483 = build_function_type (V4HI_type_node,
11484 tree_cons (NULL_TREE, V4HI_type_node,
11485 tree_cons (NULL_TREE, integer_type_node,
11486 endlink)));
11487 tree v2si_ftype_v2si_int
11488 = build_function_type (V2SI_type_node,
11489 tree_cons (NULL_TREE, V2SI_type_node,
11490 tree_cons (NULL_TREE, integer_type_node,
11491 endlink)));
11492 tree v2si_ftype_di_di
11493 = build_function_type (V2SI_type_node,
11494 tree_cons (NULL_TREE, long_long_integer_type_node,
11495 tree_cons (NULL_TREE, long_long_integer_type_node,
11496 endlink)));
11497 tree di_ftype_di_int
11498 = build_function_type (long_long_integer_type_node,
11499 tree_cons (NULL_TREE, long_long_integer_type_node,
11500 tree_cons (NULL_TREE, integer_type_node,
11501 endlink)));
11502 tree di_ftype_di_int_int
11503 = build_function_type (long_long_integer_type_node,
11504 tree_cons (NULL_TREE, long_long_integer_type_node,
11505 tree_cons (NULL_TREE, integer_type_node,
11506 tree_cons (NULL_TREE,
11507 integer_type_node,
11508 endlink))));
11509 tree int_ftype_v8qi
11510 = build_function_type (integer_type_node,
11511 tree_cons (NULL_TREE, V8QI_type_node,
11512 endlink));
11513 tree int_ftype_v4hi
11514 = build_function_type (integer_type_node,
11515 tree_cons (NULL_TREE, V4HI_type_node,
11516 endlink));
11517 tree int_ftype_v2si
11518 = build_function_type (integer_type_node,
11519 tree_cons (NULL_TREE, V2SI_type_node,
11520 endlink));
11521 tree int_ftype_v8qi_int
11522 = build_function_type (integer_type_node,
11523 tree_cons (NULL_TREE, V8QI_type_node,
11524 tree_cons (NULL_TREE, integer_type_node,
11525 endlink)));
11526 tree int_ftype_v4hi_int
11527 = build_function_type (integer_type_node,
11528 tree_cons (NULL_TREE, V4HI_type_node,
11529 tree_cons (NULL_TREE, integer_type_node,
11530 endlink)));
11531 tree int_ftype_v2si_int
11532 = build_function_type (integer_type_node,
11533 tree_cons (NULL_TREE, V2SI_type_node,
11534 tree_cons (NULL_TREE, integer_type_node,
11535 endlink)));
11536 tree v8qi_ftype_v8qi_int_int
11537 = build_function_type (V8QI_type_node,
11538 tree_cons (NULL_TREE, V8QI_type_node,
11539 tree_cons (NULL_TREE, integer_type_node,
11540 tree_cons (NULL_TREE,
11541 integer_type_node,
11542 endlink))));
11543 tree v4hi_ftype_v4hi_int_int
11544 = build_function_type (V4HI_type_node,
11545 tree_cons (NULL_TREE, V4HI_type_node,
11546 tree_cons (NULL_TREE, integer_type_node,
11547 tree_cons (NULL_TREE,
11548 integer_type_node,
11549 endlink))));
11550 tree v2si_ftype_v2si_int_int
11551 = build_function_type (V2SI_type_node,
11552 tree_cons (NULL_TREE, V2SI_type_node,
11553 tree_cons (NULL_TREE, integer_type_node,
11554 tree_cons (NULL_TREE,
11555 integer_type_node,
11556 endlink))));
11557 /* Miscellaneous. */
11558 tree v8qi_ftype_v4hi_v4hi
11559 = build_function_type (V8QI_type_node,
11560 tree_cons (NULL_TREE, V4HI_type_node,
11561 tree_cons (NULL_TREE, V4HI_type_node,
11562 endlink)));
11563 tree v4hi_ftype_v2si_v2si
11564 = build_function_type (V4HI_type_node,
11565 tree_cons (NULL_TREE, V2SI_type_node,
11566 tree_cons (NULL_TREE, V2SI_type_node,
11567 endlink)));
11568 tree v2si_ftype_v4hi_v4hi
11569 = build_function_type (V2SI_type_node,
11570 tree_cons (NULL_TREE, V4HI_type_node,
11571 tree_cons (NULL_TREE, V4HI_type_node,
11572 endlink)));
11573 tree v2si_ftype_v8qi_v8qi
11574 = build_function_type (V2SI_type_node,
11575 tree_cons (NULL_TREE, V8QI_type_node,
11576 tree_cons (NULL_TREE, V8QI_type_node,
11577 endlink)));
11578 tree v4hi_ftype_v4hi_di
11579 = build_function_type (V4HI_type_node,
11580 tree_cons (NULL_TREE, V4HI_type_node,
11581 tree_cons (NULL_TREE,
11582 long_long_integer_type_node,
11583 endlink)));
11584 tree v2si_ftype_v2si_di
11585 = build_function_type (V2SI_type_node,
11586 tree_cons (NULL_TREE, V2SI_type_node,
11587 tree_cons (NULL_TREE,
11588 long_long_integer_type_node,
11589 endlink)));
11590 tree void_ftype_int_int
11591 = build_function_type (void_type_node,
11592 tree_cons (NULL_TREE, integer_type_node,
11593 tree_cons (NULL_TREE, integer_type_node,
11594 endlink)));
11595 tree di_ftype_void
11596 = build_function_type (long_long_unsigned_type_node, endlink);
11597 tree di_ftype_v8qi
11598 = build_function_type (long_long_integer_type_node,
11599 tree_cons (NULL_TREE, V8QI_type_node,
11600 endlink));
11601 tree di_ftype_v4hi
11602 = build_function_type (long_long_integer_type_node,
11603 tree_cons (NULL_TREE, V4HI_type_node,
11604 endlink));
11605 tree di_ftype_v2si
11606 = build_function_type (long_long_integer_type_node,
11607 tree_cons (NULL_TREE, V2SI_type_node,
11608 endlink));
11609 tree v2si_ftype_v4hi
11610 = build_function_type (V2SI_type_node,
11611 tree_cons (NULL_TREE, V4HI_type_node,
11612 endlink));
11613 tree v4hi_ftype_v8qi
11614 = build_function_type (V4HI_type_node,
11615 tree_cons (NULL_TREE, V8QI_type_node,
11616 endlink));
11618 tree di_ftype_di_v4hi_v4hi
11619 = build_function_type (long_long_unsigned_type_node,
11620 tree_cons (NULL_TREE,
11621 long_long_unsigned_type_node,
11622 tree_cons (NULL_TREE, V4HI_type_node,
11623 tree_cons (NULL_TREE,
11624 V4HI_type_node,
11625 endlink))));
11627 tree di_ftype_v4hi_v4hi
11628 = build_function_type (long_long_unsigned_type_node,
11629 tree_cons (NULL_TREE, V4HI_type_node,
11630 tree_cons (NULL_TREE, V4HI_type_node,
11631 endlink)));
11633 /* Normal vector binops. */
11634 tree v8qi_ftype_v8qi_v8qi
11635 = build_function_type (V8QI_type_node,
11636 tree_cons (NULL_TREE, V8QI_type_node,
11637 tree_cons (NULL_TREE, V8QI_type_node,
11638 endlink)));
11639 tree v4hi_ftype_v4hi_v4hi
11640 = build_function_type (V4HI_type_node,
11641 tree_cons (NULL_TREE, V4HI_type_node,
11642 tree_cons (NULL_TREE, V4HI_type_node,
11643 endlink)));
11644 tree v2si_ftype_v2si_v2si
11645 = build_function_type (V2SI_type_node,
11646 tree_cons (NULL_TREE, V2SI_type_node,
11647 tree_cons (NULL_TREE, V2SI_type_node,
11648 endlink)));
11649 tree di_ftype_di_di
11650 = build_function_type (long_long_unsigned_type_node,
11651 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11652 tree_cons (NULL_TREE,
11653 long_long_unsigned_type_node,
11654 endlink)));
11656 /* Add all builtins that are more or less simple operations on two
11657 operands. */
11658 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11660 /* Use one of the operands; the target can have a different mode for
11661 mask-generating compares. */
11662 enum machine_mode mode;
11663 tree type;
11665 if (d->name == 0)
11666 continue;
11668 mode = insn_data[d->icode].operand[1].mode;
11670 switch (mode)
11672 case V8QImode:
11673 type = v8qi_ftype_v8qi_v8qi;
11674 break;
11675 case V4HImode:
11676 type = v4hi_ftype_v4hi_v4hi;
11677 break;
11678 case V2SImode:
11679 type = v2si_ftype_v2si_v2si;
11680 break;
11681 case DImode:
11682 type = di_ftype_di_di;
11683 break;
11685 default:
11686 abort ();
11689 def_mbuiltin (d->mask, d->name, type, d->code);
11692 /* Add the remaining MMX insns with somewhat more complicated types. */
11693 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11694 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11695 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11697 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11698 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11699 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11700 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11701 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11702 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11704 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11705 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11706 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11707 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11708 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11709 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11711 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11712 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11713 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11714 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11715 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11716 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11718 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11719 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11720 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11721 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11722 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11723 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11725 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11727 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11728 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11729 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11730 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11732 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11733 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11734 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11735 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11736 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11737 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11738 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11739 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11740 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11742 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11743 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11744 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11746 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11747 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11748 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11750 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11751 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11752 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11753 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11754 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11755 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11757 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11758 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11759 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11760 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11761 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11762 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11763 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11764 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11765 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11766 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11767 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11768 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11770 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11771 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11772 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11773 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11775 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11776 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11777 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11778 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11779 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11780 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11781 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11784 static void
11785 arm_init_builtins (void)
11787 if (TARGET_REALLY_IWMMXT)
11788 arm_init_iwmmxt_builtins ();
11791 /* Errors in the source file can cause expand_expr to return const0_rtx
11792 where we expect a vector. To avoid crashing, use one of the vector
11793 clear instructions. */
11795 static rtx
11796 safe_vector_operand (rtx x, enum machine_mode mode)
11798 if (x != const0_rtx)
11799 return x;
11800 x = gen_reg_rtx (mode);
11802 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11803 : gen_rtx_SUBREG (DImode, x, 0)));
11804 return x;
11807 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11809 static rtx
11810 arm_expand_binop_builtin (enum insn_code icode,
11811 tree arglist, rtx target)
11813 rtx pat;
11814 tree arg0 = TREE_VALUE (arglist);
11815 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11816 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11817 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11818 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11819 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11820 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11822 if (VECTOR_MODE_P (mode0))
11823 op0 = safe_vector_operand (op0, mode0);
11824 if (VECTOR_MODE_P (mode1))
11825 op1 = safe_vector_operand (op1, mode1);
11827 if (! target
11828 || GET_MODE (target) != tmode
11829 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11830 target = gen_reg_rtx (tmode);
11832 /* In case the insn wants input operands in modes different from
11833 the result, abort. */
11834 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11835 abort ();
11837 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11838 op0 = copy_to_mode_reg (mode0, op0);
11839 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11840 op1 = copy_to_mode_reg (mode1, op1);
11842 pat = GEN_FCN (icode) (target, op0, op1);
11843 if (! pat)
11844 return 0;
11845 emit_insn (pat);
11846 return target;
11849 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11851 static rtx
11852 arm_expand_unop_builtin (enum insn_code icode,
11853 tree arglist, rtx target, int do_load)
11855 rtx pat;
11856 tree arg0 = TREE_VALUE (arglist);
11857 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11858 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11859 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11861 if (! target
11862 || GET_MODE (target) != tmode
11863 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11864 target = gen_reg_rtx (tmode);
11865 if (do_load)
11866 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
11867 else
11869 if (VECTOR_MODE_P (mode0))
11870 op0 = safe_vector_operand (op0, mode0);
11872 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11873 op0 = copy_to_mode_reg (mode0, op0);
11876 pat = GEN_FCN (icode) (target, op0);
11877 if (! pat)
11878 return 0;
11879 emit_insn (pat);
11880 return target;
11883 /* Expand an expression EXP that calls a built-in function,
11884 with result going to TARGET if that's convenient
11885 (and in mode MODE if that's convenient).
11886 SUBTARGET may be used as the target for computing one of EXP's operands.
11887 IGNORE is nonzero if the value is to be ignored. */
11889 static rtx
11890 arm_expand_builtin (tree exp,
11891 rtx target,
11892 rtx subtarget ATTRIBUTE_UNUSED,
11893 enum machine_mode mode ATTRIBUTE_UNUSED,
11894 int ignore ATTRIBUTE_UNUSED)
11896 const struct builtin_description * d;
11897 enum insn_code icode;
11898 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11899 tree arglist = TREE_OPERAND (exp, 1);
11900 tree arg0;
11901 tree arg1;
11902 tree arg2;
11903 rtx op0;
11904 rtx op1;
11905 rtx op2;
11906 rtx pat;
11907 int fcode = DECL_FUNCTION_CODE (fndecl);
11908 size_t i;
11909 enum machine_mode tmode;
11910 enum machine_mode mode0;
11911 enum machine_mode mode1;
11912 enum machine_mode mode2;
11914 switch (fcode)
11916 case ARM_BUILTIN_TEXTRMSB:
11917 case ARM_BUILTIN_TEXTRMUB:
11918 case ARM_BUILTIN_TEXTRMSH:
11919 case ARM_BUILTIN_TEXTRMUH:
11920 case ARM_BUILTIN_TEXTRMSW:
11921 case ARM_BUILTIN_TEXTRMUW:
11922 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11923 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11924 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11925 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11926 : CODE_FOR_iwmmxt_textrmw);
11928 arg0 = TREE_VALUE (arglist);
11929 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11930 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11931 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11932 tmode = insn_data[icode].operand[0].mode;
11933 mode0 = insn_data[icode].operand[1].mode;
11934 mode1 = insn_data[icode].operand[2].mode;
11936 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11937 op0 = copy_to_mode_reg (mode0, op0);
11938 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11940 /* @@@ better error message */
11941 error ("selector must be an immediate");
11942 return gen_reg_rtx (tmode);
11944 if (target == 0
11945 || GET_MODE (target) != tmode
11946 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11947 target = gen_reg_rtx (tmode);
11948 pat = GEN_FCN (icode) (target, op0, op1);
11949 if (! pat)
11950 return 0;
11951 emit_insn (pat);
11952 return target;
11954 case ARM_BUILTIN_TINSRB:
11955 case ARM_BUILTIN_TINSRH:
11956 case ARM_BUILTIN_TINSRW:
11957 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11958 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11959 : CODE_FOR_iwmmxt_tinsrw);
11960 arg0 = TREE_VALUE (arglist);
11961 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11962 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11963 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11964 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11965 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11966 tmode = insn_data[icode].operand[0].mode;
11967 mode0 = insn_data[icode].operand[1].mode;
11968 mode1 = insn_data[icode].operand[2].mode;
11969 mode2 = insn_data[icode].operand[3].mode;
11971 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11972 op0 = copy_to_mode_reg (mode0, op0);
11973 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11974 op1 = copy_to_mode_reg (mode1, op1);
11975 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11977 /* @@@ better error message */
11978 error ("selector must be an immediate");
11979 return const0_rtx;
11981 if (target == 0
11982 || GET_MODE (target) != tmode
11983 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11984 target = gen_reg_rtx (tmode);
11985 pat = GEN_FCN (icode) (target, op0, op1, op2);
11986 if (! pat)
11987 return 0;
11988 emit_insn (pat);
11989 return target;
11991 case ARM_BUILTIN_SETWCX:
11992 arg0 = TREE_VALUE (arglist);
11993 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11994 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
11995 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11996 emit_insn (gen_iwmmxt_tmcr (op1, op0));
11997 return 0;
11999 case ARM_BUILTIN_GETWCX:
12000 arg0 = TREE_VALUE (arglist);
12001 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12002 target = gen_reg_rtx (SImode);
12003 emit_insn (gen_iwmmxt_tmrc (target, op0));
12004 return target;
12006 case ARM_BUILTIN_WSHUFH:
12007 icode = CODE_FOR_iwmmxt_wshufh;
12008 arg0 = TREE_VALUE (arglist);
12009 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12010 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12011 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12012 tmode = insn_data[icode].operand[0].mode;
12013 mode1 = insn_data[icode].operand[1].mode;
12014 mode2 = insn_data[icode].operand[2].mode;
12016 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12017 op0 = copy_to_mode_reg (mode1, op0);
12018 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12020 /* @@@ better error message */
12021 error ("mask must be an immediate");
12022 return const0_rtx;
12024 if (target == 0
12025 || GET_MODE (target) != tmode
12026 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12027 target = gen_reg_rtx (tmode);
12028 pat = GEN_FCN (icode) (target, op0, op1);
12029 if (! pat)
12030 return 0;
12031 emit_insn (pat);
12032 return target;
12034 case ARM_BUILTIN_WSADB:
12035 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12036 case ARM_BUILTIN_WSADH:
12037 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12038 case ARM_BUILTIN_WSADBZ:
12039 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12040 case ARM_BUILTIN_WSADHZ:
12041 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12043 /* Several three-argument builtins. */
12044 case ARM_BUILTIN_WMACS:
12045 case ARM_BUILTIN_WMACU:
12046 case ARM_BUILTIN_WALIGN:
12047 case ARM_BUILTIN_TMIA:
12048 case ARM_BUILTIN_TMIAPH:
12049 case ARM_BUILTIN_TMIATT:
12050 case ARM_BUILTIN_TMIATB:
12051 case ARM_BUILTIN_TMIABT:
12052 case ARM_BUILTIN_TMIABB:
12053 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12054 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12055 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12056 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12057 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12058 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12059 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12060 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12061 : CODE_FOR_iwmmxt_walign);
12062 arg0 = TREE_VALUE (arglist);
12063 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12064 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12065 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12066 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12067 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12068 tmode = insn_data[icode].operand[0].mode;
12069 mode0 = insn_data[icode].operand[1].mode;
12070 mode1 = insn_data[icode].operand[2].mode;
12071 mode2 = insn_data[icode].operand[3].mode;
12073 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12074 op0 = copy_to_mode_reg (mode0, op0);
12075 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12076 op1 = copy_to_mode_reg (mode1, op1);
12077 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12078 op2 = copy_to_mode_reg (mode2, op2);
12079 if (target == 0
12080 || GET_MODE (target) != tmode
12081 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12082 target = gen_reg_rtx (tmode);
12083 pat = GEN_FCN (icode) (target, op0, op1, op2);
12084 if (! pat)
12085 return 0;
12086 emit_insn (pat);
12087 return target;
12089 case ARM_BUILTIN_WZERO:
12090 target = gen_reg_rtx (DImode);
12091 emit_insn (gen_iwmmxt_clrdi (target));
12092 return target;
12094 default:
12095 break;
12098 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12099 if (d->code == (const enum arm_builtins) fcode)
12100 return arm_expand_binop_builtin (d->icode, arglist, target);
12102 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12103 if (d->code == (const enum arm_builtins) fcode)
12104 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12106 /* @@@ Should really do something sensible here. */
12107 return NULL_RTX;
12110 /* Recursively search through all of the blocks in a function
12111 checking to see if any of the variables created in that
12112 function match the RTX called 'orig'. If they do then
12113 replace them with the RTX called 'new'. */
12114 static void
12115 replace_symbols_in_block (tree block, rtx orig, rtx new)
12117 for (; block; block = BLOCK_CHAIN (block))
12119 tree sym;
12121 if (!TREE_USED (block))
12122 continue;
12124 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12126 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12127 || DECL_IGNORED_P (sym)
12128 || TREE_CODE (sym) != VAR_DECL
12129 || DECL_EXTERNAL (sym)
12130 || !rtx_equal_p (DECL_RTL (sym), orig)
12132 continue;
12134 SET_DECL_RTL (sym, new);
12137 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12141 /* Return the number (counting from 0) of
12142 the least significant set bit in MASK. */
12144 inline static int
12145 number_of_first_bit_set (int mask)
12147 int bit;
12149 for (bit = 0;
12150 (mask & (1 << bit)) == 0;
12151 ++bit)
12152 continue;
12154 return bit;
12157 /* Generate code to return from a thumb function.
12158 If 'reg_containing_return_addr' is -1, then the return address is
12159 actually on the stack, at the stack pointer. */
12160 static void
12161 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12163 unsigned regs_available_for_popping;
12164 unsigned regs_to_pop;
12165 int pops_needed;
12166 unsigned available;
12167 unsigned required;
12168 int mode;
12169 int size;
12170 int restore_a4 = FALSE;
12172 /* Compute the registers we need to pop. */
12173 regs_to_pop = 0;
12174 pops_needed = 0;
12176 /* There is an assumption here, that if eh_ofs is not NULL, the
12177 normal return address will have been pushed. */
12178 if (reg_containing_return_addr == -1 || eh_ofs)
12180 /* When we are generating a return for __builtin_eh_return,
12181 reg_containing_return_addr must specify the return regno. */
12182 if (eh_ofs && reg_containing_return_addr == -1)
12183 abort ();
12185 regs_to_pop |= 1 << LR_REGNUM;
12186 ++pops_needed;
12189 if (TARGET_BACKTRACE)
12191 /* Restore the (ARM) frame pointer and stack pointer. */
12192 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12193 pops_needed += 2;
12196 /* If there is nothing to pop then just emit the BX instruction and
12197 return. */
12198 if (pops_needed == 0)
12200 if (eh_ofs)
12201 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12203 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12204 return;
12206 /* Otherwise if we are not supporting interworking and we have not created
12207 a backtrace structure and the function was not entered in ARM mode then
12208 just pop the return address straight into the PC. */
12209 else if (!TARGET_INTERWORK
12210 && !TARGET_BACKTRACE
12211 && !is_called_in_ARM_mode (current_function_decl))
12213 if (eh_ofs)
12215 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12216 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12217 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12219 else
12220 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12222 return;
12225 /* Find out how many of the (return) argument registers we can corrupt. */
12226 regs_available_for_popping = 0;
12228 /* If returning via __builtin_eh_return, the bottom three registers
12229 all contain information needed for the return. */
12230 if (eh_ofs)
12231 size = 12;
12232 else
12234 #ifdef RTX_CODE
12235 /* If we can deduce the registers used from the function's
12236 return value. This is more reliable that examining
12237 regs_ever_live[] because that will be set if the register is
12238 ever used in the function, not just if the register is used
12239 to hold a return value. */
12241 if (current_function_return_rtx != 0)
12242 mode = GET_MODE (current_function_return_rtx);
12243 else
12244 #endif
12245 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12247 size = GET_MODE_SIZE (mode);
12249 if (size == 0)
12251 /* In a void function we can use any argument register.
12252 In a function that returns a structure on the stack
12253 we can use the second and third argument registers. */
12254 if (mode == VOIDmode)
12255 regs_available_for_popping =
12256 (1 << ARG_REGISTER (1))
12257 | (1 << ARG_REGISTER (2))
12258 | (1 << ARG_REGISTER (3));
12259 else
12260 regs_available_for_popping =
12261 (1 << ARG_REGISTER (2))
12262 | (1 << ARG_REGISTER (3));
12264 else if (size <= 4)
12265 regs_available_for_popping =
12266 (1 << ARG_REGISTER (2))
12267 | (1 << ARG_REGISTER (3));
12268 else if (size <= 8)
12269 regs_available_for_popping =
12270 (1 << ARG_REGISTER (3));
12273 /* Match registers to be popped with registers into which we pop them. */
12274 for (available = regs_available_for_popping,
12275 required = regs_to_pop;
12276 required != 0 && available != 0;
12277 available &= ~(available & - available),
12278 required &= ~(required & - required))
12279 -- pops_needed;
12281 /* If we have any popping registers left over, remove them. */
12282 if (available > 0)
12283 regs_available_for_popping &= ~available;
12285 /* Otherwise if we need another popping register we can use
12286 the fourth argument register. */
12287 else if (pops_needed)
12289 /* If we have not found any free argument registers and
12290 reg a4 contains the return address, we must move it. */
12291 if (regs_available_for_popping == 0
12292 && reg_containing_return_addr == LAST_ARG_REGNUM)
12294 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12295 reg_containing_return_addr = LR_REGNUM;
12297 else if (size > 12)
12299 /* Register a4 is being used to hold part of the return value,
12300 but we have dire need of a free, low register. */
12301 restore_a4 = TRUE;
12303 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12306 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12308 /* The fourth argument register is available. */
12309 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12311 --pops_needed;
12315 /* Pop as many registers as we can. */
12316 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12317 regs_available_for_popping);
12319 /* Process the registers we popped. */
12320 if (reg_containing_return_addr == -1)
12322 /* The return address was popped into the lowest numbered register. */
12323 regs_to_pop &= ~(1 << LR_REGNUM);
12325 reg_containing_return_addr =
12326 number_of_first_bit_set (regs_available_for_popping);
12328 /* Remove this register for the mask of available registers, so that
12329 the return address will not be corrupted by further pops. */
12330 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12333 /* If we popped other registers then handle them here. */
12334 if (regs_available_for_popping)
12336 int frame_pointer;
12338 /* Work out which register currently contains the frame pointer. */
12339 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12341 /* Move it into the correct place. */
12342 asm_fprintf (f, "\tmov\t%r, %r\n",
12343 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12345 /* (Temporarily) remove it from the mask of popped registers. */
12346 regs_available_for_popping &= ~(1 << frame_pointer);
12347 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12349 if (regs_available_for_popping)
12351 int stack_pointer;
12353 /* We popped the stack pointer as well,
12354 find the register that contains it. */
12355 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12357 /* Move it into the stack register. */
12358 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12360 /* At this point we have popped all necessary registers, so
12361 do not worry about restoring regs_available_for_popping
12362 to its correct value:
12364 assert (pops_needed == 0)
12365 assert (regs_available_for_popping == (1 << frame_pointer))
12366 assert (regs_to_pop == (1 << STACK_POINTER)) */
12368 else
12370 /* Since we have just move the popped value into the frame
12371 pointer, the popping register is available for reuse, and
12372 we know that we still have the stack pointer left to pop. */
12373 regs_available_for_popping |= (1 << frame_pointer);
12377 /* If we still have registers left on the stack, but we no longer have
12378 any registers into which we can pop them, then we must move the return
12379 address into the link register and make available the register that
12380 contained it. */
12381 if (regs_available_for_popping == 0 && pops_needed > 0)
12383 regs_available_for_popping |= 1 << reg_containing_return_addr;
12385 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12386 reg_containing_return_addr);
12388 reg_containing_return_addr = LR_REGNUM;
12391 /* If we have registers left on the stack then pop some more.
12392 We know that at most we will want to pop FP and SP. */
12393 if (pops_needed > 0)
12395 int popped_into;
12396 int move_to;
12398 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12399 regs_available_for_popping);
12401 /* We have popped either FP or SP.
12402 Move whichever one it is into the correct register. */
12403 popped_into = number_of_first_bit_set (regs_available_for_popping);
12404 move_to = number_of_first_bit_set (regs_to_pop);
12406 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12408 regs_to_pop &= ~(1 << move_to);
12410 --pops_needed;
12413 /* If we still have not popped everything then we must have only
12414 had one register available to us and we are now popping the SP. */
12415 if (pops_needed > 0)
12417 int popped_into;
12419 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12420 regs_available_for_popping);
12422 popped_into = number_of_first_bit_set (regs_available_for_popping);
12424 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12426 assert (regs_to_pop == (1 << STACK_POINTER))
12427 assert (pops_needed == 1)
12431 /* If necessary restore the a4 register. */
12432 if (restore_a4)
12434 if (reg_containing_return_addr != LR_REGNUM)
12436 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12437 reg_containing_return_addr = LR_REGNUM;
12440 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12443 if (eh_ofs)
12444 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12446 /* Return to caller. */
12447 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12450 /* Emit code to push or pop registers to or from the stack. F is the
12451 assembly file. MASK is the registers to push or pop. PUSH is
12452 nonzero if we should push, and zero if we should pop. For debugging
12453 output, if pushing, adjust CFA_OFFSET by the amount of space added
12454 to the stack. REAL_REGS should have the same number of bits set as
12455 MASK, and will be used instead (in the same order) to describe which
12456 registers were saved - this is used to mark the save slots when we
12457 push high registers after moving them to low registers. */
12458 static void
12459 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12461 int regno;
12462 int lo_mask = mask & 0xFF;
12463 int pushed_words = 0;
12465 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12467 /* Special case. Do not generate a POP PC statement here, do it in
12468 thumb_exit() */
12469 thumb_exit (f, -1, NULL_RTX);
12470 return;
12473 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12475 /* Look at the low registers first. */
12476 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12478 if (lo_mask & 1)
12480 asm_fprintf (f, "%r", regno);
12482 if ((lo_mask & ~1) != 0)
12483 fprintf (f, ", ");
12485 pushed_words++;
12489 if (push && (mask & (1 << LR_REGNUM)))
12491 /* Catch pushing the LR. */
12492 if (mask & 0xFF)
12493 fprintf (f, ", ");
12495 asm_fprintf (f, "%r", LR_REGNUM);
12497 pushed_words++;
12499 else if (!push && (mask & (1 << PC_REGNUM)))
12501 /* Catch popping the PC. */
12502 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12504 /* The PC is never poped directly, instead
12505 it is popped into r3 and then BX is used. */
12506 fprintf (f, "}\n");
12508 thumb_exit (f, -1, NULL_RTX);
12510 return;
12512 else
12514 if (mask & 0xFF)
12515 fprintf (f, ", ");
12517 asm_fprintf (f, "%r", PC_REGNUM);
12521 fprintf (f, "}\n");
12523 if (push && pushed_words && dwarf2out_do_frame ())
12525 char *l = dwarf2out_cfi_label ();
12526 int pushed_mask = real_regs;
12528 *cfa_offset += pushed_words * 4;
12529 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12531 pushed_words = 0;
12532 pushed_mask = real_regs;
12533 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12535 if (pushed_mask & 1)
12536 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12541 void
12542 thumb_final_prescan_insn (rtx insn)
12544 if (flag_print_asm_name)
12545 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12546 INSN_ADDRESSES (INSN_UID (insn)));
12550 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12552 unsigned HOST_WIDE_INT mask = 0xff;
12553 int i;
12555 if (val == 0) /* XXX */
12556 return 0;
12558 for (i = 0; i < 25; i++)
12559 if ((val & (mask << i)) == val)
12560 return 1;
12562 return 0;
12565 /* Returns nonzero if the current function contains,
12566 or might contain a far jump. */
12568 thumb_far_jump_used_p (int in_prologue)
12570 rtx insn;
12572 /* This test is only important for leaf functions. */
12573 /* assert (!leaf_function_p ()); */
12575 /* If we have already decided that far jumps may be used,
12576 do not bother checking again, and always return true even if
12577 it turns out that they are not being used. Once we have made
12578 the decision that far jumps are present (and that hence the link
12579 register will be pushed onto the stack) we cannot go back on it. */
12580 if (cfun->machine->far_jump_used)
12581 return 1;
12583 /* If this function is not being called from the prologue/epilogue
12584 generation code then it must be being called from the
12585 INITIAL_ELIMINATION_OFFSET macro. */
12586 if (!in_prologue)
12588 /* In this case we know that we are being asked about the elimination
12589 of the arg pointer register. If that register is not being used,
12590 then there are no arguments on the stack, and we do not have to
12591 worry that a far jump might force the prologue to push the link
12592 register, changing the stack offsets. In this case we can just
12593 return false, since the presence of far jumps in the function will
12594 not affect stack offsets.
12596 If the arg pointer is live (or if it was live, but has now been
12597 eliminated and so set to dead) then we do have to test to see if
12598 the function might contain a far jump. This test can lead to some
12599 false negatives, since before reload is completed, then length of
12600 branch instructions is not known, so gcc defaults to returning their
12601 longest length, which in turn sets the far jump attribute to true.
12603 A false negative will not result in bad code being generated, but it
12604 will result in a needless push and pop of the link register. We
12605 hope that this does not occur too often. */
12606 if (regs_ever_live [ARG_POINTER_REGNUM])
12607 cfun->machine->arg_pointer_live = 1;
12608 else if (!cfun->machine->arg_pointer_live)
12609 return 0;
12612 /* Check to see if the function contains a branch
12613 insn with the far jump attribute set. */
12614 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12616 if (GET_CODE (insn) == JUMP_INSN
12617 /* Ignore tablejump patterns. */
12618 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12619 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12620 && get_attr_far_jump (insn) == FAR_JUMP_YES
12623 /* Record the fact that we have decided that
12624 the function does use far jumps. */
12625 cfun->machine->far_jump_used = 1;
12626 return 1;
12630 return 0;
12633 /* Return nonzero if FUNC must be entered in ARM mode. */
12635 is_called_in_ARM_mode (tree func)
12637 if (TREE_CODE (func) != FUNCTION_DECL)
12638 abort ();
12640 /* Ignore the problem about functions whoes address is taken. */
12641 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12642 return TRUE;
12644 #ifdef ARM_PE
12645 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12646 #else
12647 return FALSE;
12648 #endif
12651 /* The bits which aren't usefully expanded as rtl. */
12652 const char *
12653 thumb_unexpanded_epilogue (void)
12655 int regno;
12656 int live_regs_mask = 0;
12657 int high_regs_pushed = 0;
12658 int leaf_function = leaf_function_p ();
12659 int had_to_push_lr;
12660 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12662 if (return_used_this_function)
12663 return "";
12665 if (IS_NAKED (arm_current_func_type ()))
12666 return "";
12668 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12669 if (THUMB_REG_PUSHED_P (regno))
12670 live_regs_mask |= 1 << regno;
12672 for (regno = 8; regno < 13; regno++)
12673 if (THUMB_REG_PUSHED_P (regno))
12674 high_regs_pushed++;
12676 /* The prolog may have pushed some high registers to use as
12677 work registers. eg the testsuite file:
12678 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12679 compiles to produce:
12680 push {r4, r5, r6, r7, lr}
12681 mov r7, r9
12682 mov r6, r8
12683 push {r6, r7}
12684 as part of the prolog. We have to undo that pushing here. */
12686 if (high_regs_pushed)
12688 int mask = live_regs_mask;
12689 int next_hi_reg;
12690 int size;
12691 int mode;
12693 #ifdef RTX_CODE
12694 /* If we can deduce the registers used from the function's return value.
12695 This is more reliable that examining regs_ever_live[] because that
12696 will be set if the register is ever used in the function, not just if
12697 the register is used to hold a return value. */
12699 if (current_function_return_rtx != 0)
12700 mode = GET_MODE (current_function_return_rtx);
12701 else
12702 #endif
12703 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12705 size = GET_MODE_SIZE (mode);
12707 /* Unless we are returning a type of size > 12 register r3 is
12708 available. */
12709 if (size < 13)
12710 mask |= 1 << 3;
12712 if (mask == 0)
12713 /* Oh dear! We have no low registers into which we can pop
12714 high registers! */
12715 internal_error
12716 ("no low registers available for popping high registers");
12718 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12719 if (THUMB_REG_PUSHED_P (next_hi_reg))
12720 break;
12722 while (high_regs_pushed)
12724 /* Find lo register(s) into which the high register(s) can
12725 be popped. */
12726 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12728 if (mask & (1 << regno))
12729 high_regs_pushed--;
12730 if (high_regs_pushed == 0)
12731 break;
12734 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12736 /* Pop the values into the low register(s). */
12737 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12739 /* Move the value(s) into the high registers. */
12740 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12742 if (mask & (1 << regno))
12744 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12745 regno);
12747 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12748 if (THUMB_REG_PUSHED_P (next_hi_reg))
12749 break;
12755 had_to_push_lr = (live_regs_mask || !leaf_function
12756 || thumb_far_jump_used_p (1));
12758 if (TARGET_BACKTRACE
12759 && ((live_regs_mask & 0xFF) == 0)
12760 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12762 /* The stack backtrace structure creation code had to
12763 push R7 in order to get a work register, so we pop
12764 it now. */
12765 live_regs_mask |= (1 << LAST_LO_REGNUM);
12768 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12770 if (had_to_push_lr
12771 && !is_called_in_ARM_mode (current_function_decl)
12772 && !eh_ofs)
12773 live_regs_mask |= 1 << PC_REGNUM;
12775 /* Either no argument registers were pushed or a backtrace
12776 structure was created which includes an adjusted stack
12777 pointer, so just pop everything. */
12778 if (live_regs_mask)
12779 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12780 live_regs_mask);
12782 if (eh_ofs)
12783 thumb_exit (asm_out_file, 2, eh_ofs);
12784 /* We have either just popped the return address into the
12785 PC or it is was kept in LR for the entire function or
12786 it is still on the stack because we do not want to
12787 return by doing a pop {pc}. */
12788 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
12789 thumb_exit (asm_out_file,
12790 (had_to_push_lr
12791 && is_called_in_ARM_mode (current_function_decl)) ?
12792 -1 : LR_REGNUM, NULL_RTX);
12794 else
12796 /* Pop everything but the return address. */
12797 live_regs_mask &= ~(1 << PC_REGNUM);
12799 if (live_regs_mask)
12800 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12801 live_regs_mask);
12803 if (had_to_push_lr)
12804 /* Get the return address into a temporary register. */
12805 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12806 1 << LAST_ARG_REGNUM);
12808 /* Remove the argument registers that were pushed onto the stack. */
12809 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12810 SP_REGNUM, SP_REGNUM,
12811 current_function_pretend_args_size);
12813 if (eh_ofs)
12814 thumb_exit (asm_out_file, 2, eh_ofs);
12815 else
12816 thumb_exit (asm_out_file,
12817 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
12820 return "";
12823 /* Functions to save and restore machine-specific function data. */
12824 static struct machine_function *
12825 arm_init_machine_status (void)
12827 struct machine_function *machine;
12828 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12830 #if ARM_FT_UNKNOWN != 0
12831 machine->func_type = ARM_FT_UNKNOWN;
12832 #endif
12833 return machine;
12836 /* Return an RTX indicating where the return address to the
12837 calling function can be found. */
12839 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12841 if (count != 0)
12842 return NULL_RTX;
12844 if (TARGET_APCS_32)
12845 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12846 else
12848 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
12849 GEN_INT (RETURN_ADDR_MASK26));
12850 return get_func_hard_reg_initial_val (cfun, lr);
12854 /* Do anything needed before RTL is emitted for each function. */
12855 void
12856 arm_init_expanders (void)
12858 /* Arrange to initialize and mark the machine per-function status. */
12859 init_machine_status = arm_init_machine_status;
12862 HOST_WIDE_INT
12863 thumb_get_frame_size (void)
12865 int regno;
12867 int base_size = ROUND_UP_WORD (get_frame_size ());
12868 int count_regs = 0;
12869 int entry_size = 0;
12870 int leaf;
12872 if (! TARGET_THUMB)
12873 abort ();
12875 if (! TARGET_ATPCS)
12876 return base_size;
12878 /* We need to know if we are a leaf function. Unfortunately, it
12879 is possible to be called after start_sequence has been called,
12880 which causes get_insns to return the insns for the sequence,
12881 not the function, which will cause leaf_function_p to return
12882 the incorrect result.
12884 To work around this, we cache the computed frame size. This
12885 works because we will only be calling RTL expanders that need
12886 to know about leaf functions once reload has completed, and the
12887 frame size cannot be changed after that time, so we can safely
12888 use the cached value. */
12890 if (reload_completed)
12891 return cfun->machine->frame_size;
12893 leaf = leaf_function_p ();
12895 /* A leaf function does not need any stack alignment if it has nothing
12896 on the stack. */
12897 if (leaf && base_size == 0)
12899 cfun->machine->frame_size = 0;
12900 return 0;
12903 /* We know that SP will be word aligned on entry, and we must
12904 preserve that condition at any subroutine call. But those are
12905 the only constraints. */
12907 /* Space for variadic functions. */
12908 if (current_function_pretend_args_size)
12909 entry_size += current_function_pretend_args_size;
12911 /* Space for pushed lo registers. */
12912 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12913 if (THUMB_REG_PUSHED_P (regno))
12914 count_regs++;
12916 /* Space for backtrace structure. */
12917 if (TARGET_BACKTRACE)
12919 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
12920 entry_size += 20;
12921 else
12922 entry_size += 16;
12925 if (count_regs || !leaf || thumb_far_jump_used_p (1))
12926 count_regs++; /* LR */
12928 entry_size += count_regs * 4;
12929 count_regs = 0;
12931 /* Space for pushed hi regs. */
12932 for (regno = 8; regno < 13; regno++)
12933 if (THUMB_REG_PUSHED_P (regno))
12934 count_regs++;
12936 entry_size += count_regs * 4;
12938 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12939 base_size += 4;
12940 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12941 abort ();
12943 cfun->machine->frame_size = base_size;
12945 return base_size;
12948 /* Generate the rest of a function's prologue. */
12949 void
12950 thumb_expand_prologue (void)
12952 rtx insn, dwarf;
12954 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12955 + current_function_outgoing_args_size);
12956 unsigned long func_type;
12958 func_type = arm_current_func_type ();
12960 /* Naked functions don't have prologues. */
12961 if (IS_NAKED (func_type))
12962 return;
12964 if (IS_INTERRUPT (func_type))
12966 error ("interrupt Service Routines cannot be coded in Thumb mode");
12967 return;
12970 if (frame_pointer_needed)
12972 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
12973 RTX_FRAME_RELATED_P (insn) = 1;
12976 if (amount)
12978 amount = ROUND_UP_WORD (amount);
12980 if (amount < 512)
12982 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12983 GEN_INT (- amount)));
12984 RTX_FRAME_RELATED_P (insn) = 1;
12986 else
12988 int regno;
12989 rtx reg;
12991 /* The stack decrement is too big for an immediate value in a single
12992 insn. In theory we could issue multiple subtracts, but after
12993 three of them it becomes more space efficient to place the full
12994 value in the constant pool and load into a register. (Also the
12995 ARM debugger really likes to see only one stack decrement per
12996 function). So instead we look for a scratch register into which
12997 we can load the decrement, and then we subtract this from the
12998 stack pointer. Unfortunately on the thumb the only available
12999 scratch registers are the argument registers, and we cannot use
13000 these as they may hold arguments to the function. Instead we
13001 attempt to locate a call preserved register which is used by this
13002 function. If we can find one, then we know that it will have
13003 been pushed at the start of the prologue and so we can corrupt
13004 it now. */
13005 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13006 if (THUMB_REG_PUSHED_P (regno)
13007 && !(frame_pointer_needed
13008 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13009 break;
13011 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13013 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13015 /* Choose an arbitrary, non-argument low register. */
13016 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13018 /* Save it by copying it into a high, scratch register. */
13019 emit_insn (gen_movsi (spare, reg));
13020 /* Add a USE to stop propagate_one_insn() from barfing. */
13021 emit_insn (gen_prologue_use (spare));
13023 /* Decrement the stack. */
13024 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13025 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13026 stack_pointer_rtx, reg));
13027 RTX_FRAME_RELATED_P (insn) = 1;
13028 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13029 plus_constant (stack_pointer_rtx,
13030 GEN_INT (- amount)));
13031 RTX_FRAME_RELATED_P (dwarf) = 1;
13032 REG_NOTES (insn)
13033 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13034 REG_NOTES (insn));
13036 /* Restore the low register's original value. */
13037 emit_insn (gen_movsi (reg, spare));
13039 /* Emit a USE of the restored scratch register, so that flow
13040 analysis will not consider the restore redundant. The
13041 register won't be used again in this function and isn't
13042 restored by the epilogue. */
13043 emit_insn (gen_prologue_use (reg));
13045 else
13047 reg = gen_rtx_REG (SImode, regno);
13049 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13051 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13052 stack_pointer_rtx, reg));
13053 RTX_FRAME_RELATED_P (insn) = 1;
13054 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13055 plus_constant (stack_pointer_rtx,
13056 GEN_INT (- amount)));
13057 RTX_FRAME_RELATED_P (dwarf) = 1;
13058 REG_NOTES (insn)
13059 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13060 REG_NOTES (insn));
13065 if (current_function_profile || TARGET_NO_SCHED_PRO)
13066 emit_insn (gen_blockage ());
13069 void
13070 thumb_expand_epilogue (void)
13072 HOST_WIDE_INT amount = (thumb_get_frame_size ()
13073 + current_function_outgoing_args_size);
13074 int regno;
13076 /* Naked functions don't have prologues. */
13077 if (IS_NAKED (arm_current_func_type ()))
13078 return;
13080 if (frame_pointer_needed)
13081 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13082 else if (amount)
13084 amount = ROUND_UP_WORD (amount);
13086 if (amount < 512)
13087 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13088 GEN_INT (amount)));
13089 else
13091 /* r3 is always free in the epilogue. */
13092 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13094 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13095 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13099 /* Emit a USE (stack_pointer_rtx), so that
13100 the stack adjustment will not be deleted. */
13101 emit_insn (gen_prologue_use (stack_pointer_rtx));
13103 if (current_function_profile || TARGET_NO_SCHED_PRO)
13104 emit_insn (gen_blockage ());
13106 /* Emit a clobber for each insn that will be restored in the epilogue,
13107 so that flow2 will get register lifetimes correct. */
13108 for (regno = 0; regno < 13; regno++)
13109 if (regs_ever_live[regno] && !call_used_regs[regno])
13110 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13112 if (! regs_ever_live[LR_REGNUM])
13113 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13116 static void
13117 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13119 int live_regs_mask = 0;
13120 int high_regs_pushed = 0;
13121 int cfa_offset = 0;
13122 int regno;
13124 if (IS_NAKED (arm_current_func_type ()))
13125 return;
13127 if (is_called_in_ARM_mode (current_function_decl))
13129 const char * name;
13131 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13132 abort ();
13133 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13134 abort ();
13135 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13137 /* Generate code sequence to switch us into Thumb mode. */
13138 /* The .code 32 directive has already been emitted by
13139 ASM_DECLARE_FUNCTION_NAME. */
13140 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13141 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13143 /* Generate a label, so that the debugger will notice the
13144 change in instruction sets. This label is also used by
13145 the assembler to bypass the ARM code when this function
13146 is called from a Thumb encoded function elsewhere in the
13147 same file. Hence the definition of STUB_NAME here must
13148 agree with the definition in gas/config/tc-arm.c. */
13150 #define STUB_NAME ".real_start_of"
13152 fprintf (f, "\t.code\t16\n");
13153 #ifdef ARM_PE
13154 if (arm_dllexport_name_p (name))
13155 name = arm_strip_name_encoding (name);
13156 #endif
13157 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13158 fprintf (f, "\t.thumb_func\n");
13159 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13162 if (current_function_pretend_args_size)
13164 if (cfun->machine->uses_anonymous_args)
13166 int num_pushes;
13168 fprintf (f, "\tpush\t{");
13170 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13172 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13173 regno <= LAST_ARG_REGNUM;
13174 regno++)
13175 asm_fprintf (f, "%r%s", regno,
13176 regno == LAST_ARG_REGNUM ? "" : ", ");
13178 fprintf (f, "}\n");
13180 else
13181 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13182 SP_REGNUM, SP_REGNUM,
13183 current_function_pretend_args_size);
13185 /* We don't need to record the stores for unwinding (would it
13186 help the debugger any if we did?), but record the change in
13187 the stack pointer. */
13188 if (dwarf2out_do_frame ())
13190 char *l = dwarf2out_cfi_label ();
13191 cfa_offset = cfa_offset + current_function_pretend_args_size;
13192 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13196 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13197 if (THUMB_REG_PUSHED_P (regno))
13198 live_regs_mask |= 1 << regno;
13200 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
13201 live_regs_mask |= 1 << LR_REGNUM;
13203 if (TARGET_BACKTRACE)
13205 int offset;
13206 int work_register = 0;
13207 int wr;
13209 /* We have been asked to create a stack backtrace structure.
13210 The code looks like this:
13212 0 .align 2
13213 0 func:
13214 0 sub SP, #16 Reserve space for 4 registers.
13215 2 push {R7} Get a work register.
13216 4 add R7, SP, #20 Get the stack pointer before the push.
13217 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13218 8 mov R7, PC Get hold of the start of this code plus 12.
13219 10 str R7, [SP, #16] Store it.
13220 12 mov R7, FP Get hold of the current frame pointer.
13221 14 str R7, [SP, #4] Store it.
13222 16 mov R7, LR Get hold of the current return address.
13223 18 str R7, [SP, #12] Store it.
13224 20 add R7, SP, #16 Point at the start of the backtrace structure.
13225 22 mov FP, R7 Put this value into the frame pointer. */
13227 if ((live_regs_mask & 0xFF) == 0)
13229 /* See if the a4 register is free. */
13231 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13232 work_register = LAST_ARG_REGNUM;
13233 else /* We must push a register of our own. */
13234 live_regs_mask |= (1 << LAST_LO_REGNUM);
13237 if (work_register == 0)
13239 /* Select a register from the list that will be pushed to
13240 use as our work register. */
13241 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13242 if ((1 << work_register) & live_regs_mask)
13243 break;
13246 asm_fprintf
13247 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13248 SP_REGNUM, SP_REGNUM);
13250 if (dwarf2out_do_frame ())
13252 char *l = dwarf2out_cfi_label ();
13253 cfa_offset = cfa_offset + 16;
13254 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13257 if (live_regs_mask)
13258 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13260 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13261 if (wr & live_regs_mask)
13262 offset += 4;
13264 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13265 offset + 16 + current_function_pretend_args_size);
13267 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13268 offset + 4);
13270 /* Make sure that the instruction fetching the PC is in the right place
13271 to calculate "start of backtrace creation code + 12". */
13272 if (live_regs_mask)
13274 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13275 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13276 offset + 12);
13277 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13278 ARM_HARD_FRAME_POINTER_REGNUM);
13279 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13280 offset);
13282 else
13284 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13285 ARM_HARD_FRAME_POINTER_REGNUM);
13286 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13287 offset);
13288 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13289 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13290 offset + 12);
13293 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13294 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13295 offset + 8);
13296 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13297 offset + 12);
13298 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13299 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13301 else if (live_regs_mask)
13302 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13304 for (regno = 8; regno < 13; regno++)
13305 if (THUMB_REG_PUSHED_P (regno))
13306 high_regs_pushed++;
13308 if (high_regs_pushed)
13310 int pushable_regs = 0;
13311 int mask = live_regs_mask & 0xff;
13312 int next_hi_reg;
13314 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13315 if (THUMB_REG_PUSHED_P (next_hi_reg))
13316 break;
13318 pushable_regs = mask;
13320 if (pushable_regs == 0)
13322 /* Desperation time -- this probably will never happen. */
13323 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13324 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13325 mask = 1 << LAST_ARG_REGNUM;
13328 while (high_regs_pushed > 0)
13330 int real_regs_mask = 0;
13332 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13334 if (mask & (1 << regno))
13336 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13338 high_regs_pushed--;
13339 real_regs_mask |= (1 << next_hi_reg);
13341 if (high_regs_pushed)
13343 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13344 next_hi_reg--)
13345 if (THUMB_REG_PUSHED_P (next_hi_reg))
13346 break;
13348 else
13350 mask &= ~((1 << regno) - 1);
13351 break;
13356 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13359 if (pushable_regs == 0
13360 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13361 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13365 /* Handle the case of a double word load into a low register from
13366 a computed memory address. The computed address may involve a
13367 register which is overwritten by the load. */
13368 const char *
13369 thumb_load_double_from_address (rtx *operands)
13371 rtx addr;
13372 rtx base;
13373 rtx offset;
13374 rtx arg1;
13375 rtx arg2;
13377 if (GET_CODE (operands[0]) != REG)
13378 abort ();
13380 if (GET_CODE (operands[1]) != MEM)
13381 abort ();
13383 /* Get the memory address. */
13384 addr = XEXP (operands[1], 0);
13386 /* Work out how the memory address is computed. */
13387 switch (GET_CODE (addr))
13389 case REG:
13390 operands[2] = gen_rtx_MEM (SImode,
13391 plus_constant (XEXP (operands[1], 0), 4));
13393 if (REGNO (operands[0]) == REGNO (addr))
13395 output_asm_insn ("ldr\t%H0, %2", operands);
13396 output_asm_insn ("ldr\t%0, %1", operands);
13398 else
13400 output_asm_insn ("ldr\t%0, %1", operands);
13401 output_asm_insn ("ldr\t%H0, %2", operands);
13403 break;
13405 case CONST:
13406 /* Compute <address> + 4 for the high order load. */
13407 operands[2] = gen_rtx_MEM (SImode,
13408 plus_constant (XEXP (operands[1], 0), 4));
13410 output_asm_insn ("ldr\t%0, %1", operands);
13411 output_asm_insn ("ldr\t%H0, %2", operands);
13412 break;
13414 case PLUS:
13415 arg1 = XEXP (addr, 0);
13416 arg2 = XEXP (addr, 1);
13418 if (CONSTANT_P (arg1))
13419 base = arg2, offset = arg1;
13420 else
13421 base = arg1, offset = arg2;
13423 if (GET_CODE (base) != REG)
13424 abort ();
13426 /* Catch the case of <address> = <reg> + <reg> */
13427 if (GET_CODE (offset) == REG)
13429 int reg_offset = REGNO (offset);
13430 int reg_base = REGNO (base);
13431 int reg_dest = REGNO (operands[0]);
13433 /* Add the base and offset registers together into the
13434 higher destination register. */
13435 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13436 reg_dest + 1, reg_base, reg_offset);
13438 /* Load the lower destination register from the address in
13439 the higher destination register. */
13440 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13441 reg_dest, reg_dest + 1);
13443 /* Load the higher destination register from its own address
13444 plus 4. */
13445 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13446 reg_dest + 1, reg_dest + 1);
13448 else
13450 /* Compute <address> + 4 for the high order load. */
13451 operands[2] = gen_rtx_MEM (SImode,
13452 plus_constant (XEXP (operands[1], 0), 4));
13454 /* If the computed address is held in the low order register
13455 then load the high order register first, otherwise always
13456 load the low order register first. */
13457 if (REGNO (operands[0]) == REGNO (base))
13459 output_asm_insn ("ldr\t%H0, %2", operands);
13460 output_asm_insn ("ldr\t%0, %1", operands);
13462 else
13464 output_asm_insn ("ldr\t%0, %1", operands);
13465 output_asm_insn ("ldr\t%H0, %2", operands);
13468 break;
13470 case LABEL_REF:
13471 /* With no registers to worry about we can just load the value
13472 directly. */
13473 operands[2] = gen_rtx_MEM (SImode,
13474 plus_constant (XEXP (operands[1], 0), 4));
13476 output_asm_insn ("ldr\t%H0, %2", operands);
13477 output_asm_insn ("ldr\t%0, %1", operands);
13478 break;
13480 default:
13481 abort ();
13482 break;
13485 return "";
13488 const char *
13489 thumb_output_move_mem_multiple (int n, rtx *operands)
13491 rtx tmp;
13493 switch (n)
13495 case 2:
13496 if (REGNO (operands[4]) > REGNO (operands[5]))
13498 tmp = operands[4];
13499 operands[4] = operands[5];
13500 operands[5] = tmp;
13502 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13503 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13504 break;
13506 case 3:
13507 if (REGNO (operands[4]) > REGNO (operands[5]))
13509 tmp = operands[4];
13510 operands[4] = operands[5];
13511 operands[5] = tmp;
13513 if (REGNO (operands[5]) > REGNO (operands[6]))
13515 tmp = operands[5];
13516 operands[5] = operands[6];
13517 operands[6] = tmp;
13519 if (REGNO (operands[4]) > REGNO (operands[5]))
13521 tmp = operands[4];
13522 operands[4] = operands[5];
13523 operands[5] = tmp;
13526 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13527 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13528 break;
13530 default:
13531 abort ();
13534 return "";
13537 /* Routines for generating rtl. */
13538 void
13539 thumb_expand_movstrqi (rtx *operands)
13541 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13542 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13543 HOST_WIDE_INT len = INTVAL (operands[2]);
13544 HOST_WIDE_INT offset = 0;
13546 while (len >= 12)
13548 emit_insn (gen_movmem12b (out, in, out, in));
13549 len -= 12;
13552 if (len >= 8)
13554 emit_insn (gen_movmem8b (out, in, out, in));
13555 len -= 8;
13558 if (len >= 4)
13560 rtx reg = gen_reg_rtx (SImode);
13561 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13562 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13563 len -= 4;
13564 offset += 4;
13567 if (len >= 2)
13569 rtx reg = gen_reg_rtx (HImode);
13570 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13571 plus_constant (in, offset))));
13572 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13573 reg));
13574 len -= 2;
13575 offset += 2;
13578 if (len)
13580 rtx reg = gen_reg_rtx (QImode);
13581 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13582 plus_constant (in, offset))));
13583 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13584 reg));
13589 thumb_cmp_operand (rtx op, enum machine_mode mode)
13591 return ((GET_CODE (op) == CONST_INT
13592 && INTVAL (op) < 256
13593 && INTVAL (op) >= 0)
13594 || s_register_operand (op, mode));
13598 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13600 return (GET_CODE (op) == CONST_INT
13601 && INTVAL (op) < 0
13602 && INTVAL (op) > -256);
13605 /* Return TRUE if a result can be stored in OP without clobbering the
13606 condition code register. Prior to reload we only accept a
13607 register. After reload we have to be able to handle memory as
13608 well, since a pseudo may not get a hard reg and reload cannot
13609 handle output-reloads on jump insns.
13611 We could possibly handle mem before reload as well, but that might
13612 complicate things with the need to handle increment
13613 side-effects. */
13616 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13618 return (s_register_operand (op, mode)
13619 || ((reload_in_progress || reload_completed)
13620 && memory_operand (op, mode)));
13623 /* Handle storing a half-word to memory during reload. */
13624 void
13625 thumb_reload_out_hi (rtx *operands)
13627 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13630 /* Handle reading a half-word from memory during reload. */
13631 void
13632 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13634 abort ();
13637 /* Return the length of a function name prefix
13638 that starts with the character 'c'. */
13639 static int
13640 arm_get_strip_length (int c)
13642 switch (c)
13644 ARM_NAME_ENCODING_LENGTHS
13645 default: return 0;
13649 /* Return a pointer to a function's name with any
13650 and all prefix encodings stripped from it. */
13651 const char *
13652 arm_strip_name_encoding (const char *name)
13654 int skip;
13656 while ((skip = arm_get_strip_length (* name)))
13657 name += skip;
13659 return name;
13662 /* If there is a '*' anywhere in the name's prefix, then
13663 emit the stripped name verbatim, otherwise prepend an
13664 underscore if leading underscores are being used. */
13665 void
13666 arm_asm_output_labelref (FILE *stream, const char *name)
13668 int skip;
13669 int verbatim = 0;
13671 while ((skip = arm_get_strip_length (* name)))
13673 verbatim |= (*name == '*');
13674 name += skip;
13677 if (verbatim)
13678 fputs (name, stream);
13679 else
13680 asm_fprintf (stream, "%U%s", name);
13683 rtx aof_pic_label;
13685 #ifdef AOF_ASSEMBLER
13686 /* Special functions only needed when producing AOF syntax assembler. */
13688 struct pic_chain
13690 struct pic_chain * next;
13691 const char * symname;
13694 static struct pic_chain * aof_pic_chain = NULL;
13697 aof_pic_entry (rtx x)
13699 struct pic_chain ** chainp;
13700 int offset;
13702 if (aof_pic_label == NULL_RTX)
13704 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13707 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13708 offset += 4, chainp = &(*chainp)->next)
13709 if ((*chainp)->symname == XSTR (x, 0))
13710 return plus_constant (aof_pic_label, offset);
13712 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13713 (*chainp)->next = NULL;
13714 (*chainp)->symname = XSTR (x, 0);
13715 return plus_constant (aof_pic_label, offset);
13718 void
13719 aof_dump_pic_table (FILE *f)
13721 struct pic_chain * chain;
13723 if (aof_pic_chain == NULL)
13724 return;
13726 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13727 PIC_OFFSET_TABLE_REGNUM,
13728 PIC_OFFSET_TABLE_REGNUM);
13729 fputs ("|x$adcons|\n", f);
13731 for (chain = aof_pic_chain; chain; chain = chain->next)
13733 fputs ("\tDCD\t", f);
13734 assemble_name (f, chain->symname);
13735 fputs ("\n", f);
13739 int arm_text_section_count = 1;
13741 char *
13742 aof_text_section (void )
13744 static char buf[100];
13745 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13746 arm_text_section_count++);
13747 if (flag_pic)
13748 strcat (buf, ", PIC, REENTRANT");
13749 return buf;
13752 static int arm_data_section_count = 1;
13754 char *
13755 aof_data_section (void)
13757 static char buf[100];
13758 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13759 return buf;
13762 /* The AOF assembler is religiously strict about declarations of
13763 imported and exported symbols, so that it is impossible to declare
13764 a function as imported near the beginning of the file, and then to
13765 export it later on. It is, however, possible to delay the decision
13766 until all the functions in the file have been compiled. To get
13767 around this, we maintain a list of the imports and exports, and
13768 delete from it any that are subsequently defined. At the end of
13769 compilation we spit the remainder of the list out before the END
13770 directive. */
13772 struct import
13774 struct import * next;
13775 const char * name;
13778 static struct import * imports_list = NULL;
13780 void
13781 aof_add_import (const char *name)
13783 struct import * new;
13785 for (new = imports_list; new; new = new->next)
13786 if (new->name == name)
13787 return;
13789 new = (struct import *) xmalloc (sizeof (struct import));
13790 new->next = imports_list;
13791 imports_list = new;
13792 new->name = name;
13795 void
13796 aof_delete_import (const char *name)
13798 struct import ** old;
13800 for (old = &imports_list; *old; old = & (*old)->next)
13802 if ((*old)->name == name)
13804 *old = (*old)->next;
13805 return;
13810 int arm_main_function = 0;
13812 static void
13813 aof_dump_imports (FILE *f)
13815 /* The AOF assembler needs this to cause the startup code to be extracted
13816 from the library. Brining in __main causes the whole thing to work
13817 automagically. */
13818 if (arm_main_function)
13820 text_section ();
13821 fputs ("\tIMPORT __main\n", f);
13822 fputs ("\tDCD __main\n", f);
13825 /* Now dump the remaining imports. */
13826 while (imports_list)
13828 fprintf (f, "\tIMPORT\t");
13829 assemble_name (f, imports_list->name);
13830 fputc ('\n', f);
13831 imports_list = imports_list->next;
13835 static void
13836 aof_globalize_label (FILE *stream, const char *name)
13838 default_globalize_label (stream, name);
13839 if (! strcmp (name, "main"))
13840 arm_main_function = 1;
13843 static void
13844 aof_file_start (void)
13846 fputs ("__r0\tRN\t0\n", asm_out_file);
13847 fputs ("__a1\tRN\t0\n", asm_out_file);
13848 fputs ("__a2\tRN\t1\n", asm_out_file);
13849 fputs ("__a3\tRN\t2\n", asm_out_file);
13850 fputs ("__a4\tRN\t3\n", asm_out_file);
13851 fputs ("__v1\tRN\t4\n", asm_out_file);
13852 fputs ("__v2\tRN\t5\n", asm_out_file);
13853 fputs ("__v3\tRN\t6\n", asm_out_file);
13854 fputs ("__v4\tRN\t7\n", asm_out_file);
13855 fputs ("__v5\tRN\t8\n", asm_out_file);
13856 fputs ("__v6\tRN\t9\n", asm_out_file);
13857 fputs ("__sl\tRN\t10\n", asm_out_file);
13858 fputs ("__fp\tRN\t11\n", asm_out_file);
13859 fputs ("__ip\tRN\t12\n", asm_out_file);
13860 fputs ("__sp\tRN\t13\n", asm_out_file);
13861 fputs ("__lr\tRN\t14\n", asm_out_file);
13862 fputs ("__pc\tRN\t15\n", asm_out_file);
13863 fputs ("__f0\tFN\t0\n", asm_out_file);
13864 fputs ("__f1\tFN\t1\n", asm_out_file);
13865 fputs ("__f2\tFN\t2\n", asm_out_file);
13866 fputs ("__f3\tFN\t3\n", asm_out_file);
13867 fputs ("__f4\tFN\t4\n", asm_out_file);
13868 fputs ("__f5\tFN\t5\n", asm_out_file);
13869 fputs ("__f6\tFN\t6\n", asm_out_file);
13870 fputs ("__f7\tFN\t7\n", asm_out_file);
13871 text_section ();
13874 static void
13875 aof_file_end (void)
13877 if (flag_pic)
13878 aof_dump_pic_table (asm_out_file);
13879 aof_dump_imports (asm_out_file);
13880 fputs ("\tEND\n", asm_out_file);
13882 #endif /* AOF_ASSEMBLER */
13884 #ifdef OBJECT_FORMAT_ELF
13885 /* Switch to an arbitrary section NAME with attributes as specified
13886 by FLAGS. ALIGN specifies any known alignment requirements for
13887 the section; 0 if the default should be used.
13889 Differs from the default elf version only in the prefix character
13890 used before the section type. */
13892 static void
13893 arm_elf_asm_named_section (const char *name, unsigned int flags)
13895 char flagchars[10], *f = flagchars;
13897 if (! named_section_first_declaration (name))
13899 fprintf (asm_out_file, "\t.section\t%s\n", name);
13900 return;
13903 if (!(flags & SECTION_DEBUG))
13904 *f++ = 'a';
13905 if (flags & SECTION_WRITE)
13906 *f++ = 'w';
13907 if (flags & SECTION_CODE)
13908 *f++ = 'x';
13909 if (flags & SECTION_SMALL)
13910 *f++ = 's';
13911 if (flags & SECTION_MERGE)
13912 *f++ = 'M';
13913 if (flags & SECTION_STRINGS)
13914 *f++ = 'S';
13915 if (flags & SECTION_TLS)
13916 *f++ = 'T';
13917 *f = '\0';
13919 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
13921 if (!(flags & SECTION_NOTYPE))
13923 const char *type;
13925 if (flags & SECTION_BSS)
13926 type = "nobits";
13927 else
13928 type = "progbits";
13930 fprintf (asm_out_file, ",%%%s", type);
13932 if (flags & SECTION_ENTSIZE)
13933 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
13936 putc ('\n', asm_out_file);
13938 #endif
13940 #ifndef ARM_PE
13941 /* Symbols in the text segment can be accessed without indirecting via the
13942 constant pool; it may take an extra binary operation, but this is still
13943 faster than indirecting via memory. Don't do this when not optimizing,
13944 since we won't be calculating al of the offsets necessary to do this
13945 simplification. */
13947 static void
13948 arm_encode_section_info (tree decl, rtx rtl, int first)
13950 /* This doesn't work with AOF syntax, since the string table may be in
13951 a different AREA. */
13952 #ifndef AOF_ASSEMBLER
13953 if (optimize > 0 && TREE_CONSTANT (decl))
13954 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13955 #endif
13957 /* If we are referencing a function that is weak then encode a long call
13958 flag in the function name, otherwise if the function is static or
13959 or known to be defined in this file then encode a short call flag. */
13960 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
13962 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13963 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13964 else if (! TREE_PUBLIC (decl))
13965 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13968 #endif /* !ARM_PE */
13970 static void
13971 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13973 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13974 && !strcmp (prefix, "L"))
13976 arm_ccfsm_state = 0;
13977 arm_target_insn = NULL;
13979 default_internal_label (stream, prefix, labelno);
13982 /* Output code to add DELTA to the first argument, and then jump
13983 to FUNCTION. Used for C++ multiple inheritance. */
13984 static void
13985 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13986 HOST_WIDE_INT delta,
13987 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13988 tree function)
13990 static int thunk_label = 0;
13991 char label[256];
13992 int mi_delta = delta;
13993 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13994 int shift = 0;
13995 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13996 ? 1 : 0);
13997 if (mi_delta < 0)
13998 mi_delta = - mi_delta;
13999 if (TARGET_THUMB)
14001 int labelno = thunk_label++;
14002 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14003 fputs ("\tldr\tr12, ", file);
14004 assemble_name (file, label);
14005 fputc ('\n', file);
14007 while (mi_delta != 0)
14009 if ((mi_delta & (3 << shift)) == 0)
14010 shift += 2;
14011 else
14013 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14014 mi_op, this_regno, this_regno,
14015 mi_delta & (0xff << shift));
14016 mi_delta &= ~(0xff << shift);
14017 shift += 8;
14020 if (TARGET_THUMB)
14022 fprintf (file, "\tbx\tr12\n");
14023 ASM_OUTPUT_ALIGN (file, 2);
14024 assemble_name (file, label);
14025 fputs (":\n", file);
14026 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14028 else
14030 fputs ("\tb\t", file);
14031 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14032 if (NEED_PLT_RELOC)
14033 fputs ("(PLT)", file);
14034 fputc ('\n', file);
14039 arm_emit_vector_const (FILE *file, rtx x)
14041 int i;
14042 const char * pattern;
14044 if (GET_CODE (x) != CONST_VECTOR)
14045 abort ();
14047 switch (GET_MODE (x))
14049 case V2SImode: pattern = "%08x"; break;
14050 case V4HImode: pattern = "%04x"; break;
14051 case V8QImode: pattern = "%02x"; break;
14052 default: abort ();
14055 fprintf (file, "0x");
14056 for (i = CONST_VECTOR_NUNITS (x); i--;)
14058 rtx element;
14060 element = CONST_VECTOR_ELT (x, i);
14061 fprintf (file, pattern, INTVAL (element));
14064 return 1;
14067 const char *
14068 arm_output_load_gr (rtx *operands)
14070 rtx reg;
14071 rtx offset;
14072 rtx wcgr;
14073 rtx sum;
14075 if (GET_CODE (operands [1]) != MEM
14076 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14077 || GET_CODE (reg = XEXP (sum, 0)) != REG
14078 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14079 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14080 return "wldrw%?\t%0, %1";
14082 /* Fix up an out-of-range load of a GR register. */
14083 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14084 wcgr = operands[0];
14085 operands[0] = reg;
14086 output_asm_insn ("ldr%?\t%0, %1", operands);
14088 operands[0] = wcgr;
14089 operands[1] = reg;
14090 output_asm_insn ("tmcr%?\t%0, %1", operands);
14091 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14093 return "";
14096 static rtx
14097 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14098 int incoming ATTRIBUTE_UNUSED)
14100 #if 0
14101 /* FIXME: The ARM backend has special code to handle structure
14102 returns, and will reserve its own hidden first argument. So
14103 if this macro is enabled a *second* hidden argument will be
14104 reserved, which will break binary compatibility with old
14105 toolchains and also thunk handling. One day this should be
14106 fixed. */
14107 return 0;
14108 #else
14109 /* Register in which address to store a structure value
14110 is passed to a function. */
14111 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14112 #endif
14115 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14117 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14118 named arg and all anonymous args onto the stack.
14119 XXX I know the prologue shouldn't be pushing registers, but it is faster
14120 that way. */
14122 static void
14123 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14124 enum machine_mode mode ATTRIBUTE_UNUSED,
14125 tree type ATTRIBUTE_UNUSED,
14126 int *pretend_size,
14127 int second_time ATTRIBUTE_UNUSED)
14129 cfun->machine->uses_anonymous_args = 1;
14130 if (cum->nregs < NUM_ARG_REGS)
14131 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14134 /* Return nonzero if the CONSUMER instruction (a store) does not need
14135 PRODUCER's value to calculate the address. */
14138 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14140 rtx value = PATTERN (producer);
14141 rtx addr = PATTERN (consumer);
14143 if (GET_CODE (value) == COND_EXEC)
14144 value = COND_EXEC_CODE (value);
14145 if (GET_CODE (value) == PARALLEL)
14146 value = XVECEXP (value, 0, 0);
14147 value = XEXP (value, 0);
14148 if (GET_CODE (addr) == COND_EXEC)
14149 addr = COND_EXEC_CODE (addr);
14150 if (GET_CODE (addr) == PARALLEL)
14151 addr = XVECEXP (addr, 0, 0);
14152 addr = XEXP (addr, 0);
14154 return !reg_overlap_mentioned_p (value, addr);
14157 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14158 have an early register shift value or amount dependency on the
14159 result of PRODUCER. */
14162 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14164 rtx value = PATTERN (producer);
14165 rtx op = PATTERN (consumer);
14166 rtx early_op;
14168 if (GET_CODE (value) == COND_EXEC)
14169 value = COND_EXEC_CODE (value);
14170 if (GET_CODE (value) == PARALLEL)
14171 value = XVECEXP (value, 0, 0);
14172 value = XEXP (value, 0);
14173 if (GET_CODE (op) == COND_EXEC)
14174 op = COND_EXEC_CODE (op);
14175 if (GET_CODE (op) == PARALLEL)
14176 op = XVECEXP (op, 0, 0);
14177 op = XEXP (op, 1);
14179 early_op = XEXP (op, 0);
14180 /* This is either an actual independent shift, or a shift applied to
14181 the first operand of another operation. We want the whole shift
14182 operation. */
14183 if (GET_CODE (early_op) == REG)
14184 early_op = op;
14186 return !reg_overlap_mentioned_p (value, early_op);
14189 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14190 have an early register shift value dependency on the result of
14191 PRODUCER. */
14194 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14196 rtx value = PATTERN (producer);
14197 rtx op = PATTERN (consumer);
14198 rtx early_op;
14200 if (GET_CODE (value) == COND_EXEC)
14201 value = COND_EXEC_CODE (value);
14202 if (GET_CODE (value) == PARALLEL)
14203 value = XVECEXP (value, 0, 0);
14204 value = XEXP (value, 0);
14205 if (GET_CODE (op) == COND_EXEC)
14206 op = COND_EXEC_CODE (op);
14207 if (GET_CODE (op) == PARALLEL)
14208 op = XVECEXP (op, 0, 0);
14209 op = XEXP (op, 1);
14211 early_op = XEXP (op, 0);
14213 /* This is either an actual independent shift, or a shift applied to
14214 the first operand of another operation. We want the value being
14215 shifted, in either case. */
14216 if (GET_CODE (early_op) != REG)
14217 early_op = XEXP (early_op, 0);
14219 return !reg_overlap_mentioned_p (value, early_op);
14222 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14223 have an early register mult dependency on the result of
14224 PRODUCER. */
14227 arm_no_early_mul_dep (rtx producer, rtx consumer)
14229 rtx value = PATTERN (producer);
14230 rtx op = PATTERN (consumer);
14232 if (GET_CODE (value) == COND_EXEC)
14233 value = COND_EXEC_CODE (value);
14234 if (GET_CODE (value) == PARALLEL)
14235 value = XVECEXP (value, 0, 0);
14236 value = XEXP (value, 0);
14237 if (GET_CODE (op) == COND_EXEC)
14238 op = COND_EXEC_CODE (op);
14239 if (GET_CODE (op) == PARALLEL)
14240 op = XVECEXP (op, 0, 0);
14241 op = XEXP (op, 1);
14243 return (GET_CODE (op) == PLUS
14244 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));