1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
149 ;; Instruction operand type as used in the Principles of Operation.
150 ;; Used to determine defaults for length and other attribute values.
152 (define_attr "op_type"
153 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
156 ;; Instruction type attribute used for scheduling.
158 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
160 imulhi,imulsi,imuldi,
161 branch,jsr,fsimpdf,fsimpsf,
162 floaddf,floadsf,fstoredf,fstoresf,
163 fmuldf,fmulsf,fdivdf,fdivsf,
164 ftoi,itof,fsqrtdf,fsqrtsf,
166 (cond [(eq_attr "op_type" "NN") (const_string "other")
167 (eq_attr "op_type" "SS") (const_string "cs")]
168 (const_string "integer")))
170 ;; Another attribute used for scheduling purposes:
171 ;; agen: Instruction uses the address generation unit
172 ;; reg: Instruction does not use the agen unit
174 (define_attr "atype" "agen,reg"
175 (cond [(eq_attr "op_type" "E") (const_string "reg")
176 (eq_attr "op_type" "RR") (const_string "reg")
177 (eq_attr "op_type" "RX") (const_string "agen")
178 (eq_attr "op_type" "RI") (const_string "reg")
179 (eq_attr "op_type" "RRE") (const_string "reg")
180 (eq_attr "op_type" "RS") (const_string "agen")
181 (eq_attr "op_type" "RSI") (const_string "agen")
182 (eq_attr "op_type" "S") (const_string "agen")
183 (eq_attr "op_type" "SI") (const_string "agen")
184 (eq_attr "op_type" "SS") (const_string "agen")
185 (eq_attr "op_type" "SSE") (const_string "agen")
186 (eq_attr "op_type" "RXE") (const_string "agen")
187 (eq_attr "op_type" "RSE") (const_string "agen")
188 (eq_attr "op_type" "RIL") (const_string "agen")
189 (eq_attr "op_type" "RXY") (const_string "agen")
190 (eq_attr "op_type" "RSY") (const_string "agen")
191 (eq_attr "op_type" "SIY") (const_string "agen")]
192 (const_string "agen")))
196 (define_attr "length" ""
197 (cond [(eq_attr "op_type" "E") (const_int 2)
198 (eq_attr "op_type" "RR") (const_int 2)
199 (eq_attr "op_type" "RX") (const_int 4)
200 (eq_attr "op_type" "RI") (const_int 4)
201 (eq_attr "op_type" "RRE") (const_int 4)
202 (eq_attr "op_type" "RS") (const_int 4)
203 (eq_attr "op_type" "RSI") (const_int 4)
204 (eq_attr "op_type" "S") (const_int 4)
205 (eq_attr "op_type" "SI") (const_int 4)
206 (eq_attr "op_type" "SS") (const_int 6)
207 (eq_attr "op_type" "SSE") (const_int 6)
208 (eq_attr "op_type" "RXE") (const_int 6)
209 (eq_attr "op_type" "RSE") (const_int 6)
210 (eq_attr "op_type" "RIL") (const_int 6)
211 (eq_attr "op_type" "RXY") (const_int 6)
212 (eq_attr "op_type" "RSY") (const_int 6)
213 (eq_attr "op_type" "SIY") (const_int 6)]
217 ;; Processor type. This attribute must exactly match the processor_type
218 ;; enumeration in s390.h. The current machine description does not
219 ;; distinguish between g5 and g6, but there are differences between the two
220 ;; CPUs could in theory be modeled.
222 (define_attr "cpu" "g5,g6,z900,z990"
223 (const (symbol_ref "s390_tune")))
225 ;; Pipeline description for z900. For lack of anything better,
226 ;; this description is also used for the g5 and g6.
229 ;; Pipeline description for z990.
233 (include "predicates.md")
238 ;; This mode macro allows DF and SF patterns to be generated from the
240 (define_mode_macro FPR [DF SF])
242 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
243 ;; from the same template.
244 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
245 (define_mode_macro DSI [DI SI])
247 ;; This mode macro allows :P to be used for patterns that operate on
248 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
249 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
251 ;; This mode macro allows the QI and HI patterns to be defined from
252 ;; the same template.
253 (define_mode_macro HQI [HI QI])
255 ;; This mode macro allows the integer patterns to be defined from the
257 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
259 ;; This macro allows to unify all 'bCOND' expander patterns.
260 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
261 ordered uneq unlt ungt unle unge ltgt])
263 ;; This macro allows to unify all 'sCOND' patterns.
264 (define_code_macro SCOND [ltu gtu leu geu])
266 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
267 ;; the same template.
268 (define_code_macro SHIFT [ashift lshiftrt])
271 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
272 ;; and "ltebr" in SFmode.
273 (define_mode_attr de [(DF "d") (SF "e")])
275 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
276 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
277 (define_mode_attr dee [(DF "d") (SF "ee")])
279 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
280 ;; 'ashift' and "srdl" in 'lshiftrt'.
281 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
283 ;; In SHIFT templates, this attribute holds the correct standard name for the
284 ;; pattern itself and the corresponding function calls.
285 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
287 ;; This attribute handles differences in the instruction 'type' and will result
288 ;; in "RRE" for DImode and "RR" for SImode.
289 (define_mode_attr E [(DI "E") (SI "")])
291 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
292 ;; and "lcr" in SImode.
293 (define_mode_attr g [(DI "g") (SI "")])
295 ;; ICM mask required to load MODE value into the highest subreg
296 ;; of a SImode register.
297 (define_mode_attr icm_hi [(HI "12") (QI "8")])
299 ;; ICM mask required to load MODE value into the lowest subreg
300 ;; of a SImode register.
301 (define_mode_attr icm_lo [(HI "3") (QI "1")])
303 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
304 ;; HImode and "llgc" in QImode.
305 (define_mode_attr hc [(HI "h") (QI "c")])
307 ;; Maximum unsigned integer that fits in MODE.
308 (define_mode_attr max_uint [(HI "65535") (QI "255")])
312 ;;- Compare instructions.
315 (define_expand "cmp<mode>"
317 (compare:CC (match_operand:GPR 0 "register_operand" "")
318 (match_operand:GPR 1 "general_operand" "")))]
321 s390_compare_op0 = operands[0];
322 s390_compare_op1 = operands[1];
326 (define_expand "cmp<mode>"
328 (compare:CC (match_operand:FPR 0 "register_operand" "")
329 (match_operand:FPR 1 "general_operand" "")))]
332 s390_compare_op0 = operands[0];
333 s390_compare_op1 = operands[1];
338 ; Test-under-Mask instructions
340 (define_insn "*tmqi_mem"
342 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
343 (match_operand:QI 1 "immediate_operand" "n,n"))
344 (match_operand:QI 2 "immediate_operand" "n,n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
349 [(set_attr "op_type" "SI,SIY")])
351 (define_insn "*tmdi_reg"
353 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
354 (match_operand:DI 1 "immediate_operand"
355 "N0HD0,N1HD0,N2HD0,N3HD0"))
356 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
358 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
359 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
365 [(set_attr "op_type" "RI")])
367 (define_insn "*tmsi_reg"
369 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
370 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
371 (match_operand:SI 2 "immediate_operand" "n,n")))]
372 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
373 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
377 [(set_attr "op_type" "RI")])
379 (define_insn "*tm<mode>_full"
381 (compare (match_operand:HQI 0 "register_operand" "d")
382 (match_operand:HQI 1 "immediate_operand" "n")))]
383 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
385 [(set_attr "op_type" "RI")])
388 ; Load-and-Test instructions
390 (define_insn "*tstdi_sign"
392 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
393 (const_int 32)) (const_int 32))
394 (match_operand:DI 1 "const0_operand" "")))
395 (set (match_operand:DI 2 "register_operand" "=d")
396 (sign_extend:DI (match_dup 0)))]
397 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
399 [(set_attr "op_type" "RRE")])
401 (define_insn "*tstdi"
403 (compare (match_operand:DI 0 "register_operand" "d")
404 (match_operand:DI 1 "const0_operand" "")))
405 (set (match_operand:DI 2 "register_operand" "=d")
407 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
409 [(set_attr "op_type" "RRE")])
411 (define_insn "*tstdi_cconly"
413 (compare (match_operand:DI 0 "register_operand" "d")
414 (match_operand:DI 1 "const0_operand" "")))]
415 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
417 [(set_attr "op_type" "RRE")])
419 (define_insn "*tstdi_cconly_31"
421 (compare (match_operand:DI 0 "register_operand" "d")
422 (match_operand:DI 1 "const0_operand" "")))]
423 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
425 [(set_attr "op_type" "RS")
426 (set_attr "atype" "reg")])
429 (define_insn "*tstsi"
431 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
432 (match_operand:SI 1 "const0_operand" "")))
433 (set (match_operand:SI 2 "register_operand" "=d,d,d")
435 "s390_match_ccmode(insn, CCSmode)"
440 [(set_attr "op_type" "RR,RS,RSY")])
442 (define_insn "*tstsi_cconly"
444 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
445 (match_operand:SI 1 "const0_operand" "")))
446 (clobber (match_scratch:SI 2 "=X,d,d"))]
447 "s390_match_ccmode(insn, CCSmode)"
452 [(set_attr "op_type" "RR,RS,RSY")])
454 (define_insn "*tstsi_cconly2"
456 (compare (match_operand:SI 0 "register_operand" "d")
457 (match_operand:SI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode)"
460 [(set_attr "op_type" "RR")])
462 (define_insn "*tst<mode>CCT"
464 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
465 (match_operand:HQI 1 "const0_operand" "")))
466 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
468 "s390_match_ccmode(insn, CCTmode)"
471 icmy\t%2,<icm_lo>,%S0
473 [(set_attr "op_type" "RS,RSY,RI")])
475 (define_insn "*tsthiCCT_cconly"
477 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
478 (match_operand:HI 1 "const0_operand" "")))
479 (clobber (match_scratch:HI 2 "=d,d,X"))]
480 "s390_match_ccmode(insn, CCTmode)"
485 [(set_attr "op_type" "RS,RSY,RI")])
487 (define_insn "*tstqiCCT_cconly"
489 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
490 (match_operand:QI 1 "const0_operand" "")))]
491 "s390_match_ccmode(insn, CCTmode)"
496 [(set_attr "op_type" "SI,SIY,RI")])
498 (define_insn "*tst<mode>"
500 (compare (match_operand:HQI 0 "s_operand" "Q,S")
501 (match_operand:HQI 1 "const0_operand" "")))
502 (set (match_operand:HQI 2 "register_operand" "=d,d")
504 "s390_match_ccmode(insn, CCSmode)"
507 icmy\t%2,<icm_lo>,%S0"
508 [(set_attr "op_type" "RS,RSY")])
510 (define_insn "*tst<mode>_cconly"
512 (compare (match_operand:HQI 0 "s_operand" "Q,S")
513 (match_operand:HQI 1 "const0_operand" "")))
514 (clobber (match_scratch:HQI 2 "=d,d"))]
515 "s390_match_ccmode(insn, CCSmode)"
518 icmy\t%2,<icm_lo>,%S0"
519 [(set_attr "op_type" "RS,RSY")])
522 ; Compare (equality) instructions
524 (define_insn "*cmpdi_cct"
526 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
527 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
528 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
534 [(set_attr "op_type" "RRE,RI,RXY,SS")])
536 (define_insn "*cmpsi_cct"
538 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
539 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
540 "s390_match_ccmode (insn, CCTmode)"
547 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
550 ; Compare (signed) instructions
552 (define_insn "*cmpdi_ccs_sign"
554 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
555 (match_operand:DI 0 "register_operand" "d,d")))]
556 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
560 [(set_attr "op_type" "RRE,RXY")])
562 (define_insn "*cmpdi_ccs"
564 (compare (match_operand:DI 0 "register_operand" "d,d,d")
565 (match_operand:DI 1 "general_operand" "d,K,m")))]
566 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
571 [(set_attr "op_type" "RRE,RI,RXY")])
573 (define_insn "*cmpsi_ccs_sign"
575 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
576 (match_operand:SI 0 "register_operand" "d,d")))]
577 "s390_match_ccmode(insn, CCSRmode)"
581 [(set_attr "op_type" "RX,RXY")])
583 (define_insn "*cmpsi_ccs"
585 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
586 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
587 "s390_match_ccmode(insn, CCSmode)"
593 [(set_attr "op_type" "RR,RI,RX,RXY")])
596 ; Compare (unsigned) instructions
598 (define_insn "*cmpdi_ccu_zero"
600 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
601 (match_operand:DI 0 "register_operand" "d,d")))]
602 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
606 [(set_attr "op_type" "RRE,RXY")])
608 (define_insn "*cmpdi_ccu"
610 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
611 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
612 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
618 [(set_attr "op_type" "RRE,RXY,SS,SS")])
620 (define_insn "*cmpsi_ccu"
622 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
623 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
624 "s390_match_ccmode (insn, CCUmode)"
631 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
633 (define_insn "*cmphi_ccu"
635 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
636 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
637 "s390_match_ccmode (insn, CCUmode)
638 && !register_operand (operands[1], HImode)"
644 [(set_attr "op_type" "RS,RSY,SS,SS")])
646 (define_insn "*cmpqi_ccu"
648 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
649 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
650 "s390_match_ccmode (insn, CCUmode)
651 && !register_operand (operands[1], QImode)"
659 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
662 ; Block compare (CLC) instruction patterns.
666 (compare (match_operand:BLK 0 "memory_operand" "Q")
667 (match_operand:BLK 1 "memory_operand" "Q")))
668 (use (match_operand 2 "const_int_operand" "n"))]
669 "s390_match_ccmode (insn, CCUmode)
670 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
671 "clc\t%O0(%2,%R0),%S1"
672 [(set_attr "op_type" "SS")])
676 (compare (match_operand 0 "memory_operand" "")
677 (match_operand 1 "memory_operand" "")))]
679 && s390_match_ccmode (insn, CCUmode)
680 && GET_MODE (operands[0]) == GET_MODE (operands[1])
681 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
683 [(set (match_dup 0) (match_dup 1))
684 (use (match_dup 2))])]
686 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
687 operands[0] = adjust_address (operands[0], BLKmode, 0);
688 operands[1] = adjust_address (operands[1], BLKmode, 0);
690 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
691 operands[0], operands[1]);
692 operands[0] = SET_DEST (PATTERN (curr_insn));
696 ; (DF|SF) instructions
698 (define_insn "*cmp<mode>_ccs_0"
700 (compare (match_operand:FPR 0 "register_operand" "f")
701 (match_operand:FPR 1 "const0_operand" "")))]
702 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
704 [(set_attr "op_type" "RRE")
705 (set_attr "type" "fsimp<mode>")])
707 (define_insn "*cmp<mode>_ccs_0_ibm"
709 (compare (match_operand:FPR 0 "register_operand" "f")
710 (match_operand:FPR 1 "const0_operand" "")))]
711 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
713 [(set_attr "op_type" "RR")
714 (set_attr "type" "fsimp<mode>")])
716 (define_insn "*cmp<mode>_ccs"
718 (compare (match_operand:FPR 0 "register_operand" "f,f")
719 (match_operand:FPR 1 "general_operand" "f,R")))]
720 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
724 [(set_attr "op_type" "RRE,RXE")
725 (set_attr "type" "fsimp<mode>")])
727 (define_insn "*cmp<mode>_ccs_ibm"
729 (compare (match_operand:FPR 0 "register_operand" "f,f")
730 (match_operand:FPR 1 "general_operand" "f,R")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
735 [(set_attr "op_type" "RR,RX")
736 (set_attr "type" "fsimp<mode>")])
740 ;;- Move instructions.
744 ; movti instruction pattern(s).
748 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
749 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
757 [(set_attr "op_type" "RSY,RSY,*,*,SS")
758 (set_attr "type" "lm,stm,*,*,*")])
761 [(set (match_operand:TI 0 "nonimmediate_operand" "")
762 (match_operand:TI 1 "general_operand" ""))]
763 "TARGET_64BIT && reload_completed
764 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
765 [(set (match_dup 2) (match_dup 4))
766 (set (match_dup 3) (match_dup 5))]
768 operands[2] = operand_subword (operands[0], 0, 0, TImode);
769 operands[3] = operand_subword (operands[0], 1, 0, TImode);
770 operands[4] = operand_subword (operands[1], 0, 0, TImode);
771 operands[5] = operand_subword (operands[1], 1, 0, TImode);
775 [(set (match_operand:TI 0 "nonimmediate_operand" "")
776 (match_operand:TI 1 "general_operand" ""))]
777 "TARGET_64BIT && reload_completed
778 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
779 [(set (match_dup 2) (match_dup 4))
780 (set (match_dup 3) (match_dup 5))]
782 operands[2] = operand_subword (operands[0], 1, 0, TImode);
783 operands[3] = operand_subword (operands[0], 0, 0, TImode);
784 operands[4] = operand_subword (operands[1], 1, 0, TImode);
785 operands[5] = operand_subword (operands[1], 0, 0, TImode);
789 [(set (match_operand:TI 0 "register_operand" "")
790 (match_operand:TI 1 "memory_operand" ""))]
791 "TARGET_64BIT && reload_completed
792 && !s_operand (operands[1], VOIDmode)"
793 [(set (match_dup 0) (match_dup 1))]
795 rtx addr = operand_subword (operands[0], 1, 0, TImode);
796 s390_load_address (addr, XEXP (operands[1], 0));
797 operands[1] = replace_equiv_address (operands[1], addr);
800 (define_expand "reload_outti"
801 [(parallel [(match_operand:TI 0 "" "")
802 (match_operand:TI 1 "register_operand" "d")
803 (match_operand:DI 2 "register_operand" "=&a")])]
806 gcc_assert (MEM_P (operands[0]));
807 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
808 operands[0] = replace_equiv_address (operands[0], operands[2]);
809 emit_move_insn (operands[0], operands[1]);
814 ; movdi instruction pattern(s).
817 (define_expand "movdi"
818 [(set (match_operand:DI 0 "general_operand" "")
819 (match_operand:DI 1 "general_operand" ""))]
822 /* Handle symbolic constants. */
823 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
824 emit_symbolic_move (operands);
827 (define_insn "*movdi_larl"
828 [(set (match_operand:DI 0 "register_operand" "=d")
829 (match_operand:DI 1 "larl_operand" "X"))]
831 && !FP_REG_P (operands[0])"
833 [(set_attr "op_type" "RIL")
834 (set_attr "type" "larl")])
836 (define_insn "*movdi_64"
837 [(set (match_operand:DI 0 "nonimmediate_operand"
838 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
839 (match_operand:DI 1 "general_operand"
840 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
862 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
863 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
864 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
865 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
868 [(set (match_operand:DI 0 "register_operand" "")
869 (match_operand:DI 1 "register_operand" ""))]
870 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
871 [(set (match_dup 2) (match_dup 3))
872 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
873 (set (strict_low_part (match_dup 2)) (match_dup 4))]
874 "operands[2] = gen_lowpart (SImode, operands[0]);
875 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
878 [(set (match_operand:DI 0 "register_operand" "")
879 (match_operand:DI 1 "register_operand" ""))]
880 "TARGET_64BIT && ACCESS_REG_P (operands[0])
881 && dead_or_set_p (insn, operands[1])"
882 [(set (match_dup 3) (match_dup 2))
883 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
884 (set (match_dup 4) (match_dup 2))]
885 "operands[2] = gen_lowpart (SImode, operands[1]);
886 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
889 [(set (match_operand:DI 0 "register_operand" "")
890 (match_operand:DI 1 "register_operand" ""))]
891 "TARGET_64BIT && ACCESS_REG_P (operands[0])
892 && !dead_or_set_p (insn, operands[1])"
893 [(set (match_dup 3) (match_dup 2))
894 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
895 (set (match_dup 4) (match_dup 2))
896 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
897 "operands[2] = gen_lowpart (SImode, operands[1]);
898 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
900 (define_insn "*movdi_31"
901 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
902 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
915 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
916 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
919 [(set (match_operand:DI 0 "nonimmediate_operand" "")
920 (match_operand:DI 1 "general_operand" ""))]
921 "!TARGET_64BIT && reload_completed
922 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
923 [(set (match_dup 2) (match_dup 4))
924 (set (match_dup 3) (match_dup 5))]
926 operands[2] = operand_subword (operands[0], 0, 0, DImode);
927 operands[3] = operand_subword (operands[0], 1, 0, DImode);
928 operands[4] = operand_subword (operands[1], 0, 0, DImode);
929 operands[5] = operand_subword (operands[1], 1, 0, DImode);
933 [(set (match_operand:DI 0 "nonimmediate_operand" "")
934 (match_operand:DI 1 "general_operand" ""))]
935 "!TARGET_64BIT && reload_completed
936 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
937 [(set (match_dup 2) (match_dup 4))
938 (set (match_dup 3) (match_dup 5))]
940 operands[2] = operand_subword (operands[0], 1, 0, DImode);
941 operands[3] = operand_subword (operands[0], 0, 0, DImode);
942 operands[4] = operand_subword (operands[1], 1, 0, DImode);
943 operands[5] = operand_subword (operands[1], 0, 0, DImode);
947 [(set (match_operand:DI 0 "register_operand" "")
948 (match_operand:DI 1 "memory_operand" ""))]
949 "!TARGET_64BIT && reload_completed
950 && !FP_REG_P (operands[0])
951 && !s_operand (operands[1], VOIDmode)"
952 [(set (match_dup 0) (match_dup 1))]
954 rtx addr = operand_subword (operands[0], 1, 0, DImode);
955 s390_load_address (addr, XEXP (operands[1], 0));
956 operands[1] = replace_equiv_address (operands[1], addr);
959 (define_expand "reload_outdi"
960 [(parallel [(match_operand:DI 0 "" "")
961 (match_operand:DI 1 "register_operand" "d")
962 (match_operand:SI 2 "register_operand" "=&a")])]
965 gcc_assert (MEM_P (operands[0]));
966 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
967 operands[0] = replace_equiv_address (operands[0], operands[2]);
968 emit_move_insn (operands[0], operands[1]);
973 [(set (match_operand:DI 0 "register_operand" "")
974 (mem:DI (match_operand 1 "address_operand" "")))]
976 && !FP_REG_P (operands[0])
977 && GET_CODE (operands[1]) == SYMBOL_REF
978 && CONSTANT_POOL_ADDRESS_P (operands[1])
979 && get_pool_mode (operands[1]) == DImode
980 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
981 [(set (match_dup 0) (match_dup 2))]
982 "operands[2] = get_pool_constant (operands[1]);")
984 (define_insn "*la_64"
985 [(set (match_operand:DI 0 "register_operand" "=d,d")
986 (match_operand:QI 1 "address_operand" "U,W"))]
991 [(set_attr "op_type" "RX,RXY")
992 (set_attr "type" "la")])
996 [(set (match_operand:DI 0 "register_operand" "")
997 (match_operand:QI 1 "address_operand" ""))
998 (clobber (reg:CC 33))])]
1000 && preferred_la_operand_p (operands[1], const0_rtx)"
1001 [(set (match_dup 0) (match_dup 1))]
1005 [(set (match_operand:DI 0 "register_operand" "")
1006 (match_operand:DI 1 "register_operand" ""))
1009 (plus:DI (match_dup 0)
1010 (match_operand:DI 2 "nonmemory_operand" "")))
1011 (clobber (reg:CC 33))])]
1013 && !reg_overlap_mentioned_p (operands[0], operands[2])
1014 && preferred_la_operand_p (operands[1], operands[2])"
1015 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1018 (define_expand "reload_indi"
1019 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1020 (match_operand:DI 1 "s390_plus_operand" "")
1021 (match_operand:DI 2 "register_operand" "=&a")])]
1024 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1029 ; movsi instruction pattern(s).
1032 (define_expand "movsi"
1033 [(set (match_operand:SI 0 "general_operand" "")
1034 (match_operand:SI 1 "general_operand" ""))]
1037 /* Handle symbolic constants. */
1038 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1039 emit_symbolic_move (operands);
1042 (define_insn "*movsi_larl"
1043 [(set (match_operand:SI 0 "register_operand" "=d")
1044 (match_operand:SI 1 "larl_operand" "X"))]
1045 "!TARGET_64BIT && TARGET_CPU_ZARCH
1046 && !FP_REG_P (operands[0])"
1048 [(set_attr "op_type" "RIL")
1049 (set_attr "type" "larl")])
1051 (define_insn "*movsi_zarch"
1052 [(set (match_operand:SI 0 "nonimmediate_operand"
1053 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1054 (match_operand:SI 1 "general_operand"
1055 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1077 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1078 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1079 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1080 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1082 (define_insn "*movsi_esa"
1083 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1084 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1099 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1100 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1103 [(set (match_operand:SI 0 "register_operand" "")
1104 (mem:SI (match_operand 1 "address_operand" "")))]
1105 "!FP_REG_P (operands[0])
1106 && GET_CODE (operands[1]) == SYMBOL_REF
1107 && CONSTANT_POOL_ADDRESS_P (operands[1])
1108 && get_pool_mode (operands[1]) == SImode
1109 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1110 [(set (match_dup 0) (match_dup 2))]
1111 "operands[2] = get_pool_constant (operands[1]);")
1113 (define_insn "*la_31"
1114 [(set (match_operand:SI 0 "register_operand" "=d,d")
1115 (match_operand:QI 1 "address_operand" "U,W"))]
1116 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1120 [(set_attr "op_type" "RX,RXY")
1121 (set_attr "type" "la")])
1125 [(set (match_operand:SI 0 "register_operand" "")
1126 (match_operand:QI 1 "address_operand" ""))
1127 (clobber (reg:CC 33))])]
1129 && preferred_la_operand_p (operands[1], const0_rtx)"
1130 [(set (match_dup 0) (match_dup 1))]
1134 [(set (match_operand:SI 0 "register_operand" "")
1135 (match_operand:SI 1 "register_operand" ""))
1138 (plus:SI (match_dup 0)
1139 (match_operand:SI 2 "nonmemory_operand" "")))
1140 (clobber (reg:CC 33))])]
1142 && !reg_overlap_mentioned_p (operands[0], operands[2])
1143 && preferred_la_operand_p (operands[1], operands[2])"
1144 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1147 (define_insn "*la_31_and"
1148 [(set (match_operand:SI 0 "register_operand" "=d,d")
1149 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1150 (const_int 2147483647)))]
1155 [(set_attr "op_type" "RX,RXY")
1156 (set_attr "type" "la")])
1158 (define_insn_and_split "*la_31_and_cc"
1159 [(set (match_operand:SI 0 "register_operand" "=d")
1160 (and:SI (match_operand:QI 1 "address_operand" "p")
1161 (const_int 2147483647)))
1162 (clobber (reg:CC 33))]
1165 "&& reload_completed"
1167 (and:SI (match_dup 1) (const_int 2147483647)))]
1169 [(set_attr "op_type" "RX")
1170 (set_attr "type" "la")])
1172 (define_insn "force_la_31"
1173 [(set (match_operand:SI 0 "register_operand" "=d,d")
1174 (match_operand:QI 1 "address_operand" "U,W"))
1175 (use (const_int 0))]
1180 [(set_attr "op_type" "RX")
1181 (set_attr "type" "la")])
1183 (define_expand "reload_insi"
1184 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1185 (match_operand:SI 1 "s390_plus_operand" "")
1186 (match_operand:SI 2 "register_operand" "=&a")])]
1189 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1194 ; movhi instruction pattern(s).
1197 (define_expand "movhi"
1198 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1199 (match_operand:HI 1 "general_operand" ""))]
1202 /* Make it explicit that loading a register from memory
1203 always sign-extends (at least) to SImode. */
1204 if (optimize && !no_new_pseudos
1205 && register_operand (operands[0], VOIDmode)
1206 && GET_CODE (operands[1]) == MEM)
1208 rtx tmp = gen_reg_rtx (SImode);
1209 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1210 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1211 operands[1] = gen_lowpart (HImode, tmp);
1215 (define_insn "*movhi"
1216 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1217 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1227 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1228 (set_attr "type" "lr,*,*,*,store,store,*")])
1231 [(set (match_operand:HI 0 "register_operand" "")
1232 (mem:HI (match_operand 1 "address_operand" "")))]
1233 "GET_CODE (operands[1]) == SYMBOL_REF
1234 && CONSTANT_POOL_ADDRESS_P (operands[1])
1235 && get_pool_mode (operands[1]) == HImode
1236 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1237 [(set (match_dup 0) (match_dup 2))]
1238 "operands[2] = get_pool_constant (operands[1]);")
1241 ; movqi instruction pattern(s).
1244 (define_expand "movqi"
1245 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1246 (match_operand:QI 1 "general_operand" ""))]
1249 /* On z/Architecture, zero-extending from memory to register
1250 is just as fast as a QImode load. */
1251 if (TARGET_ZARCH && optimize && !no_new_pseudos
1252 && register_operand (operands[0], VOIDmode)
1253 && GET_CODE (operands[1]) == MEM)
1255 rtx tmp = gen_reg_rtx (word_mode);
1256 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1257 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1258 operands[1] = gen_lowpart (QImode, tmp);
1262 (define_insn "*movqi"
1263 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1264 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1276 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1277 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1280 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1281 (mem:QI (match_operand 1 "address_operand" "")))]
1282 "GET_CODE (operands[1]) == SYMBOL_REF
1283 && CONSTANT_POOL_ADDRESS_P (operands[1])
1284 && get_pool_mode (operands[1]) == QImode
1285 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1286 [(set (match_dup 0) (match_dup 2))]
1287 "operands[2] = get_pool_constant (operands[1]);")
1290 ; movstrictqi instruction pattern(s).
1293 (define_insn "*movstrictqi"
1294 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1295 (match_operand:QI 1 "memory_operand" "R,T"))]
1300 [(set_attr "op_type" "RX,RXY")])
1303 ; movstricthi instruction pattern(s).
1306 (define_insn "*movstricthi"
1307 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1308 (match_operand:HI 1 "memory_operand" "Q,S"))
1309 (clobber (reg:CC 33))]
1314 [(set_attr "op_type" "RS,RSY")])
1317 ; movstrictsi instruction pattern(s).
1320 (define_insn "movstrictsi"
1321 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1322 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1329 [(set_attr "op_type" "RR,RX,RXY,RRE")
1330 (set_attr "type" "lr,load,load,*")])
1333 ; movdf instruction pattern(s).
1336 (define_expand "movdf"
1337 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1338 (match_operand:DF 1 "general_operand" ""))]
1342 (define_insn "*movdf_64"
1343 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1344 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1356 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1357 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1359 (define_insn "*movdf_31"
1360 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1361 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1374 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1375 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1378 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1379 (match_operand:DF 1 "general_operand" ""))]
1380 "!TARGET_64BIT && reload_completed
1381 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1382 [(set (match_dup 2) (match_dup 4))
1383 (set (match_dup 3) (match_dup 5))]
1385 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1386 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1387 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1388 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1392 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1393 (match_operand:DF 1 "general_operand" ""))]
1394 "!TARGET_64BIT && reload_completed
1395 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1396 [(set (match_dup 2) (match_dup 4))
1397 (set (match_dup 3) (match_dup 5))]
1399 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1400 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1401 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1402 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1406 [(set (match_operand:DF 0 "register_operand" "")
1407 (match_operand:DF 1 "memory_operand" ""))]
1408 "!TARGET_64BIT && reload_completed
1409 && !FP_REG_P (operands[0])
1410 && !s_operand (operands[1], VOIDmode)"
1411 [(set (match_dup 0) (match_dup 1))]
1413 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1414 s390_load_address (addr, XEXP (operands[1], 0));
1415 operands[1] = replace_equiv_address (operands[1], addr);
1418 (define_expand "reload_outdf"
1419 [(parallel [(match_operand:DF 0 "" "")
1420 (match_operand:DF 1 "register_operand" "d")
1421 (match_operand:SI 2 "register_operand" "=&a")])]
1424 gcc_assert (MEM_P (operands[0]));
1425 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1426 operands[0] = replace_equiv_address (operands[0], operands[2]);
1427 emit_move_insn (operands[0], operands[1]);
1432 ; movsf instruction pattern(s).
1435 (define_insn "movsf"
1436 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1437 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1451 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1452 (set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
1453 lr,load,load,store,store,*")])
1456 ; movcc instruction pattern
1459 (define_insn "movcc"
1460 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1461 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1471 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1472 (set_attr "type" "lr,*,*,store,store,load,load")])
1475 ; Block move (MVC) patterns.
1479 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1480 (match_operand:BLK 1 "memory_operand" "Q"))
1481 (use (match_operand 2 "const_int_operand" "n"))]
1482 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1483 "mvc\t%O0(%2,%R0),%S1"
1484 [(set_attr "op_type" "SS")])
1487 [(set (match_operand 0 "memory_operand" "")
1488 (match_operand 1 "memory_operand" ""))]
1490 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1491 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1493 [(set (match_dup 0) (match_dup 1))
1494 (use (match_dup 2))])]
1496 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1497 operands[0] = adjust_address (operands[0], BLKmode, 0);
1498 operands[1] = adjust_address (operands[1], BLKmode, 0);
1503 [(set (match_operand:BLK 0 "memory_operand" "")
1504 (match_operand:BLK 1 "memory_operand" ""))
1505 (use (match_operand 2 "const_int_operand" ""))])
1507 [(set (match_operand:BLK 3 "memory_operand" "")
1508 (match_operand:BLK 4 "memory_operand" ""))
1509 (use (match_operand 5 "const_int_operand" ""))])]
1510 "s390_offset_p (operands[0], operands[3], operands[2])
1511 && s390_offset_p (operands[1], operands[4], operands[2])
1512 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1514 [(set (match_dup 6) (match_dup 7))
1515 (use (match_dup 8))])]
1516 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1517 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1518 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1522 ; load_multiple pattern(s).
1524 ; ??? Due to reload problems with replacing registers inside match_parallel
1525 ; we currently support load_multiple/store_multiple only after reload.
1528 (define_expand "load_multiple"
1529 [(match_par_dup 3 [(set (match_operand 0 "" "")
1530 (match_operand 1 "" ""))
1531 (use (match_operand 2 "" ""))])]
1534 enum machine_mode mode;
1540 /* Support only loading a constant number of fixed-point registers from
1541 memory and only bother with this if more than two */
1542 if (GET_CODE (operands[2]) != CONST_INT
1543 || INTVAL (operands[2]) < 2
1544 || INTVAL (operands[2]) > 16
1545 || GET_CODE (operands[1]) != MEM
1546 || GET_CODE (operands[0]) != REG
1547 || REGNO (operands[0]) >= 16)
1550 count = INTVAL (operands[2]);
1551 regno = REGNO (operands[0]);
1552 mode = GET_MODE (operands[0]);
1553 if (mode != SImode && mode != word_mode)
1556 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1559 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1561 from = XEXP (operands[1], 0);
1564 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1565 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1566 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1568 from = XEXP (XEXP (operands[1], 0), 0);
1569 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1576 from = force_reg (Pmode, XEXP (operands[1], 0));
1580 for (i = 0; i < count; i++)
1581 XVECEXP (operands[3], 0, i)
1582 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1583 change_address (operands[1], mode,
1584 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1587 (define_insn "*load_multiple_di"
1588 [(match_parallel 0 "load_multiple_operation"
1589 [(set (match_operand:DI 1 "register_operand" "=r")
1590 (match_operand:DI 2 "s_operand" "QS"))])]
1591 "reload_completed && word_mode == DImode"
1593 int words = XVECLEN (operands[0], 0);
1594 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1595 return "lmg\t%1,%0,%S2";
1597 [(set_attr "op_type" "RSY")
1598 (set_attr "type" "lm")])
1600 (define_insn "*load_multiple_si"
1601 [(match_parallel 0 "load_multiple_operation"
1602 [(set (match_operand:SI 1 "register_operand" "=r,r")
1603 (match_operand:SI 2 "s_operand" "Q,S"))])]
1606 int words = XVECLEN (operands[0], 0);
1607 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1608 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1610 [(set_attr "op_type" "RS,RSY")
1611 (set_attr "type" "lm")])
1614 ; store multiple pattern(s).
1617 (define_expand "store_multiple"
1618 [(match_par_dup 3 [(set (match_operand 0 "" "")
1619 (match_operand 1 "" ""))
1620 (use (match_operand 2 "" ""))])]
1623 enum machine_mode mode;
1629 /* Support only storing a constant number of fixed-point registers to
1630 memory and only bother with this if more than two. */
1631 if (GET_CODE (operands[2]) != CONST_INT
1632 || INTVAL (operands[2]) < 2
1633 || INTVAL (operands[2]) > 16
1634 || GET_CODE (operands[0]) != MEM
1635 || GET_CODE (operands[1]) != REG
1636 || REGNO (operands[1]) >= 16)
1639 count = INTVAL (operands[2]);
1640 regno = REGNO (operands[1]);
1641 mode = GET_MODE (operands[1]);
1642 if (mode != SImode && mode != word_mode)
1645 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1649 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1651 to = XEXP (operands[0], 0);
1654 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1655 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1656 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1658 to = XEXP (XEXP (operands[0], 0), 0);
1659 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1666 to = force_reg (Pmode, XEXP (operands[0], 0));
1670 for (i = 0; i < count; i++)
1671 XVECEXP (operands[3], 0, i)
1672 = gen_rtx_SET (VOIDmode,
1673 change_address (operands[0], mode,
1674 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1675 gen_rtx_REG (mode, regno + i));
1678 (define_insn "*store_multiple_di"
1679 [(match_parallel 0 "store_multiple_operation"
1680 [(set (match_operand:DI 1 "s_operand" "=QS")
1681 (match_operand:DI 2 "register_operand" "r"))])]
1682 "reload_completed && word_mode == DImode"
1684 int words = XVECLEN (operands[0], 0);
1685 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1686 return "stmg\t%2,%0,%S1";
1688 [(set_attr "op_type" "RSY")
1689 (set_attr "type" "stm")])
1692 (define_insn "*store_multiple_si"
1693 [(match_parallel 0 "store_multiple_operation"
1694 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1695 (match_operand:SI 2 "register_operand" "r,r"))])]
1698 int words = XVECLEN (operands[0], 0);
1699 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1700 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1702 [(set_attr "op_type" "RS,RSY")
1703 (set_attr "type" "stm")])
1706 ;; String instructions.
1709 (define_insn "*execute"
1710 [(match_parallel 0 ""
1711 [(unspec [(match_operand 1 "register_operand" "a")
1712 (match_operand:BLK 2 "memory_operand" "R")
1713 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1714 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1715 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1717 [(set_attr "op_type" "RX")
1718 (set_attr "type" "cs")])
1722 ; strlenM instruction pattern(s).
1725 (define_expand "strlen<mode>"
1726 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1729 (unspec:P [(const_int 0)
1730 (match_operand:BLK 1 "memory_operand" "")
1732 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1733 (clobber (scratch:P))
1734 (clobber (reg:CC 33))])
1736 [(set (match_operand:P 0 "register_operand" "")
1737 (minus:P (match_dup 4) (match_dup 5)))
1738 (clobber (reg:CC 33))])]
1741 operands[4] = gen_reg_rtx (Pmode);
1742 operands[5] = gen_reg_rtx (Pmode);
1743 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1744 operands[1] = replace_equiv_address (operands[1], operands[5]);
1747 (define_insn "*strlen<mode>"
1748 [(set (match_operand:P 0 "register_operand" "=a")
1749 (unspec:P [(match_operand:P 2 "general_operand" "0")
1750 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1752 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1753 (clobber (match_scratch:P 1 "=a"))
1754 (clobber (reg:CC 33))]
1756 "srst\t%0,%1\;jo\t.-4"
1757 [(set_attr "length" "8")
1758 (set_attr "type" "vs")])
1761 ; movmemM instruction pattern(s).
1764 (define_expand "movmem<mode>"
1765 [(set (match_operand:BLK 0 "memory_operand" "")
1766 (match_operand:BLK 1 "memory_operand" ""))
1767 (use (match_operand:GPR 2 "general_operand" ""))
1768 (match_operand 3 "" "")]
1770 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1772 ; Move a block that is up to 256 bytes in length.
1773 ; The block length is taken as (operands[2] % 256) + 1.
1775 (define_expand "movmem_short"
1777 [(set (match_operand:BLK 0 "memory_operand" "")
1778 (match_operand:BLK 1 "memory_operand" ""))
1779 (use (match_operand 2 "nonmemory_operand" ""))
1780 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1781 (clobber (match_dup 3))])]
1783 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1785 (define_insn "*movmem_short"
1786 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1787 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1788 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1789 (use (match_operand 3 "immediate_operand" "X,R,X"))
1790 (clobber (match_scratch 4 "=X,X,&a"))]
1791 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1792 && GET_MODE (operands[4]) == Pmode"
1794 [(set_attr "type" "cs")])
1797 [(set (match_operand:BLK 0 "memory_operand" "")
1798 (match_operand:BLK 1 "memory_operand" ""))
1799 (use (match_operand 2 "const_int_operand" ""))
1800 (use (match_operand 3 "immediate_operand" ""))
1801 (clobber (scratch))]
1804 [(set (match_dup 0) (match_dup 1))
1805 (use (match_dup 2))])]
1806 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1809 [(set (match_operand:BLK 0 "memory_operand" "")
1810 (match_operand:BLK 1 "memory_operand" ""))
1811 (use (match_operand 2 "register_operand" ""))
1812 (use (match_operand 3 "memory_operand" ""))
1813 (clobber (scratch))]
1816 [(unspec [(match_dup 2) (match_dup 3)
1817 (const_int 0)] UNSPEC_EXECUTE)
1818 (set (match_dup 0) (match_dup 1))
1819 (use (const_int 1))])]
1823 [(set (match_operand:BLK 0 "memory_operand" "")
1824 (match_operand:BLK 1 "memory_operand" ""))
1825 (use (match_operand 2 "register_operand" ""))
1826 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1827 (clobber (match_operand 3 "register_operand" ""))]
1828 "reload_completed && TARGET_CPU_ZARCH"
1829 [(set (match_dup 3) (label_ref (match_dup 4)))
1831 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1832 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1833 (set (match_dup 0) (match_dup 1))
1834 (use (const_int 1))])]
1835 "operands[4] = gen_label_rtx ();")
1837 ; Move a block of arbitrary length.
1839 (define_expand "movmem_long"
1841 [(clobber (match_dup 2))
1842 (clobber (match_dup 3))
1843 (set (match_operand:BLK 0 "memory_operand" "")
1844 (match_operand:BLK 1 "memory_operand" ""))
1845 (use (match_operand 2 "general_operand" ""))
1847 (clobber (reg:CC 33))])]
1850 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1851 rtx reg0 = gen_reg_rtx (dword_mode);
1852 rtx reg1 = gen_reg_rtx (dword_mode);
1853 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1854 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1855 rtx len0 = gen_lowpart (Pmode, reg0);
1856 rtx len1 = gen_lowpart (Pmode, reg1);
1858 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1859 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1860 emit_move_insn (len0, operands[2]);
1862 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1863 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1864 emit_move_insn (len1, operands[2]);
1866 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1867 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1872 (define_insn "*movmem_long_64"
1873 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1874 (clobber (match_operand:TI 1 "register_operand" "=d"))
1875 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1876 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1879 (clobber (reg:CC 33))]
1881 "mvcle\t%0,%1,0\;jo\t.-4"
1882 [(set_attr "length" "8")
1883 (set_attr "type" "vs")])
1885 (define_insn "*movmem_long_31"
1886 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1887 (clobber (match_operand:DI 1 "register_operand" "=d"))
1888 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1889 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1892 (clobber (reg:CC 33))]
1894 "mvcle\t%0,%1,0\;jo\t.-4"
1895 [(set_attr "length" "8")
1896 (set_attr "type" "vs")])
1899 ; clrmemM instruction pattern(s).
1902 (define_expand "clrmem<mode>"
1903 [(set (match_operand:BLK 0 "memory_operand" "")
1905 (use (match_operand:GPR 1 "general_operand" ""))
1906 (match_operand 2 "" "")]
1908 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1910 ; Clear a block that is up to 256 bytes in length.
1911 ; The block length is taken as (operands[1] % 256) + 1.
1913 (define_expand "clrmem_short"
1915 [(set (match_operand:BLK 0 "memory_operand" "")
1917 (use (match_operand 1 "nonmemory_operand" ""))
1918 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1919 (clobber (match_dup 2))
1920 (clobber (reg:CC 33))])]
1922 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1924 (define_insn "*clrmem_short"
1925 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1927 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1928 (use (match_operand 2 "immediate_operand" "X,R,X"))
1929 (clobber (match_scratch 3 "=X,X,&a"))
1930 (clobber (reg:CC 33))]
1931 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1932 && GET_MODE (operands[3]) == Pmode"
1934 [(set_attr "type" "cs")])
1937 [(set (match_operand:BLK 0 "memory_operand" "")
1939 (use (match_operand 1 "const_int_operand" ""))
1940 (use (match_operand 2 "immediate_operand" ""))
1942 (clobber (reg:CC 33))]
1945 [(set (match_dup 0) (const_int 0))
1947 (clobber (reg:CC 33))])]
1948 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1951 [(set (match_operand:BLK 0 "memory_operand" "")
1953 (use (match_operand 1 "register_operand" ""))
1954 (use (match_operand 2 "memory_operand" ""))
1956 (clobber (reg:CC 33))]
1959 [(unspec [(match_dup 1) (match_dup 2)
1960 (const_int 0)] UNSPEC_EXECUTE)
1961 (set (match_dup 0) (const_int 0))
1963 (clobber (reg:CC 33))])]
1967 [(set (match_operand:BLK 0 "memory_operand" "")
1969 (use (match_operand 1 "register_operand" ""))
1970 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1971 (clobber (match_operand 2 "register_operand" ""))
1972 (clobber (reg:CC 33))]
1973 "reload_completed && TARGET_CPU_ZARCH"
1974 [(set (match_dup 2) (label_ref (match_dup 3)))
1976 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
1977 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
1978 (set (match_dup 0) (const_int 0))
1980 (clobber (reg:CC 33))])]
1981 "operands[3] = gen_label_rtx ();")
1983 ; Clear a block of arbitrary length.
1985 (define_expand "clrmem_long"
1987 [(clobber (match_dup 1))
1988 (set (match_operand:BLK 0 "memory_operand" "")
1990 (use (match_operand 1 "general_operand" ""))
1992 (clobber (reg:CC 33))])]
1995 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1996 rtx reg0 = gen_reg_rtx (dword_mode);
1997 rtx reg1 = gen_reg_rtx (dword_mode);
1998 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1999 rtx len0 = gen_lowpart (Pmode, reg0);
2001 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2002 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2003 emit_move_insn (len0, operands[1]);
2005 emit_move_insn (reg1, const0_rtx);
2007 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2012 (define_insn "*clrmem_long_64"
2013 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2014 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2017 (use (match_operand:TI 1 "register_operand" "d"))
2018 (clobber (reg:CC 33))]
2020 "mvcle\t%0,%1,0\;jo\t.-4"
2021 [(set_attr "length" "8")
2022 (set_attr "type" "vs")])
2024 (define_insn "*clrmem_long_31"
2025 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2026 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2029 (use (match_operand:DI 1 "register_operand" "d"))
2030 (clobber (reg:CC 33))]
2032 "mvcle\t%0,%1,0\;jo\t.-4"
2033 [(set_attr "length" "8")
2034 (set_attr "type" "vs")])
2037 ; cmpmemM instruction pattern(s).
2040 (define_expand "cmpmemsi"
2041 [(set (match_operand:SI 0 "register_operand" "")
2042 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2043 (match_operand:BLK 2 "memory_operand" "") ) )
2044 (use (match_operand:SI 3 "general_operand" ""))
2045 (use (match_operand:SI 4 "" ""))]
2047 "s390_expand_cmpmem (operands[0], operands[1],
2048 operands[2], operands[3]); DONE;")
2050 ; Compare a block that is up to 256 bytes in length.
2051 ; The block length is taken as (operands[2] % 256) + 1.
2053 (define_expand "cmpmem_short"
2056 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2057 (match_operand:BLK 1 "memory_operand" "")))
2058 (use (match_operand 2 "nonmemory_operand" ""))
2059 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2060 (clobber (match_dup 3))])]
2062 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2064 (define_insn "*cmpmem_short"
2066 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2067 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2068 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2069 (use (match_operand 3 "immediate_operand" "X,R,X"))
2070 (clobber (match_scratch 4 "=X,X,&a"))]
2071 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2072 && GET_MODE (operands[4]) == Pmode"
2074 [(set_attr "type" "cs")])
2078 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2079 (match_operand:BLK 1 "memory_operand" "")))
2080 (use (match_operand 2 "const_int_operand" ""))
2081 (use (match_operand 3 "immediate_operand" ""))
2082 (clobber (scratch))]
2085 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2086 (use (match_dup 2))])]
2087 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2091 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2092 (match_operand:BLK 1 "memory_operand" "")))
2093 (use (match_operand 2 "register_operand" ""))
2094 (use (match_operand 3 "memory_operand" ""))
2095 (clobber (scratch))]
2098 [(unspec [(match_dup 2) (match_dup 3)
2099 (const_int 0)] UNSPEC_EXECUTE)
2100 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2101 (use (const_int 1))])]
2106 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2107 (match_operand:BLK 1 "memory_operand" "")))
2108 (use (match_operand 2 "register_operand" ""))
2109 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2110 (clobber (match_operand 3 "register_operand" ""))]
2111 "reload_completed && TARGET_CPU_ZARCH"
2112 [(set (match_dup 3) (label_ref (match_dup 4)))
2114 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2115 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2116 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2117 (use (const_int 1))])]
2118 "operands[4] = gen_label_rtx ();")
2120 ; Compare a block of arbitrary length.
2122 (define_expand "cmpmem_long"
2124 [(clobber (match_dup 2))
2125 (clobber (match_dup 3))
2127 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2128 (match_operand:BLK 1 "memory_operand" "")))
2129 (use (match_operand 2 "general_operand" ""))
2130 (use (match_dup 3))])]
2133 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2134 rtx reg0 = gen_reg_rtx (dword_mode);
2135 rtx reg1 = gen_reg_rtx (dword_mode);
2136 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2137 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2138 rtx len0 = gen_lowpart (Pmode, reg0);
2139 rtx len1 = gen_lowpart (Pmode, reg1);
2141 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2142 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2143 emit_move_insn (len0, operands[2]);
2145 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2146 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2147 emit_move_insn (len1, operands[2]);
2149 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2150 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2155 (define_insn "*cmpmem_long_64"
2156 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2157 (clobber (match_operand:TI 1 "register_operand" "=d"))
2159 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2160 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2162 (use (match_dup 3))]
2164 "clcle\t%0,%1,0\;jo\t.-4"
2165 [(set_attr "length" "8")
2166 (set_attr "type" "vs")])
2168 (define_insn "*cmpmem_long_31"
2169 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2170 (clobber (match_operand:DI 1 "register_operand" "=d"))
2172 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2173 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2175 (use (match_dup 3))]
2177 "clcle\t%0,%1,0\;jo\t.-4"
2178 [(set_attr "length" "8")
2179 (set_attr "type" "vs")])
2181 ; Convert CCUmode condition code to integer.
2182 ; Result is zero if EQ, positive if LTU, negative if GTU.
2184 (define_insn_and_split "cmpint"
2185 [(set (match_operand:SI 0 "register_operand" "=d")
2186 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2188 (clobber (reg:CC 33))]
2192 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2194 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2195 (clobber (reg:CC 33))])])
2197 (define_insn_and_split "*cmpint_cc"
2199 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2202 (set (match_operand:SI 0 "register_operand" "=d")
2203 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2204 "s390_match_ccmode (insn, CCSmode)"
2206 "&& reload_completed"
2207 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2209 [(set (match_dup 2) (match_dup 3))
2210 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2212 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2213 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2214 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2217 (define_insn_and_split "*cmpint_sign"
2218 [(set (match_operand:DI 0 "register_operand" "=d")
2219 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2221 (clobber (reg:CC 33))]
2224 "&& reload_completed"
2225 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2227 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2228 (clobber (reg:CC 33))])])
2230 (define_insn_and_split "*cmpint_sign_cc"
2232 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2233 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2235 (const_int 32)) (const_int 32))
2237 (set (match_operand:DI 0 "register_operand" "=d")
2238 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2239 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2241 "&& reload_completed"
2242 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2244 [(set (match_dup 2) (match_dup 3))
2245 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2247 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2248 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2249 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2254 ;;- Conversion instructions.
2258 (define_insn "*sethigh<mode>si"
2259 [(set (match_operand:SI 0 "register_operand" "=d,d")
2260 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2261 (clobber (reg:CC 33))]
2264 icm\t%0,<icm_hi>,%S1
2265 icmy\t%0,<icm_hi>,%S1"
2266 [(set_attr "op_type" "RS,RSY")])
2268 (define_insn "*sethighqidi_64"
2269 [(set (match_operand:DI 0 "register_operand" "=d")
2270 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2271 (clobber (reg:CC 33))]
2274 [(set_attr "op_type" "RSY")])
2276 (define_insn "*sethighqidi_31"
2277 [(set (match_operand:DI 0 "register_operand" "=d,d")
2278 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2279 (clobber (reg:CC 33))]
2284 [(set_attr "op_type" "RS,RSY")])
2286 (define_insn_and_split "*extractqi"
2287 [(set (match_operand:SI 0 "register_operand" "=d")
2288 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2289 (match_operand 2 "const_int_operand" "n")
2291 (clobber (reg:CC 33))]
2293 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2295 "&& reload_completed"
2297 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2298 (clobber (reg:CC 33))])
2299 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2301 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2302 operands[1] = change_address (operands[1], QImode, 0);
2305 (define_insn_and_split "*extracthi"
2306 [(set (match_operand:SI 0 "register_operand" "=d")
2307 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2308 (match_operand 2 "const_int_operand" "n")
2310 (clobber (reg:CC 33))]
2312 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2314 "&& reload_completed"
2316 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2317 (clobber (reg:CC 33))])
2318 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2320 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2321 operands[1] = change_address (operands[1], HImode, 0);
2325 ; extendsidi2 instruction pattern(s).
2328 (define_expand "extendsidi2"
2329 [(set (match_operand:DI 0 "register_operand" "")
2330 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2336 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2337 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2338 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2339 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2345 (define_insn "*extendsidi2"
2346 [(set (match_operand:DI 0 "register_operand" "=d,d")
2347 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2352 [(set_attr "op_type" "RRE,RXY")])
2355 ; extend(hi|qi)di2 instruction pattern(s).
2358 (define_expand "extend<mode>di2"
2359 [(set (match_operand:DI 0 "register_operand" "")
2360 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2366 rtx tmp = gen_reg_rtx (SImode);
2367 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2368 emit_insn (gen_extendsidi2 (operands[0], tmp));
2373 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2374 GET_MODE_BITSIZE (<MODE>mode));
2375 operands[1] = gen_lowpart (DImode, operands[1]);
2376 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2377 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2383 (define_insn "*extendhidi2"
2384 [(set (match_operand:DI 0 "register_operand" "=d")
2385 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2388 [(set_attr "op_type" "RXY")])
2390 (define_insn "*extendqidi2"
2391 [(set (match_operand:DI 0 "register_operand" "=d")
2392 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2393 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2395 [(set_attr "op_type" "RXY")])
2397 (define_insn_and_split "*extendqidi2_short_displ"
2398 [(set (match_operand:DI 0 "register_operand" "=d")
2399 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2400 (clobber (reg:CC 33))]
2401 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2403 "&& reload_completed"
2405 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2406 (clobber (reg:CC 33))])
2408 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2409 (clobber (reg:CC 33))])]
2413 ; extend(hi|qi)si2 instruction pattern(s).
2416 (define_expand "extend<mode>si2"
2417 [(set (match_operand:SI 0 "register_operand" "")
2418 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2422 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2423 GET_MODE_BITSIZE(<MODE>mode));
2424 operands[1] = gen_lowpart (SImode, operands[1]);
2425 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2426 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2431 (define_insn "*extendhisi2"
2432 [(set (match_operand:SI 0 "register_operand" "=d,d")
2433 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2438 [(set_attr "op_type" "RX,RXY")])
2440 (define_insn "*extendqisi2"
2441 [(set (match_operand:SI 0 "register_operand" "=d")
2442 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2443 "TARGET_LONG_DISPLACEMENT"
2445 [(set_attr "op_type" "RXY")])
2447 (define_insn_and_split "*extendqisi2_short_displ"
2448 [(set (match_operand:SI 0 "register_operand" "=d")
2449 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2450 (clobber (reg:CC 33))]
2451 "!TARGET_LONG_DISPLACEMENT"
2453 "&& reload_completed"
2455 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2456 (clobber (reg:CC 33))])
2458 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2459 (clobber (reg:CC 33))])]
2463 ; extendqihi2 instruction pattern(s).
2468 ; zero_extendsidi2 instruction pattern(s).
2471 (define_expand "zero_extendsidi2"
2472 [(set (match_operand:DI 0 "register_operand" "")
2473 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2479 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2480 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2481 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2487 (define_insn "*zero_extendsidi2"
2488 [(set (match_operand:DI 0 "register_operand" "=d,d")
2489 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2494 [(set_attr "op_type" "RRE,RXY")])
2497 ; zero_extend(hi|qi)di2 instruction pattern(s).
2500 (define_expand "zero_extend<mode>di2"
2501 [(set (match_operand:DI 0 "register_operand" "")
2502 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2508 rtx tmp = gen_reg_rtx (SImode);
2509 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2510 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2515 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2516 GET_MODE_BITSIZE(<MODE>mode));
2517 operands[1] = gen_lowpart (DImode, operands[1]);
2518 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2519 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2525 (define_insn "*zero_extend<mode>di2"
2526 [(set (match_operand:DI 0 "register_operand" "=d")
2527 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2530 [(set_attr "op_type" "RXY")])
2533 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2536 (define_insn "*llgt_sidi"
2537 [(set (match_operand:DI 0 "register_operand" "=d")
2538 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2539 (const_int 2147483647)))]
2542 [(set_attr "op_type" "RXE")])
2544 (define_insn_and_split "*llgt_sidi_split"
2545 [(set (match_operand:DI 0 "register_operand" "=d")
2546 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2547 (const_int 2147483647)))
2548 (clobber (reg:CC 33))]
2551 "&& reload_completed"
2553 (and:DI (subreg:DI (match_dup 1) 0)
2554 (const_int 2147483647)))]
2557 (define_insn "*llgt_sisi"
2558 [(set (match_operand:SI 0 "register_operand" "=d,d")
2559 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2560 (const_int 2147483647)))]
2565 [(set_attr "op_type" "RRE,RXE")])
2567 (define_insn "*llgt_didi"
2568 [(set (match_operand:DI 0 "register_operand" "=d,d")
2569 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2570 (const_int 2147483647)))]
2575 [(set_attr "op_type" "RRE,RXE")])
2578 [(set (match_operand:GPR 0 "register_operand" "")
2579 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2580 (const_int 2147483647)))
2581 (clobber (reg:CC 33))]
2582 "TARGET_64BIT && reload_completed"
2584 (and:GPR (match_dup 1)
2585 (const_int 2147483647)))]
2589 ; zero_extend(hi|qi)si2 instruction pattern(s).
2592 (define_expand "zero_extend<mode>si2"
2593 [(set (match_operand:SI 0 "register_operand" "")
2594 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2598 operands[1] = gen_lowpart (SImode, operands[1]);
2599 emit_insn (gen_andsi3 (operands[0], operands[1],
2600 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2605 (define_insn "*zero_extend<mode>si2_64"
2606 [(set (match_operand:SI 0 "register_operand" "=d")
2607 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2610 [(set_attr "op_type" "RXY")])
2612 (define_insn_and_split "*zero_extendhisi2_31"
2613 [(set (match_operand:SI 0 "register_operand" "=&d")
2614 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2615 (clobber (reg:CC 33))]
2618 "&& reload_completed"
2619 [(set (match_dup 0) (const_int 0))
2621 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2622 (clobber (reg:CC 33))])]
2623 "operands[2] = gen_lowpart (HImode, operands[0]);")
2625 (define_insn_and_split "*zero_extendqisi2_31"
2626 [(set (match_operand:SI 0 "register_operand" "=&d")
2627 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2630 "&& reload_completed"
2631 [(set (match_dup 0) (const_int 0))
2632 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2633 "operands[2] = gen_lowpart (QImode, operands[0]);")
2636 ; zero_extendqihi2 instruction pattern(s).
2639 (define_expand "zero_extendqihi2"
2640 [(set (match_operand:HI 0 "register_operand" "")
2641 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2645 operands[1] = gen_lowpart (HImode, operands[1]);
2646 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2651 (define_insn "*zero_extendqihi2_64"
2652 [(set (match_operand:HI 0 "register_operand" "=d")
2653 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2656 [(set_attr "op_type" "RXY")])
2658 (define_insn_and_split "*zero_extendqihi2_31"
2659 [(set (match_operand:HI 0 "register_operand" "=&d")
2660 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2663 "&& reload_completed"
2664 [(set (match_dup 0) (const_int 0))
2665 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2666 "operands[2] = gen_lowpart (QImode, operands[0]);")
2670 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2673 (define_expand "fixuns_truncdfdi2"
2674 [(set (match_operand:DI 0 "register_operand" "")
2675 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2676 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2678 rtx label1 = gen_label_rtx ();
2679 rtx label2 = gen_label_rtx ();
2680 rtx temp = gen_reg_rtx (DFmode);
2681 operands[1] = force_reg (DFmode, operands[1]);
2683 emit_insn (gen_cmpdf (operands[1],
2684 CONST_DOUBLE_FROM_REAL_VALUE (
2685 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2686 emit_jump_insn (gen_blt (label1));
2687 emit_insn (gen_subdf3 (temp, operands[1],
2688 CONST_DOUBLE_FROM_REAL_VALUE (
2689 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2690 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2693 emit_label (label1);
2694 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2695 emit_label (label2);
2699 (define_expand "fix_truncdfdi2"
2700 [(set (match_operand:DI 0 "register_operand" "")
2701 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2702 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2704 operands[1] = force_reg (DFmode, operands[1]);
2705 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2709 (define_insn "fix_truncdfdi2_ieee"
2710 [(set (match_operand:DI 0 "register_operand" "=d")
2711 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2712 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2713 (clobber (reg:CC 33))]
2714 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2716 [(set_attr "op_type" "RRE")
2717 (set_attr "type" "ftoi")])
2720 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2723 (define_expand "fixuns_truncdfsi2"
2724 [(set (match_operand:SI 0 "register_operand" "")
2725 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2726 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2728 rtx label1 = gen_label_rtx ();
2729 rtx label2 = gen_label_rtx ();
2730 rtx temp = gen_reg_rtx (DFmode);
2732 operands[1] = force_reg (DFmode,operands[1]);
2733 emit_insn (gen_cmpdf (operands[1],
2734 CONST_DOUBLE_FROM_REAL_VALUE (
2735 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2736 emit_jump_insn (gen_blt (label1));
2737 emit_insn (gen_subdf3 (temp, operands[1],
2738 CONST_DOUBLE_FROM_REAL_VALUE (
2739 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2740 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2743 emit_label (label1);
2744 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2745 emit_label (label2);
2749 (define_expand "fix_truncdfsi2"
2750 [(set (match_operand:SI 0 "register_operand" "")
2751 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2754 if (TARGET_IBM_FLOAT)
2756 /* This is the algorithm from POP chapter A.5.7.2. */
2758 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2759 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2760 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2762 operands[1] = force_reg (DFmode, operands[1]);
2763 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2764 two31r, two32, temp));
2768 operands[1] = force_reg (DFmode, operands[1]);
2769 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2775 (define_insn "fix_truncdfsi2_ieee"
2776 [(set (match_operand:SI 0 "register_operand" "=d")
2777 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2778 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2779 (clobber (reg:CC 33))]
2780 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2782 [(set_attr "op_type" "RRE")
2783 (set_attr "type" "ftoi")])
2785 (define_insn "fix_truncdfsi2_ibm"
2786 [(set (match_operand:SI 0 "register_operand" "=d")
2787 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2788 (use (match_operand:DI 2 "immediate_operand" "m"))
2789 (use (match_operand:DI 3 "immediate_operand" "m"))
2790 (use (match_operand:BLK 4 "memory_operand" "m"))
2791 (clobber (reg:CC 33))]
2792 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2794 output_asm_insn ("sd\t%1,%2", operands);
2795 output_asm_insn ("aw\t%1,%3", operands);
2796 output_asm_insn ("std\t%1,%4", operands);
2797 output_asm_insn ("xi\t%N4,128", operands);
2800 [(set_attr "length" "20")])
2803 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2806 (define_expand "fixuns_truncsfdi2"
2807 [(set (match_operand:DI 0 "register_operand" "")
2808 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2809 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2811 rtx label1 = gen_label_rtx ();
2812 rtx label2 = gen_label_rtx ();
2813 rtx temp = gen_reg_rtx (SFmode);
2815 operands[1] = force_reg (SFmode, operands[1]);
2816 emit_insn (gen_cmpsf (operands[1],
2817 CONST_DOUBLE_FROM_REAL_VALUE (
2818 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
2819 emit_jump_insn (gen_blt (label1));
2821 emit_insn (gen_subsf3 (temp, operands[1],
2822 CONST_DOUBLE_FROM_REAL_VALUE (
2823 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
2824 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2827 emit_label (label1);
2828 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2829 emit_label (label2);
2833 (define_expand "fix_truncsfdi2"
2834 [(set (match_operand:DI 0 "register_operand" "")
2835 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2836 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2838 operands[1] = force_reg (SFmode, operands[1]);
2839 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2843 (define_insn "fix_truncsfdi2_ieee"
2844 [(set (match_operand:DI 0 "register_operand" "=d")
2845 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2846 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2847 (clobber (reg:CC 33))]
2848 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2850 [(set_attr "op_type" "RRE")
2851 (set_attr "type" "ftoi")])
2854 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2857 (define_expand "fixuns_truncsfsi2"
2858 [(set (match_operand:SI 0 "register_operand" "")
2859 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2860 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2862 rtx label1 = gen_label_rtx ();
2863 rtx label2 = gen_label_rtx ();
2864 rtx temp = gen_reg_rtx (SFmode);
2866 operands[1] = force_reg (SFmode, operands[1]);
2867 emit_insn (gen_cmpsf (operands[1],
2868 CONST_DOUBLE_FROM_REAL_VALUE (
2869 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
2870 emit_jump_insn (gen_blt (label1));
2871 emit_insn (gen_subsf3 (temp, operands[1],
2872 CONST_DOUBLE_FROM_REAL_VALUE (
2873 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
2874 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2877 emit_label (label1);
2878 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2879 emit_label (label2);
2883 (define_expand "fix_truncsfsi2"
2884 [(set (match_operand:SI 0 "register_operand" "")
2885 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2888 if (TARGET_IBM_FLOAT)
2890 /* Convert to DFmode and then use the POP algorithm. */
2891 rtx temp = gen_reg_rtx (DFmode);
2892 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2893 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2897 operands[1] = force_reg (SFmode, operands[1]);
2898 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2904 (define_insn "fix_truncsfsi2_ieee"
2905 [(set (match_operand:SI 0 "register_operand" "=d")
2906 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2907 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2908 (clobber (reg:CC 33))]
2909 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2911 [(set_attr "op_type" "RRE")
2912 (set_attr "type" "ftoi")])
2915 ; floatdi(df|sf)2 instruction pattern(s).
2918 (define_insn "floatdi<mode>2"
2919 [(set (match_operand:FPR 0 "register_operand" "=f")
2920 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2921 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2923 [(set_attr "op_type" "RRE")
2924 (set_attr "type" "itof" )])
2927 ; floatsidf2 instruction pattern(s).
2930 (define_expand "floatsidf2"
2931 [(set (match_operand:DF 0 "register_operand" "")
2932 (float:DF (match_operand:SI 1 "register_operand" "")))]
2935 if (TARGET_IBM_FLOAT)
2937 /* This is the algorithm from POP chapter A.5.7.1. */
2939 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2940 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2942 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2947 (define_insn "floatsidf2_ieee"
2948 [(set (match_operand:DF 0 "register_operand" "=f")
2949 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2950 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2952 [(set_attr "op_type" "RRE")
2953 (set_attr "type" "itof" )])
2955 (define_insn "floatsidf2_ibm"
2956 [(set (match_operand:DF 0 "register_operand" "=f")
2957 (float:DF (match_operand:SI 1 "register_operand" "d")))
2958 (use (match_operand:DI 2 "immediate_operand" "m"))
2959 (use (match_operand:BLK 3 "memory_operand" "m"))
2960 (clobber (reg:CC 33))]
2961 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2963 output_asm_insn ("st\t%1,%N3", operands);
2964 output_asm_insn ("xi\t%N3,128", operands);
2965 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2966 output_asm_insn ("ld\t%0,%3", operands);
2969 [(set_attr "length" "20")])
2972 ; floatsisf2 instruction pattern(s).
2975 (define_expand "floatsisf2"
2976 [(set (match_operand:SF 0 "register_operand" "")
2977 (float:SF (match_operand:SI 1 "register_operand" "")))]
2980 if (TARGET_IBM_FLOAT)
2982 /* Use the POP algorithm to convert to DFmode and then truncate. */
2983 rtx temp = gen_reg_rtx (DFmode);
2984 emit_insn (gen_floatsidf2 (temp, operands[1]));
2985 emit_insn (gen_truncdfsf2 (operands[0], temp));
2990 (define_insn "floatsisf2_ieee"
2991 [(set (match_operand:SF 0 "register_operand" "=f")
2992 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2993 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2995 [(set_attr "op_type" "RRE")
2996 (set_attr "type" "itof" )])
2999 ; truncdfsf2 instruction pattern(s).
3002 (define_expand "truncdfsf2"
3003 [(set (match_operand:SF 0 "register_operand" "")
3004 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3008 (define_insn "truncdfsf2_ieee"
3009 [(set (match_operand:SF 0 "register_operand" "=f")
3010 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3011 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3013 [(set_attr "op_type" "RRE")])
3015 (define_insn "truncdfsf2_ibm"
3016 [(set (match_operand:SF 0 "register_operand" "=f,f")
3017 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3018 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3022 [(set_attr "op_type" "RR,RX")
3023 (set_attr "type" "floadsf")])
3026 ; extendsfdf2 instruction pattern(s).
3029 (define_expand "extendsfdf2"
3030 [(set (match_operand:DF 0 "register_operand" "")
3031 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3034 if (TARGET_IBM_FLOAT)
3036 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3041 (define_insn "extendsfdf2_ieee"
3042 [(set (match_operand:DF 0 "register_operand" "=f,f")
3043 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3044 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3048 [(set_attr "op_type" "RRE,RXE")
3049 (set_attr "type" "floadsf")])
3051 (define_insn "extendsfdf2_ibm"
3052 [(set (match_operand:DF 0 "register_operand" "=f,f")
3053 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3054 (clobber (reg:CC 33))]
3055 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3057 sdr\t%0,%0\;ler\t%0,%1
3058 sdr\t%0,%0\;le\t%0,%1"
3059 [(set_attr "length" "4,6")
3060 (set_attr "type" "floadsf")])
3064 ;; ARITHMETIC OPERATIONS
3066 ; arithmetic operations set the ConditionCode,
3067 ; because of unpredictable Bits in Register for Halfword and Byte
3068 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3071 ;;- Add instructions.
3075 ; addti3 instruction pattern(s).
3078 (define_insn_and_split "addti3"
3079 [(set (match_operand:TI 0 "register_operand" "=&d")
3080 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3081 (match_operand:TI 2 "general_operand" "do") ) )
3082 (clobber (reg:CC 33))]
3085 "&& reload_completed"
3088 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3090 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3092 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3093 (ltu:DI (reg:CCL1 33) (const_int 0))))
3094 (clobber (reg:CC 33))])]
3095 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3096 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3097 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3098 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3099 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3100 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3103 ; adddi3 instruction pattern(s).
3106 (define_insn "*adddi3_sign"
3107 [(set (match_operand:DI 0 "register_operand" "=d,d")
3108 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3109 (match_operand:DI 1 "register_operand" "0,0")))
3110 (clobber (reg:CC 33))]
3115 [(set_attr "op_type" "RRE,RXY")])
3117 (define_insn "*adddi3_zero_cc"
3119 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3120 (match_operand:DI 1 "register_operand" "0,0"))
3122 (set (match_operand:DI 0 "register_operand" "=d,d")
3123 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3124 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3128 [(set_attr "op_type" "RRE,RXY")])
3130 (define_insn "*adddi3_zero_cconly"
3132 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3133 (match_operand:DI 1 "register_operand" "0,0"))
3135 (clobber (match_scratch:DI 0 "=d,d"))]
3136 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3140 [(set_attr "op_type" "RRE,RXY")])
3142 (define_insn "*adddi3_zero"
3143 [(set (match_operand:DI 0 "register_operand" "=d,d")
3144 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3145 (match_operand:DI 1 "register_operand" "0,0")))
3146 (clobber (reg:CC 33))]
3151 [(set_attr "op_type" "RRE,RXY")])
3153 (define_insn "*adddi3_imm_cc"
3155 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3156 (match_operand:DI 2 "const_int_operand" "K"))
3158 (set (match_operand:DI 0 "register_operand" "=d")
3159 (plus:DI (match_dup 1) (match_dup 2)))]
3161 && s390_match_ccmode (insn, CCAmode)
3162 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3164 [(set_attr "op_type" "RI")])
3166 (define_insn "*adddi3_carry1_cc"
3168 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3169 (match_operand:DI 2 "general_operand" "d,m"))
3171 (set (match_operand:DI 0 "register_operand" "=d,d")
3172 (plus:DI (match_dup 1) (match_dup 2)))]
3173 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3177 [(set_attr "op_type" "RRE,RXY")])
3179 (define_insn "*adddi3_carry1_cconly"
3181 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3182 (match_operand:DI 2 "general_operand" "d,m"))
3184 (clobber (match_scratch:DI 0 "=d,d"))]
3185 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3189 [(set_attr "op_type" "RRE,RXY")])
3191 (define_insn "*adddi3_carry2_cc"
3193 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3194 (match_operand:DI 2 "general_operand" "d,m"))
3196 (set (match_operand:DI 0 "register_operand" "=d,d")
3197 (plus:DI (match_dup 1) (match_dup 2)))]
3198 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3202 [(set_attr "op_type" "RRE,RXY")])
3204 (define_insn "*adddi3_carry2_cconly"
3206 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3207 (match_operand:DI 2 "general_operand" "d,m"))
3209 (clobber (match_scratch:DI 0 "=d,d"))]
3210 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3214 [(set_attr "op_type" "RRE,RXY")])
3216 (define_insn "*adddi3_cc"
3218 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3219 (match_operand:DI 2 "general_operand" "d,m"))
3221 (set (match_operand:DI 0 "register_operand" "=d,d")
3222 (plus:DI (match_dup 1) (match_dup 2)))]
3223 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3227 [(set_attr "op_type" "RRE,RXY")])
3229 (define_insn "*adddi3_cconly"
3231 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3232 (match_operand:DI 2 "general_operand" "d,m"))
3234 (clobber (match_scratch:DI 0 "=d,d"))]
3235 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3239 [(set_attr "op_type" "RRE,RXY")])
3241 (define_insn "*adddi3_cconly2"
3243 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3244 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3245 (clobber (match_scratch:DI 0 "=d,d"))]
3246 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3250 [(set_attr "op_type" "RRE,RXY")])
3252 (define_insn "*adddi3_64"
3253 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3254 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3255 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3256 (clobber (reg:CC 33))]
3262 [(set_attr "op_type" "RRE,RI,RXY")])
3264 (define_insn_and_split "*adddi3_31z"
3265 [(set (match_operand:DI 0 "register_operand" "=&d")
3266 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3267 (match_operand:DI 2 "general_operand" "do") ) )
3268 (clobber (reg:CC 33))]
3269 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3271 "&& reload_completed"
3274 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3276 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3278 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3279 (ltu:SI (reg:CCL1 33) (const_int 0))))
3280 (clobber (reg:CC 33))])]
3281 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3282 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3283 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3284 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3285 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3286 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3288 (define_insn_and_split "*adddi3_31"
3289 [(set (match_operand:DI 0 "register_operand" "=&d")
3290 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3291 (match_operand:DI 2 "general_operand" "do") ) )
3292 (clobber (reg:CC 33))]
3295 "&& reload_completed"
3297 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3298 (clobber (reg:CC 33))])
3301 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3303 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3305 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3307 (label_ref (match_dup 9))))
3309 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3310 (clobber (reg:CC 33))])
3312 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3313 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3314 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3315 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3316 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3317 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3318 operands[9] = gen_label_rtx ();")
3320 (define_expand "adddi3"
3322 [(set (match_operand:DI 0 "register_operand" "")
3323 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3324 (match_operand:DI 2 "general_operand" "")))
3325 (clobber (reg:CC 33))])]
3330 ; addsi3 instruction pattern(s).
3333 (define_insn "*addsi3_imm_cc"
3335 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3336 (match_operand:SI 2 "const_int_operand" "K"))
3338 (set (match_operand:SI 0 "register_operand" "=d")
3339 (plus:SI (match_dup 1) (match_dup 2)))]
3340 "s390_match_ccmode (insn, CCAmode)
3341 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3343 [(set_attr "op_type" "RI")])
3345 (define_insn "*addsi3_carry1_cc"
3347 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3348 (match_operand:SI 2 "general_operand" "d,R,T"))
3350 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3351 (plus:SI (match_dup 1) (match_dup 2)))]
3352 "s390_match_ccmode (insn, CCL1mode)"
3357 [(set_attr "op_type" "RR,RX,RXY")])
3359 (define_insn "*addsi3_carry1_cconly"
3361 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3362 (match_operand:SI 2 "general_operand" "d,R,T"))
3364 (clobber (match_scratch:SI 0 "=d,d,d"))]
3365 "s390_match_ccmode (insn, CCL1mode)"
3370 [(set_attr "op_type" "RR,RX,RXY")])
3372 (define_insn "*addsi3_carry2_cc"
3374 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3375 (match_operand:SI 2 "general_operand" "d,R,T"))
3377 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3378 (plus:SI (match_dup 1) (match_dup 2)))]
3379 "s390_match_ccmode (insn, CCL1mode)"
3384 [(set_attr "op_type" "RR,RX,RXY")])
3386 (define_insn "*addsi3_carry2_cconly"
3388 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3389 (match_operand:SI 2 "general_operand" "d,R,T"))
3391 (clobber (match_scratch:SI 0 "=d,d,d"))]
3392 "s390_match_ccmode (insn, CCL1mode)"
3397 [(set_attr "op_type" "RR,RX,RXY")])
3399 (define_insn "*addsi3_cc"
3401 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3402 (match_operand:SI 2 "general_operand" "d,R,T"))
3404 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3405 (plus:SI (match_dup 1) (match_dup 2)))]
3406 "s390_match_ccmode (insn, CCLmode)"
3411 [(set_attr "op_type" "RR,RX,RXY")])
3413 (define_insn "*addsi3_cconly"
3415 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3416 (match_operand:SI 2 "general_operand" "d,R,T"))
3418 (clobber (match_scratch:SI 0 "=d,d,d"))]
3419 "s390_match_ccmode (insn, CCLmode)"
3424 [(set_attr "op_type" "RR,RX,RXY")])
3426 (define_insn "*addsi3_cconly2"
3428 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3429 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3430 (clobber (match_scratch:SI 0 "=d,d,d"))]
3431 "s390_match_ccmode (insn, CCLmode)"
3436 [(set_attr "op_type" "RR,RX,RXY")])
3438 (define_insn "*addsi3_sign"
3439 [(set (match_operand:SI 0 "register_operand" "=d,d")
3440 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3441 (match_operand:SI 1 "register_operand" "0,0")))
3442 (clobber (reg:CC 33))]
3447 [(set_attr "op_type" "RX,RXY")])
3449 (define_insn "addsi3"
3450 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3451 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3452 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3453 (clobber (reg:CC 33))]
3460 [(set_attr "op_type" "RR,RI,RX,RXY")])
3463 ; add(df|sf)3 instruction pattern(s).
3466 (define_expand "add<mode>3"
3468 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3469 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3470 (match_operand:FPR 2 "general_operand" "f,R")))
3471 (clobber (reg:CC 33))])]
3475 (define_insn "*add<mode>3"
3476 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3477 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3478 (match_operand:FPR 2 "general_operand" "f,R")))
3479 (clobber (reg:CC 33))]
3480 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3484 [(set_attr "op_type" "RRE,RXE")
3485 (set_attr "type" "fsimp<mode>")])
3487 (define_insn "*add<mode>3_cc"
3489 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3490 (match_operand:FPR 2 "general_operand" "f,R"))
3491 (match_operand:FPR 3 "const0_operand" "")))
3492 (set (match_operand:FPR 0 "register_operand" "=f,f")
3493 (plus:FPR (match_dup 1) (match_dup 2)))]
3494 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3498 [(set_attr "op_type" "RRE,RXE")
3499 (set_attr "type" "fsimp<mode>")])
3501 (define_insn "*add<mode>3_cconly"
3503 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3504 (match_operand:FPR 2 "general_operand" "f,R"))
3505 (match_operand:FPR 3 "const0_operand" "")))
3506 (clobber (match_scratch:FPR 0 "=f,f"))]
3507 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3511 [(set_attr "op_type" "RRE,RXE")
3512 (set_attr "type" "fsimp<mode>")])
3514 (define_insn "*add<mode>3_ibm"
3515 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3516 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3517 (match_operand:FPR 2 "general_operand" "f,R")))
3518 (clobber (reg:CC 33))]
3519 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3523 [(set_attr "op_type" "RR,RX")
3524 (set_attr "type" "fsimp<mode>")])
3528 ;;- Subtract instructions.
3532 ; subti3 instruction pattern(s).
3535 (define_insn_and_split "subti3"
3536 [(set (match_operand:TI 0 "register_operand" "=&d")
3537 (minus:TI (match_operand:TI 1 "register_operand" "0")
3538 (match_operand:TI 2 "general_operand" "do") ) )
3539 (clobber (reg:CC 33))]
3542 "&& reload_completed"
3545 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3547 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3549 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3550 (gtu:DI (reg:CCL2 33) (const_int 0))))
3551 (clobber (reg:CC 33))])]
3552 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3553 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3554 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3555 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3556 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3557 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3560 ; subdi3 instruction pattern(s).
3563 (define_insn "*subdi3_sign"
3564 [(set (match_operand:DI 0 "register_operand" "=d,d")
3565 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3566 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3567 (clobber (reg:CC 33))]
3572 [(set_attr "op_type" "RRE,RXY")])
3574 (define_insn "*subdi3_zero_cc"
3576 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3577 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3579 (set (match_operand:DI 0 "register_operand" "=d,d")
3580 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3581 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3585 [(set_attr "op_type" "RRE,RXY")])
3587 (define_insn "*subdi3_zero_cconly"
3589 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3590 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3592 (clobber (match_scratch:DI 0 "=d,d"))]
3593 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3597 [(set_attr "op_type" "RRE,RXY")])
3599 (define_insn "*subdi3_zero"
3600 [(set (match_operand:DI 0 "register_operand" "=d,d")
3601 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3602 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3603 (clobber (reg:CC 33))]
3608 [(set_attr "op_type" "RRE,RXY")])
3610 (define_insn "*subdi3_borrow_cc"
3612 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3613 (match_operand:DI 2 "general_operand" "d,m"))
3615 (set (match_operand:DI 0 "register_operand" "=d,d")
3616 (minus:DI (match_dup 1) (match_dup 2)))]
3617 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3621 [(set_attr "op_type" "RRE,RXY")])
3623 (define_insn "*subdi3_borrow_cconly"
3625 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3626 (match_operand:DI 2 "general_operand" "d,m"))
3628 (clobber (match_scratch:DI 0 "=d,d"))]
3629 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3633 [(set_attr "op_type" "RRE,RXY")])
3635 (define_insn "*subdi3_cc"
3637 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3638 (match_operand:DI 2 "general_operand" "d,m"))
3640 (set (match_operand:DI 0 "register_operand" "=d,d")
3641 (minus:DI (match_dup 1) (match_dup 2)))]
3642 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3646 [(set_attr "op_type" "RRE,RXY")])
3648 (define_insn "*subdi3_cc2"
3650 (compare (match_operand:DI 1 "register_operand" "0,0")
3651 (match_operand:DI 2 "general_operand" "d,m")))
3652 (set (match_operand:DI 0 "register_operand" "=d,d")
3653 (minus:DI (match_dup 1) (match_dup 2)))]
3654 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3658 [(set_attr "op_type" "RRE,RXY")])
3660 (define_insn "*subdi3_cconly"
3662 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3663 (match_operand:DI 2 "general_operand" "d,m"))
3665 (clobber (match_scratch:DI 0 "=d,d"))]
3666 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3670 [(set_attr "op_type" "RRE,RXY")])
3672 (define_insn "*subdi3_cconly2"
3674 (compare (match_operand:DI 1 "register_operand" "0,0")
3675 (match_operand:DI 2 "general_operand" "d,m")))
3676 (clobber (match_scratch:DI 0 "=d,d"))]
3677 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3681 [(set_attr "op_type" "RRE,RXY")])
3683 (define_insn "*subdi3_64"
3684 [(set (match_operand:DI 0 "register_operand" "=d,d")
3685 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3686 (match_operand:DI 2 "general_operand" "d,m") ) )
3687 (clobber (reg:CC 33))]
3692 [(set_attr "op_type" "RRE,RRE")])
3694 (define_insn_and_split "*subdi3_31z"
3695 [(set (match_operand:DI 0 "register_operand" "=&d")
3696 (minus:DI (match_operand:DI 1 "register_operand" "0")
3697 (match_operand:DI 2 "general_operand" "do") ) )
3698 (clobber (reg:CC 33))]
3699 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3701 "&& reload_completed"
3704 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3706 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3708 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3709 (gtu:SI (reg:CCL2 33) (const_int 0))))
3710 (clobber (reg:CC 33))])]
3711 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3712 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3713 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3714 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3715 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3716 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3718 (define_insn_and_split "*subdi3_31"
3719 [(set (match_operand:DI 0 "register_operand" "=&d")
3720 (minus:DI (match_operand:DI 1 "register_operand" "0")
3721 (match_operand:DI 2 "general_operand" "do") ) )
3722 (clobber (reg:CC 33))]
3725 "&& reload_completed"
3727 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3728 (clobber (reg:CC 33))])
3731 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3733 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3735 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3737 (label_ref (match_dup 9))))
3739 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3740 (clobber (reg:CC 33))])
3742 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3743 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3744 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3745 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3746 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3747 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3748 operands[9] = gen_label_rtx ();")
3750 (define_expand "subdi3"
3752 [(set (match_operand:DI 0 "register_operand" "")
3753 (minus:DI (match_operand:DI 1 "register_operand" "")
3754 (match_operand:DI 2 "general_operand" "")))
3755 (clobber (reg:CC 33))])]
3760 ; subsi3 instruction pattern(s).
3763 (define_insn "*subsi3_borrow_cc"
3765 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3766 (match_operand:SI 2 "general_operand" "d,R,T"))
3768 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3769 (minus:SI (match_dup 1) (match_dup 2)))]
3770 "s390_match_ccmode (insn, CCL2mode)"
3775 [(set_attr "op_type" "RR,RX,RXY")])
3777 (define_insn "*subsi3_borrow_cconly"
3779 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3780 (match_operand:SI 2 "general_operand" "d,R,T"))
3782 (clobber (match_scratch:SI 0 "=d,d,d"))]
3783 "s390_match_ccmode (insn, CCL2mode)"
3788 [(set_attr "op_type" "RR,RX,RXY")])
3790 (define_insn "*subsi3_cc"
3792 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3793 (match_operand:SI 2 "general_operand" "d,R,T"))
3795 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3796 (minus:SI (match_dup 1) (match_dup 2)))]
3797 "s390_match_ccmode (insn, CCLmode)"
3802 [(set_attr "op_type" "RR,RX,RXY")])
3804 (define_insn "*subsi3_cc2"
3806 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3807 (match_operand:SI 2 "general_operand" "d,R,T")))
3808 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3809 (minus:SI (match_dup 1) (match_dup 2)))]
3810 "s390_match_ccmode (insn, CCL3mode)"
3815 [(set_attr "op_type" "RR,RX,RXY")])
3817 (define_insn "*subsi3_cconly"
3819 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3820 (match_operand:SI 2 "general_operand" "d,R,T"))
3822 (clobber (match_scratch:SI 0 "=d,d,d"))]
3823 "s390_match_ccmode (insn, CCLmode)"
3828 [(set_attr "op_type" "RR,RX,RXY")])
3830 (define_insn "*subsi3_cconly2"
3832 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3833 (match_operand:SI 2 "general_operand" "d,R,T")))
3834 (clobber (match_scratch:SI 0 "=d,d,d"))]
3835 "s390_match_ccmode (insn, CCL3mode)"
3840 [(set_attr "op_type" "RR,RX,RXY")])
3842 (define_insn "*subsi3_sign"
3843 [(set (match_operand:SI 0 "register_operand" "=d,d")
3844 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3845 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3846 (clobber (reg:CC 33))]
3851 [(set_attr "op_type" "RX,RXY")])
3853 (define_insn "subsi3"
3854 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3855 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3856 (match_operand:SI 2 "general_operand" "d,R,T")))
3857 (clobber (reg:CC 33))]
3863 [(set_attr "op_type" "RR,RX,RXY")])
3867 ; sub(df|sf)3 instruction pattern(s).
3870 (define_expand "sub<mode>3"
3872 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3873 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3874 (match_operand:FPR 2 "general_operand" "f,R")))
3875 (clobber (reg:CC 33))])]
3879 (define_insn "*sub<mode>3"
3880 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3881 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3882 (match_operand:FPR 2 "general_operand" "f,R")))
3883 (clobber (reg:CC 33))]
3884 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3888 [(set_attr "op_type" "RRE,RXE")
3889 (set_attr "type" "fsimp<mode>")])
3891 (define_insn "*sub<mode>3_cc"
3893 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3894 (match_operand:FPR 2 "general_operand" "f,R"))
3895 (match_operand:FPR 3 "const0_operand" "")))
3896 (set (match_operand:FPR 0 "register_operand" "=f,f")
3897 (minus:FPR (match_dup 1) (match_dup 2)))]
3898 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3902 [(set_attr "op_type" "RRE,RXE")
3903 (set_attr "type" "fsimp<mode>")])
3905 (define_insn "*sub<mode>3_cconly"
3907 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3908 (match_operand:FPR 2 "general_operand" "f,R"))
3909 (match_operand:FPR 3 "const0_operand" "")))
3910 (clobber (match_scratch:FPR 0 "=f,f"))]
3911 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3915 [(set_attr "op_type" "RRE,RXE")
3916 (set_attr "type" "fsimp<mode>")])
3918 (define_insn "*sub<mode>3_ibm"
3919 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3920 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3921 (match_operand:FPR 2 "general_operand" "f,R")))
3922 (clobber (reg:CC 33))]
3923 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3927 [(set_attr "op_type" "RR,RX")
3928 (set_attr "type" "fsimp<mode>")])
3932 ;;- Conditional add/subtract instructions.
3936 ; add(di|si)cc instruction pattern(s).
3939 (define_insn "*add<mode>3_alc_cc"
3942 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3943 (match_operand:GPR 2 "general_operand" "d,m"))
3944 (match_operand:GPR 3 "s390_alc_comparison" ""))
3946 (set (match_operand:GPR 0 "register_operand" "=d,d")
3947 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3948 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3952 [(set_attr "op_type" "RRE,RXY")])
3954 (define_insn "*add<mode>3_alc"
3955 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3956 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3957 (match_operand:GPR 2 "general_operand" "d,m"))
3958 (match_operand:GPR 3 "s390_alc_comparison" "")))
3959 (clobber (reg:CC 33))]
3964 [(set_attr "op_type" "RRE,RXY")])
3966 (define_insn "*sub<mode>3_slb_cc"
3969 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3970 (match_operand:GPR 2 "general_operand" "d,m"))
3971 (match_operand:GPR 3 "s390_slb_comparison" ""))
3973 (set (match_operand:GPR 0 "register_operand" "=d,d")
3974 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3975 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3979 [(set_attr "op_type" "RRE,RXY")])
3981 (define_insn "*sub<mode>3_slb"
3982 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3983 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3984 (match_operand:GPR 2 "general_operand" "d,m"))
3985 (match_operand:GPR 3 "s390_slb_comparison" "")))
3986 (clobber (reg:CC 33))]
3991 [(set_attr "op_type" "RRE,RXY")])
3993 (define_expand "add<mode>cc"
3994 [(match_operand:GPR 0 "register_operand" "")
3995 (match_operand 1 "comparison_operator" "")
3996 (match_operand:GPR 2 "register_operand" "")
3997 (match_operand:GPR 3 "const_int_operand" "")]
3999 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4000 s390_compare_op0, s390_compare_op1,
4001 operands[0], operands[2],
4002 operands[3])) FAIL; DONE;")
4005 ; scond instruction pattern(s).
4008 (define_insn_and_split "*scond<mode>"
4009 [(set (match_operand:GPR 0 "register_operand" "=&d")
4010 (match_operand:GPR 1 "s390_alc_comparison" ""))
4011 (clobber (reg:CC 33))]
4014 "&& reload_completed"
4015 [(set (match_dup 0) (const_int 0))
4017 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4019 (clobber (reg:CC 33))])]
4022 (define_insn_and_split "*scond<mode>_neg"
4023 [(set (match_operand:GPR 0 "register_operand" "=&d")
4024 (match_operand:GPR 1 "s390_slb_comparison" ""))
4025 (clobber (reg:CC 33))]
4028 "&& reload_completed"
4029 [(set (match_dup 0) (const_int 0))
4031 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4033 (clobber (reg:CC 33))])
4035 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4036 (clobber (reg:CC 33))])]
4040 (define_expand "s<code>"
4041 [(set (match_operand:SI 0 "register_operand" "")
4042 (SCOND (match_dup 0)
4045 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4046 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4050 ;;- Multiply instructions.
4054 ; muldi3 instruction pattern(s).
4057 (define_insn "*muldi3_sign"
4058 [(set (match_operand:DI 0 "register_operand" "=d,d")
4059 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4060 (match_operand:DI 1 "register_operand" "0,0")))]
4065 [(set_attr "op_type" "RRE,RXY")
4066 (set_attr "type" "imuldi")])
4068 (define_insn "muldi3"
4069 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4070 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4071 (match_operand:DI 2 "general_operand" "d,K,m")))]
4077 [(set_attr "op_type" "RRE,RI,RXY")
4078 (set_attr "type" "imuldi")])
4081 ; mulsi3 instruction pattern(s).
4084 (define_insn "*mulsi3_sign"
4085 [(set (match_operand:SI 0 "register_operand" "=d")
4086 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4087 (match_operand:SI 1 "register_operand" "0")))]
4090 [(set_attr "op_type" "RX")
4091 (set_attr "type" "imulhi")])
4093 (define_insn "mulsi3"
4094 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4095 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4096 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4103 [(set_attr "op_type" "RRE,RI,RX,RXY")
4104 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4107 ; mulsidi3 instruction pattern(s).
4110 (define_insn "mulsidi3"
4111 [(set (match_operand:DI 0 "register_operand" "=d,d")
4112 (mult:DI (sign_extend:DI
4113 (match_operand:SI 1 "register_operand" "%0,0"))
4115 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4120 [(set_attr "op_type" "RR,RX")
4121 (set_attr "type" "imulsi")])
4124 ; umulsidi3 instruction pattern(s).
4127 (define_insn "umulsidi3"
4128 [(set (match_operand:DI 0 "register_operand" "=d,d")
4129 (mult:DI (zero_extend:DI
4130 (match_operand:SI 1 "register_operand" "%0,0"))
4132 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4133 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4137 [(set_attr "op_type" "RRE,RXY")
4138 (set_attr "type" "imulsi")])
4141 ; mul(df|sf)3 instruction pattern(s).
4144 (define_expand "mul<mode>3"
4145 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4146 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4147 (match_operand:FPR 2 "general_operand" "f,R")))]
4151 (define_insn "*mul<mode>3"
4152 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4153 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4154 (match_operand:FPR 2 "general_operand" "f,R")))]
4155 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4159 [(set_attr "op_type" "RRE,RXE")
4160 (set_attr "type" "fmul<mode>")])
4162 (define_insn "*mul<mode>3_ibm"
4163 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4164 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4165 (match_operand:FPR 2 "general_operand" "f,R")))]
4166 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4170 [(set_attr "op_type" "RR,RX")
4171 (set_attr "type" "fmul<mode>")])
4173 (define_insn "*fmadd<mode>"
4174 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4175 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4176 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4177 (match_operand:FPR 3 "register_operand" "0,0")))]
4178 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4182 [(set_attr "op_type" "RRE,RXE")
4183 (set_attr "type" "fmul<mode>")])
4185 (define_insn "*fmsub<mode>"
4186 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4187 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4188 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4189 (match_operand:FPR 3 "register_operand" "0,0")))]
4190 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4194 [(set_attr "op_type" "RRE,RXE")
4195 (set_attr "type" "fmul<mode>")])
4198 ;;- Divide and modulo instructions.
4202 ; divmoddi4 instruction pattern(s).
4205 (define_expand "divmoddi4"
4206 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4207 (div:DI (match_operand:DI 1 "register_operand" "")
4208 (match_operand:DI 2 "general_operand" "")))
4209 (set (match_operand:DI 3 "general_operand" "")
4210 (mod:DI (match_dup 1) (match_dup 2)))])
4211 (clobber (match_dup 4))]
4214 rtx insn, div_equal, mod_equal;
4216 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4217 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4219 operands[4] = gen_reg_rtx(TImode);
4220 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4222 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4224 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4226 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4228 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4233 (define_insn "divmodtidi3"
4234 [(set (match_operand:TI 0 "register_operand" "=d,d")
4238 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4239 (match_operand:DI 2 "general_operand" "d,m")))
4241 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4246 [(set_attr "op_type" "RRE,RXY")
4247 (set_attr "type" "idiv")])
4249 (define_insn "divmodtisi3"
4250 [(set (match_operand:TI 0 "register_operand" "=d,d")
4254 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4256 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4259 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4264 [(set_attr "op_type" "RRE,RXY")
4265 (set_attr "type" "idiv")])
4268 ; udivmoddi4 instruction pattern(s).
4271 (define_expand "udivmoddi4"
4272 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4273 (udiv:DI (match_operand:DI 1 "general_operand" "")
4274 (match_operand:DI 2 "nonimmediate_operand" "")))
4275 (set (match_operand:DI 3 "general_operand" "")
4276 (umod:DI (match_dup 1) (match_dup 2)))])
4277 (clobber (match_dup 4))]
4280 rtx insn, div_equal, mod_equal, equal;
4282 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4283 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4284 equal = gen_rtx_IOR (TImode,
4285 gen_rtx_ASHIFT (TImode,
4286 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4288 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4290 operands[4] = gen_reg_rtx(TImode);
4291 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4292 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4293 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4294 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4296 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4298 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4300 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4302 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4304 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4309 (define_insn "udivmodtidi3"
4310 [(set (match_operand:TI 0 "register_operand" "=d,d")
4315 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4317 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4321 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4326 [(set_attr "op_type" "RRE,RXY")
4327 (set_attr "type" "idiv")])
4330 ; divmodsi4 instruction pattern(s).
4333 (define_expand "divmodsi4"
4334 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4335 (div:SI (match_operand:SI 1 "general_operand" "")
4336 (match_operand:SI 2 "nonimmediate_operand" "")))
4337 (set (match_operand:SI 3 "general_operand" "")
4338 (mod:SI (match_dup 1) (match_dup 2)))])
4339 (clobber (match_dup 4))]
4342 rtx insn, div_equal, mod_equal, equal;
4344 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4345 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4346 equal = gen_rtx_IOR (DImode,
4347 gen_rtx_ASHIFT (DImode,
4348 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4350 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4352 operands[4] = gen_reg_rtx(DImode);
4353 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4354 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4356 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4358 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4360 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4362 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4364 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4369 (define_insn "divmoddisi3"
4370 [(set (match_operand:DI 0 "register_operand" "=d,d")
4375 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4377 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4381 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4386 [(set_attr "op_type" "RR,RX")
4387 (set_attr "type" "idiv")])
4390 ; udivsi3 and umodsi3 instruction pattern(s).
4393 (define_expand "udivmodsi4"
4394 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4395 (udiv:SI (match_operand:SI 1 "general_operand" "")
4396 (match_operand:SI 2 "nonimmediate_operand" "")))
4397 (set (match_operand:SI 3 "general_operand" "")
4398 (umod:SI (match_dup 1) (match_dup 2)))])
4399 (clobber (match_dup 4))]
4400 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4402 rtx insn, div_equal, mod_equal, equal;
4404 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4405 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4406 equal = gen_rtx_IOR (DImode,
4407 gen_rtx_ASHIFT (DImode,
4408 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4410 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4412 operands[4] = gen_reg_rtx(DImode);
4413 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4414 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4415 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4416 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4418 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4420 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4422 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4424 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4426 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4431 (define_insn "udivmoddisi3"
4432 [(set (match_operand:DI 0 "register_operand" "=d,d")
4437 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4439 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4443 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4444 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4448 [(set_attr "op_type" "RRE,RXY")
4449 (set_attr "type" "idiv")])
4451 (define_expand "udivsi3"
4452 [(set (match_operand:SI 0 "register_operand" "=d")
4453 (udiv:SI (match_operand:SI 1 "general_operand" "")
4454 (match_operand:SI 2 "general_operand" "")))
4455 (clobber (match_dup 3))]
4456 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4458 rtx insn, udiv_equal, umod_equal, equal;
4460 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4461 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4462 equal = gen_rtx_IOR (DImode,
4463 gen_rtx_ASHIFT (DImode,
4464 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4466 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4468 operands[3] = gen_reg_rtx (DImode);
4470 if (CONSTANT_P (operands[2]))
4472 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4474 rtx label1 = gen_label_rtx ();
4476 operands[1] = make_safe_from (operands[1], operands[0]);
4477 emit_move_insn (operands[0], const0_rtx);
4478 emit_insn (gen_cmpsi (operands[1], operands[2]));
4479 emit_jump_insn (gen_bltu (label1));
4480 emit_move_insn (operands[0], const1_rtx);
4481 emit_label (label1);
4485 operands[2] = force_reg (SImode, operands[2]);
4486 operands[2] = make_safe_from (operands[2], operands[0]);
4488 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4489 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4492 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4494 insn = emit_move_insn (operands[0],
4495 gen_lowpart (SImode, operands[3]));
4497 gen_rtx_EXPR_LIST (REG_EQUAL,
4498 udiv_equal, REG_NOTES (insn));
4503 rtx label1 = gen_label_rtx ();
4504 rtx label2 = gen_label_rtx ();
4505 rtx label3 = gen_label_rtx ();
4507 operands[1] = force_reg (SImode, operands[1]);
4508 operands[1] = make_safe_from (operands[1], operands[0]);
4509 operands[2] = force_reg (SImode, operands[2]);
4510 operands[2] = make_safe_from (operands[2], operands[0]);
4512 emit_move_insn (operands[0], const0_rtx);
4513 emit_insn (gen_cmpsi (operands[2], operands[1]));
4514 emit_jump_insn (gen_bgtu (label3));
4515 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4516 emit_jump_insn (gen_blt (label2));
4517 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4518 emit_jump_insn (gen_beq (label1));
4519 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4520 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4523 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4525 insn = emit_move_insn (operands[0],
4526 gen_lowpart (SImode, operands[3]));
4528 gen_rtx_EXPR_LIST (REG_EQUAL,
4529 udiv_equal, REG_NOTES (insn));
4531 emit_label (label1);
4532 emit_move_insn (operands[0], operands[1]);
4534 emit_label (label2);
4535 emit_move_insn (operands[0], const1_rtx);
4536 emit_label (label3);
4538 emit_move_insn (operands[0], operands[0]);
4542 (define_expand "umodsi3"
4543 [(set (match_operand:SI 0 "register_operand" "=d")
4544 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4545 (match_operand:SI 2 "nonimmediate_operand" "")))
4546 (clobber (match_dup 3))]
4547 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4549 rtx insn, udiv_equal, umod_equal, equal;
4551 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4552 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4553 equal = gen_rtx_IOR (DImode,
4554 gen_rtx_ASHIFT (DImode,
4555 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4557 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4559 operands[3] = gen_reg_rtx (DImode);
4561 if (CONSTANT_P (operands[2]))
4563 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4565 rtx label1 = gen_label_rtx ();
4567 operands[1] = make_safe_from (operands[1], operands[0]);
4568 emit_move_insn (operands[0], operands[1]);
4569 emit_insn (gen_cmpsi (operands[0], operands[2]));
4570 emit_jump_insn (gen_bltu (label1));
4571 emit_insn (gen_abssi2 (operands[0], operands[2]));
4572 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4573 emit_label (label1);
4577 operands[2] = force_reg (SImode, operands[2]);
4578 operands[2] = make_safe_from (operands[2], operands[0]);
4580 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4581 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4584 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4586 insn = emit_move_insn (operands[0],
4587 gen_highpart (SImode, operands[3]));
4589 gen_rtx_EXPR_LIST (REG_EQUAL,
4590 umod_equal, REG_NOTES (insn));
4595 rtx label1 = gen_label_rtx ();
4596 rtx label2 = gen_label_rtx ();
4597 rtx label3 = gen_label_rtx ();
4599 operands[1] = force_reg (SImode, operands[1]);
4600 operands[1] = make_safe_from (operands[1], operands[0]);
4601 operands[2] = force_reg (SImode, operands[2]);
4602 operands[2] = make_safe_from (operands[2], operands[0]);
4604 emit_move_insn(operands[0], operands[1]);
4605 emit_insn (gen_cmpsi (operands[2], operands[1]));
4606 emit_jump_insn (gen_bgtu (label3));
4607 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4608 emit_jump_insn (gen_blt (label2));
4609 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4610 emit_jump_insn (gen_beq (label1));
4611 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4612 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4615 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4617 insn = emit_move_insn (operands[0],
4618 gen_highpart (SImode, operands[3]));
4620 gen_rtx_EXPR_LIST (REG_EQUAL,
4621 umod_equal, REG_NOTES (insn));
4623 emit_label (label1);
4624 emit_move_insn (operands[0], const0_rtx);
4626 emit_label (label2);
4627 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4628 emit_label (label3);
4634 ; div(df|sf)3 instruction pattern(s).
4637 (define_expand "div<mode>3"
4638 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4639 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4640 (match_operand:FPR 2 "general_operand" "f,R")))]
4644 (define_insn "*div<mode>3"
4645 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4646 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4647 (match_operand:FPR 2 "general_operand" "f,R")))]
4648 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4652 [(set_attr "op_type" "RRE,RXE")
4653 (set_attr "type" "fdiv<mode>")])
4655 (define_insn "*div<mode>3_ibm"
4656 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4657 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4658 (match_operand:FPR 2 "general_operand" "f,R")))]
4659 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4663 [(set_attr "op_type" "RR,RX")
4664 (set_attr "type" "fdiv<mode>")])
4668 ;;- And instructions.
4672 ; anddi3 instruction pattern(s).
4675 (define_insn "*anddi3_cc"
4677 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4678 (match_operand:DI 2 "general_operand" "d,m"))
4680 (set (match_operand:DI 0 "register_operand" "=d,d")
4681 (and:DI (match_dup 1) (match_dup 2)))]
4682 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4686 [(set_attr "op_type" "RRE,RXY")])
4688 (define_insn "*anddi3_cconly"
4690 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4691 (match_operand:DI 2 "general_operand" "d,m"))
4693 (clobber (match_scratch:DI 0 "=d,d"))]
4694 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4695 /* Do not steal TM patterns. */
4696 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4700 [(set_attr "op_type" "RRE,RXY")])
4702 (define_insn "*anddi3"
4703 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4704 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4705 "%d,o,0,0,0,0,0,0,0,0")
4706 (match_operand:DI 2 "general_operand"
4707 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4708 (clobber (reg:CC 33))]
4709 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4721 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4724 [(set (match_operand:DI 0 "s_operand" "")
4725 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4726 (clobber (reg:CC 33))]
4729 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4730 (clobber (reg:CC 33))])]
4731 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4733 (define_expand "anddi3"
4734 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4735 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
4736 (match_operand:DI 2 "general_operand" "")))
4737 (clobber (reg:CC 33))]
4739 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
4742 ; andsi3 instruction pattern(s).
4745 (define_insn "*andsi3_cc"
4747 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4748 (match_operand:SI 2 "general_operand" "d,R,T"))
4750 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4751 (and:SI (match_dup 1) (match_dup 2)))]
4752 "s390_match_ccmode(insn, CCTmode)"
4757 [(set_attr "op_type" "RR,RX,RXY")])
4759 (define_insn "*andsi3_cconly"
4761 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4762 (match_operand:SI 2 "general_operand" "d,R,T"))
4764 (clobber (match_scratch:SI 0 "=d,d,d"))]
4765 "s390_match_ccmode(insn, CCTmode)
4766 /* Do not steal TM patterns. */
4767 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4772 [(set_attr "op_type" "RR,RX,RXY")])
4774 (define_insn "*andsi3_zarch"
4775 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4776 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4777 "%d,o,0,0,0,0,0,0,0")
4778 (match_operand:SI 2 "general_operand"
4779 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4780 (clobber (reg:CC 33))]
4781 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4792 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4794 (define_insn "*andsi3_esa"
4795 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4796 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4797 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4798 (clobber (reg:CC 33))]
4799 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4805 [(set_attr "op_type" "RR,RX,SI,SS")])
4808 [(set (match_operand:SI 0 "s_operand" "")
4809 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4810 (clobber (reg:CC 33))]
4813 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4814 (clobber (reg:CC 33))])]
4815 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4817 (define_expand "andsi3"
4818 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4819 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
4820 (match_operand:SI 2 "general_operand" "")))
4821 (clobber (reg:CC 33))]
4823 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
4826 ; andhi3 instruction pattern(s).
4829 (define_insn "*andhi3_zarch"
4830 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4831 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4832 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4833 (clobber (reg:CC 33))]
4834 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4840 [(set_attr "op_type" "RR,RI,SI,SS")])
4842 (define_insn "*andhi3_esa"
4843 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4844 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4845 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4846 (clobber (reg:CC 33))]
4847 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4852 [(set_attr "op_type" "RR,SI,SS")])
4855 [(set (match_operand:HI 0 "s_operand" "")
4856 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4857 (clobber (reg:CC 33))]
4860 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4861 (clobber (reg:CC 33))])]
4862 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4864 (define_expand "andhi3"
4865 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4866 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
4867 (match_operand:HI 2 "general_operand" "")))
4868 (clobber (reg:CC 33))]
4870 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
4873 ; andqi3 instruction pattern(s).
4876 (define_insn "*andqi3_zarch"
4877 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4878 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4879 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4880 (clobber (reg:CC 33))]
4881 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4888 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4890 (define_insn "*andqi3_esa"
4891 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4892 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4893 (match_operand:QI 2 "general_operand" "d,n,Q")))
4894 (clobber (reg:CC 33))]
4895 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4900 [(set_attr "op_type" "RR,SI,SS")])
4902 (define_expand "andqi3"
4903 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4904 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
4905 (match_operand:QI 2 "general_operand" "")))
4906 (clobber (reg:CC 33))]
4908 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
4911 ; Block and (NC) patterns.
4915 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4916 (and:BLK (match_dup 0)
4917 (match_operand:BLK 1 "memory_operand" "Q")))
4918 (use (match_operand 2 "const_int_operand" "n"))
4919 (clobber (reg:CC 33))]
4920 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4921 "nc\t%O0(%2,%R0),%S1"
4922 [(set_attr "op_type" "SS")])
4925 [(set (match_operand 0 "memory_operand" "")
4927 (match_operand 1 "memory_operand" "")))
4928 (clobber (reg:CC 33))]
4930 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4931 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4933 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4935 (clobber (reg:CC 33))])]
4937 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4938 operands[0] = adjust_address (operands[0], BLKmode, 0);
4939 operands[1] = adjust_address (operands[1], BLKmode, 0);
4944 [(set (match_operand:BLK 0 "memory_operand" "")
4945 (and:BLK (match_dup 0)
4946 (match_operand:BLK 1 "memory_operand" "")))
4947 (use (match_operand 2 "const_int_operand" ""))
4948 (clobber (reg:CC 33))])
4950 [(set (match_operand:BLK 3 "memory_operand" "")
4951 (and:BLK (match_dup 3)
4952 (match_operand:BLK 4 "memory_operand" "")))
4953 (use (match_operand 5 "const_int_operand" ""))
4954 (clobber (reg:CC 33))])]
4955 "s390_offset_p (operands[0], operands[3], operands[2])
4956 && s390_offset_p (operands[1], operands[4], operands[2])
4957 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4959 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4961 (clobber (reg:CC 33))])]
4962 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4963 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4964 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4968 ;;- Bit set (inclusive or) instructions.
4972 ; iordi3 instruction pattern(s).
4975 (define_insn "*iordi3_cc"
4977 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4978 (match_operand:DI 2 "general_operand" "d,m"))
4980 (set (match_operand:DI 0 "register_operand" "=d,d")
4981 (ior:DI (match_dup 1) (match_dup 2)))]
4982 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4986 [(set_attr "op_type" "RRE,RXY")])
4988 (define_insn "*iordi3_cconly"
4990 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4991 (match_operand:DI 2 "general_operand" "d,m"))
4993 (clobber (match_scratch:DI 0 "=d,d"))]
4994 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4998 [(set_attr "op_type" "RRE,RXY")])
5000 (define_insn "*iordi3"
5001 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5002 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5003 (match_operand:DI 2 "general_operand"
5004 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5005 (clobber (reg:CC 33))]
5006 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5016 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5019 [(set (match_operand:DI 0 "s_operand" "")
5020 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5021 (clobber (reg:CC 33))]
5024 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5025 (clobber (reg:CC 33))])]
5026 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5028 (define_expand "iordi3"
5029 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5030 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5031 (match_operand:DI 2 "general_operand" "")))
5032 (clobber (reg:CC 33))]
5034 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5037 ; iorsi3 instruction pattern(s).
5040 (define_insn "*iorsi3_cc"
5042 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5043 (match_operand:SI 2 "general_operand" "d,R,T"))
5045 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5046 (ior:SI (match_dup 1) (match_dup 2)))]
5047 "s390_match_ccmode(insn, CCTmode)"
5052 [(set_attr "op_type" "RR,RX,RXY")])
5054 (define_insn "*iorsi3_cconly"
5056 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5057 (match_operand:SI 2 "general_operand" "d,R,T"))
5059 (clobber (match_scratch:SI 0 "=d,d,d"))]
5060 "s390_match_ccmode(insn, CCTmode)"
5065 [(set_attr "op_type" "RR,RX,RXY")])
5067 (define_insn "*iorsi3_zarch"
5068 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5069 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5070 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5071 (clobber (reg:CC 33))]
5072 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5081 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5083 (define_insn "*iorsi3_esa"
5084 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5085 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5086 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5087 (clobber (reg:CC 33))]
5088 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5094 [(set_attr "op_type" "RR,RX,SI,SS")])
5097 [(set (match_operand:SI 0 "s_operand" "")
5098 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5099 (clobber (reg:CC 33))]
5102 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5103 (clobber (reg:CC 33))])]
5104 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5106 (define_expand "iorsi3"
5107 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5108 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5109 (match_operand:SI 2 "general_operand" "")))
5110 (clobber (reg:CC 33))]
5112 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5115 ; iorhi3 instruction pattern(s).
5118 (define_insn "*iorhi3_zarch"
5119 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5120 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5121 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5122 (clobber (reg:CC 33))]
5123 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5129 [(set_attr "op_type" "RR,RI,SI,SS")])
5131 (define_insn "*iorhi3_esa"
5132 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5133 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5134 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5135 (clobber (reg:CC 33))]
5136 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5141 [(set_attr "op_type" "RR,SI,SS")])
5144 [(set (match_operand:HI 0 "s_operand" "")
5145 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5146 (clobber (reg:CC 33))]
5149 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5150 (clobber (reg:CC 33))])]
5151 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5153 (define_expand "iorhi3"
5154 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5155 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5156 (match_operand:HI 2 "general_operand" "")))
5157 (clobber (reg:CC 33))]
5159 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5162 ; iorqi3 instruction pattern(s).
5165 (define_insn "*iorqi3_zarch"
5166 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5167 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5168 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5169 (clobber (reg:CC 33))]
5170 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5177 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5179 (define_insn "*iorqi3_esa"
5180 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5181 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5182 (match_operand:QI 2 "general_operand" "d,n,Q")))
5183 (clobber (reg:CC 33))]
5184 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5189 [(set_attr "op_type" "RR,SI,SS")])
5191 (define_expand "iorqi3"
5192 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5193 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5194 (match_operand:QI 2 "general_operand" "")))
5195 (clobber (reg:CC 33))]
5197 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5200 ; Block inclusive or (OC) patterns.
5204 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5205 (ior:BLK (match_dup 0)
5206 (match_operand:BLK 1 "memory_operand" "Q")))
5207 (use (match_operand 2 "const_int_operand" "n"))
5208 (clobber (reg:CC 33))]
5209 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5210 "oc\t%O0(%2,%R0),%S1"
5211 [(set_attr "op_type" "SS")])
5214 [(set (match_operand 0 "memory_operand" "")
5216 (match_operand 1 "memory_operand" "")))
5217 (clobber (reg:CC 33))]
5219 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5220 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5222 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5224 (clobber (reg:CC 33))])]
5226 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5227 operands[0] = adjust_address (operands[0], BLKmode, 0);
5228 operands[1] = adjust_address (operands[1], BLKmode, 0);
5233 [(set (match_operand:BLK 0 "memory_operand" "")
5234 (ior:BLK (match_dup 0)
5235 (match_operand:BLK 1 "memory_operand" "")))
5236 (use (match_operand 2 "const_int_operand" ""))
5237 (clobber (reg:CC 33))])
5239 [(set (match_operand:BLK 3 "memory_operand" "")
5240 (ior:BLK (match_dup 3)
5241 (match_operand:BLK 4 "memory_operand" "")))
5242 (use (match_operand 5 "const_int_operand" ""))
5243 (clobber (reg:CC 33))])]
5244 "s390_offset_p (operands[0], operands[3], operands[2])
5245 && s390_offset_p (operands[1], operands[4], operands[2])
5246 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5248 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5250 (clobber (reg:CC 33))])]
5251 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5252 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5253 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5257 ;;- Xor instructions.
5261 ; xordi3 instruction pattern(s).
5264 (define_insn "*xordi3_cc"
5266 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5267 (match_operand:DI 2 "general_operand" "d,m"))
5269 (set (match_operand:DI 0 "register_operand" "=d,d")
5270 (xor:DI (match_dup 1) (match_dup 2)))]
5271 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5275 [(set_attr "op_type" "RRE,RXY")])
5277 (define_insn "*xordi3_cconly"
5279 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5280 (match_operand:DI 2 "general_operand" "d,m"))
5282 (clobber (match_scratch:DI 0 "=d,d"))]
5283 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5287 [(set_attr "op_type" "RRE,RXY")])
5289 (define_insn "*xordi3"
5290 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5291 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5292 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5293 (clobber (reg:CC 33))]
5294 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5300 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5303 [(set (match_operand:DI 0 "s_operand" "")
5304 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5305 (clobber (reg:CC 33))]
5308 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5309 (clobber (reg:CC 33))])]
5310 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5312 (define_expand "xordi3"
5313 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5314 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5315 (match_operand:DI 2 "general_operand" "")))
5316 (clobber (reg:CC 33))]
5318 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5321 ; xorsi3 instruction pattern(s).
5324 (define_insn "*xorsi3_cc"
5326 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5327 (match_operand:SI 2 "general_operand" "d,R,T"))
5329 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5330 (xor:SI (match_dup 1) (match_dup 2)))]
5331 "s390_match_ccmode(insn, CCTmode)"
5336 [(set_attr "op_type" "RR,RX,RXY")])
5338 (define_insn "*xorsi3_cconly"
5340 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5341 (match_operand:SI 2 "general_operand" "d,R,T"))
5343 (clobber (match_scratch:SI 0 "=d,d,d"))]
5344 "s390_match_ccmode(insn, CCTmode)"
5349 [(set_attr "op_type" "RR,RX,RXY")])
5351 (define_insn "*xorsi3"
5352 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5353 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5354 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5355 (clobber (reg:CC 33))]
5356 "s390_logical_operator_ok_p (operands)"
5363 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5366 [(set (match_operand:SI 0 "s_operand" "")
5367 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5368 (clobber (reg:CC 33))]
5371 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5372 (clobber (reg:CC 33))])]
5373 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5375 (define_expand "xorsi3"
5376 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5377 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5378 (match_operand:SI 2 "general_operand" "")))
5379 (clobber (reg:CC 33))]
5381 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5384 ; xorhi3 instruction pattern(s).
5387 (define_insn "*xorhi3"
5388 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5389 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5390 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5391 (clobber (reg:CC 33))]
5392 "s390_logical_operator_ok_p (operands)"
5397 [(set_attr "op_type" "RR,SI,SS")])
5400 [(set (match_operand:HI 0 "s_operand" "")
5401 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5402 (clobber (reg:CC 33))]
5405 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5406 (clobber (reg:CC 33))])]
5407 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5409 (define_expand "xorhi3"
5410 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5411 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5412 (match_operand:HI 2 "general_operand" "")))
5413 (clobber (reg:CC 33))]
5415 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5418 ; xorqi3 instruction pattern(s).
5421 (define_insn "*xorqi3"
5422 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5423 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5424 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5425 (clobber (reg:CC 33))]
5426 "s390_logical_operator_ok_p (operands)"
5432 [(set_attr "op_type" "RR,SI,SIY,SS")])
5434 (define_expand "xorqi3"
5435 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5436 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5437 (match_operand:QI 2 "general_operand" "")))
5438 (clobber (reg:CC 33))]
5440 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5443 ; Block exclusive or (XC) patterns.
5447 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5448 (xor:BLK (match_dup 0)
5449 (match_operand:BLK 1 "memory_operand" "Q")))
5450 (use (match_operand 2 "const_int_operand" "n"))
5451 (clobber (reg:CC 33))]
5452 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5453 "xc\t%O0(%2,%R0),%S1"
5454 [(set_attr "op_type" "SS")])
5457 [(set (match_operand 0 "memory_operand" "")
5459 (match_operand 1 "memory_operand" "")))
5460 (clobber (reg:CC 33))]
5462 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5463 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5465 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5467 (clobber (reg:CC 33))])]
5469 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5470 operands[0] = adjust_address (operands[0], BLKmode, 0);
5471 operands[1] = adjust_address (operands[1], BLKmode, 0);
5476 [(set (match_operand:BLK 0 "memory_operand" "")
5477 (xor:BLK (match_dup 0)
5478 (match_operand:BLK 1 "memory_operand" "")))
5479 (use (match_operand 2 "const_int_operand" ""))
5480 (clobber (reg:CC 33))])
5482 [(set (match_operand:BLK 3 "memory_operand" "")
5483 (xor:BLK (match_dup 3)
5484 (match_operand:BLK 4 "memory_operand" "")))
5485 (use (match_operand 5 "const_int_operand" ""))
5486 (clobber (reg:CC 33))])]
5487 "s390_offset_p (operands[0], operands[3], operands[2])
5488 && s390_offset_p (operands[1], operands[4], operands[2])
5489 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5491 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5493 (clobber (reg:CC 33))])]
5494 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5495 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5496 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5499 ; Block xor (XC) patterns with src == dest.
5502 (define_insn "*xc_zero"
5503 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5505 (use (match_operand 1 "const_int_operand" "n"))
5506 (clobber (reg:CC 33))]
5507 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5508 "xc\t%O0(%1,%R0),%S0"
5509 [(set_attr "op_type" "SS")])
5513 [(set (match_operand:BLK 0 "memory_operand" "")
5515 (use (match_operand 1 "const_int_operand" ""))
5516 (clobber (reg:CC 33))])
5518 [(set (match_operand:BLK 2 "memory_operand" "")
5520 (use (match_operand 3 "const_int_operand" ""))
5521 (clobber (reg:CC 33))])]
5522 "s390_offset_p (operands[0], operands[2], operands[1])
5523 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5525 [(set (match_dup 4) (const_int 0))
5527 (clobber (reg:CC 33))])]
5528 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5529 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5533 ;;- Negate instructions.
5537 ; neg(di|si)2 instruction pattern(s).
5540 (define_expand "neg<mode>2"
5542 [(set (match_operand:DSI 0 "register_operand" "=d")
5543 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5544 (clobber (reg:CC 33))])]
5548 (define_insn "*negdi2_sign_cc"
5550 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5551 (match_operand:SI 1 "register_operand" "d") 0)
5552 (const_int 32)) (const_int 32)))
5554 (set (match_operand:DI 0 "register_operand" "=d")
5555 (neg:DI (sign_extend:DI (match_dup 1))))]
5556 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5558 [(set_attr "op_type" "RRE")])
5560 (define_insn "*negdi2_sign"
5561 [(set (match_operand:DI 0 "register_operand" "=d")
5562 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5563 (clobber (reg:CC 33))]
5566 [(set_attr "op_type" "RRE")])
5568 (define_insn "*neg<mode>2_cc"
5570 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5572 (set (match_operand:GPR 0 "register_operand" "=d")
5573 (neg:GPR (match_dup 1)))]
5574 "s390_match_ccmode (insn, CCAmode)"
5576 [(set_attr "op_type" "RR<E>")])
5578 (define_insn "*neg<mode>2_cconly"
5580 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5582 (clobber (match_scratch:GPR 0 "=d"))]
5583 "s390_match_ccmode (insn, CCAmode)"
5585 [(set_attr "op_type" "RR<E>")])
5587 (define_insn "*neg<mode>2"
5588 [(set (match_operand:GPR 0 "register_operand" "=d")
5589 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5590 (clobber (reg:CC 33))]
5593 [(set_attr "op_type" "RR<E>")])
5595 (define_insn_and_split "*negdi2_31"
5596 [(set (match_operand:DI 0 "register_operand" "=d")
5597 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5598 (clobber (reg:CC 33))]
5601 "&& reload_completed"
5603 [(set (match_dup 2) (neg:SI (match_dup 3)))
5604 (clobber (reg:CC 33))])
5607 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5608 (set (match_dup 4) (neg:SI (match_dup 5)))])
5610 (if_then_else (ne (reg:CCAP 33) (const_int 0))
5612 (label_ref (match_dup 6))))
5614 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5615 (clobber (reg:CC 33))])
5617 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5618 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5619 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5620 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5621 operands[6] = gen_label_rtx ();")
5624 ; neg(df|sf)2 instruction pattern(s).
5627 (define_expand "neg<mode>2"
5629 [(set (match_operand:FPR 0 "register_operand" "=f")
5630 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5631 (clobber (reg:CC 33))])]
5635 (define_insn "*neg<mode>2_cc"
5637 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5638 (match_operand:FPR 2 "const0_operand" "")))
5639 (set (match_operand:FPR 0 "register_operand" "=f")
5640 (neg:FPR (match_dup 1)))]
5641 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5643 [(set_attr "op_type" "RRE")
5644 (set_attr "type" "fsimp<mode>")])
5646 (define_insn "*neg<mode>2_cconly"
5648 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5649 (match_operand:FPR 2 "const0_operand" "")))
5650 (clobber (match_scratch:FPR 0 "=f"))]
5651 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5653 [(set_attr "op_type" "RRE")
5654 (set_attr "type" "fsimp<mode>")])
5656 (define_insn "*neg<mode>2"
5657 [(set (match_operand:FPR 0 "register_operand" "=f")
5658 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5659 (clobber (reg:CC 33))]
5660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5662 [(set_attr "op_type" "RRE")
5663 (set_attr "type" "fsimp<mode>")])
5665 (define_insn "*neg<mode>2_ibm"
5666 [(set (match_operand:FPR 0 "register_operand" "=f")
5667 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5668 (clobber (reg:CC 33))]
5669 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5671 [(set_attr "op_type" "RR")
5672 (set_attr "type" "fsimp<mode>")])
5676 ;;- Absolute value instructions.
5680 ; abs(di|si)2 instruction pattern(s).
5683 (define_insn "*absdi2_sign_cc"
5685 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5686 (match_operand:SI 1 "register_operand" "d") 0)
5687 (const_int 32)) (const_int 32)))
5689 (set (match_operand:DI 0 "register_operand" "=d")
5690 (abs:DI (sign_extend:DI (match_dup 1))))]
5691 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5693 [(set_attr "op_type" "RRE")])
5695 (define_insn "*absdi2_sign"
5696 [(set (match_operand:DI 0 "register_operand" "=d")
5697 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5698 (clobber (reg:CC 33))]
5701 [(set_attr "op_type" "RRE")])
5703 (define_insn "*abs<mode>2_cc"
5705 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5707 (set (match_operand:GPR 0 "register_operand" "=d")
5708 (abs:GPR (match_dup 1)))]
5709 "s390_match_ccmode (insn, CCAmode)"
5711 [(set_attr "op_type" "RR<E>")])
5713 (define_insn "*abs<mode>2_cconly"
5715 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5717 (clobber (match_scratch:GPR 0 "=d"))]
5718 "s390_match_ccmode (insn, CCAmode)"
5720 [(set_attr "op_type" "RR<E>")])
5722 (define_insn "abs<mode>2"
5723 [(set (match_operand:GPR 0 "register_operand" "=d")
5724 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5725 (clobber (reg:CC 33))]
5728 [(set_attr "op_type" "RR<E>")])
5731 ; abs(df|sf)2 instruction pattern(s).
5734 (define_expand "abs<mode>2"
5736 [(set (match_operand:FPR 0 "register_operand" "=f")
5737 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5738 (clobber (reg:CC 33))])]
5742 (define_insn "*abs<mode>2_cc"
5744 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5745 (match_operand:FPR 2 "const0_operand" "")))
5746 (set (match_operand:FPR 0 "register_operand" "=f")
5747 (abs:FPR (match_dup 1)))]
5748 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5750 [(set_attr "op_type" "RRE")
5751 (set_attr "type" "fsimp<mode>")])
5753 (define_insn "*abs<mode>2_cconly"
5755 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5756 (match_operand:FPR 2 "const0_operand" "")))
5757 (clobber (match_scratch:FPR 0 "=f"))]
5758 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5760 [(set_attr "op_type" "RRE")
5761 (set_attr "type" "fsimp<mode>")])
5763 (define_insn "*abs<mode>2"
5764 [(set (match_operand:FPR 0 "register_operand" "=f")
5765 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5766 (clobber (reg:CC 33))]
5767 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5769 [(set_attr "op_type" "RRE")
5770 (set_attr "type" "fsimp<mode>")])
5772 (define_insn "*abs<mode>2_ibm"
5773 [(set (match_operand:FPR 0 "register_operand" "=f")
5774 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5775 (clobber (reg:CC 33))]
5776 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5778 [(set_attr "op_type" "RR")
5779 (set_attr "type" "fsimp<mode>")])
5782 ;;- Negated absolute value instructions
5789 (define_insn "*negabsdi2_sign_cc"
5791 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5792 (match_operand:SI 1 "register_operand" "d") 0)
5793 (const_int 32)) (const_int 32))))
5795 (set (match_operand:DI 0 "register_operand" "=d")
5796 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5797 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5799 [(set_attr "op_type" "RRE")])
5801 (define_insn "*negabsdi2_sign"
5802 [(set (match_operand:DI 0 "register_operand" "=d")
5803 (neg:DI (abs:DI (sign_extend:DI
5804 (match_operand:SI 1 "register_operand" "d")))))
5805 (clobber (reg:CC 33))]
5808 [(set_attr "op_type" "RRE")])
5810 (define_insn "*negabs<mode>2_cc"
5812 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5814 (set (match_operand:GPR 0 "register_operand" "=d")
5815 (neg:GPR (abs:GPR (match_dup 1))))]
5816 "s390_match_ccmode (insn, CCAmode)"
5818 [(set_attr "op_type" "RR<E>")])
5820 (define_insn "*negabs<mode>2_cconly"
5822 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5824 (clobber (match_scratch:GPR 0 "=d"))]
5825 "s390_match_ccmode (insn, CCAmode)"
5827 [(set_attr "op_type" "RR<E>")])
5829 (define_insn "*negabs<mode>2"
5830 [(set (match_operand:GPR 0 "register_operand" "=d")
5831 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5832 (clobber (reg:CC 33))]
5835 [(set_attr "op_type" "RR<E>")])
5841 (define_insn "*negabs<mode>2_cc"
5843 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5844 (match_operand:FPR 2 "const0_operand" "")))
5845 (set (match_operand:FPR 0 "register_operand" "=f")
5846 (neg:FPR (abs:FPR (match_dup 1))))]
5847 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5849 [(set_attr "op_type" "RRE")
5850 (set_attr "type" "fsimp<mode>")])
5852 (define_insn "*negabs<mode>2_cconly"
5854 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5855 (match_operand:FPR 2 "const0_operand" "")))
5856 (clobber (match_scratch:FPR 0 "=f"))]
5857 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5859 [(set_attr "op_type" "RRE")
5860 (set_attr "type" "fsimp<mode>")])
5862 (define_insn "*negabs<mode>2"
5863 [(set (match_operand:FPR 0 "register_operand" "=f")
5864 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5865 (clobber (reg:CC 33))]
5866 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5868 [(set_attr "op_type" "RRE")
5869 (set_attr "type" "fsimp<mode>")])
5872 ;;- Square root instructions.
5876 ; sqrt(df|sf)2 instruction pattern(s).
5879 (define_insn "sqrt<mode>2"
5880 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5881 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5882 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5886 [(set_attr "op_type" "RRE,RXE")
5887 (set_attr "type" "fsqrt<mode>")])
5891 ;;- One complement instructions.
5895 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5898 (define_expand "one_cmpl<mode>2"
5900 [(set (match_operand:INT 0 "register_operand" "")
5901 (xor:INT (match_operand:INT 1 "register_operand" "")
5903 (clobber (reg:CC 33))])]
5909 ;;- Rotate instructions.
5913 ; rotl(di|si)3 instruction pattern(s).
5916 (define_insn "rotl<mode>3"
5917 [(set (match_operand:GPR 0 "register_operand" "=d")
5918 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5919 (match_operand:SI 2 "shift_count_operand" "Y")))]
5922 [(set_attr "op_type" "RSE")
5923 (set_attr "atype" "reg")])
5927 ;;- Shift instructions.
5931 ; (ashl|lshr)di3 instruction pattern(s).
5934 (define_expand "<shift>di3"
5935 [(set (match_operand:DI 0 "register_operand" "")
5936 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5937 (match_operand:SI 2 "shift_count_operand" "")))]
5941 (define_insn "*<shift>di3_31"
5942 [(set (match_operand:DI 0 "register_operand" "=d")
5943 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5944 (match_operand:SI 2 "shift_count_operand" "Y")))]
5947 [(set_attr "op_type" "RS")
5948 (set_attr "atype" "reg")])
5950 (define_insn "*<shift>di3_64"
5951 [(set (match_operand:DI 0 "register_operand" "=d")
5952 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5953 (match_operand:SI 2 "shift_count_operand" "Y")))]
5955 "s<lr>lg\t%0,%1,%Y2"
5956 [(set_attr "op_type" "RSE")
5957 (set_attr "atype" "reg")])
5960 ; ashrdi3 instruction pattern(s).
5963 (define_expand "ashrdi3"
5965 [(set (match_operand:DI 0 "register_operand" "")
5966 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5967 (match_operand:SI 2 "shift_count_operand" "")))
5968 (clobber (reg:CC 33))])]
5972 (define_insn "*ashrdi3_cc_31"
5974 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5975 (match_operand:SI 2 "shift_count_operand" "Y"))
5977 (set (match_operand:DI 0 "register_operand" "=d")
5978 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5979 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5981 [(set_attr "op_type" "RS")
5982 (set_attr "atype" "reg")])
5984 (define_insn "*ashrdi3_cconly_31"
5986 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5987 (match_operand:SI 2 "shift_count_operand" "Y"))
5989 (clobber (match_scratch:DI 0 "=d"))]
5990 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5992 [(set_attr "op_type" "RS")
5993 (set_attr "atype" "reg")])
5995 (define_insn "*ashrdi3_31"
5996 [(set (match_operand:DI 0 "register_operand" "=d")
5997 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5998 (match_operand:SI 2 "shift_count_operand" "Y")))
5999 (clobber (reg:CC 33))]
6002 [(set_attr "op_type" "RS")
6003 (set_attr "atype" "reg")])
6005 (define_insn "*ashrdi3_cc_64"
6007 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6008 (match_operand:SI 2 "shift_count_operand" "Y"))
6010 (set (match_operand:DI 0 "register_operand" "=d")
6011 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6012 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6014 [(set_attr "op_type" "RSE")
6015 (set_attr "atype" "reg")])
6017 (define_insn "*ashrdi3_cconly_64"
6019 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6020 (match_operand:SI 2 "shift_count_operand" "Y"))
6022 (clobber (match_scratch:DI 0 "=d"))]
6023 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6025 [(set_attr "op_type" "RSE")
6026 (set_attr "atype" "reg")])
6028 (define_insn "*ashrdi3_64"
6029 [(set (match_operand:DI 0 "register_operand" "=d")
6030 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6031 (match_operand:SI 2 "shift_count_operand" "Y")))
6032 (clobber (reg:CC 33))]
6035 [(set_attr "op_type" "RSE")
6036 (set_attr "atype" "reg")])
6040 ; (ashl|lshr)si3 instruction pattern(s).
6043 (define_insn "<shift>si3"
6044 [(set (match_operand:SI 0 "register_operand" "=d")
6045 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6046 (match_operand:SI 2 "shift_count_operand" "Y")))]
6049 [(set_attr "op_type" "RS")
6050 (set_attr "atype" "reg")])
6053 ; ashrsi3 instruction pattern(s).
6056 (define_insn "*ashrsi3_cc"
6058 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6059 (match_operand:SI 2 "shift_count_operand" "Y"))
6061 (set (match_operand:SI 0 "register_operand" "=d")
6062 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6063 "s390_match_ccmode(insn, CCSmode)"
6065 [(set_attr "op_type" "RS")
6066 (set_attr "atype" "reg")])
6069 (define_insn "*ashrsi3_cconly"
6071 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6072 (match_operand:SI 2 "shift_count_operand" "Y"))
6074 (clobber (match_scratch:SI 0 "=d"))]
6075 "s390_match_ccmode(insn, CCSmode)"
6077 [(set_attr "op_type" "RS")
6078 (set_attr "atype" "reg")])
6080 (define_insn "ashrsi3"
6081 [(set (match_operand:SI 0 "register_operand" "=d")
6082 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6083 (match_operand:SI 2 "shift_count_operand" "Y")))
6084 (clobber (reg:CC 33))]
6087 [(set_attr "op_type" "RS")
6088 (set_attr "atype" "reg")])
6092 ;; Branch instruction patterns.
6095 (define_expand "b<code>"
6097 (if_then_else (COMPARE (match_operand 0 "" "")
6102 "s390_emit_jump (operands[0],
6103 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6107 ;;- Conditional jump instructions.
6110 (define_insn "*cjump_64"
6113 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6114 (label_ref (match_operand 0 "" ""))
6118 if (get_attr_length (insn) == 4)
6121 return "jg%C1\t%l0";
6123 [(set_attr "op_type" "RI")
6124 (set_attr "type" "branch")
6125 (set (attr "length")
6126 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6127 (const_int 4) (const_int 6)))])
6129 (define_insn "*cjump_31"
6132 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6133 (label_ref (match_operand 0 "" ""))
6137 if (get_attr_length (insn) == 4)
6142 [(set_attr "op_type" "RI")
6143 (set_attr "type" "branch")
6144 (set (attr "length")
6145 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6146 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6147 (const_int 4) (const_int 6))
6148 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6149 (const_int 4) (const_int 8))))])
6151 (define_insn "*cjump_long"
6154 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6155 (match_operand 0 "address_operand" "U")
6159 if (get_attr_op_type (insn) == OP_TYPE_RR)
6164 [(set (attr "op_type")
6165 (if_then_else (match_operand 0 "register_operand" "")
6166 (const_string "RR") (const_string "RX")))
6167 (set_attr "type" "branch")
6168 (set_attr "atype" "agen")])
6172 ;;- Negated conditional jump instructions.
6175 (define_insn "*icjump_64"
6178 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6180 (label_ref (match_operand 0 "" ""))))]
6183 if (get_attr_length (insn) == 4)
6186 return "jg%D1\t%l0";
6188 [(set_attr "op_type" "RI")
6189 (set_attr "type" "branch")
6190 (set (attr "length")
6191 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6192 (const_int 4) (const_int 6)))])
6194 (define_insn "*icjump_31"
6197 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6199 (label_ref (match_operand 0 "" ""))))]
6202 if (get_attr_length (insn) == 4)
6207 [(set_attr "op_type" "RI")
6208 (set_attr "type" "branch")
6209 (set (attr "length")
6210 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6211 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6212 (const_int 4) (const_int 6))
6213 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6214 (const_int 4) (const_int 8))))])
6216 (define_insn "*icjump_long"
6219 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6221 (match_operand 0 "address_operand" "U")))]
6224 if (get_attr_op_type (insn) == OP_TYPE_RR)
6229 [(set (attr "op_type")
6230 (if_then_else (match_operand 0 "register_operand" "")
6231 (const_string "RR") (const_string "RX")))
6232 (set_attr "type" "branch")
6233 (set_attr "atype" "agen")])
6236 ;;- Trap instructions.
6240 [(trap_if (const_int 1) (const_int 0))]
6243 [(set_attr "op_type" "RI")
6244 (set_attr "type" "branch")])
6246 (define_expand "conditional_trap"
6247 [(trap_if (match_operand 0 "comparison_operator" "")
6248 (match_operand 1 "general_operand" ""))]
6251 if (operands[1] != const0_rtx) FAIL;
6252 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6253 s390_compare_op0, s390_compare_op1);
6256 (define_insn "*trap"
6257 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
6261 [(set_attr "op_type" "RI")
6262 (set_attr "type" "branch")])
6265 ;;- Loop instructions.
6267 ;; This is all complicated by the fact that since this is a jump insn
6268 ;; we must handle our own output reloads.
6270 (define_expand "doloop_end"
6271 [(use (match_operand 0 "" "")) ; loop pseudo
6272 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6273 (use (match_operand 2 "" "")) ; max iterations
6274 (use (match_operand 3 "" "")) ; loop level
6275 (use (match_operand 4 "" ""))] ; label
6278 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6279 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6280 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6281 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6282 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6283 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6290 (define_insn_and_split "doloop_si64"
6293 (ne (match_operand:SI 1 "register_operand" "d,d")
6295 (label_ref (match_operand 0 "" ""))
6297 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6298 (plus:SI (match_dup 1) (const_int -1)))
6299 (clobber (match_scratch:SI 3 "=X,&1"))
6300 (clobber (reg:CC 33))]
6303 if (which_alternative != 0)
6305 else if (get_attr_length (insn) == 4)
6306 return "brct\t%1,%l0";
6308 return "ahi\t%1,-1\;jgne\t%l0";
6310 "&& reload_completed
6311 && (! REG_P (operands[2])
6312 || ! rtx_equal_p (operands[1], operands[2]))"
6313 [(parallel [(set (reg:CCAN 33)
6314 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6316 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6317 (set (match_dup 2) (match_dup 3))
6318 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6319 (label_ref (match_dup 0))
6322 [(set_attr "op_type" "RI")
6323 (set_attr "type" "branch")
6324 (set (attr "length")
6325 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6326 (const_int 4) (const_int 10)))])
6328 (define_insn_and_split "doloop_si31"
6331 (ne (match_operand:SI 1 "register_operand" "d,d")
6333 (label_ref (match_operand 0 "" ""))
6335 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6336 (plus:SI (match_dup 1) (const_int -1)))
6337 (clobber (match_scratch:SI 3 "=X,&1"))
6338 (clobber (reg:CC 33))]
6341 if (which_alternative != 0)
6343 else if (get_attr_length (insn) == 4)
6344 return "brct\t%1,%l0";
6348 "&& reload_completed
6349 && (! REG_P (operands[2])
6350 || ! rtx_equal_p (operands[1], operands[2]))"
6351 [(parallel [(set (reg:CCAN 33)
6352 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6354 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6355 (set (match_dup 2) (match_dup 3))
6356 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6357 (label_ref (match_dup 0))
6360 [(set_attr "op_type" "RI")
6361 (set_attr "type" "branch")
6362 (set (attr "length")
6363 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6364 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6365 (const_int 4) (const_int 6))
6366 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6367 (const_int 4) (const_int 8))))])
6369 (define_insn "*doloop_si_long"
6372 (ne (match_operand:SI 1 "register_operand" "d,d")
6374 (match_operand 0 "address_operand" "U,U")
6376 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6377 (plus:SI (match_dup 1) (const_int -1)))
6378 (clobber (match_scratch:SI 3 "=X,&1"))
6379 (clobber (reg:CC 33))]
6382 if (get_attr_op_type (insn) == OP_TYPE_RR)
6383 return "bctr\t%1,%0";
6385 return "bct\t%1,%a0";
6387 [(set (attr "op_type")
6388 (if_then_else (match_operand 0 "register_operand" "")
6389 (const_string "RR") (const_string "RX")))
6390 (set_attr "type" "branch")
6391 (set_attr "atype" "agen")])
6393 (define_insn_and_split "doloop_di"
6396 (ne (match_operand:DI 1 "register_operand" "d,d")
6398 (label_ref (match_operand 0 "" ""))
6400 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6401 (plus:DI (match_dup 1) (const_int -1)))
6402 (clobber (match_scratch:DI 3 "=X,&1"))
6403 (clobber (reg:CC 33))]
6406 if (which_alternative != 0)
6408 else if (get_attr_length (insn) == 4)
6409 return "brctg\t%1,%l0";
6411 return "aghi\t%1,-1\;jgne\t%l0";
6413 "&& reload_completed
6414 && (! REG_P (operands[2])
6415 || ! rtx_equal_p (operands[1], operands[2]))"
6416 [(parallel [(set (reg:CCAN 33)
6417 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6419 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6420 (set (match_dup 2) (match_dup 3))
6421 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6422 (label_ref (match_dup 0))
6425 [(set_attr "op_type" "RI")
6426 (set_attr "type" "branch")
6427 (set (attr "length")
6428 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6429 (const_int 4) (const_int 10)))])
6432 ;;- Unconditional jump instructions.
6436 ; jump instruction pattern(s).
6439 (define_expand "jump"
6440 [(match_operand 0 "" "")]
6442 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6444 (define_insn "*jump64"
6445 [(set (pc) (label_ref (match_operand 0 "" "")))]
6448 if (get_attr_length (insn) == 4)
6453 [(set_attr "op_type" "RI")
6454 (set_attr "type" "branch")
6455 (set (attr "length")
6456 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6457 (const_int 4) (const_int 6)))])
6459 (define_insn "*jump31"
6460 [(set (pc) (label_ref (match_operand 0 "" "")))]
6463 if (get_attr_length (insn) == 4)
6468 [(set_attr "op_type" "RI")
6469 (set_attr "type" "branch")
6470 (set (attr "length")
6471 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6472 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6473 (const_int 4) (const_int 6))
6474 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6475 (const_int 4) (const_int 8))))])
6478 ; indirect-jump instruction pattern(s).
6481 (define_insn "indirect_jump"
6482 [(set (pc) (match_operand 0 "address_operand" "U"))]
6485 if (get_attr_op_type (insn) == OP_TYPE_RR)
6490 [(set (attr "op_type")
6491 (if_then_else (match_operand 0 "register_operand" "")
6492 (const_string "RR") (const_string "RX")))
6493 (set_attr "type" "branch")
6494 (set_attr "atype" "agen")])
6497 ; casesi instruction pattern(s).
6500 (define_insn "casesi_jump"
6501 [(set (pc) (match_operand 0 "address_operand" "U"))
6502 (use (label_ref (match_operand 1 "" "")))]
6505 if (get_attr_op_type (insn) == OP_TYPE_RR)
6510 [(set (attr "op_type")
6511 (if_then_else (match_operand 0 "register_operand" "")
6512 (const_string "RR") (const_string "RX")))
6513 (set_attr "type" "branch")
6514 (set_attr "atype" "agen")])
6516 (define_expand "casesi"
6517 [(match_operand:SI 0 "general_operand" "")
6518 (match_operand:SI 1 "general_operand" "")
6519 (match_operand:SI 2 "general_operand" "")
6520 (label_ref (match_operand 3 "" ""))
6521 (label_ref (match_operand 4 "" ""))]
6524 rtx index = gen_reg_rtx (SImode);
6525 rtx base = gen_reg_rtx (Pmode);
6526 rtx target = gen_reg_rtx (Pmode);
6528 emit_move_insn (index, operands[0]);
6529 emit_insn (gen_subsi3 (index, index, operands[1]));
6530 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6533 if (Pmode != SImode)
6534 index = convert_to_mode (Pmode, index, 1);
6535 if (GET_CODE (index) != REG)
6536 index = copy_to_mode_reg (Pmode, index);
6539 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6541 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6543 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6545 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6546 emit_move_insn (target, index);
6549 target = gen_rtx_PLUS (Pmode, base, target);
6550 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6557 ;;- Jump to subroutine.
6562 ; untyped call instruction pattern(s).
6565 ;; Call subroutine returning any type.
6566 (define_expand "untyped_call"
6567 [(parallel [(call (match_operand 0 "" "")
6569 (match_operand 1 "" "")
6570 (match_operand 2 "" "")])]
6575 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6577 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6579 rtx set = XVECEXP (operands[2], 0, i);
6580 emit_move_insn (SET_DEST (set), SET_SRC (set));
6583 /* The optimizer does not know that the call sets the function value
6584 registers we stored in the result block. We avoid problems by
6585 claiming that all hard registers are used and clobbered at this
6587 emit_insn (gen_blockage ());
6592 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6593 ;; all of memory. This blocks insns from being moved across this point.
6595 (define_insn "blockage"
6596 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6599 [(set_attr "type" "none")
6600 (set_attr "length" "0")])
6606 (define_expand "sibcall"
6607 [(call (match_operand 0 "" "")
6608 (match_operand 1 "" ""))]
6611 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6615 (define_insn "*sibcall_br"
6616 [(call (mem:QI (reg 1))
6617 (match_operand 0 "const_int_operand" "n"))]
6618 "SIBLING_CALL_P (insn)
6619 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6621 [(set_attr "op_type" "RR")
6622 (set_attr "type" "branch")
6623 (set_attr "atype" "agen")])
6625 (define_insn "*sibcall_brc"
6626 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6627 (match_operand 1 "const_int_operand" "n"))]
6628 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6630 [(set_attr "op_type" "RI")
6631 (set_attr "type" "branch")])
6633 (define_insn "*sibcall_brcl"
6634 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6635 (match_operand 1 "const_int_operand" "n"))]
6636 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6638 [(set_attr "op_type" "RIL")
6639 (set_attr "type" "branch")])
6642 ; sibcall_value patterns
6645 (define_expand "sibcall_value"
6646 [(set (match_operand 0 "" "")
6647 (call (match_operand 1 "" "")
6648 (match_operand 2 "" "")))]
6651 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6655 (define_insn "*sibcall_value_br"
6656 [(set (match_operand 0 "" "")
6657 (call (mem:QI (reg 1))
6658 (match_operand 1 "const_int_operand" "n")))]
6659 "SIBLING_CALL_P (insn)
6660 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6662 [(set_attr "op_type" "RR")
6663 (set_attr "type" "branch")
6664 (set_attr "atype" "agen")])
6666 (define_insn "*sibcall_value_brc"
6667 [(set (match_operand 0 "" "")
6668 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6669 (match_operand 2 "const_int_operand" "n")))]
6670 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6672 [(set_attr "op_type" "RI")
6673 (set_attr "type" "branch")])
6675 (define_insn "*sibcall_value_brcl"
6676 [(set (match_operand 0 "" "")
6677 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6678 (match_operand 2 "const_int_operand" "n")))]
6679 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6681 [(set_attr "op_type" "RIL")
6682 (set_attr "type" "branch")])
6686 ; call instruction pattern(s).
6689 (define_expand "call"
6690 [(call (match_operand 0 "" "")
6691 (match_operand 1 "" ""))
6692 (use (match_operand 2 "" ""))]
6695 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6696 gen_rtx_REG (Pmode, RETURN_REGNUM));
6700 (define_insn "*bras"
6701 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6702 (match_operand 1 "const_int_operand" "n"))
6703 (clobber (match_operand 2 "register_operand" "=r"))]
6704 "!SIBLING_CALL_P (insn)
6705 && TARGET_SMALL_EXEC
6706 && GET_MODE (operands[2]) == Pmode"
6708 [(set_attr "op_type" "RI")
6709 (set_attr "type" "jsr")])
6711 (define_insn "*brasl"
6712 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6713 (match_operand 1 "const_int_operand" "n"))
6714 (clobber (match_operand 2 "register_operand" "=r"))]
6715 "!SIBLING_CALL_P (insn)
6717 && GET_MODE (operands[2]) == Pmode"
6719 [(set_attr "op_type" "RIL")
6720 (set_attr "type" "jsr")])
6722 (define_insn "*basr"
6723 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6724 (match_operand 1 "const_int_operand" "n"))
6725 (clobber (match_operand 2 "register_operand" "=r"))]
6726 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6728 if (get_attr_op_type (insn) == OP_TYPE_RR)
6729 return "basr\t%2,%0";
6731 return "bas\t%2,%a0";
6733 [(set (attr "op_type")
6734 (if_then_else (match_operand 0 "register_operand" "")
6735 (const_string "RR") (const_string "RX")))
6736 (set_attr "type" "jsr")
6737 (set_attr "atype" "agen")])
6740 ; call_value instruction pattern(s).
6743 (define_expand "call_value"
6744 [(set (match_operand 0 "" "")
6745 (call (match_operand 1 "" "")
6746 (match_operand 2 "" "")))
6747 (use (match_operand 3 "" ""))]
6750 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6751 gen_rtx_REG (Pmode, RETURN_REGNUM));
6755 (define_insn "*bras_r"
6756 [(set (match_operand 0 "" "")
6757 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6758 (match_operand:SI 2 "const_int_operand" "n")))
6759 (clobber (match_operand 3 "register_operand" "=r"))]
6760 "!SIBLING_CALL_P (insn)
6761 && TARGET_SMALL_EXEC
6762 && GET_MODE (operands[3]) == Pmode"
6764 [(set_attr "op_type" "RI")
6765 (set_attr "type" "jsr")])
6767 (define_insn "*brasl_r"
6768 [(set (match_operand 0 "" "")
6769 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6770 (match_operand 2 "const_int_operand" "n")))
6771 (clobber (match_operand 3 "register_operand" "=r"))]
6772 "!SIBLING_CALL_P (insn)
6774 && GET_MODE (operands[3]) == Pmode"
6776 [(set_attr "op_type" "RIL")
6777 (set_attr "type" "jsr")])
6779 (define_insn "*basr_r"
6780 [(set (match_operand 0 "" "")
6781 (call (mem:QI (match_operand 1 "address_operand" "U"))
6782 (match_operand 2 "const_int_operand" "n")))
6783 (clobber (match_operand 3 "register_operand" "=r"))]
6784 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6786 if (get_attr_op_type (insn) == OP_TYPE_RR)
6787 return "basr\t%3,%1";
6789 return "bas\t%3,%a1";
6791 [(set (attr "op_type")
6792 (if_then_else (match_operand 1 "register_operand" "")
6793 (const_string "RR") (const_string "RX")))
6794 (set_attr "type" "jsr")
6795 (set_attr "atype" "agen")])
6798 ;;- Thread-local storage support.
6801 (define_expand "get_tp_64"
6802 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
6806 (define_expand "get_tp_31"
6807 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
6811 (define_expand "set_tp_64"
6812 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
6813 (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))]
6817 (define_expand "set_tp_31"
6818 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
6819 (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))]
6823 (define_insn "*set_tp"
6824 [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))]
6827 [(set_attr "type" "none")
6828 (set_attr "length" "0")])
6830 (define_insn "*tls_load_64"
6831 [(set (match_operand:DI 0 "register_operand" "=d")
6832 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6833 (match_operand:DI 2 "" "")]
6837 [(set_attr "op_type" "RXE")])
6839 (define_insn "*tls_load_31"
6840 [(set (match_operand:SI 0 "register_operand" "=d,d")
6841 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6842 (match_operand:SI 2 "" "")]
6848 [(set_attr "op_type" "RX,RXY")])
6850 (define_insn "*bras_tls"
6851 [(set (match_operand 0 "" "")
6852 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6853 (match_operand 2 "const_int_operand" "n")))
6854 (clobber (match_operand 3 "register_operand" "=r"))
6855 (use (match_operand 4 "" ""))]
6856 "!SIBLING_CALL_P (insn)
6857 && TARGET_SMALL_EXEC
6858 && GET_MODE (operands[3]) == Pmode"
6860 [(set_attr "op_type" "RI")
6861 (set_attr "type" "jsr")])
6863 (define_insn "*brasl_tls"
6864 [(set (match_operand 0 "" "")
6865 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6866 (match_operand 2 "const_int_operand" "n")))
6867 (clobber (match_operand 3 "register_operand" "=r"))
6868 (use (match_operand 4 "" ""))]
6869 "!SIBLING_CALL_P (insn)
6871 && GET_MODE (operands[3]) == Pmode"
6873 [(set_attr "op_type" "RIL")
6874 (set_attr "type" "jsr")])
6876 (define_insn "*basr_tls"
6877 [(set (match_operand 0 "" "")
6878 (call (mem:QI (match_operand 1 "address_operand" "U"))
6879 (match_operand 2 "const_int_operand" "n")))
6880 (clobber (match_operand 3 "register_operand" "=r"))
6881 (use (match_operand 4 "" ""))]
6882 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6884 if (get_attr_op_type (insn) == OP_TYPE_RR)
6885 return "basr\t%3,%1%J4";
6887 return "bas\t%3,%a1%J4";
6889 [(set (attr "op_type")
6890 (if_then_else (match_operand 1 "register_operand" "")
6891 (const_string "RR") (const_string "RX")))
6892 (set_attr "type" "jsr")
6893 (set_attr "atype" "agen")])
6896 ;;- Miscellaneous instructions.
6900 ; allocate stack instruction pattern(s).
6903 (define_expand "allocate_stack"
6904 [(match_operand 0 "general_operand" "")
6905 (match_operand 1 "general_operand" "")]
6908 rtx temp = gen_reg_rtx (Pmode);
6910 emit_move_insn (temp, s390_back_chain_rtx ());
6911 anti_adjust_stack (operands[1]);
6912 emit_move_insn (s390_back_chain_rtx (), temp);
6914 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6920 ; setjmp instruction pattern.
6923 (define_expand "builtin_setjmp_receiver"
6924 [(match_operand 0 "" "")]
6927 emit_insn (s390_load_got ());
6928 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6932 ;; These patterns say how to save and restore the stack pointer. We need not
6933 ;; save the stack pointer at function level since we are careful to
6934 ;; preserve the backchain. At block level, we have to restore the backchain
6935 ;; when we restore the stack pointer.
6937 ;; For nonlocal gotos, we must save both the stack pointer and its
6938 ;; backchain and restore both. Note that in the nonlocal case, the
6939 ;; save area is a memory location.
6941 (define_expand "save_stack_function"
6942 [(match_operand 0 "general_operand" "")
6943 (match_operand 1 "general_operand" "")]
6947 (define_expand "restore_stack_function"
6948 [(match_operand 0 "general_operand" "")
6949 (match_operand 1 "general_operand" "")]
6953 (define_expand "restore_stack_block"
6954 [(match_operand 0 "register_operand" "")
6955 (match_operand 1 "register_operand" "")]
6958 rtx temp = gen_reg_rtx (Pmode);
6960 emit_move_insn (temp, s390_back_chain_rtx ());
6961 emit_move_insn (operands[0], operands[1]);
6962 emit_move_insn (s390_back_chain_rtx (), temp);
6967 (define_expand "save_stack_nonlocal"
6968 [(match_operand 0 "memory_operand" "")
6969 (match_operand 1 "register_operand" "")]
6972 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6973 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6975 /* Copy the backchain to the first word, sp to the second and the
6976 literal pool base to the third. */
6978 if (TARGET_BACKCHAIN)
6980 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6981 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6984 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6985 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6990 (define_expand "restore_stack_nonlocal"
6991 [(match_operand 0 "register_operand" "")
6992 (match_operand 1 "memory_operand" "")]
6995 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6996 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6997 rtx temp = NULL_RTX;
6999 /* Restore the backchain from the first word, sp from the second and the
7000 literal pool base from the third. */
7002 if (TARGET_BACKCHAIN)
7003 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7005 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7006 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7009 emit_move_insn (s390_back_chain_rtx (), temp);
7011 emit_insn (gen_rtx_USE (VOIDmode, base));
7017 ; nop instruction pattern(s).
7024 [(set_attr "op_type" "RR")])
7028 ; Special literal pool access instruction pattern(s).
7031 (define_insn "*pool_entry"
7032 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7033 UNSPECV_POOL_ENTRY)]
7036 enum machine_mode mode = GET_MODE (PATTERN (insn));
7037 unsigned int align = GET_MODE_BITSIZE (mode);
7038 s390_output_pool_entry (operands[0], mode, align);
7041 [(set (attr "length")
7042 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7044 (define_insn "pool_align"
7045 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7046 UNSPECV_POOL_ALIGN)]
7049 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7051 (define_insn "pool_section_start"
7052 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7055 [(set_attr "length" "0")])
7057 (define_insn "pool_section_end"
7058 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7061 [(set_attr "length" "0")])
7063 (define_insn "main_base_31_small"
7064 [(set (match_operand 0 "register_operand" "=a")
7065 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7066 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7068 [(set_attr "op_type" "RR")
7069 (set_attr "type" "la")])
7071 (define_insn "main_base_31_large"
7072 [(set (match_operand 0 "register_operand" "=a")
7073 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7074 (set (pc) (label_ref (match_operand 2 "" "")))]
7075 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7077 [(set_attr "op_type" "RI")])
7079 (define_insn "main_base_64"
7080 [(set (match_operand 0 "register_operand" "=a")
7081 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7082 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7084 [(set_attr "op_type" "RIL")
7085 (set_attr "type" "larl")])
7087 (define_insn "main_pool"
7088 [(set (match_operand 0 "register_operand" "=a")
7089 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7090 "GET_MODE (operands[0]) == Pmode"
7093 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7094 (const_string "larl") (const_string "la")))])
7096 (define_insn "reload_base_31"
7097 [(set (match_operand 0 "register_operand" "=a")
7098 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7099 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7100 "basr\t%0,0\;la\t%0,%1-.(%0)"
7101 [(set_attr "length" "6")
7102 (set_attr "type" "la")])
7104 (define_insn "reload_base_64"
7105 [(set (match_operand 0 "register_operand" "=a")
7106 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7107 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7109 [(set_attr "op_type" "RIL")
7110 (set_attr "type" "larl")])
7113 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7116 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7119 ;; Insns related to generating the function prologue and epilogue.
7123 (define_expand "prologue"
7124 [(use (const_int 0))]
7126 "s390_emit_prologue (); DONE;")
7128 (define_insn "prologue_tpf"
7129 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
7130 (clobber (reg:DI 1))]
7131 "TARGET_TPF_PROFILING"
7132 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
7133 [(set_attr "length" "14")])
7135 (define_expand "epilogue"
7136 [(use (const_int 1))]
7138 "s390_emit_epilogue (false); DONE;")
7140 (define_insn "epilogue_tpf"
7141 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
7142 (clobber (reg:DI 1))]
7143 "TARGET_TPF_PROFILING"
7144 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
7145 [(set_attr "length" "14")])
7147 (define_expand "sibcall_epilogue"
7148 [(use (const_int 0))]
7150 "s390_emit_epilogue (true); DONE;")
7152 (define_insn "*return"
7154 (use (match_operand 0 "register_operand" "a"))]
7155 "GET_MODE (operands[0]) == Pmode"
7157 [(set_attr "op_type" "RR")
7158 (set_attr "type" "jsr")
7159 (set_attr "atype" "agen")])
7162 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7163 ;; pointer. This is used for compatibility.
7165 (define_expand "ptr_extend"
7166 [(set (match_operand:DI 0 "register_operand" "=r")
7167 (match_operand:SI 1 "register_operand" "r"))]
7170 emit_insn (gen_anddi3 (operands[0],
7171 gen_lowpart (DImode, operands[1]),
7172 GEN_INT (0x7fffffff)));
7176 ;; Instruction definition to expand eh_return macro to support
7177 ;; swapping in special linkage return addresses.
7179 (define_expand "eh_return"
7180 [(use (match_operand 0 "register_operand" ""))]
7183 s390_emit_tpf_eh_return (operands[0]);