| blob | a8b27bcf986868fdac1b825907f8c5384e7c1c79 |
1 ;; ARM VFP instruction patterns
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; SImode moves
22 ;; ??? For now do not allow loading constants into vfp regs. This causes
23 ;; problems because small constants get converted into adds.
24 (define_insn "*arm_movsi_vfp"
25 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
26 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
27 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
28 && ( s_register_operand (operands[0], SImode)
29 || s_register_operand (operands[1], SImode))"
30 "*
31 switch (which_alternative)
32 {
33 case 0: case 1:
34 return \"mov%?\\t%0, %1\";
35 case 2:
36 return \"mvn%?\\t%0, #%B1\";
37 case 3:
38 return \"movw%?\\t%0, %1\";
39 case 4:
40 return \"ldr%?\\t%0, %1\";
41 case 5:
42 return \"str%?\\t%1, %0\";
43 case 6:
44 return \"fmsr%?\\t%0, %1\\t%@ int\";
45 case 7:
46 return \"fmrs%?\\t%0, %1\\t%@ int\";
47 case 8:
48 return \"fcpys%?\\t%0, %1\\t%@ int\";
49 case 9: case 10:
50 return output_move_vfp (operands);
51 default:
52 gcc_unreachable ();
53 }
54 "
55 [(set_attr "predicable" "yes")
56 (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
57 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
58 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
59 )
61 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
62 ;; high/low register alternatives for loads and stores here.
63 ;; The l/Py alternative should come after r/I to ensure that the short variant
64 ;; is chosen with length 2 when the instruction is predicated for
65 ;; arm_restrict_it.
66 (define_insn "*thumb2_movsi_vfp"
67 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv")
68 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
69 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
70 && ( s_register_operand (operands[0], SImode)
71 || s_register_operand (operands[1], SImode))"
72 "*
73 switch (which_alternative)
74 {
75 case 0:
76 case 1:
77 case 2:
78 return \"mov%?\\t%0, %1\";
79 case 3:
80 return \"mvn%?\\t%0, #%B1\";
81 case 4:
82 return \"movw%?\\t%0, %1\";
83 case 5:
84 case 6:
85 return \"ldr%?\\t%0, %1\";
86 case 7:
87 case 8:
88 return \"str%?\\t%1, %0\";
89 case 9:
90 return \"fmsr%?\\t%0, %1\\t%@ int\";
91 case 10:
92 return \"fmrs%?\\t%0, %1\\t%@ int\";
93 case 11:
94 return \"fcpys%?\\t%0, %1\\t%@ int\";
95 case 12: case 13:
96 return output_move_vfp (operands);
97 default:
98 gcc_unreachable ();
99 }
100 "
101 [(set_attr "predicable" "yes")
102 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
103 (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
104 (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
105 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
106 (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
107 )
110 ;; DImode moves
112 (define_insn "*movdi_vfp"
113 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
114 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
115 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
116 && ( register_operand (operands[0], DImode)
117 || register_operand (operands[1], DImode))
118 && !(TARGET_NEON && CONST_INT_P (operands[1])
119 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
120 "*
121 switch (which_alternative)
122 {
123 case 0:
124 case 1:
125 case 2:
126 case 3:
127 return \"#\";
128 case 4:
129 case 5:
130 case 6:
131 return output_move_double (operands, true, NULL);
132 case 7:
133 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
134 case 8:
135 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
136 case 9:
137 if (TARGET_VFP_SINGLE)
138 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
139 else
140 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
141 case 10: case 11:
142 return output_move_vfp (operands);
143 default:
144 gcc_unreachable ();
145 }
146 "
147 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
148 (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
149 (eq_attr "alternative" "2") (const_int 12)
150 (eq_attr "alternative" "3") (const_int 16)
151 (eq_attr "alternative" "9")
152 (if_then_else
153 (match_test "TARGET_VFP_SINGLE")
154 (const_int 8)
155 (const_int 4))]
156 (const_int 4)))
157 (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*")
158 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
159 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
160 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
161 )
163 (define_insn "*movdi_vfp_cortexa8"
164 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
165 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
166 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
167 && ( register_operand (operands[0], DImode)
168 || register_operand (operands[1], DImode))
169 && !(TARGET_NEON && CONST_INT_P (operands[1])
170 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
171 "*
172 switch (which_alternative)
173 {
174 case 0:
175 case 1:
176 case 2:
177 case 3:
178 return \"#\";
179 case 4:
180 case 5:
181 case 6:
182 return output_move_double (operands, true, NULL);
183 case 7:
184 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
185 case 8:
186 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
187 case 9:
188 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
189 case 10: case 11:
190 return output_move_vfp (operands);
191 default:
192 gcc_unreachable ();
193 }
194 "
195 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
196 (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
197 (eq_attr "alternative" "2") (const_int 12)
198 (eq_attr "alternative" "3") (const_int 16)
199 (eq_attr "alternative" "4,5,6")
200 (symbol_ref
201 "arm_count_output_move_double_insns (operands) \
202 * 4")]
203 (const_int 4)))
204 (set_attr "predicable" "yes")
205 (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
206 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
207 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
208 (set (attr "ce_count")
209 (symbol_ref "get_attr_length (insn) / 4"))
210 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
211 )
213 ;; HFmode moves
214 (define_insn "*movhf_vfp_neon"
215 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
216 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
217 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
218 && ( s_register_operand (operands[0], HFmode)
219 || s_register_operand (operands[1], HFmode))"
220 "*
221 switch (which_alternative)
222 {
223 case 0: /* S register from memory */
224 return \"vld1.16\\t{%z0}, %A1\";
225 case 1: /* memory from S register */
226 return \"vst1.16\\t{%z1}, %A0\";
227 case 2: /* ARM register from memory */
228 return \"ldrh\\t%0, %1\\t%@ __fp16\";
229 case 3: /* memory from ARM register */
230 return \"strh\\t%1, %0\\t%@ __fp16\";
231 case 4: /* S register from S register */
232 return \"fcpys\\t%0, %1\";
233 case 5: /* ARM register from ARM register */
234 return \"mov\\t%0, %1\\t%@ __fp16\";
235 case 6: /* S register from ARM register */
236 return \"fmsr\\t%0, %1\";
237 case 7: /* ARM register from S register */
238 return \"fmrs\\t%0, %1\";
239 case 8: /* ARM register from constant */
240 {
241 REAL_VALUE_TYPE r;
242 long bits;
243 rtx ops[4];
245 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
246 bits = real_to_target (NULL, &r, HFmode);
247 ops[0] = operands[0];
248 ops[1] = GEN_INT (bits);
249 ops[2] = GEN_INT (bits & 0xff00);
250 ops[3] = GEN_INT (bits & 0x00ff);
252 if (arm_arch_thumb2)
253 output_asm_insn (\"movw\\t%0, %1\", ops);
254 else
255 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
256 return \"\";
257 }
258 default:
259 gcc_unreachable ();
260 }
261 "
262 [(set_attr "conds" "unconditional")
263 (set_attr "type" "neon_load1_1reg,neon_store1_1reg,\
264 load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
265 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
266 )
268 ;; FP16 without element load/store instructions.
269 (define_insn "*movhf_vfp"
270 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
271 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
272 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
273 && ( s_register_operand (operands[0], HFmode)
274 || s_register_operand (operands[1], HFmode))"
275 "*
276 switch (which_alternative)
277 {
278 case 0: /* ARM register from memory */
279 return \"ldrh\\t%0, %1\\t%@ __fp16\";
280 case 1: /* memory from ARM register */
281 return \"strh\\t%1, %0\\t%@ __fp16\";
282 case 2: /* S register from S register */
283 return \"fcpys\\t%0, %1\";
284 case 3: /* ARM register from ARM register */
285 return \"mov\\t%0, %1\\t%@ __fp16\";
286 case 4: /* S register from ARM register */
287 return \"fmsr\\t%0, %1\";
288 case 5: /* ARM register from S register */
289 return \"fmrs\\t%0, %1\";
290 case 6: /* ARM register from constant */
291 {
292 REAL_VALUE_TYPE r;
293 long bits;
294 rtx ops[4];
296 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
297 bits = real_to_target (NULL, &r, HFmode);
298 ops[0] = operands[0];
299 ops[1] = GEN_INT (bits);
300 ops[2] = GEN_INT (bits & 0xff00);
301 ops[3] = GEN_INT (bits & 0x00ff);
303 if (arm_arch_thumb2)
304 output_asm_insn (\"movw\\t%0, %1\", ops);
305 else
306 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
307 return \"\";
308 }
309 default:
310 gcc_unreachable ();
311 }
312 "
313 [(set_attr "conds" "unconditional")
314 (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
315 (set_attr "length" "4,4,4,4,4,4,8")]
316 )
319 ;; SFmode moves
320 ;; Disparage the w<->r cases because reloading an invalid address is
321 ;; preferable to loading the value via integer registers.
323 (define_insn "*movsf_vfp"
324 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
325 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
326 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
327 && ( s_register_operand (operands[0], SFmode)
328 || s_register_operand (operands[1], SFmode))"
329 "*
330 switch (which_alternative)
331 {
332 case 0:
333 return \"fmsr%?\\t%0, %1\";
334 case 1:
335 return \"fmrs%?\\t%0, %1\";
336 case 2:
337 return \"fconsts%?\\t%0, #%G1\";
338 case 3: case 4:
339 return output_move_vfp (operands);
340 case 5:
341 return \"ldr%?\\t%0, %1\\t%@ float\";
342 case 6:
343 return \"str%?\\t%1, %0\\t%@ float\";
344 case 7:
345 return \"fcpys%?\\t%0, %1\";
346 case 8:
347 return \"mov%?\\t%0, %1\\t%@ float\";
348 default:
349 gcc_unreachable ();
350 }
351 "
352 [(set_attr "predicable" "yes")
353 (set_attr "type"
354 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
355 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
356 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
357 )
359 (define_insn "*thumb2_movsf_vfp"
360 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
361 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
362 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
363 && ( s_register_operand (operands[0], SFmode)
364 || s_register_operand (operands[1], SFmode))"
365 "*
366 switch (which_alternative)
367 {
368 case 0:
369 return \"fmsr%?\\t%0, %1\";
370 case 1:
371 return \"fmrs%?\\t%0, %1\";
372 case 2:
373 return \"fconsts%?\\t%0, #%G1\";
374 case 3: case 4:
375 return output_move_vfp (operands);
376 case 5:
377 return \"ldr%?\\t%0, %1\\t%@ float\";
378 case 6:
379 return \"str%?\\t%1, %0\\t%@ float\";
380 case 7:
381 return \"fcpys%?\\t%0, %1\";
382 case 8:
383 return \"mov%?\\t%0, %1\\t%@ float\";
384 default:
385 gcc_unreachable ();
386 }
387 "
388 [(set_attr "predicable" "yes")
389 (set_attr "predicable_short_it" "no")
390 (set_attr "type"
391 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
392 (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
393 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
394 )
396 ;; DFmode moves
398 (define_insn "*movdf_vfp"
399 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
400 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
401 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
402 && ( register_operand (operands[0], DFmode)
403 || register_operand (operands[1], DFmode))"
404 "*
405 {
406 switch (which_alternative)
407 {
408 case 0:
409 return \"fmdrr%?\\t%P0, %Q1, %R1\";
410 case 1:
411 return \"fmrrd%?\\t%Q0, %R0, %P1\";
412 case 2:
413 gcc_assert (TARGET_VFP_DOUBLE);
414 return \"fconstd%?\\t%P0, #%G1\";
415 case 3: case 4:
416 return output_move_vfp (operands);
417 case 5: case 6:
418 return output_move_double (operands, true, NULL);
419 case 7:
420 if (TARGET_VFP_SINGLE)
421 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
422 else
423 return \"fcpyd%?\\t%P0, %P1\";
424 case 8:
425 return \"#\";
426 default:
427 gcc_unreachable ();
428 }
429 }
430 "
431 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
432 load2,store2,ffarithd,multiple")
433 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
434 (eq_attr "alternative" "7")
435 (if_then_else
436 (match_test "TARGET_VFP_SINGLE")
437 (const_int 8)
438 (const_int 4))]
439 (const_int 4)))
440 (set_attr "predicable" "yes")
441 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
442 (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
443 )
445 (define_insn "*thumb2_movdf_vfp"
446 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
447 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
448 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
449 && ( register_operand (operands[0], DFmode)
450 || register_operand (operands[1], DFmode))"
451 "*
452 {
453 switch (which_alternative)
454 {
455 case 0:
456 return \"fmdrr%?\\t%P0, %Q1, %R1\";
457 case 1:
458 return \"fmrrd%?\\t%Q0, %R0, %P1\";
459 case 2:
460 gcc_assert (TARGET_VFP_DOUBLE);
461 return \"fconstd%?\\t%P0, #%G1\";
462 case 3: case 4:
463 return output_move_vfp (operands);
464 case 5: case 6: case 8:
465 return output_move_double (operands, true, NULL);
466 case 7:
467 if (TARGET_VFP_SINGLE)
468 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
469 else
470 return \"fcpyd%?\\t%P0, %P1\";
471 default:
472 abort ();
473 }
474 }
475 "
476 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
477 f_stored,load2,store2,ffarithd,multiple")
478 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
479 (eq_attr "alternative" "7")
480 (if_then_else
481 (match_test "TARGET_VFP_SINGLE")
482 (const_int 8)
483 (const_int 4))]
484 (const_int 4)))
485 (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
486 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
487 )
490 ;; Conditional move patterns
492 (define_insn "*movsfcc_vfp"
493 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
494 (if_then_else:SF
495 (match_operator 3 "arm_comparison_operator"
496 [(match_operand 4 "cc_register" "") (const_int 0)])
497 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
498 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
499 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
500 "@
501 fcpys%D3\\t%0, %2
502 fcpys%d3\\t%0, %1
503 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
504 fmsr%D3\\t%0, %2
505 fmsr%d3\\t%0, %1
506 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
507 fmrs%D3\\t%0, %2
508 fmrs%d3\\t%0, %1
509 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
510 [(set_attr "conds" "use")
511 (set_attr "length" "4,4,8,4,4,8,4,4,8")
512 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
513 )
515 (define_insn "*thumb2_movsfcc_vfp"
516 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
517 (if_then_else:SF
518 (match_operator 3 "arm_comparison_operator"
519 [(match_operand 4 "cc_register" "") (const_int 0)])
520 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
521 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
522 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
523 "@
524 it\\t%D3\;fcpys%D3\\t%0, %2
525 it\\t%d3\;fcpys%d3\\t%0, %1
526 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
527 it\\t%D3\;fmsr%D3\\t%0, %2
528 it\\t%d3\;fmsr%d3\\t%0, %1
529 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
530 it\\t%D3\;fmrs%D3\\t%0, %2
531 it\\t%d3\;fmrs%d3\\t%0, %1
532 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
533 [(set_attr "conds" "use")
534 (set_attr "length" "6,6,10,6,6,10,6,6,10")
535 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
536 )
538 (define_insn "*movdfcc_vfp"
539 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
540 (if_then_else:DF
541 (match_operator 3 "arm_comparison_operator"
542 [(match_operand 4 "cc_register" "") (const_int 0)])
543 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
544 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
545 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
546 "@
547 fcpyd%D3\\t%P0, %P2
548 fcpyd%d3\\t%P0, %P1
549 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
550 fmdrr%D3\\t%P0, %Q2, %R2
551 fmdrr%d3\\t%P0, %Q1, %R1
552 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
553 fmrrd%D3\\t%Q0, %R0, %P2
554 fmrrd%d3\\t%Q0, %R0, %P1
555 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
556 [(set_attr "conds" "use")
557 (set_attr "length" "4,4,8,4,4,8,4,4,8")
558 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
559 )
561 (define_insn "*thumb2_movdfcc_vfp"
562 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
563 (if_then_else:DF
564 (match_operator 3 "arm_comparison_operator"
565 [(match_operand 4 "cc_register" "") (const_int 0)])
566 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
567 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
568 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
569 "@
570 it\\t%D3\;fcpyd%D3\\t%P0, %P2
571 it\\t%d3\;fcpyd%d3\\t%P0, %P1
572 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
573 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
574 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
575 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
576 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
577 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
578 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
579 [(set_attr "conds" "use")
580 (set_attr "length" "6,6,10,6,6,10,6,6,10")
581 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
582 )
585 ;; Sign manipulation functions
587 (define_insn "*abssf2_vfp"
588 [(set (match_operand:SF 0 "s_register_operand" "=t")
589 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
590 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
591 "fabss%?\\t%0, %1"
592 [(set_attr "predicable" "yes")
593 (set_attr "predicable_short_it" "no")
594 (set_attr "type" "ffariths")]
595 )
597 (define_insn "*absdf2_vfp"
598 [(set (match_operand:DF 0 "s_register_operand" "=w")
599 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
600 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
601 "fabsd%?\\t%P0, %P1"
602 [(set_attr "predicable" "yes")
603 (set_attr "predicable_short_it" "no")
604 (set_attr "type" "ffarithd")]
605 )
607 (define_insn "*negsf2_vfp"
608 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
609 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
610 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
611 "@
612 fnegs%?\\t%0, %1
613 eor%?\\t%0, %1, #-2147483648"
614 [(set_attr "predicable" "yes")
615 (set_attr "predicable_short_it" "no")
616 (set_attr "type" "ffariths")]
617 )
619 (define_insn_and_split "*negdf2_vfp"
620 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
621 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
622 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
623 "@
624 fnegd%?\\t%P0, %P1
625 #
626 #"
627 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
628 && arm_general_register_operand (operands[0], DFmode)"
629 [(set (match_dup 0) (match_dup 1))]
630 "
631 if (REGNO (operands[0]) == REGNO (operands[1]))
632 {
633 operands[0] = gen_highpart (SImode, operands[0]);
634 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
635 }
636 else
637 {
638 rtx in_hi, in_lo, out_hi, out_lo;
640 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
641 GEN_INT (0x80000000));
642 in_lo = gen_lowpart (SImode, operands[1]);
643 out_hi = gen_highpart (SImode, operands[0]);
644 out_lo = gen_lowpart (SImode, operands[0]);
646 if (REGNO (in_lo) == REGNO (out_hi))
647 {
648 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
649 operands[0] = out_hi;
650 operands[1] = in_hi;
651 }
652 else
653 {
654 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
655 operands[0] = out_lo;
656 operands[1] = in_lo;
657 }
658 }
659 "
660 [(set_attr "predicable" "yes")
661 (set_attr "predicable_short_it" "no")
662 (set_attr "length" "4,4,8")
663 (set_attr "type" "ffarithd")]
664 )
667 ;; Arithmetic insns
669 (define_insn "*addsf3_vfp"
670 [(set (match_operand:SF 0 "s_register_operand" "=t")
671 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
672 (match_operand:SF 2 "s_register_operand" "t")))]
673 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
674 "fadds%?\\t%0, %1, %2"
675 [(set_attr "predicable" "yes")
676 (set_attr "predicable_short_it" "no")
677 (set_attr "type" "fadds")]
678 )
680 (define_insn "*adddf3_vfp"
681 [(set (match_operand:DF 0 "s_register_operand" "=w")
682 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
683 (match_operand:DF 2 "s_register_operand" "w")))]
684 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
685 "faddd%?\\t%P0, %P1, %P2"
686 [(set_attr "predicable" "yes")
687 (set_attr "predicable_short_it" "no")
688 (set_attr "type" "faddd")]
689 )
692 (define_insn "*subsf3_vfp"
693 [(set (match_operand:SF 0 "s_register_operand" "=t")
694 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
695 (match_operand:SF 2 "s_register_operand" "t")))]
696 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
697 "fsubs%?\\t%0, %1, %2"
698 [(set_attr "predicable" "yes")
699 (set_attr "predicable_short_it" "no")
700 (set_attr "type" "fadds")]
701 )
703 (define_insn "*subdf3_vfp"
704 [(set (match_operand:DF 0 "s_register_operand" "=w")
705 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
706 (match_operand:DF 2 "s_register_operand" "w")))]
707 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
708 "fsubd%?\\t%P0, %P1, %P2"
709 [(set_attr "predicable" "yes")
710 (set_attr "predicable_short_it" "no")
711 (set_attr "type" "faddd")]
712 )
715 ;; Division insns
717 (define_insn "*divsf3_vfp"
718 [(set (match_operand:SF 0 "s_register_operand" "=t")
719 (div:SF (match_operand:SF 1 "s_register_operand" "t")
720 (match_operand:SF 2 "s_register_operand" "t")))]
721 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
722 "fdivs%?\\t%0, %1, %2"
723 [(set_attr "predicable" "yes")
724 (set_attr "predicable_short_it" "no")
725 (set_attr "type" "fdivs")]
726 )
728 (define_insn "*divdf3_vfp"
729 [(set (match_operand:DF 0 "s_register_operand" "=w")
730 (div:DF (match_operand:DF 1 "s_register_operand" "w")
731 (match_operand:DF 2 "s_register_operand" "w")))]
732 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
733 "fdivd%?\\t%P0, %P1, %P2"
734 [(set_attr "predicable" "yes")
735 (set_attr "predicable_short_it" "no")
736 (set_attr "type" "fdivd")]
737 )
740 ;; Multiplication insns
742 (define_insn "*mulsf3_vfp"
743 [(set (match_operand:SF 0 "s_register_operand" "=t")
744 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
745 (match_operand:SF 2 "s_register_operand" "t")))]
746 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
747 "fmuls%?\\t%0, %1, %2"
748 [(set_attr "predicable" "yes")
749 (set_attr "predicable_short_it" "no")
750 (set_attr "type" "fmuls")]
751 )
753 (define_insn "*muldf3_vfp"
754 [(set (match_operand:DF 0 "s_register_operand" "=w")
755 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
756 (match_operand:DF 2 "s_register_operand" "w")))]
757 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
758 "fmuld%?\\t%P0, %P1, %P2"
759 [(set_attr "predicable" "yes")
760 (set_attr "predicable_short_it" "no")
761 (set_attr "type" "fmuld")]
762 )
764 (define_insn "*mulsf3negsf_vfp"
765 [(set (match_operand:SF 0 "s_register_operand" "=t")
766 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
767 (match_operand:SF 2 "s_register_operand" "t")))]
768 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
769 "fnmuls%?\\t%0, %1, %2"
770 [(set_attr "predicable" "yes")
771 (set_attr "predicable_short_it" "no")
772 (set_attr "type" "fmuls")]
773 )
775 (define_insn "*muldf3negdf_vfp"
776 [(set (match_operand:DF 0 "s_register_operand" "=w")
777 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
778 (match_operand:DF 2 "s_register_operand" "w")))]
779 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
780 "fnmuld%?\\t%P0, %P1, %P2"
781 [(set_attr "predicable" "yes")
782 (set_attr "predicable_short_it" "no")
783 (set_attr "type" "fmuld")]
784 )
787 ;; Multiply-accumulate insns
789 ;; 0 = 1 * 2 + 0
790 (define_insn "*mulsf3addsf_vfp"
791 [(set (match_operand:SF 0 "s_register_operand" "=t")
792 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
793 (match_operand:SF 3 "s_register_operand" "t"))
794 (match_operand:SF 1 "s_register_operand" "0")))]
795 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
796 "fmacs%?\\t%0, %2, %3"
797 [(set_attr "predicable" "yes")
798 (set_attr "predicable_short_it" "no")
799 (set_attr "type" "fmacs")]
800 )
802 (define_insn "*muldf3adddf_vfp"
803 [(set (match_operand:DF 0 "s_register_operand" "=w")
804 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
805 (match_operand:DF 3 "s_register_operand" "w"))
806 (match_operand:DF 1 "s_register_operand" "0")))]
807 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
808 "fmacd%?\\t%P0, %P2, %P3"
809 [(set_attr "predicable" "yes")
810 (set_attr "predicable_short_it" "no")
811 (set_attr "type" "fmacd")]
812 )
814 ;; 0 = 1 * 2 - 0
815 (define_insn "*mulsf3subsf_vfp"
816 [(set (match_operand:SF 0 "s_register_operand" "=t")
817 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
818 (match_operand:SF 3 "s_register_operand" "t"))
819 (match_operand:SF 1 "s_register_operand" "0")))]
820 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
821 "fmscs%?\\t%0, %2, %3"
822 [(set_attr "predicable" "yes")
823 (set_attr "predicable_short_it" "no")
824 (set_attr "type" "fmacs")]
825 )
827 (define_insn "*muldf3subdf_vfp"
828 [(set (match_operand:DF 0 "s_register_operand" "=w")
829 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
830 (match_operand:DF 3 "s_register_operand" "w"))
831 (match_operand:DF 1 "s_register_operand" "0")))]
832 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
833 "fmscd%?\\t%P0, %P2, %P3"
834 [(set_attr "predicable" "yes")
835 (set_attr "predicable_short_it" "no")
836 (set_attr "type" "fmacd")]
837 )
839 ;; 0 = -(1 * 2) + 0
840 (define_insn "*mulsf3negsfaddsf_vfp"
841 [(set (match_operand:SF 0 "s_register_operand" "=t")
842 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
843 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
844 (match_operand:SF 3 "s_register_operand" "t"))))]
845 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
846 "fnmacs%?\\t%0, %2, %3"
847 [(set_attr "predicable" "yes")
848 (set_attr "predicable_short_it" "no")
849 (set_attr "type" "fmacs")]
850 )
852 (define_insn "*fmuldf3negdfadddf_vfp"
853 [(set (match_operand:DF 0 "s_register_operand" "=w")
854 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
855 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
856 (match_operand:DF 3 "s_register_operand" "w"))))]
857 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
858 "fnmacd%?\\t%P0, %P2, %P3"
859 [(set_attr "predicable" "yes")
860 (set_attr "predicable_short_it" "no")
861 (set_attr "type" "fmacd")]
862 )
865 ;; 0 = -(1 * 2) - 0
866 (define_insn "*mulsf3negsfsubsf_vfp"
867 [(set (match_operand:SF 0 "s_register_operand" "=t")
868 (minus:SF (mult:SF
869 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
870 (match_operand:SF 3 "s_register_operand" "t"))
871 (match_operand:SF 1 "s_register_operand" "0")))]
872 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
873 "fnmscs%?\\t%0, %2, %3"
874 [(set_attr "predicable" "yes")
875 (set_attr "predicable_short_it" "no")
876 (set_attr "type" "fmacs")]
877 )
879 (define_insn "*muldf3negdfsubdf_vfp"
880 [(set (match_operand:DF 0 "s_register_operand" "=w")
881 (minus:DF (mult:DF
882 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
883 (match_operand:DF 3 "s_register_operand" "w"))
884 (match_operand:DF 1 "s_register_operand" "0")))]
885 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
886 "fnmscd%?\\t%P0, %P2, %P3"
887 [(set_attr "predicable" "yes")
888 (set_attr "predicable_short_it" "no")
889 (set_attr "type" "fmacd")]
890 )
892 ;; Fused-multiply-accumulate
894 (define_insn "fma<SDF:mode>4"
895 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
896 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
897 (match_operand:SDF 2 "register_operand" "<F_constraint>")
898 (match_operand:SDF 3 "register_operand" "0")))]
899 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
900 "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
901 [(set_attr "predicable" "yes")
902 (set_attr "predicable_short_it" "no")
903 (set_attr "type" "ffma<vfp_type>")]
904 )
906 (define_insn "*fmsub<SDF:mode>4"
907 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
908 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
909 "<F_constraint>"))
910 (match_operand:SDF 2 "register_operand" "<F_constraint>")
911 (match_operand:SDF 3 "register_operand" "0")))]
912 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
913 "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
914 [(set_attr "predicable" "yes")
915 (set_attr "predicable_short_it" "no")
916 (set_attr "type" "ffma<vfp_type>")]
917 )
919 (define_insn "*fnmsub<SDF:mode>4"
920 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
921 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
922 (match_operand:SDF 2 "register_operand" "<F_constraint>")
923 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
924 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
925 "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
926 [(set_attr "predicable" "yes")
927 (set_attr "predicable_short_it" "no")
928 (set_attr "type" "ffma<vfp_type>")]
929 )
931 (define_insn "*fnmadd<SDF:mode>4"
932 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
933 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
934 "<F_constraint>"))
935 (match_operand:SDF 2 "register_operand" "<F_constraint>")
936 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
937 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
938 "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
939 [(set_attr "predicable" "yes")
940 (set_attr "predicable_short_it" "no")
941 (set_attr "type" "ffma<vfp_type>")]
942 )
945 ;; Conversion routines
947 (define_insn "*extendsfdf2_vfp"
948 [(set (match_operand:DF 0 "s_register_operand" "=w")
949 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
950 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
951 "fcvtds%?\\t%P0, %1"
952 [(set_attr "predicable" "yes")
953 (set_attr "predicable_short_it" "no")
954 (set_attr "type" "f_cvt")]
955 )
957 (define_insn "*truncdfsf2_vfp"
958 [(set (match_operand:SF 0 "s_register_operand" "=t")
959 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
960 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
961 "fcvtsd%?\\t%0, %P1"
962 [(set_attr "predicable" "yes")
963 (set_attr "predicable_short_it" "no")
964 (set_attr "type" "f_cvt")]
965 )
967 (define_insn "extendhfsf2"
968 [(set (match_operand:SF 0 "s_register_operand" "=t")
969 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
970 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
971 "vcvtb%?.f32.f16\\t%0, %1"
972 [(set_attr "predicable" "yes")
973 (set_attr "predicable_short_it" "no")
974 (set_attr "type" "f_cvt")]
975 )
977 (define_insn "truncsfhf2"
978 [(set (match_operand:HF 0 "s_register_operand" "=t")
979 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
980 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
981 "vcvtb%?.f16.f32\\t%0, %1"
982 [(set_attr "predicable" "yes")
983 (set_attr "predicable_short_it" "no")
984 (set_attr "type" "f_cvt")]
985 )
987 (define_insn "*truncsisf2_vfp"
988 [(set (match_operand:SI 0 "s_register_operand" "=t")
989 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
990 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
991 "ftosizs%?\\t%0, %1"
992 [(set_attr "predicable" "yes")
993 (set_attr "predicable_short_it" "no")
994 (set_attr "type" "f_cvtf2i")]
995 )
997 (define_insn "*truncsidf2_vfp"
998 [(set (match_operand:SI 0 "s_register_operand" "=t")
999 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
1000 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1001 "ftosizd%?\\t%0, %P1"
1002 [(set_attr "predicable" "yes")
1003 (set_attr "predicable_short_it" "no")
1004 (set_attr "type" "f_cvtf2i")]
1005 )
1008 (define_insn "fixuns_truncsfsi2"
1009 [(set (match_operand:SI 0 "s_register_operand" "=t")
1010 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1011 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1012 "ftouizs%?\\t%0, %1"
1013 [(set_attr "predicable" "yes")
1014 (set_attr "predicable_short_it" "no")
1015 (set_attr "type" "f_cvtf2i")]
1016 )
1018 (define_insn "fixuns_truncdfsi2"
1019 [(set (match_operand:SI 0 "s_register_operand" "=t")
1020 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1021 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1022 "ftouizd%?\\t%0, %P1"
1023 [(set_attr "predicable" "yes")
1024 (set_attr "predicable_short_it" "no")
1025 (set_attr "type" "f_cvtf2i")]
1026 )
1029 (define_insn "*floatsisf2_vfp"
1030 [(set (match_operand:SF 0 "s_register_operand" "=t")
1031 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1032 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1033 "fsitos%?\\t%0, %1"
1034 [(set_attr "predicable" "yes")
1035 (set_attr "predicable_short_it" "no")
1036 (set_attr "type" "f_cvti2f")]
1037 )
1039 (define_insn "*floatsidf2_vfp"
1040 [(set (match_operand:DF 0 "s_register_operand" "=w")
1041 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1042 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1043 "fsitod%?\\t%P0, %1"
1044 [(set_attr "predicable" "yes")
1045 (set_attr "predicable_short_it" "no")
1046 (set_attr "type" "f_cvti2f")]
1047 )
1050 (define_insn "floatunssisf2"
1051 [(set (match_operand:SF 0 "s_register_operand" "=t")
1052 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1053 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1054 "fuitos%?\\t%0, %1"
1055 [(set_attr "predicable" "yes")
1056 (set_attr "predicable_short_it" "no")
1057 (set_attr "type" "f_cvti2f")]
1058 )
1060 (define_insn "floatunssidf2"
1061 [(set (match_operand:DF 0 "s_register_operand" "=w")
1062 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1063 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1064 "fuitod%?\\t%P0, %1"
1065 [(set_attr "predicable" "yes")
1066 (set_attr "predicable_short_it" "no")
1067 (set_attr "type" "f_cvti2f")]
1068 )
1071 ;; Sqrt insns.
1073 (define_insn "*sqrtsf2_vfp"
1074 [(set (match_operand:SF 0 "s_register_operand" "=t")
1075 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
1076 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1077 "fsqrts%?\\t%0, %1"
1078 [(set_attr "predicable" "yes")
1079 (set_attr "predicable_short_it" "no")
1080 (set_attr "type" "fsqrts")]
1081 )
1083 (define_insn "*sqrtdf2_vfp"
1084 [(set (match_operand:DF 0 "s_register_operand" "=w")
1085 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
1086 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1087 "fsqrtd%?\\t%P0, %P1"
1088 [(set_attr "predicable" "yes")
1089 (set_attr "predicable_short_it" "no")
1090 (set_attr "type" "fsqrtd")]
1091 )
1094 ;; Patterns to split/copy vfp condition flags.
1096 (define_insn "*movcc_vfp"
1097 [(set (reg CC_REGNUM)
1098 (reg VFPCC_REGNUM))]
1099 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1100 "fmstat%?"
1101 [(set_attr "conds" "set")
1102 (set_attr "type" "f_flag")]
1103 )
1105 (define_insn_and_split "*cmpsf_split_vfp"
1106 [(set (reg:CCFP CC_REGNUM)
1107 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
1108 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1109 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1110 "#"
1111 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1112 [(set (reg:CCFP VFPCC_REGNUM)
1113 (compare:CCFP (match_dup 0)
1114 (match_dup 1)))
1115 (set (reg:CCFP CC_REGNUM)
1116 (reg:CCFP VFPCC_REGNUM))]
1117 ""
1118 )
1120 (define_insn_and_split "*cmpsf_trap_split_vfp"
1121 [(set (reg:CCFPE CC_REGNUM)
1122 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
1123 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1124 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1125 "#"
1126 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1127 [(set (reg:CCFPE VFPCC_REGNUM)
1128 (compare:CCFPE (match_dup 0)
1129 (match_dup 1)))
1130 (set (reg:CCFPE CC_REGNUM)
1131 (reg:CCFPE VFPCC_REGNUM))]
1132 ""
1133 )
1135 (define_insn_and_split "*cmpdf_split_vfp"
1136 [(set (reg:CCFP CC_REGNUM)
1137 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
1138 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1139 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1140 "#"
1141 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1142 [(set (reg:CCFP VFPCC_REGNUM)
1143 (compare:CCFP (match_dup 0)
1144 (match_dup 1)))
1145 (set (reg:CCFP CC_REGNUM)
1146 (reg:CCFP VFPCC_REGNUM))]
1147 ""
1148 )
1150 (define_insn_and_split "*cmpdf_trap_split_vfp"
1151 [(set (reg:CCFPE CC_REGNUM)
1152 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
1153 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1154 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1155 "#"
1156 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1157 [(set (reg:CCFPE VFPCC_REGNUM)
1158 (compare:CCFPE (match_dup 0)
1159 (match_dup 1)))
1160 (set (reg:CCFPE CC_REGNUM)
1161 (reg:CCFPE VFPCC_REGNUM))]
1162 ""
1163 )
1166 ;; Comparison patterns
1168 (define_insn "*cmpsf_vfp"
1169 [(set (reg:CCFP VFPCC_REGNUM)
1170 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
1171 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1172 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1173 "@
1174 fcmps%?\\t%0, %1
1175 fcmpzs%?\\t%0"
1176 [(set_attr "predicable" "yes")
1177 (set_attr "predicable_short_it" "no")
1178 (set_attr "type" "fcmps")]
1179 )
1181 (define_insn "*cmpsf_trap_vfp"
1182 [(set (reg:CCFPE VFPCC_REGNUM)
1183 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
1184 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1185 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1186 "@
1187 fcmpes%?\\t%0, %1
1188 fcmpezs%?\\t%0"
1189 [(set_attr "predicable" "yes")
1190 (set_attr "predicable_short_it" "no")
1191 (set_attr "type" "fcmps")]
1192 )
1194 (define_insn "*cmpdf_vfp"
1195 [(set (reg:CCFP VFPCC_REGNUM)
1196 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
1197 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1198 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1199 "@
1200 fcmpd%?\\t%P0, %P1
1201 fcmpzd%?\\t%P0"
1202 [(set_attr "predicable" "yes")
1203 (set_attr "predicable_short_it" "no")
1204 (set_attr "type" "fcmpd")]
1205 )
1207 (define_insn "*cmpdf_trap_vfp"
1208 [(set (reg:CCFPE VFPCC_REGNUM)
1209 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
1210 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1211 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1212 "@
1213 fcmped%?\\t%P0, %P1
1214 fcmpezd%?\\t%P0"
1215 [(set_attr "predicable" "yes")
1216 (set_attr "predicable_short_it" "no")
1217 (set_attr "type" "fcmpd")]
1218 )
1220 ;; Fixed point to floating point conversions.
1221 (define_code_iterator FCVT [unsigned_float float])
1222 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1224 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1225 [(set (match_operand:SF 0 "s_register_operand" "=t")
1226 (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1227 (match_operand 2
1228 "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1229 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1230 "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
1231 [(set_attr "predicable" "yes")
1232 (set_attr "predicable_short_it" "no")
1233 (set_attr "type" "f_cvti2f")]
1234 )
1236 ;; Not the ideal way of implementing this. Ideally we would be able to split
1237 ;; this into a move to a DP register and then a vcvt.f64.i32
1238 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1239 [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1240 (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1241 (match_operand 2
1242 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1243 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1244 && !TARGET_VFP_SINGLE"
1245 "@
1246 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1247 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1248 vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1249 [(set_attr "predicable" "yes")
1250 (set_attr "ce_count" "2")
1251 (set_attr "predicable_short_it" "no")
1252 (set_attr "type" "f_cvti2f")
1253 (set_attr "length" "8")]
1254 )
1256 (define_insn "*combine_vcvtf2i"
1257 [(set (match_operand:SI 0 "s_register_operand" "=r")
1258 (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
1259 (match_operand 2
1260 "const_double_vcvt_power_of_two" "Dp")))))]
1261 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1262 "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
1263 [(set_attr "predicable" "yes")
1264 (set_attr "predicable_short_it" "no")
1265 (set_attr "ce_count" "2")
1266 (set_attr "type" "f_cvtf2i")
1267 (set_attr "length" "8")]
1268 )
1270 ;; Store multiple insn used in function prologue.
1271 (define_insn "*push_multi_vfp"
1272 [(match_parallel 2 "multi_register_push"
1273 [(set (match_operand:BLK 0 "memory_operand" "=m")
1274 (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1275 UNSPEC_PUSH_MULT))])]
1276 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1277 "* return vfp_output_fstmd (operands);"
1278 [(set_attr "type" "f_stored")]
1279 )
1281 ;; VRINT round to integral instructions.
1282 ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
1283 ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
1284 ;; rintsf2, rintdf2.
1285 (define_insn "<vrint_pattern><SDF:mode>2"
1286 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1287 (unspec:SDF [(match_operand:SDF 1
1288 "register_operand" "<F_constraint>")]
1289 VRINT))]
1290 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1291 "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1292 [(set_attr "predicable" "<vrint_predicable>")
1293 (set_attr "predicable_short_it" "no")
1294 (set_attr "type" "f_rint<vfp_type>")
1295 (set_attr "conds" "<vrint_conds>")]
1296 )
1298 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
1299 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
1300 ;; operand will be returned when both operands are zero (i.e. they may not
1301 ;; honour signed zeroes), or when either operand is NaN. Therefore GCC
1302 ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
1303 ;; NaNs.
1305 (define_insn "smax<mode>3"
1306 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1307 (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1308 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1309 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1310 "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1311 [(set_attr "type" "f_minmax<vfp_type>")
1312 (set_attr "conds" "unconditional")]
1313 )
1315 (define_insn "smin<mode>3"
1316 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1317 (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1318 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1319 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1320 "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1321 [(set_attr "type" "f_minmax<vfp_type>")
1322 (set_attr "conds" "unconditional")]
1323 )
1325 ;; Write Floating-point Status and Control Register.
1326 (define_insn "set_fpscr"
1327 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
1328 "TARGET_VFP"
1329 "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
1330 [(set_attr "type" "mrs")])
1332 ;; Read Floating-point Status and Control Register.
1333 (define_insn "get_fpscr"
1334 [(set (match_operand:SI 0 "register_operand" "=r")
1335 (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
1336 "TARGET_VFP"
1337 "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
1338 [(set_attr "type" "mrs")])
1341 ;; Unimplemented insns:
1342 ;; fldm*
1343 ;; fstm*
1344 ;; fmdhr et al (VFPv1)
1345 ;; Support for xD (single precision only) variants.
1346 ;; fmrrs, fmsrr