1 /* IBM RS
/6000 CPU names..
2 Copyright (C
) 1991-2015 Free Software Foundation
, Inc.
3 Contributed by Richard
Kenner (kenner@vlsi1.ultra.nyu.edu
)
5 This file is part of GCC.
7 GCC is free software
; you can redistribute it and
/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation
; either version
3, or (at your
10 option
) any later version.
12 GCC is distributed in the hope that it will be useful
, but WITHOUT
13 ANY WARRANTY
; without even the implied warranty of MERCHANTABILITY
14 or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC
; see the file COPYING3. If not see
19 <http
://www.gnu.org
/licenses
/>.
*/
23 #define ISA_2_1_MASKS OPTION_MASK_MFCRF
24 #define
ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB
)
25 #define
ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND
)
27 /* For ISA
2.05, do not add MFPGPR
, since it isn
't in ISA 2.06, and don't add
28 ALTIVEC
, since in general it isn
't a win on power6. In ISA 2.04, fsel,
29 fre, fsqrt, etc. were no longer documented as optional. Group masks by
30 server and embedded. */
31 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
33 | OPTION_MASK_RECIP_PRECISION \
34 | OPTION_MASK_PPC_GFXOPT \
35 | OPTION_MASK_PPC_GPOPT)
37 #define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
39 /* For ISA 2.06, don't add ISEL
, since in general it isn
't a win, but
40 altivec is a win so enable it. */
41 /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
43 #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
44 #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
45 | OPTION_MASK_POPCNTD \
46 | OPTION_MASK_ALTIVEC \
48 | OPTION_MASK_UPPER_REGS_DF)
50 /* For now, don't provide an embedded version of ISA
2.07.
*/
51 #define
ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
52 | OPTION_MASK_P8_FUSION \
53 | OPTION_MASK_P8_VECTOR \
54 | OPTION_MASK_CRYPTO \
55 | OPTION_MASK_DIRECT_MOVE \
57 | OPTION_MASK_QUAD_MEMORY \
58 | OPTION_MASK_QUAD_MEMORY_ATOMIC \
59 | OPTION_MASK_UPPER_REGS_SF
)
61 #define
POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC
)
63 /* Deal with ports that do not have
-mstrict
-align.
*/
64 #ifdef OPTION_MASK_STRICT_ALIGN
65 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
67 #define OPTION_MASK_STRICT_ALIGN
0
68 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL
0
69 #ifndef MASK_STRICT_ALIGN
70 #define MASK_STRICT_ALIGN
0
74 /* Mask of all options to set the default isa flags based on
-mcpu
=<xxx
>.
*/
75 #define
POWERPC_MASKS (OPTION_MASK_ALTIVEC \
77 | OPTION_MASK_CRYPTO \
79 | OPTION_MASK_DIRECT_MOVE \
85 | OPTION_MASK_MFPGPR \
87 | OPTION_MASK_NO_UPDATE \
88 | OPTION_MASK_P8_FUSION \
89 | OPTION_MASK_P8_VECTOR \
90 | OPTION_MASK_POPCNTB \
91 | OPTION_MASK_POPCNTD \
92 | OPTION_MASK_POWERPC64 \
93 | OPTION_MASK_PPC_GFXOPT \
94 | OPTION_MASK_PPC_GPOPT \
95 | OPTION_MASK_QUAD_MEMORY \
96 | OPTION_MASK_QUAD_MEMORY_ATOMIC \
97 | OPTION_MASK_RECIP_PRECISION \
98 | OPTION_MASK_SOFT_FLOAT \
99 | OPTION_MASK_STRICT_ALIGN_OPTIONAL \
100 | OPTION_MASK_UPPER_REGS_DF \
101 | OPTION_MASK_UPPER_REGS_SF \
103 | OPTION_MASK_VSX_TIMODE
)
107 /* This table occasionally claims that a processor does not support a
108 particular feature even though it does
, but the feature is slower than the
109 alternative. Thus
, it shouldn
't be relied on as a complete description of
110 the processor's support.
112 Please keep this list in order
, and don
't forget to update the documentation
113 in invoke.texi when adding a new processor or flag.
115 Before including this file, define a macro:
117 RS6000_CPU (NAME, CPU, FLAGS)
119 where the arguments are the fields of struct rs6000_ptt. */
121 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
122 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
123 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
124 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
125 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
126 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
127 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
128 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
129 RS6000_CPU ("476", PROCESSOR_PPC476,
130 MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
131 | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
132 RS6000_CPU ("476fp", PROCESSOR_PPC476,
133 MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
134 | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
135 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
136 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
137 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
138 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
139 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
140 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
141 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
142 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
143 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
144 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
145 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
146 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
147 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
148 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
149 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
150 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
151 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
152 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
153 RS6000_CPU ("a2", PROCESSOR_PPCA2,
154 MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
156 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
157 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
158 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
159 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
160 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
161 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
162 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
163 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
164 | MASK_MFCRF | MASK_ISEL)
165 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
166 RS6000_CPU ("970", PROCESSOR_POWER4,
167 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
168 RS6000_CPU ("cell", PROCESSOR_CELL,
169 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
170 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
171 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
172 RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
173 RS6000_CPU ("G5", PROCESSOR_POWER4,
174 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
175 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
176 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
177 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
178 | MASK_PPC_GFXOPT | MASK_MFCRF)
179 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
180 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
181 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
182 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
183 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
184 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
185 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
186 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
187 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
188 | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
189 RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default
*/
190 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
191 | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
192 | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
)
193 RS6000_CPU ("power8", PROCESSOR_POWER8
, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
)
194 RS6000_CPU ("powerpc", PROCESSOR_POWERPC
, 0)
195 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64
, MASK_PPC_GFXOPT | MASK_POWERPC64
)
196 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8
, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
)
197 RS6000_CPU ("rs64", PROCESSOR_RS64A
, MASK_PPC_GFXOPT | MASK_POWERPC64
)