1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (match_operand 0 "register_operand")
121 if (GET_CODE (op) == SUBREG)
122 op = SUBREG_REG (op);
127 return CA_REGNO_P (REGNO (op));
130 ;; Return 1 if op is a signed 5-bit constant integer.
131 (define_predicate "s5bit_cint_operand"
132 (and (match_code "const_int")
133 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
135 ;; Return 1 if op is a unsigned 3-bit constant integer.
136 (define_predicate "u3bit_cint_operand"
137 (and (match_code "const_int")
138 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
140 ;; Return 1 if op is a unsigned 5-bit constant integer.
141 (define_predicate "u5bit_cint_operand"
142 (and (match_code "const_int")
143 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
145 ;; Return 1 if op is a signed 8-bit constant integer.
146 ;; Integer multiplication complete more quickly
147 (define_predicate "s8bit_cint_operand"
148 (and (match_code "const_int")
149 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
151 ;; Return 1 if op is a unsigned 10-bit constant integer.
152 (define_predicate "u10bit_cint_operand"
153 (and (match_code "const_int")
154 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
156 ;; Return 1 if op is a constant integer that can fit in a D field.
157 (define_predicate "short_cint_operand"
158 (and (match_code "const_int")
159 (match_test "satisfies_constraint_I (op)")))
161 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
162 (define_predicate "u_short_cint_operand"
163 (and (match_code "const_int")
164 (match_test "satisfies_constraint_K (op)")))
166 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
167 (define_predicate "non_short_cint_operand"
168 (and (match_code "const_int")
169 (match_test "(unsigned HOST_WIDE_INT)
170 (INTVAL (op) + 0x8000) >= 0x10000")))
172 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
173 (define_predicate "exact_log2_cint_operand"
174 (and (match_code "const_int")
175 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
177 ;; Match op = 0 or op = 1.
178 (define_predicate "const_0_to_1_operand"
179 (and (match_code "const_int")
180 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
183 (define_predicate "const_0_to_3_operand"
184 (and (match_code "const_int")
185 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
187 ;; Match op = 2 or op = 3.
188 (define_predicate "const_2_to_3_operand"
189 (and (match_code "const_int")
190 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
193 (define_predicate "const_0_to_15_operand"
194 (and (match_code "const_int")
195 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
197 ;; Return 1 if op is a register that is not special.
198 (define_predicate "gpc_reg_operand"
199 (match_operand 0 "register_operand")
201 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
204 if (GET_CODE (op) == SUBREG)
205 op = SUBREG_REG (op);
210 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
213 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
216 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
219 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
222 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
223 ;; allow floating point or vector registers.
224 (define_predicate "int_reg_operand"
225 (match_operand 0 "register_operand")
227 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
230 if (GET_CODE (op) == SUBREG)
231 op = SUBREG_REG (op);
236 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
239 return INT_REGNO_P (REGNO (op));
242 ;; Like int_reg_operand, but only return true for base registers
243 (define_predicate "base_reg_operand"
244 (match_operand 0 "int_reg_operand")
246 if (GET_CODE (op) == SUBREG)
247 op = SUBREG_REG (op);
252 return (REGNO (op) != FIRST_GPR_REGNO);
255 ;; Return 1 if op is a HTM specific SPR register.
256 (define_predicate "htm_spr_reg_operand"
257 (match_operand 0 "register_operand")
262 if (GET_CODE (op) == SUBREG)
263 op = SUBREG_REG (op);
282 ;; Return 1 if op is a general purpose register that is an even register
283 ;; which suitable for a load/store quad operation
284 (define_predicate "quad_int_reg_operand"
285 (match_operand 0 "register_operand")
289 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
292 if (GET_CODE (op) == SUBREG)
293 op = SUBREG_REG (op);
299 if (r >= FIRST_PSEUDO_REGISTER)
302 return (INT_REGNO_P (r) && ((r & 1) == 0));
305 ;; Return 1 if op is a register that is a condition register field.
306 (define_predicate "cc_reg_operand"
307 (match_operand 0 "register_operand")
309 if (GET_CODE (op) == SUBREG)
310 op = SUBREG_REG (op);
315 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
318 return CR_REGNO_P (REGNO (op));
321 ;; Return 1 if op is a register that is a condition register field not cr0.
322 (define_predicate "cc_reg_not_cr0_operand"
323 (match_operand 0 "register_operand")
325 if (GET_CODE (op) == SUBREG)
326 op = SUBREG_REG (op);
331 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
334 return CR_REGNO_NOT_CR0_P (REGNO (op));
337 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
338 (define_predicate "cc_reg_not_micro_cr0_operand"
339 (match_operand 0 "register_operand")
341 if (GET_CODE (op) == SUBREG)
342 op = SUBREG_REG (op);
347 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
350 if (rs6000_gen_cell_microcode)
351 return CR_REGNO_NOT_CR0_P (REGNO (op));
353 return CR_REGNO_P (REGNO (op));
356 ;; Return 1 if op is a constant integer valid for D field
357 ;; or non-special register register.
358 (define_predicate "reg_or_short_operand"
359 (if_then_else (match_code "const_int")
360 (match_operand 0 "short_cint_operand")
361 (match_operand 0 "gpc_reg_operand")))
363 ;; Return 1 if op is a constant integer valid for DS field
364 ;; or non-special register.
365 (define_predicate "reg_or_aligned_short_operand"
366 (if_then_else (match_code "const_int")
367 (and (match_operand 0 "short_cint_operand")
368 (match_test "!(INTVAL (op) & 3)"))
369 (match_operand 0 "gpc_reg_operand")))
371 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
372 ;; or non-special register.
373 (define_predicate "reg_or_u_short_operand"
374 (if_then_else (match_code "const_int")
375 (match_operand 0 "u_short_cint_operand")
376 (match_operand 0 "gpc_reg_operand")))
378 ;; Return 1 if op is any constant integer
379 ;; or non-special register.
380 (define_predicate "reg_or_cint_operand"
381 (ior (match_code "const_int")
382 (match_operand 0 "gpc_reg_operand")))
384 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
385 (define_predicate "add_cint_operand"
386 (and (match_code "const_int")
387 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
388 + (mode == SImode ? 0x80000000 : 0x80008000))
389 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
391 ;; Return 1 if op is a constant integer valid for addition
392 ;; or non-special register.
393 (define_predicate "reg_or_add_cint_operand"
394 (if_then_else (match_code "const_int")
395 (match_operand 0 "add_cint_operand")
396 (match_operand 0 "gpc_reg_operand")))
398 ;; Return 1 if op is a constant integer valid for subtraction
399 ;; or non-special register.
400 (define_predicate "reg_or_sub_cint_operand"
401 (if_then_else (match_code "const_int")
402 (match_test "(unsigned HOST_WIDE_INT)
403 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
404 < (unsigned HOST_WIDE_INT) 0x100000000ll")
405 (match_operand 0 "gpc_reg_operand")))
407 ;; Return 1 if op is any 32-bit unsigned constant integer
408 ;; or non-special register.
409 (define_predicate "reg_or_logical_cint_operand"
410 (if_then_else (match_code "const_int")
411 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
413 || ((INTVAL (op) & GET_MODE_MASK (mode)
414 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
415 (match_operand 0 "gpc_reg_operand")))
417 ;; Like reg_or_logical_cint_operand, but allow vsx registers
418 (define_predicate "vsx_reg_or_cint_operand"
419 (ior (match_operand 0 "vsx_register_operand")
420 (match_operand 0 "reg_or_logical_cint_operand")))
422 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
423 ;; with no more than one instruction per word.
424 (define_predicate "easy_fp_constant"
425 (match_code "const_double")
427 if (GET_MODE (op) != mode
428 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
431 /* Consider all constants with -msoft-float to be easy. */
432 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
433 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
437 /* The constant 0.0 is easy under VSX. */
438 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
441 if (DECIMAL_FLOAT_MODE_P (mode))
444 /* If we are using V.4 style PIC, consider all constants to be hard. */
445 if (flag_pic && DEFAULT_ABI == ABI_V4)
448 #ifdef TARGET_RELOCATABLE
449 /* Similarly if we are using -mrelocatable, consider all constants
451 if (TARGET_RELOCATABLE)
455 /* If we have real FPRs, consider floating point constants hard (other than
456 0.0 under VSX), so that the constant gets pushed to memory during the
457 early RTL phases. This has the advantage that double precision constants
458 that can be represented in single precision without a loss of precision
459 will use single precision loads. */
469 return (num_insns_constant (op, DImode) <= 2);
479 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
480 ;; vector register without using memory.
481 (define_predicate "easy_vector_constant"
482 (match_code "const_vector")
484 /* As the paired vectors are actually FPRs it seems that there is
485 no easy way to load a CONST_VECTOR without using memory. */
486 if (TARGET_PAIRED_FLOAT)
489 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
491 if (zero_constant (op, mode))
494 return easy_altivec_constant (op, mode);
497 if (SPE_VECTOR_MODE (mode))
500 if (zero_constant (op, mode))
502 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
505 /* Limit SPE vectors to 15 bits signed. These we can generate with:
510 I don't know how efficient it would be to allow bigger constants,
511 considering we'll have an extra 'ori' for every 'li'. I doubt 5
512 instructions is better than a 64-bit memory load, but I don't
513 have the e500 timing specs. */
514 if (mode == V2SImode)
516 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
517 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
518 return cst >= -0x7fff && cst <= 0x7fff
519 && cst2 >= -0x7fff && cst2 <= 0x7fff;
526 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
527 (define_predicate "easy_vector_constant_add_self"
528 (and (match_code "const_vector")
529 (and (match_test "TARGET_ALTIVEC")
530 (match_test "easy_altivec_constant (op, mode)")))
534 if (mode == V2DImode || mode == V2DFmode)
536 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
537 val = const_vector_elt_as_int (op, elt);
538 val = ((val & 0xff) ^ 0x80) - 0x80;
539 return EASY_VECTOR_15_ADD_SELF (val);
542 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
543 (define_predicate "easy_vector_constant_msb"
544 (and (match_code "const_vector")
545 (and (match_test "TARGET_ALTIVEC")
546 (match_test "easy_altivec_constant (op, mode)")))
550 if (mode == V2DImode || mode == V2DFmode)
552 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
553 val = const_vector_elt_as_int (op, elt);
554 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
557 ;; Return 1 if operand is constant zero (scalars and vectors).
558 (define_predicate "zero_constant"
559 (and (match_code "const_int,const_double,const_wide_int,const_vector")
560 (match_test "op == CONST0_RTX (mode)")))
562 ;; Return 1 if operand is 0.0.
563 (define_predicate "zero_fp_constant"
564 (and (match_code "const_double")
565 (match_test "SCALAR_FLOAT_MODE_P (mode)
566 && op == CONST0_RTX (mode)")))
568 ;; Return 1 if the operand is in volatile memory. Note that during the
569 ;; RTL generation phase, memory_operand does not return TRUE for volatile
570 ;; memory references. So this function allows us to recognize volatile
571 ;; references where it's safe.
572 (define_predicate "volatile_mem_operand"
573 (and (and (match_code "mem")
574 (match_test "MEM_VOLATILE_P (op)"))
575 (if_then_else (match_test "reload_completed")
576 (match_operand 0 "memory_operand")
577 (if_then_else (match_test "reload_in_progress")
578 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
579 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
581 ;; Return 1 if the operand is an offsettable memory operand.
582 (define_predicate "offsettable_mem_operand"
583 (and (match_operand 0 "memory_operand")
584 (match_test "offsettable_nonstrict_memref_p (op)")))
586 ;; Return 1 if the operand is suitable for load/store quad memory.
587 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
588 (define_predicate "quad_memory_operand"
594 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
597 else if (!memory_operand (op, mode))
600 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
603 else if (MEM_ALIGN (op) < 128)
609 if (int_reg_operand (addr, Pmode))
612 else if (GET_CODE (addr) != PLUS)
617 op0 = XEXP (addr, 0);
618 op1 = XEXP (addr, 1);
619 ret = (int_reg_operand (op0, Pmode)
620 && GET_CODE (op1) == CONST_INT
621 && IN_RANGE (INTVAL (op1), -32768, 32767)
622 && (INTVAL (op1) & 15) == 0);
626 if (TARGET_DEBUG_ADDR)
628 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
635 ;; Return 1 if the operand is an indexed or indirect memory operand.
636 (define_predicate "indexed_or_indirect_operand"
640 if (VECTOR_MEM_ALTIVEC_P (mode)
641 && GET_CODE (op) == AND
642 && GET_CODE (XEXP (op, 1)) == CONST_INT
643 && INTVAL (XEXP (op, 1)) == -16)
646 return indexed_or_indirect_address (op, mode);
649 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
650 ;; moves are supported.
651 (define_predicate "reg_or_indexed_operand"
652 (match_code "mem,reg")
655 return indexed_or_indirect_operand (op, mode);
656 else if (TARGET_DIRECT_MOVE)
657 return register_operand (op, mode);
662 ;; Return 1 if the operand is an indexed or indirect memory operand with an
663 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
664 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
665 ;; while VSX uses the full address and traps)
666 (define_predicate "altivec_indexed_or_indirect_operand"
670 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
671 && GET_CODE (op) == AND
672 && GET_CODE (XEXP (op, 1)) == CONST_INT
673 && INTVAL (XEXP (op, 1)) == -16)
674 return indexed_or_indirect_address (XEXP (op, 0), mode);
679 ;; Return 1 if the operand is an indexed or indirect address.
680 (define_special_predicate "indexed_or_indirect_address"
681 (and (match_test "REG_P (op)
682 || (GET_CODE (op) == PLUS
683 /* Omit testing REG_P (XEXP (op, 0)). */
684 && REG_P (XEXP (op, 1)))")
685 (match_operand 0 "address_operand")))
687 ;; Return 1 if the operand is an index-form address.
688 (define_special_predicate "indexed_address"
689 (match_test "(GET_CODE (op) == PLUS
690 && REG_P (XEXP (op, 0))
691 && REG_P (XEXP (op, 1)))"))
693 ;; Return 1 if the operand is a MEM with an update-form address. This may
694 ;; also include update-indexed form.
695 (define_special_predicate "update_address_mem"
696 (match_test "(MEM_P (op)
697 && (GET_CODE (XEXP (op, 0)) == PRE_INC
698 || GET_CODE (XEXP (op, 0)) == PRE_DEC
699 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
701 ;; Return 1 if the operand is a MEM with an indexed-form address.
702 (define_special_predicate "indexed_address_mem"
703 (match_test "(MEM_P (op)
704 && (indexed_address (XEXP (op, 0), mode)
705 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
706 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
708 ;; Return 1 if the operand is either a non-special register or can be used
709 ;; as the operand of a `mode' add insn.
710 (define_predicate "add_operand"
711 (if_then_else (match_code "const_int")
712 (match_test "satisfies_constraint_I (op)
713 || satisfies_constraint_L (op)")
714 (match_operand 0 "gpc_reg_operand")))
716 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
717 (define_predicate "adde_operand"
718 (if_then_else (match_code "const_int")
719 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
720 (match_operand 0 "gpc_reg_operand")))
722 ;; Return 1 if OP is a constant but not a valid add_operand.
723 (define_predicate "non_add_cint_operand"
724 (and (match_code "const_int")
725 (match_test "!satisfies_constraint_I (op)
726 && !satisfies_constraint_L (op)")))
728 ;; Return 1 if the operand is a constant that can be used as the operand
730 (define_predicate "logical_const_operand"
731 (match_code "const_int")
735 opl = INTVAL (op) & GET_MODE_MASK (mode);
737 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
738 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
741 ;; Return 1 if the operand is a non-special register or a constant that
742 ;; can be used as the operand of an OR or XOR.
743 (define_predicate "logical_operand"
744 (ior (match_operand 0 "gpc_reg_operand")
745 (match_operand 0 "logical_const_operand")))
747 ;; Return 1 if op is a constant that is not a logical operand, but could
748 ;; be split into one.
749 (define_predicate "non_logical_cint_operand"
750 (and (match_code "const_int,const_wide_int")
751 (and (not (match_operand 0 "logical_operand"))
752 (match_operand 0 "reg_or_logical_cint_operand"))))
754 ;; Return 1 if the operand is either a non-special register or a
755 ;; constant that can be used as the operand of a logical AND.
756 (define_predicate "and_operand"
757 (ior (match_test "rs6000_is_valid_and_mask (op, mode)")
758 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
759 (match_operand 0 "gpc_reg_operand")
760 (match_operand 0 "logical_operand"))))
762 ;; Return 1 if the operand is either a logical operand or a short cint operand.
763 (define_predicate "scc_eq_operand"
764 (ior (match_operand 0 "logical_operand")
765 (match_operand 0 "short_cint_operand")))
767 ;; Return 1 if the operand is a general non-special register or memory operand.
768 (define_predicate "reg_or_mem_operand"
769 (ior (match_operand 0 "memory_operand")
770 (ior (and (match_code "mem")
771 (match_test "macho_lo_sum_memory_operand (op, mode)"))
772 (ior (match_operand 0 "volatile_mem_operand")
773 (match_operand 0 "gpc_reg_operand")))))
775 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
776 (define_predicate "reg_or_none500mem_operand"
777 (if_then_else (match_code "mem")
778 (and (match_test "!TARGET_E500_DOUBLE")
779 (ior (match_operand 0 "memory_operand")
780 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
781 (match_operand 0 "volatile_mem_operand"))))
782 (match_operand 0 "gpc_reg_operand")))
784 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
785 (define_predicate "zero_reg_mem_operand"
786 (ior (and (match_test "TARGET_VSX")
787 (match_operand 0 "zero_fp_constant"))
788 (match_operand 0 "reg_or_mem_operand")))
790 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
791 ;; data types inside of a vector that scalar instructions operate on
792 (define_predicate "vsx_scalar_64bit"
793 (match_code "const_int")
795 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
798 ;; Return 1 if the operand is a general register or memory operand without
799 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
801 (define_predicate "lwa_operand"
802 (match_code "reg,subreg,mem")
804 rtx inner, addr, offset;
807 if (reload_completed && GET_CODE (inner) == SUBREG)
808 inner = SUBREG_REG (inner);
810 if (gpc_reg_operand (inner, mode))
812 if (!memory_operand (inner, mode))
814 if (!rs6000_gen_cell_microcode)
817 addr = XEXP (inner, 0);
818 if (GET_CODE (addr) == PRE_INC
819 || GET_CODE (addr) == PRE_DEC
820 || (GET_CODE (addr) == PRE_MODIFY
821 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
823 if (GET_CODE (addr) == LO_SUM
824 && GET_CODE (XEXP (addr, 0)) == REG
825 && GET_CODE (XEXP (addr, 1)) == CONST)
826 addr = XEXP (XEXP (addr, 1), 0);
827 if (GET_CODE (addr) != PLUS)
829 offset = XEXP (addr, 1);
830 if (GET_CODE (offset) != CONST_INT)
832 return INTVAL (offset) % 4 == 0;
835 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
836 (define_predicate "symbol_ref_operand"
837 (and (match_code "symbol_ref")
838 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
839 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
841 ;; Return 1 if op is an operand that can be loaded via the GOT.
842 ;; or non-special register register field no cr0
843 (define_predicate "got_operand"
844 (match_code "symbol_ref,const,label_ref"))
846 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
847 ;; excluding labels involving addition.
848 (define_predicate "got_no_const_operand"
849 (match_code "symbol_ref,label_ref"))
851 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
852 (define_predicate "rs6000_tls_symbol_ref"
853 (and (match_code "symbol_ref")
854 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
856 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
857 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
858 (define_predicate "call_operand"
859 (if_then_else (match_code "reg")
860 (match_test "REGNO (op) == LR_REGNO
861 || REGNO (op) == CTR_REGNO
862 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
863 (match_code "symbol_ref")))
865 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
867 (define_predicate "current_file_function_operand"
868 (and (match_code "symbol_ref")
869 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
870 && ((SYMBOL_REF_LOCAL_P (op)
871 && ((DEFAULT_ABI != ABI_AIX
872 && DEFAULT_ABI != ABI_ELFv2)
873 || !SYMBOL_REF_EXTERNAL_P (op)))
874 || (op == XEXP (DECL_RTL (current_function_decl),
877 ;; Return 1 if this operand is a valid input for a move insn.
878 (define_predicate "input_operand"
879 (match_code "symbol_ref,const,reg,subreg,mem,
880 const_double,const_wide_int,const_vector,const_int")
882 /* Memory is always valid. */
883 if (memory_operand (op, mode))
886 /* For floating-point, easy constants are valid. */
887 if (SCALAR_FLOAT_MODE_P (mode)
888 && easy_fp_constant (op, mode))
891 /* Allow any integer constant. */
892 if (GET_MODE_CLASS (mode) == MODE_INT
893 && CONST_SCALAR_INT_P (op))
896 /* Allow easy vector constants. */
897 if (GET_CODE (op) == CONST_VECTOR
898 && easy_vector_constant (op, mode))
901 /* Do not allow invalid E500 subregs. */
902 if ((TARGET_E500_DOUBLE || TARGET_SPE)
903 && GET_CODE (op) == SUBREG
904 && invalid_e500_subreg (op, mode))
907 /* For floating-point or multi-word mode, the only remaining valid type
909 if (SCALAR_FLOAT_MODE_P (mode)
910 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
911 return register_operand (op, mode);
913 /* We don't allow moving the carry bit around. */
914 if (ca_operand (op, mode))
917 /* The only cases left are integral modes one word or smaller (we
918 do not get called for MODE_CC values). These can be in any
920 if (register_operand (op, mode))
923 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
925 if (DEFAULT_ABI == ABI_V4
926 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
927 && small_data_operand (op, Pmode))
933 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
934 (define_predicate "splat_input_operand"
935 (match_code "symbol_ref,const,reg,subreg,mem,
936 const_double,const_wide_int,const_vector,const_int")
940 if (! volatile_ok && MEM_VOLATILE_P (op))
944 else if (mode == DImode)
948 return memory_address_addr_space_p (mode, XEXP (op, 0),
949 MEM_ADDR_SPACE (op));
951 return input_operand (op, mode);
954 ;; Return true if OP is a non-immediate operand and not an invalid
955 ;; SUBREG operation on the e500.
956 (define_predicate "rs6000_nonimmediate_operand"
957 (match_code "reg,subreg,mem")
959 if ((TARGET_E500_DOUBLE || TARGET_SPE)
960 && GET_CODE (op) == SUBREG
961 && invalid_e500_subreg (op, mode))
964 return nonimmediate_operand (op, mode);
967 ;; Return true if operand is an operator used in rotate-and-mask instructions.
968 (define_predicate "rotate_mask_operator"
969 (match_code "rotate,ashift,lshiftrt"))
971 ;; Return true if operand is boolean operator.
972 (define_predicate "boolean_operator"
973 (match_code "and,ior,xor"))
975 ;; Return true if operand is OR-form of boolean operator.
976 (define_predicate "boolean_or_operator"
977 (match_code "ior,xor"))
979 ;; Return true if operand is an equality operator.
980 (define_special_predicate "equality_operator"
981 (match_code "eq,ne"))
983 ;; Return true if operand is MIN or MAX operator.
984 (define_predicate "min_max_operator"
985 (match_code "smin,smax,umin,umax"))
987 ;; Return 1 if OP is a comparison operation that is valid for a branch
988 ;; instruction. We check the opcode against the mode of the CC value.
989 ;; validate_condition_mode is an assertion.
990 (define_predicate "branch_comparison_operator"
991 (and (match_operand 0 "comparison_operator")
992 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
993 (match_test "validate_condition_mode (GET_CODE (op),
994 GET_MODE (XEXP (op, 0))),
997 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
998 ;; If we're assuming that FP operations cannot generate user-visible traps,
999 ;; then on e500 we can use the ordered-signaling instructions to implement
1000 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1001 (define_predicate "rs6000_cbranch_operator"
1002 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1003 (if_then_else (match_test "flag_trapping_math")
1004 (match_operand 0 "ordered_comparison_operator")
1005 (ior (match_operand 0 "ordered_comparison_operator")
1006 (match_code ("unlt,unle,ungt,unge"))))
1007 (match_operand 0 "comparison_operator")))
1009 ;; Return 1 if OP is an unsigned comparison operator.
1010 (define_predicate "unsigned_comparison_operator"
1011 (match_code "ltu,gtu,leu,geu"))
1013 ;; Return 1 if OP is a signed comparison operator.
1014 (define_predicate "signed_comparison_operator"
1015 (match_code "lt,gt,le,ge"))
1017 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1018 ;; it must be a positive comparison.
1019 (define_predicate "scc_comparison_operator"
1020 (and (match_operand 0 "branch_comparison_operator")
1021 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1023 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1025 (define_predicate "scc_rev_comparison_operator"
1026 (and (match_operand 0 "branch_comparison_operator")
1027 (match_code "ne,le,ge,leu,geu,ordered")))
1029 ;; Return 1 if OP is a comparison operation that is valid for a branch
1030 ;; insn, which is true if the corresponding bit in the CC register is set.
1031 (define_predicate "branch_positive_comparison_operator"
1032 (and (match_operand 0 "branch_comparison_operator")
1033 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1035 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1036 (define_predicate "load_multiple_operation"
1037 (match_code "parallel")
1039 int count = XVECLEN (op, 0);
1040 unsigned int dest_regno;
1044 /* Perform a quick check so we don't blow up below. */
1046 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1047 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1048 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1051 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1052 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1054 for (i = 1; i < count; i++)
1056 rtx elt = XVECEXP (op, 0, i);
1058 if (GET_CODE (elt) != SET
1059 || GET_CODE (SET_DEST (elt)) != REG
1060 || GET_MODE (SET_DEST (elt)) != SImode
1061 || REGNO (SET_DEST (elt)) != dest_regno + i
1062 || GET_CODE (SET_SRC (elt)) != MEM
1063 || GET_MODE (SET_SRC (elt)) != SImode
1064 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1065 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1066 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1067 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1074 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1075 ;; The second vector element is a CLOBBER.
1076 (define_predicate "store_multiple_operation"
1077 (match_code "parallel")
1079 int count = XVECLEN (op, 0) - 1;
1080 unsigned int src_regno;
1084 /* Perform a quick check so we don't blow up below. */
1086 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1087 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1088 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1091 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1092 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1094 for (i = 1; i < count; i++)
1096 rtx elt = XVECEXP (op, 0, i + 1);
1098 if (GET_CODE (elt) != SET
1099 || GET_CODE (SET_SRC (elt)) != REG
1100 || GET_MODE (SET_SRC (elt)) != SImode
1101 || REGNO (SET_SRC (elt)) != src_regno + i
1102 || GET_CODE (SET_DEST (elt)) != MEM
1103 || GET_MODE (SET_DEST (elt)) != SImode
1104 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1105 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1106 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1107 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1114 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1116 (define_predicate "save_world_operation"
1117 (match_code "parallel")
1122 int count = XVECLEN (op, 0);
1128 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1129 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1132 for (i=1; i <= 18; i++)
1134 elt = XVECEXP (op, 0, index++);
1135 if (GET_CODE (elt) != SET
1136 || GET_CODE (SET_DEST (elt)) != MEM
1137 || ! memory_operand (SET_DEST (elt), DFmode)
1138 || GET_CODE (SET_SRC (elt)) != REG
1139 || GET_MODE (SET_SRC (elt)) != DFmode)
1143 for (i=1; i <= 12; i++)
1145 elt = XVECEXP (op, 0, index++);
1146 if (GET_CODE (elt) != SET
1147 || GET_CODE (SET_DEST (elt)) != MEM
1148 || GET_CODE (SET_SRC (elt)) != REG
1149 || GET_MODE (SET_SRC (elt)) != V4SImode)
1153 for (i=1; i <= 19; i++)
1155 elt = XVECEXP (op, 0, index++);
1156 if (GET_CODE (elt) != SET
1157 || GET_CODE (SET_DEST (elt)) != MEM
1158 || ! memory_operand (SET_DEST (elt), Pmode)
1159 || GET_CODE (SET_SRC (elt)) != REG
1160 || GET_MODE (SET_SRC (elt)) != Pmode)
1164 elt = XVECEXP (op, 0, index++);
1165 if (GET_CODE (elt) != SET
1166 || GET_CODE (SET_DEST (elt)) != MEM
1167 || ! memory_operand (SET_DEST (elt), Pmode)
1168 || GET_CODE (SET_SRC (elt)) != REG
1169 || REGNO (SET_SRC (elt)) != CR2_REGNO
1170 || GET_MODE (SET_SRC (elt)) != Pmode)
1173 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1174 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1179 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1181 (define_predicate "restore_world_operation"
1182 (match_code "parallel")
1187 int count = XVECLEN (op, 0);
1193 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1194 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1195 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1196 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1199 elt = XVECEXP (op, 0, index++);
1200 if (GET_CODE (elt) != SET
1201 || GET_CODE (SET_SRC (elt)) != MEM
1202 || ! memory_operand (SET_SRC (elt), Pmode)
1203 || GET_CODE (SET_DEST (elt)) != REG
1204 || REGNO (SET_DEST (elt)) != CR2_REGNO
1205 || GET_MODE (SET_DEST (elt)) != Pmode)
1208 for (i=1; i <= 19; i++)
1210 elt = XVECEXP (op, 0, index++);
1211 if (GET_CODE (elt) != SET
1212 || GET_CODE (SET_SRC (elt)) != MEM
1213 || ! memory_operand (SET_SRC (elt), Pmode)
1214 || GET_CODE (SET_DEST (elt)) != REG
1215 || GET_MODE (SET_DEST (elt)) != Pmode)
1219 for (i=1; i <= 12; i++)
1221 elt = XVECEXP (op, 0, index++);
1222 if (GET_CODE (elt) != SET
1223 || GET_CODE (SET_SRC (elt)) != MEM
1224 || GET_CODE (SET_DEST (elt)) != REG
1225 || GET_MODE (SET_DEST (elt)) != V4SImode)
1229 for (i=1; i <= 18; i++)
1231 elt = XVECEXP (op, 0, index++);
1232 if (GET_CODE (elt) != SET
1233 || GET_CODE (SET_SRC (elt)) != MEM
1234 || ! memory_operand (SET_SRC (elt), DFmode)
1235 || GET_CODE (SET_DEST (elt)) != REG
1236 || GET_MODE (SET_DEST (elt)) != DFmode)
1240 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1241 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1242 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1243 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1244 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1249 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1250 (define_predicate "vrsave_operation"
1251 (match_code "parallel")
1253 int count = XVECLEN (op, 0);
1254 unsigned int dest_regno, src_regno;
1258 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1259 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1260 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1261 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1264 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1265 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1267 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1270 for (i = 1; i < count; i++)
1272 rtx elt = XVECEXP (op, 0, i);
1274 if (GET_CODE (elt) != CLOBBER
1275 && GET_CODE (elt) != SET)
1282 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1283 (define_predicate "mfcr_operation"
1284 (match_code "parallel")
1286 int count = XVECLEN (op, 0);
1289 /* Perform a quick check so we don't blow up below. */
1291 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1292 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1293 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1296 for (i = 0; i < count; i++)
1298 rtx exp = XVECEXP (op, 0, i);
1303 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1305 if (GET_CODE (src_reg) != REG
1306 || GET_MODE (src_reg) != CCmode
1307 || ! CR_REGNO_P (REGNO (src_reg)))
1310 if (GET_CODE (exp) != SET
1311 || GET_CODE (SET_DEST (exp)) != REG
1312 || GET_MODE (SET_DEST (exp)) != SImode
1313 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1315 unspec = SET_SRC (exp);
1316 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1318 if (GET_CODE (unspec) != UNSPEC
1319 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1320 || XVECLEN (unspec, 0) != 2
1321 || XVECEXP (unspec, 0, 0) != src_reg
1322 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1323 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1329 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1330 (define_predicate "mtcrf_operation"
1331 (match_code "parallel")
1333 int count = XVECLEN (op, 0);
1337 /* Perform a quick check so we don't blow up below. */
1339 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1340 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1341 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1343 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1345 if (GET_CODE (src_reg) != REG
1346 || GET_MODE (src_reg) != SImode
1347 || ! INT_REGNO_P (REGNO (src_reg)))
1350 for (i = 0; i < count; i++)
1352 rtx exp = XVECEXP (op, 0, i);
1356 if (GET_CODE (exp) != SET
1357 || GET_CODE (SET_DEST (exp)) != REG
1358 || GET_MODE (SET_DEST (exp)) != CCmode
1359 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1361 unspec = SET_SRC (exp);
1362 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1364 if (GET_CODE (unspec) != UNSPEC
1365 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1366 || XVECLEN (unspec, 0) != 2
1367 || XVECEXP (unspec, 0, 0) != src_reg
1368 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1369 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1375 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1376 (define_predicate "crsave_operation"
1377 (match_code "parallel")
1379 int count = XVECLEN (op, 0);
1382 for (i = 1; i < count; i++)
1384 rtx exp = XVECEXP (op, 0, i);
1386 if (GET_CODE (exp) != USE
1387 || GET_CODE (XEXP (exp, 0)) != REG
1388 || GET_MODE (XEXP (exp, 0)) != CCmode
1389 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1395 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1396 (define_predicate "lmw_operation"
1397 (match_code "parallel")
1399 int count = XVECLEN (op, 0);
1400 unsigned int dest_regno;
1402 unsigned int base_regno;
1403 HOST_WIDE_INT offset;
1406 /* Perform a quick check so we don't blow up below. */
1408 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1409 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1410 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1413 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1414 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1417 || count != 32 - (int) dest_regno)
1420 if (legitimate_indirect_address_p (src_addr, 0))
1423 base_regno = REGNO (src_addr);
1424 if (base_regno == 0)
1427 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1429 offset = INTVAL (XEXP (src_addr, 1));
1430 base_regno = REGNO (XEXP (src_addr, 0));
1435 for (i = 0; i < count; i++)
1437 rtx elt = XVECEXP (op, 0, i);
1440 HOST_WIDE_INT newoffset;
1442 if (GET_CODE (elt) != SET
1443 || GET_CODE (SET_DEST (elt)) != REG
1444 || GET_MODE (SET_DEST (elt)) != SImode
1445 || REGNO (SET_DEST (elt)) != dest_regno + i
1446 || GET_CODE (SET_SRC (elt)) != MEM
1447 || GET_MODE (SET_SRC (elt)) != SImode)
1449 newaddr = XEXP (SET_SRC (elt), 0);
1450 if (legitimate_indirect_address_p (newaddr, 0))
1455 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1457 addr_reg = XEXP (newaddr, 0);
1458 newoffset = INTVAL (XEXP (newaddr, 1));
1462 if (REGNO (addr_reg) != base_regno
1463 || newoffset != offset + 4 * i)
1470 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1471 (define_predicate "stmw_operation"
1472 (match_code "parallel")
1474 int count = XVECLEN (op, 0);
1475 unsigned int src_regno;
1477 unsigned int base_regno;
1478 HOST_WIDE_INT offset;
1481 /* Perform a quick check so we don't blow up below. */
1483 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1484 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1485 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1488 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1489 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1492 || count != 32 - (int) src_regno)
1495 if (legitimate_indirect_address_p (dest_addr, 0))
1498 base_regno = REGNO (dest_addr);
1499 if (base_regno == 0)
1502 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1504 offset = INTVAL (XEXP (dest_addr, 1));
1505 base_regno = REGNO (XEXP (dest_addr, 0));
1510 for (i = 0; i < count; i++)
1512 rtx elt = XVECEXP (op, 0, i);
1515 HOST_WIDE_INT newoffset;
1517 if (GET_CODE (elt) != SET
1518 || GET_CODE (SET_SRC (elt)) != REG
1519 || GET_MODE (SET_SRC (elt)) != SImode
1520 || REGNO (SET_SRC (elt)) != src_regno + i
1521 || GET_CODE (SET_DEST (elt)) != MEM
1522 || GET_MODE (SET_DEST (elt)) != SImode)
1524 newaddr = XEXP (SET_DEST (elt), 0);
1525 if (legitimate_indirect_address_p (newaddr, 0))
1530 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1532 addr_reg = XEXP (newaddr, 0);
1533 newoffset = INTVAL (XEXP (newaddr, 1));
1537 if (REGNO (addr_reg) != base_regno
1538 || newoffset != offset + 4 * i)
1545 ;; Return 1 if OP is a stack tie operand.
1546 (define_predicate "tie_operand"
1547 (match_code "parallel")
1549 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1550 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1551 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1552 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1555 ;; Match a small code model toc reference (or medium and large
1556 ;; model toc references before reload).
1557 (define_predicate "small_toc_ref"
1558 (match_code "unspec,plus")
1560 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1563 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1566 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1567 ;; GPR registers on power8.
1568 (define_predicate "fusion_gpr_addis"
1569 (match_code "const_int,high,plus")
1571 HOST_WIDE_INT value;
1574 if (GET_CODE (op) == HIGH)
1577 if (CONST_INT_P (op))
1580 else if (GET_CODE (op) == PLUS
1581 && base_reg_operand (XEXP (op, 0), Pmode)
1582 && CONST_INT_P (XEXP (op, 1)))
1583 int_const = XEXP (op, 1);
1588 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1589 value are all 1's or 0's. */
1590 value = INTVAL (int_const);
1591 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1594 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1597 return (IN_RANGE (value >> 16, -32, 31));
1600 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1601 ;; and loads to GPR registers on power8.
1602 (define_predicate "fusion_gpr_mem_load"
1603 (match_code "mem,sign_extend,zero_extend")
1605 rtx addr, base, offset;
1607 /* Handle sign/zero extend. */
1608 if (GET_CODE (op) == ZERO_EXTEND
1609 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1612 mode = GET_MODE (op);
1626 if (!TARGET_POWERPC64)
1634 addr = XEXP (op, 0);
1635 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1638 base = XEXP (addr, 0);
1639 if (!base_reg_operand (base, GET_MODE (base)))
1642 offset = XEXP (addr, 1);
1644 if (GET_CODE (addr) == PLUS)
1645 return satisfies_constraint_I (offset);
1647 else if (GET_CODE (addr) == LO_SUM)
1649 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1650 return small_toc_ref (offset, GET_MODE (offset));
1652 else if (TARGET_ELF && !TARGET_POWERPC64)
1653 return CONSTANT_P (offset);
1659 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1660 ;; memory field with both the addis and the memory offset. Sign extension
1661 ;; is not handled here, since lha and lwa are not fused.
1662 (define_predicate "fusion_gpr_mem_combo"
1663 (match_code "mem,zero_extend")
1665 rtx addr, base, offset;
1667 /* Handle zero extend. */
1668 if (GET_CODE (op) == ZERO_EXTEND)
1671 mode = GET_MODE (op);
1685 if (!TARGET_POWERPC64)
1693 addr = XEXP (op, 0);
1694 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1697 base = XEXP (addr, 0);
1698 if (!fusion_gpr_addis (base, GET_MODE (base)))
1701 offset = XEXP (addr, 1);
1702 if (GET_CODE (addr) == PLUS)
1703 return satisfies_constraint_I (offset);
1705 else if (GET_CODE (addr) == LO_SUM)
1707 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1708 return small_toc_ref (offset, GET_MODE (offset));
1710 else if (TARGET_ELF && !TARGET_POWERPC64)
1711 return CONSTANT_P (offset);