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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
122 \f
123 /* First, some functions that were used before GCC got a control flow graph.
124 These functions are now only used here in reorg.c, and have therefore
125 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
127 /* Return the last label to mark the same position as LABEL. Return LABEL
128 itself if it is null or any return rtx. */
130 static rtx
132 {
145 }
147 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
148 and REG_CC_USER notes so we can find it. */
150 static void
152 {
160 }
161 \f
162 /* Insns which have delay slots that have not yet been filled. */
167 /* Define macros to refer to the first and last slot containing unfilled
168 insns. These are used because the list may move and its address
169 should be recomputed at each use. */
171 #define unfilled_slots_base \
172 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
174 #define unfilled_slots_next \
175 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
177 /* Points to the label before the end of the function, or before a
178 return insn. */
180 /* Likewise for a simple_return. */
183 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
184 not always monotonically increase. */
187 /* Highest valid index in `uid_to_ruid'. */
215 rtx *);
237 \f
238 /* A wrapper around next_active_insn which takes care to return ret_rtx
239 unchanged. */
241 static rtx
243 {
247 }
248 \f
249 /* Return true iff INSN is a simplejump, or any kind of return insn. */
251 static bool
253 {
257 }
258 \f
259 /* Return TRUE if this insn should stop the search for insn to fill delay
260 slots. LABELS_P indicates that labels should terminate the search.
261 In all cases, jumps terminate the search. */
263 static int
265 {
269 /* If the insn can throw an exception that is caught within the function,
270 it may effectively perform a jump from the viewpoint of the function.
271 Therefore act like for a jump. */
276 {
289 /* OK unless it contains a delay slot or is an `asm' insn of some type.
290 We don't know anything about these. */
297 }
298 }
299 \f
300 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
301 resource set contains a volatile memory reference. Otherwise, return FALSE. */
303 static int
305 {
311 }
313 /* Return TRUE if any resource marked in RES, a `struct resources', is
314 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
315 routine is using those resources.
317 We compute this by computing all the resources referenced by INSN and
318 seeing if this conflicts with RES. It might be faster to directly check
319 ourselves, and this is the way it used to work, but it means duplicating
320 a large block of complex code. */
322 static int
325 {
331 }
333 /* Return TRUE if INSN modifies resources that are marked in RES.
334 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
335 included. CC0 is only modified if it is explicitly set; see comments
336 in front of mark_set_resources for details. */
338 static int
341 {
346 (include_delayed_effects
347 ? MARK_SRC_DEST_CALL
350 }
351 \f
352 /* Find a label at the end of the function or before a RETURN. If there
353 is none, try to make one. If that fails, returns 0.
355 The property of such a label is that it is placed just before the
356 epilogue or a bare RETURN insn, so that another bare RETURN can be
357 turned into a jump to the label unconditionally. In particular, the
358 label cannot be placed before a RETURN insn with a filled delay slot.
360 ??? There may be a problem with the current implementation. Suppose
361 we start with a bare RETURN insn and call find_end_label. It may set
362 function_return_label just before the RETURN. Suppose the machinery
363 is able to fill the delay slot of the RETURN insn afterwards. Then
364 function_return_label is no longer valid according to the property
365 described above and find_end_label will still return it unmodified.
366 Note that this is probably mitigated by the following observation:
367 once function_return_label is made, it is very likely the target of
368 a jump, so filling the delay slot of the RETURN will be much more
369 difficult.
370 KIND is either simple_return_rtx or ret_rtx, indicating which type of
371 return we're looking for. */
375 {
381 else
382 {
385 }
387 /* If we found one previously, return it. */
391 /* Otherwise, see if there is a label at the end of the function. If there
392 is, it must be that RETURN insns aren't needed, so that is our return
393 label and we don't have to do anything else. */
402 /* When a target threads its epilogue we might already have a
403 suitable return insn. If so put a label before it for the
404 function_return_label. */
408 {
413 /* Put the label before any USE insns that may precede the RETURN
414 insn. */
420 }
424 else
425 {
428 /* If the basic block reorder pass moves the return insn to
429 some other place try to locate it again and put our
430 function_return_label there. */
434 {
437 /* Put the label before any USE insns that may precede the
438 RETURN insn. */
443 }
444 else
445 {
447 /* The RETURN insn has its delay slot filled so we cannot
448 emit the label just before it. Since we already have
449 an epilogue and cannot emit a new RETURN, we cannot
450 emit the label at all. */
453 /* Otherwise, make a new label and emit a RETURN and BARRIER,
454 if needed. */
457 {
458 /* The return we make may have delay slots too. */
465 }
466 }
468 }
470 /* Show one additional use for this label so it won't go away until
471 we are done. */
475 }
476 \f
477 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
478 the pattern of INSN with the SEQUENCE.
480 Returns the insn containing the SEQUENCE that replaces INSN. */
484 {
485 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
490 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
491 not have a location, but one of the delayed insns does, we pick up a
492 location from there later. */
495 /* Unlink INSN from the insn chain, so that we can put it into
496 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
501 /* Build our SEQUENCE and rebuild the insn chain. */
508 {
512 /* Show that this copy of the insn isn't deleted. */
515 /* Unlink insn from its original place, and re-emit it into
516 the sequence. */
520 /* SPARC assembler, for instance, emit warning when debug info is output
521 into the delay slot. */
527 {
530 {
532 /* Remove any REG_DEAD notes because we can't rely on them now
533 that the insn has been moved. */
539 /* Keep the label reference count up to date. */
546 }
547 }
548 }
551 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
555 }
557 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
558 be in the order in which the insns are to be executed. */
560 static void
562 {
563 /* If INSN has its block number recorded, clear it since we may
564 be moving the insn to a new block. */
567 }
568 \f
569 /* Delete INSN from the delay slot of the insn that it is in, which may
570 produce an insn with no delay slots. Return the new insn. */
574 {
580 /* We first must find the insn containing the SEQUENCE with INSN in its
581 delay slot. Do this by finding an insn, TRIAL, where
582 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
587 ;
595 /* Create a delay list consisting of all the insns other than the one
596 we are deleting (unless we were the only one). */
603 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
604 list, and rebuild the delay list if non-empty. */
610 /* If there was a barrier after the old SEQUENCE, remit it. */
614 /* If there are any delay insns, remit them. Otherwise clear the
615 annul flag. */
623 /* Show we need to fill this insn again. */
627 }
628 \f
629 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
630 the insn that sets CC0 for it and delete it too. */
632 static void
634 {
635 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
636 delete the insn that sets the condition code, but it is hard to find it.
637 Since this case is rare anyway, don't bother trying; there would likely
638 be other insns that became dead anyway, which we wouldn't know to
639 delete. */
642 {
645 /* If a reg-note was found, it points to an insn to set CC0. This
646 insn is in the delay list of some other insn. So delete it from
647 the delay list it was in. */
649 {
653 }
654 else
655 {
656 /* The insn setting CC0 is our previous insn, but it may be in
657 a delay slot. It will be the last insn in the delay slot, if
658 it is. */
667 else
669 }
670 }
673 }
674 \f
675 /* Counters for delay-slot filling. */
677 #define NUM_REORG_FUNCTIONS 2
678 #define MAX_DELAY_HISTOGRAM 3
679 #define MAX_REORG_PASSES 2
687 static void
689 {
694 }
695 \f
696 /* Optimize the following cases:
698 1. When a conditional branch skips over only one instruction,
699 use an annulling branch and put that insn in the delay slot.
700 Use either a branch that annuls when the condition if true or
701 invert the test with a branch that annuls when the condition is
702 false. This saves insns, since otherwise we must copy an insn
703 from the L1 target.
705 (orig) (skip) (otherwise)
706 Bcc.n L1 Bcc',a L1 Bcc,a L1'
707 insn insn insn2
708 L1: L1: L1:
709 insn2 insn2 insn2
710 insn3 insn3 L1':
711 insn3
713 2. When a conditional branch skips over only one instruction,
714 and after that, it unconditionally branches somewhere else,
715 perform the similar optimization. This saves executing the
716 second branch in the case where the inverted condition is true.
718 Bcc.n L1 Bcc',a L2
719 insn insn
720 L1: L1:
721 Bra L2 Bra L2
723 INSN is a JUMP_INSN.
725 This should be expanded to skip over N insns, where N is the number
726 of delay slots required. */
728 static void
730 {
747 /* There are two cases where we are just executing one insn (we assume
748 here that a branch requires only one insn; this should be generalized
749 at some point): Where the branch goes around a single insn or where
750 we have one insn followed by a branch to the same label we branch to.
751 In both of these cases, inverting the jump and annulling the delay
752 slot give the same effect in fewer insns. */
757 {
759 {
764 }
771 /* Also, if we are targeting an unconditional
772 branch, thread our jump to the target of that branch. Don't
773 change this into a RETURN here, because it may not accept what
774 we have in the delay slot. We'll fix this up later. */
776 {
782 {
783 /* Recompute the flags based on TARGET_LABEL since threading
784 the jump to TARGET_LABEL may change the direction of the
785 jump (which may change the circumstances in which the
786 delay slot is nullified). */
790 }
791 }
794 }
795 }
796 \f
797 /* Encode and return branch direction and prediction information for
798 INSN assuming it will jump to LABEL.
800 Non conditional branches return no direction information and
801 are predicted as very likely taken. */
803 static int
805 {
808 /* get_jump_flags can be passed any insn with delay slots, these may
809 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
810 direction information, and only if they are conditional jumps.
812 If LABEL is a return, then there is no way to determine the branch
813 direction. */
819 flags
822 /* No valid direction information. */
823 else
827 }
829 /* Return truth value of the statement that this branch
830 is mostly taken. If we think that the branch is extremely likely
831 to be taken, we return 2. If the branch is slightly more likely to be
832 taken, return 1. If the branch is slightly less likely to be taken,
833 return 0 and if the branch is highly unlikely to be taken, return -1. */
835 static int
837 {
838 /* If branch probabilities are available, then use that number since it
839 always gives a correct answer. */
842 {
852 else
854 }
856 /* If there is no note, assume branches are not taken.
857 This should be rare. */
859 }
861 /* Return the condition under which INSN will branch to TARGET. If TARGET
862 is zero, return the condition under which INSN will return. If INSN is
863 an unconditional branch, return const_true_rtx. If INSN isn't a simple
864 type of jump, or it doesn't go to TARGET, return 0. */
866 static rtx
868 {
870 rtx src;
897 {
904 }
907 }
909 /* Return nonzero if CONDITION is more strict than the condition of
910 INSN, i.e., if INSN will always branch if CONDITION is true. */
912 static int
914 {
933 }
935 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
936 any insns already in the delay slot of JUMP. */
938 static int
940 {
944 /* Make sure all the delay slots of this jump would still
945 be valid after threading the jump. If they are still
946 valid, then return nonzero. */
951 #if ANNUL_IFFALSE_SLOTS
955 #endif
956 #if ANNUL_IFTRUE_SLOTS
960 #endif
965 }
967 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
968 any insns we wish to place in the delay slot of JUMP. */
970 static int
973 {
974 /* Make sure all the insns in DELAY_LIST would still be
975 valid after threading the jump. If they are still
976 valid, then return nonzero. */
983 #if ANNUL_IFFALSE_SLOTS
987 #endif
988 #if ANNUL_IFTRUE_SLOTS
992 #endif
997 }
999 /* DELAY_LIST is a list of insns that have already been placed into delay
1000 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
1001 If not, return 0; otherwise return 1. */
1003 static int
1006 {
1015 }
1016 \f
1017 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1018 the condition tested by INSN is CONDITION and the resources shown in
1019 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1020 from SEQ's delay list, in addition to whatever insns it may execute
1021 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1022 needed while searching for delay slot insns. Return the concatenated
1023 delay list if possible, otherwise, return 0.
1025 SLOTS_TO_FILL is the total number of slots required by INSN, and
1026 PSLOTS_FILLED points to the number filled so far (also the number of
1027 insns in DELAY_LIST). It is updated with the number that have been
1028 filled from the SEQUENCE, if any.
1030 PANNUL_P points to a nonzero value if we already know that we need
1031 to annul INSN. If this routine determines that annulling is needed,
1032 it may set that value nonzero.
1034 PNEW_THREAD points to a location that is to receive the place at which
1035 execution should continue. */
1037 static void
1044 {
1054 /* We can't do anything if there are more delay slots in SEQ than we
1055 can handle, or if we don't know that it will be a taken branch.
1056 We know that it will be a taken branch if it is either an unconditional
1057 branch or a conditional branch with a stricter branch condition.
1059 Also, exit if the branch has more than one set, since then it is computing
1060 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1061 ??? It may be possible to move other sets into INSN in addition to
1062 moving the instructions in the delay slots.
1064 We can not steal the delay list if one of the instructions in the
1065 current delay_list modifies the condition codes and the jump in the
1066 sequence is a conditional jump. We can not do this because we can
1067 not change the direction of the jump because the condition codes
1068 will effect the direction of the jump in the sequence. */
1074 {
1078 }
1085 /* On some targets, branches with delay slots can have a limited
1086 displacement. Give the back end a chance to tell us we can't do
1087 this. */
1093 {
1100 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1101 delay list. */
1103 /* If TRIAL is from the fallthrough code of an annulled branch insn
1104 in SEQ, we cannot use it. */
1109 /* If this insn was already done (usually in a previous delay slot),
1110 pretend we put it in our delay slot. */
1115 /* We will end up re-vectoring this branch, so compute flags
1116 based on jumping to the new label. */
1130 {
1132 {
1133 /* Frame related instructions cannot go into annulled delay
1134 slots, it messes up the dwarf info. */
1138 }
1142 total_slots_filled++;
1146 }
1147 else
1149 }
1151 /* Record the effect of the instructions that were redundant and which
1152 we therefore decided not to copy. */
1157 /* Show the place to which we will be branching. */
1160 /* Add any new insns to the delay list and update the count of the
1161 number of slots filled. */
1169 }
1170 \f
1171 /* Similar to steal_delay_list_from_target except that SEQ is on the
1172 fallthrough path of INSN. Here we only do something if the delay insn
1173 of SEQ is an unconditional branch. In that case we steal its delay slot
1174 for INSN since unconditional branches are much easier to fill. */
1176 static void
1185 {
1193 /* We can't do anything if SEQ's delay insn isn't an
1194 unconditional branch. */
1200 {
1203 /* If TRIAL sets CC0, stealing it will move it too far from the use
1204 of CC0. */
1212 /* If this insn was already done, we don't need it. */
1214 {
1218 }
1228 {
1236 }
1237 else
1239 }
1243 }
1244 \f
1245 /* Try merging insns starting at THREAD which match exactly the insns in
1246 INSN's delay list.
1248 If all insns were matched and the insn was previously annulling, the
1249 annul bit will be cleared.
1251 For each insn that is merged, if the branch is or will be non-annulling,
1252 we delete the merged insn. */
1254 static void
1256 {
1272 /* If this is not an annulling branch, take into account anything needed in
1273 INSN's delay slot. This prevents two increments from being incorrectly
1274 folded into one. If we are annulling, this would be the correct
1275 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1276 will essentially disable this optimization. This method is somewhat of
1277 a kludge, but I don't see a better way.) */
1285 {
1291 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1297 /* We can't share an insn that sets cc0. */
1303 /* Update next_trial, in case try_split succeeded. */
1305 /* Likewise THREAD. */
1308 /* Have to test this condition if annul condition is different
1309 from (and less restrictive than) non-annulling one. */
1311 {
1314 {
1321 }
1322 else
1329 }
1333 }
1335 /* See if we stopped on a filled insn. If we did, try to see if its
1336 delay slots match. */
1342 {
1346 /* Account for resources set/needed by the filled insn. */
1351 {
1355 /* Account for resources set by the insn following NEXT_TO_MATCH
1356 inside INSN's delay list. */
1360 /* Account for resources set by the insn before DTRIAL and inside
1361 TRIAL's delay list. */
1370 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1371 resource modified between them (only dtrial is checked because
1372 next_to_match and dtrial shall to be equal in order to hit
1373 this line) */
1376 {
1378 {
1386 }
1387 else
1395 }
1396 else
1397 {
1398 /* Keep track of the set/referenced resources for the delay
1399 slots of any trial insns we encounter. */
1402 }
1403 }
1404 }
1406 /* If all insns in the delay slot have been matched and we were previously
1407 annulling the branch, we need not any more. In that case delete all the
1408 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1409 the delay list so that we know that it isn't only being used at the
1410 target. */
1412 {
1416 {
1421 }
1422 else
1423 {
1426 }
1432 }
1433 }
1434 \f
1435 /* See if INSN is redundant with an insn in front of TARGET. Often this
1436 is called when INSN is a candidate for a delay slot of TARGET.
1437 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1438 of INSN. Often INSN will be redundant with an insn in a delay slot of
1439 some previous insn. This happens when we have a series of branches to the
1440 same label; in that case the first insn at the target might want to go
1441 into each of the delay slots.
1443 If we are not careful, this routine can take up a significant fraction
1444 of the total compilation time (4%), but only wins rarely. Hence we
1445 speed this routine up by making two passes. The first pass goes back
1446 until it hits a label and sees if it finds an insn with an identical
1447 pattern. Only in this (relatively rare) event does it check for
1448 data conflicts.
1450 We do not split insns we encounter. This could cause us not to find a
1451 redundant insn, but the cost of splitting seems greater than the possible
1452 gain in rare cases. */
1456 {
1460 rtx pat;
1465 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1466 are allowed to not actually assign to such a register. */
1470 /* Scan backwards looking for a match. */
1475 {
1476 /* (use (insn))s can come immediately after a barrier if the
1477 label that used to precede them has been deleted as dead.
1478 See delete_related_insns. */
1491 {
1492 /* Stop for a CALL and its delay slots because it is difficult to
1493 track its resource needs correctly. */
1497 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1498 slots because it is difficult to track its resource needs
1499 correctly. */
1507 /* See if any of the insns in the delay slot match, updating
1508 resource requirements as we go. */
1515 /* If found a match, exit this loop early. */
1518 }
1523 }
1525 /* If we didn't find an insn that matches, return 0. */
1529 /* See what resources this insn sets and needs. If they overlap, or
1530 if this insn references CC0, it can't be redundant. */
1537 /* If TARGET is a SEQUENCE, get the main insn. */
1543 /* The insn requiring the delay may not set anything needed or set by
1544 INSN. */
1549 /* Insns we pass may not set either NEEDED or SET, so merge them for
1550 simpler tests. */
1554 /* This insn isn't redundant if it conflicts with an insn that either is
1555 or will be in a delay slot of TARGET. */
1569 /* Scan backwards until we reach a label or an insn that uses something
1570 INSN sets or sets something insn uses or sets. */
1576 {
1586 {
1590 /* If this is a CALL_INSN and its delay slots, it is hard to track
1591 the resource needs properly, so give up. */
1595 /* If this is an INSN or JUMP_INSN with delayed effects, it
1596 is hard to track the resource needs properly, so give up. */
1607 /* See if any of the insns in the delay slot match, updating
1608 resource requirements as we go. */
1610 {
1613 /* If an insn will be annulled if the branch is false, it isn't
1614 considered as a possible duplicate insn. */
1617 {
1618 /* Show that this insn will be used in the sequel. */
1621 }
1623 /* Unless this is an annulled insn from the target of a branch,
1624 we must stop if it sets anything needed or set by INSN. */
1628 }
1630 /* If the insn requiring the delay slot conflicts with INSN, we
1631 must stop. */
1634 }
1635 else
1636 {
1637 /* See if TRIAL is the same as INSN. */
1642 /* Can't go any further if TRIAL conflicts with INSN. */
1645 }
1646 }
1649 }
1650 \f
1651 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1652 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1653 is nonzero, we are allowed to fall into this thread; otherwise, we are
1654 not.
1656 If LABEL is used more than one or we pass a label other than LABEL before
1657 finding an active insn, we do not own this thread. */
1659 static int
1661 {
1665 /* We don't own the function end. */
1669 /* We have a non-NULL insn. */
1672 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1683 /* Ensure that we reach a BARRIER before any insn or label. */
1695 }
1696 \f
1697 /* Called when INSN is being moved from a location near the target of a jump.
1698 We leave a marker of the form (use (INSN)) immediately in front of WHERE
1699 for mark_target_live_regs. These markers will be deleted at the end.
1701 We used to try to update the live status of registers if WHERE is at
1702 the start of a basic block, but that can't work since we may remove a
1703 BARRIER in relax_delay_slots. */
1705 static void
1707 {
1710 /* INSN might be making a value live in a block where it didn't use to
1711 be. So recompute liveness information for this block. */
1713 }
1715 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1716 the basic block containing the jump. */
1718 static int
1720 {
1723 }
1725 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1726 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1727 that reference values used in INSN. If we find one, then we move the
1728 REG_DEAD note to INSN.
1730 This is needed to handle the case where a later insn (after INSN) has a
1731 REG_DEAD note for a register used by INSN, and this later insn subsequently
1732 gets moved before a CODE_LABEL because it is a redundant insn. In this
1733 case, mark_target_live_regs may be confused into thinking the register
1734 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1736 static void
1738 {
1745 {
1753 {
1754 /* Move the REG_DEAD note from P to INSN. */
1758 }
1759 }
1760 }
1762 /* Called when an insn redundant with start_insn is deleted. If there
1763 is a REG_DEAD note for the target of start_insn between start_insn
1764 and stop_insn, then the REG_DEAD note needs to be deleted since the
1765 value no longer dies there.
1767 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1768 confused into thinking the register is dead. */
1770 static void
1772 {
1779 {
1787 {
1790 }
1791 }
1792 }
1794 /* Delete any REG_UNUSED notes that exist on INSN but not on REDUNDANT_INSN.
1796 This handles the case of udivmodXi4 instructions which optimize their
1797 output depending on whether any REG_UNUSED notes are present.
1798 we must make sure that INSN calculates as many results as REDUNDANT_INSN
1799 does. */
1801 static void
1803 {
1807 {
1817 }
1818 }
1819 \f
1822 /* Return the label before INSN, or put a new label there. If SIBLING is
1823 non-zero, it is another label associated with the new label (if any),
1824 typically the former target of the jump that will be redirected to
1825 the new label. */
1829 {
1832 /* Find an existing label at this point
1833 or make a new one if there is none. */
1837 {
1844 {
1847 }
1848 }
1850 }
1852 /* Scan a function looking for insns that need a delay slot and find insns to
1853 put into the delay slot.
1855 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1856 as calls). We do these first since we don't want jump insns (that are
1857 easier to fill) to get the only insns that could be used for non-jump insns.
1858 When it is zero, only try to fill JUMP_INSNs.
1860 When slots are filled in this manner, the insns (including the
1861 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1862 it is possible to tell whether a delay slot has really been filled
1863 or not. `final' knows how to deal with this, by communicating
1864 through FINAL_SEQUENCE. */
1866 static void
1868 {
1870 rtx pat;
1878 {
1880 /* Get the next insn to fill. If it has already had any slots assigned,
1881 we can't do anything with it. Maybe we'll improve this later. */
1892 /* It may have been that this insn used to need delay slots, but
1893 now doesn't; ignore in that case. This can happen, for example,
1894 on the HP PA RISC, where the number of delay slots depends on
1895 what insns are nearby. */
1898 /* Some machine description have defined instructions to have
1899 delay slots only in certain circumstances which may depend on
1900 nearby insns (which change due to reorg's actions).
1902 For example, the PA port normally has delay slots for unconditional
1903 jumps.
1905 However, the PA port claims such jumps do not have a delay slot
1906 if they are immediate successors of certain CALL_INSNs. This
1907 allows the port to favor filling the delay slot of the call with
1908 the unconditional jump. */
1912 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1913 says how many. After initialization, first try optimizing
1915 call _foo call _foo
1916 nop add %o7,.-L1,%o7
1917 b,a L1
1918 nop
1920 If this case applies, the delay slot of the call is filled with
1921 the unconditional jump. This is done first to avoid having the
1922 delay slot of the call filled in the backward scan. Also, since
1923 the unconditional jump is likely to also have a delay slot, that
1924 insn must exist when it is subsequently scanned.
1926 This is tried on each insn with delay slots as some machines
1927 have insns which perform calls, but are not represented as
1928 CALL_INSNs. */
1935 else
1944 {
1946 slots_filled++;
1949 /* TRIAL may have had its delay slot filled, then unfilled. When
1950 the delay slot is unfilled, TRIAL is placed back on the unfilled
1951 slots obstack. Unfortunately, it is placed on the end of the
1952 obstack, not in its original location. Therefore, we must search
1953 from entry i + 1 to the end of the unfilled slots obstack to
1954 try and find TRIAL. */
1957 tmp++;
1959 /* Remove the unconditional jump from consideration for delay slot
1960 filling and unthread it. */
1963 {
1970 }
1971 }
1973 /* Now, scan backwards from the insn to search for a potential
1974 delay-slot candidate. Stop searching when a label or jump is hit.
1976 For each candidate, if it is to go into the delay slot (moved
1977 forward in execution sequence), it must not need or set any resources
1978 that were set by later insns and must not set any resources that
1979 are needed for those insns.
1981 The delay slot insn itself sets resources unless it is a call
1982 (in which case the called routine, not the insn itself, is doing
1983 the setting). */
1986 {
1987 /* If the flags register is dead after the insn, then we want to be
1988 able to accept a candidate that clobbers it. For this purpose,
1989 we need to filter the flags register during life analysis, so
1990 that it doesn't create RAW and WAW dependencies, while still
1991 creating the necessary WAR dependencies. */
1992 bool filter_flags
2001 {
2004 }
2009 {
2012 /* This must be an INSN or CALL_INSN. */
2015 /* Stand-alone USE and CLOBBER are just for flow. */
2019 /* Check for resource conflict first, to avoid unnecessary
2020 splitting. */
2026 /* Can't separate set of cc0 from its use. */
2029 {
2033 {
2034 /* In this case, we are searching backward, so if we
2035 find insns to put on the delay list, we want
2036 to put them at the head, rather than the
2037 tail, of the list. */
2046 }
2047 }
2051 {
2053 /* If the flags register is set, then it doesn't create RAW
2054 dependencies any longer and it also doesn't create WAW
2055 dependencies since it's dead after the original insn. */
2057 {
2060 }
2061 }
2063 }
2064 }
2066 /* If all needed slots haven't been filled, we come here. */
2068 /* Try to optimize case of jumping around a single insn. */
2075 {
2079 }
2081 /* Try to get insns from beyond the insn needing the delay slot.
2082 These insns can neither set or reference resources set in insns being
2083 skipped, cannot set resources in the insn being skipped, and, if this
2084 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2085 call might not return).
2087 There used to be code which continued past the target label if
2088 we saw all uses of the target label. This code did not work,
2089 because it failed to account for some instructions which were
2090 both annulled and marked as from the target. This can happen as a
2091 result of optimize_skip. Since this code was redundant with
2092 fill_eager_delay_slots anyways, it was just deleted. */
2095 /* If this instruction could throw an exception which is
2096 caught in the same function, then it's not safe to fill
2097 the delay slot with an instruction from beyond this
2098 point. For example, consider:
2100 int i = 2;
2102 try {
2103 f();
2104 i = 3;
2105 } catch (...) {}
2107 return i;
2109 Even though `i' is a local variable, we must be sure not
2110 to put `i = 3' in the delay slot if `f' might throw an
2111 exception.
2113 Presumably, we should also check to see if we could get
2114 back to this function via `setjmp'. */
2117 {
2131 {
2134 /* This must be an INSN or CALL_INSN. */
2137 /* Stand-alone USE and CLOBBER are just for flow. */
2141 /* If this already has filled delay slots, get the insn needing
2142 the delay slots. */
2145 else
2148 /* Stop our search when seeing a jump. */
2152 /* See if we have a resource problem before we try to split. */
2162 {
2172 }
2177 /* Ensure we don't put insns between the setting of cc and the
2178 comparison by moving a setting of cc into an earlier delay
2179 slot since these insns could clobber the condition code. */
2182 /* If this is a call, we might not get here. */
2185 }
2187 /* If there are slots left to fill and our search was stopped by an
2188 unconditional branch, try the insn at the branch target. We can
2189 redirect the branch if it works.
2191 Don't do this if the insn at the branch target is a branch. */
2193 && trial
2208 {
2209 /* See comment in relax_delay_slots about necessity of using
2210 next_real_insn here. */
2215 else
2219 {
2222 slots_filled++;
2224 new_label);
2225 }
2226 }
2227 }
2229 /* If this is an unconditional jump, then try to get insns from the
2230 target of the jump. */
2249 }
2250 }
2251 \f
2252 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2253 return the ultimate label reached by any such chain of jumps.
2254 Return a suitable return rtx if the chain ultimately leads to a
2255 return instruction.
2256 If LABEL is not followed by a jump, return LABEL.
2257 If the chain loops or we can't find end, return LABEL,
2258 since that tells caller to avoid changing the insn.
2259 If the returned label is obtained by following a crossing jump,
2260 set *CROSSING to true, otherwise set it to false. */
2262 static rtx
2264 {
2284 depth++)
2285 {
2288 /* If we have found a cycle, make the insn jump to itself. */
2292 /* Cannot follow returns and cannot look through tablejumps. */
2306 }
2310 }
2312 /* Try to find insns to place in delay slots.
2314 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2315 or is an unconditional branch if CONDITION is const_true_rtx.
2316 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2318 THREAD is a flow-of-control, either the insns to be executed if the
2319 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2321 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2322 to see if any potential delay slot insns set things needed there.
2324 LIKELY is nonzero if it is extremely likely that the branch will be
2325 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2326 end of a loop back up to the top.
2328 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
2329 thread. I.e., it is the fallthrough code of our jump or the target of the
2330 jump when we are the only jump going there.
2332 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2333 case, we can only take insns from the head of the thread for our delay
2334 slot. We then adjust the jump to point after the insns we have taken. */
2336 static void
2341 {
2342 rtx new_thread;
2349 /* Validate our arguments. */
2355 /* If our thread is the end of subroutine, we can't get any delay
2356 insns from that. */
2362 /* If this is an unconditional branch, nothing is needed at the
2363 opposite thread. Otherwise, compute what is needed there. */
2366 else
2369 /* If the insn at THREAD can be split, do it here to avoid having to
2370 update THREAD and NEW_THREAD if it is done in the loop below. Also
2371 initialize NEW_THREAD. */
2375 /* Scan insns at THREAD. We are looking for an insn that can be removed
2376 from THREAD (it neither sets nor references resources that were set
2377 ahead of it and it doesn't set anything needs by the insns ahead of
2378 it) and that either can be placed in an annulling insn or aren't
2379 needed at OPPOSITE_THREAD. */
2384 /* If we do not own this thread, we must stop as soon as we find
2385 something that we can't put in a delay slot, since all we can do
2386 is branch into THREAD at a later point. Therefore, labels stop
2387 the search if this is not the `true' thread. */
2392 {
2395 /* If we have passed a label, we no longer own this thread. */
2397 {
2400 }
2406 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2407 don't separate or copy insns that set and use CC0. */
2414 {
2417 /* If TRIAL is redundant with some insn before INSN, we don't
2418 actually need to add it to the delay list; we can merely pretend
2419 we did. */
2421 {
2424 {
2427 {
2431 }
2434 }
2435 else
2436 {
2439 }
2442 }
2444 /* There are two ways we can win: If TRIAL doesn't set anything
2445 needed at the opposite thread and can't trap, or if it can
2446 go into an annulled delay slot. But we want neither to copy
2447 nor to speculate frame-related insns. */
2454 {
2464 }
2468 {
2481 {
2485 winner:
2490 /* If we own this thread, delete the insn. If this is the
2491 destination of a branch, show that a basic block status
2492 may have been updated. In any case, mark the new
2493 starting point of this thread. */
2495 {
2496 rtx note;
2500 {
2504 }
2506 /* We are moving this insn, not deleting it. We must
2507 temporarily increment the use count on any referenced
2508 label lest it be deleted by delete_related_insns. */
2514 {
2515 /* REG_LABEL_OPERAND could be
2516 NOTE_INSN_DELETED_LABEL too. */
2519 else
2522 }
2533 {
2534 /* REG_LABEL_OPERAND could be
2535 NOTE_INSN_DELETED_LABEL too. */
2538 else
2541 }
2544 }
2545 else
2555 {
2556 /* Even though we have filled all the slots, we
2557 may be branching to a location that has a
2558 redundant insn. Skip any if so. */
2565 && (prior_insn
2568 {
2569 /* We know we do not own the thread, so no need
2570 to call update_block and delete_insn. */
2573 new_thread
2575 }
2577 }
2580 }
2581 }
2582 }
2584 /* This insn can't go into a delay slot. */
2589 /* Ensure we don't put insns between the setting of cc and the comparison
2590 by moving a setting of cc into an earlier delay slot since these insns
2591 could clobber the condition code. */
2594 /* If this insn is a register-register copy and the next insn has
2595 a use of our destination, change it to use our source. That way,
2596 it will become a candidate for our delay slot the next time
2597 through this loop. This case occurs commonly in loops that
2598 scan a list.
2600 We could check for more complex cases than those tested below,
2601 but it doesn't seem worth it. It might also be a good idea to try
2602 to swap the two insns. That might do better.
2604 We can't do this if the next insn modifies our destination, because
2605 that would make the replacement into the insn invalid. We also can't
2606 do this if it modifies our source, because it might be an earlyclobber
2607 operand. This latter test also prevents updating the contents of
2608 a PRE_INC. We also can't do this if there's overlap of source and
2609 destination. Overlap may happen for larger-than-register-size modes. */
2615 {
2625 }
2626 }
2628 /* If we stopped on a branch insn that has delay slots, see if we can
2629 steal some of the insns in those slots. */
2633 {
2635 /* If this is the `true' thread, we will want to follow the jump,
2636 so we can only do this if we have taken everything up to here. */
2638 {
2644 /* If we owned the thread and are told that it branched
2645 elsewhere, make sure we own the thread at the new location. */
2648 }
2654 }
2656 /* If we haven't found anything for this delay slot and it is very
2657 likely that the branch will be taken, see if the insn at our target
2658 increments or decrements a register with an increment that does not
2659 depend on the destination register. If so, try to place the opposite
2660 arithmetic insn after the jump insn and put the arithmetic insn in the
2661 delay slot. If we can't do this, return. */
2668 {
2670 rtx dest;
2671 rtx src;
2673 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2674 above. */
2691 {
2693 rtx new_arith;
2696 /* If this is a constant adjustment, use the same code with
2697 the negated constant. Otherwise, reverse the sense of the
2698 arithmetic. */
2702 else
2711 {
2714 }
2717 {
2720 {
2724 }
2726 }
2727 else
2736 }
2737 }
2742 /* If we are to branch into the middle of this thread, find an appropriate
2743 label or make a new one if none, and redirect INSN to it. If we hit the
2744 end of the function, use the end-of-function label. */
2746 {
2747 rtx label;
2763 else
2768 {
2772 }
2773 }
2774 }
2775 \f
2776 /* Make another attempt to find insns to place in delay slots.
2778 We previously looked for insns located in front of the delay insn
2779 and, for non-jump delay insns, located behind the delay insn.
2781 Here only try to schedule jump insns and try to move insns from either
2782 the target or the following insns into the delay slot. If annulling is
2783 supported, we will be likely to do this. Otherwise, we can do this only
2784 if safe. */
2786 static void
2788 {
2794 {
2795 rtx condition;
2812 /* Some machine description have defined instructions to have
2813 delay slots only in certain circumstances which may depend on
2814 nearby insns (which change due to reorg's actions).
2816 For example, the PA port normally has delay slots for unconditional
2817 jumps.
2819 However, the PA port claims such jumps do not have a delay slot
2820 if they are immediate successors of certain CALL_INSNs. This
2821 allows the port to favor filling the delay slot of the call with
2822 the unconditional jump. */
2833 /* Get the next active fallthrough and target insns and see if we own
2834 them. Then see whether the branch is likely true. We don't need
2835 to do a lot of this for unconditional branches. */
2841 {
2845 }
2846 else
2847 {
2851 }
2853 /* If this insn is expected to branch, first try to get insns from our
2854 target, then our fallthrough insns. If it is not expected to branch,
2855 try the other order. */
2858 {
2861 own_target,
2865 {
2866 /* Even though we didn't find anything for delay slots,
2867 we might have found a redundant insn which we deleted
2868 from the thread that was filled. So we have to recompute
2869 the next insn at the target. */
2877 }
2878 }
2879 else
2880 {
2890 }
2900 }
2901 }
2902 \f
2905 /* Recursively delete prior insns that compute the value (used only by INSN
2906 which the caller is deleting) stored in the register mentioned by NOTE
2907 which is a REG_DEAD note associated with INSN. */
2909 static void
2911 {
2919 {
2922 /* If we reach a CALL which is not calling a const function
2923 or the callee pops the arguments, then give up. */
2929 /* If we reach a SEQUENCE, it is too complex to try to
2930 do anything with it, so give up. We can be run during
2931 and after reorg, so SEQUENCE rtl can legitimately show
2932 up here. */
2938 /* reorg creates USEs that look like this. We leave them
2939 alone because reorg needs them for its own purposes. */
2943 {
2948 {
2949 /* If we find a SET of something else, we can't
2950 delete the insn. */
2955 {
2961 }
2965 }
2968 {
2978 /* We may have a multi-word hard register and some, but not
2979 all, of the words of the register are needed in subsequent
2980 insns. Write REG_UNUSED notes for those parts that were not
2981 needed. */
2984 {
2995 }
2996 }
2999 }
3001 /* If PAT references the register that dies here, it is an
3002 additional use. Hence any prior SET isn't dead. However, this
3003 insn becomes the new place for the REG_DEAD note. */
3005 {
3009 }
3010 }
3011 }
3013 /* Delete INSN and recursively delete insns that compute values used only
3014 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3016 Look at all our REG_DEAD notes. If a previous insn does nothing other
3017 than set a register that dies in this insn, we can delete that insn
3018 as well.
3020 On machines with CC0, if CC0 is used in this insn, we may be able to
3021 delete the insn that set it. */
3023 static void
3025 {
3029 {
3031 /* We assume that at this stage
3032 CC's are always set explicitly
3033 and always immediately before the jump that
3034 will use them. So if the previous insn
3035 exists to set the CC's, delete it
3036 (unless it performs auto-increments, etc.). */
3039 {
3043 else
3044 /* Otherwise, show that cc0 won't be used. */
3046 }
3047 }
3050 {
3054 /* Verify that the REG_NOTE is legitimate. */
3059 }
3062 }
3064 /* If all INSN does is set the pc, delete it,
3065 and delete the insn that set the condition codes for it
3066 if that's what the previous thing was. */
3068 static void
3070 {
3075 }
3079 {
3082 {
3088 }
3090 }
3092 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3093 BEG and END. */
3095 static bool
3097 {
3103 }
3105 \f
3106 /* Once we have tried two ways to fill a delay slot, make a pass over the
3107 code to try to improve the results and to do such things as more jump
3108 threading. */
3110 static void
3112 {
3116 rtx target_label;
3118 /* Look at every JUMP_INSN and see if we can improve it. */
3120 {
3126 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3127 the next insn, or jumps to a label that is not the last of a
3128 group of consecutive labels. */
3132 {
3134 target_label
3144 {
3147 }
3150 {
3154 }
3156 /* See if this jump conditionally branches around an unconditional
3157 jump. If so, invert this jump and point it to the target of the
3158 second jump. Check if it's possible on the target. */
3161 && target_label
3166 {
3169 /* Be careful how we do this to avoid deleting code or
3170 labels that are momentarily dead. See similar optimization
3171 in jump.c.
3173 We also need to ensure we properly handle the case when
3174 invert_jump fails. */
3181 {
3184 }
3193 }
3194 }
3196 /* If this is an unconditional jump and the previous insn is a
3197 conditional jump, try reversing the condition of the previous
3198 insn and swapping our targets. The next pass might be able to
3199 fill the slots.
3201 Don't do this if we expect the conditional branch to be true, because
3202 we would then be making the more common case longer. */
3209 {
3215 }
3217 /* Now look only at cases where we have a filled delay slot. */
3224 /* See if the first insn in the delay slot is redundant with some
3225 previous insn. Remove it from the delay slot if so; then set up
3226 to reprocess this insn. */
3228 {
3233 }
3235 /* See if we have a RETURN insn with a filled delay slot followed
3236 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3237 the first RETURN (but not its delay insn). This gives the same
3238 effect in fewer instructions.
3240 Only do so if optimizing for size since this results in slower, but
3241 smaller code. */
3244 && next
3247 {
3251 /* Delete the RETURN and just execute the delay list insns.
3253 We do this by deleting the INSN containing the SEQUENCE, then
3254 re-emitting the insns separately, and then deleting the RETURN.
3255 This allows the count of the jump target to be properly
3256 decremented.
3258 Note that we need to change the INSN_UID of the re-emitted insns
3259 since it is used to hash the insns for mark_target_live_regs and
3260 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3262 Clear the from target bit, since these insns are no longer
3263 in delay slots. */
3276 }
3278 /* Now look only at the cases where we have a filled JUMP_INSN. */
3289 /* If this jump goes to another unconditional jump, thread it, but
3290 don't convert a jump into a RETURN here. */
3292 delay_jump_insn,
3299 {
3304 }
3306 /* If the first insn at TARGET_LABEL is redundant with a previous
3307 insn, redirect the jump to the following insn and process again.
3308 We use next_real_insn instead of next_active_insn so we
3309 don't skip USE-markers, or we'll end up with incorrect
3310 liveness info. */
3315 {
3316 /* Figure out where to emit the special USE insn so we don't
3317 later incorrectly compute register live/death info. */
3323 {
3324 /* Insert the special USE insn and update dataflow info.
3325 We know "trial" is an insn here as it is the output of
3326 next_real_insn () above. */
3329 /* Now emit a label before the special USE insn, and
3330 redirect our jump to the new label. */
3335 }
3336 }
3338 /* Similarly, if it is an unconditional jump with one insn in its
3339 delay list and that insn is redundant, thread the jump. */
3347 {
3355 {
3360 }
3361 }
3363 /* See if we have a simple (conditional) jump that is useless. */
3368 /* If the last insn in the delay slot sets CC0 for some insn,
3369 various code assumes that it is in a delay slot. We could
3370 put it back where it belonged and delete the register notes,
3371 but it doesn't seem worthwhile in this uncommon case. */
3372 && (!HAVE_cc0
3375 {
3379 /* All this insn does is execute its delay list and jump to the
3380 following insn. So delete the jump and just execute the delay
3381 list insns.
3383 We do this by deleting the INSN containing the SEQUENCE, then
3384 re-emitting the insns separately, and then deleting the jump.
3385 This allows the count of the jump target to be properly
3386 decremented.
3388 Note that we need to change the INSN_UID of the re-emitted insns
3389 since it is used to hash the insns for mark_target_live_regs and
3390 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3392 Clear the from target bit, since these insns are no longer
3393 in delay slots. */
3406 }
3408 /* See if this is an unconditional jump around a single insn which is
3409 identical to the one in its delay slot. In this case, we can just
3410 delete the branch and the insn in its delay slot. */
3416 {
3419 }
3421 /* See if this jump (with its delay slots) conditionally branches
3422 around an unconditional jump (without delay slots). If so, invert
3423 this jump and point it to the target of the second jump. We cannot
3424 do this for annulled jumps, though. Again, don't convert a jump to
3425 a RETURN here. */
3432 {
3439 /* find_end_label can generate a new label. Check this first. */
3444 {
3445 /* Be careful how we do this to avoid deleting code or labels
3446 that are momentarily dead. See similar optimization in
3447 jump.c */
3452 {
3455 /* Must update the INSN_FROM_TARGET_P bits now that
3456 the branch is reversed, so that mark_target_live_regs
3457 will handle the delay slot insn correctly. */
3459 {
3462 }
3466 }
3471 }
3472 }
3474 /* If we own the thread opposite the way this insn branches, see if we
3475 can merge its delay slots with following insns. */
3484 /* If we get here, we haven't deleted INSN. But we may have deleted
3485 NEXT, so recompute it. */
3487 }
3488 }
3489 \f
3491 /* Look for filled jumps to the end of function label. We can try to convert
3492 them into RETURN insns if the insns in the delay slot are valid for the
3493 RETURN as well. */
3495 static void
3497 {
3504 /* See if there is a RETURN insn in the function other than the one we
3505 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3506 into a RETURN to jump to it. */
3509 {
3513 else
3516 }
3518 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3519 was equal to END_OF_FUNCTION_LABEL. */
3525 /* Clear the list of insns to fill so we can use it. */
3529 {
3533 /* Only look at filled JUMP_INSNs that go to the end of function
3534 label. */
3547 {
3550 }
3552 {
3555 }
3556 else
3561 /* If we can't make the jump into a RETURN, try to redirect it to the best
3562 RETURN and go on to the next insn. */
3564 {
3565 /* Make sure redirecting the jump will not invalidate the delay
3566 slot insns. */
3570 }
3572 /* See if this RETURN can accept the insns current in its delay slot.
3573 It can if it has more or an equal number of slots and the contents
3574 of each is valid. */
3579 {
3582 #if ANNUL_IFFALSE_SLOTS
3587 #endif
3588 #if ANNUL_IFTRUE_SLOTS
3593 #endif
3597 }
3598 else
3604 /* We have to do something with this insn. If it is an unconditional
3605 RETURN, delete the SEQUENCE and output the individual insns,
3606 followed by the RETURN. Then set things up so we try to find
3607 insns for its delay slots, if it needs some. */
3609 {
3621 }
3622 else
3623 /* It is probably more efficient to keep this with its current
3624 delay slot as a branch to a RETURN. */
3626 }
3628 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3629 new delay slots we have created. */
3638 }
3639 \f
3640 /* Try to find insns to place in delay slots. */
3642 static void
3644 {
3649 /* If the current function has no insns other than the prologue and
3650 epilogue, then do not try to fill any delay slots. */
3654 /* Find the highest INSN_UID and allocate and initialize our map from
3655 INSN_UID's to position in code. */
3657 {
3663 }
3669 /* Initialize the list of insns that need filling. */
3671 {
3674 }
3677 {
3678 rtx target;
3680 /* Skip vector tables. We can't get attributes for them. */
3691 /* Ensure all jumps go to the last of a set of consecutive labels. */
3698 }
3702 /* Show we haven't computed an end-of-function label yet. */
3705 /* Initialize the statistics for this function. */
3709 /* Now do the delay slot filling. Try everything twice in case earlier
3710 changes make more slots fillable. */
3714 reorg_pass_number++)
3715 {
3721 }
3723 /* If we made an end of function label, indicate that it is now
3724 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3725 If it is now unused, delete it. */
3739 /* Delete any USE insns made by update_block; subsequent passes don't need
3740 them or know how to deal with them. */
3742 {
3748 }
3752 /* It is not clear why the line below is needed, but it does seem to be. */
3756 {
3763 reorg_pass_number++)
3764 {
3767 {
3776 {
3782 }
3784 }
3785 }
3789 {
3794 {
3796 {
3797 rtx control;
3804 else
3806 }
3809 }
3810 }
3814 {
3816 {
3821 }
3822 }
3826 {
3830 {
3832 {
3837 }
3838 }
3840 }
3843 }
3846 {
3849 }
3854 }
3855 \f
3856 /* Run delay slot optimization. */
3857 static unsigned int
3859 {
3864 }
3869 {
3879 };
3882 {
3886 {}
3888 /* opt_pass methods: */
3891 {
3893 }
3897 bool
3899 {
3900 /* At -O0 dataflow info isn't updated after RA. */
3905 }
3909 rtl_opt_pass *
3911 {
3913 }
3915 /* Machine dependent reorg pass. */
3920 {
3930 };
3933 {
3937 {}
3939 /* opt_pass methods: */
3941 {
3943 }
3946 {
3949 }
3955 rtl_opt_pass *
3957 {
3959 }