PR go/67101
[official-gcc.git] / gcc / auto-inc-dec.c
blob3b9a1f360fb24bd64fdb430e5e020d0767699853
1 /* Discovery of auto-inc and auto-dec instructions.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Kenneth Zadeck <zadeck@naturalbridge.com>
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "predict.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "df.h"
29 #include "alias.h"
30 #include "tm_p.h"
31 #include "cfgrtl.h"
32 #include "insn-config.h"
33 #include "regs.h"
34 #include "flags.h"
35 #include "except.h"
36 #include "diagnostic-core.h"
37 #include "recog.h"
38 #include "expmed.h"
39 #include "dojump.h"
40 #include "explow.h"
41 #include "calls.h"
42 #include "emit-rtl.h"
43 #include "varasm.h"
44 #include "stmt.h"
45 #include "expr.h"
46 #include "tree-pass.h"
47 #include "dbgcnt.h"
48 #include "target.h"
50 /* This pass was originally removed from flow.c. However there is
51 almost nothing that remains of that code.
53 There are (4) basic forms that are matched:
55 (1) FORM_PRE_ADD
56 a <- b + c
57 ...
60 becomes
62 a <- b
63 ...
64 *(a += c) pre
67 (2) FORM_PRE_INC
68 a += c
69 ...
72 becomes
74 *(a += c) pre
77 (3) FORM_POST_ADD
79 ...
80 b <- a + c
82 (For this case to be true, b must not be assigned or used between
83 the *a and the assignment to b. B must also be a Pmode reg.)
85 becomes
87 b <- a
88 ...
89 *(b += c) post
92 (4) FORM_POST_INC
94 ...
95 a <- a + c
97 becomes
99 *(a += c) post
101 There are three types of values of c.
103 1) c is a constant equal to the width of the value being accessed by
104 the pointer. This is useful for machines that have
105 HAVE_PRE_INCREMENT, HAVE_POST_INCREMENT, HAVE_PRE_DECREMENT or
106 HAVE_POST_DECREMENT defined.
108 2) c is a constant not equal to the width of the value being accessed
109 by the pointer. This is useful for machines that have
110 HAVE_PRE_MODIFY_DISP, HAVE_POST_MODIFY_DISP defined.
112 3) c is a register. This is useful for machines that have
113 HAVE_PRE_MODIFY_REG, HAVE_POST_MODIFY_REG
115 The is one special case: if a already had an offset equal to it +-
116 its width and that offset is equal to -c when the increment was
117 before the ref or +c if the increment was after the ref, then if we
118 can do the combination but switch the pre/post bit. */
121 enum form
123 FORM_PRE_ADD,
124 FORM_PRE_INC,
125 FORM_POST_ADD,
126 FORM_POST_INC,
127 FORM_last
130 /* The states of the second operands of mem refs and inc insns. If no
131 second operand of the mem_ref was found, it is assumed to just be
132 ZERO. SIZE is the size of the mode accessed in the memref. The
133 ANY is used for constants that are not +-size or 0. REG is used if
134 the forms are reg1 + reg2. */
136 enum inc_state
138 INC_ZERO, /* == 0 */
139 INC_NEG_SIZE, /* == +size */
140 INC_POS_SIZE, /* == -size */
141 INC_NEG_ANY, /* == some -constant */
142 INC_POS_ANY, /* == some +constant */
143 INC_REG, /* == some register */
144 INC_last
147 /* The eight forms that pre/post inc/dec can take. */
148 enum gen_form
150 NOTHING,
151 SIMPLE_PRE_INC, /* ++size */
152 SIMPLE_POST_INC, /* size++ */
153 SIMPLE_PRE_DEC, /* --size */
154 SIMPLE_POST_DEC, /* size-- */
155 DISP_PRE, /* ++con */
156 DISP_POST, /* con++ */
157 REG_PRE, /* ++reg */
158 REG_POST /* reg++ */
161 /* Tmp mem rtx for use in cost modeling. */
162 static rtx mem_tmp;
164 static enum inc_state
165 set_inc_state (HOST_WIDE_INT val, int size)
167 if (val == 0)
168 return INC_ZERO;
169 if (val < 0)
170 return (val == -size) ? INC_NEG_SIZE : INC_NEG_ANY;
171 else
172 return (val == size) ? INC_POS_SIZE : INC_POS_ANY;
175 /* The DECISION_TABLE that describes what form, if any, the increment
176 or decrement will take. It is a three dimensional table. The first
177 index is the type of constant or register found as the second
178 operand of the inc insn. The second index is the type of constant
179 or register found as the second operand of the memory reference (if
180 no second operand exists, 0 is used). The third index is the form
181 and location (relative to the mem reference) of inc insn. */
183 static bool initialized = false;
184 static enum gen_form decision_table[INC_last][INC_last][FORM_last];
186 static void
187 init_decision_table (void)
189 enum gen_form value;
191 if (HAVE_PRE_INCREMENT || HAVE_PRE_MODIFY_DISP)
193 /* Prefer the simple form if both are available. */
194 value = (HAVE_PRE_INCREMENT) ? SIMPLE_PRE_INC : DISP_PRE;
196 decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_ADD] = value;
197 decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_INC] = value;
199 decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_ADD] = value;
200 decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_INC] = value;
203 if (HAVE_POST_INCREMENT || HAVE_POST_MODIFY_DISP)
205 /* Prefer the simple form if both are available. */
206 value = (HAVE_POST_INCREMENT) ? SIMPLE_POST_INC : DISP_POST;
208 decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_ADD] = value;
209 decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_INC] = value;
211 decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_ADD] = value;
212 decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_INC] = value;
215 if (HAVE_PRE_DECREMENT || HAVE_PRE_MODIFY_DISP)
217 /* Prefer the simple form if both are available. */
218 value = (HAVE_PRE_DECREMENT) ? SIMPLE_PRE_DEC : DISP_PRE;
220 decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_ADD] = value;
221 decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_INC] = value;
223 decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_ADD] = value;
224 decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_INC] = value;
227 if (HAVE_POST_DECREMENT || HAVE_POST_MODIFY_DISP)
229 /* Prefer the simple form if both are available. */
230 value = (HAVE_POST_DECREMENT) ? SIMPLE_POST_DEC : DISP_POST;
232 decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_ADD] = value;
233 decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_INC] = value;
235 decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_ADD] = value;
236 decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_INC] = value;
239 if (HAVE_PRE_MODIFY_DISP)
241 decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE;
242 decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE;
244 decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_ADD] = DISP_PRE;
245 decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_INC] = DISP_PRE;
247 decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE;
248 decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE;
250 decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_ADD] = DISP_PRE;
251 decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_INC] = DISP_PRE;
254 if (HAVE_POST_MODIFY_DISP)
256 decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST;
257 decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST;
259 decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_ADD] = DISP_POST;
260 decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_INC] = DISP_POST;
262 decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST;
263 decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST;
265 decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_ADD] = DISP_POST;
266 decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_INC] = DISP_POST;
269 /* This is much simpler than the other cases because we do not look
270 for the reg1-reg2 case. Note that we do not have a INC_POS_REG
271 and INC_NEG_REG states. Most of the use of such states would be
272 on a target that had an R1 - R2 update address form.
274 There is the remote possibility that you could also catch a = a +
275 b; *(a - b) as a postdecrement of (a + b). However, it is
276 unclear if *(a - b) would ever be generated on a machine that did
277 not have that kind of addressing mode. The IA-64 and RS6000 will
278 not do this, and I cannot speak for any other. If any
279 architecture does have an a-b update for, these cases should be
280 added. */
281 if (HAVE_PRE_MODIFY_REG)
283 decision_table[INC_REG][INC_ZERO][FORM_PRE_ADD] = REG_PRE;
284 decision_table[INC_REG][INC_ZERO][FORM_PRE_INC] = REG_PRE;
286 decision_table[INC_REG][INC_REG][FORM_POST_ADD] = REG_PRE;
287 decision_table[INC_REG][INC_REG][FORM_POST_INC] = REG_PRE;
290 if (HAVE_POST_MODIFY_REG)
292 decision_table[INC_REG][INC_ZERO][FORM_POST_ADD] = REG_POST;
293 decision_table[INC_REG][INC_ZERO][FORM_POST_INC] = REG_POST;
296 initialized = true;
299 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
300 "reg_res = reg0+c". */
302 static struct inc_insn
304 rtx_insn *insn; /* The insn being parsed. */
305 rtx pat; /* The pattern of the insn. */
306 bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */
307 enum form form;
308 rtx reg_res;
309 rtx reg0;
310 rtx reg1;
311 enum inc_state reg1_state;/* The form of the const if reg1 is a const. */
312 HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */
313 } inc_insn;
316 /* Dump the parsed inc insn to FILE. */
318 static void
319 dump_inc_insn (FILE *file)
321 const char *f = ((inc_insn.form == FORM_PRE_ADD)
322 || (inc_insn.form == FORM_PRE_INC)) ? "pre" : "post";
324 dump_insn_slim (file, inc_insn.insn);
326 switch (inc_insn.form)
328 case FORM_PRE_ADD:
329 case FORM_POST_ADD:
330 if (inc_insn.reg1_is_const)
331 fprintf (file, "found %s add(%d) r[%d]=r[%d]+%d\n",
332 f, INSN_UID (inc_insn.insn),
333 REGNO (inc_insn.reg_res),
334 REGNO (inc_insn.reg0), (int) inc_insn.reg1_val);
335 else
336 fprintf (file, "found %s add(%d) r[%d]=r[%d]+r[%d]\n",
337 f, INSN_UID (inc_insn.insn),
338 REGNO (inc_insn.reg_res),
339 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
340 break;
342 case FORM_PRE_INC:
343 case FORM_POST_INC:
344 if (inc_insn.reg1_is_const)
345 fprintf (file, "found %s inc(%d) r[%d]+=%d\n",
346 f, INSN_UID (inc_insn.insn),
347 REGNO (inc_insn.reg_res), (int) inc_insn.reg1_val);
348 else
349 fprintf (file, "found %s inc(%d) r[%d]+=r[%d]\n",
350 f, INSN_UID (inc_insn.insn),
351 REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1));
352 break;
354 default:
355 break;
360 /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */
362 static struct mem_insn
364 rtx_insn *insn; /* The insn being parsed. */
365 rtx pat; /* The pattern of the insn. */
366 rtx *mem_loc; /* The address of the field that holds the mem */
367 /* that is to be replaced. */
368 bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */
369 rtx reg0;
370 rtx reg1; /* This is either a reg or a const depending on
371 reg1_is_const. */
372 enum inc_state reg1_state;/* The form of the const if reg1 is a const. */
373 HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */
374 } mem_insn;
377 /* Dump the parsed mem insn to FILE. */
379 static void
380 dump_mem_insn (FILE *file)
382 dump_insn_slim (file, mem_insn.insn);
384 if (mem_insn.reg1_is_const)
385 fprintf (file, "found mem(%d) *(r[%d]+%d)\n",
386 INSN_UID (mem_insn.insn),
387 REGNO (mem_insn.reg0), (int) mem_insn.reg1_val);
388 else
389 fprintf (file, "found mem(%d) *(r[%d]+r[%d])\n",
390 INSN_UID (mem_insn.insn),
391 REGNO (mem_insn.reg0), REGNO (mem_insn.reg1));
395 /* The following three arrays contain pointers to instructions. They
396 are indexed by REGNO. At any point in the basic block where we are
397 looking these three arrays contain, respectively, the next insn
398 that uses REGNO, the next inc or add insn that uses REGNO and the
399 next insn that sets REGNO.
401 The arrays are not cleared when we move from block to block so
402 whenever an insn is retrieved from these arrays, it's block number
403 must be compared with the current block.
406 static rtx_insn **reg_next_use = NULL;
407 static rtx_insn **reg_next_inc_use = NULL;
408 static rtx_insn **reg_next_def = NULL;
411 /* Move dead note that match PATTERN to TO_INSN from FROM_INSN. We do
412 not really care about moving any other notes from the inc or add
413 insn. Moving the REG_EQUAL and REG_EQUIV is clearly wrong and it
414 does not appear that there are any other kinds of relevant notes. */
416 static void
417 move_dead_notes (rtx_insn *to_insn, rtx_insn *from_insn, rtx pattern)
419 rtx note;
420 rtx next_note;
421 rtx prev_note = NULL;
423 for (note = REG_NOTES (from_insn); note; note = next_note)
425 next_note = XEXP (note, 1);
427 if ((REG_NOTE_KIND (note) == REG_DEAD)
428 && pattern == XEXP (note, 0))
430 XEXP (note, 1) = REG_NOTES (to_insn);
431 REG_NOTES (to_insn) = note;
432 if (prev_note)
433 XEXP (prev_note, 1) = next_note;
434 else
435 REG_NOTES (from_insn) = next_note;
437 else prev_note = note;
442 /* Create a mov insn DEST_REG <- SRC_REG and insert it before
443 NEXT_INSN. */
445 static rtx_insn *
446 insert_move_insn_before (rtx_insn *next_insn, rtx dest_reg, rtx src_reg)
448 rtx_insn *insns;
450 start_sequence ();
451 emit_move_insn (dest_reg, src_reg);
452 insns = get_insns ();
453 end_sequence ();
454 emit_insn_before (insns, next_insn);
455 return insns;
459 /* Change mem_insn.mem_loc so that uses NEW_ADDR which has an
460 increment of INC_REG. To have reached this point, the change is a
461 legitimate one from a dataflow point of view. The only questions
462 are is this a valid change to the instruction and is this a
463 profitable change to the instruction. */
465 static bool
466 attempt_change (rtx new_addr, rtx inc_reg)
468 /* There are four cases: For the two cases that involve an add
469 instruction, we are going to have to delete the add and insert a
470 mov. We are going to assume that the mov is free. This is
471 fairly early in the backend and there are a lot of opportunities
472 for removing that move later. In particular, there is the case
473 where the move may be dead, this is what dead code elimination
474 passes are for. The two cases where we have an inc insn will be
475 handled mov free. */
477 basic_block bb = BLOCK_FOR_INSN (mem_insn.insn);
478 rtx_insn *mov_insn = NULL;
479 int regno;
480 rtx mem = *mem_insn.mem_loc;
481 machine_mode mode = GET_MODE (mem);
482 rtx new_mem;
483 int old_cost = 0;
484 int new_cost = 0;
485 bool speed = optimize_bb_for_speed_p (bb);
487 PUT_MODE (mem_tmp, mode);
488 XEXP (mem_tmp, 0) = new_addr;
490 old_cost = (set_src_cost (mem, mode, speed)
491 + set_rtx_cost (PATTERN (inc_insn.insn), speed));
492 new_cost = set_src_cost (mem_tmp, mode, speed);
494 /* The first item of business is to see if this is profitable. */
495 if (old_cost < new_cost)
497 if (dump_file)
498 fprintf (dump_file, "cost failure old=%d new=%d\n", old_cost, new_cost);
499 return false;
502 /* Jump through a lot of hoops to keep the attributes up to date. We
503 do not want to call one of the change address variants that take
504 an offset even though we know the offset in many cases. These
505 assume you are changing where the address is pointing by the
506 offset. */
507 new_mem = replace_equiv_address_nv (mem, new_addr);
508 if (! validate_change (mem_insn.insn, mem_insn.mem_loc, new_mem, 0))
510 if (dump_file)
511 fprintf (dump_file, "validation failure\n");
512 return false;
515 /* From here to the end of the function we are committed to the
516 change, i.e. nothing fails. Generate any necessary movs, move
517 any regnotes, and fix up the reg_next_{use,inc_use,def}. */
518 switch (inc_insn.form)
520 case FORM_PRE_ADD:
521 /* Replace the addition with a move. Do it at the location of
522 the addition since the operand of the addition may change
523 before the memory reference. */
524 mov_insn = insert_move_insn_before (inc_insn.insn,
525 inc_insn.reg_res, inc_insn.reg0);
526 move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0);
528 regno = REGNO (inc_insn.reg_res);
529 reg_next_def[regno] = mov_insn;
530 reg_next_use[regno] = NULL;
531 regno = REGNO (inc_insn.reg0);
532 reg_next_use[regno] = mov_insn;
533 df_recompute_luids (bb);
534 break;
536 case FORM_POST_INC:
537 regno = REGNO (inc_insn.reg_res);
538 if (reg_next_use[regno] == reg_next_inc_use[regno])
539 reg_next_inc_use[regno] = NULL;
541 /* Fallthru. */
542 case FORM_PRE_INC:
543 regno = REGNO (inc_insn.reg_res);
544 reg_next_def[regno] = mem_insn.insn;
545 reg_next_use[regno] = NULL;
547 break;
549 case FORM_POST_ADD:
550 mov_insn = insert_move_insn_before (mem_insn.insn,
551 inc_insn.reg_res, inc_insn.reg0);
552 move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0);
554 /* Do not move anything to the mov insn because the instruction
555 pointer for the main iteration has not yet hit that. It is
556 still pointing to the mem insn. */
557 regno = REGNO (inc_insn.reg_res);
558 reg_next_def[regno] = mem_insn.insn;
559 reg_next_use[regno] = NULL;
561 regno = REGNO (inc_insn.reg0);
562 reg_next_use[regno] = mem_insn.insn;
563 if ((reg_next_use[regno] == reg_next_inc_use[regno])
564 || (reg_next_inc_use[regno] == inc_insn.insn))
565 reg_next_inc_use[regno] = NULL;
566 df_recompute_luids (bb);
567 break;
569 case FORM_last:
570 default:
571 gcc_unreachable ();
574 if (!inc_insn.reg1_is_const)
576 regno = REGNO (inc_insn.reg1);
577 reg_next_use[regno] = mem_insn.insn;
578 if ((reg_next_use[regno] == reg_next_inc_use[regno])
579 || (reg_next_inc_use[regno] == inc_insn.insn))
580 reg_next_inc_use[regno] = NULL;
583 delete_insn (inc_insn.insn);
585 if (dump_file && mov_insn)
587 fprintf (dump_file, "inserting mov ");
588 dump_insn_slim (dump_file, mov_insn);
591 /* Record that this insn has an implicit side effect. */
592 add_reg_note (mem_insn.insn, REG_INC, inc_reg);
594 if (dump_file)
596 fprintf (dump_file, "****success ");
597 dump_insn_slim (dump_file, mem_insn.insn);
600 return true;
604 /* Try to combine the instruction in INC_INSN with the instruction in
605 MEM_INSN. First the form is determined using the DECISION_TABLE
606 and the results of parsing the INC_INSN and the MEM_INSN.
607 Assuming the form is ok, a prototype new address is built which is
608 passed to ATTEMPT_CHANGE for final processing. */
610 static bool
611 try_merge (void)
613 enum gen_form gen_form;
614 rtx mem = *mem_insn.mem_loc;
615 rtx inc_reg = inc_insn.form == FORM_POST_ADD ?
616 inc_insn.reg_res : mem_insn.reg0;
618 /* The width of the mem being accessed. */
619 int size = GET_MODE_SIZE (GET_MODE (mem));
620 rtx_insn *last_insn = NULL;
621 machine_mode reg_mode = GET_MODE (inc_reg);
623 switch (inc_insn.form)
625 case FORM_PRE_ADD:
626 case FORM_PRE_INC:
627 last_insn = mem_insn.insn;
628 break;
629 case FORM_POST_INC:
630 case FORM_POST_ADD:
631 last_insn = inc_insn.insn;
632 break;
633 case FORM_last:
634 default:
635 gcc_unreachable ();
638 /* Cannot handle auto inc of the stack. */
639 if (inc_reg == stack_pointer_rtx)
641 if (dump_file)
642 fprintf (dump_file, "cannot inc stack %d failure\n", REGNO (inc_reg));
643 return false;
646 /* Look to see if the inc register is dead after the memory
647 reference. If it is, do not do the combination. */
648 if (find_regno_note (last_insn, REG_DEAD, REGNO (inc_reg)))
650 if (dump_file)
651 fprintf (dump_file, "dead failure %d\n", REGNO (inc_reg));
652 return false;
655 mem_insn.reg1_state = (mem_insn.reg1_is_const)
656 ? set_inc_state (mem_insn.reg1_val, size) : INC_REG;
657 inc_insn.reg1_state = (inc_insn.reg1_is_const)
658 ? set_inc_state (inc_insn.reg1_val, size) : INC_REG;
660 /* Now get the form that we are generating. */
661 gen_form = decision_table
662 [inc_insn.reg1_state][mem_insn.reg1_state][inc_insn.form];
664 if (dbg_cnt (auto_inc_dec) == false)
665 return false;
667 switch (gen_form)
669 default:
670 case NOTHING:
671 return false;
673 case SIMPLE_PRE_INC: /* ++size */
674 if (dump_file)
675 fprintf (dump_file, "trying SIMPLE_PRE_INC\n");
676 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg);
677 break;
679 case SIMPLE_POST_INC: /* size++ */
680 if (dump_file)
681 fprintf (dump_file, "trying SIMPLE_POST_INC\n");
682 return attempt_change (gen_rtx_POST_INC (reg_mode, inc_reg), inc_reg);
683 break;
685 case SIMPLE_PRE_DEC: /* --size */
686 if (dump_file)
687 fprintf (dump_file, "trying SIMPLE_PRE_DEC\n");
688 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg);
689 break;
691 case SIMPLE_POST_DEC: /* size-- */
692 if (dump_file)
693 fprintf (dump_file, "trying SIMPLE_POST_DEC\n");
694 return attempt_change (gen_rtx_POST_DEC (reg_mode, inc_reg), inc_reg);
695 break;
697 case DISP_PRE: /* ++con */
698 if (dump_file)
699 fprintf (dump_file, "trying DISP_PRE\n");
700 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode,
701 inc_reg,
702 gen_rtx_PLUS (reg_mode,
703 inc_reg,
704 inc_insn.reg1)),
705 inc_reg);
706 break;
708 case DISP_POST: /* con++ */
709 if (dump_file)
710 fprintf (dump_file, "trying POST_DISP\n");
711 return attempt_change (gen_rtx_POST_MODIFY (reg_mode,
712 inc_reg,
713 gen_rtx_PLUS (reg_mode,
714 inc_reg,
715 inc_insn.reg1)),
716 inc_reg);
717 break;
719 case REG_PRE: /* ++reg */
720 if (dump_file)
721 fprintf (dump_file, "trying PRE_REG\n");
722 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode,
723 inc_reg,
724 gen_rtx_PLUS (reg_mode,
725 inc_reg,
726 inc_insn.reg1)),
727 inc_reg);
728 break;
730 case REG_POST: /* reg++ */
731 if (dump_file)
732 fprintf (dump_file, "trying POST_REG\n");
733 return attempt_change (gen_rtx_POST_MODIFY (reg_mode,
734 inc_reg,
735 gen_rtx_PLUS (reg_mode,
736 inc_reg,
737 inc_insn.reg1)),
738 inc_reg);
739 break;
743 /* Return the next insn that uses (if reg_next_use is passed in
744 NEXT_ARRAY) or defines (if reg_next_def is passed in NEXT_ARRAY)
745 REGNO in BB. */
747 static rtx_insn *
748 get_next_ref (int regno, basic_block bb, rtx_insn **next_array)
750 rtx_insn *insn = next_array[regno];
752 /* Lazy about cleaning out the next_arrays. */
753 if (insn && BLOCK_FOR_INSN (insn) != bb)
755 next_array[regno] = NULL;
756 insn = NULL;
759 return insn;
763 /* Return true if INSN is of a form "a = b op c" where a and b are
764 regs. op is + if c is a reg and +|- if c is a const. Fill in
765 INC_INSN with what is found.
767 This function is called in two contexts, if BEFORE_MEM is true,
768 this is called for each insn in the basic block. If BEFORE_MEM is
769 false, it is called for the instruction in the block that uses the
770 index register for some memory reference that is currently being
771 processed. */
773 static bool
774 parse_add_or_inc (rtx_insn *insn, bool before_mem)
776 rtx pat = single_set (insn);
777 if (!pat)
778 return false;
780 /* Result must be single reg. */
781 if (!REG_P (SET_DEST (pat)))
782 return false;
784 if ((GET_CODE (SET_SRC (pat)) != PLUS)
785 && (GET_CODE (SET_SRC (pat)) != MINUS))
786 return false;
788 if (!REG_P (XEXP (SET_SRC (pat), 0)))
789 return false;
791 inc_insn.insn = insn;
792 inc_insn.pat = pat;
793 inc_insn.reg_res = SET_DEST (pat);
794 inc_insn.reg0 = XEXP (SET_SRC (pat), 0);
795 if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg0))
796 inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC;
797 else
798 inc_insn.form = before_mem ? FORM_PRE_ADD : FORM_POST_ADD;
800 if (CONST_INT_P (XEXP (SET_SRC (pat), 1)))
802 /* Process a = b + c where c is a const. */
803 inc_insn.reg1_is_const = true;
804 if (GET_CODE (SET_SRC (pat)) == PLUS)
806 inc_insn.reg1 = XEXP (SET_SRC (pat), 1);
807 inc_insn.reg1_val = INTVAL (inc_insn.reg1);
809 else
811 inc_insn.reg1_val = -INTVAL (XEXP (SET_SRC (pat), 1));
812 inc_insn.reg1 = GEN_INT (inc_insn.reg1_val);
814 return true;
816 else if ((HAVE_PRE_MODIFY_REG || HAVE_POST_MODIFY_REG)
817 && (REG_P (XEXP (SET_SRC (pat), 1)))
818 && GET_CODE (SET_SRC (pat)) == PLUS)
820 /* Process a = b + c where c is a reg. */
821 inc_insn.reg1 = XEXP (SET_SRC (pat), 1);
822 inc_insn.reg1_is_const = false;
824 if (inc_insn.form == FORM_PRE_INC
825 || inc_insn.form == FORM_POST_INC)
826 return true;
827 else if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg1))
829 /* Reverse the two operands and turn *_ADD into *_INC since
830 a = c + a. */
831 std::swap (inc_insn.reg0, inc_insn.reg1);
832 inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC;
833 return true;
835 else
836 return true;
839 return false;
843 /* A recursive function that checks all of the mem uses in
844 ADDRESS_OF_X to see if any single one of them is compatible with
845 what has been found in inc_insn.
847 -1 is returned for success. 0 is returned if nothing was found and
848 1 is returned for failure. */
850 static int
851 find_address (rtx *address_of_x)
853 rtx x = *address_of_x;
854 enum rtx_code code = GET_CODE (x);
855 const char *const fmt = GET_RTX_FORMAT (code);
856 int i;
857 int value = 0;
858 int tem;
860 if (code == MEM && rtx_equal_p (XEXP (x, 0), inc_insn.reg_res))
862 /* Match with *reg0. */
863 mem_insn.mem_loc = address_of_x;
864 mem_insn.reg0 = inc_insn.reg_res;
865 mem_insn.reg1_is_const = true;
866 mem_insn.reg1_val = 0;
867 mem_insn.reg1 = GEN_INT (0);
868 return -1;
870 if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
871 && rtx_equal_p (XEXP (XEXP (x, 0), 0), inc_insn.reg_res))
873 rtx b = XEXP (XEXP (x, 0), 1);
874 mem_insn.mem_loc = address_of_x;
875 mem_insn.reg0 = inc_insn.reg_res;
876 mem_insn.reg1 = b;
877 mem_insn.reg1_is_const = inc_insn.reg1_is_const;
878 if (CONST_INT_P (b))
880 /* Match with *(reg0 + reg1) where reg1 is a const. */
881 HOST_WIDE_INT val = INTVAL (b);
882 if (inc_insn.reg1_is_const
883 && (inc_insn.reg1_val == val || inc_insn.reg1_val == -val))
885 mem_insn.reg1_val = val;
886 return -1;
889 else if (!inc_insn.reg1_is_const
890 && rtx_equal_p (inc_insn.reg1, b))
891 /* Match with *(reg0 + reg1). */
892 return -1;
895 if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
897 /* If REG occurs inside a MEM used in a bit-field reference,
898 that is unacceptable. */
899 if (find_address (&XEXP (x, 0)))
900 return 1;
903 if (x == inc_insn.reg_res)
904 return 1;
906 /* Time for some deep diving. */
907 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
909 if (fmt[i] == 'e')
911 tem = find_address (&XEXP (x, i));
912 /* If this is the first use, let it go so the rest of the
913 insn can be checked. */
914 if (value == 0)
915 value = tem;
916 else if (tem != 0)
917 /* More than one match was found. */
918 return 1;
920 else if (fmt[i] == 'E')
922 int j;
923 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
925 tem = find_address (&XVECEXP (x, i, j));
926 /* If this is the first use, let it go so the rest of
927 the insn can be checked. */
928 if (value == 0)
929 value = tem;
930 else if (tem != 0)
931 /* More than one match was found. */
932 return 1;
936 return value;
939 /* Once a suitable mem reference has been found and the MEM_INSN
940 structure has been filled in, FIND_INC is called to see if there is
941 a suitable add or inc insn that follows the mem reference and
942 determine if it is suitable to merge.
944 In the case where the MEM_INSN has two registers in the reference,
945 this function may be called recursively. The first time looking
946 for an add of the first register, and if that fails, looking for an
947 add of the second register. The FIRST_TRY parameter is used to
948 only allow the parameters to be reversed once. */
950 static bool
951 find_inc (bool first_try)
953 rtx_insn *insn;
954 basic_block bb = BLOCK_FOR_INSN (mem_insn.insn);
955 rtx_insn *other_insn;
956 df_ref def;
958 /* Make sure this reg appears only once in this insn. */
959 if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg0, 1) != 1)
961 if (dump_file)
962 fprintf (dump_file, "mem count failure\n");
963 return false;
966 if (dump_file)
967 dump_mem_insn (dump_file);
969 /* Find the next use that is an inc. */
970 insn = get_next_ref (REGNO (mem_insn.reg0),
971 BLOCK_FOR_INSN (mem_insn.insn),
972 reg_next_inc_use);
973 if (!insn)
974 return false;
976 /* Even though we know the next use is an add or inc because it came
977 from the reg_next_inc_use, we must still reparse. */
978 if (!parse_add_or_inc (insn, false))
980 /* Next use was not an add. Look for one extra case. It could be
981 that we have:
983 *(a + b)
984 ...= a;
985 ...= b + a
987 if we reverse the operands in the mem ref we would
988 find this. Only try it once though. */
989 if (first_try && !mem_insn.reg1_is_const)
991 std::swap (mem_insn.reg0, mem_insn.reg1);
992 return find_inc (false);
994 else
995 return false;
998 /* Need to assure that none of the operands of the inc instruction are
999 assigned to by the mem insn. */
1000 FOR_EACH_INSN_DEF (def, mem_insn.insn)
1002 unsigned int regno = DF_REF_REGNO (def);
1003 if ((regno == REGNO (inc_insn.reg0))
1004 || (regno == REGNO (inc_insn.reg_res)))
1006 if (dump_file)
1007 fprintf (dump_file, "inc conflicts with store failure.\n");
1008 return false;
1010 if (!inc_insn.reg1_is_const && (regno == REGNO (inc_insn.reg1)))
1012 if (dump_file)
1013 fprintf (dump_file, "inc conflicts with store failure.\n");
1014 return false;
1018 if (dump_file)
1019 dump_inc_insn (dump_file);
1021 if (inc_insn.form == FORM_POST_ADD)
1023 /* Make sure that there is no insn that assigns to inc_insn.res
1024 between the mem_insn and the inc_insn. */
1025 rtx_insn *other_insn = get_next_ref (REGNO (inc_insn.reg_res),
1026 BLOCK_FOR_INSN (mem_insn.insn),
1027 reg_next_def);
1028 if (other_insn != inc_insn.insn)
1030 if (dump_file)
1031 fprintf (dump_file,
1032 "result of add is assigned to between mem and inc insns.\n");
1033 return false;
1036 other_insn = get_next_ref (REGNO (inc_insn.reg_res),
1037 BLOCK_FOR_INSN (mem_insn.insn),
1038 reg_next_use);
1039 if (other_insn
1040 && (other_insn != inc_insn.insn)
1041 && (DF_INSN_LUID (inc_insn.insn) > DF_INSN_LUID (other_insn)))
1043 if (dump_file)
1044 fprintf (dump_file,
1045 "result of add is used between mem and inc insns.\n");
1046 return false;
1049 /* For the post_add to work, the result_reg of the inc must not be
1050 used in the mem insn since this will become the new index
1051 register. */
1052 if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn)))
1054 if (dump_file)
1055 fprintf (dump_file, "base reg replacement failure.\n");
1056 return false;
1060 if (mem_insn.reg1_is_const)
1062 if (mem_insn.reg1_val == 0)
1064 if (!inc_insn.reg1_is_const)
1066 /* The mem looks like *r0 and the rhs of the add has two
1067 registers. */
1068 int luid = DF_INSN_LUID (inc_insn.insn);
1069 if (inc_insn.form == FORM_POST_ADD)
1071 /* The trick is that we are not going to increment r0,
1072 we are going to increment the result of the add insn.
1073 For this trick to be correct, the result reg of
1074 the inc must be a valid addressing reg. */
1075 addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc);
1076 if (GET_MODE (inc_insn.reg_res)
1077 != targetm.addr_space.address_mode (as))
1079 if (dump_file)
1080 fprintf (dump_file, "base reg mode failure.\n");
1081 return false;
1084 /* We also need to make sure that the next use of
1085 inc result is after the inc. */
1086 other_insn
1087 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use);
1088 if (other_insn && luid > DF_INSN_LUID (other_insn))
1089 return false;
1091 if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
1092 std::swap (inc_insn.reg0, inc_insn.reg1);
1095 other_insn
1096 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
1097 if (other_insn && luid > DF_INSN_LUID (other_insn))
1098 return false;
1101 /* Both the inc/add and the mem have a constant. Need to check
1102 that the constants are ok. */
1103 else if ((mem_insn.reg1_val != inc_insn.reg1_val)
1104 && (mem_insn.reg1_val != -inc_insn.reg1_val))
1105 return false;
1107 else
1109 /* The mem insn is of the form *(a + b) where a and b are both
1110 regs. It may be that in order to match the add or inc we
1111 need to treat it as if it was *(b + a). It may also be that
1112 the add is of the form a + c where c does not match b and
1113 then we just abandon this. */
1115 int luid = DF_INSN_LUID (inc_insn.insn);
1116 rtx_insn *other_insn;
1118 /* Make sure this reg appears only once in this insn. */
1119 if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg1, 1) != 1)
1120 return false;
1122 if (inc_insn.form == FORM_POST_ADD)
1124 /* For this trick to be correct, the result reg of the inc
1125 must be a valid addressing reg. */
1126 addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc);
1127 if (GET_MODE (inc_insn.reg_res)
1128 != targetm.addr_space.address_mode (as))
1130 if (dump_file)
1131 fprintf (dump_file, "base reg mode failure.\n");
1132 return false;
1135 if (rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
1137 if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1))
1139 /* See comment above on find_inc (false) call. */
1140 if (first_try)
1142 std::swap (mem_insn.reg0, mem_insn.reg1);
1143 return find_inc (false);
1145 else
1146 return false;
1149 /* Need to check that there are no assignments to b
1150 before the add insn. */
1151 other_insn
1152 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
1153 if (other_insn && luid > DF_INSN_LUID (other_insn))
1154 return false;
1155 /* All ok for the next step. */
1157 else
1159 /* We know that mem_insn.reg0 must equal inc_insn.reg1
1160 or else we would not have found the inc insn. */
1161 std::swap (mem_insn.reg0, mem_insn.reg1);
1162 if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
1164 /* See comment above on find_inc (false) call. */
1165 if (first_try)
1166 return find_inc (false);
1167 else
1168 return false;
1170 /* To have gotten here know that.
1171 *(b + a)
1173 ... = (b + a)
1175 We also know that the lhs of the inc is not b or a. We
1176 need to make sure that there are no assignments to b
1177 between the mem ref and the inc. */
1179 other_insn
1180 = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_def);
1181 if (other_insn && luid > DF_INSN_LUID (other_insn))
1182 return false;
1185 /* Need to check that the next use of the add result is later than
1186 add insn since this will be the reg incremented. */
1187 other_insn
1188 = get_next_ref (REGNO (inc_insn.reg_res), bb, reg_next_use);
1189 if (other_insn && luid > DF_INSN_LUID (other_insn))
1190 return false;
1192 else /* FORM_POST_INC. There is less to check here because we
1193 know that operands must line up. */
1195 if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1))
1196 /* See comment above on find_inc (false) call. */
1198 if (first_try)
1200 std::swap (mem_insn.reg0, mem_insn.reg1);
1201 return find_inc (false);
1203 else
1204 return false;
1207 /* To have gotten here know that.
1208 *(a + b)
1210 ... = (a + b)
1212 We also know that the lhs of the inc is not b. We need to make
1213 sure that there are no assignments to b between the mem ref and
1214 the inc. */
1215 other_insn
1216 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
1217 if (other_insn && luid > DF_INSN_LUID (other_insn))
1218 return false;
1222 if (inc_insn.form == FORM_POST_INC)
1224 other_insn
1225 = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_use);
1226 /* When we found inc_insn, we were looking for the
1227 next add or inc, not the next insn that used the
1228 reg. Because we are going to increment the reg
1229 in this form, we need to make sure that there
1230 were no intervening uses of reg. */
1231 if (inc_insn.insn != other_insn)
1232 return false;
1235 return try_merge ();
1239 /* A recursive function that walks ADDRESS_OF_X to find all of the mem
1240 uses in pat that could be used as an auto inc or dec. It then
1241 calls FIND_INC for each one. */
1243 static bool
1244 find_mem (rtx *address_of_x)
1246 rtx x = *address_of_x;
1247 enum rtx_code code = GET_CODE (x);
1248 const char *const fmt = GET_RTX_FORMAT (code);
1249 int i;
1251 if (code == MEM && REG_P (XEXP (x, 0)))
1253 /* Match with *reg0. */
1254 mem_insn.mem_loc = address_of_x;
1255 mem_insn.reg0 = XEXP (x, 0);
1256 mem_insn.reg1_is_const = true;
1257 mem_insn.reg1_val = 0;
1258 mem_insn.reg1 = GEN_INT (0);
1259 if (find_inc (true))
1260 return true;
1262 if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
1263 && REG_P (XEXP (XEXP (x, 0), 0)))
1265 rtx reg1 = XEXP (XEXP (x, 0), 1);
1266 mem_insn.mem_loc = address_of_x;
1267 mem_insn.reg0 = XEXP (XEXP (x, 0), 0);
1268 mem_insn.reg1 = reg1;
1269 if (CONST_INT_P (reg1))
1271 mem_insn.reg1_is_const = true;
1272 /* Match with *(reg0 + c) where c is a const. */
1273 mem_insn.reg1_val = INTVAL (reg1);
1274 if (find_inc (true))
1275 return true;
1277 else if (REG_P (reg1))
1279 /* Match with *(reg0 + reg1). */
1280 mem_insn.reg1_is_const = false;
1281 if (find_inc (true))
1282 return true;
1286 if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
1288 /* If REG occurs inside a MEM used in a bit-field reference,
1289 that is unacceptable. */
1290 return false;
1293 /* Time for some deep diving. */
1294 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1296 if (fmt[i] == 'e')
1298 if (find_mem (&XEXP (x, i)))
1299 return true;
1301 else if (fmt[i] == 'E')
1303 int j;
1304 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1305 if (find_mem (&XVECEXP (x, i, j)))
1306 return true;
1309 return false;
1313 /* Try to combine all incs and decs by constant values with memory
1314 references in BB. */
1316 static void
1317 merge_in_block (int max_reg, basic_block bb)
1319 rtx_insn *insn;
1320 rtx_insn *curr;
1321 int success_in_block = 0;
1323 if (dump_file)
1324 fprintf (dump_file, "\n\nstarting bb %d\n", bb->index);
1326 FOR_BB_INSNS_REVERSE_SAFE (bb, insn, curr)
1328 bool insn_is_add_or_inc = true;
1330 if (!NONDEBUG_INSN_P (insn))
1331 continue;
1333 /* This continue is deliberate. We do not want the uses of the
1334 jump put into reg_next_use because it is not considered safe to
1335 combine a preincrement with a jump. */
1336 if (JUMP_P (insn))
1337 continue;
1339 if (dump_file)
1340 dump_insn_slim (dump_file, insn);
1342 /* Does this instruction increment or decrement a register? */
1343 if (parse_add_or_inc (insn, true))
1345 int regno = REGNO (inc_insn.reg_res);
1346 /* Cannot handle case where there are three separate regs
1347 before a mem ref. Too many moves would be needed to be
1348 profitable. */
1349 if ((inc_insn.form == FORM_PRE_INC) || inc_insn.reg1_is_const)
1351 mem_insn.insn = get_next_ref (regno, bb, reg_next_use);
1352 if (mem_insn.insn)
1354 bool ok = true;
1355 if (!inc_insn.reg1_is_const)
1357 /* We are only here if we are going to try a
1358 HAVE_*_MODIFY_REG type transformation. c is a
1359 reg and we must sure that the path from the
1360 inc_insn to the mem_insn.insn is both def and use
1361 clear of c because the inc insn is going to move
1362 into the mem_insn.insn. */
1363 int luid = DF_INSN_LUID (mem_insn.insn);
1364 rtx_insn *other_insn
1365 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use);
1367 if (other_insn && luid > DF_INSN_LUID (other_insn))
1368 ok = false;
1370 other_insn
1371 = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
1373 if (other_insn && luid > DF_INSN_LUID (other_insn))
1374 ok = false;
1377 if (dump_file)
1378 dump_inc_insn (dump_file);
1380 if (ok && find_address (&PATTERN (mem_insn.insn)) == -1)
1382 if (dump_file)
1383 dump_mem_insn (dump_file);
1384 if (try_merge ())
1386 success_in_block++;
1387 insn_is_add_or_inc = false;
1393 else
1395 insn_is_add_or_inc = false;
1396 mem_insn.insn = insn;
1397 if (find_mem (&PATTERN (insn)))
1398 success_in_block++;
1401 /* If the inc insn was merged with a mem, the inc insn is gone
1402 and there is noting to update. */
1403 if (df_insn_info *insn_info = DF_INSN_INFO_GET (insn))
1405 df_ref def, use;
1407 /* Need to update next use. */
1408 FOR_EACH_INSN_INFO_DEF (def, insn_info)
1410 reg_next_use[DF_REF_REGNO (def)] = NULL;
1411 reg_next_inc_use[DF_REF_REGNO (def)] = NULL;
1412 reg_next_def[DF_REF_REGNO (def)] = insn;
1415 FOR_EACH_INSN_INFO_USE (use, insn_info)
1417 reg_next_use[DF_REF_REGNO (use)] = insn;
1418 if (insn_is_add_or_inc)
1419 reg_next_inc_use[DF_REF_REGNO (use)] = insn;
1420 else
1421 reg_next_inc_use[DF_REF_REGNO (use)] = NULL;
1424 else if (dump_file)
1425 fprintf (dump_file, "skipping update of deleted insn %d\n",
1426 INSN_UID (insn));
1429 /* If we were successful, try again. There may have been several
1430 opportunities that were interleaved. This is rare but
1431 gcc.c-torture/compile/pr17273.c actually exhibits this. */
1432 if (success_in_block)
1434 /* In this case, we must clear these vectors since the trick of
1435 testing if the stale insn in the block will not work. */
1436 memset (reg_next_use, 0, max_reg * sizeof (rtx));
1437 memset (reg_next_inc_use, 0, max_reg * sizeof (rtx));
1438 memset (reg_next_def, 0, max_reg * sizeof (rtx));
1439 df_recompute_luids (bb);
1440 merge_in_block (max_reg, bb);
1444 /* Discover auto-inc auto-dec instructions. */
1446 namespace {
1448 const pass_data pass_data_inc_dec =
1450 RTL_PASS, /* type */
1451 "auto_inc_dec", /* name */
1452 OPTGROUP_NONE, /* optinfo_flags */
1453 TV_AUTO_INC_DEC, /* tv_id */
1454 0, /* properties_required */
1455 0, /* properties_provided */
1456 0, /* properties_destroyed */
1457 0, /* todo_flags_start */
1458 TODO_df_finish, /* todo_flags_finish */
1461 class pass_inc_dec : public rtl_opt_pass
1463 public:
1464 pass_inc_dec (gcc::context *ctxt)
1465 : rtl_opt_pass (pass_data_inc_dec, ctxt)
1468 /* opt_pass methods: */
1469 virtual bool gate (function *)
1471 if (!AUTO_INC_DEC)
1472 return false;
1474 return (optimize > 0 && flag_auto_inc_dec);
1478 unsigned int execute (function *);
1480 }; // class pass_inc_dec
1482 unsigned int
1483 pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED)
1485 if (!AUTO_INC_DEC)
1486 return 0;
1488 basic_block bb;
1489 int max_reg = max_reg_num ();
1491 if (!initialized)
1492 init_decision_table ();
1494 mem_tmp = gen_rtx_MEM (Pmode, NULL_RTX);
1496 df_note_add_problem ();
1497 df_analyze ();
1499 reg_next_use = XCNEWVEC (rtx_insn *, max_reg);
1500 reg_next_inc_use = XCNEWVEC (rtx_insn *, max_reg);
1501 reg_next_def = XCNEWVEC (rtx_insn *, max_reg);
1502 FOR_EACH_BB_FN (bb, fun)
1503 merge_in_block (max_reg, bb);
1505 free (reg_next_use);
1506 free (reg_next_inc_use);
1507 free (reg_next_def);
1509 mem_tmp = NULL;
1511 return 0;
1514 } // anon namespace
1516 rtl_opt_pass *
1517 make_pass_inc_dec (gcc::context *ctxt)
1519 return new pass_inc_dec (ctxt);