| blob | 7a8185d4bad37178d9953dd6b7048463ca5b4f03 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshhold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
252 #if 0
254 #endif
284 rtx *));
367 {
368 rtx r1;
369 rtx r2;
373 {
374 rtx match;
375 rtx replacement;
376 rtx insn;
379 /* Nonzero iff INSN is between START and END, inclusive. */
380 #define INSN_IN_RANGE_P(INSN, START, END) \
381 (INSN_UID (INSN) < max_uid_for_loop \
382 && INSN_LUID (INSN) >= INSN_LUID (START) \
383 && INSN_LUID (INSN) <= INSN_LUID (END))
385 /* Indirect_jump_in_function is computed once per function. */
393 rtx));
394 \f
395 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
396 copy the value of the strength reduced giv to its original register. */
399 /* Cost of using a register, to normalize the benefits of a giv. */
402 void
404 {
410 }
411 \f
412 /* Compute the mapping from uids to luids.
413 LUIDs are numbers assigned to insns, like uids,
414 except that luids increase monotonically through the code.
415 Start at insn START and stop just before END. Assign LUIDs
416 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
417 static int
421 {
423 rtx insn;
426 {
429 /* Don't assign luids to line-number NOTEs, so that the distance in
430 luids between two insns is not affected by -g. */
434 else
435 /* Give a line number note the same luid as preceding insn. */
437 }
439 }
440 \f
441 /* Entry point of this file. Perform loop optimization
442 on the current function. F is the first insn of the function
443 and DUMPFILE is a stream for output of a trace of actions taken
444 (or 0 if none should be output). */
446 void
448 /* f is the first instruction of a chain of insns for one function */
449 rtx f;
452 {
453 rtx insn;
468 /* Count the number of loops. */
472 {
475 max_loop_num++;
476 }
478 /* Don't waste time if no loops. */
484 /* Get size to use for tables indexed by uids.
485 Leave some space for labels allocated by find_and_verify_loops. */
492 /* Allocate storage for array of loops. */
496 /* Find and process each loop.
497 First, find them, and record them in order of their beginnings. */
500 /* Allocate and initialize auxiliary loop information. */
505 /* Now find all register lifetimes. This must be done after
506 find_and_verify_loops, because it might reorder the insns in the
507 function. */
510 /* This must occur after reg_scan so that registers created by gcse
511 will have entries in the register tables.
513 We could have added a call to reg_scan after gcse_main in toplev.c,
514 but moving this call to init_alias_analysis is more efficient. */
517 /* See if we went too far. Note that get_max_uid already returns
518 one more that the maximum uid of all insn. */
521 /* Now reset it to the actual size we need. See above. */
524 /* find_and_verify_loops has already called compute_luids, but it
525 might have rearranged code afterwards, so we need to recompute
526 the luids now. */
529 /* Don't leave gaps in uid_luid for insns that have been
530 deleted. It is possible that the first or last insn
531 using some register has been deleted by cross-jumping.
532 Make sure that uid_luid for that former insn's uid
533 points to the general area where that insn used to be. */
535 {
539 }
544 /* Determine if the function has indirect jump. On some systems
545 this prevents low overhead loop instructions from being used. */
548 /* Now scan the loops, last ones first, since this means inner ones are done
549 before outer ones. */
551 {
556 }
560 /* Clean up. */
565 }
566 \f
567 /* Returns the next insn, in execution order, after INSN. START and
568 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
569 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
570 insn-stream; it is used with loops that are entered near the
571 bottom. */
573 static rtx
576 rtx insn;
577 {
581 {
583 /* Go to the top of the loop, and continue there. */
585 else
586 /* We're done. */
588 }
591 /* We're done. */
595 }
597 /* Optimize one loop described by LOOP. */
599 /* ??? Could also move memory writes out of loops if the destination address
600 is invariant, the source is invariant, the memory write is not volatile,
601 and if we can prove that no read inside the loop can read this address
602 before the write occurs. If there is a read of this address after the
603 write, then we can also mark the memory read as invariant. */
605 static void
609 {
615 rtx p;
616 /* 1 if we are scanning insns that could be executed zero times. */
618 /* 1 if we are scanning insns that might never be executed
619 due to a subroutine call which might exit before they are reached. */
621 /* Number of insns in the loop. */
625 /* The SET from an insn, if it is the only SET in the insn. */
627 /* Chain describing insns movable in current loop. */
629 /* Ratio of extra register life span we can justify
630 for saving an instruction. More if loop doesn't call subroutines
631 since in that case saving an insn makes more difference
632 and more registers are available. */
634 /* Nonzero if we are scanning instructions in a sub-loop. */
643 /* Determine whether this loop starts with a jump down to a test at
644 the end. This will occur for a small number of loops with a test
645 that is too complex to duplicate in front of the loop.
647 We search for the first insn or label in the loop, skipping NOTEs.
648 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
649 (because we might have a loop executed only once that contains a
650 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
651 (in case we have a degenerate loop).
653 Note that if we mistakenly think that a loop is entered at the top
654 when, in fact, it is entered at the exit test, the only effect will be
655 slightly poorer optimization. Making the opposite error can generate
656 incorrect code. Since very few loops now start with a jump to the
657 exit test, the code here to detect that case is very conservative. */
660 p != loop_end
666 ;
670 /* If loop end is the end of the current function, then emit a
671 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
672 note insn. This is the position we use when sinking insns out of
673 the loop. */
676 else
679 /* Set up variables describing this loop. */
683 /* If loop has a jump before the first label,
684 the true entry is the target of that jump.
685 Start scan from there.
686 But record in LOOP->TOP the place where the end-test jumps
687 back to so we can scan that after the end of the loop. */
689 /* Loop entry must be unconditional jump (and not a RETURN) */
692 /* Check to see whether the jump actually
693 jumps out of the loop (meaning it's no loop).
694 This case can happen for things like
695 do {..} while (0). If this label was generated previously
696 by loop, we can't tell anything about it and have to reject
697 the loop. */
699 {
702 }
704 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
705 as required by loop_reg_used_before_p. So skip such loops. (This
706 test may never be true, but it's best to play it safe.)
708 Also, skip loops where we do not start scanning at a label. This
709 test also rejects loops starting with a JUMP_INSN that failed the
710 test above. */
714 {
719 }
721 /* Allocate extra space for REGs that might be created by load_mems.
722 We allocate a little extra slop as well, in the hopes that we
723 won't have to reallocate the regs array. */
728 {
734 }
736 /* Scan through the loop finding insns that are safe to move.
737 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
738 this reg will be considered invariant for subsequent insns.
739 We consider whether subsequent insns use the reg
740 in deciding whether it is worth actually moving.
742 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
743 and therefore it is possible that the insns we are scanning
744 would never be executed. At such times, we must make sure
745 that it is safe to execute the insn once instead of zero times.
746 When MAYBE_NEVER is 0, all insns will be executed at least once
747 so that is not a problem. */
752 {
754 in_libcall--;
756 {
759 in_libcall++;
763 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
765 #endif
767 {
775 /* Figure out what to use as a source of this insn. If a
776 REG_EQUIV note is given or if a REG_EQUAL note with a
777 constant operand is specified, use it as the source and
778 mark that we should move this insn by calling
779 emit_move_insn rather that duplicating the insn.
781 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
782 note is present. */
786 else
787 {
792 {
794 /* A libcall block can use regs that don't appear in
795 the equivalent expression. To move the libcall,
796 we must move those regs too. */
798 }
799 }
801 /* For parallels, add any possible uses to the dependencies, as
802 we can't move the insn without resolving them first. */
804 {
806 {
809 dependencies
811 dependencies);
812 }
813 }
816 than the one where it is set (meaning that
817 something after this point in the loop might
818 depend on its value before the set). */
820 /* And the set is not guaranteed to be executed once
821 the loop starts, or the value before the set is
822 needed before the set occurs...
824 ??? Note we have quadratic behavior here, mitigated
825 by the fact that the previous test will often fail for
826 large loops. Rather than re-scanning the entire loop
827 each time for register usage, we should build tables
828 of the register usage and use them here instead. */
829 && (maybe_never
831 /* It is unsafe to move the set. However, it may be OK to
832 move the source into a new psuedo, and subsitute a
833 reg-to-reg copy for the original insn.
835 This code used to consider it OK to move a set of a variable
836 which was not created by the user and not used in an exit
837 test.
838 That behavior is incorrect and was removed. */
841 /* Don't try to optimize a register that was made
842 by loop-optimization for an inner loop.
843 We don't know its life-span, so we can't compute
844 the benefit. */
846 ;
847 /* Don't move the source and add a reg-to-reg copy with -Os
848 (this certainly increases size) or if the source is
849 already a reg (the motion will gain nothing). */
854 ;
857 || (tem2
860 || (tem1
861 = consec_sets_invariant_p
864 p)))
865 /* If the insn can cause a trap (such as divide by zero),
866 can't move it unless it's guaranteed to be executed
867 once loop is entered. Even a function call might
868 prevent the trap insn from being reached
869 (since it might exit!) */
872 {
876 /* A potential lossage is where we have a case where two insns
877 can be combined as long as they are both in the loop, but
878 we move one of them outside the loop. For large loops,
879 this can lose. The most common case of this is the address
880 of a function being called.
882 Therefore, if this register is marked as being used
883 exactly once if we are in a loop with calls
884 (a "large loop"), see if we can replace the usage of
885 this register with the source of this SET. If we can,
886 delete this insn.
888 Don't do this if P has a REG_RETVAL note or if we have
889 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
901 && (! SMALL_REGISTER_CLASSES
905 /* This test is not redundant; SET_SRC (set) might be
906 a call-clobbered register and the life of REGNO
907 might span a call. */
914 {
915 /* Replace any usage in a REG_EQUAL note. Must copy
916 the new source, so that we don't get rtx sharing
917 between the SET_SOURCE and REG_NOTES of insn p. */
919 = (replace_rtx
925 i++)
928 }
937 m->consec
948 /* Set M->cond if either loop_invariant_p
949 or consec_sets_invariant_p returned 2
950 (only conditionally invariant). */
960 /* Add M to the end of the chain MOVABLES. */
964 {
965 /* It is possible for the first instruction to have a
966 REG_EQUAL note but a non-invariant SET_SRC, so we must
967 remember the status of the first instruction in case
968 the last instruction doesn't have a REG_EQUAL note. */
971 /* Skip this insn, not checking REG_LIBCALL notes. */
973 /* Skip the consecutive insns, if there are any. */
975 /* Back up to the last insn of the consecutive group. */
978 /* We must now reset m->move_insn, m->is_equiv, and
979 possibly m->set_src to correspond to the effects of
980 all the insns. */
984 else
985 {
989 else
992 }
993 m->is_equiv
995 }
996 }
997 /* If this register is always set within a STRICT_LOW_PART
998 or set to zero, then its high bytes are constant.
999 So clear them outside the loop and within the loop
1000 just load the low bytes.
1001 We must check that the machine has an instruction to do so.
1002 Also, if the value loaded into the register
1003 depends on the same register, this cannot be done. */
1013 {
1016 {
1031 /* If the insn may not be executed on some cycles,
1032 we can't clear the whole reg; clear just high part.
1033 Not even if the reg is used only within this loop.
1034 Consider this:
1035 while (1)
1036 while (s != t) {
1037 if (foo ()) x = *s;
1038 use (x);
1039 }
1040 Clearing x before the inner loop could clobber a value
1041 being saved from the last time around the outer loop.
1042 However, if the reg is not used outside this loop
1043 and all uses of the register are in the same
1044 basic block as the store, there is no problem.
1046 If this insn was made by loop, we don't know its
1047 INSN_LUID and hence must make a conservative
1048 assumption. */
1051 || (labels_in_range_p
1055 else
1064 i++)
1066 /* Add M to the end of the chain MOVABLES. */
1068 }
1069 }
1070 }
1071 }
1072 /* Past a call insn, we get to insns which might not be executed
1073 because the call might exit. This matters for insns that trap.
1074 Constant and pure call insns always return, so they don't count. */
1077 /* Past a label or a jump, we get to insns for which we
1078 can't count on whether or how many times they will be
1079 executed during each iteration. Therefore, we can
1080 only move out sets of trivial variables
1081 (those not used after the loop). */
1082 /* Similar code appears twice in strength_reduce. */
1084 /* If we enter the loop in the middle, and scan around to the
1085 beginning, don't set maybe_never for that. This must be an
1086 unconditional jump, otherwise the code at the top of the
1087 loop might never be executed. Unconditional jumps are
1088 followed by a barrier then the loop_end. */
1094 {
1095 /* At the virtual top of a converted loop, insns are again known to
1096 be executed: logically, the loop begins here even though the exit
1097 code has been duplicated. */
1101 loop_depth++;
1103 loop_depth--;
1104 }
1105 }
1107 /* If one movable subsumes another, ignore that other. */
1111 /* For each movable insn, see if the reg that it loads
1112 leads when it dies right into another conditionally movable insn.
1113 If so, record that the second insn "forces" the first one,
1114 since the second can be moved only if the first is. */
1118 /* See if there are multiple movable insns that load the same value.
1119 If there are, make all but the first point at the first one
1120 through the `match' field, and add the priorities of them
1121 all together as the priority of the first. */
1125 /* Now consider each movable insn to decide whether it is worth moving.
1126 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1128 For machines with few registers this increases code size, so do not
1129 move moveables when optimizing for code size on such machines.
1130 (The 18 below is the value for i386.) */
1134 {
1137 /* Recalculate regs->array if move_movables has created new
1138 registers. */
1140 {
1146 ;
1151 }
1152 }
1154 /* Now candidates that still are negative are those not moved.
1155 Change regs->array[I].set_in_loop to indicate that those are not actually
1156 invariant. */
1161 /* Now that we've moved some things out of the loop, we might be able to
1162 hoist even more memory references. */
1165 /* Recalculate regs->array if load_mems has created new registers. */
1173 ;
1180 {
1182 /* Ensure our label doesn't go away. */
1193 }
1196 /* The movable information is required for strength reduction. */
1202 }
1203 \f
1204 /* Add elements to *OUTPUT to record all the pseudo-regs
1205 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1207 void
1211 {
1219 {
1237 }
1241 {
1245 {
1254 }
1255 }
1256 }
1257 \f
1258 /* Check what regs are referred to in the libcall block ending with INSN,
1259 aside from those mentioned in the equivalent value.
1260 If there are none, return 0.
1261 If there are one or more, return an EXPR_LIST containing all of them. */
1263 rtx
1266 {
1271 /* First, find all the regs used in the libcall block
1272 that are not mentioned as inputs to the result. */
1275 {
1280 }
1283 }
1284 \f
1285 /* Return 1 if all uses of REG
1286 are between INSN and the end of the basic block. */
1288 static int
1291 {
1293 rtx p;
1298 /* Search this basic block for the already recorded last use of the reg. */
1300 {
1302 {
1308 /* Ordinary insn: if this is the last use, we win. */
1314 /* Jump insn: if this is the last use, we win. */
1317 /* Otherwise, it's the end of the basic block, so we lose. */
1322 /* It's the end of the basic block, so we lose. */
1327 }
1328 }
1330 /* The "last use" that was recorded can't be found after the first
1331 use. This can happen when the last use was deleted while
1332 processing an inner loop, this inner loop was then completely
1333 unrolled, and the outer loop is always exited after the inner loop,
1334 so that everything after the first use becomes a single basic block. */
1336 }
1337 \f
1338 /* Compute the benefit of eliminating the insns in the block whose
1339 last insn is LAST. This may be a group of insns used to compute a
1340 value directly or can contain a library call. */
1342 static int
1344 rtx last;
1345 {
1346 rtx insn;
1351 {
1354 routine. */
1358 benefit++;
1359 }
1362 }
1363 \f
1364 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1366 static rtx
1368 rtx insn;
1370 {
1372 {
1373 rtx temp;
1375 /* If first insn of libcall sequence, skip to end. */
1376 /* Do this at start of loop, since INSN is guaranteed to
1377 be an insn here. */
1382 do
1385 }
1388 }
1390 /* Ignore any movable whose insn falls within a libcall
1391 which is part of another movable.
1392 We make use of the fact that the movable for the libcall value
1393 was made later and so appears later on the chain. */
1395 static void
1398 {
1402 {
1403 /* Is this a movable for the value of a libcall? */
1406 {
1407 rtx insn;
1408 /* Check for earlier movables inside that range,
1409 and mark them invalid. We cannot use LUIDs here because
1410 insns created by loop.c for prior loops don't have LUIDs.
1411 Rather than reject all such insns from movables, we just
1412 explicitly check each insn in the libcall (since invariant
1413 libcalls aren't that common). */
1418 }
1419 }
1420 }
1422 /* For each movable insn, see if the reg that it loads
1423 leads when it dies right into another conditionally movable insn.
1424 If so, record that the second insn "forces" the first one,
1425 since the second can be moved only if the first is. */
1427 static void
1430 {
1434 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1436 {
1439 /* ??? Could this be a bug? What if CSE caused the
1440 register of M1 to be used after this insn?
1441 Since CSE does not update regno_last_uid,
1442 this insn M->insn might not be where it dies.
1443 But very likely this doesn't matter; what matters is
1444 that M's reg is computed from M1's reg. */
1449 /* If m->consec, m->set_src isn't valid. */
1453 /* Increase the priority of the moving the first insn
1454 since it permits the second to be moved as well. */
1456 {
1460 }
1461 }
1462 }
1463 \f
1464 /* Find invariant expressions that are equal and can be combined into
1465 one register. */
1467 static void
1471 {
1476 /* Regs that are set more than once are not allowed to match
1477 or be matched. I'm no longer sure why not. */
1478 /* Only pseudo registers are allowed to match or be matched,
1479 since move_movables does not validate the change. */
1480 /* Perhaps testing m->consec_sets would be more appropriate here? */
1487 {
1494 /* We want later insns to match the first one. Don't make the first
1495 one match any later ones. So start this loop at m->next. */
1501 /* A reg used outside the loop mustn't be eliminated. */
1503 /* A reg used for zero-extending mustn't be eliminated. */
1506 ||
1507 (
1508 /* Can combine regs with different modes loaded from the
1509 same constant only if the modes are the same or
1510 if both are integer modes with M wider or the same
1511 width as M1. The check for integer is redundant, but
1512 safe, since the only case of differing destination
1513 modes with equal sources is when both sources are
1514 VOIDmode, i.e., CONST_INT. */
1520 /* See if the source of M1 says it matches M. */
1527 {
1533 }
1534 }
1536 /* Now combine the regs used for zero-extension.
1537 This can be done for those not marked `global'
1538 provided their lives don't overlap. */
1542 {
1545 /* Combine all the registers for extension from mode MODE.
1546 Don't combine any that are used outside this loop. */
1550 {
1557 {
1558 /* First one: don't check for overlap, just record it. */
1561 }
1563 /* Make sure they extend to the same mode.
1564 (Almost always true.) */
1568 /* We already have one: check for overlap with those
1569 already combined together. */
1576 /* No overlap: we can combine this with the others. */
1582 overlap:
1583 ;
1584 }
1585 }
1587 /* Clean up. */
1589 }
1591 /* Returns the number of movable instructions in LOOP that were not
1592 moved outside the loop. */
1594 static int
1597 {
1606 }
1608 \f
1609 /* Return 1 if regs X and Y will become the same if moved. */
1611 static int
1615 {
1632 }
1634 /* Return 1 if X and Y are identical-looking rtx's.
1635 This is the Lisp function EQUAL for rtx arguments.
1637 If two registers are matching movables or a movable register and an
1638 equivalent constant, consider them equal. */
1640 static int
1645 {
1659 /* If we have a register and a constant, they may sometimes be
1660 equal. */
1663 {
1668 }
1671 {
1676 }
1678 /* Otherwise, rtx's of different codes cannot be equal. */
1682 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1683 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1688 /* These three types of rtx's can be compared nonrecursively. */
1697 /* Compare the elements. If any pair of corresponding elements
1698 fail to match, return 0 for the whole things. */
1702 {
1704 {
1716 /* Two vectors must have the same length. */
1720 /* And the corresponding elements must match. */
1739 /* These are just backpointers, so they don't matter. */
1745 /* It is believed that rtx's at this level will never
1746 contain anything but integers and other rtx's,
1747 except for within LABEL_REFs and SYMBOL_REFs. */
1750 }
1751 }
1753 }
1754 \f
1755 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1756 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1757 references is incremented once for each added note. */
1759 static void
1761 rtx x;
1762 rtx insns;
1763 {
1767 rtx insn;
1770 {
1771 /* This code used to ignore labels that referred to dispatch tables to
1772 avoid flow generating (slighly) worse code.
1774 We no longer ignore such label references (see LABEL_REF handling in
1775 mark_jump_label for additional information). */
1778 {
1783 }
1784 }
1788 {
1794 }
1795 }
1796 \f
1797 /* Scan MOVABLES, and move the insns that deserve to be moved.
1798 If two matching movables are combined, replace one reg with the
1799 other throughout. */
1801 static void
1807 {
1812 rtx p;
1815 /* Map of pseudo-register replacements to handle combining
1816 when we move several insns that load the same value
1817 into different pseudo-registers. */
1822 {
1823 /* Describe this movable insn. */
1826 {
1847 }
1849 /* Ignore the insn if it's already done (it matched something else).
1850 Otherwise, see if it is now safe to move. */
1862 {
1864 rtx p;
1867 /* We have an insn that is safe to move.
1868 Compute its desirability. */
1879 /* An insn MUST be moved if we already moved something else
1880 which is safe only if this one is moved too: that is,
1881 if already_moved[REGNO] is nonzero. */
1883 /* An insn is desirable to move if the new lifetime of the
1884 register is no more than THRESHOLD times the old lifetime.
1885 If it's not desirable, it means the loop is so big
1886 that moving won't speed things up much,
1887 and it is liable to make register usage worse. */
1889 /* It is also desirable to move if it can be moved at no
1890 extra cost because something else was already moved. */
1893 || flag_move_all_movables
1898 {
1907 /* Now move the insns that set the reg. */
1910 {
1913 /* Find the end of this chain of matching regs.
1914 Thus, we load each reg in the chain from that one reg.
1915 And that reg is loaded with 0 directly,
1916 since it has ->match == 0. */
1922 /* Mark the moved, invariant reg as being allowed to
1923 share a hard reg with the other matching invariant. */
1927 regs_may_share
1930 regs_may_share));
1938 }
1939 /* If we are to re-generate the item being moved with a
1940 new move insn, first delete what we have and then emit
1941 the move insn before the loop. */
1943 {
1947 {
1948 /* If this is the first insn of a library call sequence,
1949 something is very wrong. */
1954 /* If this is the last insn of a libcall sequence, then
1955 delete every insn in the sequence except the last.
1956 The last insn is handled in the normal manner. */
1959 {
1963 }
1968 /* simplify_giv_expr expects that it can walk the insns
1969 at m->insn forwards and see this old sequence we are
1970 tossing here. delete_insn does preserve the next
1971 pointers, but when we skip over a NOTE we must fix
1972 it up. Otherwise that code walks into the non-deleted
1973 insn stream. */
1978 {
1979 /* Replace the original insn with a move from
1980 our newly created temp. */
1986 }
1987 }
2006 /* The more regs we move, the less we like moving them. */
2008 }
2009 else
2010 {
2012 {
2015 /* If first insn of libcall sequence, skip to end. */
2016 /* Do this at start of loop, since p is guaranteed to
2017 be an insn here. */
2022 /* If last insn of libcall sequence, move all
2023 insns except the last before the loop. The last
2024 insn is handled in the normal manner. */
2027 {
2035 {
2036 rtx body;
2037 rtx n;
2038 rtx next;
2045 /* Find the next insn after TEMP,
2046 not counting USE or NOTE insns. */
2054 /* If that is the call, this may be the insn
2055 that loads the function address.
2057 Extract the function address from the insn
2058 that loads it into a register.
2059 If this insn was cse'd, we get incorrect code.
2061 So emit a new move insn that copies the
2062 function address into the register that the
2063 call insn will use. flow.c will delete any
2064 redundant stores that we have created. */
2069 NULL_RTX)))
2070 {
2076 }
2077 /* We have the call insn.
2078 If it uses the register we suspect it might,
2079 load it with the correct address directly. */
2084 gen_move_insn
2088 {
2090 /* Because the USAGE information potentially
2091 contains objects other than hard registers
2092 we need to copy it. */
2096 }
2097 else
2106 }
2109 }
2111 {
2112 /* P sets REG to zero; but we should clear only
2113 the bits that are not covered by the mode
2114 m->savemode. */
2116 rtx sequence;
2117 rtx tem;
2120 tem = expand_simple_binop
2133 }
2135 {
2137 /* Because the USAGE information potentially
2138 contains objects other than hard registers
2139 we need to copy it. */
2143 }
2145 {
2146 rtx seq;
2147 /* The SET_SRC might not be invariant, so we must
2148 use the REG_EQUAL note. */
2160 }
2162 {
2170 }
2171 else
2175 {
2179 /* If there is a REG_EQUAL note present whose value
2180 is not loop invariant, then delete it, since it
2181 may cause problems with later optimization passes.
2182 It is possible for cse to create such notes
2183 like this as a result of record_jump_cond. */
2188 }
2197 /* If library call, now fix the REG_NOTES that contain
2198 insn pointers, namely REG_LIBCALL on FIRST
2199 and REG_RETVAL on I1. */
2201 {
2205 }
2211 /* simplify_giv_expr expects that it can walk the insns
2212 at m->insn forwards and see this old sequence we are
2213 tossing here. delete_insn does preserve the next
2214 pointers, but when we skip over a NOTE we must fix
2215 it up. Otherwise that code walks into the non-deleted
2216 insn stream. */
2221 {
2222 rtx seq;
2223 /* Replace the original insn with a move from
2224 our newly created temp. */
2230 }
2231 }
2233 /* The more regs we move, the less we like moving them. */
2235 }
2240 {
2241 /* Any other movable that loads the same register
2242 MUST be moved. */
2245 /* This reg has been moved out of one loop. */
2248 /* The reg set here is now invariant. */
2250 {
2254 }
2256 /* Change the length-of-life info for the register
2257 to say it lives at least the full length of this loop.
2258 This will help guide optimizations in outer loops. */
2261 /* This is the old insn before all the moved insns.
2262 We can't use the moved insn because it is out of range
2263 in uid_luid. Only the old insns have luids. */
2267 }
2269 /* Combine with this moved insn any other matching movables. */
2274 {
2275 rtx temp;
2277 /* Schedule the reg loaded by M1
2278 for replacement so that shares the reg of M.
2279 If the modes differ (only possible in restricted
2280 circumstances, make a SUBREG.
2282 Note this assumes that the target dependent files
2283 treat REG and SUBREG equally, including within
2284 GO_IF_LEGITIMATE_ADDRESS and in all the
2285 predicates since we never verify that replacing the
2286 original register with a SUBREG results in a
2287 recognizable insn. */
2290 else
2295 /* Get rid of the matching insn
2296 and prevent further processing of it. */
2299 /* if library call, delete all insns. */
2301 NULL_RTX)))
2303 else
2306 /* Any other movable that loads the same register
2307 MUST be moved. */
2310 /* The reg merged here is now invariant,
2311 if the reg it matches is invariant. */
2313 {
2317 i++)
2319 }
2320 }
2321 }
2324 }
2330 }
2335 /* Go through all the instructions in the loop, making
2336 all the register substitutions scheduled in REG_MAP. */
2340 {
2344 }
2346 /* Clean up. */
2349 }
2352 static void
2356 {
2359 else
2362 }
2365 static void
2368 {
2373 {
2376 }
2377 }
2378 \f
2379 #if 0
2380 /* Scan X and replace the address of any MEM in it with ADDR.
2381 REG is the address that MEM should have before the replacement. */
2383 static void
2386 {
2395 {
2407 /* Short cut for very common case. */
2412 /* Short cut for very common case. */
2417 /* If this MEM uses a reg other than the one we expected,
2418 something is wrong. */
2426 }
2430 {
2434 {
2438 }
2439 }
2440 }
2441 #endif
2442 \f
2443 /* Return the number of memory refs to addresses that vary
2444 in the rtx X. */
2446 static int
2449 rtx x;
2450 {
2461 {
2478 }
2483 {
2487 {
2491 }
2492 }
2494 }
2495 \f
2496 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2497 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2498 `unknown_address_altered', `unknown_constant_address_altered', and
2499 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2500 list `store_mems' in LOOP. */
2502 static void
2505 {
2507 rtx insn;
2511 /* The label after END. Jumping here is just like falling off the
2512 end of the loop. We use next_nonnote_insn instead of next_label
2513 as a hedge against the (pathological) case where some actual insn
2514 might end up between the two. */
2533 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2538 {
2540 {
2543 }
2544 }
2548 {
2550 {
2553 {
2555 /* Count number of loops contained in this one. */
2557 }
2564 {
2567 }
2577 {
2581 {
2586 {
2589 }
2590 else
2591 {
2594 }
2596 do
2597 {
2599 {
2601 {
2602 /* Something tricky. */
2605 }
2608 {
2609 /* A jump outside the current loop. */
2612 }
2613 }
2617 }
2619 }
2620 else
2621 {
2622 /* A return, or something tricky. */
2624 }
2625 }
2626 /* FALLTHRU */
2647 }
2648 }
2650 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2652 anywhere. */
2654 /* We don't want loads for MEMs moved to a location before the
2655 one at which their stack memory becomes allocated. (Note
2656 that this is not a problem for malloc, etc., since those
2657 require actual function calls. */
2658 && ! current_function_calls_alloca
2659 /* There are ways to leave the loop other than falling off the
2660 end. */
2666 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2667 that loop_invariant_p and load_mems can use true_dependence
2668 to determine what is really clobbered. */
2670 {
2673 loop_info->store_mems
2675 }
2677 {
2681 loop_info->store_mems
2683 }
2684 }
2685 \f
2686 /* Invalidate all loops containing LABEL. */
2688 static void
2690 rtx label;
2691 {
2695 }
2697 /* Scan the function looking for loops. Record the start and end of each loop.
2698 Also mark as invalid loops any loops that contain a setjmp or are branched
2699 to from outside the loop. */
2701 static void
2703 rtx f;
2705 {
2706 rtx insn;
2707 rtx label;
2717 /* If there are jumps to undefined labels,
2718 treat them as jumps out of any/all loops.
2719 This also avoids writing past end of tables when there are no loops. */
2722 /* Find boundaries of loops, mark which loops are contained within
2723 loops, and invalidate loops that have setjmp. */
2728 {
2731 {
2735 num_loops++;
2759 }
2763 {
2764 /* In this case, we must invalidate our current loop and any
2765 enclosing loop. */
2767 {
2773 }
2774 }
2776 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2777 enclosing loop, but this doesn't matter. */
2779 }
2781 /* Any loop containing a label used in an initializer must be invalidated,
2782 because it can be jumped into from anywhere. */
2786 /* Any loop containing a label used for an exception handler must be
2787 invalidated, because it can be jumped into from anywhere. */
2790 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2791 loop that it is not contained within, that loop is marked invalid.
2792 If any INSN or CALL_INSN uses a label's address, then the loop containing
2793 that label is marked invalid, because it could be jumped into from
2794 anywhere.
2796 Also look for blocks of code ending in an unconditional branch that
2797 exits the loop. If such a block is surrounded by a conditional
2798 branch around the block, move the block elsewhere (see below) and
2799 invert the jump to point to the code block. This may eliminate a
2800 label in our loop and will simplify processing by both us and a
2801 possible second cse pass. */
2805 {
2809 {
2813 }
2820 /* See if this is an unconditional branch outside the loop. */
2828 {
2829 rtx p;
2835 /* Go backwards until we reach the start of the loop, a label,
2836 or a JUMP_INSN. */
2843 ;
2845 /* Check for the case where we have a jump to an inner nested
2846 loop, and do not perform the optimization in that case. */
2849 {
2852 {
2857 }
2858 }
2860 /* Make sure that the target of P is within the current loop. */
2866 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2867 we have a block of code to try to move.
2869 We look backward and then forward from the target of INSN
2870 to find a BARRIER at the same loop depth as the target.
2871 If we find such a BARRIER, we make a new label for the start
2872 of the block, invert the jump in P and point it to that label,
2873 and move the block of code to the spot we found. */
2878 /* Just ignore jumps to labels that were never emitted.
2879 These always indicate compilation errors. */
2883 /* If it's not safe to move the sequence, then we
2884 mustn't try. */
2887 {
2888 rtx target
2892 rtx tmp;
2894 /* Search for possible garbage past the conditional jumps
2895 and look for the last barrier. */
2903 /* Don't move things inside a tablejump. */
2916 /* Don't move things inside a tablejump. */
2927 {
2931 /* Ensure our label doesn't go away. */
2934 /* Verify that uid_loop is large enough and that
2935 we can invert P. */
2937 {
2940 /* If no suitable BARRIER was found, create a suitable
2941 one before TARGET. Since TARGET is a fall through
2942 path, we'll need to insert a jump around our block
2943 and add a BARRIER before TARGET.
2945 This creates an extra unconditional jump outside
2946 the loop. However, the benefits of removing rarely
2947 executed instructions from inside the loop usually
2948 outweighs the cost of the extra unconditional jump
2949 outside the loop. */
2951 {
2952 rtx temp;
2959 }
2961 /* Include the BARRIER after INSN and copy the
2962 block after LOC. */
2967 /* All those insns are now in TARGET_LOOP. */
2973 /* The label jumped to by INSN is no longer a loop
2974 exit. Unless INSN does not have a label (e.g.,
2975 it is a RETURN insn), search loop->exit_labels
2976 to find its label_ref, and remove it. Also turn
2977 off LABEL_OUTSIDE_LOOP_P bit. */
2979 {
2981 r;
2984 {
2988 else
2991 }
2997 /* If we didn't find it, then something is
2998 wrong. */
3001 }
3003 /* P is now a jump outside the loop, so it must be put
3004 in loop->exit_labels, and marked as such.
3005 The easiest way to do this is to just call
3006 mark_loop_jump again for P. */
3009 /* If INSN now jumps to the insn after it,
3010 delete INSN. */
3015 }
3017 /* Continue the loop after where the conditional
3018 branch used to jump, since the only branch insn
3019 in the block (if it still remains) is an inter-loop
3020 branch and hence needs no processing. */
3026 /* This loop will be continued with NEXT_INSN (insn). */
3028 }
3029 }
3030 }
3031 }
3032 }
3034 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3035 loops it is contained in, mark the target loop invalid.
3037 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3039 static void
3041 rtx x;
3043 {
3049 {
3061 /* There could be a label reference in here. */
3073 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3085 /* Link together all labels that branch outside the loop. This
3086 is used by final_[bg]iv_value and the loop unrolling code. Also
3087 mark this LABEL_REF so we know that this branch should predict
3088 false. */
3090 /* A check to make sure the label is not in an inner nested loop,
3091 since this does not count as a loop exit. */
3093 {
3098 }
3099 else
3103 {
3112 }
3114 /* If this is inside a loop, but not in the current loop or one enclosed
3115 by it, it invalidates at least one loop. */
3120 /* We must invalidate every nested loop containing the target of this
3121 label, except those that also contain the jump insn. */
3124 {
3125 /* Stop when we reach a loop that also contains the jump insn. */
3130 /* If we get here, we know we need to invalidate a loop. */
3137 }
3141 /* If this is not setting pc, ignore. */
3163 /* Strictly speaking this is not a jump into the loop, only a possible
3164 jump out of the loop. However, we have no way to link the destination
3165 of this jump onto the list of exit labels. To be safe we mark this
3166 loop and any containing loops as invalid. */
3168 {
3170 {
3176 }
3177 }
3179 }
3180 }
3181 \f
3182 /* Return nonzero if there is a label in the range from
3183 insn INSN to and including the insn whose luid is END
3184 INSN must have an assigned luid (i.e., it must not have
3185 been previously created by loop.c). */
3187 static int
3189 rtx insn;
3191 {
3193 {
3197 }
3200 }
3202 /* Record that a memory reference X is being set. */
3204 static void
3206 rtx x;
3207 rtx y ATTRIBUTE_UNUSED;
3209 {
3215 /* Count number of memory writes.
3216 This affects heuristics in strength_reduce. */
3219 /* BLKmode MEM means all memory is clobbered. */
3221 {
3224 else
3228 }
3232 }
3234 /* X is a value modified by an INSN that references a biv inside a loop
3235 exit test (ie, X is somehow related to the value of the biv). If X
3236 is a pseudo that is used more than once, then the biv is (effectively)
3237 used more than once. DATA is a pointer to a loop_regs structure. */
3239 static void
3241 rtx x;
3242 rtx y ATTRIBUTE_UNUSED;
3244 {
3259 /* If we do not have usage information, or if we know the register
3260 is used more than once, note that fact for check_dbra_loop. */
3265 }
3266 \f
3267 /* Return nonzero if the rtx X is invariant over the current loop.
3269 The value is 2 if we refer to something only conditionally invariant.
3271 A memory ref is invariant if it is not volatile and does not conflict
3272 with anything stored in `loop_info->store_mems'. */
3274 int
3277 rtx x;
3278 {
3285 rtx mem_list_entry;
3291 {
3299 /* A LABEL_REF is normally invariant, however, if we are unrolling
3300 loops, and this label is inside the loop, then it isn't invariant.
3301 This is because each unrolled copy of the loop body will have
3302 a copy of this label. If this was invariant, then an insn loading
3303 the address of this label into a register might get moved outside
3304 the loop, and then each loop body would end up using the same label.
3306 We don't know the loop bounds here though, so just fail for all
3307 labels. */
3310 else
3319 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3320 since the reg might be set by initialization within the loop. */
3331 /* Out-of-range regs can occur when we are called from unrolling.
3332 These have always been created by the unroller and are set in
3333 the loop, hence are never invariant. */
3344 /* Volatile memory references must be rejected. Do this before
3345 checking for read-only items, so that volatile read-only items
3346 will be rejected also. */
3350 /* See if there is any dependence between a store and this load. */
3353 {
3359 }
3361 /* It's not invalidated by a store in memory
3362 but we must still verify the address is invariant. */
3366 /* Don't mess with insns declared volatile. */
3373 }
3377 {
3379 {
3385 }
3387 {
3390 {
3396 }
3398 }
3399 }
3402 }
3403 \f
3404 /* Return nonzero if all the insns in the loop that set REG
3405 are INSN and the immediately following insns,
3406 and if each of those insns sets REG in an invariant way
3407 (not counting uses of REG in them).
3409 The value is 2 if some of these insns are only conditionally invariant.
3411 We assume that INSN itself is the first set of REG
3412 and that its source is invariant. */
3414 static int
3419 {
3423 rtx temp;
3424 /* Number of sets we have to insist on finding after INSN. */
3430 /* If N_SETS hit the limit, we can't rely on its value. */
3437 {
3439 rtx set;
3444 /* If library call, skip to end of it. */
3453 {
3458 {
3459 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3460 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3461 notes are OK. */
3467 }
3468 }
3470 count--;
3472 {
3475 }
3476 }
3479 /* If loop_invariant_p ever returned 2, we return 2. */
3481 }
3483 #if 0
3484 /* I don't think this condition is sufficient to allow INSN
3485 to be moved, so we no longer test it. */
3487 /* Return 1 if all insns in the basic block of INSN and following INSN
3488 that set REG are invariant according to TABLE. */
3490 static int
3494 {
3499 {
3508 {
3511 }
3512 }
3513 }
3515 \f
3516 /* Look at all uses (not sets) of registers in X. For each, if it is
3517 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3518 a different insn, set USAGE[REGNO] to const0_rtx. */
3520 static void
3523 rtx insn;
3524 rtx x;
3525 {
3537 {
3538 /* Don't count SET_DEST if it is a REG; otherwise count things
3539 in SET_DEST because if a register is partially modified, it won't
3540 show up as a potential movable so we don't care how USAGE is set
3541 for it. */
3545 }
3546 else
3548 {
3554 }
3555 }
3556 \f
3557 /* Count and record any set in X which is contained in INSN. Update
3558 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3559 in X. */
3561 static void
3566 {
3568 /* Don't move a reg that has an explicit clobber.
3569 It's not worth the pain to try to do it correctly. */
3573 {
3581 {
3585 {
3586 /* If this is the first setting of this reg
3587 in current basic block, and it was set before,
3588 it must be set in two basic blocks, so it cannot
3589 be moved out of the loop. */
3593 /* If this is not first setting in current basic block,
3594 see if reg was used in between previous one and this.
3595 If so, neither one can be moved. */
3602 }
3603 }
3604 }
3605 }
3606 \f
3607 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3608 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3609 contained in insn INSN is used by any insn that precedes INSN in
3610 cyclic order starting from the loop entry point.
3612 We don't want to use INSN_LUID here because if we restrict INSN to those
3613 that have a valid INSN_LUID, it means we cannot move an invariant out
3614 from an inner loop past two loops. */
3616 static int
3620 {
3622 rtx p;
3624 /* Scan forward checking for register usage. If we hit INSN, we
3625 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3627 {
3633 }
3636 }
3637 \f
3639 /* Information we collect about arrays that we might want to prefetch. */
3640 struct prefetch_info
3641 {
3645 index. */
3646 HOST_WIDE_INT index;
3648 iteration. */
3650 prefetch area in one iteration. */
3652 This is set only for loops with known
3653 iteration counts and is 0xffffffff
3654 otherwise. */
3658 };
3660 /* Data used by check_store function. */
3661 struct check_store_data
3662 {
3663 rtx mem_address;
3665 };
3671 /* Set mem_write when mem_address is found. Used as callback to
3672 note_stores. */
3673 static void
3677 {
3682 }
3683 \f
3684 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3685 important to get some addresses combined. Later more sophisticated
3686 transformations can be added when necessary.
3688 ??? Same trick with swapping operand is done at several other places.
3689 It can be nice to develop some common way to handle this. */
3691 static int
3694 {
3708 {
3713 }
3714 /* Compare the elements. If any pair of corresponding elements fails to
3715 match, return 0 for the whole thing. */
3719 {
3721 {
3733 /* Two vectors must have the same length. */
3737 /* And the corresponding elements must match. */
3755 /* These are just backpointers, so they don't matter. */
3761 /* It is believed that rtx's at this level will never
3762 contain anything but integers and other rtx's,
3763 except for within LABEL_REFs and SYMBOL_REFs. */
3766 }
3767 }
3769 }
3770 \f
3771 /* Remove constant addition value from the expression X (when present)
3772 and return it. */
3774 static HOST_WIDE_INT
3777 {
3781 /* Avoid clobbering a shared CONST expression. */
3783 {
3787 {
3790 }
3792 }
3795 {
3798 }
3800 /* For plus expression recurse on ourself. */
3802 {
3806 /* In case our parameter was constant, remove extra zero from the
3807 expression. */
3812 }
3815 }
3817 /* Attempt to identify accesses to arrays that are most likely to cause cache
3818 misses, and emit prefetch instructions a few prefetch blocks forward.
3820 To detect the arrays we use the GIV information that was collected by the
3821 strength reduction pass.
3823 The prefetch instructions are generated after the GIV information is done
3824 and before the strength reduction process. The new GIVs are injected into
3825 the strength reduction tables, so the prefetch addresses are optimized as
3826 well.
3828 GIVs are split into base address, stride, and constant addition values.
3829 GIVs with the same address, stride and close addition values are combined
3830 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3831 for write instructions can be used for the block we write to, on machines
3832 that support write prefetches.
3834 Several heuristics are used to determine when to prefetch. They are
3835 controlled by defined symbols that can be overridden for each target. */
3837 static void
3840 {
3856 /* Consider only loops w/o calls. When a call is done, the loop is probably
3857 slow enough to read the memory. */
3859 {
3864 }
3866 /* Don't prefetch in loops known to have few iterations. */
3870 {
3875 }
3877 /* Search all induction variables and pick those interesting for the prefetch
3878 machinery. */
3880 {
3886 /* Expect all BIVs to be executed in each iteration. This makes our
3887 analysis more conservative. */
3889 {
3890 /* Discard non-constant additions that we can't handle well yet, and
3891 BIVs that are executed multiple times; such BIVs ought to be
3892 handled in the nested loop. We accept not_every_iteration BIVs,
3893 since these only result in larger strides and make our
3894 heuristics more conservative. */
3896 {
3898 {
3904 }
3906 }
3909 {
3911 {
3917 }
3919 }
3923 }
3929 {
3930 rtx address;
3931 rtx temp;
3940 /* See whether an induction variable is interesting to us and if
3941 not, report the reason. */
3945 /* We are interested only in constant stride memory references
3946 in order to be able to compute density easily. */
3950 else
3951 {
3954 {
3957 }
3959 /* On some targets, reversed order prefetches are not
3960 worthwhile. */
3964 /* Prefetch of accesses with an extreme stride might not be
3965 worthwhile, either. */
3970 /* Ignore GIVs with varying add values; we can't predict the
3971 value for the next iteration. */
3975 /* Ignore GIVs in the nested loops; they ought to have been
3976 handled already. */
3979 }
3982 {
3988 }
3990 /* Determine the pointer to the basic array we are examining. It is
3991 the sum of the BIV's initial value and the GIV's add_val. */
4001 /* When the GIV is not always executed, we might be better off by
4002 not dirtying the cache pages. */
4005 else
4006 {
4011 }
4013 /* Attempt to find another prefetch to the same array and see if we
4014 can merge this one. */
4018 {
4019 /* In case both access same array (same location
4020 just with small difference in constant indexes), merge
4021 the prefetches. Just do the later and the earlier will
4022 get prefetched from previous iteration.
4023 The artificial threshold should not be too small,
4024 but also not bigger than small portion of memory usually
4025 traversed by single loop. */
4028 {
4037 }
4041 {
4046 }
4047 }
4049 /* Merging failed. */
4051 {
4059 num_prefetches++;
4061 {
4066 }
4067 }
4068 }
4069 }
4072 {
4075 /* Attempt to calculate the total number of bytes fetched by all
4076 iterations of the loop. Avoid overflow. */
4081 else
4086 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4091 {
4096 }
4097 else
4098 {
4104 }
4105 else
4108 /* Find how many prefetch instructions we'll use within the loop. */
4110 {
4116 }
4117 }
4119 /* Determine how many iterations ahead to prefetch within the loop, based
4120 on how many prefetches we currently expect to do within the loop. */
4122 {
4124 {
4130 }
4131 }
4132 /* We'll also use AHEAD to determine how many prefetch instructions to
4133 emit before a loop, so don't leave it zero. */
4138 {
4139 /* Update if we've decided not to prefetch anything within the loop. */
4143 /* Find how many prefetch instructions we'll use before the loop. */
4145 {
4153 }
4156 {
4178 }
4179 }
4182 {
4183 /* Record that this loop uses prefetch instructions. */
4187 {
4192 }
4193 }
4196 {
4200 {
4202 rtx insn;
4206 rtx seq;
4208 /* We can save some effort by offsetting the address on
4209 architectures with offsettable memory references. */
4212 else
4213 {
4219 }
4222 /* Make sure the address operand is valid for prefetch. */
4232 /* Check all insns emitted and record the new GIV
4233 information. */
4236 {
4241 }
4242 }
4245 {
4246 /* Emit insns before the loop to fetch the first cache lines or,
4247 if we're not prefetching within the loop, everything we expect
4248 to need. */
4250 {
4258 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4259 non-constant INIT_VAL to have the same mode as REG, which
4260 in this case we know to be Pmode. */
4262 {
4263 rtx seq;
4270 }
4276 loop_start);
4277 }
4278 }
4279 }
4282 }
4283 \f
4284 /* A "basic induction variable" or biv is a pseudo reg that is set
4285 (within this loop) only by incrementing or decrementing it. */
4286 /* A "general induction variable" or giv is a pseudo reg whose
4287 value is a linear function of a biv. */
4289 /* Bivs are recognized by `basic_induction_var';
4290 Givs by `general_induction_var'. */
4292 /* Communication with routines called via `note_stores'. */
4296 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4300 /* ??? Unfinished optimizations, and possible future optimizations,
4301 for the strength reduction code. */
4303 /* ??? The interaction of biv elimination, and recognition of 'constant'
4304 bivs, may cause problems. */
4306 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4307 performance problems.
4309 Perhaps don't eliminate things that can be combined with an addressing
4310 mode. Find all givs that have the same biv, mult_val, and add_val;
4311 then for each giv, check to see if its only use dies in a following
4312 memory address. If so, generate a new memory address and check to see
4313 if it is valid. If it is valid, then store the modified memory address,
4314 otherwise, mark the giv as not done so that it will get its own iv. */
4316 /* ??? Could try to optimize branches when it is known that a biv is always
4317 positive. */
4319 /* ??? When replace a biv in a compare insn, we should replace with closest
4320 giv so that an optimized branch can still be recognized by the combiner,
4321 e.g. the VAX acb insn. */
4323 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4324 was rerun in loop_optimize whenever a register was added or moved.
4325 Also, some of the optimizations could be a little less conservative. */
4326 \f
4327 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4328 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4329 callback.
4331 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4332 least once for every loop iteration except for the last one.
4334 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4335 loop iteration.
4336 */
4337 void
4340 loop_insn_callback fncall;
4341 {
4346 rtx p;
4348 /* If loop_scan_start points to the loop exit test, we have to be wary of
4349 subversive use of gotos inside expression statements. */
4353 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4357 {
4360 /* Past CODE_LABEL, we get to insns that may be executed multiple
4361 times. The only way we can be sure that they can't is if every
4362 jump insn between here and the end of the loop either
4363 returns, exits the loop, is a jump to a location that is still
4364 behind the label, or is a jump to the loop start. */
4367 {
4373 {
4378 {
4381 else
4385 }
4393 {
4396 }
4397 }
4398 }
4400 /* Past a jump, we get to insns for which we can't count
4401 on whether they will be executed during each iteration. */
4402 /* This code appears twice in strength_reduce. There is also similar
4403 code in scan_loop. */
4405 /* If we enter the loop in the middle, and scan around to the
4406 beginning, don't set not_every_iteration for that.
4407 This can be any kind of jump, since we want to know if insns
4408 will be executed if the loop is executed. */
4413 {
4416 /* If this is a jump outside the loop, then it also doesn't
4417 matter. Check to see if the target of this branch is on the
4418 loop->exits_labels list. */
4426 }
4429 {
4430 /* At the virtual top of a converted loop, insns are again known to
4431 be executed each iteration: logically, the loop begins here
4432 even though the exit code has been duplicated.
4434 Insns are also again known to be executed each iteration at
4435 the LOOP_CONT note. */
4441 loop_depth++;
4443 loop_depth--;
4444 }
4446 /* Note if we pass a loop latch. If we do, then we can not clear
4447 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4448 a loop since a jump before the last CODE_LABEL may have started
4449 a new loop iteration.
4451 Note that LOOP_TOP is only set for rotated loops and we need
4452 this check for all loops, so compare against the CODE_LABEL
4453 which immediately follows LOOP_START. */
4458 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4459 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4460 or not an insn is known to be executed each iteration of the
4461 loop, whether or not any iterations are known to occur.
4463 Therefore, if we have just passed a label and have no more labels
4464 between here and the test insn of the loop, and we have not passed
4465 a jump to the top of the loop, then we know these insns will be
4466 executed each iteration. */
4469 && !past_loop_latch
4474 }
4475 }
4476 \f
4477 static void
4480 {
4483 /* Temporary list pointers for traversing ivs->list. */
4490 /* Scan ivs->list to remove all regs that proved not to be bivs.
4491 Make a sanity check against regs->n_times_set. */
4493 {
4495 /* Above happens if register modified by subreg, etc. */
4496 /* Make sure it is not recognized as a basic induction var: */
4498 /* If never incremented, it is invariant that we decided not to
4499 move. So leave it alone. */
4501 {
4512 }
4513 else
4514 {
4519 }
4520 }
4521 }
4524 /* Determine how BIVS are initialized by looking through pre-header
4525 extended basic block. */
4526 static void
4529 {
4531 /* Temporary list pointers for traversing ivs->list. */
4534 rtx p;
4536 /* Find initial value for each biv by searching backwards from loop_start,
4537 halting at first label. Also record any test condition. */
4541 {
4542 rtx test;
4552 /* Record any test of a biv that branches around the loop if no store
4553 between it and the start of loop. We only care about tests with
4554 constants and registers and only certain of those. */
4564 {
4565 /* If an NE test, we have an initial value! */
4567 {
4571 }
4572 else
4574 }
4575 }
4576 }
4579 /* Look at the each biv and see if we can say anything better about its
4580 initial value from any initializing insns set up above. (This is done
4581 in two passes to avoid missing SETs in a PARALLEL.) */
4582 static void
4585 {
4587 /* Temporary list pointers for traversing ivs->list. */
4592 {
4593 rtx src;
4594 rtx note;
4599 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4600 is a constant, use the value of that. */
4606 else
4619 {
4623 {
4626 }
4627 }
4628 /* If we can't make it a giv,
4629 let biv keep initial value of "itself". */
4632 }
4633 }
4636 /* Search the loop for general induction variables. */
4638 static void
4641 {
4643 }
4646 /* For each giv for which we still don't know whether or not it is
4647 replaceable, check to see if it is replaceable because its final value
4648 can be calculated. */
4650 static void
4653 {
4658 {
4664 }
4665 }
4668 /* Return nonzero if it is possible to eliminate the biv BL provided
4669 all givs are reduced. This is possible if either the reg is not
4670 used outside the loop, or we can compute what its final value will
4671 be. */
4673 static int
4679 {
4680 /* For architectures with a decrement_and_branch_until_zero insn,
4681 don't do this if we put a REG_NONNEG note on the endtest for this
4682 biv. */
4684 #ifdef HAVE_decrement_and_branch_until_zero
4686 {
4691 }
4692 #endif
4694 /* Check that biv is used outside loop or if it has a final value.
4695 Compare against bl->init_insn rather than loop->start. We aren't
4696 concerned with any uses of the biv between init_insn and
4697 loop->start since these won't be affected by the value of the biv
4698 elsewhere in the function, so long as init_insn doesn't use the
4699 biv itself. */
4710 {
4718 }
4720 }
4723 /* Reduce each giv of BL that we have decided to reduce. */
4725 static void
4729 {
4733 {
4736 {
4739 /* If the code for derived givs immediately below has already
4740 allocated a new_reg, we must keep it. */
4744 #ifdef AUTO_INC_DEC
4745 /* If the target has auto-increment addressing modes, and
4746 this is an address giv, then try to put the increment
4747 immediately after its use, so that flow can create an
4748 auto-increment addressing mode. */
4751 /* We don't handle reversed biv's because bl->biv->insn
4752 does not have a valid INSN_LUID. */
4756 {
4757 /* If other giv's have been combined with this one, then
4758 this will work only if all uses of the other giv's occur
4759 before this giv's insn. This is difficult to check.
4761 We simplify this by looking for the common case where
4762 there is one DEST_REG giv, and this giv's insn is the
4763 last use of the dest_reg of that DEST_REG giv. If the
4764 increment occurs after the address giv, then we can
4765 perform the optimization. (Otherwise, the increment
4766 would have to go before other_giv, and we would not be
4767 able to combine it with the address giv to get an
4768 auto-inc address.) */
4770 {
4775 {
4778 else
4780 }
4787 }
4788 /* Check for case where increment is before the address
4789 giv. Do this test in "loop order". */
4798 else
4801 #ifdef HAVE_cc0
4802 {
4803 rtx prev;
4805 /* We can't put an insn immediately after one setting
4806 cc0, or immediately before one using cc0. */
4813 }
4814 #endif
4818 }
4819 #endif
4821 /* For each place where the biv is incremented, add an insn
4822 to increment the new, reduced reg for the giv. */
4824 {
4825 rtx insert_before;
4831 else
4839 /* A multiply is acceptable here
4840 since this is presumed to be seldom executed. */
4844 }
4846 /* Add code at loop start to initialize giv's reduced reg. */
4851 }
4852 }
4853 }
4856 /* Check for givs whose first use is their definition and whose
4857 last use is the definition of another giv. If so, it is likely
4858 dead and should not be used to derive another giv nor to
4859 eliminate a biv. */
4861 static void
4865 {
4869 {
4876 {
4882 }
4883 }
4884 }
4887 static void
4892 {
4896 {
4903 /* Update expression if this was combined, in case other giv was
4904 replaced. */
4909 /* See if this register is known to be a pointer to something. If
4910 so, see if we can find the alignment. First see if there is a
4911 destination register that is a pointer. If so, this shares the
4912 alignment too. Next see if we can deduce anything from the
4913 computational information. If not, and this is a DEST_ADDR
4914 giv, at least we know that it's a pointer, though we don't know
4915 the alignment. */
4923 {
4932 }
4936 {
4944 }
4949 /* Store reduced reg as the address in the memref where we found
4950 this giv. */
4953 {
4955 }
4956 else
4957 {
4959 rtx note;
4961 /* Not replaceable; emit an insn to set the original giv reg from
4962 the reduced giv, same as above. */
4967 /* The original insn may have a REG_EQUAL note. This note is
4968 now incorrect and may result in invalid substitutions later.
4969 The original insn is dead, but may be part of a libcall
4970 sequence, which doesn't seem worth the bother of handling. */
4974 }
4976 /* When a loop is reversed, givs which depend on the reversed
4977 biv, and which are live outside the loop, must be set to their
4978 correct final value. This insn is only needed if the giv is
4979 not replaceable. The correct final value is the same as the
4980 value that the giv starts the reversed loop with. */
4991 {
4996 }
4997 }
4998 }
5001 static int
5006 rtx test_reg;
5007 {
5016 /* Reduce benefit if not replaceable, since we will insert a
5017 move-insn to replace the insn that calculates this giv. Don't do
5018 this unless the giv is a user variable, since it will often be
5019 marked non-replaceable because of the duplication of the exit
5020 code outside the loop. In such a case, the copies we insert are
5021 dead and will be deleted. So they don't have a cost. Similar
5022 situations exist. */
5023 /* ??? The new final_[bg]iv_value code does a much better job of
5024 finding replaceable giv's, and hence this code may no longer be
5025 necessary. */
5030 /* Decrease the benefit to count the add-insns that we will insert
5031 to increment the reduced reg for the giv. ??? This can
5032 overestimate the run-time cost of the additional insns, e.g. if
5033 there are multiple basic blocks that increment the biv, but only
5034 one of these blocks is executed during each iteration. There is
5035 no good way to detect cases like this with the current structure
5036 of the loop optimizer. This code is more accurate for
5037 determining code size than run-time benefits. */
5040 /* Decide whether to strength-reduce this giv or to leave the code
5041 unchanged (recompute it from the biv each time it is used). This
5042 decision can be made independently for each giv. */
5044 #ifdef AUTO_INC_DEC
5045 /* Attempt to guess whether autoincrement will handle some of the
5046 new add insns; if so, increase BENEFIT (undo the subtraction of
5047 add_cost that was done above). */
5049 /* Increasing the benefit is risky, since this is only a guess.
5050 Avoid increasing register pressure in cases where there would
5051 be no other benefit from reducing this giv. */
5054 {
5069 }
5070 #endif
5073 }
5076 /* Free IV structures for LOOP. */
5078 static void
5081 {
5088 {
5094 {
5097 }
5099 {
5102 }
5106 }
5107 }
5110 /* Perform strength reduction and induction variable elimination.
5112 Pseudo registers created during this function will be beyond the
5113 last valid index in several tables including
5114 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5115 problem here, because the added registers cannot be givs outside of
5116 their loop, and hence will never be reconsidered. But scan_loop
5117 must check regnos to make sure they are in bounds. */
5119 static void
5123 {
5127 rtx p;
5128 /* Temporary list pointer for traversing ivs->list. */
5130 /* Ratio of extra register life span we can justify
5131 for saving an instruction. More if loop doesn't call subroutines
5132 since in that case saving an insn makes more difference
5133 and more registers are available. */
5134 /* ??? could set this to last value of threshold in move_movables */
5136 /* Map of pseudo-register replacements. */
5148 /* Find all BIVs in loop. */
5151 /* Exit if there are no bivs. */
5153 {
5154 /* Can still unroll the loop anyways, but indicate that there is no
5155 strength reduction info available. */
5161 }
5163 /* Determine how BIVS are initialized by looking through pre-header
5164 extended basic block. */
5167 /* Look at the each biv and see if we can say anything better about its
5168 initial value from any initializing insns set up above. */
5171 /* Search the loop for general induction variables. */
5174 /* Try to calculate and save the number of loop iterations. This is
5175 set to zero if the actual number can not be calculated. This must
5176 be called after all giv's have been identified, since otherwise it may
5177 fail if the iteration variable is a giv. */
5180 #ifdef HAVE_prefetch
5183 #endif
5185 /* Now for each giv for which we still don't know whether or not it is
5186 replaceable, check to see if it is replaceable because its final value
5187 can be calculated. This must be done after loop_iterations is called,
5188 so that final_giv_value will work correctly. */
5191 /* Try to prove that the loop counter variable (if any) is always
5192 nonnegative; if so, record that fact with a REG_NONNEG note
5193 so that "decrement and branch until zero" insn can be used. */
5196 /* Create reg_map to hold substitutions for replaceable giv regs.
5197 Some givs might have been made from biv increments, so look at
5198 ivs->reg_iv_type for a suitable size. */
5202 /* Examine each iv class for feasibility of strength reduction/induction
5203 variable elimination. */
5206 {
5210 /* Test whether it will be possible to eliminate this biv
5211 provided all givs are reduced. */
5214 /* This will be true at the end, if all givs which depend on this
5215 biv have been strength reduced.
5216 We can't (currently) eliminate the biv unless this is so. */
5219 /* Check each extension dependent giv in this class to see if its
5220 root biv is safe from wrapping in the interior mode. */
5223 /* Combine all giv's for this iv_class. */
5227 {
5235 /* If an insn is not to be strength reduced, then set its ignore
5236 flag, and clear bl->all_reduced. */
5238 /* A giv that depends on a reversed biv must be reduced if it is
5239 used after the loop exit, otherwise, it would have the wrong
5240 value after the loop exit. To make it simple, just reduce all
5241 of such giv's whether or not we know they are used after the loop
5242 exit. */
5247 {
5255 }
5256 else
5257 {
5258 /* Check that we can increment the reduced giv without a
5259 multiply insn. If not, reject it. */
5264 {
5272 }
5273 }
5274 }
5276 /* Check for givs whose first use is their definition and whose
5277 last use is the definition of another giv. If so, it is likely
5278 dead and should not be used to derive another giv nor to
5279 eliminate a biv. */
5282 /* Reduce each giv that we decided to reduce. */
5285 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5286 as not reduced.
5288 For each giv register that can be reduced now: if replaceable,
5289 substitute reduced reg wherever the old giv occurs;
5290 else add new move insn "giv_reg = reduced_reg". */
5293 /* All the givs based on the biv bl have been reduced if they
5294 merit it. */
5296 /* For each giv not marked as maybe dead that has been combined with a
5297 second giv, clear any "maybe dead" mark on that second giv.
5298 v->new_reg will either be or refer to the register of the giv it
5299 combined with.
5301 Doing this clearing avoids problems in biv elimination where
5302 a giv's new_reg is a complex value that can't be put in the
5303 insn but the giv combined with (with a reg as new_reg) is
5304 marked maybe_dead. Since the register will be used in either
5305 case, we'd prefer it be used from the simpler giv. */
5311 /* Try to eliminate the biv, if it is a candidate.
5312 This won't work if ! bl->all_reduced,
5313 since the givs we planned to use might not have been reduced.
5315 We have to be careful that we didn't initially think we could
5316 eliminate this biv because of a giv that we now think may be
5317 dead and shouldn't be used as a biv replacement.
5319 Also, there is the possibility that we may have a giv that looks
5320 like it can be used to eliminate a biv, but the resulting insn
5321 isn't valid. This can happen, for example, on the 88k, where a
5322 JUMP_INSN can compare a register only with zero. Attempts to
5323 replace it with a compare with a constant will fail.
5325 Note that in cases where this call fails, we may have replaced some
5326 of the occurrences of the biv with a giv, but no harm was done in
5327 doing so in the rare cases where it can occur. */
5331 {
5332 /* ?? If we created a new test to bypass the loop entirely,
5333 or otherwise drop straight in, based on this test, then
5334 we might want to rewrite it also. This way some later
5335 pass has more hope of removing the initialization of this
5336 biv entirely. */
5338 /* If final_value != 0, then the biv may be used after loop end
5339 and we must emit an insn to set it just in case.
5341 Reversed bivs already have an insn after the loop setting their
5342 value, so we don't need another one. We can't calculate the
5343 proper final value for such a biv here anyways. */
5352 }
5353 /* See above note wrt final_value. But since we couldn't eliminate
5354 the biv, we must set the value after the loop instead of before. */
5358 }
5360 /* Go through all the instructions in the loop, making all the
5361 register substitutions scheduled in REG_MAP. */
5366 {
5370 }
5373 {
5374 /* When we completely unroll a loop we will likely not need the increment
5375 of the loop BIV and we will not need the conditional branch at the
5376 end of the loop. */
5379 #ifdef HAVE_cc0
5380 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5381 need the comparison before the conditional branch at the end of the
5382 loop. */
5384 #endif
5386 /* We'll need one copy for each loop iteration. */
5389 /* A little slop to account for the ability to remove initialization
5390 code, better CSE, and other secondary benefits of completely
5391 unrolling some loops. */
5394 /* Clamp the value. */
5397 }
5399 /* Unroll loops from within strength reduction so that we can use the
5400 induction variable information that strength_reduce has already
5401 collected. Always unroll loops that would be as small or smaller
5402 unrolled than when rolled. */
5409 #ifdef HAVE_doloop_end
5414 /* In case number of iterations is known, drop branch prediction note
5415 in the branch. Do that only in second loop pass, as loop unrolling
5416 may change the number of iterations performed. */
5418 {
5419 unsigned HOST_WIDE_INT n
5424 }
5432 }
5433 \f
5434 /*Record all basic induction variables calculated in the insn. */
5435 static rtx
5438 rtx p;
5441 {
5443 rtx set;
5444 rtx dest_reg;
5445 rtx inc_val;
5446 rtx mult_val;
5452 {
5457 {
5462 {
5463 /* It is a possible basic induction variable.
5464 Create and initialize an induction structure for it. */
5472 }
5475 }
5476 }
5478 }
5479 \f
5480 /* Record all givs calculated in the insn.
5481 A register is a giv if: it is only set once, it is a function of a
5482 biv and a constant (or invariant), and it is not a biv. */
5483 static rtx
5486 rtx p;
5489 {
5492 rtx set;
5493 /* Look for a general induction variable in a register. */
5498 {
5499 rtx src_reg;
5500 rtx dest_reg;
5501 rtx add_val;
5502 rtx mult_val;
5503 rtx ext_val;
5506 rtx last_consec_insn;
5515 /* Equivalent expression is a giv. */
5520 /* Don't try to handle any regs made by loop optimization.
5521 We have nothing on them in regno_first_uid, etc. */
5523 /* Don't recognize a BASIC_INDUCT_VAR here. */
5525 /* This must be the only place where the register is set. */
5527 /* or all sets must be consecutive and make a giv. */
5532 {
5536 /* If this is a library call, increase benefit. */
5540 /* Skip the consecutive insns, if there are any. */
5548 }
5549 }
5551 #ifndef DONT_REDUCE_ADDR
5552 /* Look for givs which are memory addresses. */
5553 /* This resulted in worse code on a VAX 8600. I wonder if it
5554 still does. */
5557 maybe_multiple);
5558 #endif
5560 /* Update the status of whether giv can derive other givs. This can
5561 change when we pass a label or an insn that updates a biv. */
5566 }
5567 \f
5568 /* Return 1 if X is a valid source for an initial value (or as value being
5569 compared against in an initial test).
5571 X must be either a register or constant and must not be clobbered between
5572 the current insn and the start of the loop.
5574 INSN is the insn containing X. */
5576 static int
5578 rtx x;
5579 rtx insn;
5581 rtx loop_start;
5582 {
5586 /* Only consider pseudos we know about initialized in insns whose luids
5587 we know. */
5592 /* Don't use call-clobbered registers across a call which clobbers it. On
5593 some machines, don't use any hard registers at all. */
5595 && (SMALL_REGISTER_CLASSES
5599 /* Don't use registers that have been clobbered before the start of the
5600 loop. */
5605 }
5606 \f
5607 /* Scan X for memory refs and check each memory address
5608 as a possible giv. INSN is the insn whose pattern X comes from.
5609 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5610 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5611 more than once in each loop iteration. */
5613 static void
5616 rtx x;
5617 rtx insn;
5619 {
5629 {
5645 {
5646 rtx src_reg;
5647 rtx add_val;
5648 rtx mult_val;
5649 rtx ext_val;
5652 /* This code used to disable creating GIVs with mult_val == 1 and
5653 add_val == 0. However, this leads to lost optimizations when
5654 it comes time to combine a set of related DEST_ADDR GIVs, since
5655 this one would not be seen. */
5660 {
5661 /* Found one; record it. */
5670 }
5671 }
5676 }
5678 /* Recursively scan the subexpressions for other mem refs. */
5684 maybe_multiple);
5688 maybe_multiple);
5689 }
5690 \f
5691 /* Fill in the data about one biv update.
5692 V is the `struct induction' in which we record the biv. (It is
5693 allocated by the caller, with alloca.)
5694 INSN is the insn that sets it.
5695 DEST_REG is the biv's reg.
5697 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5698 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5699 being set to INC_VAL.
5701 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5702 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5703 can be executed more than once per iteration. If MAYBE_MULTIPLE
5704 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5705 executed exactly once per iteration. */
5707 static void
5712 rtx insn;
5713 rtx dest_reg;
5714 rtx inc_val;
5715 rtx mult_val;
5719 {
5735 /* Add this to the reg's iv_class, creating a class
5736 if this is the first incrementation of the reg. */
5740 {
5741 /* Create and initialize new iv_class. */
5751 /* Set initial value to the reg itself. */
5754 /* We haven't seen the initializing insn yet */
5764 /* Add this class to ivs->list. */
5768 /* Put it in the array of biv register classes. */
5770 }
5772 /* Update IV_CLASS entry for this biv. */
5781 }
5782 \f
5783 /* Fill in the data about one giv.
5784 V is the `struct induction' in which we record the giv. (It is
5785 allocated by the caller, with alloca.)
5786 INSN is the insn that sets it.
5787 BENEFIT estimates the savings from deleting this insn.
5788 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5789 into a register or is used as a memory address.
5791 SRC_REG is the biv reg which the giv is computed from.
5792 DEST_REG is the giv's reg (if the giv is stored in a reg).
5793 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5794 LOCATION points to the place where this giv's value appears in INSN. */
5796 static void
5801 rtx insn;
5802 rtx src_reg;
5803 rtx dest_reg;
5809 {
5814 rtx temp;
5816 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5817 undo the MULT canonicalization that we performed earlier. */
5847 /* The v->always_computable field is used in update_giv_derive, to
5848 determine whether a giv can be used to derive another giv. For a
5849 DEST_REG giv, INSN computes a new value for the giv, so its value
5850 isn't computable if INSN insn't executed every iteration.
5851 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5852 it does not compute a new value. Hence the value is always computable
5853 regardless of whether INSN is executed each iteration. */
5857 else
5863 {
5866 }
5868 {
5873 /* If the lifetime is zero, it means that this register is
5874 really a dead store. So mark this as a giv that can be
5875 ignored. This will not prevent the biv from being eliminated. */
5881 }
5883 /* Add the giv to the class of givs computed from one biv. */
5887 {
5890 /* Don't count DEST_ADDR. This is supposed to count the number of
5891 insns that calculate givs. */
5895 }
5896 else
5897 /* Fatal error, biv missing for this giv? */
5901 {
5904 }
5905 else
5906 {
5907 /* The giv can be replaced outright by the reduced register only if all
5908 of the following conditions are true:
5909 - the insn that sets the giv is always executed on any iteration
5910 on which the giv is used at all
5911 (there are two ways to deduce this:
5912 either the insn is executed on every iteration,
5913 or all uses follow that insn in the same basic block),
5914 - the giv is not used outside the loop
5915 - no assignments to the biv occur during the giv's lifetime. */
5918 /* Previous line always fails if INSN was moved by loop opt. */
5921 && (! not_every_iteration
5923 {
5924 /* Now check that there are no assignments to the biv within the
5925 giv's lifetime. This requires two separate checks. */
5927 /* Check each biv update, and fail if any are between the first
5928 and last use of the giv.
5930 If this loop contains an inner loop that was unrolled, then
5931 the insn modifying the biv may have been emitted by the loop
5932 unrolling code, and hence does not have a valid luid. Just
5933 mark the biv as not replaceable in this case. It is not very
5934 useful as a biv, because it is used in two different loops.
5935 It is very unlikely that we would be able to optimize the giv
5936 using this biv anyways. */
5941 {
5947 {
5951 }
5952 }
5954 /* If there are any backwards branches that go from after the
5955 biv update to before it, then this giv is not replaceable. */
5959 {
5963 }
5964 }
5965 else
5966 {
5967 /* May still be replaceable, we don't have enough info here to
5968 decide. */
5971 }
5972 }
5974 /* Record whether the add_val contains a const_int, for later use by
5975 combine_givs. */
5976 {
5981 ;
5985 {
5987 {
5992 else
5994 }
5997 }
5998 }
6002 }
6004 /* All this does is determine whether a giv can be made replaceable because
6005 its final value can be calculated. This code can not be part of record_giv
6006 above, because final_giv_value requires that the number of loop iterations
6007 be known, and that can not be accurately calculated until after all givs
6008 have been identified. */
6010 static void
6014 {
6017 /* DEST_ADDR givs will never reach here, because they are always marked
6018 replaceable above in record_giv. */
6020 /* The giv can be replaced outright by the reduced register only if all
6021 of the following conditions are true:
6022 - the insn that sets the giv is always executed on any iteration
6023 on which the giv is used at all
6024 (there are two ways to deduce this:
6025 either the insn is executed on every iteration,
6026 or all uses follow that insn in the same basic block),
6027 - its final value can be calculated (this condition is different
6028 than the one above in record_giv)
6029 - it's not used before the it's set
6030 - no assignments to the biv occur during the giv's lifetime. */
6032 #if 0
6033 /* This is only called now when replaceable is known to be false. */
6034 /* Clear replaceable, so that it won't confuse final_giv_value. */
6036 #endif
6041 {
6044 rtx last_giv_use;
6049 /* When trying to determine whether or not a biv increment occurs
6050 during the lifetime of the giv, we can ignore uses of the variable
6051 outside the loop because final_value is true. Hence we can not
6052 use regno_last_uid and regno_first_uid as above in record_giv. */
6054 /* Search the loop to determine whether any assignments to the
6055 biv occur during the giv's lifetime. Start with the insn
6056 that sets the giv, and search around the loop until we come
6057 back to that insn again.
6059 Also fail if there is a jump within the giv's lifetime that jumps
6060 to somewhere outside the lifetime but still within the loop. This
6061 catches spaghetti code where the execution order is not linear, and
6062 hence the above test fails. Here we assume that the giv lifetime
6063 does not extend from one iteration of the loop to the next, so as
6064 to make the test easier. Since the lifetime isn't known yet,
6065 this requires two loops. See also record_giv above. */
6070 {
6073 {
6076 }
6082 {
6083 /* It is possible for the BIV increment to use the GIV if we
6084 have a cycle. Thus we must be sure to check each insn for
6085 both BIV and GIV uses, and we must check for BIV uses
6086 first. */
6093 {
6095 {
6099 }
6101 }
6102 }
6103 }
6105 /* Now that the lifetime of the giv is known, check for branches
6106 from within the lifetime to outside the lifetime if it is still
6107 replaceable. */
6110 {
6113 {
6126 {
6135 }
6136 }
6137 }
6139 /* If it is replaceable, then save the final value. */
6142 }
6147 }
6148 \f
6149 /* Update the status of whether a giv can derive other givs.
6151 We need to do something special if there is or may be an update to the biv
6152 between the time the giv is defined and the time it is used to derive
6153 another giv.
6155 In addition, a giv that is only conditionally set is not allowed to
6156 derive another giv once a label has been passed.
6158 The cases we look at are when a label or an update to a biv is passed. */
6160 static void
6163 rtx p;
6164 {
6168 rtx tem;
6171 /* Search all IV classes, then all bivs, and finally all givs.
6173 There are three cases we are concerned with. First we have the situation
6174 of a giv that is only updated conditionally. In that case, it may not
6175 derive any givs after a label is passed.
6177 The second case is when a biv update occurs, or may occur, after the
6178 definition of a giv. For certain biv updates (see below) that are
6179 known to occur between the giv definition and use, we can adjust the
6180 giv definition. For others, or when the biv update is conditional,
6181 we must prevent the giv from deriving any other givs. There are two
6182 sub-cases within this case.
6184 If this is a label, we are concerned with any biv update that is done
6185 conditionally, since it may be done after the giv is defined followed by
6186 a branch here (actually, we need to pass both a jump and a label, but
6187 this extra tracking doesn't seem worth it).
6189 If this is a jump, we are concerned about any biv update that may be
6190 executed multiple times. We are actually only concerned about
6191 backward jumps, but it is probably not worth performing the test
6192 on the jump again here.
6194 If this is a biv update, we must adjust the giv status to show that a
6195 subsequent biv update was performed. If this adjustment cannot be done,
6196 the giv cannot derive further givs. */
6202 {
6204 {
6205 /* If cant_derive is already true, there is no point in
6206 checking all of these conditions again. */
6210 /* If this giv is conditionally set and we have passed a label,
6211 it cannot derive anything. */
6215 /* Skip givs that have mult_val == 0, since
6216 they are really invariants. Also skip those that are
6217 replaceable, since we know their lifetime doesn't contain
6218 any biv update. */
6222 /* The only way we can allow this giv to derive another
6223 is if this is a biv increment and we can form the product
6224 of biv->add_val and giv->mult_val. In this case, we will
6225 be able to compute a compensation. */
6227 {
6228 rtx ext_val_dummy;
6239 tem = simplify_giv_expr
6246 else
6248 }
6252 }
6253 }
6254 }
6255 \f
6256 /* Check whether an insn is an increment legitimate for a basic induction var.
6257 X is the source of insn P, or a part of it.
6258 MODE is the mode in which X should be interpreted.
6260 DEST_REG is the putative biv, also the destination of the insn.
6261 We accept patterns of these forms:
6262 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6263 REG = INVARIANT + REG
6265 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6266 store the additive term into *INC_VAL, and store the place where
6267 we found the additive term into *LOCATION.
6269 If X is an assignment of an invariant into DEST_REG, we set
6270 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6272 We also want to detect a BIV when it corresponds to a variable
6273 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6274 of the variable may be a PLUS that adds a SUBREG of that variable to
6275 an invariant and then sign- or zero-extends the result of the PLUS
6276 into the variable.
6278 Most GIVs in such cases will be in the promoted mode, since that is the
6279 probably the natural computation mode (and almost certainly the mode
6280 used for addresses) on the machine. So we view the pseudo-reg containing
6281 the variable as the BIV, as if it were simply incremented.
6283 Note that treating the entire pseudo as a BIV will result in making
6284 simple increments to any GIVs based on it. However, if the variable
6285 overflows in its declared mode but not its promoted mode, the result will
6286 be incorrect. This is acceptable if the variable is signed, since
6287 overflows in such cases are undefined, but not if it is unsigned, since
6288 those overflows are defined. So we only check for SIGN_EXTEND and
6289 not ZERO_EXTEND.
6291 If we cannot find a biv, we return 0. */
6293 static int
6296 rtx x;
6298 rtx dest_reg;
6299 rtx p;
6303 {
6311 {
6317 {
6319 }
6324 {
6326 }
6327 else
6340 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6341 handle addition of promoted variables.
6342 ??? The comment at the start of this function is wrong: promoted
6343 variable increments don't look like it says they do. */
6349 /* If this register is assigned in a previous insn, look at its
6350 source, but don't go outside the loop or past a label. */
6352 /* If this sets a register to itself, we would repeat any previous
6353 biv increment if we applied this strategy blindly. */
6359 {
6360 rtx dest;
6361 do
6362 {
6364 }
6393 }
6394 /* Fall through. */
6396 /* Can accept constant setting of biv only when inside inner most loop.
6397 Otherwise, a biv of an inner loop may be incorrectly recognized
6398 as a biv of the outer loop,
6399 causing code to be moved INTO the inner loop. */
6406 /* convert_modes aborts if we try to convert to or from CCmode, so just
6407 exclude that case. It is very unlikely that a condition code value
6408 would be a useful iterator anyways. convert_modes aborts if we try to
6409 convert a float mode to non-float or vice versa too. */
6413 {
6414 /* Possible bug here? Perhaps we don't know the mode of X. */
6418 }
6419 else
6427 /* Similar, since this can be a sign extension. */
6432 ;
6446 location);
6451 }
6452 }
6453 \f
6454 /* A general induction variable (giv) is any quantity that is a linear
6455 function of a basic induction variable,
6456 i.e. giv = biv * mult_val + add_val.
6457 The coefficients can be any loop invariant quantity.
6458 A giv need not be computed directly from the biv;
6459 it can be computed by way of other givs. */
6461 /* Determine whether X computes a giv.
6462 If it does, return a nonzero value
6463 which is the benefit from eliminating the computation of X;
6464 set *SRC_REG to the register of the biv that it is computed from;
6465 set *ADD_VAL and *MULT_VAL to the coefficients,
6466 such that the value of X is biv * mult + add; */
6468 static int
6472 rtx x;
6480 {
6484 /* If this is an invariant, forget it, it isn't a giv. */
6495 {
6498 /* Since this is now an invariant and wasn't before, it must be a giv
6499 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6500 with. */
6507 /* This is equivalent to a BIV. */
6514 /* Either (plus (biv) (invar)) or
6515 (plus (mult (biv) (invar_1)) (invar_2)). */
6517 {
6520 }
6521 else
6522 {
6525 }
6530 /* ADD_VAL is zero. */
6538 }
6540 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6541 unless they are CONST_INT). */
6549 else
6552 /* Always return true if this is a giv so it will be detected as such,
6553 even if the benefit is zero or negative. This allows elimination
6554 of bivs that might otherwise not be eliminated. */
6556 }
6557 \f
6558 /* Given an expression, X, try to form it as a linear function of a biv.
6559 We will canonicalize it to be of the form
6560 (plus (mult (BIV) (invar_1))
6561 (invar_2))
6562 with possible degeneracies.
6564 The invariant expressions must each be of a form that can be used as a
6565 machine operand. We surround then with a USE rtx (a hack, but localized
6566 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6567 routine; it is the caller's responsibility to strip them.
6569 If no such canonicalization is possible (i.e., two biv's are used or an
6570 expression that is neither invariant nor a biv or giv), this routine
6571 returns 0.
6573 For a nonzero return, the result will have a code of CONST_INT, USE,
6574 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6576 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6581 static rtx
6584 rtx x;
6587 {
6592 rtx tem;
6594 /* If this is not an integer mode, or if we cannot do arithmetic in this
6595 mode, this can't be a giv. */
6602 {
6609 /* Put constant last, CONST_INT last if both constant. */
6617 /* Handle addition of zero, then addition of an invariant. */
6622 {
6625 /* Adding two invariants must result in an invariant, so enclose
6626 addition operation inside a USE and return it. */
6636 else
6645 /* biv + invar or mult + invar. Return sum. */
6649 /* (a + invar_1) + invar_2. Associate. */
6650 return
6656 arg1)),
6661 }
6663 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6664 MULT to reduce cases. */
6670 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6671 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6672 Recurse to associate the second PLUS. */
6677 return
6685 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6701 /* Handle "a - b" as "a + b * (-1)". */
6707 constm1_rtx)),
6716 /* Put constant last, CONST_INT last if both constant. */
6721 /* If second argument is not now constant, not giv. */
6725 /* Handle multiply by 0 or 1. */
6733 {
6735 /* biv * invar. Done. */
6739 /* Product of two constants. */
6743 /* invar * invar is a giv, but attempt to simplify it somehow. */
6749 {
6750 /* (invar_0 * invar_1) * invar_2. Associate. */
6757 arg1)),
6759 }
6760 /* Propagate the MULT expressions to the intermost nodes. */
6762 {
6763 /* (invar_0 + invar_1) * invar_2. Distribute. */
6769 arg1),
6773 arg1)),
6775 }
6779 /* (a * invar_1) * invar_2. Associate. */
6785 arg1)),
6789 /* (a + invar_1) * invar_2. Distribute. */
6794 arg1),
6797 arg1)),
6802 }
6805 /* Shift by constant is multiply by power of two. */
6809 return
6818 /* "-a" is "a * (-1)" */
6824 /* "~a" is "-a - 1". Silly, but easy. */
6828 const1_rtx),
6832 /* Already in proper form for invariant. */
6838 /* Conditionally recognize extensions of simple IVs. After we've
6839 computed loop traversal counts and verified the range of the
6840 source IV, we'll reevaluate this as a GIV. */
6842 {
6845 {
6848 }
6849 }
6853 /* If this is a new register, we can't deal with it. */
6857 /* Check for biv or giv. */
6859 {
6863 {
6866 /* Form expression from giv and add benefit. Ensure this giv
6867 can derive another and subtract any needed adjustment if so. */
6869 /* Increasing the benefit here is risky. The only case in which it
6870 is arguably correct is if this is the only use of V. In other
6871 cases, this will artificially inflate the benefit of the current
6872 giv, and lead to suboptimal code. Thus, it is disabled, since
6873 potentially not reducing an only marginally beneficial giv is
6874 less harmful than reducing many givs that are not really
6875 beneficial. */
6876 {
6880 }
6893 {
6896 }
6897 else
6898 {
6901 }
6903 }
6906 do_default:
6907 /* If it isn't an induction variable, and it is invariant, we
6908 may be able to simplify things further by looking through
6909 the bits we just moved outside the loop. */
6911 {
6917 {
6918 /* Ok, we found a match. Substitute and simplify. */
6920 /* If we match another movable, we must use that, as
6921 this one is going away. */
6926 /* If consec is nonzero, this is a member of a group of
6927 instructions that were moved together. We handle this
6928 case only to the point of seeking to the last insn and
6929 looking for a REG_EQUAL. Fail if we don't find one. */
6931 {
6934 do
6935 {
6937 }
6943 }
6944 else
6945 {
6949 }
6952 {
6953 /* What we are most interested in is pointer
6954 arithmetic on invariants -- only take
6955 patterns we may be able to do something with. */
6961 {
6963 benefit);
6966 }
6971 {
6976 }
6977 }
6979 }
6980 }
6982 }
6984 /* Fall through to general case. */
6986 /* If invariant, return as USE (unless CONST_INT).
6987 Otherwise, not giv. */
6992 {
7001 }
7002 else
7004 }
7005 }
7007 /* This routine folds invariants such that there is only ever one
7008 CONST_INT in the summation. It is only used by simplify_giv_expr. */
7010 static rtx
7013 {
7019 {
7022 }
7025 {
7028 }
7029 else
7030 {
7033 }
7034 }
7036 static rtx
7040 {
7042 {
7046 else
7049 }
7052 else
7055 }
7056 \f
7057 /* Help detect a giv that is calculated by several consecutive insns;
7058 for example,
7059 giv = biv * M
7060 giv = giv + A
7061 The caller has already identified the first insn P as having a giv as dest;
7062 we check that all other insns that set the same register follow
7063 immediately after P, that they alter nothing else,
7064 and that the result of the last is still a giv.
7066 The value is 0 if the reg set in P is not really a giv.
7067 Otherwise, the value is the amount gained by eliminating
7068 all the consecutive insns that compute the value.
7070 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7071 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7073 The coefficients of the ultimate giv value are stored in
7074 *MULT_VAL and *ADD_VAL. */
7076 static int
7081 rtx p;
7082 rtx src_reg;
7083 rtx dest_reg;
7088 {
7094 rtx temp;
7095 rtx set;
7097 /* Indicate that this is a giv so that we can update the value produced in
7098 each insn of the multi-insn sequence.
7100 This induction structure will be used only by the call to
7101 general_induction_var below, so we can allocate it on our stack.
7102 If this is a giv, our caller will replace the induct var entry with
7103 a new induction structure. */
7124 {
7128 /* If libcall, skip to end of call sequence. */
7139 /* Giv created by equivalent expression. */
7145 {
7149 count--;
7153 }
7155 {
7156 /* Allow insns that set something other than this giv to a
7157 constant. Such insns are needed on machines which cannot
7158 include long constants and should not disqualify a giv. */
7167 }
7168 }
7173 }
7174 \f
7175 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7176 represented by G1. If no such expression can be found, or it is clear that
7177 it cannot possibly be a valid address, 0 is returned.
7179 To perform the computation, we note that
7180 G1 = x * v + a and
7181 G2 = y * v + b
7182 where `v' is the biv.
7184 So G2 = (y/b) * G1 + (b - a*y/x).
7186 Note that MULT = y/x.
7188 Update: A and B are now allowed to be additive expressions such that
7189 B contains all variables in A. That is, computing B-A will not require
7190 subtracting variables. */
7192 static rtx
7195 {
7196 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7201 /* If MULT is not 1, we cannot handle A with non-constants, since we
7202 would then be required to subtract multiples of the registers in A.
7203 This is theoretically possible, and may even apply to some Fortran
7204 constructs, but it is a lot of work and we do not attempt it here. */
7209 /* In general these structures are sorted top to bottom (down the PLUS
7210 chain), but not left to right across the PLUS. If B is a higher
7211 order giv than A, we can strip one level and recurse. If A is higher
7212 order, we'll eventually bail out, but won't know that until the end.
7213 If they are the same, we'll strip one level around this loop. */
7216 {
7228 /* We matched: remove one reg completely. */
7231 /* An alternate match. */
7234 /* An alternate match. */
7236 else
7237 {
7238 /* Indicates an extra register in B. Strip one level from B and
7239 recurse, hoping B was the higher order expression. */
7244 }
7245 }
7247 /* Here we are at the last level of A, go through the cases hoping to
7248 get rid of everything but a constant. */
7251 {
7264 }
7266 {
7268 }
7270 {
7275 }
7277 {
7282 else
7284 }
7289 }
7291 rtx
7294 {
7297 /* The value that G1 will be multiplied by must be a constant integer. Also,
7298 the only chance we have of getting a valid address is if b*c/a (see above
7299 for notation) is also an integer. */
7302 {
7307 }
7310 else
7311 {
7312 /* ??? Find out if the one is a multiple of the other? */
7314 }
7318 {
7319 /* Failed. If we've got a multiplication factor between G1 and G2,
7320 scale G1's addend and try again. */
7322 {
7326 {
7327 HOST_WIDE_INT m;
7331 }
7332 else
7333 {
7335 mult);
7336 }
7339 }
7340 }
7344 /* Form simplified final result. */
7349 else
7354 else
7355 {
7358 {
7362 }
7365 }
7366 }
7367 \f
7368 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7369 represented by G1. This indicates that G2 should be combined with G1 and
7370 that G2 can use (either directly or via an address expression) a register
7371 used to represent G1. */
7373 static rtx
7376 {
7379 /* With the introduction of ext dependent givs, we must care for modes.
7380 G2 must not use a wider mode than G1. */
7390 /* If these givs are identical, they can be combined. We use the results
7391 of express_from because the addends are not in a canonical form, so
7392 rtx_equal_p is a weaker test. */
7393 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7394 combination to be the other way round. */
7397 {
7399 }
7401 /* If G2 can be expressed as a function of G1 and that function is valid
7402 as an address and no more expensive than using a register for G2,
7403 the expression of G2 in terms of G1 can be used. */
7410 }
7411 \f
7412 /* Check each extension dependent giv in this class to see if its
7413 root biv is safe from wrapping in the interior mode, which would
7414 make the giv illegal. */
7416 static void
7420 {
7423 HOST_WIDE_INT start_val;
7429 /* Make sure the iteration data is available. We must have
7430 constants in order to be certain of no overflow. */
7431 /* ??? An unknown iteration count with an increment of +-1
7432 combined with friendly exit tests of against an invariant
7433 value is also amenable to optimization. Not implemented. */
7439 /* Make sure the host can represent the arithmetic. */
7441 {
7443 HOST_WIDE_INT s_end_val;
7455 /* Check for host arithmetic overflow. */
7457 {
7459 HOST_WIDE_INT s_max;
7466 /* Check zero extension of biv ok. */
7468 /* Check for host arithmetic overflow. */
7469 && (neg_incr
7472 /* Check for target arithmetic overflow. */
7473 && (neg_incr
7476 {
7478 }
7480 /* Check sign extension of biv ok. */
7481 /* ??? While it is true that overflow with signed and pointer
7482 arithmetic is undefined, I fear too many programmers don't
7483 keep this fact in mind -- myself included on occasion.
7484 So leave alone with the signed overflow optimizations. */
7486 /* Check for host arithmetic overflow. */
7487 && (neg_incr
7490 /* Check for target arithmetic overflow. */
7491 && (neg_incr
7494 {
7496 }
7497 }
7498 }
7500 /* Invalidate givs that fail the tests. */
7503 {
7508 {
7517 /* We don't know whether this value is being used as either
7518 signed or unsigned, so to safely truncate we must satisfy
7519 both. The initial check here verifies the BIV itself;
7520 once that is successful we may check its range wrt the
7521 derived GIV. */
7523 {
7527 /* We know from the above that both endpoints are nonnegative,
7528 and that there is no wrapping. Verify that both endpoints
7529 are within the (signed) range of the outer mode. */
7532 }
7537 }
7540 {
7542 {
7546 }
7547 }
7548 else
7549 {
7551 {
7556 else
7557 {
7562 else
7564 }
7569 }
7572 }
7573 }
7574 }
7576 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7578 rtx
7581 rtx value;
7582 {
7588 /* Recall that check_ext_dependent_givs verified that the known bounds
7589 of a biv did not overflow or wrap with respect to the extension for
7590 the giv. Therefore, constants need no additional adjustment. */
7594 /* Otherwise, we must adjust the value to compensate for the
7595 differing modes of the biv and the giv. */
7597 }
7598 \f
7599 struct combine_givs_stats
7600 {
7603 };
7605 static int
7609 {
7616 /* Stabilize the sort. */
7620 }
7622 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7623 any other. If so, point SAME to the giv combined with and set NEW_REG to
7624 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7625 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7627 static void
7631 {
7632 /* Additional benefit to add for being combined multiple times. */
7640 /* Count givs, because bl->giv_count is incorrect here. */
7644 giv_count++;
7646 giv_array
7657 {
7659 rtx single_use;
7664 /* If a DEST_REG GIV is used only once, do not allow it to combine
7665 with anything, for in doing so we will gain nothing that cannot
7666 be had by simply letting the GIV with which we would have combined
7667 to be reduced on its own. The losage shows up in particular with
7668 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7669 be seen elsewhere as well. */
7676 /* Add an additional weight for zero addends. */
7681 {
7682 rtx this_combine;
7687 {
7690 }
7691 }
7693 }
7695 /* Iterate, combining until we can't. */
7696 restart:
7700 {
7703 {
7709 }
7711 }
7714 {
7720 /* If it has already been combined, skip. */
7725 {
7728 /* If it has already been combined, skip. */
7730 {
7735 /* For destination, we now may replace by mem expression instead
7736 of register. This changes the costs considerably, so add the
7737 compensation. */
7747 /* ??? The new final_[bg]iv_value code does a much better job
7748 of finding replaceable giv's, and hence this code may no
7749 longer be necessary. */
7753 /* To help optimize the next set of combinations, remove
7754 this giv from the benefits of other potential mates. */
7756 {
7760 }
7767 }
7768 }
7770 /* To help optimize the next set of combinations, remove
7771 this giv from the benefits of other potential mates. */
7773 {
7775 {
7779 }
7783 /* We've finished with this giv, and everything it touched.
7784 Restart the combination so that proper weights for the
7785 rest of the givs are properly taken into account. */
7786 /* ??? Ideally we would compact the arrays at this point, so
7787 as to not cover old ground. But sanely compacting
7788 can_combine is tricky. */
7790 }
7791 }
7793 /* Clean up. */
7796 }
7797 \f
7798 /* Generate sequence for REG = B * M + A. */
7800 static rtx
7806 {
7807 rtx seq;
7808 rtx result;
7811 /* Use unsigned arithmetic. */
7819 }
7822 /* Update registers created in insn sequence SEQ. */
7824 static void
7827 rtx seq;
7828 {
7829 rtx insn;
7831 /* Update register info for alias analysis. */
7837 {
7840 {
7847 }
7848 }
7852 }
7855 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7857 void
7864 basic_block before_bb;
7865 rtx before_insn;
7866 {
7867 rtx seq;
7870 {
7873 }
7875 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7878 /* Increase the lifetime of any invariants moved further in code. */
7885 /* It is possible that the expansion created lots of new registers.
7886 Iterate over the sequence we just created and record them all. */
7888 }
7891 /* Emit insns in loop pre-header to set REG = B * M + A. */
7893 void
7900 {
7901 rtx seq;
7903 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7906 /* Increase the lifetime of any invariants moved further in code.
7907 ???? Is this really necessary? */
7914 /* It is possible that the expansion created lots of new registers.
7915 Iterate over the sequence we just created and record them all. */
7917 }
7920 /* Emit insns after loop to set REG = B * M + A. */
7922 void
7929 {
7930 rtx seq;
7932 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7937 /* It is possible that the expansion created lots of new registers.
7938 Iterate over the sequence we just created and record them all. */
7940 }
7944 /* Similar to gen_add_mult, but compute cost rather than generating
7945 sequence. */
7947 static int
7953 {
7963 {
7968 }
7971 }
7972 \f
7973 /* Test whether A * B can be computed without
7974 an actual multiply insn. Value is 1 if so.
7976 ??? This function stinks because it generates a ton of wasted RTL
7977 ??? and as a result fragments GC memory to no end. There are other
7978 ??? places in the compiler which are invoked a lot and do the same
7979 ??? thing, generate wasted RTL just to see if something is possible. */
7981 static int
7983 rtx a;
7984 rtx b;
7985 {
7986 rtx tmp;
7989 /* If only one is constant, make it B. */
7993 /* If first constant, both constant, so don't need multiply. */
7997 /* If second not constant, neither is constant, so would need multiply. */
8001 /* One operand is constant, so might not need multiply insn. Generate the
8002 code for the multiply and see if a call or multiply, or long sequence
8003 of insns is generated. */
8012 {
8015 {
8025 {
8028 }
8031 }
8032 }
8042 }
8043 \f
8044 /* Check to see if loop can be terminated by a "decrement and branch until
8045 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
8046 Also try reversing an increment loop to a decrement loop
8047 to see if the optimization can be performed.
8048 Value is nonzero if optimization was performed. */
8050 /* This is useful even if the architecture doesn't have such an insn,
8051 because it might change a loops which increments from 0 to n to a loop
8052 which decrements from n to 0. A loop that decrements to zero is usually
8053 faster than one that increments from zero. */
8055 /* ??? This could be rewritten to use some of the loop unrolling procedures,
8056 such as approx_final_value, biv_total_increment, loop_iterations, and
8057 final_[bg]iv_value. */
8059 static int
8063 {
8068 rtx reg;
8069 rtx jump_label;
8070 rtx final_value;
8071 rtx start_value;
8072 rtx new_add_val;
8073 rtx comparison;
8074 rtx before_comparison;
8075 rtx p;
8076 rtx jump;
8077 rtx first_compare;
8082 /* If last insn is a conditional branch, and the insn before tests a
8083 register value, try to optimize it. Otherwise, we can't do anything. */
8092 /* Try to compute whether the compare/branch at the loop end is one or
8093 two instructions. */
8099 else
8102 {
8103 /* If more than one condition is present to control the loop, then
8104 do not proceed, as this function does not know how to rewrite
8105 loop tests with more than one condition.
8107 Look backwards from the first insn in the last comparison
8108 sequence and see if we've got another comparison sequence. */
8110 rtx jump1;
8114 }
8116 /* Check all of the bivs to see if the compare uses one of them.
8117 Skip biv's set more than once because we can't guarantee that
8118 it will be zero on the last iteration. Also skip if the biv is
8119 used between its update and the test insn. */
8122 {
8127 first_compare))
8129 }
8134 /* Look for the case where the basic induction variable is always
8135 nonnegative, and equals zero on the last iteration.
8136 In this case, add a reg_note REG_NONNEG, which allows the
8137 m68k DBRA instruction to be used. */
8145 {
8146 /* Initial value must be greater than 0,
8147 init_val % -dec_value == 0 to ensure that it equals zero on
8148 the last iteration */
8154 {
8155 /* register always nonnegative, add REG_NOTE to branch */
8163 }
8165 /* If the decrement is 1 and the value was tested as >= 0 before
8166 the loop, then we can safely optimize. */
8168 {
8181 {
8189 }
8190 }
8191 }
8194 {
8195 /* Try to change inc to dec, so can apply above optimization. */
8196 /* Can do this if:
8197 all registers modified are induction variables or invariant,
8198 all memory references have non-overlapping addresses
8199 (obviously true if only one write)
8200 allow 2 insns for the compare/jump at the end of the loop. */
8201 /* Also, we must avoid any instructions which use both the reversed
8202 biv and another biv. Such instructions will fail if the loop is
8203 reversed. We meet this condition by requiring that either
8204 no_use_except_counting is true, or else that there is only
8205 one biv. */
8207 /* 1 if the iteration var is used only to count iterations. */
8209 /* 1 if the loop has no memory store, or it has a single memory store
8210 which is reversible. */
8216 {
8220 /* If there are no givs for this biv, and the only exit is the
8221 fall through at the end of the loop, then
8222 see if perhaps there are no uses except to count. */
8226 {
8231 /* An insn that sets the biv is okay. */
8232 ;
8236 {
8237 /* If either of these insns uses the biv and sets a pseudo
8238 that has more than one usage, then the biv has uses
8239 other than counting since it's used to derive a value
8240 that is used more than one time. */
8242 regs);
8244 {
8247 }
8248 }
8250 {
8253 }
8254 }
8256 /* A biv has uses besides counting if it is used to set
8257 another biv. */
8261 {
8264 }
8265 }
8268 /* No need to worry about MEMs. */
8269 ;
8271 {
8276 /* If the loop has a single store, and the destination address is
8277 invariant, then we can't reverse the loop, because this address
8278 might then have the wrong value at loop exit.
8279 This would work if the source was invariant also, however, in that
8280 case, the insn should have been moved out of the loop. */
8283 {
8286 /* If we could prove that each of the memory locations
8287 written to was different, then we could reverse the
8288 store -- but we don't presently have any way of
8289 knowing that. */
8292 /* If the store depends on a register that is set after the
8293 store, it depends on the initial value, and is thus not
8294 reversible. */
8296 {
8303 }
8304 }
8305 }
8306 else
8309 /* This code only acts for innermost loops. Also it simplifies
8310 the memory address check by only reversing loops with
8311 zero or one memory access.
8312 Two memory accesses could involve parts of the same array,
8313 and that can't be reversed.
8314 If the biv is used only for counting, than we don't need to worry
8315 about all these things. */
8321 && reversible_mem_store
8326 {
8327 rtx tem;
8329 /* Loop can be reversed. */
8333 /* Now check other conditions:
8335 The increment must be a constant, as must the initial value,
8336 and the comparison code must be LT.
8338 This test can probably be improved since +/- 1 in the constant
8339 can be obtained by changing LT to LE and vice versa; this is
8340 confusing. */
8343 /* for constants, LE gets turned into LT */
8347 {
8358 comparison_const_width
8360 else
8361 comparison_const_width
8365 comparison_sign_mask
8368 /* If the comparison value is not a loop invariant, then we
8369 can not reverse this loop.
8371 ??? If the insns which initialize the comparison value as
8372 a whole compute an invariant result, then we could move
8373 them out of the loop and proceed with loop reversal. */
8381 /* Normalize the initial value if it is an integer and
8382 has no other use except as a counter. This will allow
8383 a few more loops to be reversed. */
8387 {
8389 /* The code below requires comparison_val to be a multiple
8390 of add_val in order to do the loop reversal, so
8391 round up comparison_val to a multiple of add_val.
8392 Since comparison_value is constant, we know that the
8393 current comparison code is LT. */
8395 comparison_val
8397 /* We postpone overflow checks for COMPARISON_VAL here;
8398 even if there is an overflow, we might still be able to
8399 reverse the loop, if converting the loop exit test to
8400 NE is possible. */
8402 }
8404 /* First check if we can do a vanilla loop reversal. */
8406 /* If we have a decrement_and_branch_on_count,
8407 prefer the NE test, since this will allow that
8408 instruction to be generated. Note that we must
8409 use a vanilla loop reversal if the biv is used to
8410 calculate a giv or has a non-counting use. */
8411 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8412 && defined (HAVE_decrement_and_branch_on_count)
8416 #endif
8418 /* Now do postponed overflow checks on COMPARISON_VAL. */
8421 {
8422 /* Register will always be nonnegative, with value
8423 0 on last iteration */
8427 }
8431 {
8434 }
8435 else
8441 /* If the initial value is not zero, or if the comparison
8442 value is not an exact multiple of the increment, then we
8443 can not reverse this loop. */
8446 {
8449 }
8450 else
8451 {
8454 }
8458 /* Reset these in case we normalized the initial value
8459 and comparison value above. */
8462 {
8464 final_value
8466 }
8469 /* Save some info needed to produce the new insns. */
8474 /* Set start_value; if this is not a CONST_INT, we need
8475 to generate a SUB.
8476 Initialize biv to start_value before loop start.
8477 The old initializing insn will be deleted as a
8478 dead store by flow.c. */
8481 {
8484 }
8486 {
8494 start_value
8500 }
8502 {
8505 initial_value);
8509 start_value
8512 }
8513 else
8514 /* We could handle the other cases too, but it'll be
8515 better to have a testcase first. */
8518 /* We may not have a single insn which can increment a reg, so
8519 create a sequence to hold all the insns from expand_inc. */
8528 /* Update biv info to reflect its new status. */
8533 /* Update loop info. */
8542 /* Inc LABEL_NUSES so that delete_insn will
8543 not delete the label. */
8546 /* Emit an insn after the end of the loop to set the biv's
8547 proper exit value if it is used anywhere outside the loop. */
8553 /* Delete compare/branch at end of loop. */
8558 /* Add new compare/branch insn at end of loop. */
8570 ;
8576 {
8578 {
8579 /* Increment of LABEL_NUSES done above. */
8580 /* Register is now always nonnegative,
8581 so add REG_NONNEG note to the branch. */
8584 }
8586 }
8588 /* No insn may reference both the reversed and another biv or it
8589 will fail (see comment near the top of the loop reversal
8590 code).
8591 Earlier on, we have verified that the biv has no use except
8592 counting, or it is the only biv in this function.
8593 However, the code that computes no_use_except_counting does
8594 not verify reg notes. It's possible to have an insn that
8595 references another biv, and has a REG_EQUAL note with an
8596 expression based on the reversed biv. To avoid this case,
8597 remove all REG_EQUAL notes based on the reversed biv
8598 here. */
8601 {
8604 /* If this is a set of a GIV based on the reversed biv, any
8605 REG_EQUAL notes should still be correct. */
8612 {
8617 else
8619 }
8620 }
8622 /* Mark that this biv has been reversed. Each giv which depends
8623 on this biv, and which is also live past the end of the loop
8624 will have to be fixed up. */
8629 {
8633 else
8635 }
8638 }
8639 }
8640 }
8643 }
8644 \f
8645 /* Verify whether the biv BL appears to be eliminable,
8646 based on the insns in the loop that refer to it.
8648 If ELIMINATE_P is nonzero, actually do the elimination.
8650 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8651 determine whether invariant insns should be placed inside or at the
8652 start of the loop. */
8654 static int
8660 {
8663 rtx p;
8665 /* Scan all insns in the loop, stopping if we find one that uses the
8666 biv in a way that we cannot eliminate. */
8669 {
8673 rtx note;
8675 /* If this is a libcall that sets a giv, skip ahead to its end. */
8677 {
8681 {
8686 {
8693 }
8694 }
8695 }
8697 /* Closely examine the insn if the biv is mentioned. */
8702 {
8708 }
8710 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8715 }
8718 {
8723 }
8726 }
8727 \f
8728 /* INSN and REFERENCE are instructions in the same insn chain.
8729 Return nonzero if INSN is first. */
8731 int
8734 {
8738 {
8739 /* Start with test for not first so that INSN == REFERENCE yields not
8740 first. */
8746 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8747 previous insn, hence the <= comparison below does not work if
8748 P is a note. */
8759 }
8760 }
8762 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8763 the offset that we have to take into account due to auto-increment /
8764 div derivation is zero. */
8765 static int
8768 rtx insn;
8769 {
8770 /* If the giv V had the auto-inc address optimization applied
8771 to it, and INSN occurs between the giv insn and the biv
8772 insn, then we'd have to adjust the value used here.
8773 This is rare, so we don't bother to make this possible. */
8782 }
8784 /* If BL appears in X (part of the pattern of INSN), see if we can
8785 eliminate its use. If so, return 1. If not, return 0.
8787 If BIV does not appear in X, return 1.
8789 If ELIMINATE_P is nonzero, actually do the elimination.
8790 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8791 Depending on how many items have been moved out of the loop, it
8792 will either be before INSN (when WHERE_INSN is nonzero) or at the
8793 start of the loop (when WHERE_INSN is zero). */
8795 static int
8801 basic_block where_bb;
8802 rtx where_insn;
8803 {
8809 #ifdef HAVE_cc0
8811 #endif
8817 {
8819 /* If we haven't already been able to do something with this BIV,
8820 we can't eliminate it. */
8826 /* If this sets the BIV, it is not a problem. */
8830 /* If this is an insn that defines a giv, it is also ok because
8831 it will go away when the giv is reduced. */
8836 #ifdef HAVE_cc0
8838 {
8839 /* Can replace with any giv that was reduced and
8840 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8841 Require a constant for MULT_VAL, so we know it's nonzero.
8842 ??? We disable this optimization to avoid potential
8843 overflows. */
8851 {
8858 /* If the giv has the opposite direction of change,
8859 then reverse the comparison. */
8863 else
8866 /* We can probably test that giv's reduced reg. */
8869 }
8871 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8872 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8873 Require a constant for MULT_VAL, so we know it's nonzero.
8874 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8875 overflow problem. */
8887 {
8894 /* If the giv has the opposite direction of change,
8895 then reverse the comparison. */
8899 else
8903 /* Replace biv with the giv's reduced register. */
8908 /* Insn doesn't support that constant or invariant. Copy it
8909 into a register (it will be a loop invariant.) */
8916 /* Substitute the new register for its invariant value in
8917 the compare expression. */
8921 }
8922 }
8923 #endif
8930 /* See if either argument is the biv. */
8935 else
8939 {
8940 /* First try to replace with any giv that has constant positive
8941 mult_val and constant add_val. We might be able to support
8942 negative mult_val, but it seems complex to do it in general. */
8954 {
8958 /* Don't eliminate if the linear combination that makes up
8959 the giv overflows when it is applied to ARG. */
8961 {
8962 rtx add_val;
8966 else
8972 }
8977 /* Replace biv with the giv's reduced reg. */
8980 /* If all constants are actually constant integers and
8981 the derived constant can be directly placed in the COMPARE,
8982 do so. */
8985 {
8988 }
8989 else
8990 {
8991 /* Otherwise, load it into a register. */
8996 }
9002 }
9004 /* Look for giv with positive constant mult_val and nonconst add_val.
9005 Insert insns to calculate new compare value.
9006 ??? Turn this off due to possible overflow. */
9014 {
9015 rtx tem;
9025 /* Replace biv with giv's reduced register. */
9029 /* Compute value to compare against. */
9033 /* Use it in this insn. */
9037 }
9038 }
9040 {
9042 {
9043 /* Look for giv with constant positive mult_val and nonconst
9044 add_val. Insert insns to compute new compare value.
9045 ??? Turn this off due to possible overflow. */
9052 {
9053 rtx tem;
9063 /* Replace biv with giv's reduced register. */
9067 /* Compute value to compare against. */
9074 }
9075 }
9077 /* This code has problems. Basically, you can't know when
9078 seeing if we will eliminate BL, whether a particular giv
9079 of ARG will be reduced. If it isn't going to be reduced,
9080 we can't eliminate BL. We can try forcing it to be reduced,
9081 but that can generate poor code.
9083 The problem is that the benefit of reducing TV, below should
9084 be increased if BL can actually be eliminated, but this means
9085 we might have to do a topological sort of the order in which
9086 we try to process biv. It doesn't seem worthwhile to do
9087 this sort of thing now. */
9089 #if 0
9090 /* Otherwise the reg compared with had better be a biv. */
9095 /* Look for a pair of givs, one for each biv,
9096 with identical coefficients. */
9098 {
9110 {
9117 /* Replace biv with its giv's reduced reg. */
9119 /* Replace other operand with the other giv's
9120 reduced reg. */
9123 }
9124 }
9125 #endif
9126 }
9128 /* If we get here, the biv can't be eliminated. */
9132 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9133 biv is used in it, since it will be replaced. */
9141 }
9143 /* See if any subexpression fails elimination. */
9146 {
9148 {
9161 }
9162 }
9165 }
9166 \f
9167 /* Return nonzero if the last use of REG
9168 is in an insn following INSN in the same basic block. */
9170 static int
9172 rtx reg;
9173 rtx insn;
9174 {
9175 rtx n;
9179 {
9182 }
9184 }
9185 \f
9186 /* Called via `note_stores' to record the initial value of a biv. Here we
9187 just record the location of the set and process it later. */
9189 static void
9191 rtx dest;
9192 rtx set;
9194 {
9205 /* If this is the first set found, record it. */
9207 {
9210 }
9211 }
9212 \f
9213 /* If any of the registers in X are "old" and currently have a last use earlier
9214 than INSN, update them to have a last use of INSN. Their actual last use
9215 will be the previous insn but it will not have a valid uid_luid so we can't
9216 use it. X must be a source expression only. */
9218 static void
9220 rtx x;
9221 rtx insn;
9222 {
9223 /* Check for the case where INSN does not have a valid luid. In this case,
9224 there is no need to modify the regno_last_uid, as this can only happen
9225 when code is inserted after the loop_end to set a pseudo's final value,
9226 and hence this insn will never be the last use of x.
9227 ???? This comment is not correct. See for example loop_givs_reduce.
9228 This may insert an insn before another new insn. */
9232 {
9234 }
9235 else
9236 {
9240 {
9246 }
9247 }
9248 }
9249 \f
9250 /* Given an insn INSN and condition COND, return the condition in a
9251 canonical form to simplify testing by callers. Specifically:
9253 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9254 (2) Both operands will be machine operands; (cc0) will have been replaced.
9255 (3) If an operand is a constant, it will be the second operand.
9256 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9257 for GE, GEU, and LEU.
9259 If the condition cannot be understood, or is an inequality floating-point
9260 comparison which needs to be reversed, 0 will be returned.
9262 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9264 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9265 insn used in locating the condition was found. If a replacement test
9266 of the condition is desired, it should be placed in front of that
9267 insn and we will be sure that the inputs are still valid.
9269 If WANT_REG is nonzero, we wish the condition to be relative to that
9270 register, if possible. Therefore, do not canonicalize the condition
9271 further. */
9273 rtx
9275 rtx insn;
9276 rtx cond;
9279 rtx want_reg;
9280 {
9283 rtx set;
9284 rtx tem;
9302 /* If we are comparing a register with zero, see if the register is set
9303 in the previous insn to a COMPARE or a comparison operation. Perform
9304 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9305 in cse.c */
9310 {
9311 /* Set nonzero when we find something of interest. */
9314 #ifdef HAVE_cc0
9315 /* If comparison with cc0, import actual comparison from compare
9316 insn. */
9318 {
9329 }
9330 #endif
9332 /* If this is a COMPARE, pick up the two things being compared. */
9334 {
9338 }
9342 /* Go back to the previous insn. Stop if it is not an INSN. We also
9343 stop if it isn't a single set or if it has a REG_INC note because
9344 we don't want to bother dealing with it. */
9358 /* If this is setting OP0, get what it sets it to if it looks
9359 relevant. */
9361 {
9363 #ifdef FLOAT_STORE_FLAG_VALUE
9364 REAL_VALUE_TYPE fsfv;
9365 #endif
9367 /* ??? We may not combine comparisons done in a CCmode with
9368 comparisons not done in a CCmode. This is to aid targets
9369 like Alpha that have an IEEE compliant EQ instruction, and
9370 a non-IEEE compliant BEQ instruction. The use of CCmode is
9371 actually artificial, simply to prevent the combination, but
9372 should not affect other platforms.
9374 However, we must allow VOIDmode comparisons to match either
9375 CCmode or non-CCmode comparison, because some ports have
9376 modeless comparisons inside branch patterns.
9378 ??? This mode check should perhaps look more like the mode check
9379 in simplify_comparison in combine. */
9387 && (STORE_FLAG_VALUE
9390 #ifdef FLOAT_STORE_FLAG_VALUE
9395 #endif
9396 ))
9407 && (STORE_FLAG_VALUE
9410 #ifdef FLOAT_STORE_FLAG_VALUE
9415 #endif
9416 ))
9422 {
9425 }
9426 else
9428 }
9431 /* If this sets OP0, but not directly, we have to give up. */
9435 {
9439 {
9444 }
9449 }
9450 }
9452 /* If constant is first, put it last. */
9456 /* If OP0 is the result of a comparison, we weren't able to find what
9457 was really being compared, so fail. */
9461 /* Canonicalize any ordered comparison with integers involving equality
9462 if we can do computations in the relevant mode and we do not
9463 overflow. */
9468 {
9471 unsigned HOST_WIDE_INT max_val
9475 {
9481 /* When cross-compiling, const_val might be sign-extended from
9482 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9502 }
9503 }
9505 /* Never return CC0; return zero instead. */
9510 }
9512 /* Given a jump insn JUMP, return the condition that will cause it to branch
9513 to its JUMP_LABEL. If the condition cannot be understood, or is an
9514 inequality floating-point comparison which needs to be reversed, 0 will
9515 be returned.
9517 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9518 insn used in locating the condition was found. If a replacement test
9519 of the condition is desired, it should be placed in front of that
9520 insn and we will be sure that the inputs are still valid. */
9522 rtx
9524 rtx jump;
9526 {
9527 rtx cond;
9529 rtx set;
9531 /* If this is not a standard conditional jump, we can't parse it. */
9539 /* If this branches to JUMP_LABEL when the condition is false, reverse
9540 the condition. */
9541 reverse
9546 }
9548 /* Similar to above routine, except that we also put an invariant last
9549 unless both operands are invariants. */
9551 rtx
9554 rtx x;
9555 {
9565 }
9567 /* Scan the function and determine whether it has indirect (computed) jumps.
9569 This is taken mostly from flow.c; similar code exists elsewhere
9570 in the compiler. It may be useful to put this into rtlanal.c. */
9571 static int
9573 rtx start;
9574 {
9575 rtx insn;
9582 }
9584 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9585 documentation for LOOP_MEMS for the definition of `appropriate'.
9586 This function is called from prescan_loop via for_each_rtx. */
9588 static int
9592 {
9601 {
9606 /* We're not interested in MEMs that are only clobbered. */
9610 /* We're not interested in the MEM associated with a
9611 CONST_DOUBLE, so there's no need to traverse into this. */
9615 /* We're not interested in any MEMs that only appear in notes. */
9619 /* This is not a MEM. */
9621 }
9623 /* See if we've already seen this MEM. */
9626 {
9628 /* The modes of the two memory accesses are different. If
9629 this happens, something tricky is going on, and we just
9630 don't optimize accesses to this MEM. */
9634 }
9636 /* Resize the array, if necessary. */
9638 {
9641 else
9647 }
9649 /* Actually insert the MEM. */
9651 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9652 because we can't put it in a register. We still store it in the
9653 table, though, so that if we see the same address later, but in a
9654 non-BLK mode, we'll not think we can optimize it at that point. */
9660 }
9663 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9665 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9666 register that is modified by an insn between FROM and TO. If the
9667 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9668 more, stop incrementing it, to avoid overflow.
9670 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9671 register I is used, if it is only used once. Otherwise, it is set
9672 to 0 (for no uses) or const0_rtx for more than one use. This
9673 parameter may be zero, in which case this processing is not done.
9675 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9676 optimize register I. */
9678 static void
9682 {
9685 /* last_set[n] is nonzero iff reg n has been set in the current
9686 basic block. In that case, it is the insn that last set reg n. */
9688 rtx insn;
9694 /* Grow the regs array if not allocated or too small. */
9696 {
9702 /* Zero the new elements. */
9705 }
9707 /* Clear previously scanned fields but do not clear n_times_set. */
9709 {
9713 }
9717 /* Scan the loop, recording register usage. */
9720 {
9722 {
9723 /* Record registers that have exactly one use. */
9726 /* Include uses in REG_EQUAL notes. */
9734 {
9738 last_set);
9739 }
9740 }
9745 /* Invalidate all registers used for function argument passing.
9746 We check rtx_varies_p for the same reason as below, to allow
9747 optimizing PIC calculations. */
9749 {
9750 rtx link;
9752 link;
9754 {
9761 }
9762 }
9763 }
9765 /* Invalidate all hard registers clobbered by calls. With one exception:
9766 a call-clobbered PIC register is still function-invariant for our
9767 purposes, since we can hoist any PIC calculations out of the loop.
9768 Thus the call to rtx_varies_p. */
9773 {
9776 }
9778 #ifdef AVOID_CCMODE_COPIES
9779 /* Don't try to move insns which set CC registers if we should not
9780 create CCmode register copies. */
9784 #endif
9786 /* Set regs->array[I].n_times_set for the new registers. */
9791 }
9793 /* Returns the number of real INSNs in the LOOP. */
9795 static int
9798 {
9800 rtx insn;
9808 }
9810 /* Move MEMs into registers for the duration of the loop. */
9812 static void
9815 {
9822 rtx end_label;
9823 /* Nonzero if the next instruction may never be executed. */
9830 /* We cannot use next_label here because it skips over normal insns. */
9835 /* Check to see if it's possible that some instructions in the loop are
9836 never executed. Also check if there is a goto out of the loop other
9837 than right after the end of the loop. */
9841 {
9845 /* If we enter the loop in the middle, and scan
9846 around to the beginning, don't set maybe_never
9847 for that. This must be an unconditional jump,
9848 otherwise the code at the top of the loop might
9849 never be executed. Unconditional jumps are
9850 followed a by barrier then loop end. */
9855 {
9856 /* If this is a jump outside of the loop but not right
9857 after the end of the loop, we would have to emit new fixup
9858 sequences for each such label. */
9860 JUMP_INSN is executed, we must be conservative. */
9869 /* Something complicated. */
9871 else
9872 /* If there are any more instructions in the loop, they
9873 might not be reached. */
9875 }
9878 }
9880 /* Find start of the extended basic block that enters the loop. */
9884 ;
9889 /* Build table of mems that get set to constant values before the
9890 loop. */
9894 /* Actually move the MEMs. */
9896 {
9897 regset_head load_copies;
9898 regset_head store_copies;
9900 rtx reg;
9902 rtx mem_list_entry;
9906 /* There's no telling whether or not MEM is modified. */
9909 /* Go through the MEMs written to in the loop to see if this
9910 one is aliased by one of them. */
9913 {
9918 {
9919 /* MEM is indeed aliased by this store. */
9922 }
9924 }
9930 /* If this MEM is written to, we must be sure that there
9931 are no reads from another MEM that aliases this one. */
9933 {
9937 {
9941 VOIDmode,
9943 rtx_varies_p))
9944 {
9945 /* It's not safe to hoist loop_info->mems[i] out of
9946 the loop because writes to it might not be
9947 seen by reads from loop_info->mems[j]. */
9950 }
9951 }
9952 }
9955 /* We can't access the MEM outside the loop; it might
9956 cause a trap that wouldn't have happened otherwise. */
9960 /* We thought we were going to lift this MEM out of the
9961 loop, but later discovered that we could not. */
9967 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9968 order to keep scan_loop from moving stores to this MEM
9969 out of the loop just because this REG is neither a
9970 user-variable nor used in the loop test. */
9975 /* Now, replace all references to the MEM with the
9976 corresponding pseudos. */
9981 {
9983 {
9984 rtx set;
9988 /* See if this copies the mem into a register that isn't
9989 modified afterwards. We'll try to do copy propagation
9990 a little further on. */
9992 /* @@@ This test is _way_ too conservative. */
9993 && ! maybe_never
10001 /* See if this copies the mem from a register that isn't
10002 modified afterwards. We'll try to remove the
10003 redundant copy later on by doing a little register
10004 renaming and copy propagation. This will help
10005 to untangle things for the BIV detection code. */
10007 && ! maybe_never
10015 /* If this is a call which uses / clobbers this memory
10016 location, we must not change the interface here. */
10020 {
10024 }
10025 else
10026 /* Replace the memory reference with the shadow register. */
10029 }
10034 }
10039 /* We couldn't replace all occurrences of the MEM. */
10041 else
10042 {
10043 /* Load the memory immediately before LOOP->START, which is
10044 the NOTE_LOOP_BEG. */
10046 rtx set;
10052 {
10056 {
10060 /* Extending hard register lifetimes causes crash
10061 on SRC targets. Doing so on non-SRC is
10062 probably also not good idea, since we most
10063 probably have pseudoregister equivalence as
10064 well. */
10067 }
10068 /* Use the constant equivalence if that is cheap enough. */
10074 {
10077 }
10079 /* If best_equiv is nonzero, we know that MEM is set to a
10080 constant or register before the loop. We will use this
10081 knowledge to initialize the shadow register with that
10082 constant or reg rather than by loading from MEM. */
10085 }
10090 {
10093 {
10096 }
10097 }
10103 {
10105 {
10108 }
10110 /* Store the memory immediately after END, which is
10111 the NOTE_LOOP_END. */
10114 }
10117 {
10122 }
10124 /* Attempt a bit of copy propagation. This helps untangle the
10125 data flow, and enables {basic,general}_induction_var to find
10126 more bivs/givs. */
10127 EXECUTE_IF_SET_IN_REG_SET
10129 {
10131 });
10134 EXECUTE_IF_SET_IN_REG_SET
10136 {
10138 });
10140 }
10141 }
10144 {
10145 /* Now, we need to replace all references to the previous exit
10146 label with the new one. */
10147 rtx_pair rr;
10152 {
10155 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10156 field. This is not handled by for_each_rtx because it doesn't
10157 handle unprinted ('0') fields. We need to update JUMP_LABEL
10158 because the immediately following unroll pass will use it.
10159 replace_label would not work anyways, because that only handles
10160 LABEL_REFs. */
10163 }
10164 }
10167 }
10169 /* For communication between note_reg_stored and its caller. */
10170 struct note_reg_stored_arg
10171 {
10173 rtx reg;
10174 };
10176 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10177 is equal to ARG. */
10178 static void
10182 {
10186 }
10188 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10189 There must be exactly one insn that sets this pseudo; it will be
10190 deleted if all replacements succeed and we can prove that the register
10191 is not used after the loop. */
10193 static void
10196 rtx replacement;
10198 {
10199 /* This is the reg that we are copying from. */
10202 rtx insn;
10203 /* These help keep track of whether we replaced all uses of the reg. */
10210 {
10211 rtx set;
10213 /* Only substitute within one extended basic block from the initializing
10214 insn. */
10221 /* Is this the initializing insn? */
10226 {
10233 }
10235 /* Only substitute after seeing the initializing insn. */
10237 {
10244 /* Stop replacing when REPLACEMENT is modified. */
10249 {
10252 /* It is possible that we've turned previously valid REG_EQUAL to
10253 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10254 REPLACEMENT is modified, we get different meaning. */
10258 }
10259 }
10260 }
10264 {
10268 {
10269 rtx first;
10270 rtx retval_note;
10272 /* Assume we're just deleting INIT_INSN. */
10274 /* Look for REG_RETVAL note. If we're deleting the end of
10275 the libcall sequence, the whole sequence can go. */
10277 /* If we found a REG_RETVAL note, find the first instruction
10278 in the sequence. */
10282 /* Delete the instructions. */
10284 }
10287 }
10288 }
10290 /* Replace all the instructions from FIRST up to and including LAST
10291 with NOTE_INSN_DELETED notes. */
10293 static void
10295 rtx first;
10296 rtx last;
10297 {
10299 {
10305 /* If this was the LAST instructions we're supposed to delete,
10306 we're done. */
10311 }
10312 }
10314 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10315 loop LOOP if the order of the sets of these registers can be
10316 swapped. There must be exactly one insn within the loop that sets
10317 this pseudo followed immediately by a move insn that sets
10318 REPLACEMENT with REGNO. */
10319 static void
10322 rtx replacement;
10324 {
10325 rtx insn;
10334 {
10335 /* Search for the insn that copies REGNO to NEW_REGNO? */
10343 }
10346 {
10347 rtx prev_insn;
10348 rtx prev_set;
10350 /* Some DEF-USE info would come in handy here to make this
10351 function more general. For now, just check the previous insn
10352 which is the most likely candidate for setting REGNO. */
10360 {
10361 /* We have:
10362 (set (reg regno) (expr))
10363 (set (reg new_regno) (reg regno))
10365 so try converting this to:
10366 (set (reg new_regno) (expr))
10367 (set (reg regno) (reg new_regno))
10369 The former construct is often generated when a global
10370 variable used for an induction variable is shadowed by a
10371 register (NEW_REGNO). The latter construct improves the
10372 chances of GIV replacement and BIV elimination. */
10382 {
10389 /* Update first use of REGNO. */
10393 /* Now perform copy propagation to hopefully
10394 remove all uses of REGNO within the loop. */
10396 }
10397 }
10398 }
10399 }
10401 /* Replace MEM with its associated pseudo register. This function is
10402 called from load_mems via for_each_rtx. DATA is actually a pointer
10403 to a structure describing the instruction currently being scanned
10404 and the MEM we are currently replacing. */
10406 static int
10410 {
10418 {
10423 /* We're not interested in the MEM associated with a
10424 CONST_DOUBLE, so there's no need to traverse into one. */
10428 /* This is not a MEM. */
10430 }
10433 /* This is not the MEM we are currently replacing. */
10436 /* Actually replace the MEM. */
10440 }
10442 static void
10444 rtx insn;
10445 rtx mem;
10446 rtx reg;
10447 {
10448 loop_replace_args args;
10455 }
10457 /* Replace one register with another. Called through for_each_rtx; PX points
10458 to the rtx being scanned. DATA is actually a pointer to
10459 a structure of arguments. */
10461 static int
10465 {
10476 }
10478 static void
10480 rtx insn;
10481 rtx reg;
10482 rtx replacement;
10483 {
10484 loop_replace_args args;
10491 }
10493 /* Replace occurrences of the old exit label for the loop with the new
10494 one. DATA is an rtx_pair containing the old and new labels,
10495 respectively. */
10497 static int
10501 {
10520 }
10521 \f
10522 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10523 (ignored in the interim). */
10525 static rtx
10528 basic_block where_bb ATTRIBUTE_UNUSED;
10529 rtx where_insn;
10530 rtx pattern;
10531 {
10533 }
10536 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10537 in basic block WHERE_BB (ignored in the interim) within the loop
10538 otherwise hoist PATTERN into the loop pre-header. */
10540 rtx
10543 basic_block where_bb ATTRIBUTE_UNUSED;
10544 rtx where_insn;
10545 rtx pattern;
10546 {
10550 }
10553 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10554 WHERE_BB (ignored in the interim) within the loop. */
10556 static rtx
10559 basic_block where_bb ATTRIBUTE_UNUSED;
10560 rtx where_insn;
10561 rtx pattern;
10562 {
10564 }
10567 /* Hoist insn for PATTERN into the loop pre-header. */
10569 rtx
10572 rtx pattern;
10573 {
10575 }
10578 /* Hoist call insn for PATTERN into the loop pre-header. */
10580 static rtx
10583 rtx pattern;
10584 {
10586 }
10589 /* Sink insn for PATTERN after the loop end. */
10591 rtx
10594 rtx pattern;
10595 {
10597 }
10599 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10600 and constant. Emit sequence of instructions to load it into REG. */
10601 static rtx
10604 {
10605 rtx seq;
10613 }
10615 /* If the loop has multiple exits, emit insn for PATTERN before the
10616 loop to ensure that it will always be executed no matter how the
10617 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10618 since this is slightly more efficient. */
10620 static rtx
10623 rtx pattern;
10624 {
10627 else
10629 }
10630 \f
10631 static void
10636 {
10644 iv_num++;
10649 {
10652 }
10653 }
10656 static void
10661 {
10663 rtx incr;
10674 {
10677 }
10679 {
10682 }
10686 {
10690 }
10693 {
10697 }
10699 /* List the increments. */
10701 {
10705 }
10707 /* List the givs. */
10709 {
10714 else
10717 }
10718 }
10721 static void
10726 {
10737 {
10741 }
10744 }
10747 static void
10752 {
10759 else
10775 {
10777 {
10789 }
10790 }
10801 {
10805 }
10808 }
10811 void
10814 {
10816 }
10819 void
10822 {
10824 }
10827 void
10830 {
10832 }
10835 void
10838 {
10840 }
10843 #define LOOP_BLOCK_NUM_1(INSN) \
10844 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10846 /* The notes do not have an assigned block, so look at the next insn. */
10847 #define LOOP_BLOCK_NUM(INSN) \
10848 ((INSN) ? (GET_CODE (INSN) == NOTE \
10849 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10850 : LOOP_BLOCK_NUM_1 (INSN)) \
10851 : -1)
10853 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10855 static void
10860 {
10861 rtx label;
10866 /* Print diagnostics to compare our concept of a loop with
10867 what the loop notes say. */
10882 {
10902 {
10905 {
10908 }
10909 }
10912 /* This can happen when a marked loop appears as two nested loops,
10913 say from while (a || b) {}. The inner loop won't match
10914 the loop markers but the outer one will. */
10917 }
10918 }
10920 /* Call this function from the debugger to dump LOOP. */
10922 void
10925 {
10927 }
10929 /* Call this function from the debugger to dump LOOPS. */
10931 void
10934 {
10936 }