1 ;;- Machine description for FPA co-processor for ARM cpus.
2 ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 ;; and Martin Simmons (@harleqn.co.uk).
6 ;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it
11 ;; under the terms of the GNU General Public License as published
12 ;; by the Free Software Foundation; either version 2, or (at your
13 ;; option) any later version.
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
16 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 ;; License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;;--------------------------------------------------------------------
26 ;; Floating point unit (FPA)
27 ;;--------------------------------------------------------------------
28 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
29 (eq_attr "type" "fdivx")) 71 69)
31 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
32 (eq_attr "type" "fdivd")) 59 57)
34 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
35 (eq_attr "type" "fdivs")) 31 29)
37 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
38 (eq_attr "type" "fmul")) 9 7)
40 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
41 (eq_attr "type" "ffmul")) 6 4)
43 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
44 (eq_attr "type" "farith")) 4 2)
46 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
47 (eq_attr "type" "ffarith")) 2 2)
49 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
50 (eq_attr "type" "r_2_f")) 5 3)
52 (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
53 (eq_attr "type" "f_2_r")) 1 2)
55 ; The fpa10 doesn't really have a memory read unit, but it can start to
56 ; speculatively execute the instruction in the pipeline, provided the data
57 ; is already loaded, so pretend reads have a delay of 2 (and that the
58 ; pipeline is infinite).
60 (define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")
61 (eq_attr "type" "f_load")) 3 1)
63 (define_insn "*addsf3_fpa"
64 [(set (match_operand:SF 0 "s_register_operand" "=f,f")
65 (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
66 (match_operand:SF 2 "fpa_add_operand" "fG,H")))]
67 "TARGET_ARM && TARGET_HARD_FLOAT"
70 suf%?s\\t%0, %1, #%N2"
71 [(set_attr "type" "farith")
72 (set_attr "predicable" "yes")]
75 (define_insn "*adddf3_fpa"
76 [(set (match_operand:DF 0 "s_register_operand" "=f,f")
77 (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
78 (match_operand:DF 2 "fpa_add_operand" "fG,H")))]
79 "TARGET_ARM && TARGET_HARD_FLOAT"
82 suf%?d\\t%0, %1, #%N2"
83 [(set_attr "type" "farith")
84 (set_attr "predicable" "yes")]
87 (define_insn "*adddf_esfdf_df_fpa"
88 [(set (match_operand:DF 0 "s_register_operand" "=f,f")
89 (plus:DF (float_extend:DF
90 (match_operand:SF 1 "s_register_operand" "f,f"))
91 (match_operand:DF 2 "fpa_add_operand" "fG,H")))]
92 "TARGET_ARM && TARGET_HARD_FLOAT"
95 suf%?d\\t%0, %1, #%N2"
96 [(set_attr "type" "farith")
97 (set_attr "predicable" "yes")]
100 (define_insn "*adddf_df_esfdf_fpa"
101 [(set (match_operand:DF 0 "s_register_operand" "=f")
102 (plus:DF (match_operand:DF 1 "s_register_operand" "f")
104 (match_operand:SF 2 "s_register_operand" "f"))))]
105 "TARGET_ARM && TARGET_HARD_FLOAT"
106 "adf%?d\\t%0, %1, %2"
107 [(set_attr "type" "farith")
108 (set_attr "predicable" "yes")]
111 (define_insn "*adddf_esfdf_esfdf_fpa"
112 [(set (match_operand:DF 0 "s_register_operand" "=f")
113 (plus:DF (float_extend:DF
114 (match_operand:SF 1 "s_register_operand" "f"))
116 (match_operand:SF 2 "s_register_operand" "f"))))]
117 "TARGET_ARM && TARGET_HARD_FLOAT"
118 "adf%?d\\t%0, %1, %2"
119 [(set_attr "type" "farith")
120 (set_attr "predicable" "yes")]
123 (define_insn "*subsf3_fpa"
124 [(set (match_operand:SF 0 "s_register_operand" "=f,f")
125 (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
126 (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
127 "TARGET_ARM && TARGET_HARD_FLOAT"
131 [(set_attr "type" "farith")]
134 (define_insn "*subdf3_fpa"
135 [(set (match_operand:DF 0 "s_register_operand" "=f,f")
136 (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
137 (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
138 "TARGET_ARM && TARGET_HARD_FLOAT"
142 [(set_attr "type" "farith")
143 (set_attr "predicable" "yes")]
146 (define_insn "*subdf_esfdf_df_fpa"
147 [(set (match_operand:DF 0 "s_register_operand" "=f")
148 (minus:DF (float_extend:DF
149 (match_operand:SF 1 "s_register_operand" "f"))
150 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
151 "TARGET_ARM && TARGET_HARD_FLOAT"
152 "suf%?d\\t%0, %1, %2"
153 [(set_attr "type" "farith")
154 (set_attr "predicable" "yes")]
157 (define_insn "*subdf_df_esfdf_fpa"
158 [(set (match_operand:DF 0 "s_register_operand" "=f,f")
159 (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
161 (match_operand:SF 2 "s_register_operand" "f,f"))))]
162 "TARGET_ARM && TARGET_HARD_FLOAT"
166 [(set_attr "type" "farith")
167 (set_attr "predicable" "yes")]
170 (define_insn "*subdf_esfdf_esfdf_fpa"
171 [(set (match_operand:DF 0 "s_register_operand" "=f")
172 (minus:DF (float_extend:DF
173 (match_operand:SF 1 "s_register_operand" "f"))
175 (match_operand:SF 2 "s_register_operand" "f"))))]
176 "TARGET_ARM && TARGET_HARD_FLOAT"
177 "suf%?d\\t%0, %1, %2"
178 [(set_attr "type" "farith")
179 (set_attr "predicable" "yes")]
182 (define_insn "*mulsf3_fpa"
183 [(set (match_operand:SF 0 "s_register_operand" "=f")
184 (mult:SF (match_operand:SF 1 "s_register_operand" "f")
185 (match_operand:SF 2 "fpa_rhs_operand" "fG")))]
186 "TARGET_ARM && TARGET_HARD_FLOAT"
187 "fml%?s\\t%0, %1, %2"
188 [(set_attr "type" "ffmul")
189 (set_attr "predicable" "yes")]
192 (define_insn "*muldf3_fpa"
193 [(set (match_operand:DF 0 "s_register_operand" "=f")
194 (mult:DF (match_operand:DF 1 "s_register_operand" "f")
195 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
196 "TARGET_ARM && TARGET_HARD_FLOAT"
197 "muf%?d\\t%0, %1, %2"
198 [(set_attr "type" "fmul")
199 (set_attr "predicable" "yes")]
202 (define_insn "*muldf_esfdf_df_fpa"
203 [(set (match_operand:DF 0 "s_register_operand" "=f")
204 (mult:DF (float_extend:DF
205 (match_operand:SF 1 "s_register_operand" "f"))
206 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
207 "TARGET_ARM && TARGET_HARD_FLOAT"
208 "muf%?d\\t%0, %1, %2"
209 [(set_attr "type" "fmul")
210 (set_attr "predicable" "yes")]
213 (define_insn "*muldf_df_esfdf_fpa"
214 [(set (match_operand:DF 0 "s_register_operand" "=f")
215 (mult:DF (match_operand:DF 1 "s_register_operand" "f")
217 (match_operand:SF 2 "s_register_operand" "f"))))]
218 "TARGET_ARM && TARGET_HARD_FLOAT"
219 "muf%?d\\t%0, %1, %2"
220 [(set_attr "type" "fmul")
221 (set_attr "predicable" "yes")]
224 (define_insn "*muldf_esfdf_esfdf_fpa"
225 [(set (match_operand:DF 0 "s_register_operand" "=f")
227 (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
228 (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
229 "TARGET_ARM && TARGET_HARD_FLOAT"
230 "muf%?d\\t%0, %1, %2"
231 [(set_attr "type" "fmul")
232 (set_attr "predicable" "yes")]
237 (define_insn "*divsf3_fpa"
238 [(set (match_operand:SF 0 "s_register_operand" "=f,f")
239 (div:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
240 (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
241 "TARGET_ARM && TARGET_HARD_FLOAT"
245 [(set_attr "type" "fdivs")
246 (set_attr "predicable" "yes")]
249 (define_insn "*divdf3_fpa"
250 [(set (match_operand:DF 0 "s_register_operand" "=f,f")
251 (div:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
252 (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
253 "TARGET_ARM && TARGET_HARD_FLOAT"
257 [(set_attr "type" "fdivd")
258 (set_attr "predicable" "yes")]
261 (define_insn "*divdf_esfdf_df_fpa"
262 [(set (match_operand:DF 0 "s_register_operand" "=f")
263 (div:DF (float_extend:DF
264 (match_operand:SF 1 "s_register_operand" "f"))
265 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
266 "TARGET_ARM && TARGET_HARD_FLOAT"
267 "dvf%?d\\t%0, %1, %2"
268 [(set_attr "type" "fdivd")
269 (set_attr "predicable" "yes")]
272 (define_insn "*divdf_df_esfdf_fpa"
273 [(set (match_operand:DF 0 "s_register_operand" "=f")
274 (div:DF (match_operand:DF 1 "fpa_rhs_operand" "fG")
276 (match_operand:SF 2 "s_register_operand" "f"))))]
277 "TARGET_ARM && TARGET_HARD_FLOAT"
278 "rdf%?d\\t%0, %2, %1"
279 [(set_attr "type" "fdivd")
280 (set_attr "predicable" "yes")]
283 (define_insn "*divdf_esfdf_esfdf_fpa"
284 [(set (match_operand:DF 0 "s_register_operand" "=f")
285 (div:DF (float_extend:DF
286 (match_operand:SF 1 "s_register_operand" "f"))
288 (match_operand:SF 2 "s_register_operand" "f"))))]
289 "TARGET_ARM && TARGET_HARD_FLOAT"
290 "dvf%?d\\t%0, %1, %2"
291 [(set_attr "type" "fdivd")
292 (set_attr "predicable" "yes")]
295 (define_insn "*modsf3_fpa"
296 [(set (match_operand:SF 0 "s_register_operand" "=f")
297 (mod:SF (match_operand:SF 1 "s_register_operand" "f")
298 (match_operand:SF 2 "fpa_rhs_operand" "fG")))]
299 "TARGET_ARM && TARGET_HARD_FLOAT"
300 "rmf%?s\\t%0, %1, %2"
301 [(set_attr "type" "fdivs")
302 (set_attr "predicable" "yes")]
305 (define_insn "*moddf3_fpa"
306 [(set (match_operand:DF 0 "s_register_operand" "=f")
307 (mod:DF (match_operand:DF 1 "s_register_operand" "f")
308 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
309 "TARGET_ARM && TARGET_HARD_FLOAT"
310 "rmf%?d\\t%0, %1, %2"
311 [(set_attr "type" "fdivd")
312 (set_attr "predicable" "yes")]
315 (define_insn "*moddf_esfdf_df_fpa"
316 [(set (match_operand:DF 0 "s_register_operand" "=f")
317 (mod:DF (float_extend:DF
318 (match_operand:SF 1 "s_register_operand" "f"))
319 (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
320 "TARGET_ARM && TARGET_HARD_FLOAT"
321 "rmf%?d\\t%0, %1, %2"
322 [(set_attr "type" "fdivd")
323 (set_attr "predicable" "yes")]
326 (define_insn "*moddf_df_esfdf_fpa"
327 [(set (match_operand:DF 0 "s_register_operand" "=f")
328 (mod:DF (match_operand:DF 1 "s_register_operand" "f")
330 (match_operand:SF 2 "s_register_operand" "f"))))]
331 "TARGET_ARM && TARGET_HARD_FLOAT"
332 "rmf%?d\\t%0, %1, %2"
333 [(set_attr "type" "fdivd")
334 (set_attr "predicable" "yes")]
337 (define_insn "*moddf_esfdf_esfdf_fpa"
338 [(set (match_operand:DF 0 "s_register_operand" "=f")
339 (mod:DF (float_extend:DF
340 (match_operand:SF 1 "s_register_operand" "f"))
342 (match_operand:SF 2 "s_register_operand" "f"))))]
343 "TARGET_ARM && TARGET_HARD_FLOAT"
344 "rmf%?d\\t%0, %1, %2"
345 [(set_attr "type" "fdivd")
346 (set_attr "predicable" "yes")]
349 (define_insn "*negsf2_fpa"
350 [(set (match_operand:SF 0 "s_register_operand" "=f")
351 (neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
352 "TARGET_ARM && TARGET_HARD_FLOAT"
354 [(set_attr "type" "ffarith")
355 (set_attr "predicable" "yes")]
358 (define_insn "*negdf2_fpa"
359 [(set (match_operand:DF 0 "s_register_operand" "=f")
360 (neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
361 "TARGET_ARM && TARGET_HARD_FLOAT"
363 [(set_attr "type" "ffarith")
364 (set_attr "predicable" "yes")]
367 (define_insn "*negdf_esfdf_fpa"
368 [(set (match_operand:DF 0 "s_register_operand" "=f")
369 (neg:DF (float_extend:DF
370 (match_operand:SF 1 "s_register_operand" "f"))))]
371 "TARGET_ARM && TARGET_HARD_FLOAT"
373 [(set_attr "type" "ffarith")
374 (set_attr "predicable" "yes")]
377 (define_insn "*abssf2_fpa"
378 [(set (match_operand:SF 0 "s_register_operand" "=f")
379 (abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
380 "TARGET_ARM && TARGET_HARD_FLOAT"
382 [(set_attr "type" "ffarith")
383 (set_attr "predicable" "yes")]
386 (define_insn "*absdf2_fpa"
387 [(set (match_operand:DF 0 "s_register_operand" "=f")
388 (abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
389 "TARGET_ARM && TARGET_HARD_FLOAT"
391 [(set_attr "type" "ffarith")
392 (set_attr "predicable" "yes")]
395 (define_insn "*absdf_esfdf_fpa"
396 [(set (match_operand:DF 0 "s_register_operand" "=f")
397 (abs:DF (float_extend:DF
398 (match_operand:SF 1 "s_register_operand" "f"))))]
399 "TARGET_ARM && TARGET_HARD_FLOAT"
401 [(set_attr "type" "ffarith")
402 (set_attr "predicable" "yes")]
405 (define_insn "*sqrtsf2_fpa"
406 [(set (match_operand:SF 0 "s_register_operand" "=f")
407 (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
408 "TARGET_ARM && TARGET_HARD_FLOAT"
410 [(set_attr "type" "float_em")
411 (set_attr "predicable" "yes")]
414 (define_insn "*sqrtdf2_fpa"
415 [(set (match_operand:DF 0 "s_register_operand" "=f")
416 (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
417 "TARGET_ARM && TARGET_HARD_FLOAT"
419 [(set_attr "type" "float_em")
420 (set_attr "predicable" "yes")]
423 (define_insn "*sqrtdf_esfdf_fpa"
424 [(set (match_operand:DF 0 "s_register_operand" "=f")
425 (sqrt:DF (float_extend:DF
426 (match_operand:SF 1 "s_register_operand" "f"))))]
427 "TARGET_ARM && TARGET_HARD_FLOAT"
429 [(set_attr "type" "float_em")
430 (set_attr "predicable" "yes")]
433 (define_insn "*floatsisf2_fpa"
434 [(set (match_operand:SF 0 "s_register_operand" "=f")
435 (float:SF (match_operand:SI 1 "s_register_operand" "r")))]
436 "TARGET_ARM && TARGET_HARD_FLOAT"
438 [(set_attr "type" "r_2_f")
439 (set_attr "predicable" "yes")]
442 (define_insn "*floatsidf2_fpa"
443 [(set (match_operand:DF 0 "s_register_operand" "=f")
444 (float:DF (match_operand:SI 1 "s_register_operand" "r")))]
445 "TARGET_ARM && TARGET_HARD_FLOAT"
447 [(set_attr "type" "r_2_f")
448 (set_attr "predicable" "yes")]
451 (define_insn "*fix_truncsfsi2_fpa"
452 [(set (match_operand:SI 0 "s_register_operand" "=r")
453 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))]
454 "TARGET_ARM && TARGET_HARD_FLOAT"
456 [(set_attr "type" "f_2_r")
457 (set_attr "predicable" "yes")]
460 (define_insn "*fix_truncdfsi2_fpa"
461 [(set (match_operand:SI 0 "s_register_operand" "=r")
462 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))]
463 "TARGET_ARM && TARGET_HARD_FLOAT"
465 [(set_attr "type" "f_2_r")
466 (set_attr "predicable" "yes")]
469 (define_insn "*truncdfsf2_fpa"
470 [(set (match_operand:SF 0 "s_register_operand" "=f")
472 (match_operand:DF 1 "s_register_operand" "f")))]
473 "TARGET_ARM && TARGET_HARD_FLOAT"
475 [(set_attr "type" "ffarith")
476 (set_attr "predicable" "yes")]
479 (define_insn "*extendsfdf2_fpa"
480 [(set (match_operand:DF 0 "s_register_operand" "=f")
481 (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))]
482 "TARGET_ARM && TARGET_HARD_FLOAT"
484 [(set_attr "type" "ffarith")
485 (set_attr "predicable" "yes")]
488 (define_insn "*movsf_fpa"
489 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
490 (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
493 && (GET_CODE (operands[0]) != MEM
494 || register_operand (operands[1], SFmode))"
500 str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
501 stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
503 ldr%?\\t%0, %1\\t%@ float
504 str%?\\t%1, %0\\t%@ float"
505 [(set_attr "length" "4,4,4,4,8,8,4,4,4")
506 (set_attr "predicable" "yes")
508 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")
509 (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
510 (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
513 (define_insn "*movdf_fpa"
514 [(set (match_operand:DF 0 "nonimmediate_operand"
515 "=r,Q,r,m,r, f, f,f, m,!f,!r")
516 (match_operand:DF 1 "general_operand"
517 "Q, r,r,r,mF,fG,H,mF,f,r, f"))]
520 && (GET_CODE (operands[0]) != MEM
521 || register_operand (operands[1], DFmode))"
524 switch (which_alternative)
527 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
528 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
529 case 2: case 3: case 4: return output_move_double (operands);
530 case 5: return \"mvf%?d\\t%0, %1\";
531 case 6: return \"mnf%?d\\t%0, #%N1\";
532 case 7: return \"ldf%?d\\t%0, %1\";
533 case 8: return \"stf%?d\\t%1, %0\";
534 case 9: return output_mov_double_fpa_from_arm (operands);
535 case 10: return output_mov_double_arm_from_fpa (operands);
539 [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
540 (set_attr "predicable" "yes")
542 "load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
543 (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
544 (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
547 ;; Saving and restoring the floating point registers in the prologue should
548 ;; be done in XFmode, even though we don't support that for anything else
549 ;; (Well, strictly it's 'internal representation', but that's effectively
552 (define_insn "*movxf_fpa"
553 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
554 (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
555 "TARGET_ARM && TARGET_HARD_FLOAT && reload_completed"
557 switch (which_alternative)
560 case 0: return \"mvf%?e\\t%0, %1\";
561 case 1: return \"mnf%?e\\t%0, #%N1\";
562 case 2: return \"ldf%?e\\t%0, %1\";
563 case 3: return \"stf%?e\\t%1, %0\";
564 case 4: return output_mov_long_double_fpa_from_arm (operands);
565 case 5: return output_mov_long_double_arm_from_fpa (operands);
566 case 6: return output_mov_long_double_arm_from_arm (operands);
569 [(set_attr "length" "4,4,4,4,8,8,12")
570 (set_attr "predicable" "yes")
571 (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")
572 (set_attr "pool_range" "*,*,1024,*,*,*,*")
573 (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
576 (define_insn "*cmpsf_fpa"
577 [(set (reg:CCFP CC_REGNUM)
578 (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
579 (match_operand:SF 1 "fpa_add_operand" "fG,H")))]
580 "TARGET_ARM && TARGET_HARD_FLOAT"
584 [(set_attr "conds" "set")
585 (set_attr "type" "f_2_r")]
588 (define_insn "*cmpdf_fpa"
589 [(set (reg:CCFP CC_REGNUM)
590 (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
591 (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
592 "TARGET_ARM && TARGET_HARD_FLOAT"
596 [(set_attr "conds" "set")
597 (set_attr "type" "f_2_r")]
600 (define_insn "*cmpesfdf_df_fpa"
601 [(set (reg:CCFP CC_REGNUM)
602 (compare:CCFP (float_extend:DF
603 (match_operand:SF 0 "s_register_operand" "f,f"))
604 (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
605 "TARGET_ARM && TARGET_HARD_FLOAT"
609 [(set_attr "conds" "set")
610 (set_attr "type" "f_2_r")]
613 (define_insn "*cmpdf_esfdf_fpa"
614 [(set (reg:CCFP CC_REGNUM)
615 (compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
617 (match_operand:SF 1 "s_register_operand" "f"))))]
618 "TARGET_ARM && TARGET_HARD_FLOAT"
620 [(set_attr "conds" "set")
621 (set_attr "type" "f_2_r")]
624 (define_insn "*cmpsf_trap_fpa"
625 [(set (reg:CCFPE CC_REGNUM)
626 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
627 (match_operand:SF 1 "fpa_add_operand" "fG,H")))]
628 "TARGET_ARM && TARGET_HARD_FLOAT"
632 [(set_attr "conds" "set")
633 (set_attr "type" "f_2_r")]
636 (define_insn "*cmpdf_trap_fpa"
637 [(set (reg:CCFPE CC_REGNUM)
638 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
639 (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
640 "TARGET_ARM && TARGET_HARD_FLOAT"
644 [(set_attr "conds" "set")
645 (set_attr "type" "f_2_r")]
648 (define_insn "*cmp_esfdf_df_trap_fpa"
649 [(set (reg:CCFPE CC_REGNUM)
650 (compare:CCFPE (float_extend:DF
651 (match_operand:SF 0 "s_register_operand" "f,f"))
652 (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
653 "TARGET_ARM && TARGET_HARD_FLOAT"
657 [(set_attr "conds" "set")
658 (set_attr "type" "f_2_r")]
661 (define_insn "*cmp_df_esfdf_trap_fpa"
662 [(set (reg:CCFPE CC_REGNUM)
663 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
665 (match_operand:SF 1 "s_register_operand" "f"))))]
666 "TARGET_ARM && TARGET_HARD_FLOAT"
668 [(set_attr "conds" "set")
669 (set_attr "type" "f_2_r")]
672 (define_insn "*movsfcc_fpa"
673 [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
675 (match_operator 3 "arm_comparison_operator"
676 [(match_operand 4 "cc_register" "") (const_int 0)])
677 (match_operand:SF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
678 (match_operand:SF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
679 "TARGET_ARM && TARGET_HARD_FLOAT"
685 mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
686 mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
687 mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
688 mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
689 [(set_attr "length" "4,4,4,4,8,8,8,8")
690 (set_attr "type" "ffarith")
691 (set_attr "conds" "use")]
694 (define_insn "*movdfcc_fpa"
695 [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
697 (match_operator 3 "arm_comparison_operator"
698 [(match_operand 4 "cc_register" "") (const_int 0)])
699 (match_operand:DF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
700 (match_operand:DF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
701 "TARGET_ARM && TARGET_HARD_FLOAT"
707 mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
708 mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
709 mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
710 mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
711 [(set_attr "length" "4,4,4,4,8,8,8,8")
712 (set_attr "type" "ffarith")
713 (set_attr "conds" "use")]