| blob | c4b3e13c82889d8ff298414ace8a4ddfbb09bf77 |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;;
7 ;; This file is part of GCC.
8 ;;
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; any later version.
13 ;;
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
18 ;;
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_LDGP1 1)
30 (UNSPEC_INSXH 2)
31 (UNSPEC_MSKXH 3)
32 (UNSPEC_CVTQL 4)
33 (UNSPEC_CVTLQ 5)
34 (UNSPEC_UMK_LAUM 6)
35 (UNSPEC_UMK_LALM 7)
36 (UNSPEC_UMK_LAL 8)
37 (UNSPEC_UMK_LOAD_CIW 9)
38 (UNSPEC_LDGP2 10)
39 (UNSPEC_LITERAL 11)
40 (UNSPEC_LITUSE 12)
41 (UNSPEC_SIBCALL 13)
42 (UNSPEC_SYMBOL 14)
44 ;; TLS Support
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
47 (UNSPEC_TLSGD 17)
48 (UNSPEC_TLSLDM 18)
49 (UNSPEC_DTPREL 19)
50 (UNSPEC_TPREL 20)
51 (UNSPEC_TP 21)
53 ;; Builtins
54 (UNSPEC_CMPBGE 22)
55 (UNSPEC_ZAP 23)
56 (UNSPEC_AMASK 24)
57 (UNSPEC_IMPLVER 25)
58 (UNSPEC_PERR 26)
59 (UNSPEC_COPYSIGN 27)
61 ;; Atomic operations
62 (UNSPEC_MB 28)
63 (UNSPEC_ATOMIC 31)
64 (UNSPEC_CMPXCHG 32)
65 (UNSPEC_XCHG 33)
66 ])
68 ;; UNSPEC_VOLATILE:
70 (define_constants
71 [(UNSPECV_IMB 0)
72 (UNSPECV_BLOCKAGE 1)
73 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
74 (UNSPECV_LONGJMP 3) ; builtin_longjmp
75 (UNSPECV_TRAPB 4)
76 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
77 (UNSPECV_REALIGN 6)
78 (UNSPECV_EHR 7) ; exception_receiver
79 (UNSPECV_MCOUNT 8)
80 (UNSPECV_FORCE_MOV 9)
81 (UNSPECV_LDGP1 10)
82 (UNSPECV_PLDGP2 11) ; prologue ldgp
83 (UNSPECV_SET_TP 12)
84 (UNSPECV_RPCC 13)
85 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
86 (UNSPECV_LL 15) ; load-locked
87 (UNSPECV_SC 16) ; store-conditional
88 ])
90 ;; On non-BWX targets, CQImode must be handled the similarly to HImode
91 ;; when generating reloads.
92 (define_mode_iterator RELOAD12 [QI HI CQI])
93 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
95 ;; Other mode iterators
96 (define_mode_iterator I12MODE [QI HI])
97 (define_mode_iterator I48MODE [SI DI])
98 (define_mode_attr modesuffix [(SI "l") (DI "q")])
100 ;; Where necessary, the suffixes _le and _be are used to distinguish between
101 ;; little-endian and big-endian patterns.
102 ;;
103 ;; Note that the Unicos/Mk assembler does not support the following
104 ;; opcodes: mov, fmov, nop, fnop, unop.
105 \f
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in alpha.h.
109 (define_attr "tune" "ev4,ev5,ev6"
110 (const (symbol_ref "((enum attr_tune) alpha_tune)")))
112 ;; Define an insn type attribute. This is used in function unit delay
113 ;; computations, among other purposes. For the most part, we use the names
114 ;; defined in the EV4 documentation, but add a few that we have to know about
115 ;; separately.
117 (define_attr "type"
118 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
119 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
120 multi,none"
121 (const_string "iadd"))
123 ;; Describe a user's asm statement.
124 (define_asm_attributes
125 [(set_attr "type" "multi")])
127 ;; Define the operand size an insn operates on. Used primarily by mul
128 ;; and div operations that have size dependent timings.
130 (define_attr "opsize" "si,di,udi"
131 (const_string "di"))
133 ;; The TRAP attribute marks instructions that may generate traps
134 ;; (which are imprecise and may need a trapb if software completion
135 ;; is desired).
137 (define_attr "trap" "no,yes"
138 (const_string "no"))
140 ;; The ROUND_SUFFIX attribute marks which instructions require a
141 ;; rounding-mode suffix. The value NONE indicates no suffix,
142 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
144 (define_attr "round_suffix" "none,normal,c"
145 (const_string "none"))
147 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
148 ;; NONE no suffix
149 ;; SU accepts only /su (cmpt et al)
150 ;; SUI accepts only /sui (cvtqt and cvtqs)
151 ;; V_SV accepts /v and /sv (cvtql only)
152 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
153 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
154 ;;
155 ;; The actual suffix emitted is controlled by alpha_fptm.
157 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
158 (const_string "none"))
160 ;; The length of an instruction sequence in bytes.
162 (define_attr "length" ""
163 (const_int 4))
165 ;; The USEGP attribute marks instructions that have relocations that use
166 ;; the GP.
168 (define_attr "usegp" "no,yes"
169 (cond [(eq_attr "type" "ldsym,jsr")
170 (const_string "yes")
171 (eq_attr "type" "ild,fld,ist,fst")
172 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
173 ]
174 (const_string "no")))
176 ;; The CANNOT_COPY attribute marks instructions with relocations that
177 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
178 ;; since they have to stay in 1-1 correspondence with one another. This
179 ;; also includes jsr insns, since they must stay in correspondence with
180 ;; the immediately following gpdisp instructions.
182 (define_attr "cannot_copy" "false,true"
183 (const_string "false"))
184 \f
185 ;; Include scheduling descriptions.
187 (include "ev4.md")
188 (include "ev5.md")
189 (include "ev6.md")
191 \f
192 ;; Operand and operator predicates and constraints
194 (include "predicates.md")
195 (include "constraints.md")
197 \f
198 ;; First define the arithmetic insns. Note that the 32-bit forms also
199 ;; sign-extend.
201 ;; Handle 32-64 bit extension from memory to a floating point register
202 ;; specially, since this occurs frequently in int->double conversions.
203 ;;
204 ;; Note that while we must retain the =f case in the insn for reload's
205 ;; benefit, it should be eliminated after reload, so we should never emit
206 ;; code for that case. But we don't reject the possibility.
208 (define_expand "extendsidi2"
209 [(set (match_operand:DI 0 "register_operand" "")
210 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
211 ""
212 "")
214 (define_insn "*cvtlq"
215 [(set (match_operand:DI 0 "register_operand" "=f")
216 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
217 UNSPEC_CVTLQ))]
218 ""
219 "cvtlq %1,%0"
220 [(set_attr "type" "fadd")])
222 (define_insn "*extendsidi2_1"
223 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
224 (sign_extend:DI
225 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
226 ""
227 "@
228 addl $31,%1,%0
229 ldl %0,%1
230 lds %0,%1\;cvtlq %0,%0"
231 [(set_attr "type" "iadd,ild,fld")
232 (set_attr "length" "*,*,8")])
234 (define_split
235 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
236 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
237 "reload_completed"
238 [(set (match_dup 2) (match_dup 1))
239 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
240 {
241 operands[1] = adjust_address (operands[1], SFmode, 0);
242 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
243 })
245 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
246 ;; reload when converting fp->int.
248 (define_peephole2
249 [(set (match_operand:SI 0 "hard_int_register_operand" "")
250 (match_operand:SI 1 "memory_operand" ""))
251 (set (match_operand:DI 2 "hard_int_register_operand" "")
252 (sign_extend:DI (match_dup 0)))]
253 "true_regnum (operands[0]) == true_regnum (operands[2])
254 || peep2_reg_dead_p (2, operands[0])"
255 [(set (match_dup 2)
256 (sign_extend:DI (match_dup 1)))]
257 "")
259 ;; Don't say we have addsi3 if optimizing. This generates better code. We
260 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
261 (define_expand "addsi3"
262 [(set (match_operand:SI 0 "register_operand" "")
263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
264 (match_operand:SI 2 "add_operand" "")))]
265 "! optimize"
266 "")
268 (define_insn "*addsi_internal"
269 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
270 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
271 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
272 ""
273 "@
274 addl %r1,%2,%0
275 subl %r1,%n2,%0
276 lda %0,%2(%r1)
277 ldah %0,%h2(%r1)")
279 (define_split
280 [(set (match_operand:SI 0 "register_operand" "")
281 (plus:SI (match_operand:SI 1 "register_operand" "")
282 (match_operand:SI 2 "const_int_operand" "")))]
283 "! add_operand (operands[2], SImode)"
284 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
285 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
286 {
287 HOST_WIDE_INT val = INTVAL (operands[2]);
288 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
289 HOST_WIDE_INT rest = val - low;
291 operands[3] = GEN_INT (rest);
292 operands[4] = GEN_INT (low);
293 })
295 (define_insn "*addsi_se"
296 [(set (match_operand:DI 0 "register_operand" "=r,r")
297 (sign_extend:DI
298 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
299 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
300 ""
301 "@
302 addl %r1,%2,%0
303 subl %r1,%n2,%0")
305 (define_insn "*addsi_se2"
306 [(set (match_operand:DI 0 "register_operand" "=r,r")
307 (sign_extend:DI
308 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
309 (match_operand:DI 2 "sext_add_operand" "rI,O"))
310 0)))]
311 ""
312 "@
313 addl %r1,%2,%0
314 subl %r1,%n2,%0")
316 (define_split
317 [(set (match_operand:DI 0 "register_operand" "")
318 (sign_extend:DI
319 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
320 (match_operand:SI 2 "const_int_operand" ""))))
321 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
322 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
323 && INTVAL (operands[2]) % 4 == 0"
324 [(set (match_dup 3) (match_dup 4))
325 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
326 (match_dup 5))
327 (match_dup 1))))]
328 {
329 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
330 int mult = 4;
332 if (val % 2 == 0)
333 val /= 2, mult = 8;
335 operands[4] = GEN_INT (val);
336 operands[5] = GEN_INT (mult);
337 })
339 (define_split
340 [(set (match_operand:DI 0 "register_operand" "")
341 (sign_extend:DI
342 (plus:SI (match_operator:SI 1 "comparison_operator"
343 [(match_operand 2 "" "")
344 (match_operand 3 "" "")])
345 (match_operand:SI 4 "add_operand" ""))))
346 (clobber (match_operand:DI 5 "register_operand" ""))]
347 ""
348 [(set (match_dup 5) (match_dup 6))
349 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
350 {
351 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
352 operands[2], operands[3]);
353 operands[7] = gen_lowpart (SImode, operands[5]);
354 })
356 (define_insn "addvsi3"
357 [(set (match_operand:SI 0 "register_operand" "=r,r")
358 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
359 (match_operand:SI 2 "sext_add_operand" "rI,O")))
360 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
361 (sign_extend:DI (match_dup 2)))
362 (sign_extend:DI (plus:SI (match_dup 1)
363 (match_dup 2))))
364 (const_int 0))]
365 ""
366 "@
367 addlv %r1,%2,%0
368 sublv %r1,%n2,%0")
370 (define_expand "adddi3"
371 [(set (match_operand:DI 0 "register_operand" "")
372 (plus:DI (match_operand:DI 1 "register_operand" "")
373 (match_operand:DI 2 "add_operand" "")))]
374 ""
375 "")
377 (define_insn "*adddi_er_lo16_dtp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
380 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
381 "HAVE_AS_TLS"
382 "lda %0,%2(%1)\t\t!dtprel")
384 (define_insn "*adddi_er_hi32_dtp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (plus:DI (match_operand:DI 1 "register_operand" "r")
387 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
388 "HAVE_AS_TLS"
389 "ldah %0,%2(%1)\t\t!dtprelhi")
391 (define_insn "*adddi_er_lo32_dtp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
394 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
395 "HAVE_AS_TLS"
396 "lda %0,%2(%1)\t\t!dtprello")
398 (define_insn "*adddi_er_lo16_tp"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
401 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
402 "HAVE_AS_TLS"
403 "lda %0,%2(%1)\t\t!tprel")
405 (define_insn "*adddi_er_hi32_tp"
406 [(set (match_operand:DI 0 "register_operand" "=r")
407 (plus:DI (match_operand:DI 1 "register_operand" "r")
408 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
409 "HAVE_AS_TLS"
410 "ldah %0,%2(%1)\t\t!tprelhi")
412 (define_insn "*adddi_er_lo32_tp"
413 [(set (match_operand:DI 0 "register_operand" "=r")
414 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
415 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
416 "HAVE_AS_TLS"
417 "lda %0,%2(%1)\t\t!tprello")
419 (define_insn "*adddi_er_high_l"
420 [(set (match_operand:DI 0 "register_operand" "=r")
421 (plus:DI (match_operand:DI 1 "register_operand" "r")
422 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
423 "TARGET_EXPLICIT_RELOCS && reload_completed"
424 "ldah %0,%2(%1)\t\t!gprelhigh"
425 [(set_attr "usegp" "yes")])
427 (define_split
428 [(set (match_operand:DI 0 "register_operand" "")
429 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
430 "TARGET_EXPLICIT_RELOCS && reload_completed"
431 [(set (match_dup 0)
432 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
433 "operands[2] = pic_offset_table_rtx;")
435 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
436 ;; With complications like
437 ;;
438 ;; The NT stack unwind code can't handle a subq to adjust the stack
439 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
440 ;; the exception handling code will loop if a subq is used and an
441 ;; exception occurs.
442 ;;
443 ;; The 19980616 change to emit prologues as RTL also confused some
444 ;; versions of GDB, which also interprets prologues. This has been
445 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
446 ;; use lda here.
447 ;;
448 ;; and the fact that the three insns schedule exactly the same, it's
449 ;; just not worth the effort.
451 (define_insn "*adddi_internal"
452 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
453 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
454 (match_operand:DI 2 "add_operand" "r,K,L")))]
455 ""
456 "@
457 addq %1,%2,%0
458 lda %0,%2(%1)
459 ldah %0,%h2(%1)")
461 ;; ??? Allow large constants when basing off the frame pointer or some
462 ;; virtual register that may eliminate to the frame pointer. This is
463 ;; done because register elimination offsets will change the hi/lo split,
464 ;; and if we split before reload, we will require additional instructions.
466 (define_insn "*adddi_fp_hack"
467 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
468 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
469 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
470 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
471 && INTVAL (operands[2]) >= 0
472 /* This is the largest constant an lda+ldah pair can add, minus
473 an upper bound on the displacement between SP and AP during
474 register elimination. See INITIAL_ELIMINATION_OFFSET. */
475 && INTVAL (operands[2])
476 < (0x7fff8000
477 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
478 - ALPHA_ROUND(crtl->outgoing_args_size)
479 - (ALPHA_ROUND (get_frame_size ()
480 + max_reg_num () * UNITS_PER_WORD
481 + crtl->args.pretend_args_size)
482 - crtl->args.pretend_args_size))"
483 "@
484 lda %0,%2(%1)
485 ldah %0,%h2(%1)
486 #")
488 ;; Don't do this if we are adjusting SP since we don't want to do it
489 ;; in two steps. Don't split FP sources for the reason listed above.
490 (define_split
491 [(set (match_operand:DI 0 "register_operand" "")
492 (plus:DI (match_operand:DI 1 "register_operand" "")
493 (match_operand:DI 2 "const_int_operand" "")))]
494 "! add_operand (operands[2], DImode)
495 && operands[0] != stack_pointer_rtx
496 && operands[1] != frame_pointer_rtx
497 && operands[1] != arg_pointer_rtx"
498 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
499 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
500 {
501 HOST_WIDE_INT val = INTVAL (operands[2]);
502 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
503 HOST_WIDE_INT rest = val - low;
504 rtx rest_rtx = GEN_INT (rest);
506 operands[4] = GEN_INT (low);
507 if (satisfies_constraint_L (rest_rtx))
508 operands[3] = rest_rtx;
509 else if (can_create_pseudo_p ())
510 {
511 operands[3] = gen_reg_rtx (DImode);
512 emit_move_insn (operands[3], operands[2]);
513 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
514 DONE;
515 }
516 else
517 FAIL;
518 })
520 (define_insn "*saddl"
521 [(set (match_operand:SI 0 "register_operand" "=r,r")
522 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
523 (match_operand:SI 2 "const48_operand" "I,I"))
524 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
525 ""
526 "@
527 s%2addl %1,%3,%0
528 s%2subl %1,%n3,%0")
530 (define_insn "*saddl_se"
531 [(set (match_operand:DI 0 "register_operand" "=r,r")
532 (sign_extend:DI
533 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
534 (match_operand:SI 2 "const48_operand" "I,I"))
535 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
536 ""
537 "@
538 s%2addl %1,%3,%0
539 s%2subl %1,%n3,%0")
541 (define_split
542 [(set (match_operand:DI 0 "register_operand" "")
543 (sign_extend:DI
544 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
545 [(match_operand 2 "" "")
546 (match_operand 3 "" "")])
547 (match_operand:SI 4 "const48_operand" ""))
548 (match_operand:SI 5 "sext_add_operand" ""))))
549 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
550 ""
551 [(set (match_dup 6) (match_dup 7))
552 (set (match_dup 0)
553 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
554 (match_dup 5))))]
555 {
556 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
557 operands[2], operands[3]);
558 operands[8] = gen_lowpart (SImode, operands[6]);
559 })
561 (define_insn "*saddq"
562 [(set (match_operand:DI 0 "register_operand" "=r,r")
563 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
564 (match_operand:DI 2 "const48_operand" "I,I"))
565 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
566 ""
567 "@
568 s%2addq %1,%3,%0
569 s%2subq %1,%n3,%0")
571 (define_insn "addvdi3"
572 [(set (match_operand:DI 0 "register_operand" "=r,r")
573 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
574 (match_operand:DI 2 "sext_add_operand" "rI,O")))
575 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
576 (sign_extend:TI (match_dup 2)))
577 (sign_extend:TI (plus:DI (match_dup 1)
578 (match_dup 2))))
579 (const_int 0))]
580 ""
581 "@
582 addqv %r1,%2,%0
583 subqv %r1,%n2,%0")
585 (define_insn "negsi2"
586 [(set (match_operand:SI 0 "register_operand" "=r")
587 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
588 ""
589 "subl $31,%1,%0")
591 (define_insn "*negsi_se"
592 [(set (match_operand:DI 0 "register_operand" "=r")
593 (sign_extend:DI (neg:SI
594 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
595 ""
596 "subl $31,%1,%0")
598 (define_insn "negvsi2"
599 [(set (match_operand:SI 0 "register_operand" "=r")
600 (neg:SI (match_operand:SI 1 "register_operand" "r")))
601 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
602 (sign_extend:DI (neg:SI (match_dup 1))))
603 (const_int 0))]
604 ""
605 "sublv $31,%1,%0")
607 (define_insn "negdi2"
608 [(set (match_operand:DI 0 "register_operand" "=r")
609 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
610 ""
611 "subq $31,%1,%0")
613 (define_insn "negvdi2"
614 [(set (match_operand:DI 0 "register_operand" "=r")
615 (neg:DI (match_operand:DI 1 "register_operand" "r")))
616 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
617 (sign_extend:TI (neg:DI (match_dup 1))))
618 (const_int 0))]
619 ""
620 "subqv $31,%1,%0")
622 (define_expand "subsi3"
623 [(set (match_operand:SI 0 "register_operand" "")
624 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
625 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
626 "! optimize"
627 "")
629 (define_insn "*subsi_internal"
630 [(set (match_operand:SI 0 "register_operand" "=r")
631 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
632 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
633 ""
634 "subl %r1,%2,%0")
636 (define_insn "*subsi_se"
637 [(set (match_operand:DI 0 "register_operand" "=r")
638 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
639 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
640 ""
641 "subl %r1,%2,%0")
643 (define_insn "*subsi_se2"
644 [(set (match_operand:DI 0 "register_operand" "=r")
645 (sign_extend:DI
646 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
647 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
648 0)))]
649 ""
650 "subl %r1,%2,%0")
652 (define_insn "subvsi3"
653 [(set (match_operand:SI 0 "register_operand" "=r")
654 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
655 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
656 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
657 (sign_extend:DI (match_dup 2)))
658 (sign_extend:DI (minus:SI (match_dup 1)
659 (match_dup 2))))
660 (const_int 0))]
661 ""
662 "sublv %r1,%2,%0")
664 (define_insn "subdi3"
665 [(set (match_operand:DI 0 "register_operand" "=r")
666 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
667 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
668 ""
669 "subq %r1,%2,%0")
671 (define_insn "*ssubl"
672 [(set (match_operand:SI 0 "register_operand" "=r")
673 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
674 (match_operand:SI 2 "const48_operand" "I"))
675 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
676 ""
677 "s%2subl %1,%3,%0")
679 (define_insn "*ssubl_se"
680 [(set (match_operand:DI 0 "register_operand" "=r")
681 (sign_extend:DI
682 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
683 (match_operand:SI 2 "const48_operand" "I"))
684 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
685 ""
686 "s%2subl %1,%3,%0")
688 (define_insn "*ssubq"
689 [(set (match_operand:DI 0 "register_operand" "=r")
690 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
691 (match_operand:DI 2 "const48_operand" "I"))
692 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
693 ""
694 "s%2subq %1,%3,%0")
696 (define_insn "subvdi3"
697 [(set (match_operand:DI 0 "register_operand" "=r")
698 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
699 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
700 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
701 (sign_extend:TI (match_dup 2)))
702 (sign_extend:TI (minus:DI (match_dup 1)
703 (match_dup 2))))
704 (const_int 0))]
705 ""
706 "subqv %r1,%2,%0")
708 ;; The Unicos/Mk assembler doesn't support mull.
710 (define_insn "mulsi3"
711 [(set (match_operand:SI 0 "register_operand" "=r")
712 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
713 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
714 "!TARGET_ABI_UNICOSMK"
715 "mull %r1,%2,%0"
716 [(set_attr "type" "imul")
717 (set_attr "opsize" "si")])
719 (define_insn "*mulsi_se"
720 [(set (match_operand:DI 0 "register_operand" "=r")
721 (sign_extend:DI
722 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
723 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
724 "!TARGET_ABI_UNICOSMK"
725 "mull %r1,%2,%0"
726 [(set_attr "type" "imul")
727 (set_attr "opsize" "si")])
729 (define_insn "mulvsi3"
730 [(set (match_operand:SI 0 "register_operand" "=r")
731 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
732 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
733 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
734 (sign_extend:DI (match_dup 2)))
735 (sign_extend:DI (mult:SI (match_dup 1)
736 (match_dup 2))))
737 (const_int 0))]
738 "!TARGET_ABI_UNICOSMK"
739 "mullv %r1,%2,%0"
740 [(set_attr "type" "imul")
741 (set_attr "opsize" "si")])
743 (define_insn "muldi3"
744 [(set (match_operand:DI 0 "register_operand" "=r")
745 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
746 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
747 ""
748 "mulq %r1,%2,%0"
749 [(set_attr "type" "imul")])
751 (define_insn "mulvdi3"
752 [(set (match_operand:DI 0 "register_operand" "=r")
753 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
754 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
755 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
756 (sign_extend:TI (match_dup 2)))
757 (sign_extend:TI (mult:DI (match_dup 1)
758 (match_dup 2))))
759 (const_int 0))]
760 ""
761 "mulqv %r1,%2,%0"
762 [(set_attr "type" "imul")])
764 (define_expand "umuldi3_highpart"
765 [(set (match_operand:DI 0 "register_operand" "")
766 (truncate:DI
767 (lshiftrt:TI
768 (mult:TI (zero_extend:TI
769 (match_operand:DI 1 "register_operand" ""))
770 (match_operand:DI 2 "reg_or_8bit_operand" ""))
771 (const_int 64))))]
772 ""
773 {
774 if (REG_P (operands[2]))
775 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
776 })
778 (define_insn "*umuldi3_highpart_reg"
779 [(set (match_operand:DI 0 "register_operand" "=r")
780 (truncate:DI
781 (lshiftrt:TI
782 (mult:TI (zero_extend:TI
783 (match_operand:DI 1 "register_operand" "r"))
784 (zero_extend:TI
785 (match_operand:DI 2 "register_operand" "r")))
786 (const_int 64))))]
787 ""
788 "umulh %1,%2,%0"
789 [(set_attr "type" "imul")
790 (set_attr "opsize" "udi")])
792 (define_insn "*umuldi3_highpart_const"
793 [(set (match_operand:DI 0 "register_operand" "=r")
794 (truncate:DI
795 (lshiftrt:TI
796 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
797 (match_operand:TI 2 "cint8_operand" "I"))
798 (const_int 64))))]
799 ""
800 "umulh %1,%2,%0"
801 [(set_attr "type" "imul")
802 (set_attr "opsize" "udi")])
803 \f
804 ;; The divide and remainder operations take their inputs from r24 and
805 ;; r25, put their output in r27, and clobber r23 and r28 on all
806 ;; systems except Unicos/Mk. On Unicos, the standard library provides
807 ;; subroutines which use the standard calling convention and work on
808 ;; DImode operands.
810 ;; ??? Force sign-extension here because some versions of OSF/1 and
811 ;; Interix/NT don't do the right thing if the inputs are not properly
812 ;; sign-extended. But Linux, for instance, does not have this
813 ;; problem. Is it worth the complication here to eliminate the sign
814 ;; extension?
816 (define_expand "divsi3"
817 [(set (match_dup 3)
818 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
819 (set (match_dup 4)
820 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
821 (parallel [(set (match_dup 5)
822 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
823 (clobber (reg:DI 23))
824 (clobber (reg:DI 28))])
825 (set (match_operand:SI 0 "nonimmediate_operand" "")
826 (subreg:SI (match_dup 5) 0))]
827 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
828 {
829 operands[3] = gen_reg_rtx (DImode);
830 operands[4] = gen_reg_rtx (DImode);
831 operands[5] = gen_reg_rtx (DImode);
832 })
834 (define_expand "udivsi3"
835 [(set (match_dup 3)
836 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
837 (set (match_dup 4)
838 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
839 (parallel [(set (match_dup 5)
840 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
841 (clobber (reg:DI 23))
842 (clobber (reg:DI 28))])
843 (set (match_operand:SI 0 "nonimmediate_operand" "")
844 (subreg:SI (match_dup 5) 0))]
845 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
846 {
847 operands[3] = gen_reg_rtx (DImode);
848 operands[4] = gen_reg_rtx (DImode);
849 operands[5] = gen_reg_rtx (DImode);
850 })
852 (define_expand "modsi3"
853 [(set (match_dup 3)
854 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
855 (set (match_dup 4)
856 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
857 (parallel [(set (match_dup 5)
858 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
859 (clobber (reg:DI 23))
860 (clobber (reg:DI 28))])
861 (set (match_operand:SI 0 "nonimmediate_operand" "")
862 (subreg:SI (match_dup 5) 0))]
863 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
864 {
865 operands[3] = gen_reg_rtx (DImode);
866 operands[4] = gen_reg_rtx (DImode);
867 operands[5] = gen_reg_rtx (DImode);
868 })
870 (define_expand "umodsi3"
871 [(set (match_dup 3)
872 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
873 (set (match_dup 4)
874 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
875 (parallel [(set (match_dup 5)
876 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
877 (clobber (reg:DI 23))
878 (clobber (reg:DI 28))])
879 (set (match_operand:SI 0 "nonimmediate_operand" "")
880 (subreg:SI (match_dup 5) 0))]
881 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
882 {
883 operands[3] = gen_reg_rtx (DImode);
884 operands[4] = gen_reg_rtx (DImode);
885 operands[5] = gen_reg_rtx (DImode);
886 })
888 (define_expand "divdi3"
889 [(parallel [(set (match_operand:DI 0 "register_operand" "")
890 (div:DI (match_operand:DI 1 "register_operand" "")
891 (match_operand:DI 2 "register_operand" "")))
892 (clobber (reg:DI 23))
893 (clobber (reg:DI 28))])]
894 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
895 "")
897 (define_expand "udivdi3"
898 [(parallel [(set (match_operand:DI 0 "register_operand" "")
899 (udiv:DI (match_operand:DI 1 "register_operand" "")
900 (match_operand:DI 2 "register_operand" "")))
901 (clobber (reg:DI 23))
902 (clobber (reg:DI 28))])]
903 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
904 "")
906 (define_expand "moddi3"
907 [(use (match_operand:DI 0 "register_operand" ""))
908 (use (match_operand:DI 1 "register_operand" ""))
909 (use (match_operand:DI 2 "register_operand" ""))]
910 "!TARGET_ABI_OPEN_VMS"
911 {
912 if (TARGET_ABI_UNICOSMK)
913 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
914 else
915 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
916 DONE;
917 })
919 (define_expand "moddi3_dft"
920 [(parallel [(set (match_operand:DI 0 "register_operand" "")
921 (mod:DI (match_operand:DI 1 "register_operand" "")
922 (match_operand:DI 2 "register_operand" "")))
923 (clobber (reg:DI 23))
924 (clobber (reg:DI 28))])]
925 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
926 "")
928 ;; On Unicos/Mk, we do as the system's C compiler does:
929 ;; compute the quotient, multiply and subtract.
931 (define_expand "moddi3_umk"
932 [(use (match_operand:DI 0 "register_operand" ""))
933 (use (match_operand:DI 1 "register_operand" ""))
934 (use (match_operand:DI 2 "register_operand" ""))]
935 "TARGET_ABI_UNICOSMK"
936 {
937 rtx div, mul = gen_reg_rtx (DImode);
939 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
940 NULL_RTX, 0, OPTAB_LIB);
941 div = force_reg (DImode, div);
942 emit_insn (gen_muldi3 (mul, operands[2], div));
943 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
944 DONE;
945 })
947 (define_expand "umoddi3"
948 [(use (match_operand:DI 0 "register_operand" ""))
949 (use (match_operand:DI 1 "register_operand" ""))
950 (use (match_operand:DI 2 "register_operand" ""))]
951 "! TARGET_ABI_OPEN_VMS"
952 {
953 if (TARGET_ABI_UNICOSMK)
954 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
955 else
956 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
957 DONE;
958 })
960 (define_expand "umoddi3_dft"
961 [(parallel [(set (match_operand:DI 0 "register_operand" "")
962 (umod:DI (match_operand:DI 1 "register_operand" "")
963 (match_operand:DI 2 "register_operand" "")))
964 (clobber (reg:DI 23))
965 (clobber (reg:DI 28))])]
966 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
967 "")
969 (define_expand "umoddi3_umk"
970 [(use (match_operand:DI 0 "register_operand" ""))
971 (use (match_operand:DI 1 "register_operand" ""))
972 (use (match_operand:DI 2 "register_operand" ""))]
973 "TARGET_ABI_UNICOSMK"
974 {
975 rtx div, mul = gen_reg_rtx (DImode);
977 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
978 NULL_RTX, 1, OPTAB_LIB);
979 div = force_reg (DImode, div);
980 emit_insn (gen_muldi3 (mul, operands[2], div));
981 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
982 DONE;
983 })
985 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
986 ;; expanded by the assembler.
988 (define_insn_and_split "*divmodsi_internal_er"
989 [(set (match_operand:DI 0 "register_operand" "=c")
990 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
991 [(match_operand:DI 1 "register_operand" "a")
992 (match_operand:DI 2 "register_operand" "b")])))
993 (clobber (reg:DI 23))
994 (clobber (reg:DI 28))]
995 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
996 "#"
997 "&& reload_completed"
998 [(parallel [(set (match_dup 0)
999 (sign_extend:DI (match_dup 3)))
1000 (use (match_dup 0))
1001 (use (match_dup 4))
1002 (clobber (reg:DI 23))
1003 (clobber (reg:DI 28))])]
1004 {
1005 const char *str;
1006 switch (GET_CODE (operands[3]))
1007 {
1008 case DIV:
1009 str = "__divl";
1010 break;
1011 case UDIV:
1012 str = "__divlu";
1013 break;
1014 case MOD:
1015 str = "__reml";
1016 break;
1017 case UMOD:
1018 str = "__remlu";
1019 break;
1020 default:
1021 gcc_unreachable ();
1022 }
1023 operands[4] = GEN_INT (alpha_next_sequence_number++);
1024 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1025 gen_rtx_SYMBOL_REF (DImode, str),
1026 operands[4]));
1027 }
1028 [(set_attr "type" "jsr")
1029 (set_attr "length" "8")])
1031 (define_insn "*divmodsi_internal_er_1"
1032 [(set (match_operand:DI 0 "register_operand" "=c")
1033 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1034 [(match_operand:DI 1 "register_operand" "a")
1035 (match_operand:DI 2 "register_operand" "b")])))
1036 (use (match_operand:DI 4 "register_operand" "c"))
1037 (use (match_operand 5 "const_int_operand" ""))
1038 (clobber (reg:DI 23))
1039 (clobber (reg:DI 28))]
1040 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1041 "jsr $23,($27),__%E3%j5"
1042 [(set_attr "type" "jsr")
1043 (set_attr "length" "4")])
1045 (define_insn "*divmodsi_internal"
1046 [(set (match_operand:DI 0 "register_operand" "=c")
1047 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1048 [(match_operand:DI 1 "register_operand" "a")
1049 (match_operand:DI 2 "register_operand" "b")])))
1050 (clobber (reg:DI 23))
1051 (clobber (reg:DI 28))]
1052 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1053 "%E3 %1,%2,%0"
1054 [(set_attr "type" "jsr")
1055 (set_attr "length" "8")])
1057 (define_insn_and_split "*divmoddi_internal_er"
1058 [(set (match_operand:DI 0 "register_operand" "=c")
1059 (match_operator:DI 3 "divmod_operator"
1060 [(match_operand:DI 1 "register_operand" "a")
1061 (match_operand:DI 2 "register_operand" "b")]))
1062 (clobber (reg:DI 23))
1063 (clobber (reg:DI 28))]
1064 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1065 "#"
1066 "&& reload_completed"
1067 [(parallel [(set (match_dup 0) (match_dup 3))
1068 (use (match_dup 0))
1069 (use (match_dup 4))
1070 (clobber (reg:DI 23))
1071 (clobber (reg:DI 28))])]
1072 {
1073 const char *str;
1074 switch (GET_CODE (operands[3]))
1075 {
1076 case DIV:
1077 str = "__divq";
1078 break;
1079 case UDIV:
1080 str = "__divqu";
1081 break;
1082 case MOD:
1083 str = "__remq";
1084 break;
1085 case UMOD:
1086 str = "__remqu";
1087 break;
1088 default:
1089 gcc_unreachable ();
1090 }
1091 operands[4] = GEN_INT (alpha_next_sequence_number++);
1092 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1093 gen_rtx_SYMBOL_REF (DImode, str),
1094 operands[4]));
1095 }
1096 [(set_attr "type" "jsr")
1097 (set_attr "length" "8")])
1099 (define_insn "*divmoddi_internal_er_1"
1100 [(set (match_operand:DI 0 "register_operand" "=c")
1101 (match_operator:DI 3 "divmod_operator"
1102 [(match_operand:DI 1 "register_operand" "a")
1103 (match_operand:DI 2 "register_operand" "b")]))
1104 (use (match_operand:DI 4 "register_operand" "c"))
1105 (use (match_operand 5 "const_int_operand" ""))
1106 (clobber (reg:DI 23))
1107 (clobber (reg:DI 28))]
1108 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1109 "jsr $23,($27),__%E3%j5"
1110 [(set_attr "type" "jsr")
1111 (set_attr "length" "4")])
1113 (define_insn "*divmoddi_internal"
1114 [(set (match_operand:DI 0 "register_operand" "=c")
1115 (match_operator:DI 3 "divmod_operator"
1116 [(match_operand:DI 1 "register_operand" "a")
1117 (match_operand:DI 2 "register_operand" "b")]))
1118 (clobber (reg:DI 23))
1119 (clobber (reg:DI 28))]
1120 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1121 "%E3 %1,%2,%0"
1122 [(set_attr "type" "jsr")
1123 (set_attr "length" "8")])
1124 \f
1125 ;; Next are the basic logical operations. We only expose the DImode operations
1126 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1127 ;; the atomic operation splitters.
1129 (define_insn "*andsi_internal"
1130 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1131 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1132 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1133 ""
1134 "@
1135 and %r1,%2,%0
1136 bic %r1,%N2,%0
1137 zapnot %r1,%m2,%0"
1138 [(set_attr "type" "ilog,ilog,shift")])
1140 (define_insn "anddi3"
1141 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1142 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1143 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1144 ""
1145 "@
1146 and %r1,%2,%0
1147 bic %r1,%N2,%0
1148 zapnot %r1,%m2,%0"
1149 [(set_attr "type" "ilog,ilog,shift")])
1151 ;; There are times when we can split an AND into two AND insns. This occurs
1152 ;; when we can first clear any bytes and then clear anything else. For
1153 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1154 ;; Only do this when running on 64-bit host since the computations are
1155 ;; too messy otherwise.
1157 (define_split
1158 [(set (match_operand:DI 0 "register_operand" "")
1159 (and:DI (match_operand:DI 1 "register_operand" "")
1160 (match_operand:DI 2 "const_int_operand" "")))]
1161 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1162 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1163 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1164 {
1165 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1166 unsigned HOST_WIDE_INT mask2 = mask1;
1167 int i;
1169 /* For each byte that isn't all zeros, make it all ones. */
1170 for (i = 0; i < 64; i += 8)
1171 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1172 mask1 |= (HOST_WIDE_INT) 0xff << i;
1174 /* Now turn on any bits we've just turned off. */
1175 mask2 |= ~ mask1;
1177 operands[3] = GEN_INT (mask1);
1178 operands[4] = GEN_INT (mask2);
1179 })
1181 (define_expand "zero_extendqihi2"
1182 [(set (match_operand:HI 0 "register_operand" "")
1183 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1184 ""
1185 {
1186 if (! TARGET_BWX)
1187 operands[1] = force_reg (QImode, operands[1]);
1188 })
1190 (define_insn "*zero_extendqihi2_bwx"
1191 [(set (match_operand:HI 0 "register_operand" "=r,r")
1192 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1193 "TARGET_BWX"
1194 "@
1195 and %1,0xff,%0
1196 ldbu %0,%1"
1197 [(set_attr "type" "ilog,ild")])
1199 (define_insn "*zero_extendqihi2_nobwx"
1200 [(set (match_operand:HI 0 "register_operand" "=r")
1201 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1202 "! TARGET_BWX"
1203 "and %1,0xff,%0"
1204 [(set_attr "type" "ilog")])
1206 (define_expand "zero_extendqisi2"
1207 [(set (match_operand:SI 0 "register_operand" "")
1208 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1209 ""
1210 {
1211 if (! TARGET_BWX)
1212 operands[1] = force_reg (QImode, operands[1]);
1213 })
1215 (define_insn "*zero_extendqisi2_bwx"
1216 [(set (match_operand:SI 0 "register_operand" "=r,r")
1217 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1218 "TARGET_BWX"
1219 "@
1220 and %1,0xff,%0
1221 ldbu %0,%1"
1222 [(set_attr "type" "ilog,ild")])
1224 (define_insn "*zero_extendqisi2_nobwx"
1225 [(set (match_operand:SI 0 "register_operand" "=r")
1226 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1227 "! TARGET_BWX"
1228 "and %1,0xff,%0"
1229 [(set_attr "type" "ilog")])
1231 (define_expand "zero_extendqidi2"
1232 [(set (match_operand:DI 0 "register_operand" "")
1233 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1234 ""
1235 {
1236 if (! TARGET_BWX)
1237 operands[1] = force_reg (QImode, operands[1]);
1238 })
1240 (define_insn "*zero_extendqidi2_bwx"
1241 [(set (match_operand:DI 0 "register_operand" "=r,r")
1242 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1243 "TARGET_BWX"
1244 "@
1245 and %1,0xff,%0
1246 ldbu %0,%1"
1247 [(set_attr "type" "ilog,ild")])
1249 (define_insn "*zero_extendqidi2_nobwx"
1250 [(set (match_operand:DI 0 "register_operand" "=r")
1251 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1252 "! TARGET_BWX"
1253 "and %1,0xff,%0"
1254 [(set_attr "type" "ilog")])
1256 (define_expand "zero_extendhisi2"
1257 [(set (match_operand:SI 0 "register_operand" "")
1258 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1259 ""
1260 {
1261 if (! TARGET_BWX)
1262 operands[1] = force_reg (HImode, operands[1]);
1263 })
1265 (define_insn "*zero_extendhisi2_bwx"
1266 [(set (match_operand:SI 0 "register_operand" "=r,r")
1267 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1268 "TARGET_BWX"
1269 "@
1270 zapnot %1,3,%0
1271 ldwu %0,%1"
1272 [(set_attr "type" "shift,ild")])
1274 (define_insn "*zero_extendhisi2_nobwx"
1275 [(set (match_operand:SI 0 "register_operand" "=r")
1276 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1277 "! TARGET_BWX"
1278 "zapnot %1,3,%0"
1279 [(set_attr "type" "shift")])
1281 (define_expand "zero_extendhidi2"
1282 [(set (match_operand:DI 0 "register_operand" "")
1283 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1284 ""
1285 {
1286 if (! TARGET_BWX)
1287 operands[1] = force_reg (HImode, operands[1]);
1288 })
1290 (define_insn "*zero_extendhidi2_bwx"
1291 [(set (match_operand:DI 0 "register_operand" "=r,r")
1292 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1293 "TARGET_BWX"
1294 "@
1295 zapnot %1,3,%0
1296 ldwu %0,%1"
1297 [(set_attr "type" "shift,ild")])
1299 (define_insn "*zero_extendhidi2_nobwx"
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1301 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1302 ""
1303 "zapnot %1,3,%0"
1304 [(set_attr "type" "shift")])
1306 (define_insn "zero_extendsidi2"
1307 [(set (match_operand:DI 0 "register_operand" "=r")
1308 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1309 ""
1310 "zapnot %1,15,%0"
1311 [(set_attr "type" "shift")])
1313 (define_insn "*andnotsi3"
1314 [(set (match_operand:SI 0 "register_operand" "=r")
1315 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1316 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1317 ""
1318 "bic %r2,%1,%0"
1319 [(set_attr "type" "ilog")])
1321 (define_insn "andnotdi3"
1322 [(set (match_operand:DI 0 "register_operand" "=r")
1323 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1324 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1325 ""
1326 "bic %r2,%1,%0"
1327 [(set_attr "type" "ilog")])
1329 (define_insn "*iorsi_internal"
1330 [(set (match_operand:SI 0 "register_operand" "=r,r")
1331 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1332 (match_operand:SI 2 "or_operand" "rI,N")))]
1333 ""
1334 "@
1335 bis %r1,%2,%0
1336 ornot %r1,%N2,%0"
1337 [(set_attr "type" "ilog")])
1339 (define_insn "iordi3"
1340 [(set (match_operand:DI 0 "register_operand" "=r,r")
1341 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1342 (match_operand:DI 2 "or_operand" "rI,N")))]
1343 ""
1344 "@
1345 bis %r1,%2,%0
1346 ornot %r1,%N2,%0"
1347 [(set_attr "type" "ilog")])
1349 (define_insn "*one_cmplsi_internal"
1350 [(set (match_operand:SI 0 "register_operand" "=r")
1351 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1352 ""
1353 "ornot $31,%1,%0"
1354 [(set_attr "type" "ilog")])
1356 (define_insn "one_cmpldi2"
1357 [(set (match_operand:DI 0 "register_operand" "=r")
1358 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1359 ""
1360 "ornot $31,%1,%0"
1361 [(set_attr "type" "ilog")])
1363 (define_insn "*iornotsi3"
1364 [(set (match_operand:SI 0 "register_operand" "=r")
1365 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1366 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1367 ""
1368 "ornot %r2,%1,%0"
1369 [(set_attr "type" "ilog")])
1371 (define_insn "*iornotdi3"
1372 [(set (match_operand:DI 0 "register_operand" "=r")
1373 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1374 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1375 ""
1376 "ornot %r2,%1,%0"
1377 [(set_attr "type" "ilog")])
1379 (define_insn "*xorsi_internal"
1380 [(set (match_operand:SI 0 "register_operand" "=r,r")
1381 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1382 (match_operand:SI 2 "or_operand" "rI,N")))]
1383 ""
1384 "@
1385 xor %r1,%2,%0
1386 eqv %r1,%N2,%0"
1387 [(set_attr "type" "ilog")])
1389 (define_insn "xordi3"
1390 [(set (match_operand:DI 0 "register_operand" "=r,r")
1391 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1392 (match_operand:DI 2 "or_operand" "rI,N")))]
1393 ""
1394 "@
1395 xor %r1,%2,%0
1396 eqv %r1,%N2,%0"
1397 [(set_attr "type" "ilog")])
1399 (define_insn "*xornotsi3"
1400 [(set (match_operand:SI 0 "register_operand" "=r")
1401 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1402 (match_operand:SI 2 "register_operand" "rI"))))]
1403 ""
1404 "eqv %r1,%2,%0"
1405 [(set_attr "type" "ilog")])
1407 (define_insn "*xornotdi3"
1408 [(set (match_operand:DI 0 "register_operand" "=r")
1409 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1410 (match_operand:DI 2 "register_operand" "rI"))))]
1411 ""
1412 "eqv %r1,%2,%0"
1413 [(set_attr "type" "ilog")])
1414 \f
1415 ;; Handle FFS and related insns iff we support CIX.
1417 (define_expand "ffsdi2"
1418 [(set (match_dup 2)
1419 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1420 (set (match_dup 3)
1421 (plus:DI (match_dup 2) (const_int 1)))
1422 (set (match_operand:DI 0 "register_operand" "")
1423 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1424 (const_int 0) (match_dup 3)))]
1425 "TARGET_CIX"
1426 {
1427 operands[2] = gen_reg_rtx (DImode);
1428 operands[3] = gen_reg_rtx (DImode);
1429 })
1431 (define_insn "clzdi2"
1432 [(set (match_operand:DI 0 "register_operand" "=r")
1433 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1434 "TARGET_CIX"
1435 "ctlz %1,%0"
1436 [(set_attr "type" "mvi")])
1438 (define_insn "ctzdi2"
1439 [(set (match_operand:DI 0 "register_operand" "=r")
1440 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1441 "TARGET_CIX"
1442 "cttz %1,%0"
1443 [(set_attr "type" "mvi")])
1445 (define_insn "popcountdi2"
1446 [(set (match_operand:DI 0 "register_operand" "=r")
1447 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1448 "TARGET_CIX"
1449 "ctpop %1,%0"
1450 [(set_attr "type" "mvi")])
1452 (define_expand "bswapsi2"
1453 [(set (match_operand:SI 0 "register_operand" "")
1454 (bswap:SI (match_operand:SI 1 "register_operand" "")))]
1455 "!optimize_size"
1456 {
1457 rtx t0, t1;
1459 t0 = gen_reg_rtx (DImode);
1460 t1 = gen_reg_rtx (DImode);
1462 emit_insn (gen_insxh (t0, gen_lowpart (DImode, operands[1]),
1463 GEN_INT (32), GEN_INT (WORDS_BIG_ENDIAN ? 0 : 7)));
1464 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
1465 GEN_INT (24)));
1466 emit_insn (gen_iordi3 (t1, t0, t1));
1467 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1468 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
1469 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
1470 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
1471 gen_lowpart (SImode, t1)));
1472 DONE;
1473 })
1475 (define_expand "bswapdi2"
1476 [(set (match_operand:DI 0 "register_operand" "")
1477 (bswap:DI (match_operand:DI 1 "register_operand" "")))]
1478 "!optimize_size"
1479 {
1480 rtx t0, t1;
1482 t0 = gen_reg_rtx (DImode);
1483 t1 = gen_reg_rtx (DImode);
1485 /* This method of shifting and masking is not specific to Alpha, but
1486 is only profitable on Alpha because of our handy byte zap insn. */
1488 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
1489 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
1490 emit_insn (gen_iordi3 (t1, t0, t1));
1492 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1493 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
1494 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
1495 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
1496 emit_insn (gen_iordi3 (t1, t0, t1));
1498 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
1499 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
1500 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
1501 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
1502 emit_insn (gen_iordi3 (operands[0], t0, t1));
1503 DONE;
1504 })
1505 \f
1506 ;; Next come the shifts and the various extract and insert operations.
1508 (define_insn "ashldi3"
1509 [(set (match_operand:DI 0 "register_operand" "=r,r")
1510 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1511 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1512 ""
1513 {
1514 switch (which_alternative)
1515 {
1516 case 0:
1517 if (operands[2] == const1_rtx)
1518 return "addq %r1,%r1,%0";
1519 else
1520 return "s%P2addq %r1,0,%0";
1521 case 1:
1522 return "sll %r1,%2,%0";
1523 default:
1524 gcc_unreachable ();
1525 }
1526 }
1527 [(set_attr "type" "iadd,shift")])
1529 (define_insn "*ashldi_se"
1530 [(set (match_operand:DI 0 "register_operand" "=r")
1531 (sign_extend:DI
1532 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1533 (match_operand:DI 2 "const_int_operand" "P"))
1534 0)))]
1535 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1536 {
1537 if (operands[2] == const1_rtx)
1538 return "addl %r1,%r1,%0";
1539 else
1540 return "s%P2addl %r1,0,%0";
1541 }
1542 [(set_attr "type" "iadd")])
1544 (define_insn "lshrdi3"
1545 [(set (match_operand:DI 0 "register_operand" "=r")
1546 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1547 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1548 ""
1549 "srl %r1,%2,%0"
1550 [(set_attr "type" "shift")])
1552 (define_insn "ashrdi3"
1553 [(set (match_operand:DI 0 "register_operand" "=r")
1554 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1555 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1556 ""
1557 "sra %r1,%2,%0"
1558 [(set_attr "type" "shift")])
1560 (define_expand "extendqihi2"
1561 [(set (match_dup 2)
1562 (ashift:DI (match_operand:QI 1 "some_operand" "")
1563 (const_int 56)))
1564 (set (match_operand:HI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1566 (const_int 56)))]
1567 ""
1568 {
1569 if (TARGET_BWX)
1570 {
1571 emit_insn (gen_extendqihi2x (operands[0],
1572 force_reg (QImode, operands[1])));
1573 DONE;
1574 }
1576 /* If we have an unaligned MEM, extend to DImode (which we do
1577 specially) and then copy to the result. */
1578 if (unaligned_memory_operand (operands[1], HImode))
1579 {
1580 rtx temp = gen_reg_rtx (DImode);
1582 emit_insn (gen_extendqidi2 (temp, operands[1]));
1583 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1584 DONE;
1585 }
1587 operands[0] = gen_lowpart (DImode, operands[0]);
1588 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1589 operands[2] = gen_reg_rtx (DImode);
1590 })
1592 (define_insn "extendqidi2x"
1593 [(set (match_operand:DI 0 "register_operand" "=r")
1594 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1595 "TARGET_BWX"
1596 "sextb %1,%0"
1597 [(set_attr "type" "shift")])
1599 (define_insn "extendhidi2x"
1600 [(set (match_operand:DI 0 "register_operand" "=r")
1601 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1602 "TARGET_BWX"
1603 "sextw %1,%0"
1604 [(set_attr "type" "shift")])
1606 (define_insn "extendqisi2x"
1607 [(set (match_operand:SI 0 "register_operand" "=r")
1608 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1609 "TARGET_BWX"
1610 "sextb %1,%0"
1611 [(set_attr "type" "shift")])
1613 (define_insn "extendhisi2x"
1614 [(set (match_operand:SI 0 "register_operand" "=r")
1615 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1616 "TARGET_BWX"
1617 "sextw %1,%0"
1618 [(set_attr "type" "shift")])
1620 (define_insn "extendqihi2x"
1621 [(set (match_operand:HI 0 "register_operand" "=r")
1622 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1623 "TARGET_BWX"
1624 "sextb %1,%0"
1625 [(set_attr "type" "shift")])
1627 (define_expand "extendqisi2"
1628 [(set (match_dup 2)
1629 (ashift:DI (match_operand:QI 1 "some_operand" "")
1630 (const_int 56)))
1631 (set (match_operand:SI 0 "register_operand" "")
1632 (ashiftrt:DI (match_dup 2)
1633 (const_int 56)))]
1634 ""
1635 {
1636 if (TARGET_BWX)
1637 {
1638 emit_insn (gen_extendqisi2x (operands[0],
1639 force_reg (QImode, operands[1])));
1640 DONE;
1641 }
1643 /* If we have an unaligned MEM, extend to a DImode form of
1644 the result (which we do specially). */
1645 if (unaligned_memory_operand (operands[1], QImode))
1646 {
1647 rtx temp = gen_reg_rtx (DImode);
1649 emit_insn (gen_extendqidi2 (temp, operands[1]));
1650 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1651 DONE;
1652 }
1654 operands[0] = gen_lowpart (DImode, operands[0]);
1655 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1656 operands[2] = gen_reg_rtx (DImode);
1657 })
1659 (define_expand "extendqidi2"
1660 [(set (match_dup 2)
1661 (ashift:DI (match_operand:QI 1 "some_operand" "")
1662 (const_int 56)))
1663 (set (match_operand:DI 0 "register_operand" "")
1664 (ashiftrt:DI (match_dup 2)
1665 (const_int 56)))]
1666 ""
1667 {
1668 if (TARGET_BWX)
1669 {
1670 emit_insn (gen_extendqidi2x (operands[0],
1671 force_reg (QImode, operands[1])));
1672 DONE;
1673 }
1675 if (unaligned_memory_operand (operands[1], QImode))
1676 {
1677 rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
1678 alpha_set_memflags (seq, operands[1]);
1679 emit_insn (seq);
1680 DONE;
1681 }
1683 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1684 operands[2] = gen_reg_rtx (DImode);
1685 })
1687 (define_expand "extendhisi2"
1688 [(set (match_dup 2)
1689 (ashift:DI (match_operand:HI 1 "some_operand" "")
1690 (const_int 48)))
1691 (set (match_operand:SI 0 "register_operand" "")
1692 (ashiftrt:DI (match_dup 2)
1693 (const_int 48)))]
1694 ""
1695 {
1696 if (TARGET_BWX)
1697 {
1698 emit_insn (gen_extendhisi2x (operands[0],
1699 force_reg (HImode, operands[1])));
1700 DONE;
1701 }
1703 /* If we have an unaligned MEM, extend to a DImode form of
1704 the result (which we do specially). */
1705 if (unaligned_memory_operand (operands[1], HImode))
1706 {
1707 rtx temp = gen_reg_rtx (DImode);
1709 emit_insn (gen_extendhidi2 (temp, operands[1]));
1710 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1711 DONE;
1712 }
1714 operands[0] = gen_lowpart (DImode, operands[0]);
1715 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1716 operands[2] = gen_reg_rtx (DImode);
1717 })
1719 (define_expand "extendhidi2"
1720 [(set (match_dup 2)
1721 (ashift:DI (match_operand:HI 1 "some_operand" "")
1722 (const_int 48)))
1723 (set (match_operand:DI 0 "register_operand" "")
1724 (ashiftrt:DI (match_dup 2)
1725 (const_int 48)))]
1726 ""
1727 {
1728 if (TARGET_BWX)
1729 {
1730 emit_insn (gen_extendhidi2x (operands[0],
1731 force_reg (HImode, operands[1])));
1732 DONE;
1733 }
1735 if (unaligned_memory_operand (operands[1], HImode))
1736 {
1737 rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
1739 alpha_set_memflags (seq, operands[1]);
1740 emit_insn (seq);
1741 DONE;
1742 }
1744 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1745 operands[2] = gen_reg_rtx (DImode);
1746 })
1748 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1749 ;; as a pattern saves one instruction. The code is similar to that for
1750 ;; the unaligned loads (see below).
1751 ;;
1752 ;; Operand 1 is the address, operand 0 is the result.
1753 (define_expand "unaligned_extendqidi"
1754 [(use (match_operand:QI 0 "register_operand" ""))
1755 (use (match_operand:DI 1 "address_operand" ""))]
1756 ""
1757 {
1758 operands[0] = gen_lowpart (DImode, operands[0]);
1759 if (WORDS_BIG_ENDIAN)
1760 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1761 else
1762 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1763 DONE;
1764 })
1766 (define_expand "unaligned_extendqidi_le"
1767 [(set (match_dup 3)
1768 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1769 (set (match_dup 4)
1770 (ashift:DI (match_dup 3)
1771 (minus:DI (const_int 64)
1772 (ashift:DI
1773 (and:DI (match_dup 2) (const_int 7))
1774 (const_int 3)))))
1775 (set (match_operand:DI 0 "register_operand" "")
1776 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1777 "! WORDS_BIG_ENDIAN"
1778 {
1779 operands[2] = get_unaligned_offset (operands[1], 1);
1780 operands[3] = gen_reg_rtx (DImode);
1781 operands[4] = gen_reg_rtx (DImode);
1782 })
1784 (define_expand "unaligned_extendqidi_be"
1785 [(set (match_dup 3)
1786 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1787 (set (match_dup 4)
1788 (ashift:DI (match_dup 3)
1789 (ashift:DI
1790 (and:DI
1791 (plus:DI (match_dup 2) (const_int 1))
1792 (const_int 7))
1793 (const_int 3))))
1794 (set (match_operand:DI 0 "register_operand" "")
1795 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1796 "WORDS_BIG_ENDIAN"
1797 {
1798 operands[2] = get_unaligned_offset (operands[1], -1);
1799 operands[3] = gen_reg_rtx (DImode);
1800 operands[4] = gen_reg_rtx (DImode);
1801 })
1803 (define_expand "unaligned_extendhidi"
1804 [(use (match_operand:QI 0 "register_operand" ""))
1805 (use (match_operand:DI 1 "address_operand" ""))]
1806 ""
1807 {
1808 operands[0] = gen_lowpart (DImode, operands[0]);
1809 if (WORDS_BIG_ENDIAN)
1810 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1811 else
1812 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1813 DONE;
1814 })
1816 (define_expand "unaligned_extendhidi_le"
1817 [(set (match_dup 3)
1818 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1819 (set (match_dup 4)
1820 (ashift:DI (match_dup 3)
1821 (minus:DI (const_int 64)
1822 (ashift:DI
1823 (and:DI (match_dup 2) (const_int 7))
1824 (const_int 3)))))
1825 (set (match_operand:DI 0 "register_operand" "")
1826 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1827 "! WORDS_BIG_ENDIAN"
1828 {
1829 operands[2] = get_unaligned_offset (operands[1], 2);
1830 operands[3] = gen_reg_rtx (DImode);
1831 operands[4] = gen_reg_rtx (DImode);
1832 })
1834 (define_expand "unaligned_extendhidi_be"
1835 [(set (match_dup 3)
1836 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1837 (set (match_dup 4)
1838 (ashift:DI (match_dup 3)
1839 (ashift:DI
1840 (and:DI
1841 (plus:DI (match_dup 2) (const_int 1))
1842 (const_int 7))
1843 (const_int 3))))
1844 (set (match_operand:DI 0 "register_operand" "")
1845 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1846 "WORDS_BIG_ENDIAN"
1847 {
1848 operands[2] = get_unaligned_offset (operands[1], -1);
1849 operands[3] = gen_reg_rtx (DImode);
1850 operands[4] = gen_reg_rtx (DImode);
1851 })
1853 (define_insn "*extxl_const"
1854 [(set (match_operand:DI 0 "register_operand" "=r")
1855 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1856 (match_operand:DI 2 "mode_width_operand" "n")
1857 (match_operand:DI 3 "mul8_operand" "I")))]
1858 ""
1859 "ext%M2l %r1,%s3,%0"
1860 [(set_attr "type" "shift")])
1862 (define_insn "extxl_le"
1863 [(set (match_operand:DI 0 "register_operand" "=r")
1864 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1865 (match_operand:DI 2 "mode_width_operand" "n")
1866 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1867 (const_int 3))))]
1868 "! WORDS_BIG_ENDIAN"
1869 "ext%M2l %r1,%3,%0"
1870 [(set_attr "type" "shift")])
1872 (define_insn "extxl_be"
1873 [(set (match_operand:DI 0 "register_operand" "=r")
1874 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1875 (match_operand:DI 2 "mode_width_operand" "n")
1876 (minus:DI
1877 (const_int 56)
1878 (ashift:DI
1879 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1880 (const_int 3)))))]
1881 "WORDS_BIG_ENDIAN"
1882 "ext%M2l %r1,%3,%0"
1883 [(set_attr "type" "shift")])
1885 ;; Combine has some strange notion of preserving existing undefined behavior
1886 ;; in shifts larger than a word size. So capture these patterns that it
1887 ;; should have turned into zero_extracts.
1889 (define_insn "*extxl_1_le"
1890 [(set (match_operand:DI 0 "register_operand" "=r")
1891 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1892 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1893 (const_int 3)))
1894 (match_operand:DI 3 "mode_mask_operand" "n")))]
1895 "! WORDS_BIG_ENDIAN"
1896 "ext%U3l %1,%2,%0"
1897 [(set_attr "type" "shift")])
1899 (define_insn "*extxl_1_be"
1900 [(set (match_operand:DI 0 "register_operand" "=r")
1901 (and:DI (lshiftrt:DI
1902 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1903 (minus:DI (const_int 56)
1904 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1905 (const_int 3))))
1906 (match_operand:DI 3 "mode_mask_operand" "n")))]
1907 "WORDS_BIG_ENDIAN"
1908 "ext%U3l %1,%2,%0"
1909 [(set_attr "type" "shift")])
1911 (define_insn "*extql_2_le"
1912 [(set (match_operand:DI 0 "register_operand" "=r")
1913 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1914 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1915 (const_int 3))))]
1916 "! WORDS_BIG_ENDIAN"
1917 "extql %1,%2,%0"
1918 [(set_attr "type" "shift")])
1920 (define_insn "*extql_2_be"
1921 [(set (match_operand:DI 0 "register_operand" "=r")
1922 (lshiftrt:DI
1923 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1924 (minus:DI (const_int 56)
1925 (ashift:DI
1926 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1927 (const_int 3)))))]
1928 "WORDS_BIG_ENDIAN"
1929 "extql %1,%2,%0"
1930 [(set_attr "type" "shift")])
1932 (define_insn "extqh_le"
1933 [(set (match_operand:DI 0 "register_operand" "=r")
1934 (ashift:DI
1935 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1936 (minus:DI (const_int 64)
1937 (ashift:DI
1938 (and:DI
1939 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1940 (const_int 7))
1941 (const_int 3)))))]
1942 "! WORDS_BIG_ENDIAN"
1943 "extqh %r1,%2,%0"
1944 [(set_attr "type" "shift")])
1946 (define_insn "extqh_be"
1947 [(set (match_operand:DI 0 "register_operand" "=r")
1948 (ashift:DI
1949 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1950 (ashift:DI
1951 (and:DI
1952 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1953 (const_int 1))
1954 (const_int 7))
1955 (const_int 3))))]
1956 "WORDS_BIG_ENDIAN"
1957 "extqh %r1,%2,%0"
1958 [(set_attr "type" "shift")])
1960 (define_insn "extlh_le"
1961 [(set (match_operand:DI 0 "register_operand" "=r")
1962 (ashift:DI
1963 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1964 (const_int 2147483647))
1965 (minus:DI (const_int 64)
1966 (ashift:DI
1967 (and:DI
1968 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1969 (const_int 7))
1970 (const_int 3)))))]
1971 "! WORDS_BIG_ENDIAN"
1972 "extlh %r1,%2,%0"
1973 [(set_attr "type" "shift")])
1975 (define_insn "extlh_be"
1976 [(set (match_operand:DI 0 "register_operand" "=r")
1977 (and:DI
1978 (ashift:DI
1979 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1980 (ashift:DI
1981 (and:DI
1982 (plus:DI
1983 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1984 (const_int 1))
1985 (const_int 7))
1986 (const_int 3)))
1987 (const_int 2147483647)))]
1988 "WORDS_BIG_ENDIAN"
1989 "extlh %r1,%2,%0"
1990 [(set_attr "type" "shift")])
1992 (define_insn "extwh_le"
1993 [(set (match_operand:DI 0 "register_operand" "=r")
1994 (ashift:DI
1995 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1996 (const_int 65535))
1997 (minus:DI (const_int 64)
1998 (ashift:DI
1999 (and:DI
2000 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2001 (const_int 7))
2002 (const_int 3)))))]
2003 "! WORDS_BIG_ENDIAN"
2004 "extwh %r1,%2,%0"
2005 [(set_attr "type" "shift")])
2007 (define_insn "extwh_be"
2008 [(set (match_operand:DI 0 "register_operand" "=r")
2009 (and:DI
2010 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2011 (ashift:DI
2012 (and:DI
2013 (plus:DI
2014 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2015 (const_int 1))
2016 (const_int 7))
2017 (const_int 3)))
2018 (const_int 65535)))]
2019 "WORDS_BIG_ENDIAN"
2020 "extwh %r1,%2,%0"
2021 [(set_attr "type" "shift")])
2023 ;; This converts an extXl into an extXh with an appropriate adjustment
2024 ;; to the address calculation.
2026 ;;(define_split
2027 ;; [(set (match_operand:DI 0 "register_operand" "")
2028 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2029 ;; (match_operand:DI 2 "mode_width_operand" "")
2030 ;; (ashift:DI (match_operand:DI 3 "" "")
2031 ;; (const_int 3)))
2032 ;; (match_operand:DI 4 "const_int_operand" "")))
2033 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2034 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2035 ;; [(set (match_dup 5) (match_dup 6))
2036 ;; (set (match_dup 0)
2037 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2038 ;; (ashift:DI (plus:DI (match_dup 5)
2039 ;; (match_dup 7))
2040 ;; (const_int 3)))
2041 ;; (match_dup 4)))]
2042 ;; "
2043 ;;{
2044 ;; operands[6] = plus_constant (operands[3],
2045 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2046 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2047 ;;}")
2049 (define_insn "*insbl_const"
2050 [(set (match_operand:DI 0 "register_operand" "=r")
2051 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2052 (match_operand:DI 2 "mul8_operand" "I")))]
2053 ""
2054 "insbl %1,%s2,%0"
2055 [(set_attr "type" "shift")])
2057 (define_insn "inswl_const"
2058 [(set (match_operand:DI 0 "register_operand" "=r")
2059 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2060 (match_operand:DI 2 "mul8_operand" "I")))]
2061 ""
2062 "inswl %1,%s2,%0"
2063 [(set_attr "type" "shift")])
2065 (define_insn "*insll_const"
2066 [(set (match_operand:DI 0 "register_operand" "=r")
2067 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2068 (match_operand:DI 2 "mul8_operand" "I")))]
2069 ""
2070 "insll %1,%s2,%0"
2071 [(set_attr "type" "shift")])
2073 (define_insn "insbl_le"
2074 [(set (match_operand:DI 0 "register_operand" "=r")
2075 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2076 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 (const_int 3))))]
2078 "! WORDS_BIG_ENDIAN"
2079 "insbl %1,%2,%0"
2080 [(set_attr "type" "shift")])
2082 (define_insn "insbl_be"
2083 [(set (match_operand:DI 0 "register_operand" "=r")
2084 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2085 (minus:DI (const_int 56)
2086 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2087 (const_int 3)))))]
2088 "WORDS_BIG_ENDIAN"
2089 "insbl %1,%2,%0"
2090 [(set_attr "type" "shift")])
2092 (define_insn "inswl_le"
2093 [(set (match_operand:DI 0 "register_operand" "=r")
2094 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2095 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2096 (const_int 3))))]
2097 "! WORDS_BIG_ENDIAN"
2098 "inswl %1,%2,%0"
2099 [(set_attr "type" "shift")])
2101 (define_insn "inswl_be"
2102 [(set (match_operand:DI 0 "register_operand" "=r")
2103 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2104 (minus:DI (const_int 56)
2105 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2106 (const_int 3)))))]
2107 "WORDS_BIG_ENDIAN"
2108 "inswl %1,%2,%0"
2109 [(set_attr "type" "shift")])
2111 (define_insn "insll_le"
2112 [(set (match_operand:DI 0 "register_operand" "=r")
2113 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2114 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2115 (const_int 3))))]
2116 "! WORDS_BIG_ENDIAN"
2117 "insll %1,%2,%0"
2118 [(set_attr "type" "shift")])
2120 (define_insn "insll_be"
2121 [(set (match_operand:DI 0 "register_operand" "=r")
2122 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2123 (minus:DI (const_int 56)
2124 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2125 (const_int 3)))))]
2126 "WORDS_BIG_ENDIAN"
2127 "insll %1,%2,%0"
2128 [(set_attr "type" "shift")])
2130 (define_insn "insql_le"
2131 [(set (match_operand:DI 0 "register_operand" "=r")
2132 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2133 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2134 (const_int 3))))]
2135 "! WORDS_BIG_ENDIAN"
2136 "insql %1,%2,%0"
2137 [(set_attr "type" "shift")])
2139 (define_insn "insql_be"
2140 [(set (match_operand:DI 0 "register_operand" "=r")
2141 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2142 (minus:DI (const_int 56)
2143 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2144 (const_int 3)))))]
2145 "WORDS_BIG_ENDIAN"
2146 "insql %1,%2,%0"
2147 [(set_attr "type" "shift")])
2149 ;; Combine has this sometimes habit of moving the and outside of the
2150 ;; shift, making life more interesting.
2152 (define_insn "*insxl"
2153 [(set (match_operand:DI 0 "register_operand" "=r")
2154 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2155 (match_operand:DI 2 "mul8_operand" "I"))
2156 (match_operand:DI 3 "immediate_operand" "i")))]
2157 "HOST_BITS_PER_WIDE_INT == 64
2158 && CONST_INT_P (operands[3])
2159 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2160 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2161 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2162 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2163 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2164 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2165 {
2166 #if HOST_BITS_PER_WIDE_INT == 64
2167 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2168 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2169 return "insbl %1,%s2,%0";
2170 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2171 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2172 return "inswl %1,%s2,%0";
2173 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2174 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2175 return "insll %1,%s2,%0";
2176 #endif
2177 gcc_unreachable ();
2178 }
2179 [(set_attr "type" "shift")])
2181 ;; We do not include the insXh insns because they are complex to express
2182 ;; and it does not appear that we would ever want to generate them.
2183 ;;
2184 ;; Since we need them for block moves, though, cop out and use unspec.
2186 (define_insn "insxh"
2187 [(set (match_operand:DI 0 "register_operand" "=r")
2188 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2189 (match_operand:DI 2 "mode_width_operand" "n")
2190 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2191 UNSPEC_INSXH))]
2192 ""
2193 "ins%M2h %1,%3,%0"
2194 [(set_attr "type" "shift")])
2196 (define_insn "mskxl_le"
2197 [(set (match_operand:DI 0 "register_operand" "=r")
2198 (and:DI (not:DI (ashift:DI
2199 (match_operand:DI 2 "mode_mask_operand" "n")
2200 (ashift:DI
2201 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2202 (const_int 3))))
2203 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2204 "! WORDS_BIG_ENDIAN"
2205 "msk%U2l %r1,%3,%0"
2206 [(set_attr "type" "shift")])
2208 (define_insn "mskxl_be"
2209 [(set (match_operand:DI 0 "register_operand" "=r")
2210 (and:DI (not:DI (ashift:DI
2211 (match_operand:DI 2 "mode_mask_operand" "n")
2212 (minus:DI (const_int 56)
2213 (ashift:DI
2214 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2215 (const_int 3)))))
2216 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2217 "WORDS_BIG_ENDIAN"
2218 "msk%U2l %r1,%3,%0"
2219 [(set_attr "type" "shift")])
2221 ;; We do not include the mskXh insns because it does not appear we would
2222 ;; ever generate one.
2223 ;;
2224 ;; Again, we do for block moves and we use unspec again.
2226 (define_insn "mskxh"
2227 [(set (match_operand:DI 0 "register_operand" "=r")
2228 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2229 (match_operand:DI 2 "mode_width_operand" "n")
2230 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2231 UNSPEC_MSKXH))]
2232 ""
2233 "msk%M2h %1,%3,%0"
2234 [(set_attr "type" "shift")])
2236 ;; Prefer AND + NE over LSHIFTRT + AND.
2238 (define_insn_and_split "*ze_and_ne"
2239 [(set (match_operand:DI 0 "register_operand" "=r")
2240 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2241 (const_int 1)
2242 (match_operand 2 "const_int_operand" "I")))]
2243 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2244 "#"
2245 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2246 [(set (match_dup 0)
2247 (and:DI (match_dup 1) (match_dup 3)))
2248 (set (match_dup 0)
2249 (ne:DI (match_dup 0) (const_int 0)))]
2250 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2251 \f
2252 ;; Floating-point operations. All the double-precision insns can extend
2253 ;; from single, so indicate that. The exception are the ones that simply
2254 ;; play with the sign bits; it's not clear what to do there.
2256 (define_insn "abssf2"
2257 [(set (match_operand:SF 0 "register_operand" "=f")
2258 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2259 "TARGET_FP"
2260 "cpys $f31,%R1,%0"
2261 [(set_attr "type" "fcpys")])
2263 (define_insn "*nabssf2"
2264 [(set (match_operand:SF 0 "register_operand" "=f")
2265 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2266 "TARGET_FP"
2267 "cpysn $f31,%R1,%0"
2268 [(set_attr "type" "fadd")])
2270 (define_insn "absdf2"
2271 [(set (match_operand:DF 0 "register_operand" "=f")
2272 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2273 "TARGET_FP"
2274 "cpys $f31,%R1,%0"
2275 [(set_attr "type" "fcpys")])
2277 (define_insn "*nabsdf2"
2278 [(set (match_operand:DF 0 "register_operand" "=f")
2279 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2280 "TARGET_FP"
2281 "cpysn $f31,%R1,%0"
2282 [(set_attr "type" "fadd")])
2284 (define_expand "abstf2"
2285 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2286 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2287 (use (match_dup 2))])]
2288 "TARGET_HAS_XFLOATING_LIBS"
2289 {
2290 #if HOST_BITS_PER_WIDE_INT >= 64
2291 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2292 #else
2293 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2294 #endif
2295 })
2297 (define_insn_and_split "*abstf_internal"
2298 [(set (match_operand:TF 0 "register_operand" "=r")
2299 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2300 (use (match_operand:DI 2 "register_operand" "r"))]
2301 "TARGET_HAS_XFLOATING_LIBS"
2302 "#"
2303 "&& reload_completed"
2304 [(const_int 0)]
2305 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2307 (define_insn "negsf2"
2308 [(set (match_operand:SF 0 "register_operand" "=f")
2309 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2310 "TARGET_FP"
2311 "cpysn %R1,%R1,%0"
2312 [(set_attr "type" "fadd")])
2314 (define_insn "negdf2"
2315 [(set (match_operand:DF 0 "register_operand" "=f")
2316 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2317 "TARGET_FP"
2318 "cpysn %R1,%R1,%0"
2319 [(set_attr "type" "fadd")])
2321 (define_expand "negtf2"
2322 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2323 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2324 (use (match_dup 2))])]
2325 "TARGET_HAS_XFLOATING_LIBS"
2326 {
2327 #if HOST_BITS_PER_WIDE_INT >= 64
2328 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2329 #else
2330 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2331 #endif
2332 })
2334 (define_insn_and_split "*negtf_internal"
2335 [(set (match_operand:TF 0 "register_operand" "=r")
2336 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2337 (use (match_operand:DI 2 "register_operand" "r"))]
2338 "TARGET_HAS_XFLOATING_LIBS"
2339 "#"
2340 "&& reload_completed"
2341 [(const_int 0)]
2342 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2344 (define_insn "copysignsf3"
2345 [(set (match_operand:SF 0 "register_operand" "=f")
2346 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2347 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2348 UNSPEC_COPYSIGN))]
2349 "TARGET_FP"
2350 "cpys %R2,%R1,%0"
2351 [(set_attr "type" "fadd")])
2353 (define_insn "*ncopysignsf3"
2354 [(set (match_operand:SF 0 "register_operand" "=f")
2355 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2356 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2357 UNSPEC_COPYSIGN)))]
2358 "TARGET_FP"
2359 "cpysn %R2,%R1,%0"
2360 [(set_attr "type" "fadd")])
2362 (define_insn "copysigndf3"
2363 [(set (match_operand:DF 0 "register_operand" "=f")
2364 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2365 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2366 UNSPEC_COPYSIGN))]
2367 "TARGET_FP"
2368 "cpys %R2,%R1,%0"
2369 [(set_attr "type" "fadd")])
2371 (define_insn "*ncopysigndf3"
2372 [(set (match_operand:DF 0 "register_operand" "=f")
2373 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2374 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2375 UNSPEC_COPYSIGN)))]
2376 "TARGET_FP"
2377 "cpysn %R2,%R1,%0"
2378 [(set_attr "type" "fadd")])
2380 (define_insn "*addsf_ieee"
2381 [(set (match_operand:SF 0 "register_operand" "=&f")
2382 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2383 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2384 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2385 "add%,%/ %R1,%R2,%0"
2386 [(set_attr "type" "fadd")
2387 (set_attr "trap" "yes")
2388 (set_attr "round_suffix" "normal")
2389 (set_attr "trap_suffix" "u_su_sui")])
2391 (define_insn "addsf3"
2392 [(set (match_operand:SF 0 "register_operand" "=f")
2393 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2394 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2395 "TARGET_FP"
2396 "add%,%/ %R1,%R2,%0"
2397 [(set_attr "type" "fadd")
2398 (set_attr "trap" "yes")
2399 (set_attr "round_suffix" "normal")
2400 (set_attr "trap_suffix" "u_su_sui")])
2402 (define_insn "*adddf_ieee"
2403 [(set (match_operand:DF 0 "register_operand" "=&f")
2404 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2405 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2406 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2407 "add%-%/ %R1,%R2,%0"
2408 [(set_attr "type" "fadd")
2409 (set_attr "trap" "yes")
2410 (set_attr "round_suffix" "normal")
2411 (set_attr "trap_suffix" "u_su_sui")])
2413 (define_insn "adddf3"
2414 [(set (match_operand:DF 0 "register_operand" "=f")
2415 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2416 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2417 "TARGET_FP"
2418 "add%-%/ %R1,%R2,%0"
2419 [(set_attr "type" "fadd")
2420 (set_attr "trap" "yes")
2421 (set_attr "round_suffix" "normal")
2422 (set_attr "trap_suffix" "u_su_sui")])
2424 (define_insn "*adddf_ext1"
2425 [(set (match_operand:DF 0 "register_operand" "=f")
2426 (plus:DF (float_extend:DF
2427 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2428 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2429 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2430 "add%-%/ %R1,%R2,%0"
2431 [(set_attr "type" "fadd")
2432 (set_attr "trap" "yes")
2433 (set_attr "round_suffix" "normal")
2434 (set_attr "trap_suffix" "u_su_sui")])
2436 (define_insn "*adddf_ext2"
2437 [(set (match_operand:DF 0 "register_operand" "=f")
2438 (plus:DF (float_extend:DF
2439 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2440 (float_extend:DF
2441 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2442 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2443 "add%-%/ %R1,%R2,%0"
2444 [(set_attr "type" "fadd")
2445 (set_attr "trap" "yes")
2446 (set_attr "round_suffix" "normal")
2447 (set_attr "trap_suffix" "u_su_sui")])
2449 (define_expand "addtf3"
2450 [(use (match_operand 0 "register_operand" ""))
2451 (use (match_operand 1 "general_operand" ""))
2452 (use (match_operand 2 "general_operand" ""))]
2453 "TARGET_HAS_XFLOATING_LIBS"
2454 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2456 ;; Define conversion operators between DFmode and SImode, using the cvtql
2457 ;; instruction. To allow combine et al to do useful things, we keep the
2458 ;; operation as a unit until after reload, at which point we split the
2459 ;; instructions.
2460 ;;
2461 ;; Note that we (attempt to) only consider this optimization when the
2462 ;; ultimate destination is memory. If we will be doing further integer
2463 ;; processing, it is cheaper to do the truncation in the int regs.
2465 (define_insn "*cvtql"
2466 [(set (match_operand:SF 0 "register_operand" "=f")
2467 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2468 UNSPEC_CVTQL))]
2469 "TARGET_FP"
2470 "cvtql%/ %R1,%0"
2471 [(set_attr "type" "fadd")
2472 (set_attr "trap" "yes")
2473 (set_attr "trap_suffix" "v_sv")])
2475 (define_insn_and_split "*fix_truncdfsi_ieee"
2476 [(set (match_operand:SI 0 "memory_operand" "=m")
2477 (subreg:SI
2478 (match_operator:DI 4 "fix_operator"
2479 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2480 (clobber (match_scratch:DI 2 "=&f"))
2481 (clobber (match_scratch:SF 3 "=&f"))]
2482 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2483 "#"
2484 "&& reload_completed"
2485 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2486 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2487 (set (match_dup 5) (match_dup 3))]
2488 {
2489 operands[5] = adjust_address (operands[0], SFmode, 0);
2490 }
2491 [(set_attr "type" "fadd")
2492 (set_attr "trap" "yes")])
2494 (define_insn_and_split "*fix_truncdfsi_internal"
2495 [(set (match_operand:SI 0 "memory_operand" "=m")
2496 (subreg:SI
2497 (match_operator:DI 3 "fix_operator"
2498 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2499 (clobber (match_scratch:DI 2 "=f"))]
2500 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2501 "#"
2502 "&& reload_completed"
2503 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2504 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2505 (set (match_dup 5) (match_dup 4))]
2506 {
2507 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2508 operands[5] = adjust_address (operands[0], SFmode, 0);
2509 }
2510 [(set_attr "type" "fadd")
2511 (set_attr "trap" "yes")])
2513 (define_insn "*fix_truncdfdi_ieee"
2514 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2515 (match_operator:DI 2 "fix_operator"
2516 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2517 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2518 "cvt%-q%/ %R1,%0"
2519 [(set_attr "type" "fadd")
2520 (set_attr "trap" "yes")
2521 (set_attr "round_suffix" "c")
2522 (set_attr "trap_suffix" "v_sv_svi")])
2524 (define_insn "*fix_truncdfdi2"
2525 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2526 (match_operator:DI 2 "fix_operator"
2527 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2528 "TARGET_FP"
2529 "cvt%-q%/ %R1,%0"
2530 [(set_attr "type" "fadd")
2531 (set_attr "trap" "yes")
2532 (set_attr "round_suffix" "c")
2533 (set_attr "trap_suffix" "v_sv_svi")])
2535 (define_expand "fix_truncdfdi2"
2536 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2537 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2538 "TARGET_FP"
2539 "")
2541 (define_expand "fixuns_truncdfdi2"
2542 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2543 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2544 "TARGET_FP"
2545 "")
2547 ;; Likewise between SFmode and SImode.
2549 (define_insn_and_split "*fix_truncsfsi_ieee"
2550 [(set (match_operand:SI 0 "memory_operand" "=m")
2551 (subreg:SI
2552 (match_operator:DI 4 "fix_operator"
2553 [(float_extend:DF
2554 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2555 (clobber (match_scratch:DI 2 "=&f"))
2556 (clobber (match_scratch:SF 3 "=&f"))]
2557 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2558 "#"
2559 "&& reload_completed"
2560 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2561 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2562 (set (match_dup 5) (match_dup 3))]
2563 {
2564 operands[5] = adjust_address (operands[0], SFmode, 0);
2565 }
2566 [(set_attr "type" "fadd")
2567 (set_attr "trap" "yes")])
2569 (define_insn_and_split "*fix_truncsfsi_internal"
2570 [(set (match_operand:SI 0 "memory_operand" "=m")
2571 (subreg:SI
2572 (match_operator:DI 3 "fix_operator"
2573 [(float_extend:DF
2574 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2575 (clobber (match_scratch:DI 2 "=f"))]
2576 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2577 "#"
2578 "&& reload_completed"
2579 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2580 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2581 (set (match_dup 5) (match_dup 4))]
2582 {
2583 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2584 operands[5] = adjust_address (operands[0], SFmode, 0);
2585 }
2586 [(set_attr "type" "fadd")
2587 (set_attr "trap" "yes")])
2589 (define_insn "*fix_truncsfdi_ieee"
2590 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2591 (match_operator:DI 2 "fix_operator"
2592 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2593 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2594 "cvt%-q%/ %R1,%0"
2595 [(set_attr "type" "fadd")
2596 (set_attr "trap" "yes")
2597 (set_attr "round_suffix" "c")
2598 (set_attr "trap_suffix" "v_sv_svi")])
2600 (define_insn "*fix_truncsfdi2"
2601 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2602 (match_operator:DI 2 "fix_operator"
2603 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2604 "TARGET_FP"
2605 "cvt%-q%/ %R1,%0"
2606 [(set_attr "type" "fadd")
2607 (set_attr "trap" "yes")
2608 (set_attr "round_suffix" "c")
2609 (set_attr "trap_suffix" "v_sv_svi")])
2611 (define_expand "fix_truncsfdi2"
2612 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2613 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2614 "TARGET_FP"
2615 "")
2617 (define_expand "fixuns_truncsfdi2"
2618 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2619 (unsigned_fix:DI
2620 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2621 "TARGET_FP"
2622 "")
2624 (define_expand "fix_trunctfdi2"
2625 [(use (match_operand:DI 0 "register_operand" ""))
2626 (use (match_operand:TF 1 "general_operand" ""))]
2627 "TARGET_HAS_XFLOATING_LIBS"
2628 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2630 (define_expand "fixuns_trunctfdi2"
2631 [(use (match_operand:DI 0 "register_operand" ""))
2632 (use (match_operand:TF 1 "general_operand" ""))]
2633 "TARGET_HAS_XFLOATING_LIBS"
2634 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2636 (define_insn "*floatdisf_ieee"
2637 [(set (match_operand:SF 0 "register_operand" "=&f")
2638 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2639 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2640 "cvtq%,%/ %1,%0"
2641 [(set_attr "type" "fadd")
2642 (set_attr "trap" "yes")
2643 (set_attr "round_suffix" "normal")
2644 (set_attr "trap_suffix" "sui")])
2646 (define_insn "floatdisf2"
2647 [(set (match_operand:SF 0 "register_operand" "=f")
2648 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2649 "TARGET_FP"
2650 "cvtq%,%/ %1,%0"
2651 [(set_attr "type" "fadd")
2652 (set_attr "trap" "yes")
2653 (set_attr "round_suffix" "normal")
2654 (set_attr "trap_suffix" "sui")])
2656 (define_insn_and_split "*floatsisf2_ieee"
2657 [(set (match_operand:SF 0 "register_operand" "=&f")
2658 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2659 (clobber (match_scratch:DI 2 "=&f"))
2660 (clobber (match_scratch:SF 3 "=&f"))]
2661 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2662 "#"
2663 "&& reload_completed"
2664 [(set (match_dup 3) (match_dup 1))
2665 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2666 (set (match_dup 0) (float:SF (match_dup 2)))]
2667 {
2668 operands[1] = adjust_address (operands[1], SFmode, 0);
2669 })
2671 (define_insn_and_split "*floatsisf2"
2672 [(set (match_operand:SF 0 "register_operand" "=f")
2673 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2674 "TARGET_FP"
2675 "#"
2676 "&& reload_completed"
2677 [(set (match_dup 0) (match_dup 1))
2678 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2679 (set (match_dup 0) (float:SF (match_dup 2)))]
2680 {
2681 operands[1] = adjust_address (operands[1], SFmode, 0);
2682 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2683 })
2685 (define_insn "*floatdidf_ieee"
2686 [(set (match_operand:DF 0 "register_operand" "=&f")
2687 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2688 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2689 "cvtq%-%/ %1,%0"
2690 [(set_attr "type" "fadd")
2691 (set_attr "trap" "yes")
2692 (set_attr "round_suffix" "normal")
2693 (set_attr "trap_suffix" "sui")])
2695 (define_insn "floatdidf2"
2696 [(set (match_operand:DF 0 "register_operand" "=f")
2697 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2698 "TARGET_FP"
2699 "cvtq%-%/ %1,%0"
2700 [(set_attr "type" "fadd")
2701 (set_attr "trap" "yes")
2702 (set_attr "round_suffix" "normal")
2703 (set_attr "trap_suffix" "sui")])
2705 (define_insn_and_split "*floatsidf2_ieee"
2706 [(set (match_operand:DF 0 "register_operand" "=&f")
2707 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2708 (clobber (match_scratch:DI 2 "=&f"))
2709 (clobber (match_scratch:SF 3 "=&f"))]
2710 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2711 "#"
2712 "&& reload_completed"
2713 [(set (match_dup 3) (match_dup 1))
2714 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2715 (set (match_dup 0) (float:DF (match_dup 2)))]
2716 {
2717 operands[1] = adjust_address (operands[1], SFmode, 0);
2718 })
2720 (define_insn_and_split "*floatsidf2"
2721 [(set (match_operand:DF 0 "register_operand" "=f")
2722 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2723 "TARGET_FP"
2724 "#"
2725 "&& reload_completed"
2726 [(set (match_dup 3) (match_dup 1))
2727 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2728 (set (match_dup 0) (float:DF (match_dup 2)))]
2729 {
2730 operands[1] = adjust_address (operands[1], SFmode, 0);
2731 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2732 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2733 })
2735 (define_expand "floatditf2"
2736 [(use (match_operand:TF 0 "register_operand" ""))
2737 (use (match_operand:DI 1 "general_operand" ""))]
2738 "TARGET_HAS_XFLOATING_LIBS"
2739 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2741 (define_expand "floatunsdisf2"
2742 [(use (match_operand:SF 0 "register_operand" ""))
2743 (use (match_operand:DI 1 "register_operand" ""))]
2744 "TARGET_FP"
2745 "alpha_emit_floatuns (operands); DONE;")
2747 (define_expand "floatunsdidf2"
2748 [(use (match_operand:DF 0 "register_operand" ""))
2749 (use (match_operand:DI 1 "register_operand" ""))]
2750 "TARGET_FP"
2751 "alpha_emit_floatuns (operands); DONE;")
2753 (define_expand "floatunsditf2"
2754 [(use (match_operand:TF 0 "register_operand" ""))
2755 (use (match_operand:DI 1 "general_operand" ""))]
2756 "TARGET_HAS_XFLOATING_LIBS"
2757 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2759 (define_expand "extendsfdf2"
2760 [(set (match_operand:DF 0 "register_operand" "")
2761 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2762 "TARGET_FP"
2763 {
2764 if (alpha_fptm >= ALPHA_FPTM_SU)
2765 operands[1] = force_reg (SFmode, operands[1]);
2766 })
2768 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2769 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2771 (define_insn "*extendsfdf2_ieee"
2772 [(set (match_operand:DF 0 "register_operand" "=&f")
2773 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2774 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2775 "cvtsts %1,%0"
2776 [(set_attr "type" "fadd")
2777 (set_attr "trap" "yes")])
2779 (define_insn "*extendsfdf2_internal"
2780 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2781 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2782 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2783 "@
2784 cpys %1,%1,%0
2785 ld%, %0,%1
2786 st%- %1,%0"
2787 [(set_attr "type" "fcpys,fld,fst")])
2789 ;; Use register_operand for operand 1 to prevent compress_float_constant
2790 ;; from doing something silly. When optimizing we'll put things back
2791 ;; together anyway.
2792 (define_expand "extendsftf2"
2793 [(use (match_operand:TF 0 "register_operand" ""))
2794 (use (match_operand:SF 1 "register_operand" ""))]
2795 "TARGET_HAS_XFLOATING_LIBS"
2796 {
2797 rtx tmp = gen_reg_rtx (DFmode);
2798 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2799 emit_insn (gen_extenddftf2 (operands[0], tmp));
2800 DONE;
2801 })
2803 (define_expand "extenddftf2"
2804 [(use (match_operand:TF 0 "register_operand" ""))
2805 (use (match_operand:DF 1 "register_operand" ""))]
2806 "TARGET_HAS_XFLOATING_LIBS"
2807 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2809 (define_insn "*truncdfsf2_ieee"
2810 [(set (match_operand:SF 0 "register_operand" "=&f")
2811 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2812 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2813 "cvt%-%,%/ %R1,%0"
2814 [(set_attr "type" "fadd")
2815 (set_attr "trap" "yes")
2816 (set_attr "round_suffix" "normal")
2817 (set_attr "trap_suffix" "u_su_sui")])
2819 (define_insn "truncdfsf2"
2820 [(set (match_operand:SF 0 "register_operand" "=f")
2821 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2822 "TARGET_FP"
2823 "cvt%-%,%/ %R1,%0"
2824 [(set_attr "type" "fadd")
2825 (set_attr "trap" "yes")
2826 (set_attr "round_suffix" "normal")
2827 (set_attr "trap_suffix" "u_su_sui")])
2829 (define_expand "trunctfdf2"
2830 [(use (match_operand:DF 0 "register_operand" ""))
2831 (use (match_operand:TF 1 "general_operand" ""))]
2832 "TARGET_HAS_XFLOATING_LIBS"
2833 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2835 (define_expand "trunctfsf2"
2836 [(use (match_operand:SF 0 "register_operand" ""))
2837 (use (match_operand:TF 1 "general_operand" ""))]
2838 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2839 {
2840 rtx tmpf, sticky, arg, lo, hi;
2842 tmpf = gen_reg_rtx (DFmode);
2843 sticky = gen_reg_rtx (DImode);
2844 arg = copy_to_mode_reg (TFmode, operands[1]);
2845 lo = gen_lowpart (DImode, arg);
2846 hi = gen_highpart (DImode, arg);
2848 /* Convert the low word of the TFmode value into a sticky rounding bit,
2849 then or it into the low bit of the high word. This leaves the sticky
2850 bit at bit 48 of the fraction, which is representable in DFmode,
2851 which prevents rounding error in the final conversion to SFmode. */
2853 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2854 gen_rtx_NE (DImode, lo, const0_rtx)));
2855 emit_insn (gen_iordi3 (hi, hi, sticky));
2856 emit_insn (gen_trunctfdf2 (tmpf, arg));
2857 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2858 DONE;
2859 })
2861 (define_insn "*divsf3_ieee"
2862 [(set (match_operand:SF 0 "register_operand" "=&f")
2863 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2864 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2865 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2866 "div%,%/ %R1,%R2,%0"
2867 [(set_attr "type" "fdiv")
2868 (set_attr "opsize" "si")
2869 (set_attr "trap" "yes")
2870 (set_attr "round_suffix" "normal")
2871 (set_attr "trap_suffix" "u_su_sui")])
2873 (define_insn "divsf3"
2874 [(set (match_operand:SF 0 "register_operand" "=f")
2875 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2876 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2877 "TARGET_FP"
2878 "div%,%/ %R1,%R2,%0"
2879 [(set_attr "type" "fdiv")
2880 (set_attr "opsize" "si")
2881 (set_attr "trap" "yes")
2882 (set_attr "round_suffix" "normal")
2883 (set_attr "trap_suffix" "u_su_sui")])
2885 (define_insn "*divdf3_ieee"
2886 [(set (match_operand:DF 0 "register_operand" "=&f")
2887 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2888 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2889 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2890 "div%-%/ %R1,%R2,%0"
2891 [(set_attr "type" "fdiv")
2892 (set_attr "trap" "yes")
2893 (set_attr "round_suffix" "normal")
2894 (set_attr "trap_suffix" "u_su_sui")])
2896 (define_insn "divdf3"
2897 [(set (match_operand:DF 0 "register_operand" "=f")
2898 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2899 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2900 "TARGET_FP"
2901 "div%-%/ %R1,%R2,%0"
2902 [(set_attr "type" "fdiv")
2903 (set_attr "trap" "yes")
2904 (set_attr "round_suffix" "normal")
2905 (set_attr "trap_suffix" "u_su_sui")])
2907 (define_insn "*divdf_ext1"
2908 [(set (match_operand:DF 0 "register_operand" "=f")
2909 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2910 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2911 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2912 "div%-%/ %R1,%R2,%0"
2913 [(set_attr "type" "fdiv")
2914 (set_attr "trap" "yes")
2915 (set_attr "round_suffix" "normal")
2916 (set_attr "trap_suffix" "u_su_sui")])
2918 (define_insn "*divdf_ext2"
2919 [(set (match_operand:DF 0 "register_operand" "=f")
2920 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2921 (float_extend:DF
2922 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2923 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2924 "div%-%/ %R1,%R2,%0"
2925 [(set_attr "type" "fdiv")
2926 (set_attr "trap" "yes")
2927 (set_attr "round_suffix" "normal")
2928 (set_attr "trap_suffix" "u_su_sui")])
2930 (define_insn "*divdf_ext3"
2931 [(set (match_operand:DF 0 "register_operand" "=f")
2932 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2933 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2934 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2935 "div%-%/ %R1,%R2,%0"
2936 [(set_attr "type" "fdiv")
2937 (set_attr "trap" "yes")
2938 (set_attr "round_suffix" "normal")
2939 (set_attr "trap_suffix" "u_su_sui")])
2941 (define_expand "divtf3"
2942 [(use (match_operand 0 "register_operand" ""))
2943 (use (match_operand 1 "general_operand" ""))
2944 (use (match_operand 2 "general_operand" ""))]
2945 "TARGET_HAS_XFLOATING_LIBS"
2946 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2948 (define_insn "*mulsf3_ieee"
2949 [(set (match_operand:SF 0 "register_operand" "=&f")
2950 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2951 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2952 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2953 "mul%,%/ %R1,%R2,%0"
2954 [(set_attr "type" "fmul")
2955 (set_attr "trap" "yes")
2956 (set_attr "round_suffix" "normal")
2957 (set_attr "trap_suffix" "u_su_sui")])
2959 (define_insn "mulsf3"
2960 [(set (match_operand:SF 0 "register_operand" "=f")
2961 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2962 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2963 "TARGET_FP"
2964 "mul%,%/ %R1,%R2,%0"
2965 [(set_attr "type" "fmul")
2966 (set_attr "trap" "yes")
2967 (set_attr "round_suffix" "normal")
2968 (set_attr "trap_suffix" "u_su_sui")])
2970 (define_insn "*muldf3_ieee"
2971 [(set (match_operand:DF 0 "register_operand" "=&f")
2972 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2973 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2974 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2975 "mul%-%/ %R1,%R2,%0"
2976 [(set_attr "type" "fmul")
2977 (set_attr "trap" "yes")
2978 (set_attr "round_suffix" "normal")
2979 (set_attr "trap_suffix" "u_su_sui")])
2981 (define_insn "muldf3"
2982 [(set (match_operand:DF 0 "register_operand" "=f")
2983 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2984 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2985 "TARGET_FP"
2986 "mul%-%/ %R1,%R2,%0"
2987 [(set_attr "type" "fmul")
2988 (set_attr "trap" "yes")
2989 (set_attr "round_suffix" "normal")
2990 (set_attr "trap_suffix" "u_su_sui")])
2992 (define_insn "*muldf_ext1"
2993 [(set (match_operand:DF 0 "register_operand" "=f")
2994 (mult:DF (float_extend:DF
2995 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2996 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2997 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2998 "mul%-%/ %R1,%R2,%0"
2999 [(set_attr "type" "fmul")
3000 (set_attr "trap" "yes")
3001 (set_attr "round_suffix" "normal")
3002 (set_attr "trap_suffix" "u_su_sui")])
3004 (define_insn "*muldf_ext2"
3005 [(set (match_operand:DF 0 "register_operand" "=f")
3006 (mult:DF (float_extend:DF
3007 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
3008 (float_extend:DF
3009 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3010 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3011 "mul%-%/ %R1,%R2,%0"
3012 [(set_attr "type" "fmul")
3013 (set_attr "trap" "yes")
3014 (set_attr "round_suffix" "normal")
3015 (set_attr "trap_suffix" "u_su_sui")])
3017 (define_expand "multf3"
3018 [(use (match_operand 0 "register_operand" ""))
3019 (use (match_operand 1 "general_operand" ""))
3020 (use (match_operand 2 "general_operand" ""))]
3021 "TARGET_HAS_XFLOATING_LIBS"
3022 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
3024 (define_insn "*subsf3_ieee"
3025 [(set (match_operand:SF 0 "register_operand" "=&f")
3026 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3027 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3028 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3029 "sub%,%/ %R1,%R2,%0"
3030 [(set_attr "type" "fadd")
3031 (set_attr "trap" "yes")
3032 (set_attr "round_suffix" "normal")
3033 (set_attr "trap_suffix" "u_su_sui")])
3035 (define_insn "subsf3"
3036 [(set (match_operand:SF 0 "register_operand" "=f")
3037 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3038 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3039 "TARGET_FP"
3040 "sub%,%/ %R1,%R2,%0"
3041 [(set_attr "type" "fadd")
3042 (set_attr "trap" "yes")
3043 (set_attr "round_suffix" "normal")
3044 (set_attr "trap_suffix" "u_su_sui")])
3046 (define_insn "*subdf3_ieee"
3047 [(set (match_operand:DF 0 "register_operand" "=&f")
3048 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3049 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3050 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3051 "sub%-%/ %R1,%R2,%0"
3052 [(set_attr "type" "fadd")
3053 (set_attr "trap" "yes")
3054 (set_attr "round_suffix" "normal")
3055 (set_attr "trap_suffix" "u_su_sui")])
3057 (define_insn "subdf3"
3058 [(set (match_operand:DF 0 "register_operand" "=f")
3059 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3060 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3061 "TARGET_FP"
3062 "sub%-%/ %R1,%R2,%0"
3063 [(set_attr "type" "fadd")
3064 (set_attr "trap" "yes")
3065 (set_attr "round_suffix" "normal")
3066 (set_attr "trap_suffix" "u_su_sui")])
3068 (define_insn "*subdf_ext1"
3069 [(set (match_operand:DF 0 "register_operand" "=f")
3070 (minus:DF (float_extend:DF
3071 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3072 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3073 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3074 "sub%-%/ %R1,%R2,%0"
3075 [(set_attr "type" "fadd")
3076 (set_attr "trap" "yes")
3077 (set_attr "round_suffix" "normal")
3078 (set_attr "trap_suffix" "u_su_sui")])
3080 (define_insn "*subdf_ext2"
3081 [(set (match_operand:DF 0 "register_operand" "=f")
3082 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3083 (float_extend:DF
3084 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3085 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3086 "sub%-%/ %R1,%R2,%0"
3087 [(set_attr "type" "fadd")
3088 (set_attr "trap" "yes")
3089 (set_attr "round_suffix" "normal")
3090 (set_attr "trap_suffix" "u_su_sui")])
3092 (define_insn "*subdf_ext3"
3093 [(set (match_operand:DF 0 "register_operand" "=f")
3094 (minus:DF (float_extend:DF
3095 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3096 (float_extend:DF
3097 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3098 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3099 "sub%-%/ %R1,%R2,%0"
3100 [(set_attr "type" "fadd")
3101 (set_attr "trap" "yes")
3102 (set_attr "round_suffix" "normal")
3103 (set_attr "trap_suffix" "u_su_sui")])
3105 (define_expand "subtf3"
3106 [(use (match_operand 0 "register_operand" ""))
3107 (use (match_operand 1 "general_operand" ""))
3108 (use (match_operand 2 "general_operand" ""))]
3109 "TARGET_HAS_XFLOATING_LIBS"
3110 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3112 (define_insn "*sqrtsf2_ieee"
3113 [(set (match_operand:SF 0 "register_operand" "=&f")
3114 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3115 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3116 "sqrt%,%/ %R1,%0"
3117 [(set_attr "type" "fsqrt")
3118 (set_attr "opsize" "si")
3119 (set_attr "trap" "yes")
3120 (set_attr "round_suffix" "normal")
3121 (set_attr "trap_suffix" "u_su_sui")])
3123 (define_insn "sqrtsf2"
3124 [(set (match_operand:SF 0 "register_operand" "=f")
3125 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3126 "TARGET_FP && TARGET_FIX"
3127 "sqrt%,%/ %R1,%0"
3128 [(set_attr "type" "fsqrt")
3129 (set_attr "opsize" "si")
3130 (set_attr "trap" "yes")
3131 (set_attr "round_suffix" "normal")
3132 (set_attr "trap_suffix" "u_su_sui")])
3134 (define_insn "*sqrtdf2_ieee"
3135 [(set (match_operand:DF 0 "register_operand" "=&f")
3136 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3137 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3138 "sqrt%-%/ %R1,%0"
3139 [(set_attr "type" "fsqrt")
3140 (set_attr "trap" "yes")
3141 (set_attr "round_suffix" "normal")
3142 (set_attr "trap_suffix" "u_su_sui")])
3144 (define_insn "sqrtdf2"
3145 [(set (match_operand:DF 0 "register_operand" "=f")
3146 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3147 "TARGET_FP && TARGET_FIX"
3148 "sqrt%-%/ %R1,%0"
3149 [(set_attr "type" "fsqrt")
3150 (set_attr "trap" "yes")
3151 (set_attr "round_suffix" "normal")
3152 (set_attr "trap_suffix" "u_su_sui")])
3153 \f
3154 ;; Next are all the integer comparisons, and conditional moves and branches
3155 ;; and some of the related define_expand's and define_split's.
3157 (define_insn "*setcc_internal"
3158 [(set (match_operand 0 "register_operand" "=r")
3159 (match_operator 1 "alpha_comparison_operator"
3160 [(match_operand:DI 2 "register_operand" "r")
3161 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3162 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3163 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3164 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3165 "cmp%C1 %2,%3,%0"
3166 [(set_attr "type" "icmp")])
3168 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3169 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3170 ;; from cse on.
3171 (define_insn "*setcc_swapped_internal"
3172 [(set (match_operand 0 "register_operand" "=r")
3173 (match_operator 1 "alpha_swapped_comparison_operator"
3174 [(match_operand:DI 2 "register_operand" "r")
3175 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3176 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3177 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3178 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3179 "cmp%c1 %r3,%2,%0"
3180 [(set_attr "type" "icmp")])
3182 ;; Use match_operator rather than ne directly so that we can match
3183 ;; multiple integer modes.
3184 (define_insn "*setne_internal"
3185 [(set (match_operand 0 "register_operand" "=r")
3186 (match_operator 1 "signed_comparison_operator"
3187 [(match_operand:DI 2 "register_operand" "r")
3188 (const_int 0)]))]
3189 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3190 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3191 && GET_CODE (operands[1]) == NE
3192 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3193 "cmpult $31,%2,%0"
3194 [(set_attr "type" "icmp")])
3196 ;; The mode folding trick can't be used with const_int operands, since
3197 ;; reload needs to know the proper mode.
3198 ;;
3199 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3200 ;; in order to create more pairs of constants. As long as we're allowing
3201 ;; two constants at the same time, and will have to reload one of them...
3203 (define_insn "*movqicc_internal"
3204 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3205 (if_then_else:QI
3206 (match_operator 2 "signed_comparison_operator"
3207 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3208 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3209 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3210 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3211 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3212 "@
3213 cmov%C2 %r3,%1,%0
3214 cmov%D2 %r3,%5,%0
3215 cmov%c2 %r4,%1,%0
3216 cmov%d2 %r4,%5,%0"
3217 [(set_attr "type" "icmov")])
3219 (define_insn "*movhicc_internal"
3220 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3221 (if_then_else:HI
3222 (match_operator 2 "signed_comparison_operator"
3223 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3224 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3225 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3226 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3227 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3228 "@
3229 cmov%C2 %r3,%1,%0
3230 cmov%D2 %r3,%5,%0
3231 cmov%c2 %r4,%1,%0
3232 cmov%d2 %r4,%5,%0"
3233 [(set_attr "type" "icmov")])
3235 (define_insn "*movsicc_internal"
3236 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3237 (if_then_else:SI
3238 (match_operator 2 "signed_comparison_operator"
3239 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3240 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3241 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3242 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3243 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3244 "@
3245 cmov%C2 %r3,%1,%0
3246 cmov%D2 %r3,%5,%0
3247 cmov%c2 %r4,%1,%0
3248 cmov%d2 %r4,%5,%0"
3249 [(set_attr "type" "icmov")])
3251 (define_insn "*movdicc_internal"
3252 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3253 (if_then_else:DI
3254 (match_operator 2 "signed_comparison_operator"
3255 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3256 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3257 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3258 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3259 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3260 "@
3261 cmov%C2 %r3,%1,%0
3262 cmov%D2 %r3,%5,%0
3263 cmov%c2 %r4,%1,%0
3264 cmov%d2 %r4,%5,%0"
3265 [(set_attr "type" "icmov")])
3267 (define_insn "*movqicc_lbc"
3268 [(set (match_operand:QI 0 "register_operand" "=r,r")
3269 (if_then_else:QI
3270 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3271 (const_int 1)
3272 (const_int 0))
3273 (const_int 0))
3274 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3275 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3276 ""
3277 "@
3278 cmovlbc %r2,%1,%0
3279 cmovlbs %r2,%3,%0"
3280 [(set_attr "type" "icmov")])
3282 (define_insn "*movhicc_lbc"
3283 [(set (match_operand:HI 0 "register_operand" "=r,r")
3284 (if_then_else:HI
3285 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3286 (const_int 1)
3287 (const_int 0))
3288 (const_int 0))
3289 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3290 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3291 ""
3292 "@
3293 cmovlbc %r2,%1,%0
3294 cmovlbs %r2,%3,%0"
3295 [(set_attr "type" "icmov")])
3297 (define_insn "*movsicc_lbc"
3298 [(set (match_operand:SI 0 "register_operand" "=r,r")
3299 (if_then_else:SI
3300 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3301 (const_int 1)
3302 (const_int 0))
3303 (const_int 0))
3304 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3305 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3306 ""
3307 "@
3308 cmovlbc %r2,%1,%0
3309 cmovlbs %r2,%3,%0"
3310 [(set_attr "type" "icmov")])
3312 (define_insn "*movdicc_lbc"
3313 [(set (match_operand:DI 0 "register_operand" "=r,r")
3314 (if_then_else:DI
3315 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3316 (const_int 1)
3317 (const_int 0))
3318 (const_int 0))
3319 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3320 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3321 ""
3322 "@
3323 cmovlbc %r2,%1,%0
3324 cmovlbs %r2,%3,%0"
3325 [(set_attr "type" "icmov")])
3327 (define_insn "*movqicc_lbs"
3328 [(set (match_operand:QI 0 "register_operand" "=r,r")
3329 (if_then_else:QI
3330 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3331 (const_int 1)
3332 (const_int 0))
3333 (const_int 0))
3334 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3335 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3336 ""
3337 "@
3338 cmovlbs %r2,%1,%0
3339 cmovlbc %r2,%3,%0"
3340 [(set_attr "type" "icmov")])
3342 (define_insn "*movhicc_lbs"
3343 [(set (match_operand:HI 0 "register_operand" "=r,r")
3344 (if_then_else:HI
3345 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3346 (const_int 1)
3347 (const_int 0))
3348 (const_int 0))
3349 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3350 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3351 ""
3352 "@
3353 cmovlbs %r2,%1,%0
3354 cmovlbc %r2,%3,%0"
3355 [(set_attr "type" "icmov")])
3357 (define_insn "*movsicc_lbs"
3358 [(set (match_operand:SI 0 "register_operand" "=r,r")
3359 (if_then_else:SI
3360 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3361 (const_int 1)
3362 (const_int 0))
3363 (const_int 0))
3364 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3365 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3366 ""
3367 "@
3368 cmovlbs %r2,%1,%0
3369 cmovlbc %r2,%3,%0"
3370 [(set_attr "type" "icmov")])
3372 (define_insn "*movdicc_lbs"
3373 [(set (match_operand:DI 0 "register_operand" "=r,r")
3374 (if_then_else:DI
3375 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3376 (const_int 1)
3377 (const_int 0))
3378 (const_int 0))
3379 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3380 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3381 ""
3382 "@
3383 cmovlbs %r2,%1,%0
3384 cmovlbc %r2,%3,%0"
3385 [(set_attr "type" "icmov")])
3387 ;; For ABS, we have two choices, depending on whether the input and output
3388 ;; registers are the same or not.
3389 (define_expand "absdi2"
3390 [(set (match_operand:DI 0 "register_operand" "")
3391 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3392 ""
3393 {
3394 if (rtx_equal_p (operands[0], operands[1]))
3395 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3396 else
3397 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3398 DONE;
3399 })
3401 (define_expand "absdi2_same"
3402 [(set (match_operand:DI 1 "register_operand" "")
3403 (neg:DI (match_operand:DI 0 "register_operand" "")))
3404 (set (match_dup 0)
3405 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3406 (match_dup 0)
3407 (match_dup 1)))]
3408 ""
3409 "")
3411 (define_expand "absdi2_diff"
3412 [(set (match_operand:DI 0 "register_operand" "")
3413 (neg:DI (match_operand:DI 1 "register_operand" "")))
3414 (set (match_dup 0)
3415 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3416 (match_dup 0)
3417 (match_dup 1)))]
3418 ""
3419 "")
3421 (define_split
3422 [(set (match_operand:DI 0 "register_operand" "")
3423 (abs:DI (match_dup 0)))
3424 (clobber (match_operand:DI 1 "register_operand" ""))]
3425 ""
3426 [(set (match_dup 1) (neg:DI (match_dup 0)))
3427 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3428 (match_dup 0) (match_dup 1)))]
3429 "")
3431 (define_split
3432 [(set (match_operand:DI 0 "register_operand" "")
3433 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3434 "! rtx_equal_p (operands[0], operands[1])"
3435 [(set (match_dup 0) (neg:DI (match_dup 1)))
3436 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3437 (match_dup 0) (match_dup 1)))]
3438 "")
3440 (define_split
3441 [(set (match_operand:DI 0 "register_operand" "")
3442 (neg:DI (abs:DI (match_dup 0))))
3443 (clobber (match_operand:DI 1 "register_operand" ""))]
3444 ""
3445 [(set (match_dup 1) (neg:DI (match_dup 0)))
3446 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3447 (match_dup 0) (match_dup 1)))]
3448 "")
3450 (define_split
3451 [(set (match_operand:DI 0 "register_operand" "")
3452 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3453 "! rtx_equal_p (operands[0], operands[1])"
3454 [(set (match_dup 0) (neg:DI (match_dup 1)))
3455 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3456 (match_dup 0) (match_dup 1)))]
3457 "")
3459 (define_insn "sminqi3"
3460 [(set (match_operand:QI 0 "register_operand" "=r")
3461 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3462 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3463 "TARGET_MAX"
3464 "minsb8 %r1,%2,%0"
3465 [(set_attr "type" "mvi")])
3467 (define_insn "uminqi3"
3468 [(set (match_operand:QI 0 "register_operand" "=r")
3469 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3470 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3471 "TARGET_MAX"
3472 "minub8 %r1,%2,%0"
3473 [(set_attr "type" "mvi")])
3475 (define_insn "smaxqi3"
3476 [(set (match_operand:QI 0 "register_operand" "=r")
3477 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3478 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3479 "TARGET_MAX"
3480 "maxsb8 %r1,%2,%0"
3481 [(set_attr "type" "mvi")])
3483 (define_insn "umaxqi3"
3484 [(set (match_operand:QI 0 "register_operand" "=r")
3485 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3486 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3487 "TARGET_MAX"
3488 "maxub8 %r1,%2,%0"
3489 [(set_attr "type" "mvi")])
3491 (define_insn "sminhi3"
3492 [(set (match_operand:HI 0 "register_operand" "=r")
3493 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3494 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3495 "TARGET_MAX"
3496 "minsw4 %r1,%2,%0"
3497 [(set_attr "type" "mvi")])
3499 (define_insn "uminhi3"
3500 [(set (match_operand:HI 0 "register_operand" "=r")
3501 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3502 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3503 "TARGET_MAX"
3504 "minuw4 %r1,%2,%0"
3505 [(set_attr "type" "mvi")])
3507 (define_insn "smaxhi3"
3508 [(set (match_operand:HI 0 "register_operand" "=r")
3509 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3510 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3511 "TARGET_MAX"
3512 "maxsw4 %r1,%2,%0"
3513 [(set_attr "type" "mvi")])
3515 (define_insn "umaxhi3"
3516 [(set (match_operand:HI 0 "register_operand" "=r")
3517 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3518 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3519 "TARGET_MAX"
3520 "maxuw4 %r1,%2,%0"
3521 [(set_attr "type" "mvi")])
3523 (define_expand "smaxdi3"
3524 [(set (match_dup 3)
3525 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3526 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3527 (set (match_operand:DI 0 "register_operand" "")
3528 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3529 (match_dup 1) (match_dup 2)))]
3530 ""
3531 { operands[3] = gen_reg_rtx (DImode); })
3533 (define_split
3534 [(set (match_operand:DI 0 "register_operand" "")
3535 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3536 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3537 (clobber (match_operand:DI 3 "register_operand" ""))]
3538 "operands[2] != const0_rtx"
3539 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3540 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3541 (match_dup 1) (match_dup 2)))]
3542 "")
3544 (define_insn "*smax_const0"
3545 [(set (match_operand:DI 0 "register_operand" "=r")
3546 (smax:DI (match_operand:DI 1 "register_operand" "0")
3547 (const_int 0)))]
3548 ""
3549 "cmovlt %0,0,%0"
3550 [(set_attr "type" "icmov")])
3552 (define_expand "smindi3"
3553 [(set (match_dup 3)
3554 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3555 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3556 (set (match_operand:DI 0 "register_operand" "")
3557 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3558 (match_dup 1) (match_dup 2)))]
3559 ""
3560 { operands[3] = gen_reg_rtx (DImode); })
3562 (define_split
3563 [(set (match_operand:DI 0 "register_operand" "")
3564 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3565 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3566 (clobber (match_operand:DI 3 "register_operand" ""))]
3567 "operands[2] != const0_rtx"
3568 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3569 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3570 (match_dup 1) (match_dup 2)))]
3571 "")
3573 (define_insn "*smin_const0"
3574 [(set (match_operand:DI 0 "register_operand" "=r")
3575 (smin:DI (match_operand:DI 1 "register_operand" "0")
3576 (const_int 0)))]
3577 ""
3578 "cmovgt %0,0,%0"
3579 [(set_attr "type" "icmov")])
3581 (define_expand "umaxdi3"
3582 [(set (match_dup 3)
3583 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3584 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3585 (set (match_operand:DI 0 "register_operand" "")
3586 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3587 (match_dup 1) (match_dup 2)))]
3588 ""
3589 "operands[3] = gen_reg_rtx (DImode);")
3591 (define_split
3592 [(set (match_operand:DI 0 "register_operand" "")
3593 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3594 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3595 (clobber (match_operand:DI 3 "register_operand" ""))]
3596 "operands[2] != const0_rtx"
3597 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3598 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3599 (match_dup 1) (match_dup 2)))]
3600 "")
3602 (define_expand "umindi3"
3603 [(set (match_dup 3)
3604 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3605 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3606 (set (match_operand:DI 0 "register_operand" "")
3607 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3608 (match_dup 1) (match_dup 2)))]
3609 ""
3610 "operands[3] = gen_reg_rtx (DImode);")
3612 (define_split
3613 [(set (match_operand:DI 0 "register_operand" "")
3614 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3615 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3616 (clobber (match_operand:DI 3 "register_operand" ""))]
3617 "operands[2] != const0_rtx"
3618 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3619 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3620 (match_dup 1) (match_dup 2)))]
3621 "")
3623 (define_insn "*bcc_normal"
3624 [(set (pc)
3625 (if_then_else
3626 (match_operator 1 "signed_comparison_operator"
3627 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3628 (const_int 0)])
3629 (label_ref (match_operand 0 "" ""))
3630 (pc)))]
3631 ""
3632 "b%C1 %r2,%0"
3633 [(set_attr "type" "ibr")])
3635 (define_insn "*bcc_reverse"
3636 [(set (pc)
3637 (if_then_else
3638 (match_operator 1 "signed_comparison_operator"
3639 [(match_operand:DI 2 "register_operand" "r")
3640 (const_int 0)])
3642 (pc)
3643 (label_ref (match_operand 0 "" ""))))]
3644 ""
3645 "b%c1 %2,%0"
3646 [(set_attr "type" "ibr")])
3648 (define_insn "*blbs_normal"
3649 [(set (pc)
3650 (if_then_else
3651 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3652 (const_int 1)
3653 (const_int 0))
3654 (const_int 0))
3655 (label_ref (match_operand 0 "" ""))
3656 (pc)))]
3657 ""
3658 "blbs %r1,%0"
3659 [(set_attr "type" "ibr")])
3661 (define_insn "*blbc_normal"
3662 [(set (pc)
3663 (if_then_else
3664 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3665 (const_int 1)
3666 (const_int 0))
3667 (const_int 0))
3668 (label_ref (match_operand 0 "" ""))
3669 (pc)))]
3670 ""
3671 "blbc %r1,%0"
3672 [(set_attr "type" "ibr")])
3674 (define_split
3675 [(parallel
3676 [(set (pc)
3677 (if_then_else
3678 (match_operator 1 "comparison_operator"
3679 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3680 (const_int 1)
3681 (match_operand:DI 3 "const_int_operand" ""))
3682 (const_int 0)])
3683 (label_ref (match_operand 0 "" ""))
3684 (pc)))
3685 (clobber (match_operand:DI 4 "register_operand" ""))])]
3686 "INTVAL (operands[3]) != 0"
3687 [(set (match_dup 4)
3688 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3689 (set (pc)
3690 (if_then_else (match_op_dup 1
3691 [(zero_extract:DI (match_dup 4)
3692 (const_int 1)
3693 (const_int 0))
3694 (const_int 0)])
3695 (label_ref (match_dup 0))
3696 (pc)))]
3697 "")
3698 \f
3699 ;; The following are the corresponding floating-point insns. Recall
3700 ;; we need to have variants that expand the arguments from SFmode
3701 ;; to DFmode.
3703 (define_insn "*cmpdf_ieee"
3704 [(set (match_operand:DF 0 "register_operand" "=&f")
3705 (match_operator:DF 1 "alpha_fp_comparison_operator"
3706 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3707 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3708 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3709 "cmp%-%C1%/ %R2,%R3,%0"
3710 [(set_attr "type" "fadd")
3711 (set_attr "trap" "yes")
3712 (set_attr "trap_suffix" "su")])
3714 (define_insn "*cmpdf_internal"
3715 [(set (match_operand:DF 0 "register_operand" "=f")
3716 (match_operator:DF 1 "alpha_fp_comparison_operator"
3717 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3718 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3719 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3720 "cmp%-%C1%/ %R2,%R3,%0"
3721 [(set_attr "type" "fadd")
3722 (set_attr "trap" "yes")
3723 (set_attr "trap_suffix" "su")])
3725 (define_insn "*cmpdf_ieee_ext1"
3726 [(set (match_operand:DF 0 "register_operand" "=&f")
3727 (match_operator:DF 1 "alpha_fp_comparison_operator"
3728 [(float_extend:DF
3729 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3730 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3731 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3732 "cmp%-%C1%/ %R2,%R3,%0"
3733 [(set_attr "type" "fadd")
3734 (set_attr "trap" "yes")
3735 (set_attr "trap_suffix" "su")])
3737 (define_insn "*cmpdf_ext1"
3738 [(set (match_operand:DF 0 "register_operand" "=f")
3739 (match_operator:DF 1 "alpha_fp_comparison_operator"
3740 [(float_extend:DF
3741 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3742 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3743 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3744 "cmp%-%C1%/ %R2,%R3,%0"
3745 [(set_attr "type" "fadd")
3746 (set_attr "trap" "yes")
3747 (set_attr "trap_suffix" "su")])
3749 (define_insn "*cmpdf_ieee_ext2"
3750 [(set (match_operand:DF 0 "register_operand" "=&f")
3751 (match_operator:DF 1 "alpha_fp_comparison_operator"
3752 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3753 (float_extend:DF
3754 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3755 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3756 "cmp%-%C1%/ %R2,%R3,%0"
3757 [(set_attr "type" "fadd")
3758 (set_attr "trap" "yes")
3759 (set_attr "trap_suffix" "su")])
3761 (define_insn "*cmpdf_ext2"
3762 [(set (match_operand:DF 0 "register_operand" "=f")
3763 (match_operator:DF 1 "alpha_fp_comparison_operator"
3764 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3765 (float_extend:DF
3766 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3767 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3768 "cmp%-%C1%/ %R2,%R3,%0"
3769 [(set_attr "type" "fadd")
3770 (set_attr "trap" "yes")
3771 (set_attr "trap_suffix" "su")])
3773 (define_insn "*cmpdf_ieee_ext3"
3774 [(set (match_operand:DF 0 "register_operand" "=&f")
3775 (match_operator:DF 1 "alpha_fp_comparison_operator"
3776 [(float_extend:DF
3777 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3778 (float_extend:DF
3779 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3780 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3781 "cmp%-%C1%/ %R2,%R3,%0"
3782 [(set_attr "type" "fadd")
3783 (set_attr "trap" "yes")
3784 (set_attr "trap_suffix" "su")])
3786 (define_insn "*cmpdf_ext3"
3787 [(set (match_operand:DF 0 "register_operand" "=f")
3788 (match_operator:DF 1 "alpha_fp_comparison_operator"
3789 [(float_extend:DF
3790 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3791 (float_extend:DF
3792 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3793 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3794 "cmp%-%C1%/ %R2,%R3,%0"
3795 [(set_attr "type" "fadd")
3796 (set_attr "trap" "yes")
3797 (set_attr "trap_suffix" "su")])
3799 (define_insn "*movdfcc_internal"
3800 [(set (match_operand:DF 0 "register_operand" "=f,f")
3801 (if_then_else:DF
3802 (match_operator 3 "signed_comparison_operator"
3803 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3804 (match_operand:DF 2 "const0_operand" "G,G")])
3805 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3806 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3807 "TARGET_FP"
3808 "@
3809 fcmov%C3 %R4,%R1,%0
3810 fcmov%D3 %R4,%R5,%0"
3811 [(set_attr "type" "fcmov")])
3813 (define_insn "*movsfcc_internal"
3814 [(set (match_operand:SF 0 "register_operand" "=f,f")
3815 (if_then_else:SF
3816 (match_operator 3 "signed_comparison_operator"
3817 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3818 (match_operand:DF 2 "const0_operand" "G,G")])
3819 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3820 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3821 "TARGET_FP"
3822 "@
3823 fcmov%C3 %R4,%R1,%0
3824 fcmov%D3 %R4,%R5,%0"
3825 [(set_attr "type" "fcmov")])
3827 (define_insn "*movdfcc_ext1"
3828 [(set (match_operand:DF 0 "register_operand" "=f,f")
3829 (if_then_else:DF
3830 (match_operator 3 "signed_comparison_operator"
3831 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3832 (match_operand:DF 2 "const0_operand" "G,G")])
3833 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3834 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3835 "TARGET_FP"
3836 "@
3837 fcmov%C3 %R4,%R1,%0
3838 fcmov%D3 %R4,%R5,%0"
3839 [(set_attr "type" "fcmov")])
3841 (define_insn "*movdfcc_ext2"
3842 [(set (match_operand:DF 0 "register_operand" "=f,f")
3843 (if_then_else:DF
3844 (match_operator 3 "signed_comparison_operator"
3845 [(float_extend:DF
3846 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3847 (match_operand:DF 2 "const0_operand" "G,G")])
3848 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3849 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3850 "TARGET_FP"
3851 "@
3852 fcmov%C3 %R4,%R1,%0
3853 fcmov%D3 %R4,%R5,%0"
3854 [(set_attr "type" "fcmov")])
3856 (define_insn "*movdfcc_ext3"
3857 [(set (match_operand:SF 0 "register_operand" "=f,f")
3858 (if_then_else:SF
3859 (match_operator 3 "signed_comparison_operator"
3860 [(float_extend:DF
3861 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3862 (match_operand:DF 2 "const0_operand" "G,G")])
3863 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3864 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3865 "TARGET_FP"
3866 "@
3867 fcmov%C3 %R4,%R1,%0
3868 fcmov%D3 %R4,%R5,%0"
3869 [(set_attr "type" "fcmov")])
3871 (define_insn "*movdfcc_ext4"
3872 [(set (match_operand:DF 0 "register_operand" "=f,f")
3873 (if_then_else:DF
3874 (match_operator 3 "signed_comparison_operator"
3875 [(float_extend:DF
3876 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3877 (match_operand:DF 2 "const0_operand" "G,G")])
3878 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3879 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3880 "TARGET_FP"
3881 "@
3882 fcmov%C3 %R4,%R1,%0
3883 fcmov%D3 %R4,%R5,%0"
3884 [(set_attr "type" "fcmov")])
3886 (define_expand "smaxdf3"
3887 [(set (match_dup 3)
3888 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3889 (match_operand:DF 2 "reg_or_0_operand" "")))
3890 (set (match_operand:DF 0 "register_operand" "")
3891 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3892 (match_dup 1) (match_dup 2)))]
3893 "TARGET_FP"
3894 {
3895 operands[3] = gen_reg_rtx (DFmode);
3896 operands[4] = CONST0_RTX (DFmode);
3897 })
3899 (define_expand "smindf3"
3900 [(set (match_dup 3)
3901 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3902 (match_operand:DF 2 "reg_or_0_operand" "")))
3903 (set (match_operand:DF 0 "register_operand" "")
3904 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3905 (match_dup 1) (match_dup 2)))]
3906 "TARGET_FP"
3907 {
3908 operands[3] = gen_reg_rtx (DFmode);
3909 operands[4] = CONST0_RTX (DFmode);
3910 })
3912 (define_expand "smaxsf3"
3913 [(set (match_dup 3)
3914 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3915 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3916 (set (match_operand:SF 0 "register_operand" "")
3917 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3918 (match_dup 1) (match_dup 2)))]
3919 "TARGET_FP"
3920 {
3921 operands[3] = gen_reg_rtx (DFmode);
3922 operands[4] = CONST0_RTX (DFmode);
3923 })
3925 (define_expand "sminsf3"
3926 [(set (match_dup 3)
3927 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3928 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3929 (set (match_operand:SF 0 "register_operand" "")
3930 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3931 (match_dup 1) (match_dup 2)))]
3932 "TARGET_FP"
3933 {
3934 operands[3] = gen_reg_rtx (DFmode);
3935 operands[4] = CONST0_RTX (DFmode);
3936 })
3938 (define_insn "*fbcc_normal"
3939 [(set (pc)
3940 (if_then_else
3941 (match_operator 1 "signed_comparison_operator"
3942 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3943 (match_operand:DF 3 "const0_operand" "G")])
3944 (label_ref (match_operand 0 "" ""))
3945 (pc)))]
3946 "TARGET_FP"
3947 "fb%C1 %R2,%0"
3948 [(set_attr "type" "fbr")])
3950 (define_insn "*fbcc_ext_normal"
3951 [(set (pc)
3952 (if_then_else
3953 (match_operator 1 "signed_comparison_operator"
3954 [(float_extend:DF
3955 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3956 (match_operand:DF 3 "const0_operand" "G")])
3957 (label_ref (match_operand 0 "" ""))
3958 (pc)))]
3959 "TARGET_FP"
3960 "fb%C1 %R2,%0"
3961 [(set_attr "type" "fbr")])
3962 \f
3963 ;; These are the main define_expand's used to make conditional branches
3964 ;; and compares.
3966 (define_expand "cmpdf"
3967 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3968 (match_operand:DF 1 "reg_or_0_operand" "")))]
3969 "TARGET_FP"
3970 {
3971 alpha_compare.op0 = operands[0];
3972 alpha_compare.op1 = operands[1];
3973 alpha_compare.fp_p = 1;
3974 DONE;
3975 })
3977 (define_expand "cmptf"
3978 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3979 (match_operand:TF 1 "general_operand" "")))]
3980 "TARGET_HAS_XFLOATING_LIBS"
3981 {
3982 alpha_compare.op0 = operands[0];
3983 alpha_compare.op1 = operands[1];
3984 alpha_compare.fp_p = 1;
3985 DONE;
3986 })
3988 (define_expand "cmpdi"
3989 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3990 (match_operand:DI 1 "some_operand" "")))]
3991 ""
3992 {
3993 alpha_compare.op0 = operands[0];
3994 alpha_compare.op1 = operands[1];
3995 alpha_compare.fp_p = 0;
3996 DONE;
3997 })
3999 (define_expand "beq"
4000 [(set (pc)
4001 (if_then_else (match_dup 1)
4002 (label_ref (match_operand 0 "" ""))
4003 (pc)))]
4004 ""
4005 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
4007 (define_expand "bne"
4008 [(set (pc)
4009 (if_then_else (match_dup 1)
4010 (label_ref (match_operand 0 "" ""))
4011 (pc)))]
4012 ""
4013 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
4015 (define_expand "blt"
4016 [(set (pc)
4017 (if_then_else (match_dup 1)
4018 (label_ref (match_operand 0 "" ""))
4019 (pc)))]
4020 ""
4021 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
4023 (define_expand "ble"
4024 [(set (pc)
4025 (if_then_else (match_dup 1)
4026 (label_ref (match_operand 0 "" ""))
4027 (pc)))]
4028 ""
4029 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
4031 (define_expand "bgt"
4032 [(set (pc)
4033 (if_then_else (match_dup 1)
4034 (label_ref (match_operand 0 "" ""))
4035 (pc)))]
4036 ""
4037 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
4039 (define_expand "bge"
4040 [(set (pc)
4041 (if_then_else (match_dup 1)
4042 (label_ref (match_operand 0 "" ""))
4043 (pc)))]
4044 ""
4045 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
4047 (define_expand "bltu"
4048 [(set (pc)
4049 (if_then_else (match_dup 1)
4050 (label_ref (match_operand 0 "" ""))
4051 (pc)))]
4052 ""
4053 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4055 (define_expand "bleu"
4056 [(set (pc)
4057 (if_then_else (match_dup 1)
4058 (label_ref (match_operand 0 "" ""))
4059 (pc)))]
4060 ""
4061 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4063 (define_expand "bgtu"
4064 [(set (pc)
4065 (if_then_else (match_dup 1)
4066 (label_ref (match_operand 0 "" ""))
4067 (pc)))]
4068 ""
4069 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4071 (define_expand "bgeu"
4072 [(set (pc)
4073 (if_then_else (match_dup 1)
4074 (label_ref (match_operand 0 "" ""))
4075 (pc)))]
4076 ""
4077 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4079 (define_expand "bunordered"
4080 [(set (pc)
4081 (if_then_else (match_dup 1)
4082 (label_ref (match_operand 0 "" ""))
4083 (pc)))]
4084 ""
4085 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4087 (define_expand "bordered"
4088 [(set (pc)
4089 (if_then_else (match_dup 1)
4090 (label_ref (match_operand 0 "" ""))
4091 (pc)))]
4092 ""
4093 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4095 (define_expand "seq"
4096 [(set (match_operand:DI 0 "register_operand" "")
4097 (match_dup 1))]
4098 ""
4099 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4101 (define_expand "sne"
4102 [(set (match_operand:DI 0 "register_operand" "")
4103 (match_dup 1))]
4104 ""
4105 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4107 (define_expand "slt"
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (match_dup 1))]
4110 ""
4111 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4113 (define_expand "sle"
4114 [(set (match_operand:DI 0 "register_operand" "")
4115 (match_dup 1))]
4116 ""
4117 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4119 (define_expand "sgt"
4120 [(set (match_operand:DI 0 "register_operand" "")
4121 (match_dup 1))]
4122 ""
4123 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4125 (define_expand "sge"
4126 [(set (match_operand:DI 0 "register_operand" "")
4127 (match_dup 1))]
4128 ""
4129 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4131 (define_expand "sltu"
4132 [(set (match_operand:DI 0 "register_operand" "")
4133 (match_dup 1))]
4134 ""
4135 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4137 (define_expand "sleu"
4138 [(set (match_operand:DI 0 "register_operand" "")
4139 (match_dup 1))]
4140 ""
4141 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4143 (define_expand "sgtu"
4144 [(set (match_operand:DI 0 "register_operand" "")
4145 (match_dup 1))]
4146 ""
4147 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4149 (define_expand "sgeu"
4150 [(set (match_operand:DI 0 "register_operand" "")
4151 (match_dup 1))]
4152 ""
4153 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4155 (define_expand "sunordered"
4156 [(set (match_operand:DI 0 "register_operand" "")
4157 (match_dup 1))]
4158 ""
4159 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4161 (define_expand "sordered"
4162 [(set (match_operand:DI 0 "register_operand" "")
4163 (match_dup 1))]
4164 ""
4165 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4166 \f
4167 ;; These are the main define_expand's used to make conditional moves.
4169 (define_expand "movsicc"
4170 [(set (match_operand:SI 0 "register_operand" "")
4171 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4172 (match_operand:SI 2 "reg_or_8bit_operand" "")
4173 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4174 ""
4175 {
4176 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4177 FAIL;
4178 })
4180 (define_expand "movdicc"
4181 [(set (match_operand:DI 0 "register_operand" "")
4182 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4183 (match_operand:DI 2 "reg_or_8bit_operand" "")
4184 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4185 ""
4186 {
4187 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4188 FAIL;
4189 })
4191 (define_expand "movsfcc"
4192 [(set (match_operand:SF 0 "register_operand" "")
4193 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4194 (match_operand:SF 2 "reg_or_8bit_operand" "")
4195 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4196 ""
4197 {
4198 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4199 FAIL;
4200 })
4202 (define_expand "movdfcc"
4203 [(set (match_operand:DF 0 "register_operand" "")
4204 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4205 (match_operand:DF 2 "reg_or_8bit_operand" "")
4206 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4207 ""
4208 {
4209 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4210 FAIL;
4211 })
4212 \f
4213 ;; These define_split definitions are used in cases when comparisons have
4214 ;; not be stated in the correct way and we need to reverse the second
4215 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4216 ;; comparison that tests the result being reversed. We have one define_split
4217 ;; for each use of a comparison. They do not match valid insns and need
4218 ;; not generate valid insns.
4219 ;;
4220 ;; We can also handle equality comparisons (and inequality comparisons in
4221 ;; cases where the resulting add cannot overflow) by doing an add followed by
4222 ;; a comparison with zero. This is faster since the addition takes one
4223 ;; less cycle than a compare when feeding into a conditional move.
4224 ;; For this case, we also have an SImode pattern since we can merge the add
4225 ;; and sign extend and the order doesn't matter.
4226 ;;
4227 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4228 ;; operation could have been generated.
4230 (define_split
4231 [(set (match_operand:DI 0 "register_operand" "")
4232 (if_then_else:DI
4233 (match_operator 1 "comparison_operator"
4234 [(match_operand:DI 2 "reg_or_0_operand" "")
4235 (match_operand:DI 3 "reg_or_cint_operand" "")])
4236 (match_operand:DI 4 "reg_or_cint_operand" "")
4237 (match_operand:DI 5 "reg_or_cint_operand" "")))
4238 (clobber (match_operand:DI 6 "register_operand" ""))]
4239 "operands[3] != const0_rtx"
4240 [(set (match_dup 6) (match_dup 7))
4241 (set (match_dup 0)
4242 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4243 {
4244 enum rtx_code code = GET_CODE (operands[1]);
4245 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4247 /* If we are comparing for equality with a constant and that constant
4248 appears in the arm when the register equals the constant, use the
4249 register since that is more likely to match (and to produce better code
4250 if both would). */
4252 if (code == EQ && CONST_INT_P (operands[3])
4253 && rtx_equal_p (operands[4], operands[3]))
4254 operands[4] = operands[2];
4256 else if (code == NE && CONST_INT_P (operands[3])
4257 && rtx_equal_p (operands[5], operands[3]))
4258 operands[5] = operands[2];
4260 if (code == NE || code == EQ
4261 || (extended_count (operands[2], DImode, unsignedp) >= 1
4262 && extended_count (operands[3], DImode, unsignedp) >= 1))
4263 {
4264 if (CONST_INT_P (operands[3]))
4265 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4266 GEN_INT (- INTVAL (operands[3])));
4267 else
4268 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4270 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4271 }
4273 else if (code == EQ || code == LE || code == LT
4274 || code == LEU || code == LTU)
4275 {
4276 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4277 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4278 }
4279 else
4280 {
4281 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4282 operands[2], operands[3]);
4283 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4284 }
4285 })
4287 (define_split
4288 [(set (match_operand:DI 0 "register_operand" "")
4289 (if_then_else:DI
4290 (match_operator 1 "comparison_operator"
4291 [(match_operand:SI 2 "reg_or_0_operand" "")
4292 (match_operand:SI 3 "reg_or_cint_operand" "")])
4293 (match_operand:DI 4 "reg_or_8bit_operand" "")
4294 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4295 (clobber (match_operand:DI 6 "register_operand" ""))]
4296 "operands[3] != const0_rtx
4297 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4298 [(set (match_dup 6) (match_dup 7))
4299 (set (match_dup 0)
4300 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4301 {
4302 enum rtx_code code = GET_CODE (operands[1]);
4303 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4304 rtx tem;
4306 if ((code != NE && code != EQ
4307 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4308 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4309 FAIL;
4311 if (CONST_INT_P (operands[3]))
4312 tem = gen_rtx_PLUS (SImode, operands[2],
4313 GEN_INT (- INTVAL (operands[3])));
4314 else
4315 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4317 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4318 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4319 operands[6], const0_rtx);
4320 })
4322 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4324 (define_split
4325 [(set (match_operand 0 "register_operand" "")
4326 (if_then_else (match_operator 1 "signed_comparison_operator"
4327 [(match_operand:DI 2 "reg_or_0_operand" "")
4328 (const_int 0)])
4329 (match_operand 3 "const_int_operand" "")
4330 (match_operand 4 "const_int_operand" "")))]
4331 ""
4332 [(const_int 0)]
4333 {
4334 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4335 operands[2], operands[3], operands[4]))
4336 DONE;
4337 else
4338 FAIL;
4339 })
4341 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4342 ;; Oh well, we match it in movcc, so it must be partially our fault.
4343 (define_split
4344 [(set (match_operand 0 "register_operand" "")
4345 (if_then_else (match_operator 1 "signed_comparison_operator"
4346 [(const_int 0)
4347 (match_operand:DI 2 "reg_or_0_operand" "")])
4348 (match_operand 3 "const_int_operand" "")
4349 (match_operand 4 "const_int_operand" "")))]
4350 ""
4351 [(const_int 0)]
4352 {
4353 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4354 operands[0], operands[2], operands[3],
4355 operands[4]))
4356 DONE;
4357 else
4358 FAIL;
4359 })
4361 (define_insn_and_split "*cmp_sadd_di"
4362 [(set (match_operand:DI 0 "register_operand" "=r")
4363 (plus:DI (if_then_else:DI
4364 (match_operator 1 "alpha_zero_comparison_operator"
4365 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4366 (const_int 0)])
4367 (match_operand:DI 3 "const48_operand" "I")
4368 (const_int 0))
4369 (match_operand:DI 4 "sext_add_operand" "rIO")))
4370 (clobber (match_scratch:DI 5 "=r"))]
4371 ""
4372 "#"
4373 ""
4374 [(set (match_dup 5)
4375 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4376 (set (match_dup 0)
4377 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4378 (match_dup 4)))]
4379 {
4380 if (can_create_pseudo_p ())
4381 operands[5] = gen_reg_rtx (DImode);
4382 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4383 operands[5] = operands[0];
4384 })
4386 (define_insn_and_split "*cmp_sadd_si"
4387 [(set (match_operand:SI 0 "register_operand" "=r")
4388 (plus:SI (if_then_else:SI
4389 (match_operator 1 "alpha_zero_comparison_operator"
4390 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4391 (const_int 0)])
4392 (match_operand:SI 3 "const48_operand" "I")
4393 (const_int 0))
4394 (match_operand:SI 4 "sext_add_operand" "rIO")))
4395 (clobber (match_scratch:SI 5 "=r"))]
4396 ""
4397 "#"
4398 ""
4399 [(set (match_dup 5)
4400 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4401 (set (match_dup 0)
4402 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4403 (match_dup 4)))]
4404 {
4405 if (can_create_pseudo_p ())
4406 operands[5] = gen_reg_rtx (DImode);
4407 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4408 operands[5] = operands[0];
4409 })
4411 (define_insn_and_split "*cmp_sadd_sidi"
4412 [(set (match_operand:DI 0 "register_operand" "=r")
4413 (sign_extend:DI
4414 (plus:SI (if_then_else:SI
4415 (match_operator 1 "alpha_zero_comparison_operator"
4416 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4417 (const_int 0)])
4418 (match_operand:SI 3 "const48_operand" "I")
4419 (const_int 0))
4420 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4421 (clobber (match_scratch:SI 5 "=r"))]
4422 ""
4423 "#"
4424 ""
4425 [(set (match_dup 5)
4426 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4427 (set (match_dup 0)
4428 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4429 (match_dup 4))))]
4430 {
4431 if (can_create_pseudo_p ())
4432 operands[5] = gen_reg_rtx (DImode);
4433 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4434 operands[5] = operands[0];
4435 })
4437 (define_insn_and_split "*cmp_ssub_di"
4438 [(set (match_operand:DI 0 "register_operand" "=r")
4439 (minus:DI (if_then_else:DI
4440 (match_operator 1 "alpha_zero_comparison_operator"
4441 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4442 (const_int 0)])
4443 (match_operand:DI 3 "const48_operand" "I")
4444 (const_int 0))
4445 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4446 (clobber (match_scratch:DI 5 "=r"))]
4447 ""
4448 "#"
4449 ""
4450 [(set (match_dup 5)
4451 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4452 (set (match_dup 0)
4453 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4454 (match_dup 4)))]
4455 {
4456 if (can_create_pseudo_p ())
4457 operands[5] = gen_reg_rtx (DImode);
4458 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4459 operands[5] = operands[0];
4460 })
4462 (define_insn_and_split "*cmp_ssub_si"
4463 [(set (match_operand:SI 0 "register_operand" "=r")
4464 (minus:SI (if_then_else:SI
4465 (match_operator 1 "alpha_zero_comparison_operator"
4466 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4467 (const_int 0)])
4468 (match_operand:SI 3 "const48_operand" "I")
4469 (const_int 0))
4470 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4471 (clobber (match_scratch:SI 5 "=r"))]
4472 ""
4473 "#"
4474 ""
4475 [(set (match_dup 5)
4476 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4477 (set (match_dup 0)
4478 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4479 (match_dup 4)))]
4480 {
4481 if (can_create_pseudo_p ())
4482 operands[5] = gen_reg_rtx (DImode);
4483 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4484 operands[5] = operands[0];
4485 })
4487 (define_insn_and_split "*cmp_ssub_sidi"
4488 [(set (match_operand:DI 0 "register_operand" "=r")
4489 (sign_extend:DI
4490 (minus:SI (if_then_else:SI
4491 (match_operator 1 "alpha_zero_comparison_operator"
4492 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4493 (const_int 0)])
4494 (match_operand:SI 3 "const48_operand" "I")
4495 (const_int 0))
4496 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4497 (clobber (match_scratch:SI 5 "=r"))]
4498 ""
4499 "#"
4500 ""
4501 [(set (match_dup 5)
4502 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4503 (set (match_dup 0)
4504 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4505 (match_dup 4))))]
4506 {
4507 if (can_create_pseudo_p ())
4508 operands[5] = gen_reg_rtx (DImode);
4509 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4510 operands[5] = operands[0];
4511 })
4512 \f
4513 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4514 ;; work differently, so we have different patterns for each.
4516 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4517 ;; call. The CIW contains information about arguments passed in registers
4518 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4519 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4520 ;; in the presence of inlining since the CIWs for calls performed by the
4521 ;; inlined function must be stored in the SSIB of the function it is inlined
4522 ;; into as well. We encode the CIW in an unspec and append it to the list
4523 ;; of the CIWs for the current function only when the instruction for loading
4524 ;; $25 is generated.
4526 (define_expand "call"
4527 [(use (match_operand:DI 0 "" ""))
4528 (use (match_operand 1 "" ""))
4529 (use (match_operand 2 "" ""))
4530 (use (match_operand 3 "" ""))]
4531 ""
4532 {
4533 if (TARGET_ABI_WINDOWS_NT)
4534 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4535 else if (TARGET_ABI_OPEN_VMS)
4536 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4537 else if (TARGET_ABI_UNICOSMK)
4538 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4539 else
4540 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4541 DONE;
4542 })
4544 (define_expand "sibcall"
4545 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4546 (match_operand 1 "" ""))
4547 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4548 "TARGET_ABI_OSF"
4549 {
4550 gcc_assert (MEM_P (operands[0]));
4551 operands[0] = XEXP (operands[0], 0);
4552 })
4554 (define_expand "call_osf"
4555 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4556 (match_operand 1 "" ""))
4557 (use (reg:DI 29))
4558 (clobber (reg:DI 26))])]
4559 ""
4560 {
4561 gcc_assert (MEM_P (operands[0]));
4563 operands[0] = XEXP (operands[0], 0);
4564 if (! call_operand (operands[0], Pmode))
4565 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4566 })
4568 (define_expand "call_nt"
4569 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4570 (match_operand 1 "" ""))
4571 (clobber (reg:DI 26))])]
4572 ""
4573 {
4574 gcc_assert (MEM_P (operands[0]));
4576 operands[0] = XEXP (operands[0], 0);
4577 if (GET_CODE (operands[0]) != SYMBOL_REF && !REG_P (operands[0]))
4578 operands[0] = force_reg (DImode, operands[0]);
4579 })
4581 ;; Calls on Unicos/Mk are always indirect.
4582 ;; op 0: symbol ref for called function
4583 ;; op 1: CIW for $25 represented by an unspec
4585 (define_expand "call_umk"
4586 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4587 (match_operand 1 "" ""))
4588 (use (reg:DI 25))
4589 (clobber (reg:DI 26))])]
4590 ""
4591 {
4592 gcc_assert (MEM_P (operands[0]));
4594 /* Always load the address of the called function into a register;
4595 load the CIW in $25. */
4597 operands[0] = XEXP (operands[0], 0);
4598 if (!REG_P (operands[0]))
4599 operands[0] = force_reg (DImode, operands[0]);
4601 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4602 })
4604 ;;
4605 ;; call openvms/alpha
4606 ;; op 0: symbol ref for called function
4607 ;; op 1: next_arg_reg (argument information value for R25)
4608 ;;
4609 (define_expand "call_vms"
4610 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4611 (match_operand 1 "" ""))
4612 (use (match_dup 2))
4613 (use (reg:DI 25))
4614 (use (reg:DI 26))
4615 (clobber (reg:DI 27))])]
4616 ""
4617 {
4618 gcc_assert (MEM_P (operands[0]));
4620 operands[0] = XEXP (operands[0], 0);
4622 /* Always load AI with argument information, then handle symbolic and
4623 indirect call differently. Load RA and set operands[2] to PV in
4624 both cases. */
4626 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4627 if (GET_CODE (operands[0]) == SYMBOL_REF)
4628 {
4629 alpha_need_linkage (XSTR (operands[0], 0), 0);
4631 operands[2] = const0_rtx;
4632 }
4633 else
4634 {
4635 emit_move_insn (gen_rtx_REG (Pmode, 26),
4636 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4637 operands[2] = operands[0];
4638 }
4640 })
4642 (define_expand "call_value"
4643 [(use (match_operand 0 "" ""))
4644 (use (match_operand:DI 1 "" ""))
4645 (use (match_operand 2 "" ""))
4646 (use (match_operand 3 "" ""))
4647 (use (match_operand 4 "" ""))]
4648 ""
4649 {
4650 if (TARGET_ABI_WINDOWS_NT)
4651 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4652 else if (TARGET_ABI_OPEN_VMS)
4653 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4654 operands[3]));
4655 else if (TARGET_ABI_UNICOSMK)
4656 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4657 operands[3]));
4658 else
4659 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4660 operands[2]));
4661 DONE;
4662 })
4664 (define_expand "sibcall_value"
4665 [(parallel [(set (match_operand 0 "" "")
4666 (call (mem:DI (match_operand 1 "" ""))
4667 (match_operand 2 "" "")))
4668 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4669 "TARGET_ABI_OSF"
4670 {
4671 gcc_assert (MEM_P (operands[1]));
4672 operands[1] = XEXP (operands[1], 0);
4673 })
4675 (define_expand "call_value_osf"
4676 [(parallel [(set (match_operand 0 "" "")
4677 (call (mem:DI (match_operand 1 "" ""))
4678 (match_operand 2 "" "")))
4679 (use (reg:DI 29))
4680 (clobber (reg:DI 26))])]
4681 ""
4682 {
4683 gcc_assert (MEM_P (operands[1]));
4685 operands[1] = XEXP (operands[1], 0);
4686 if (! call_operand (operands[1], Pmode))
4687 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4688 })
4690 (define_expand "call_value_nt"
4691 [(parallel [(set (match_operand 0 "" "")
4692 (call (mem:DI (match_operand 1 "" ""))
4693 (match_operand 2 "" "")))
4694 (clobber (reg:DI 26))])]
4695 ""
4696 {
4697 gcc_assert (MEM_P (operands[1]));
4699 operands[1] = XEXP (operands[1], 0);
4700 if (GET_CODE (operands[1]) != SYMBOL_REF && !REG_P (operands[1]))
4701 operands[1] = force_reg (DImode, operands[1]);
4702 })
4704 (define_expand "call_value_vms"
4705 [(parallel [(set (match_operand 0 "" "")
4706 (call (mem:DI (match_operand:DI 1 "" ""))
4707 (match_operand 2 "" "")))
4708 (use (match_dup 3))
4709 (use (reg:DI 25))
4710 (use (reg:DI 26))
4711 (clobber (reg:DI 27))])]
4712 ""
4713 {
4714 gcc_assert (MEM_P (operands[1]));
4716 operands[1] = XEXP (operands[1], 0);
4718 /* Always load AI with argument information, then handle symbolic and
4719 indirect call differently. Load RA and set operands[3] to PV in
4720 both cases. */
4722 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4723 if (GET_CODE (operands[1]) == SYMBOL_REF)
4724 {
4725 alpha_need_linkage (XSTR (operands[1], 0), 0);
4727 operands[3] = const0_rtx;
4728 }
4729 else
4730 {
4731 emit_move_insn (gen_rtx_REG (Pmode, 26),
4732 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4733 operands[3] = operands[1];
4734 }
4735 })
4737 (define_expand "call_value_umk"
4738 [(parallel [(set (match_operand 0 "" "")
4739 (call (mem:DI (match_operand 1 "" ""))
4740 (match_operand 2 "" "")))
4741 (use (reg:DI 25))
4742 (clobber (reg:DI 26))])]
4743 ""
4744 {
4745 gcc_assert (MEM_P (operands[1]));
4747 operands[1] = XEXP (operands[1], 0);
4748 if (!REG_P (operands[1]))
4749 operands[1] = force_reg (DImode, operands[1]);
4751 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4752 })
4754 (define_insn "*call_osf_1_er_noreturn"
4755 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4756 (match_operand 1 "" ""))
4757 (use (reg:DI 29))
4758 (clobber (reg:DI 26))]
4759 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4760 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4761 "@
4762 jsr $26,($27),0
4763 bsr $26,%0\t\t!samegp
4764 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
4765 [(set_attr "type" "jsr")
4766 (set_attr "length" "*,*,8")])
4768 (define_insn "*call_osf_1_er"
4769 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4770 (match_operand 1 "" ""))
4771 (use (reg:DI 29))
4772 (clobber (reg:DI 26))]
4773 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4774 "@
4775 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4776 bsr $26,%0\t\t!samegp
4777 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4778 [(set_attr "type" "jsr")
4779 (set_attr "length" "12,*,16")])
4781 ;; We must use peep2 instead of a split because we need accurate life
4782 ;; information for $gp. Consider the case of { bar(); while (1); }.
4783 (define_peephole2
4784 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4785 (match_operand 1 "" ""))
4786 (use (reg:DI 29))
4787 (clobber (reg:DI 26))])]
4788 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4789 && ! samegp_function_operand (operands[0], Pmode)
4790 && (peep2_regno_dead_p (1, 29)
4791 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4792 [(parallel [(call (mem:DI (match_dup 2))
4793 (match_dup 1))
4794 (use (reg:DI 29))
4795 (use (match_dup 0))
4796 (use (match_dup 3))
4797 (clobber (reg:DI 26))])]
4798 {
4799 if (CONSTANT_P (operands[0]))
4800 {
4801 operands[2] = gen_rtx_REG (Pmode, 27);
4802 operands[3] = GEN_INT (alpha_next_sequence_number++);
4803 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4804 operands[0], operands[3]));
4805 }
4806 else
4807 {
4808 operands[2] = operands[0];
4809 operands[0] = const0_rtx;
4810 operands[3] = const0_rtx;
4811 }
4812 })
4814 (define_peephole2
4815 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4816 (match_operand 1 "" ""))
4817 (use (reg:DI 29))
4818 (clobber (reg:DI 26))])]
4819 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4820 && ! samegp_function_operand (operands[0], Pmode)
4821 && ! (peep2_regno_dead_p (1, 29)
4822 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4823 [(parallel [(call (mem:DI (match_dup 2))
4824 (match_dup 1))
4825 (set (match_dup 5)
4826 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
4827 (use (match_dup 0))
4828 (use (match_dup 4))
4829 (clobber (reg:DI 26))])
4830 (set (match_dup 5)
4831 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
4832 {
4833 if (CONSTANT_P (operands[0]))
4834 {
4835 operands[2] = gen_rtx_REG (Pmode, 27);
4836 operands[4] = GEN_INT (alpha_next_sequence_number++);
4837 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4838 operands[0], operands[4]));
4839 }
4840 else
4841 {
4842 operands[2] = operands[0];
4843 operands[0] = const0_rtx;
4844 operands[4] = const0_rtx;
4845 }
4846 operands[3] = GEN_INT (alpha_next_sequence_number++);
4847 operands[5] = pic_offset_table_rtx;
4848 })
4850 (define_insn "*call_osf_2_er_nogp"
4851 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4852 (match_operand 1 "" ""))
4853 (use (reg:DI 29))
4854 (use (match_operand 2 "" ""))
4855 (use (match_operand 3 "const_int_operand" ""))
4856 (clobber (reg:DI 26))]
4857 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4858 "jsr $26,(%0),%2%J3"
4859 [(set_attr "type" "jsr")])
4861 (define_insn "*call_osf_2_er"
4862 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4863 (match_operand 1 "" ""))
4864 (set (reg:DI 29)
4865 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")]
4866 UNSPEC_LDGP1))
4867 (use (match_operand 2 "" ""))
4868 (use (match_operand 3 "const_int_operand" ""))
4869 (clobber (reg:DI 26))]
4870 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4871 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
4872 [(set_attr "type" "jsr")
4873 (set_attr "cannot_copy" "true")
4874 (set_attr "length" "8")])
4876 (define_insn "*call_osf_1_noreturn"
4877 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4878 (match_operand 1 "" ""))
4879 (use (reg:DI 29))
4880 (clobber (reg:DI 26))]
4881 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4882 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4883 "@
4884 jsr $26,($27),0
4885 bsr $26,$%0..ng
4886 jsr $26,%0"
4887 [(set_attr "type" "jsr")
4888 (set_attr "length" "*,*,8")])
4890 (define_insn "*call_osf_1"
4891 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4892 (match_operand 1 "" ""))
4893 (use (reg:DI 29))
4894 (clobber (reg:DI 26))]
4895 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4896 "@
4897 jsr $26,($27),0\;ldgp $29,0($26)
4898 bsr $26,$%0..ng
4899 jsr $26,%0\;ldgp $29,0($26)"
4900 [(set_attr "type" "jsr")
4901 (set_attr "length" "12,*,16")])
4903 (define_insn "*sibcall_osf_1_er"
4904 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4905 (match_operand 1 "" ""))
4906 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4907 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4908 "@
4909 br $31,%0\t\t!samegp
4910 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4911 [(set_attr "type" "jsr")
4912 (set_attr "length" "*,8")])
4914 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4915 ;; doesn't do what we want.
4916 (define_insn "*sibcall_osf_1"
4917 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4918 (match_operand 1 "" ""))
4919 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4920 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4921 "@
4922 br $31,$%0..ng
4923 lda $27,%0\;jmp $31,($27),%0"
4924 [(set_attr "type" "jsr")
4925 (set_attr "length" "*,8")])
4927 (define_insn "*call_nt_1"
4928 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4929 (match_operand 1 "" ""))
4930 (clobber (reg:DI 26))]
4931 "TARGET_ABI_WINDOWS_NT"
4932 "@
4933 jsr $26,(%0)
4934 bsr $26,%0
4935 jsr $26,%0"
4936 [(set_attr "type" "jsr")
4937 (set_attr "length" "*,*,12")])
4939 ; GAS relies on the order and position of instructions output below in order
4940 ; to generate relocs for VMS link to potentially optimize the call.
4941 ; Please do not molest.
4942 (define_insn "*call_vms_1"
4943 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4944 (match_operand 1 "" ""))
4945 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4946 (use (reg:DI 25))
4947 (use (reg:DI 26))
4948 (clobber (reg:DI 27))]
4949 "TARGET_ABI_OPEN_VMS"
4950 {
4951 switch (which_alternative)
4952 {
4953 case 0:
4954 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4955 case 1:
4956 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4957 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4958 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4959 default:
4960 gcc_unreachable ();
4961 }
4962 }
4963 [(set_attr "type" "jsr")
4964 (set_attr "length" "12,16")])
4966 (define_insn "*call_umk_1"
4967 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4968 (match_operand 1 "" ""))
4969 (use (reg:DI 25))
4970 (clobber (reg:DI 26))]
4971 "TARGET_ABI_UNICOSMK"
4972 "jsr $26,(%0)"
4973 [(set_attr "type" "jsr")])
4975 ;; Call subroutine returning any type.
4977 (define_expand "untyped_call"
4978 [(parallel [(call (match_operand 0 "" "")
4979 (const_int 0))
4980 (match_operand 1 "" "")
4981 (match_operand 2 "" "")])]
4982 ""
4983 {
4984 int i;
4986 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4988 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4989 {
4990 rtx set = XVECEXP (operands[2], 0, i);
4991 emit_move_insn (SET_DEST (set), SET_SRC (set));
4992 }
4994 /* The optimizer does not know that the call sets the function value
4995 registers we stored in the result block. We avoid problems by
4996 claiming that all hard registers are used and clobbered at this
4997 point. */
4998 emit_insn (gen_blockage ());
5000 DONE;
5001 })
5003 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5004 ;; all of memory. This blocks insns from being moved across this point.
5006 (define_insn "blockage"
5007 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5008 ""
5009 ""
5010 [(set_attr "length" "0")
5011 (set_attr "type" "none")])
5013 (define_insn "jump"
5014 [(set (pc)
5015 (label_ref (match_operand 0 "" "")))]
5016 ""
5017 "br $31,%l0"
5018 [(set_attr "type" "ibr")])
5020 (define_expand "return"
5021 [(return)]
5022 "direct_return ()"
5023 "")
5025 (define_insn "*return_internal"
5026 [(return)]
5027 "reload_completed"
5028 "ret $31,($26),1"
5029 [(set_attr "type" "ibr")])
5031 (define_insn "indirect_jump"
5032 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5033 ""
5034 "jmp $31,(%0),0"
5035 [(set_attr "type" "ibr")])
5037 (define_expand "tablejump"
5038 [(parallel [(set (pc)
5039 (match_operand 0 "register_operand" ""))
5040 (use (label_ref:DI (match_operand 1 "" "")))])]
5041 ""
5042 {
5043 if (TARGET_ABI_WINDOWS_NT)
5044 {
5045 rtx dest = gen_reg_rtx (DImode);
5046 emit_insn (gen_extendsidi2 (dest, operands[0]));
5047 operands[0] = dest;
5048 }
5049 else if (TARGET_ABI_OSF)
5050 {
5051 rtx dest = gen_reg_rtx (DImode);
5052 emit_insn (gen_extendsidi2 (dest, operands[0]));
5053 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5054 operands[0] = dest;
5055 }
5056 })
5058 (define_insn "*tablejump_osf_nt_internal"
5059 [(set (pc)
5060 (match_operand:DI 0 "register_operand" "r"))
5061 (use (label_ref:DI (match_operand 1 "" "")))]
5062 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5063 && alpha_tablejump_addr_vec (insn)"
5064 {
5065 operands[2] = alpha_tablejump_best_label (insn);
5066 return "jmp $31,(%0),%2";
5067 }
5068 [(set_attr "type" "ibr")])
5070 (define_insn "*tablejump_internal"
5071 [(set (pc)
5072 (match_operand:DI 0 "register_operand" "r"))
5073 (use (label_ref (match_operand 1 "" "")))]
5074 ""
5075 "jmp $31,(%0),0"
5076 [(set_attr "type" "ibr")])
5078 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5079 ;; want to have to include pal.h in our .s file.
5080 (define_insn "imb"
5081 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5082 ""
5083 "call_pal 0x86"
5084 [(set_attr "type" "callpal")])
5086 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5087 ;; NT does not document anything at 0x81 -- presumably it would generate
5088 ;; the equivalent of SIGILL, but this isn't that important.
5089 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5090 (define_insn "trap"
5091 [(trap_if (const_int 1) (const_int 0))]
5092 "!TARGET_ABI_WINDOWS_NT"
5093 "call_pal 0x81"
5094 [(set_attr "type" "callpal")])
5096 ;; For userland, we load the thread pointer from the TCB.
5097 ;; For the kernel, we load the per-cpu private value.
5099 (define_insn "load_tp"
5100 [(set (match_operand:DI 0 "register_operand" "=v")
5101 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5102 "TARGET_ABI_OSF"
5103 {
5104 if (TARGET_TLS_KERNEL)
5105 return "call_pal 0x32";
5106 else
5107 return "call_pal 0x9e";
5108 }
5109 [(set_attr "type" "callpal")])
5111 ;; For completeness, and possibly a __builtin function, here's how to
5112 ;; set the thread pointer. Since we don't describe enough of this
5113 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5114 ;; not much point in creating an R16_REG register class.
5116 (define_expand "set_tp"
5117 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5118 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5119 "TARGET_ABI_OSF"
5120 "")
5122 (define_insn "*set_tp"
5123 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5124 "TARGET_ABI_OSF"
5125 {
5126 if (TARGET_TLS_KERNEL)
5127 return "call_pal 0x31";
5128 else
5129 return "call_pal 0x9f";
5130 }
5131 [(set_attr "type" "callpal")])
5132 \f
5133 ;; Finally, we have the basic data motion insns. The byte and word insns
5134 ;; are done via define_expand. Start with the floating-point insns, since
5135 ;; they are simpler.
5137 (define_insn "*movsf_nofix"
5138 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5139 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5140 "TARGET_FPREGS && ! TARGET_FIX
5141 && (register_operand (operands[0], SFmode)
5142 || reg_or_0_operand (operands[1], SFmode))"
5143 "@
5144 cpys %R1,%R1,%0
5145 ld%, %0,%1
5146 bis $31,%r1,%0
5147 ldl %0,%1
5148 st%, %R1,%0
5149 stl %r1,%0"
5150 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5152 (define_insn "*movsf_fix"
5153 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5154 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5155 "TARGET_FPREGS && TARGET_FIX
5156 && (register_operand (operands[0], SFmode)
5157 || reg_or_0_operand (operands[1], SFmode))"
5158 "@
5159 cpys %R1,%R1,%0
5160 ld%, %0,%1
5161 bis $31,%r1,%0
5162 ldl %0,%1
5163 st%, %R1,%0
5164 stl %r1,%0
5165 itofs %1,%0
5166 ftois %1,%0"
5167 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5169 (define_insn "*movsf_nofp"
5170 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5171 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5172 "! TARGET_FPREGS
5173 && (register_operand (operands[0], SFmode)
5174 || reg_or_0_operand (operands[1], SFmode))"
5175 "@
5176 bis $31,%r1,%0
5177 ldl %0,%1
5178 stl %r1,%0"
5179 [(set_attr "type" "ilog,ild,ist")])
5181 (define_insn "*movdf_nofix"
5182 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5183 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5184 "TARGET_FPREGS && ! TARGET_FIX
5185 && (register_operand (operands[0], DFmode)
5186 || reg_or_0_operand (operands[1], DFmode))"
5187 "@
5188 cpys %R1,%R1,%0
5189 ld%- %0,%1
5190 bis $31,%r1,%0
5191 ldq %0,%1
5192 st%- %R1,%0
5193 stq %r1,%0"
5194 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5196 (define_insn "*movdf_fix"
5197 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5198 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5199 "TARGET_FPREGS && TARGET_FIX
5200 && (register_operand (operands[0], DFmode)
5201 || reg_or_0_operand (operands[1], DFmode))"
5202 "@
5203 cpys %R1,%R1,%0
5204 ld%- %0,%1
5205 bis $31,%r1,%0
5206 ldq %0,%1
5207 st%- %R1,%0
5208 stq %r1,%0
5209 itoft %1,%0
5210 ftoit %1,%0"
5211 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5213 (define_insn "*movdf_nofp"
5214 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5215 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5216 "! TARGET_FPREGS
5217 && (register_operand (operands[0], DFmode)
5218 || reg_or_0_operand (operands[1], DFmode))"
5219 "@
5220 bis $31,%r1,%0
5221 ldq %0,%1
5222 stq %r1,%0"
5223 [(set_attr "type" "ilog,ild,ist")])
5225 ;; Subregs suck for register allocation. Pretend we can move TFmode
5226 ;; data between general registers until after reload.
5228 (define_insn_and_split "*movtf_internal"
5229 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5230 (match_operand:TF 1 "input_operand" "roG,rG"))]
5231 "register_operand (operands[0], TFmode)
5232 || reg_or_0_operand (operands[1], TFmode)"
5233 "#"
5234 "reload_completed"
5235 [(set (match_dup 0) (match_dup 2))
5236 (set (match_dup 1) (match_dup 3))]
5237 {
5238 alpha_split_tmode_pair (operands, TFmode, true);
5239 })
5241 (define_expand "movsf"
5242 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5243 (match_operand:SF 1 "general_operand" ""))]
5244 ""
5245 {
5246 if (MEM_P (operands[0])
5247 && ! reg_or_0_operand (operands[1], SFmode))
5248 operands[1] = force_reg (SFmode, operands[1]);
5249 })
5251 (define_expand "movdf"
5252 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5253 (match_operand:DF 1 "general_operand" ""))]
5254 ""
5255 {
5256 if (MEM_P (operands[0])
5257 && ! reg_or_0_operand (operands[1], DFmode))
5258 operands[1] = force_reg (DFmode, operands[1]);
5259 })
5261 (define_expand "movtf"
5262 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5263 (match_operand:TF 1 "general_operand" ""))]
5264 ""
5265 {
5266 if (MEM_P (operands[0])
5267 && ! reg_or_0_operand (operands[1], TFmode))
5268 operands[1] = force_reg (TFmode, operands[1]);
5269 })
5271 (define_insn "*movsi"
5272 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5273 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5274 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5275 && (register_operand (operands[0], SImode)
5276 || reg_or_0_operand (operands[1], SImode))"
5277 "@
5278 bis $31,%r1,%0
5279 lda %0,%1($31)
5280 ldah %0,%h1($31)
5281 #
5282 ldl %0,%1
5283 stl %r1,%0"
5284 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5286 (define_insn "*movsi_nt_vms"
5287 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5288 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5289 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5290 && (register_operand (operands[0], SImode)
5291 || reg_or_0_operand (operands[1], SImode))"
5292 "@
5293 bis $31,%1,%0
5294 lda %0,%1
5295 ldah %0,%h1
5296 lda %0,%1
5297 #
5298 ldl %0,%1
5299 stl %r1,%0"
5300 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5302 (define_insn "*movhi_nobwx"
5303 [(set (match_operand:HI 0 "register_operand" "=r,r")
5304 (match_operand:HI 1 "input_operand" "rJ,n"))]
5305 "! TARGET_BWX
5306 && (register_operand (operands[0], HImode)
5307 || register_operand (operands[1], HImode))"
5308 "@
5309 bis $31,%r1,%0
5310 lda %0,%L1($31)"
5311 [(set_attr "type" "ilog,iadd")])
5313 (define_insn "*movhi_bwx"
5314 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5315 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5316 "TARGET_BWX
5317 && (register_operand (operands[0], HImode)
5318 || reg_or_0_operand (operands[1], HImode))"
5319 "@
5320 bis $31,%r1,%0
5321 lda %0,%L1($31)
5322 ldwu %0,%1
5323 stw %r1,%0"
5324 [(set_attr "type" "ilog,iadd,ild,ist")])
5326 (define_insn "*movqi_nobwx"
5327 [(set (match_operand:QI 0 "register_operand" "=r,r")
5328 (match_operand:QI 1 "input_operand" "rJ,n"))]
5329 "! TARGET_BWX
5330 && (register_operand (operands[0], QImode)
5331 || register_operand (operands[1], QImode))"
5332 "@
5333 bis $31,%r1,%0
5334 lda %0,%L1($31)"
5335 [(set_attr "type" "ilog,iadd")])
5337 (define_insn "*movqi_bwx"
5338 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5339 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5340 "TARGET_BWX
5341 && (register_operand (operands[0], QImode)
5342 || reg_or_0_operand (operands[1], QImode))"
5343 "@
5344 bis $31,%r1,%0
5345 lda %0,%L1($31)
5346 ldbu %0,%1
5347 stb %r1,%0"
5348 [(set_attr "type" "ilog,iadd,ild,ist")])
5350 ;; We do two major things here: handle mem->mem and construct long
5351 ;; constants.
5353 (define_expand "movsi"
5354 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5355 (match_operand:SI 1 "general_operand" ""))]
5356 ""
5357 {
5358 if (alpha_expand_mov (SImode, operands))
5359 DONE;
5360 })
5362 ;; Split a load of a large constant into the appropriate two-insn
5363 ;; sequence.
5365 (define_split
5366 [(set (match_operand:SI 0 "register_operand" "")
5367 (match_operand:SI 1 "non_add_const_operand" ""))]
5368 ""
5369 [(const_int 0)]
5370 {
5371 if (alpha_split_const_mov (SImode, operands))
5372 DONE;
5373 else
5374 FAIL;
5375 })
5377 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5378 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5379 ;; optimizations. If the symbolic operand is a label_ref, generate
5380 ;; REG_LABEL_OPERAND notes and update LABEL_NUSES because this is not done
5381 ;; automatically. Labels may be incorrectly deleted if we don't do this.
5382 ;;
5383 ;; Describing what the individual instructions do correctly is too complicated
5384 ;; so use UNSPECs for each of the three parts of an address.
5386 (define_split
5387 [(set (match_operand:DI 0 "register_operand" "")
5388 (match_operand:DI 1 "symbolic_operand" ""))]
5389 "TARGET_ABI_UNICOSMK && reload_completed"
5390 [(const_int 0)]
5391 {
5392 rtx insn1, insn2, insn3;
5394 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5395 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5396 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5397 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5398 set_unique_reg_note (insn3, REG_EQUAL, operands[1]);
5400 if (GET_CODE (operands[1]) == LABEL_REF)
5401 {
5402 rtx label;
5404 label = XEXP (operands[1], 0);
5405 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5406 REG_NOTES (insn1));
5407 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5408 REG_NOTES (insn2));
5409 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5410 REG_NOTES (insn3));
5411 LABEL_NUSES (label) += 3;
5412 }
5413 DONE;
5414 })
5416 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5418 (define_insn "umk_laum"
5419 [(set (match_operand:DI 0 "register_operand" "=r")
5420 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5421 UNSPEC_UMK_LAUM))]
5422 "TARGET_ABI_UNICOSMK"
5423 "laum %r0,%t1($31)"
5424 [(set_attr "type" "iadd")])
5426 (define_insn "umk_lalm"
5427 [(set (match_operand:DI 0 "register_operand" "=r")
5428 (plus:DI (match_operand:DI 1 "register_operand" "r")
5429 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5430 UNSPEC_UMK_LALM)))]
5431 "TARGET_ABI_UNICOSMK"
5432 "lalm %r0,%t2(%r1)"
5433 [(set_attr "type" "iadd")])
5435 (define_insn "umk_lal"
5436 [(set (match_operand:DI 0 "register_operand" "=r")
5437 (plus:DI (match_operand:DI 1 "register_operand" "r")
5438 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5439 UNSPEC_UMK_LAL)))]
5440 "TARGET_ABI_UNICOSMK"
5441 "lal %r0,%t2(%r1)"
5442 [(set_attr "type" "iadd")])
5444 ;; Add a new call information word to the current function's list of CIWs
5445 ;; and load its index into $25. Doing it here ensures that the CIW will be
5446 ;; associated with the correct function even in the presence of inlining.
5448 (define_insn "*umk_load_ciw"
5449 [(set (reg:DI 25)
5450 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5451 "TARGET_ABI_UNICOSMK"
5452 {
5453 operands[0] = unicosmk_add_call_info_word (operands[0]);
5454 return "lda $25,%0";
5455 }
5456 [(set_attr "type" "iadd")])
5458 (define_insn "*movdi_er_low_l"
5459 [(set (match_operand:DI 0 "register_operand" "=r")
5460 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5461 (match_operand:DI 2 "local_symbolic_operand" "")))]
5462 "TARGET_EXPLICIT_RELOCS"
5463 {
5464 if (true_regnum (operands[1]) == 29)
5465 return "lda %0,%2(%1)\t\t!gprel";
5466 else
5467 return "lda %0,%2(%1)\t\t!gprellow";
5468 }
5469 [(set_attr "usegp" "yes")])
5471 (define_split
5472 [(set (match_operand:DI 0 "register_operand" "")
5473 (match_operand:DI 1 "small_symbolic_operand" ""))]
5474 "TARGET_EXPLICIT_RELOCS && reload_completed"
5475 [(set (match_dup 0)
5476 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5477 "operands[2] = pic_offset_table_rtx;")
5479 (define_split
5480 [(set (match_operand:DI 0 "register_operand" "")
5481 (match_operand:DI 1 "local_symbolic_operand" ""))]
5482 "TARGET_EXPLICIT_RELOCS && reload_completed"
5483 [(set (match_dup 0)
5484 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5485 (set (match_dup 0)
5486 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5487 "operands[2] = pic_offset_table_rtx;")
5489 (define_split
5490 [(match_operand 0 "some_small_symbolic_operand" "")]
5491 ""
5492 [(match_dup 0)]
5493 "operands[0] = split_small_symbolic_operand (operands[0]);")
5495 ;; Accepts any symbolic, not just global, since function calls that
5496 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5497 (define_insn "movdi_er_high_g"
5498 [(set (match_operand:DI 0 "register_operand" "=r")
5499 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5500 (match_operand:DI 2 "symbolic_operand" "")
5501 (match_operand 3 "const_int_operand" "")]
5502 UNSPEC_LITERAL))]
5503 "TARGET_EXPLICIT_RELOCS"
5504 {
5505 if (INTVAL (operands[3]) == 0)
5506 return "ldq %0,%2(%1)\t\t!literal";
5507 else
5508 return "ldq %0,%2(%1)\t\t!literal!%3";
5509 }
5510 [(set_attr "type" "ldsym")])
5512 (define_split
5513 [(set (match_operand:DI 0 "register_operand" "")
5514 (match_operand:DI 1 "global_symbolic_operand" ""))]
5515 "TARGET_EXPLICIT_RELOCS && reload_completed"
5516 [(set (match_dup 0)
5517 (unspec:DI [(match_dup 2)
5518 (match_dup 1)
5519 (const_int 0)] UNSPEC_LITERAL))]
5520 "operands[2] = pic_offset_table_rtx;")
5522 (define_insn "movdi_er_tlsgd"
5523 [(set (match_operand:DI 0 "register_operand" "=r")
5524 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5525 (match_operand:DI 2 "symbolic_operand" "")
5526 (match_operand 3 "const_int_operand" "")]
5527 UNSPEC_TLSGD))]
5528 "HAVE_AS_TLS"
5529 {
5530 if (INTVAL (operands[3]) == 0)
5531 return "lda %0,%2(%1)\t\t!tlsgd";
5532 else
5533 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5534 })
5536 (define_insn "movdi_er_tlsldm"
5537 [(set (match_operand:DI 0 "register_operand" "=r")
5538 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5539 (match_operand 2 "const_int_operand" "")]
5540 UNSPEC_TLSLDM))]
5541 "HAVE_AS_TLS"
5542 {
5543 if (INTVAL (operands[2]) == 0)
5544 return "lda %0,%&(%1)\t\t!tlsldm";
5545 else
5546 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5547 })
5549 (define_insn "*movdi_er_gotdtp"
5550 [(set (match_operand:DI 0 "register_operand" "=r")
5551 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5552 (match_operand:DI 2 "symbolic_operand" "")]
5553 UNSPEC_DTPREL))]
5554 "HAVE_AS_TLS"
5555 "ldq %0,%2(%1)\t\t!gotdtprel"
5556 [(set_attr "type" "ild")
5557 (set_attr "usegp" "yes")])
5559 (define_split
5560 [(set (match_operand:DI 0 "register_operand" "")
5561 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5562 "HAVE_AS_TLS && reload_completed"
5563 [(set (match_dup 0)
5564 (unspec:DI [(match_dup 2)
5565 (match_dup 1)] UNSPEC_DTPREL))]
5566 {
5567 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5568 operands[2] = pic_offset_table_rtx;
5569 })
5571 (define_insn "*movdi_er_gottp"
5572 [(set (match_operand:DI 0 "register_operand" "=r")
5573 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5574 (match_operand:DI 2 "symbolic_operand" "")]
5575 UNSPEC_TPREL))]
5576 "HAVE_AS_TLS"
5577 "ldq %0,%2(%1)\t\t!gottprel"
5578 [(set_attr "type" "ild")
5579 (set_attr "usegp" "yes")])
5581 (define_split
5582 [(set (match_operand:DI 0 "register_operand" "")
5583 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5584 "HAVE_AS_TLS && reload_completed"
5585 [(set (match_dup 0)
5586 (unspec:DI [(match_dup 2)
5587 (match_dup 1)] UNSPEC_TPREL))]
5588 {
5589 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5590 operands[2] = pic_offset_table_rtx;
5591 })
5593 (define_insn "*movdi_er_nofix"
5594 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5595 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5596 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5597 && (register_operand (operands[0], DImode)
5598 || reg_or_0_operand (operands[1], DImode))"
5599 "@
5600 mov %r1,%0
5601 lda %0,%1($31)
5602 ldah %0,%h1($31)
5603 #
5604 #
5605 #
5606 ldq%A1 %0,%1
5607 stq%A0 %r1,%0
5608 fmov %R1,%0
5609 ldt %0,%1
5610 stt %R1,%0"
5611 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5612 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5614 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5615 ;; have been split up by the rules above but we shouldn't reject the
5616 ;; possibility of them getting through.
5618 (define_insn "*movdi_nofix"
5619 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5620 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5621 "! TARGET_FIX
5622 && (register_operand (operands[0], DImode)
5623 || reg_or_0_operand (operands[1], DImode))"
5624 "@
5625 bis $31,%r1,%0
5626 lda %0,%1($31)
5627 ldah %0,%h1($31)
5628 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5629 lda %0,%1
5630 #
5631 ldq%A1 %0,%1
5632 stq%A0 %r1,%0
5633 cpys %R1,%R1,%0
5634 ldt %0,%1
5635 stt %R1,%0"
5636 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5637 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5639 (define_insn "*movdi_er_fix"
5640 [(set (match_operand:DI 0 "nonimmediate_operand"
5641 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5642 (match_operand:DI 1 "input_operand"
5643 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5644 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5645 && (register_operand (operands[0], DImode)
5646 || reg_or_0_operand (operands[1], DImode))"
5647 "@
5648 mov %r1,%0
5649 lda %0,%1($31)
5650 ldah %0,%h1($31)
5651 #
5652 #
5653 #
5654 ldq%A1 %0,%1
5655 stq%A0 %r1,%0
5656 fmov %R1,%0
5657 ldt %0,%1
5658 stt %R1,%0
5659 ftoit %1,%0
5660 itoft %1,%0"
5661 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5662 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5664 (define_insn "*movdi_fix"
5665 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5666 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5667 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5668 && (register_operand (operands[0], DImode)
5669 || reg_or_0_operand (operands[1], DImode))"
5670 "@
5671 bis $31,%r1,%0
5672 lda %0,%1($31)
5673 ldah %0,%h1($31)
5674 lda %0,%1
5675 #
5676 ldq%A1 %0,%1
5677 stq%A0 %r1,%0
5678 cpys %R1,%R1,%0
5679 ldt %0,%1
5680 stt %R1,%0
5681 ftoit %1,%0
5682 itoft %1,%0"
5683 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5685 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5686 ;; often appears dead to the life analysis code, at which point we
5687 ;; die for emitting dead prologue instructions. Force this live.
5689 (define_insn "force_movdi"
5690 [(set (match_operand:DI 0 "register_operand" "=r")
5691 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5692 UNSPECV_FORCE_MOV))]
5693 ""
5694 "mov %1,%0"
5695 [(set_attr "type" "ilog")])
5697 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5698 ;; memory, and construct long 32-bit constants.
5700 (define_expand "movdi"
5701 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5702 (match_operand:DI 1 "general_operand" ""))]
5703 ""
5704 {
5705 if (alpha_expand_mov (DImode, operands))
5706 DONE;
5707 })
5709 ;; Split a load of a large constant into the appropriate two-insn
5710 ;; sequence.
5712 (define_split
5713 [(set (match_operand:DI 0 "register_operand" "")
5714 (match_operand:DI 1 "non_add_const_operand" ""))]
5715 ""
5716 [(const_int 0)]
5717 {
5718 if (alpha_split_const_mov (DImode, operands))
5719 DONE;
5720 else
5721 FAIL;
5722 })
5724 ;; We need to prevent reload from splitting TImode moves, because it
5725 ;; might decide to overwrite a pointer with the value it points to.
5726 ;; In that case we have to do the loads in the appropriate order so
5727 ;; that the pointer is not destroyed too early.
5729 (define_insn_and_split "*movti_internal"
5730 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
5731 (match_operand:TI 1 "input_operand" "roJ,rJ"))]
5732 "(register_operand (operands[0], TImode)
5733 /* Prevent rematerialization of constants. */
5734 && ! CONSTANT_P (operands[1]))
5735 || reg_or_0_operand (operands[1], TImode)"
5736 "#"
5737 "reload_completed"
5738 [(set (match_dup 0) (match_dup 2))
5739 (set (match_dup 1) (match_dup 3))]
5740 {
5741 alpha_split_tmode_pair (operands, TImode, true);
5742 })
5744 (define_expand "movti"
5745 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5746 (match_operand:TI 1 "general_operand" ""))]
5747 ""
5748 {
5749 if (MEM_P (operands[0])
5750 && ! reg_or_0_operand (operands[1], TImode))
5751 operands[1] = force_reg (TImode, operands[1]);
5753 if (operands[1] == const0_rtx)
5754 ;
5755 /* We must put 64-bit constants in memory. We could keep the
5756 32-bit constants in TImode and rely on the splitter, but
5757 this doesn't seem to be worth the pain. */
5758 else if (CONST_INT_P (operands[1])
5759 || GET_CODE (operands[1]) == CONST_DOUBLE)
5760 {
5761 rtx in[2], out[2], target;
5763 gcc_assert (can_create_pseudo_p ());
5765 split_double (operands[1], &in[0], &in[1]);
5767 if (in[0] == const0_rtx)
5768 out[0] = const0_rtx;
5769 else
5770 {
5771 out[0] = gen_reg_rtx (DImode);
5772 emit_insn (gen_movdi (out[0], in[0]));
5773 }
5775 if (in[1] == const0_rtx)
5776 out[1] = const0_rtx;
5777 else
5778 {
5779 out[1] = gen_reg_rtx (DImode);
5780 emit_insn (gen_movdi (out[1], in[1]));
5781 }
5783 if (!REG_P (operands[0]))
5784 target = gen_reg_rtx (TImode);
5785 else
5786 target = operands[0];
5788 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0]));
5789 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1]));
5791 if (target != operands[0])
5792 emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
5794 DONE;
5795 }
5796 })
5798 ;; These are the partial-word cases.
5799 ;;
5800 ;; First we have the code to load an aligned word. Operand 0 is the register
5801 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5802 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5803 ;; number of bits within the word that the value is. Operand 3 is an SImode
5804 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5805 ;; same register. It is allowed to conflict with operand 1 as well.
5807 (define_expand "aligned_loadqi"
5808 [(set (match_operand:SI 3 "register_operand" "")
5809 (match_operand:SI 1 "memory_operand" ""))
5810 (set (match_operand:DI 0 "register_operand" "")
5811 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5812 (const_int 8)
5813 (match_operand:DI 2 "const_int_operand" "")))]
5815 ""
5816 "")
5818 (define_expand "aligned_loadhi"
5819 [(set (match_operand:SI 3 "register_operand" "")
5820 (match_operand:SI 1 "memory_operand" ""))
5821 (set (match_operand:DI 0 "register_operand" "")
5822 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5823 (const_int 16)
5824 (match_operand:DI 2 "const_int_operand" "")))]
5826 ""
5827 "")
5829 ;; Similar for unaligned loads, where we use the sequence from the
5830 ;; Alpha Architecture manual. We have to distinguish between little-endian
5831 ;; and big-endian systems as the sequences are different.
5832 ;;
5833 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5834 ;; operand 3 can overlap the input and output registers.
5836 (define_expand "unaligned_loadqi"
5837 [(use (match_operand:DI 0 "register_operand" ""))
5838 (use (match_operand:DI 1 "address_operand" ""))
5839 (use (match_operand:DI 2 "register_operand" ""))
5840 (use (match_operand:DI 3 "register_operand" ""))]
5841 ""
5842 {
5843 if (WORDS_BIG_ENDIAN)
5844 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5845 operands[2], operands[3]));
5846 else
5847 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5848 operands[2], operands[3]));
5849 DONE;
5850 })
5852 (define_expand "unaligned_loadqi_le"
5853 [(set (match_operand:DI 2 "register_operand" "")
5854 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5855 (const_int -8))))
5856 (set (match_operand:DI 3 "register_operand" "")
5857 (match_dup 1))
5858 (set (match_operand:DI 0 "register_operand" "")
5859 (zero_extract:DI (match_dup 2)
5860 (const_int 8)
5861 (ashift:DI (match_dup 3) (const_int 3))))]
5862 "! WORDS_BIG_ENDIAN"
5863 "")
5865 (define_expand "unaligned_loadqi_be"
5866 [(set (match_operand:DI 2 "register_operand" "")
5867 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5868 (const_int -8))))
5869 (set (match_operand:DI 3 "register_operand" "")
5870 (match_dup 1))
5871 (set (match_operand:DI 0 "register_operand" "")
5872 (zero_extract:DI (match_dup 2)
5873 (const_int 8)
5874 (minus:DI
5875 (const_int 56)
5876 (ashift:DI (match_dup 3) (const_int 3)))))]
5877 "WORDS_BIG_ENDIAN"
5878 "")
5880 (define_expand "unaligned_loadhi"
5881 [(use (match_operand:DI 0 "register_operand" ""))
5882 (use (match_operand:DI 1 "address_operand" ""))
5883 (use (match_operand:DI 2 "register_operand" ""))
5884 (use (match_operand:DI 3 "register_operand" ""))]
5885 ""
5886 {
5887 if (WORDS_BIG_ENDIAN)
5888 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5889 operands[2], operands[3]));
5890 else
5891 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5892 operands[2], operands[3]));
5893 DONE;
5894 })
5896 (define_expand "unaligned_loadhi_le"
5897 [(set (match_operand:DI 2 "register_operand" "")
5898 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5899 (const_int -8))))
5900 (set (match_operand:DI 3 "register_operand" "")
5901 (match_dup 1))
5902 (set (match_operand:DI 0 "register_operand" "")
5903 (zero_extract:DI (match_dup 2)
5904 (const_int 16)
5905 (ashift:DI (match_dup 3) (const_int 3))))]
5906 "! WORDS_BIG_ENDIAN"
5907 "")
5909 (define_expand "unaligned_loadhi_be"
5910 [(set (match_operand:DI 2 "register_operand" "")
5911 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5912 (const_int -8))))
5913 (set (match_operand:DI 3 "register_operand" "")
5914 (plus:DI (match_dup 1) (const_int 1)))
5915 (set (match_operand:DI 0 "register_operand" "")
5916 (zero_extract:DI (match_dup 2)
5917 (const_int 16)
5918 (minus:DI
5919 (const_int 56)
5920 (ashift:DI (match_dup 3) (const_int 3)))))]
5921 "WORDS_BIG_ENDIAN"
5922 "")
5924 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5925 ;; aligned SImode MEM. Operand 1 is the register containing the
5926 ;; byte or word to store. Operand 2 is the number of bits within the word that
5927 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5929 (define_expand "aligned_store"
5930 [(set (match_operand:SI 3 "register_operand" "")
5931 (match_operand:SI 0 "memory_operand" ""))
5932 (set (subreg:DI (match_dup 3) 0)
5933 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5934 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5935 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5936 (match_operand:DI 2 "const_int_operand" "")))
5937 (set (subreg:DI (match_dup 4) 0)
5938 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5939 (set (match_dup 0) (match_dup 4))]
5940 ""
5941 {
5942 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5943 << INTVAL (operands[2])));
5944 })
5946 ;; For the unaligned byte and halfword cases, we use code similar to that
5947 ;; in the ;; Architecture book, but reordered to lower the number of registers
5948 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5949 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5950 ;; be the same temporary, if desired. If the address is in a register,
5951 ;; operand 2 can be that register.
5953 (define_expand "unaligned_storeqi"
5954 [(use (match_operand:DI 0 "address_operand" ""))
5955 (use (match_operand:QI 1 "register_operand" ""))
5956 (use (match_operand:DI 2 "register_operand" ""))
5957 (use (match_operand:DI 3 "register_operand" ""))
5958 (use (match_operand:DI 4 "register_operand" ""))]
5959 ""
5960 {
5961 if (WORDS_BIG_ENDIAN)
5962 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5963 operands[2], operands[3],
5964 operands[4]));
5965 else
5966 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5967 operands[2], operands[3],
5968 operands[4]));
5969 DONE;
5970 })
5972 (define_expand "unaligned_storeqi_le"
5973 [(set (match_operand:DI 3 "register_operand" "")
5974 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5975 (const_int -8))))
5976 (set (match_operand:DI 2 "register_operand" "")
5977 (match_dup 0))
5978 (set (match_dup 3)
5979 (and:DI (not:DI (ashift:DI (const_int 255)
5980 (ashift:DI (match_dup 2) (const_int 3))))
5981 (match_dup 3)))
5982 (set (match_operand:DI 4 "register_operand" "")
5983 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5984 (ashift:DI (match_dup 2) (const_int 3))))
5985 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5986 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5987 (match_dup 4))]
5988 "! WORDS_BIG_ENDIAN"
5989 "")
5991 (define_expand "unaligned_storeqi_be"
5992 [(set (match_operand:DI 3 "register_operand" "")
5993 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5994 (const_int -8))))
5995 (set (match_operand:DI 2 "register_operand" "")
5996 (match_dup 0))
5997 (set (match_dup 3)
5998 (and:DI (not:DI (ashift:DI (const_int 255)
5999 (minus:DI (const_int 56)
6000 (ashift:DI (match_dup 2) (const_int 3)))))
6001 (match_dup 3)))
6002 (set (match_operand:DI 4 "register_operand" "")
6003 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
6004 (minus:DI (const_int 56)
6005 (ashift:DI (match_dup 2) (const_int 3)))))
6006 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6007 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6008 (match_dup 4))]
6009 "WORDS_BIG_ENDIAN"
6010 "")
6012 (define_expand "unaligned_storehi"
6013 [(use (match_operand:DI 0 "address_operand" ""))
6014 (use (match_operand:HI 1 "register_operand" ""))
6015 (use (match_operand:DI 2 "register_operand" ""))
6016 (use (match_operand:DI 3 "register_operand" ""))
6017 (use (match_operand:DI 4 "register_operand" ""))]
6018 ""
6019 {
6020 if (WORDS_BIG_ENDIAN)
6021 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
6022 operands[2], operands[3],
6023 operands[4]));
6024 else
6025 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
6026 operands[2], operands[3],
6027 operands[4]));
6028 DONE;
6029 })
6031 (define_expand "unaligned_storehi_le"
6032 [(set (match_operand:DI 3 "register_operand" "")
6033 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6034 (const_int -8))))
6035 (set (match_operand:DI 2 "register_operand" "")
6036 (match_dup 0))
6037 (set (match_dup 3)
6038 (and:DI (not:DI (ashift:DI (const_int 65535)
6039 (ashift:DI (match_dup 2) (const_int 3))))
6040 (match_dup 3)))
6041 (set (match_operand:DI 4 "register_operand" "")
6042 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6043 (ashift:DI (match_dup 2) (const_int 3))))
6044 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6045 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6046 (match_dup 4))]
6047 "! WORDS_BIG_ENDIAN"
6048 "")
6050 (define_expand "unaligned_storehi_be"
6051 [(set (match_operand:DI 3 "register_operand" "")
6052 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6053 (const_int -8))))
6054 (set (match_operand:DI 2 "register_operand" "")
6055 (plus:DI (match_dup 0) (const_int 1)))
6056 (set (match_dup 3)
6057 (and:DI (not:DI (ashift:DI
6058 (const_int 65535)
6059 (minus:DI (const_int 56)
6060 (ashift:DI (match_dup 2) (const_int 3)))))
6061 (match_dup 3)))
6062 (set (match_operand:DI 4 "register_operand" "")
6063 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6064 (minus:DI (const_int 56)
6065 (ashift:DI (match_dup 2) (const_int 3)))))
6066 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6067 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6068 (match_dup 4))]
6069 "WORDS_BIG_ENDIAN"
6070 "")
6071 \f
6072 ;; Here are the define_expand's for QI and HI moves that use the above
6073 ;; patterns. We have the normal sets, plus the ones that need scratch
6074 ;; registers for reload.
6076 (define_expand "movqi"
6077 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6078 (match_operand:QI 1 "general_operand" ""))]
6079 ""
6080 {
6081 if (TARGET_BWX
6082 ? alpha_expand_mov (QImode, operands)
6083 : alpha_expand_mov_nobwx (QImode, operands))
6084 DONE;
6085 })
6087 (define_expand "movhi"
6088 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6089 (match_operand:HI 1 "general_operand" ""))]
6090 ""
6091 {
6092 if (TARGET_BWX
6093 ? alpha_expand_mov (HImode, operands)
6094 : alpha_expand_mov_nobwx (HImode, operands))
6095 DONE;
6096 })
6098 ;; We need to hook into the extra support that we have for HImode
6099 ;; reloads when BWX insns are not available.
6100 (define_expand "movcqi"
6101 [(set (match_operand:CQI 0 "nonimmediate_operand" "")
6102 (match_operand:CQI 1 "general_operand" ""))]
6103 "!TARGET_BWX"
6104 {
6105 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
6106 ;
6107 else if (!any_memory_operand (operands[0], CQImode))
6108 {
6109 if (!any_memory_operand (operands[1], CQImode))
6110 {
6111 emit_move_insn (gen_lowpart (HImode, operands[0]),
6112 gen_lowpart (HImode, operands[1]));
6113 DONE;
6114 }
6115 if (aligned_memory_operand (operands[1], CQImode))
6116 {
6117 bool done;
6118 do_aligned1:
6119 operands[1] = gen_lowpart (HImode, operands[1]);
6120 do_aligned2:
6121 operands[0] = gen_lowpart (HImode, operands[0]);
6122 done = alpha_expand_mov_nobwx (HImode, operands);
6123 gcc_assert (done);
6124 DONE;
6125 }
6126 }
6127 else if (aligned_memory_operand (operands[0], CQImode))
6128 {
6129 if (MEM_P (operands[1]))
6130 {
6131 rtx x = gen_reg_rtx (HImode);
6132 emit_move_insn (gen_lowpart (CQImode, x), operands[1]);
6133 operands[1] = x;
6134 goto do_aligned2;
6135 }
6136 goto do_aligned1;
6137 }
6139 gcc_assert (!reload_in_progress);
6140 emit_move_complex_parts (operands[0], operands[1]);
6141 DONE;
6142 })
6144 ;; Here are the versions for reload.
6145 ;;
6146 ;; The aligned input case is recognized early in alpha_secondary_reload
6147 ;; in order to avoid allocating an unnecessary scratch register.
6148 ;;
6149 ;; Note that in the unaligned cases we know that the operand must not be
6150 ;; a pseudo-register because stack slots are always aligned references.
6152 (define_expand "reload_in<mode>"
6153 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r")
6154 (match_operand:RELOAD12 1 "any_memory_operand" "m")
6155 (match_operand:TI 2 "register_operand" "=&r")])]
6156 "!TARGET_BWX"
6157 {
6158 rtx scratch, seq, addr;
6159 unsigned regno = REGNO (operands[2]);
6161 /* It is possible that one of the registers we got for operands[2]
6162 might coincide with that of operands[0] (which is why we made
6163 it TImode). Pick the other one to use as our scratch. */
6164 if (regno == REGNO (operands[0]))
6165 regno++;
6166 scratch = gen_rtx_REG (DImode, regno);
6168 addr = get_unaligned_address (operands[1]);
6169 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6170 seq = gen_unaligned_load<reloadmode> (operands[0], addr,
6171 scratch, operands[0]);
6172 alpha_set_memflags (seq, operands[1]);
6174 emit_insn (seq);
6175 DONE;
6176 })
6178 (define_expand "reload_out<mode>"
6179 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
6180 (match_operand:RELOAD12 1 "register_operand" "r")
6181 (match_operand:TI 2 "register_operand" "=&r")])]
6182 "! TARGET_BWX"
6183 {
6184 unsigned regno = REGNO (operands[2]);
6186 if (<MODE>mode == CQImode)
6187 {
6188 operands[0] = gen_lowpart (HImode, operands[0]);
6189 operands[1] = gen_lowpart (HImode, operands[1]);
6190 }
6192 if (aligned_memory_operand (operands[0], <MODE>mode))
6193 {
6194 emit_insn (gen_reload_out<reloadmode>_aligned
6195 (operands[0], operands[1],
6196 gen_rtx_REG (SImode, regno),
6197 gen_rtx_REG (SImode, regno + 1)));
6198 }
6199 else
6200 {
6201 rtx addr = get_unaligned_address (operands[0]);
6202 rtx scratch1 = gen_rtx_REG (DImode, regno);
6203 rtx scratch2 = gen_rtx_REG (DImode, regno + 1);
6204 rtx scratch3 = scratch1;
6205 rtx seq;
6207 if (REG_P (addr))
6208 scratch1 = addr;
6210 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
6211 scratch2, scratch3);
6212 alpha_set_memflags (seq, operands[0]);
6213 emit_insn (seq);
6214 }
6215 DONE;
6216 })
6218 ;; Helpers for the above. The way reload is structured, we can't
6219 ;; always get a proper address for a stack slot during reload_foo
6220 ;; expansion, so we must delay our address manipulations until after.
6222 (define_insn_and_split "reload_in<mode>_aligned"
6223 [(set (match_operand:I12MODE 0 "register_operand" "=r")
6224 (match_operand:I12MODE 1 "memory_operand" "m"))]
6225 "!TARGET_BWX && (reload_in_progress || reload_completed)"
6226 "#"
6227 "!TARGET_BWX && reload_completed"
6228 [(const_int 0)]
6229 {
6230 rtx aligned_mem, bitnum;
6231 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6232 emit_insn (gen_aligned_load<reloadmode>
6233 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum,
6234 gen_rtx_REG (SImode, REGNO (operands[0]))));
6235 DONE;
6236 })
6238 (define_insn_and_split "reload_out<mode>_aligned"
6239 [(set (match_operand:I12MODE 0 "memory_operand" "=m")
6240 (match_operand:I12MODE 1 "register_operand" "r"))
6241 (clobber (match_operand:SI 2 "register_operand" "=r"))
6242 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6243 "!TARGET_BWX && (reload_in_progress || reload_completed)"
6244 "#"
6245 "!TARGET_BWX && reload_completed"
6246 [(const_int 0)]
6247 {
6248 rtx aligned_mem, bitnum;
6249 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6250 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6251 operands[2], operands[3]));
6252 DONE;
6253 })
6254 \f
6255 ;; Vector operations
6257 (define_mode_iterator VEC [V8QI V4HI V2SI])
6259 (define_expand "mov<mode>"
6260 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6261 (match_operand:VEC 1 "general_operand" ""))]
6262 ""
6263 {
6264 if (alpha_expand_mov (<MODE>mode, operands))
6265 DONE;
6266 })
6268 (define_split
6269 [(set (match_operand:VEC 0 "register_operand" "")
6270 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6271 ""
6272 [(const_int 0)]
6273 {
6274 if (alpha_split_const_mov (<MODE>mode, operands))
6275 DONE;
6276 else
6277 FAIL;
6278 })
6281 (define_expand "movmisalign<mode>"
6282 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6283 (match_operand:VEC 1 "general_operand" ""))]
6284 ""
6285 {
6286 alpha_expand_movmisalign (<MODE>mode, operands);
6287 DONE;
6288 })
6290 (define_insn "*mov<mode>_fix"
6291 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6292 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6293 "TARGET_FIX
6294 && (register_operand (operands[0], <MODE>mode)
6295 || reg_or_0_operand (operands[1], <MODE>mode))"
6296 "@
6297 bis $31,%r1,%0
6298 #
6299 ldq %0,%1
6300 stq %r1,%0
6301 cpys %R1,%R1,%0
6302 ldt %0,%1
6303 stt %R1,%0
6304 ftoit %1,%0
6305 itoft %1,%0"
6306 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6308 (define_insn "*mov<mode>_nofix"
6309 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6310 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6311 "! TARGET_FIX
6312 && (register_operand (operands[0], <MODE>mode)
6313 || reg_or_0_operand (operands[1], <MODE>mode))"
6314 "@
6315 bis $31,%r1,%0
6316 #
6317 ldq %0,%1
6318 stq %r1,%0
6319 cpys %R1,%R1,%0
6320 ldt %0,%1
6321 stt %R1,%0"
6322 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6324 (define_insn "uminv8qi3"
6325 [(set (match_operand:V8QI 0 "register_operand" "=r")
6326 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6327 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6328 "TARGET_MAX"
6329 "minub8 %r1,%r2,%0"
6330 [(set_attr "type" "mvi")])
6332 (define_insn "sminv8qi3"
6333 [(set (match_operand:V8QI 0 "register_operand" "=r")
6334 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6335 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6336 "TARGET_MAX"
6337 "minsb8 %r1,%r2,%0"
6338 [(set_attr "type" "mvi")])
6340 (define_insn "uminv4hi3"
6341 [(set (match_operand:V4HI 0 "register_operand" "=r")
6342 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6343 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6344 "TARGET_MAX"
6345 "minuw4 %r1,%r2,%0"
6346 [(set_attr "type" "mvi")])
6348 (define_insn "sminv4hi3"
6349 [(set (match_operand:V4HI 0 "register_operand" "=r")
6350 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6351 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6352 "TARGET_MAX"
6353 "minsw4 %r1,%r2,%0"
6354 [(set_attr "type" "mvi")])
6356 (define_insn "umaxv8qi3"
6357 [(set (match_operand:V8QI 0 "register_operand" "=r")
6358 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6359 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6360 "TARGET_MAX"
6361 "maxub8 %r1,%r2,%0"
6362 [(set_attr "type" "mvi")])
6364 (define_insn "smaxv8qi3"
6365 [(set (match_operand:V8QI 0 "register_operand" "=r")
6366 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6367 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6368 "TARGET_MAX"
6369 "maxsb8 %r1,%r2,%0"
6370 [(set_attr "type" "mvi")])
6372 (define_insn "umaxv4hi3"
6373 [(set (match_operand:V4HI 0 "register_operand" "=r")
6374 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6375 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6376 "TARGET_MAX"
6377 "maxuw4 %r1,%r2,%0"
6378 [(set_attr "type" "mvi")])
6380 (define_insn "smaxv4hi3"
6381 [(set (match_operand:V4HI 0 "register_operand" "=r")
6382 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6383 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6384 "TARGET_MAX"
6385 "maxsw4 %r1,%r2,%0"
6386 [(set_attr "type" "mvi")])
6388 (define_insn "one_cmpl<mode>2"
6389 [(set (match_operand:VEC 0 "register_operand" "=r")
6390 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6391 ""
6392 "ornot $31,%1,%0"
6393 [(set_attr "type" "ilog")])
6395 (define_insn "and<mode>3"
6396 [(set (match_operand:VEC 0 "register_operand" "=r")
6397 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6398 (match_operand:VEC 2 "register_operand" "r")))]
6399 ""
6400 "and %1,%2,%0"
6401 [(set_attr "type" "ilog")])
6403 (define_insn "*andnot<mode>3"
6404 [(set (match_operand:VEC 0 "register_operand" "=r")
6405 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6406 (match_operand:VEC 2 "register_operand" "r")))]
6407 ""
6408 "bic %2,%1,%0"
6409 [(set_attr "type" "ilog")])
6411 (define_insn "ior<mode>3"
6412 [(set (match_operand:VEC 0 "register_operand" "=r")
6413 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6414 (match_operand:VEC 2 "register_operand" "r")))]
6415 ""
6416 "bis %1,%2,%0"
6417 [(set_attr "type" "ilog")])
6419 (define_insn "*iornot<mode>3"
6420 [(set (match_operand:VEC 0 "register_operand" "=r")
6421 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6422 (match_operand:VEC 2 "register_operand" "r")))]
6423 ""
6424 "ornot %2,%1,%0"
6425 [(set_attr "type" "ilog")])
6427 (define_insn "xor<mode>3"
6428 [(set (match_operand:VEC 0 "register_operand" "=r")
6429 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6430 (match_operand:VEC 2 "register_operand" "r")))]
6431 ""
6432 "xor %1,%2,%0"
6433 [(set_attr "type" "ilog")])
6435 (define_insn "*xornot<mode>3"
6436 [(set (match_operand:VEC 0 "register_operand" "=r")
6437 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6438 (match_operand:VEC 2 "register_operand" "r"))))]
6439 ""
6440 "eqv %1,%2,%0"
6441 [(set_attr "type" "ilog")])
6443 (define_expand "vec_shl_<mode>"
6444 [(set (match_operand:VEC 0 "register_operand" "")
6445 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6446 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6447 ""
6448 {
6449 operands[0] = gen_lowpart (DImode, operands[0]);
6450 operands[1] = gen_lowpart (DImode, operands[1]);
6451 })
6453 (define_expand "vec_shr_<mode>"
6454 [(set (match_operand:VEC 0 "register_operand" "")
6455 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6456 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6457 ""
6458 {
6459 operands[0] = gen_lowpart (DImode, operands[0]);
6460 operands[1] = gen_lowpart (DImode, operands[1]);
6461 })
6462 \f
6463 ;; Bit field extract patterns which use ext[wlq][lh]
6465 (define_expand "extv"
6466 [(set (match_operand:DI 0 "register_operand" "")
6467 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6468 (match_operand:DI 2 "immediate_operand" "")
6469 (match_operand:DI 3 "immediate_operand" "")))]
6470 ""
6471 {
6472 int ofs;
6474 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6475 if (INTVAL (operands[3]) % 8 != 0
6476 || (INTVAL (operands[2]) != 16
6477 && INTVAL (operands[2]) != 32
6478 && INTVAL (operands[2]) != 64))
6479 FAIL;
6481 /* From mips.md: extract_bit_field doesn't verify that our source
6482 matches the predicate, so we force it to be a MEM here. */
6483 if (!MEM_P (operands[1]))
6484 FAIL;
6486 /* The bit number is relative to the mode of operand 1 which is
6487 usually QImode (this might actually be a bug in expmed.c). Note
6488 that the bit number is negative in big-endian mode in this case.
6489 We have to convert that to the offset. */
6490 if (WORDS_BIG_ENDIAN)
6491 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6492 - INTVAL (operands[2]) - INTVAL (operands[3]);
6493 else
6494 ofs = INTVAL (operands[3]);
6496 ofs = ofs / 8;
6498 alpha_expand_unaligned_load (operands[0], operands[1],
6499 INTVAL (operands[2]) / 8,
6500 ofs, 1);
6501 DONE;
6502 })
6504 (define_expand "extzv"
6505 [(set (match_operand:DI 0 "register_operand" "")
6506 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6507 (match_operand:DI 2 "immediate_operand" "")
6508 (match_operand:DI 3 "immediate_operand" "")))]
6509 ""
6510 {
6511 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6512 if (INTVAL (operands[3]) % 8 != 0
6513 || (INTVAL (operands[2]) != 8
6514 && INTVAL (operands[2]) != 16
6515 && INTVAL (operands[2]) != 32
6516 && INTVAL (operands[2]) != 64))
6517 FAIL;
6519 if (MEM_P (operands[1]))
6520 {
6521 int ofs;
6523 /* Fail 8-bit fields, falling back on a simple byte load. */
6524 if (INTVAL (operands[2]) == 8)
6525 FAIL;
6527 /* The bit number is relative to the mode of operand 1 which is
6528 usually QImode (this might actually be a bug in expmed.c). Note
6529 that the bit number is negative in big-endian mode in this case.
6530 We have to convert that to the offset. */
6531 if (WORDS_BIG_ENDIAN)
6532 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6533 - INTVAL (operands[2]) - INTVAL (operands[3]);
6534 else
6535 ofs = INTVAL (operands[3]);
6537 ofs = ofs / 8;
6539 alpha_expand_unaligned_load (operands[0], operands[1],
6540 INTVAL (operands[2]) / 8,
6541 ofs, 0);
6542 DONE;
6543 }
6544 })
6546 (define_expand "insv"
6547 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6548 (match_operand:DI 1 "immediate_operand" "")
6549 (match_operand:DI 2 "immediate_operand" ""))
6550 (match_operand:DI 3 "register_operand" ""))]
6551 ""
6552 {
6553 int ofs;
6555 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6556 if (INTVAL (operands[2]) % 8 != 0
6557 || (INTVAL (operands[1]) != 16
6558 && INTVAL (operands[1]) != 32
6559 && INTVAL (operands[1]) != 64))
6560 FAIL;
6562 /* From mips.md: store_bit_field doesn't verify that our source
6563 matches the predicate, so we force it to be a MEM here. */
6564 if (!MEM_P (operands[0]))
6565 FAIL;
6567 /* The bit number is relative to the mode of operand 1 which is
6568 usually QImode (this might actually be a bug in expmed.c). Note
6569 that the bit number is negative in big-endian mode in this case.
6570 We have to convert that to the offset. */
6571 if (WORDS_BIG_ENDIAN)
6572 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6573 - INTVAL (operands[1]) - INTVAL (operands[2]);
6574 else
6575 ofs = INTVAL (operands[2]);
6577 ofs = ofs / 8;
6579 alpha_expand_unaligned_store (operands[0], operands[3],
6580 INTVAL (operands[1]) / 8, ofs);
6581 DONE;
6582 })
6584 ;; Block move/clear, see alpha.c for more details.
6585 ;; Argument 0 is the destination
6586 ;; Argument 1 is the source
6587 ;; Argument 2 is the length
6588 ;; Argument 3 is the alignment
6590 (define_expand "movmemqi"
6591 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6592 (match_operand:BLK 1 "memory_operand" ""))
6593 (use (match_operand:DI 2 "immediate_operand" ""))
6594 (use (match_operand:DI 3 "immediate_operand" ""))])]
6595 ""
6596 {
6597 if (alpha_expand_block_move (operands))
6598 DONE;
6599 else
6600 FAIL;
6601 })
6603 (define_expand "movmemdi"
6604 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6605 (match_operand:BLK 1 "memory_operand" ""))
6606 (use (match_operand:DI 2 "immediate_operand" ""))
6607 (use (match_operand:DI 3 "immediate_operand" ""))
6608 (use (match_dup 4))
6609 (clobber (reg:DI 25))
6610 (clobber (reg:DI 16))
6611 (clobber (reg:DI 17))
6612 (clobber (reg:DI 18))
6613 (clobber (reg:DI 19))
6614 (clobber (reg:DI 20))
6615 (clobber (reg:DI 26))
6616 (clobber (reg:DI 27))])]
6617 "TARGET_ABI_OPEN_VMS"
6618 {
6619 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6620 alpha_need_linkage (XSTR (operands[4], 0), 0);
6621 })
6623 (define_insn "*movmemdi_1"
6624 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6625 (match_operand:BLK 1 "memory_operand" "m,m"))
6626 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6627 (use (match_operand:DI 3 "immediate_operand" ""))
6628 (use (match_operand:DI 4 "call_operand" "i,i"))
6629 (clobber (reg:DI 25))
6630 (clobber (reg:DI 16))
6631 (clobber (reg:DI 17))
6632 (clobber (reg:DI 18))
6633 (clobber (reg:DI 19))
6634 (clobber (reg:DI 20))
6635 (clobber (reg:DI 26))
6636 (clobber (reg:DI 27))]
6637 "TARGET_ABI_OPEN_VMS"
6638 {
6639 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6640 switch (which_alternative)
6641 {
6642 case 0:
6643 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6644 case 1:
6645 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6646 default:
6647 gcc_unreachable ();
6648 }
6649 }
6650 [(set_attr "type" "multi")
6651 (set_attr "length" "28")])
6653 (define_expand "setmemqi"
6654 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6655 (match_operand 2 "const_int_operand" ""))
6656 (use (match_operand:DI 1 "immediate_operand" ""))
6657 (use (match_operand:DI 3 "immediate_operand" ""))])]
6658 ""
6659 {
6660 /* If value to set is not zero, use the library routine. */
6661 if (operands[2] != const0_rtx)
6662 FAIL;
6664 if (alpha_expand_block_clear (operands))
6665 DONE;
6666 else
6667 FAIL;
6668 })
6670 (define_expand "setmemdi"
6671 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6672 (match_operand 2 "const_int_operand" ""))
6673 (use (match_operand:DI 1 "immediate_operand" ""))
6674 (use (match_operand:DI 3 "immediate_operand" ""))
6675 (use (match_dup 4))
6676 (clobber (reg:DI 25))
6677 (clobber (reg:DI 16))
6678 (clobber (reg:DI 17))
6679 (clobber (reg:DI 26))
6680 (clobber (reg:DI 27))])]
6681 "TARGET_ABI_OPEN_VMS"
6682 {
6683 /* If value to set is not zero, use the library routine. */
6684 if (operands[2] != const0_rtx)
6685 FAIL;
6687 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6688 alpha_need_linkage (XSTR (operands[4], 0), 0);
6689 })
6691 (define_insn "*clrmemdi_1"
6692 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6693 (const_int 0))
6694 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6695 (use (match_operand:DI 2 "immediate_operand" ""))
6696 (use (match_operand:DI 3 "call_operand" "i,i"))
6697 (clobber (reg:DI 25))
6698 (clobber (reg:DI 16))
6699 (clobber (reg:DI 17))
6700 (clobber (reg:DI 26))
6701 (clobber (reg:DI 27))]
6702 "TARGET_ABI_OPEN_VMS"
6703 {
6704 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6705 switch (which_alternative)
6706 {
6707 case 0:
6708 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6709 case 1:
6710 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6711 default:
6712 gcc_unreachable ();
6713 }
6714 }
6715 [(set_attr "type" "multi")
6716 (set_attr "length" "24")])
6718 \f
6719 ;; Subroutine of stack space allocation. Perform a stack probe.
6720 (define_expand "probe_stack"
6721 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6722 ""
6723 {
6724 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6725 INTVAL (operands[0])));
6726 MEM_VOLATILE_P (operands[1]) = 1;
6728 operands[0] = const0_rtx;
6729 })
6731 ;; This is how we allocate stack space. If we are allocating a
6732 ;; constant amount of space and we know it is less than 4096
6733 ;; bytes, we need do nothing.
6734 ;;
6735 ;; If it is more than 4096 bytes, we need to probe the stack
6736 ;; periodically.
6737 (define_expand "allocate_stack"
6738 [(set (reg:DI 30)
6739 (plus:DI (reg:DI 30)
6740 (match_operand:DI 1 "reg_or_cint_operand" "")))
6741 (set (match_operand:DI 0 "register_operand" "=r")
6742 (match_dup 2))]
6743 ""
6744 {
6745 if (CONST_INT_P (operands[1])
6746 && INTVAL (operands[1]) < 32768)
6747 {
6748 if (INTVAL (operands[1]) >= 4096)
6749 {
6750 /* We do this the same way as in the prologue and generate explicit
6751 probes. Then we update the stack by the constant. */
6753 int probed = 4096;
6755 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6756 while (probed + 8192 < INTVAL (operands[1]))
6757 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6759 if (probed + 4096 < INTVAL (operands[1]))
6760 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6761 }
6763 operands[1] = GEN_INT (- INTVAL (operands[1]));
6764 operands[2] = virtual_stack_dynamic_rtx;
6765 }
6766 else
6767 {
6768 rtx out_label = 0;
6769 rtx loop_label = gen_label_rtx ();
6770 rtx want = gen_reg_rtx (Pmode);
6771 rtx tmp = gen_reg_rtx (Pmode);
6772 rtx memref;
6774 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6775 force_reg (Pmode, operands[1])));
6776 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6778 if (!CONST_INT_P (operands[1]))
6779 {
6780 out_label = gen_label_rtx ();
6781 emit_insn (gen_cmpdi (want, tmp));
6782 emit_jump_insn (gen_bgeu (out_label));
6783 }
6785 emit_label (loop_label);
6786 memref = gen_rtx_MEM (DImode, tmp);
6787 MEM_VOLATILE_P (memref) = 1;
6788 emit_move_insn (memref, const0_rtx);
6789 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6790 emit_insn (gen_cmpdi (tmp, want));
6791 emit_jump_insn (gen_bgtu (loop_label));
6793 memref = gen_rtx_MEM (DImode, want);
6794 MEM_VOLATILE_P (memref) = 1;
6795 emit_move_insn (memref, const0_rtx);
6797 if (out_label)
6798 emit_label (out_label);
6800 emit_move_insn (stack_pointer_rtx, want);
6801 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6802 DONE;
6803 }
6804 })
6806 ;; This is used by alpha_expand_prolog to do the same thing as above,
6807 ;; except we cannot at that time generate new basic blocks, so we hide
6808 ;; the loop in this one insn.
6810 (define_insn "prologue_stack_probe_loop"
6811 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6812 (match_operand:DI 1 "register_operand" "r")]
6813 UNSPECV_PSPL)]
6814 ""
6815 {
6816 operands[2] = gen_label_rtx ();
6817 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6818 CODE_LABEL_NUMBER (operands[2]));
6820 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6821 }
6822 [(set_attr "length" "16")
6823 (set_attr "type" "multi")])
6825 (define_expand "prologue"
6826 [(clobber (const_int 0))]
6827 ""
6828 {
6829 alpha_expand_prologue ();
6830 DONE;
6831 })
6833 ;; These take care of emitting the ldgp insn in the prologue. This will be
6834 ;; an lda/ldah pair and we want to align them properly. So we have two
6835 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6836 ;; and the second of which emits nothing. However, both are marked as type
6837 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6838 ;; with them.
6840 (define_expand "prologue_ldgp"
6841 [(set (match_dup 0)
6842 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6843 (set (match_dup 0)
6844 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6845 ""
6846 {
6847 operands[0] = pic_offset_table_rtx;
6848 operands[1] = gen_rtx_REG (Pmode, 27);
6849 operands[2] = (TARGET_EXPLICIT_RELOCS
6850 ? GEN_INT (alpha_next_sequence_number++)
6851 : const0_rtx);
6852 })
6854 (define_insn "*ldgp_er_1"
6855 [(set (match_operand:DI 0 "register_operand" "=r")
6856 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6857 (match_operand 2 "const_int_operand" "")]
6858 UNSPECV_LDGP1))]
6859 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6860 "ldah %0,0(%1)\t\t!gpdisp!%2"
6861 [(set_attr "cannot_copy" "true")])
6863 (define_insn "*ldgp_er_2"
6864 [(set (match_operand:DI 0 "register_operand" "=r")
6865 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6866 (match_operand 2 "const_int_operand" "")]
6867 UNSPEC_LDGP2))]
6868 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6869 "lda %0,0(%1)\t\t!gpdisp!%2"
6870 [(set_attr "cannot_copy" "true")])
6872 (define_insn "*prologue_ldgp_er_2"
6873 [(set (match_operand:DI 0 "register_operand" "=r")
6874 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6875 (match_operand 2 "const_int_operand" "")]
6876 UNSPECV_PLDGP2))]
6877 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6878 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6879 [(set_attr "cannot_copy" "true")])
6881 (define_insn "*prologue_ldgp_1"
6882 [(set (match_operand:DI 0 "register_operand" "=r")
6883 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6884 (match_operand 2 "const_int_operand" "")]
6885 UNSPECV_LDGP1))]
6886 ""
6887 "ldgp %0,0(%1)\n$%~..ng:"
6888 [(set_attr "cannot_copy" "true")])
6890 (define_insn "*prologue_ldgp_2"
6891 [(set (match_operand:DI 0 "register_operand" "=r")
6892 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6893 (match_operand 2 "const_int_operand" "")]
6894 UNSPECV_PLDGP2))]
6895 ""
6896 "")
6898 ;; The _mcount profiling hook has special calling conventions, and
6899 ;; does not clobber all the registers that a normal call would. So
6900 ;; hide the fact this is a call at all.
6902 (define_insn "prologue_mcount"
6903 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6904 ""
6905 {
6906 if (TARGET_EXPLICIT_RELOCS)
6907 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6908 cannot be called via the PLT. */
6909 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6910 else
6911 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6912 }
6913 [(set_attr "type" "multi")
6914 (set_attr "length" "8")])
6916 (define_insn "init_fp"
6917 [(set (match_operand:DI 0 "register_operand" "=r")
6918 (match_operand:DI 1 "register_operand" "r"))
6919 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6920 ""
6921 "bis $31,%1,%0")
6923 (define_expand "epilogue"
6924 [(return)]
6925 ""
6926 {
6927 alpha_expand_epilogue ();
6928 })
6930 (define_expand "sibcall_epilogue"
6931 [(return)]
6932 "TARGET_ABI_OSF"
6933 {
6934 alpha_expand_epilogue ();
6935 DONE;
6936 })
6938 (define_expand "builtin_longjmp"
6939 [(use (match_operand:DI 0 "register_operand" "r"))]
6940 "TARGET_ABI_OSF"
6941 {
6942 /* The elements of the buffer are, in order: */
6943 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6944 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6945 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6946 rtx pv = gen_rtx_REG (Pmode, 27);
6948 /* This bit is the same as expand_builtin_longjmp. */
6949 emit_move_insn (hard_frame_pointer_rtx, fp);
6950 emit_move_insn (pv, lab);
6951 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6952 emit_use (hard_frame_pointer_rtx);
6953 emit_use (stack_pointer_rtx);
6955 /* Load the label we are jumping through into $27 so that we know
6956 where to look for it when we get back to setjmp's function for
6957 restoring the gp. */
6958 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6959 emit_barrier ();
6960 DONE;
6961 })
6963 ;; This is effectively a copy of indirect_jump, but constrained such
6964 ;; that register renaming cannot foil our cunning plan with $27.
6965 (define_insn "builtin_longjmp_internal"
6966 [(set (pc)
6967 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6968 UNSPECV_LONGJMP))]
6969 ""
6970 "jmp $31,(%0),0"
6971 [(set_attr "type" "ibr")])
6973 (define_expand "builtin_setjmp_receiver"
6974 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6975 "TARGET_ABI_OSF"
6976 "")
6978 (define_insn_and_split "*builtin_setjmp_receiver_1"
6979 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6980 "TARGET_ABI_OSF"
6981 {
6982 if (TARGET_EXPLICIT_RELOCS)
6983 return "#";
6984 else
6985 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6986 }
6987 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6988 [(set (match_dup 1)
6989 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6990 (set (match_dup 1)
6991 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6992 {
6993 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6994 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6995 UNSPECV_SETJMPR_ER));
6996 operands[1] = pic_offset_table_rtx;
6997 operands[2] = gen_rtx_REG (Pmode, 27);
6998 operands[3] = GEN_INT (alpha_next_sequence_number++);
6999 }
7000 [(set_attr "length" "12")
7001 (set_attr "type" "multi")])
7003 (define_insn "*builtin_setjmp_receiver_er_sl_1"
7004 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7005 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
7006 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
7008 (define_insn "*builtin_setjmp_receiver_er_1"
7009 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7010 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
7011 "br $27,$LSJ%=\n$LSJ%=:"
7012 [(set_attr "type" "ibr")])
7014 (define_expand "exception_receiver"
7015 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
7016 "TARGET_ABI_OSF"
7017 {
7018 if (TARGET_LD_BUGGY_LDGP)
7019 operands[0] = alpha_gp_save_rtx ();
7020 else
7021 operands[0] = const0_rtx;
7022 })
7024 (define_insn "*exception_receiver_2"
7025 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
7026 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
7027 "ldq $29,%0"
7028 [(set_attr "type" "ild")])
7030 (define_insn_and_split "*exception_receiver_1"
7031 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
7032 "TARGET_ABI_OSF"
7033 {
7034 if (TARGET_EXPLICIT_RELOCS)
7035 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
7036 else
7037 return "ldgp $29,0($26)";
7038 }
7039 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
7040 [(set (match_dup 0)
7041 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
7042 (set (match_dup 0)
7043 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
7044 {
7045 operands[0] = pic_offset_table_rtx;
7046 operands[1] = gen_rtx_REG (Pmode, 26);
7047 operands[2] = GEN_INT (alpha_next_sequence_number++);
7048 }
7049 [(set_attr "length" "8")
7050 (set_attr "type" "multi")])
7052 (define_expand "nonlocal_goto_receiver"
7053 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7054 (set (reg:DI 27) (mem:DI (reg:DI 29)))
7055 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7056 (use (reg:DI 27))]
7057 "TARGET_ABI_OPEN_VMS"
7058 "")
7060 (define_insn "arg_home"
7061 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7062 (use (reg:DI 1))
7063 (use (reg:DI 25))
7064 (use (reg:DI 16))
7065 (use (reg:DI 17))
7066 (use (reg:DI 18))
7067 (use (reg:DI 19))
7068 (use (reg:DI 20))
7069 (use (reg:DI 21))
7070 (use (reg:DI 48))
7071 (use (reg:DI 49))
7072 (use (reg:DI 50))
7073 (use (reg:DI 51))
7074 (use (reg:DI 52))
7075 (use (reg:DI 53))
7076 (clobber (mem:BLK (const_int 0)))
7077 (clobber (reg:DI 24))
7078 (clobber (reg:DI 25))
7079 (clobber (reg:DI 0))]
7080 "TARGET_ABI_OPEN_VMS"
7081 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7082 [(set_attr "length" "16")
7083 (set_attr "type" "multi")])
7085 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7087 (define_expand "umk_mismatch_args"
7088 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7089 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7090 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7091 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7092 (const_int 8))
7093 (match_dup 2)))
7094 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7095 "TARGET_ABI_UNICOSMK"
7096 {
7097 operands[1] = gen_reg_rtx (DImode);
7098 operands[2] = gen_reg_rtx (DImode);
7099 operands[3] = gen_reg_rtx (DImode);
7100 })
7102 (define_insn "arg_home_umk"
7103 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7104 (use (reg:DI 1))
7105 (use (reg:DI 2))
7106 (use (reg:DI 16))
7107 (use (reg:DI 17))
7108 (use (reg:DI 18))
7109 (use (reg:DI 19))
7110 (use (reg:DI 20))
7111 (use (reg:DI 21))
7112 (use (reg:DI 48))
7113 (use (reg:DI 49))
7114 (use (reg:DI 50))
7115 (use (reg:DI 51))
7116 (use (reg:DI 52))
7117 (use (reg:DI 53))
7118 (clobber (mem:BLK (const_int 0)))
7119 (parallel [
7120 (clobber (reg:DI 22))
7121 (clobber (reg:DI 23))
7122 (clobber (reg:DI 24))
7123 (clobber (reg:DI 0))
7124 (clobber (reg:DI 1))
7125 (clobber (reg:DI 2))
7126 (clobber (reg:DI 3))
7127 (clobber (reg:DI 4))
7128 (clobber (reg:DI 5))
7129 (clobber (reg:DI 6))
7130 (clobber (reg:DI 7))
7131 (clobber (reg:DI 8))])]
7132 "TARGET_ABI_UNICOSMK"
7133 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7134 [(set_attr "length" "16")
7135 (set_attr "type" "multi")])
7137 ;; Prefetch data.
7138 ;;
7139 ;; On EV4, these instructions are nops -- no load occurs.
7140 ;;
7141 ;; On EV5, these instructions act as a normal load, and thus can trap
7142 ;; if the address is invalid. The OS may (or may not) handle this in
7143 ;; the entMM fault handler and suppress the fault. If so, then this
7144 ;; has the effect of a read prefetch instruction.
7145 ;;
7146 ;; On EV6, these become official prefetch instructions.
7148 (define_insn "prefetch"
7149 [(prefetch (match_operand:DI 0 "address_operand" "p")
7150 (match_operand:DI 1 "const_int_operand" "n")
7151 (match_operand:DI 2 "const_int_operand" "n"))]
7152 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7153 {
7154 /* Interpret "no temporal locality" as this data should be evicted once
7155 it is used. The "evict next" alternatives load the data into the cache
7156 and leave the LRU eviction counter pointing to that block. */
7157 static const char * const alt[2][2] = {
7158 {
7159 "ldq $31,%a0", /* read, evict next */
7160 "ldl $31,%a0", /* read, evict last */
7161 },
7162 {
7163 "ldt $f31,%a0", /* write, evict next */
7164 "lds $f31,%a0", /* write, evict last */
7165 }
7166 };
7168 bool write = INTVAL (operands[1]) != 0;
7169 bool lru = INTVAL (operands[2]) != 0;
7171 return alt[write][lru];
7172 }
7173 [(set_attr "type" "ild")])
7175 ;; Close the trap shadow of preceding instructions. This is generated
7176 ;; by alpha_reorg.
7178 (define_insn "trapb"
7179 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7180 ""
7181 "trapb"
7182 [(set_attr "type" "misc")])
7184 ;; No-op instructions used by machine-dependent reorg to preserve
7185 ;; alignment for instruction issue.
7186 ;; The Unicos/Mk assembler does not support these opcodes.
7188 (define_insn "nop"
7189 [(const_int 0)]
7190 ""
7191 "bis $31,$31,$31"
7192 [(set_attr "type" "ilog")])
7194 (define_insn "fnop"
7195 [(const_int 1)]
7196 "TARGET_FP"
7197 "cpys $f31,$f31,$f31"
7198 [(set_attr "type" "fcpys")])
7200 (define_insn "unop"
7201 [(const_int 2)]
7202 ""
7203 "ldq_u $31,0($30)")
7205 ;; On Unicos/Mk we use a macro for aligning code.
7207 (define_insn "realign"
7208 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7209 UNSPECV_REALIGN)]
7210 ""
7211 {
7212 if (TARGET_ABI_UNICOSMK)
7213 return "gcc@code@align %0";
7214 else
7215 return ".align %0 #realign";
7216 })
7217 \f
7218 ;; Instructions to be emitted from __builtins.
7220 (define_insn "builtin_cmpbge"
7221 [(set (match_operand:DI 0 "register_operand" "=r")
7222 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7223 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7224 UNSPEC_CMPBGE))]
7225 ""
7226 "cmpbge %r1,%2,%0"
7227 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7228 ;; actually differentiate between ILOG and ICMP in the schedule.
7229 [(set_attr "type" "icmp")])
7231 (define_expand "builtin_extbl"
7232 [(match_operand:DI 0 "register_operand" "")
7233 (match_operand:DI 1 "reg_or_0_operand" "")
7234 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7235 ""
7236 {
7237 rtx (*gen) (rtx, rtx, rtx, rtx);
7238 if (WORDS_BIG_ENDIAN)
7239 gen = gen_extxl_be;
7240 else
7241 gen = gen_extxl_le;
7242 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7243 DONE;
7244 })
7246 (define_expand "builtin_extwl"
7247 [(match_operand:DI 0 "register_operand" "")
7248 (match_operand:DI 1 "reg_or_0_operand" "")
7249 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7250 ""
7251 {
7252 rtx (*gen) (rtx, rtx, rtx, rtx);
7253 if (WORDS_BIG_ENDIAN)
7254 gen = gen_extxl_be;
7255 else
7256 gen = gen_extxl_le;
7257 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7258 DONE;
7259 })
7261 (define_expand "builtin_extll"
7262 [(match_operand:DI 0 "register_operand" "")
7263 (match_operand:DI 1 "reg_or_0_operand" "")
7264 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7265 ""
7266 {
7267 rtx (*gen) (rtx, rtx, rtx, rtx);
7268 if (WORDS_BIG_ENDIAN)
7269 gen = gen_extxl_be;
7270 else
7271 gen = gen_extxl_le;
7272 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7273 DONE;
7274 })
7276 (define_expand "builtin_extql"
7277 [(match_operand:DI 0 "register_operand" "")
7278 (match_operand:DI 1 "reg_or_0_operand" "")
7279 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7280 ""
7281 {
7282 rtx (*gen) (rtx, rtx, rtx, rtx);
7283 if (WORDS_BIG_ENDIAN)
7284 gen = gen_extxl_be;
7285 else
7286 gen = gen_extxl_le;
7287 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7288 DONE;
7289 })
7291 (define_expand "builtin_extwh"
7292 [(match_operand:DI 0 "register_operand" "")
7293 (match_operand:DI 1 "reg_or_0_operand" "")
7294 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7295 ""
7296 {
7297 rtx (*gen) (rtx, rtx, rtx);
7298 if (WORDS_BIG_ENDIAN)
7299 gen = gen_extwh_be;
7300 else
7301 gen = gen_extwh_le;
7302 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7303 DONE;
7304 })
7306 (define_expand "builtin_extlh"
7307 [(match_operand:DI 0 "register_operand" "")
7308 (match_operand:DI 1 "reg_or_0_operand" "")
7309 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7310 ""
7311 {
7312 rtx (*gen) (rtx, rtx, rtx);
7313 if (WORDS_BIG_ENDIAN)
7314 gen = gen_extlh_be;
7315 else
7316 gen = gen_extlh_le;
7317 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7318 DONE;
7319 })
7321 (define_expand "builtin_extqh"
7322 [(match_operand:DI 0 "register_operand" "")
7323 (match_operand:DI 1 "reg_or_0_operand" "")
7324 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7325 ""
7326 {
7327 rtx (*gen) (rtx, rtx, rtx);
7328 if (WORDS_BIG_ENDIAN)
7329 gen = gen_extqh_be;
7330 else
7331 gen = gen_extqh_le;
7332 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7333 DONE;
7334 })
7336 (define_expand "builtin_insbl"
7337 [(match_operand:DI 0 "register_operand" "")
7338 (match_operand:DI 1 "register_operand" "")
7339 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7340 ""
7341 {
7342 rtx (*gen) (rtx, rtx, rtx);
7343 if (WORDS_BIG_ENDIAN)
7344 gen = gen_insbl_be;
7345 else
7346 gen = gen_insbl_le;
7347 operands[1] = gen_lowpart (QImode, operands[1]);
7348 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7349 DONE;
7350 })
7352 (define_expand "builtin_inswl"
7353 [(match_operand:DI 0 "register_operand" "")
7354 (match_operand:DI 1 "register_operand" "")
7355 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7356 ""
7357 {
7358 rtx (*gen) (rtx, rtx, rtx);
7359 if (WORDS_BIG_ENDIAN)
7360 gen = gen_inswl_be;
7361 else
7362 gen = gen_inswl_le;
7363 operands[1] = gen_lowpart (HImode, operands[1]);
7364 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7365 DONE;
7366 })
7368 (define_expand "builtin_insll"
7369 [(match_operand:DI 0 "register_operand" "")
7370 (match_operand:DI 1 "register_operand" "")
7371 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7372 ""
7373 {
7374 rtx (*gen) (rtx, rtx, rtx);
7375 if (WORDS_BIG_ENDIAN)
7376 gen = gen_insll_be;
7377 else
7378 gen = gen_insll_le;
7379 operands[1] = gen_lowpart (SImode, operands[1]);
7380 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7381 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7382 DONE;
7383 })
7385 (define_expand "builtin_insql"
7386 [(match_operand:DI 0 "register_operand" "")
7387 (match_operand:DI 1 "reg_or_0_operand" "")
7388 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7389 ""
7390 {
7391 rtx (*gen) (rtx, rtx, rtx);
7392 if (WORDS_BIG_ENDIAN)
7393 gen = gen_insql_be;
7394 else
7395 gen = gen_insql_le;
7396 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7397 DONE;
7398 })
7400 (define_expand "builtin_inswh"
7401 [(match_operand:DI 0 "register_operand" "")
7402 (match_operand:DI 1 "register_operand" "")
7403 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7404 ""
7405 {
7406 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7407 DONE;
7408 })
7410 (define_expand "builtin_inslh"
7411 [(match_operand:DI 0 "register_operand" "")
7412 (match_operand:DI 1 "register_operand" "")
7413 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7414 ""
7415 {
7416 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7417 DONE;
7418 })
7420 (define_expand "builtin_insqh"
7421 [(match_operand:DI 0 "register_operand" "")
7422 (match_operand:DI 1 "register_operand" "")
7423 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7424 ""
7425 {
7426 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7427 DONE;
7428 })
7430 (define_expand "builtin_mskbl"
7431 [(match_operand:DI 0 "register_operand" "")
7432 (match_operand:DI 1 "reg_or_0_operand" "")
7433 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7434 ""
7435 {
7436 rtx (*gen) (rtx, rtx, rtx, rtx);
7437 rtx mask;
7438 if (WORDS_BIG_ENDIAN)
7439 gen = gen_mskxl_be;
7440 else
7441 gen = gen_mskxl_le;
7442 mask = GEN_INT (0xff);
7443 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7444 DONE;
7445 })
7447 (define_expand "builtin_mskwl"
7448 [(match_operand:DI 0 "register_operand" "")
7449 (match_operand:DI 1 "reg_or_0_operand" "")
7450 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7451 ""
7452 {
7453 rtx (*gen) (rtx, rtx, rtx, rtx);
7454 rtx mask;
7455 if (WORDS_BIG_ENDIAN)
7456 gen = gen_mskxl_be;
7457 else
7458 gen = gen_mskxl_le;
7459 mask = GEN_INT (0xffff);
7460 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7461 DONE;
7462 })
7464 (define_expand "builtin_mskll"
7465 [(match_operand:DI 0 "register_operand" "")
7466 (match_operand:DI 1 "reg_or_0_operand" "")
7467 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7468 ""
7469 {
7470 rtx (*gen) (rtx, rtx, rtx, rtx);
7471 rtx mask;
7472 if (WORDS_BIG_ENDIAN)
7473 gen = gen_mskxl_be;
7474 else
7475 gen = gen_mskxl_le;
7476 mask = immed_double_const (0xffffffff, 0, DImode);
7477 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7478 DONE;
7479 })
7481 (define_expand "builtin_mskql"
7482 [(match_operand:DI 0 "register_operand" "")
7483 (match_operand:DI 1 "reg_or_0_operand" "")
7484 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7485 ""
7486 {
7487 rtx (*gen) (rtx, rtx, rtx, rtx);
7488 rtx mask;
7489 if (WORDS_BIG_ENDIAN)
7490 gen = gen_mskxl_be;
7491 else
7492 gen = gen_mskxl_le;
7493 mask = constm1_rtx;
7494 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7495 DONE;
7496 })
7498 (define_expand "builtin_mskwh"
7499 [(match_operand:DI 0 "register_operand" "")
7500 (match_operand:DI 1 "register_operand" "")
7501 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7502 ""
7503 {
7504 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7505 DONE;
7506 })
7508 (define_expand "builtin_msklh"
7509 [(match_operand:DI 0 "register_operand" "")
7510 (match_operand:DI 1 "register_operand" "")
7511 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7512 ""
7513 {
7514 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7515 DONE;
7516 })
7518 (define_expand "builtin_mskqh"
7519 [(match_operand:DI 0 "register_operand" "")
7520 (match_operand:DI 1 "register_operand" "")
7521 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7522 ""
7523 {
7524 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7525 DONE;
7526 })
7528 (define_expand "builtin_zap"
7529 [(set (match_operand:DI 0 "register_operand" "")
7530 (and:DI (unspec:DI
7531 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7532 UNSPEC_ZAP)
7533 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7534 ""
7535 {
7536 if (CONST_INT_P (operands[2]))
7537 {
7538 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7540 if (mask == const0_rtx)
7541 {
7542 emit_move_insn (operands[0], const0_rtx);
7543 DONE;
7544 }
7545 if (mask == constm1_rtx)
7546 {
7547 emit_move_insn (operands[0], operands[1]);
7548 DONE;
7549 }
7551 operands[1] = force_reg (DImode, operands[1]);
7552 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7553 DONE;
7554 }
7556 operands[1] = force_reg (DImode, operands[1]);
7557 operands[2] = gen_lowpart (QImode, operands[2]);
7558 })
7560 (define_insn "*builtin_zap_1"
7561 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7562 (and:DI (unspec:DI
7563 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7564 UNSPEC_ZAP)
7565 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7566 ""
7567 "@
7568 #
7569 #
7570 bis $31,$31,%0
7571 zap %r1,%2,%0"
7572 [(set_attr "type" "shift,shift,ilog,shift")])
7574 (define_split
7575 [(set (match_operand:DI 0 "register_operand" "")
7576 (and:DI (unspec:DI
7577 [(match_operand:QI 2 "const_int_operand" "")]
7578 UNSPEC_ZAP)
7579 (match_operand:DI 1 "const_int_operand" "")))]
7580 ""
7581 [(const_int 0)]
7582 {
7583 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7584 if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask))
7585 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7586 else
7587 {
7588 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7589 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7590 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7591 c_hi & CONST_DOUBLE_HIGH (mask),
7592 DImode);
7593 }
7594 emit_move_insn (operands[0], operands[1]);
7595 DONE;
7596 })
7598 (define_split
7599 [(set (match_operand:DI 0 "register_operand" "")
7600 (and:DI (unspec:DI
7601 [(match_operand:QI 2 "const_int_operand" "")]
7602 UNSPEC_ZAP)
7603 (match_operand:DI 1 "register_operand" "")))]
7604 ""
7605 [(set (match_dup 0)
7606 (and:DI (match_dup 1) (match_dup 2)))]
7607 {
7608 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7609 if (operands[2] == const0_rtx)
7610 {
7611 emit_move_insn (operands[0], const0_rtx);
7612 DONE;
7613 }
7614 if (operands[2] == constm1_rtx)
7615 {
7616 emit_move_insn (operands[0], operands[1]);
7617 DONE;
7618 }
7619 })
7621 (define_expand "builtin_zapnot"
7622 [(set (match_operand:DI 0 "register_operand" "")
7623 (and:DI (unspec:DI
7624 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7625 UNSPEC_ZAP)
7626 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7627 ""
7628 {
7629 if (CONST_INT_P (operands[2]))
7630 {
7631 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7633 if (mask == const0_rtx)
7634 {
7635 emit_move_insn (operands[0], const0_rtx);
7636 DONE;
7637 }
7638 if (mask == constm1_rtx)
7639 {
7640 emit_move_insn (operands[0], operands[1]);
7641 DONE;
7642 }
7644 operands[1] = force_reg (DImode, operands[1]);
7645 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7646 DONE;
7647 }
7649 operands[1] = force_reg (DImode, operands[1]);
7650 operands[2] = gen_lowpart (QImode, operands[2]);
7651 })
7653 (define_insn "*builtin_zapnot_1"
7654 [(set (match_operand:DI 0 "register_operand" "=r")
7655 (and:DI (unspec:DI
7656 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7657 UNSPEC_ZAP)
7658 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7659 ""
7660 "zapnot %r1,%2,%0"
7661 [(set_attr "type" "shift")])
7663 (define_insn "builtin_amask"
7664 [(set (match_operand:DI 0 "register_operand" "=r")
7665 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7666 UNSPEC_AMASK))]
7667 ""
7668 "amask %1,%0"
7669 [(set_attr "type" "ilog")])
7671 (define_insn "builtin_implver"
7672 [(set (match_operand:DI 0 "register_operand" "=r")
7673 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7674 ""
7675 "implver %0"
7676 [(set_attr "type" "ilog")])
7678 (define_insn "builtin_rpcc"
7679 [(set (match_operand:DI 0 "register_operand" "=r")
7680 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7681 ""
7682 "rpcc %0"
7683 [(set_attr "type" "ilog")])
7685 (define_expand "builtin_minub8"
7686 [(match_operand:DI 0 "register_operand" "")
7687 (match_operand:DI 1 "reg_or_0_operand" "")
7688 (match_operand:DI 2 "reg_or_0_operand" "")]
7689 "TARGET_MAX"
7690 {
7691 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7692 operands[1], operands[2]);
7693 DONE;
7694 })
7696 (define_expand "builtin_minsb8"
7697 [(match_operand:DI 0 "register_operand" "")
7698 (match_operand:DI 1 "reg_or_0_operand" "")
7699 (match_operand:DI 2 "reg_or_0_operand" "")]
7700 "TARGET_MAX"
7701 {
7702 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7703 operands[1], operands[2]);
7704 DONE;
7705 })
7707 (define_expand "builtin_minuw4"
7708 [(match_operand:DI 0 "register_operand" "")
7709 (match_operand:DI 1 "reg_or_0_operand" "")
7710 (match_operand:DI 2 "reg_or_0_operand" "")]
7711 "TARGET_MAX"
7712 {
7713 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7714 operands[1], operands[2]);
7715 DONE;
7716 })
7718 (define_expand "builtin_minsw4"
7719 [(match_operand:DI 0 "register_operand" "")
7720 (match_operand:DI 1 "reg_or_0_operand" "")
7721 (match_operand:DI 2 "reg_or_0_operand" "")]
7722 "TARGET_MAX"
7723 {
7724 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7725 operands[1], operands[2]);
7726 DONE;
7727 })
7729 (define_expand "builtin_maxub8"
7730 [(match_operand:DI 0 "register_operand" "")
7731 (match_operand:DI 1 "reg_or_0_operand" "")
7732 (match_operand:DI 2 "reg_or_0_operand" "")]
7733 "TARGET_MAX"
7734 {
7735 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7736 operands[1], operands[2]);
7737 DONE;
7738 })
7740 (define_expand "builtin_maxsb8"
7741 [(match_operand:DI 0 "register_operand" "")
7742 (match_operand:DI 1 "reg_or_0_operand" "")
7743 (match_operand:DI 2 "reg_or_0_operand" "")]
7744 "TARGET_MAX"
7745 {
7746 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7747 operands[1], operands[2]);
7748 DONE;
7749 })
7751 (define_expand "builtin_maxuw4"
7752 [(match_operand:DI 0 "register_operand" "")
7753 (match_operand:DI 1 "reg_or_0_operand" "")
7754 (match_operand:DI 2 "reg_or_0_operand" "")]
7755 "TARGET_MAX"
7756 {
7757 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7758 operands[1], operands[2]);
7759 DONE;
7760 })
7762 (define_expand "builtin_maxsw4"
7763 [(match_operand:DI 0 "register_operand" "")
7764 (match_operand:DI 1 "reg_or_0_operand" "")
7765 (match_operand:DI 2 "reg_or_0_operand" "")]
7766 "TARGET_MAX"
7767 {
7768 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7769 operands[1], operands[2]);
7770 DONE;
7771 })
7773 (define_insn "builtin_perr"
7774 [(set (match_operand:DI 0 "register_operand" "=r")
7775 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7776 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7777 UNSPEC_PERR))]
7778 "TARGET_MAX"
7779 "perr %r1,%r2,%0"
7780 [(set_attr "type" "mvi")])
7782 (define_expand "builtin_pklb"
7783 [(set (match_operand:DI 0 "register_operand" "")
7784 (vec_concat:V8QI
7785 (vec_concat:V4QI
7786 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7787 (match_dup 2))
7788 (match_dup 3)))]
7789 "TARGET_MAX"
7790 {
7791 operands[0] = gen_lowpart (V8QImode, operands[0]);
7792 operands[1] = gen_lowpart (V2SImode, operands[1]);
7793 operands[2] = CONST0_RTX (V2QImode);
7794 operands[3] = CONST0_RTX (V4QImode);
7795 })
7797 (define_insn "*pklb"
7798 [(set (match_operand:V8QI 0 "register_operand" "=r")
7799 (vec_concat:V8QI
7800 (vec_concat:V4QI
7801 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7802 (match_operand:V2QI 2 "const0_operand" ""))
7803 (match_operand:V4QI 3 "const0_operand" "")))]
7804 "TARGET_MAX"
7805 "pklb %r1,%0"
7806 [(set_attr "type" "mvi")])
7808 (define_expand "builtin_pkwb"
7809 [(set (match_operand:DI 0 "register_operand" "")
7810 (vec_concat:V8QI
7811 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7812 (match_dup 2)))]
7813 "TARGET_MAX"
7814 {
7815 operands[0] = gen_lowpart (V8QImode, operands[0]);
7816 operands[1] = gen_lowpart (V4HImode, operands[1]);
7817 operands[2] = CONST0_RTX (V4QImode);
7818 })
7820 (define_insn "*pkwb"
7821 [(set (match_operand:V8QI 0 "register_operand" "=r")
7822 (vec_concat:V8QI
7823 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7824 (match_operand:V4QI 2 "const0_operand" "")))]
7825 "TARGET_MAX"
7826 "pkwb %r1,%0"
7827 [(set_attr "type" "mvi")])
7829 (define_expand "builtin_unpkbl"
7830 [(set (match_operand:DI 0 "register_operand" "")
7831 (zero_extend:V2SI
7832 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7833 (parallel [(const_int 0) (const_int 1)]))))]
7834 "TARGET_MAX"
7835 {
7836 operands[0] = gen_lowpart (V2SImode, operands[0]);
7837 operands[1] = gen_lowpart (V8QImode, operands[1]);
7838 })
7840 (define_insn "*unpkbl"
7841 [(set (match_operand:V2SI 0 "register_operand" "=r")
7842 (zero_extend:V2SI
7843 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7844 (parallel [(const_int 0) (const_int 1)]))))]
7845 "TARGET_MAX"
7846 "unpkbl %r1,%0"
7847 [(set_attr "type" "mvi")])
7849 (define_expand "builtin_unpkbw"
7850 [(set (match_operand:DI 0 "register_operand" "")
7851 (zero_extend:V4HI
7852 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7853 (parallel [(const_int 0)
7854 (const_int 1)
7855 (const_int 2)
7856 (const_int 3)]))))]
7857 "TARGET_MAX"
7858 {
7859 operands[0] = gen_lowpart (V4HImode, operands[0]);
7860 operands[1] = gen_lowpart (V8QImode, operands[1]);
7861 })
7863 (define_insn "*unpkbw"
7864 [(set (match_operand:V4HI 0 "register_operand" "=r")
7865 (zero_extend:V4HI
7866 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7867 (parallel [(const_int 0)
7868 (const_int 1)
7869 (const_int 2)
7870 (const_int 3)]))))]
7871 "TARGET_MAX"
7872 "unpkbw %r1,%0"
7873 [(set_attr "type" "mvi")])
7874 \f
7875 (include "sync.md")
7876 \f
7877 ;; The call patterns are at the end of the file because their
7878 ;; wildcard operand0 interferes with nice recognition.
7880 (define_insn "*call_value_osf_1_er_noreturn"
7881 [(set (match_operand 0 "" "")
7882 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7883 (match_operand 2 "" "")))
7884 (use (reg:DI 29))
7885 (clobber (reg:DI 26))]
7886 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7887 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7888 "@
7889 jsr $26,($27),0
7890 bsr $26,%1\t\t!samegp
7891 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
7892 [(set_attr "type" "jsr")
7893 (set_attr "length" "*,*,8")])
7895 (define_insn "*call_value_osf_1_er"
7896 [(set (match_operand 0 "" "")
7897 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7898 (match_operand 2 "" "")))
7899 (use (reg:DI 29))
7900 (clobber (reg:DI 26))]
7901 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7902 "@
7903 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7904 bsr $26,%1\t\t!samegp
7905 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7906 [(set_attr "type" "jsr")
7907 (set_attr "length" "12,*,16")])
7909 ;; We must use peep2 instead of a split because we need accurate life
7910 ;; information for $gp. Consider the case of { bar(); while (1); }.
7911 (define_peephole2
7912 [(parallel [(set (match_operand 0 "" "")
7913 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7914 (match_operand 2 "" "")))
7915 (use (reg:DI 29))
7916 (clobber (reg:DI 26))])]
7917 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7918 && ! samegp_function_operand (operands[1], Pmode)
7919 && (peep2_regno_dead_p (1, 29)
7920 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7921 [(parallel [(set (match_dup 0)
7922 (call (mem:DI (match_dup 3))
7923 (match_dup 2)))
7924 (use (reg:DI 29))
7925 (use (match_dup 1))
7926 (use (match_dup 4))
7927 (clobber (reg:DI 26))])]
7928 {
7929 if (CONSTANT_P (operands[1]))
7930 {
7931 operands[3] = gen_rtx_REG (Pmode, 27);
7932 operands[4] = GEN_INT (alpha_next_sequence_number++);
7933 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7934 operands[1], operands[4]));
7935 }
7936 else
7937 {
7938 operands[3] = operands[1];
7939 operands[1] = const0_rtx;
7940 operands[4] = const0_rtx;
7941 }
7942 })
7944 (define_peephole2
7945 [(parallel [(set (match_operand 0 "" "")
7946 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7947 (match_operand 2 "" "")))
7948 (use (reg:DI 29))
7949 (clobber (reg:DI 26))])]
7950 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7951 && ! samegp_function_operand (operands[1], Pmode)
7952 && ! (peep2_regno_dead_p (1, 29)
7953 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7954 [(parallel [(set (match_dup 0)
7955 (call (mem:DI (match_dup 3))
7956 (match_dup 2)))
7957 (set (match_dup 6)
7958 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
7959 (use (match_dup 1))
7960 (use (match_dup 5))
7961 (clobber (reg:DI 26))])
7962 (set (match_dup 6)
7963 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
7964 {
7965 if (CONSTANT_P (operands[1]))
7966 {
7967 operands[3] = gen_rtx_REG (Pmode, 27);
7968 operands[5] = GEN_INT (alpha_next_sequence_number++);
7969 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7970 operands[1], operands[5]));
7971 }
7972 else
7973 {
7974 operands[3] = operands[1];
7975 operands[1] = const0_rtx;
7976 operands[5] = const0_rtx;
7977 }
7978 operands[4] = GEN_INT (alpha_next_sequence_number++);
7979 operands[6] = pic_offset_table_rtx;
7980 })
7982 (define_insn "*call_value_osf_2_er_nogp"
7983 [(set (match_operand 0 "" "")
7984 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7985 (match_operand 2 "" "")))
7986 (use (reg:DI 29))
7987 (use (match_operand 3 "" ""))
7988 (use (match_operand 4 "" ""))
7989 (clobber (reg:DI 26))]
7990 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7991 "jsr $26,(%1),%3%J4"
7992 [(set_attr "type" "jsr")])
7994 (define_insn "*call_value_osf_2_er"
7995 [(set (match_operand 0 "" "")
7996 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7997 (match_operand 2 "" "")))
7998 (set (reg:DI 29)
7999 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")]
8000 UNSPEC_LDGP1))
8001 (use (match_operand 3 "" ""))
8002 (use (match_operand 4 "" ""))
8003 (clobber (reg:DI 26))]
8004 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8005 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
8006 [(set_attr "type" "jsr")
8007 (set_attr "cannot_copy" "true")
8008 (set_attr "length" "8")])
8010 (define_insn "*call_value_osf_1_noreturn"
8011 [(set (match_operand 0 "" "")
8012 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8013 (match_operand 2 "" "")))
8014 (use (reg:DI 29))
8015 (clobber (reg:DI 26))]
8016 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
8017 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8018 "@
8019 jsr $26,($27),0
8020 bsr $26,$%1..ng
8021 jsr $26,%1"
8022 [(set_attr "type" "jsr")
8023 (set_attr "length" "*,*,8")])
8025 (define_insn_and_split "call_value_osf_tlsgd"
8026 [(set (match_operand 0 "" "")
8027 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8028 (const_int 0)))
8029 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
8030 (use (reg:DI 29))
8031 (clobber (reg:DI 26))]
8032 "HAVE_AS_TLS"
8033 "#"
8034 "&& reload_completed"
8035 [(set (match_dup 3)
8036 (unspec:DI [(match_dup 5)
8037 (match_dup 1)
8038 (match_dup 2)] UNSPEC_LITERAL))
8039 (parallel [(set (match_dup 0)
8040 (call (mem:DI (match_dup 3))
8041 (const_int 0)))
8042 (set (match_dup 5)
8043 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8044 (use (match_dup 1))
8045 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
8046 (clobber (reg:DI 26))])
8047 (set (match_dup 5)
8048 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8049 {
8050 operands[3] = gen_rtx_REG (Pmode, 27);
8051 operands[4] = GEN_INT (alpha_next_sequence_number++);
8052 operands[5] = pic_offset_table_rtx;
8053 }
8054 [(set_attr "type" "multi")])
8056 (define_insn_and_split "call_value_osf_tlsldm"
8057 [(set (match_operand 0 "" "")
8058 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8059 (const_int 0)))
8060 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
8061 (use (reg:DI 29))
8062 (clobber (reg:DI 26))]
8063 "HAVE_AS_TLS"
8064 "#"
8065 "&& reload_completed"
8066 [(set (match_dup 3)
8067 (unspec:DI [(match_dup 5)
8068 (match_dup 1)
8069 (match_dup 2)] UNSPEC_LITERAL))
8070 (parallel [(set (match_dup 0)
8071 (call (mem:DI (match_dup 3))
8072 (const_int 0)))
8073 (set (match_dup 5)
8074 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8075 (use (match_dup 1))
8076 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
8077 (clobber (reg:DI 26))])
8078 (set (match_dup 5)
8079 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8080 {
8081 operands[3] = gen_rtx_REG (Pmode, 27);
8082 operands[4] = GEN_INT (alpha_next_sequence_number++);
8083 operands[5] = pic_offset_table_rtx;
8084 }
8085 [(set_attr "type" "multi")])
8087 (define_insn "*call_value_osf_1"
8088 [(set (match_operand 0 "" "")
8089 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8090 (match_operand 2 "" "")))
8091 (use (reg:DI 29))
8092 (clobber (reg:DI 26))]
8093 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8094 "@
8095 jsr $26,($27),0\;ldgp $29,0($26)
8096 bsr $26,$%1..ng
8097 jsr $26,%1\;ldgp $29,0($26)"
8098 [(set_attr "type" "jsr")
8099 (set_attr "length" "12,*,16")])
8101 (define_insn "*sibcall_value_osf_1_er"
8102 [(set (match_operand 0 "" "")
8103 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8104 (match_operand 2 "" "")))
8105 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8106 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8107 "@
8108 br $31,%1\t\t!samegp
8109 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8110 [(set_attr "type" "jsr")
8111 (set_attr "length" "*,8")])
8113 (define_insn "*sibcall_value_osf_1"
8114 [(set (match_operand 0 "" "")
8115 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8116 (match_operand 2 "" "")))
8117 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8118 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8119 "@
8120 br $31,$%1..ng
8121 lda $27,%1\;jmp $31,($27),%1"
8122 [(set_attr "type" "jsr")
8123 (set_attr "length" "*,8")])
8125 (define_insn "*call_value_nt_1"
8126 [(set (match_operand 0 "" "")
8127 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8128 (match_operand 2 "" "")))
8129 (clobber (reg:DI 26))]
8130 "TARGET_ABI_WINDOWS_NT"
8131 "@
8132 jsr $26,(%1)
8133 bsr $26,%1
8134 jsr $26,%1"
8135 [(set_attr "type" "jsr")
8136 (set_attr "length" "*,*,12")])
8138 ; GAS relies on the order and position of instructions output below in order
8139 ; to generate relocs for VMS link to potentially optimize the call.
8140 ; Please do not molest.
8141 (define_insn "*call_value_vms_1"
8142 [(set (match_operand 0 "" "")
8143 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8144 (match_operand 2 "" "")))
8145 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8146 (use (reg:DI 25))
8147 (use (reg:DI 26))
8148 (clobber (reg:DI 27))]
8149 "TARGET_ABI_OPEN_VMS"
8150 {
8151 switch (which_alternative)
8152 {
8153 case 0:
8154 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8155 case 1:
8156 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8157 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8158 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8159 default:
8160 gcc_unreachable ();
8161 }
8162 }
8163 [(set_attr "type" "jsr")
8164 (set_attr "length" "12,16")])
8166 (define_insn "*call_value_umk"
8167 [(set (match_operand 0 "" "")
8168 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8169 (match_operand 2 "" "")))
8170 (use (reg:DI 25))
8171 (clobber (reg:DI 26))]
8172 "TARGET_ABI_UNICOSMK"
8173 "jsr $26,(%1)"
8174 [(set_attr "type" "jsr")])