1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
47 #include "target-def.h"
49 #include "langhooks.h"
57 /* Define the specific costs for a given cpu. */
59 struct processor_costs
62 const int m
; /* cost of an M instruction. */
63 const int mghi
; /* cost of an MGHI instruction. */
64 const int mh
; /* cost of an MH instruction. */
65 const int mhi
; /* cost of an MHI instruction. */
66 const int ml
; /* cost of an ML instruction. */
67 const int mr
; /* cost of an MR instruction. */
68 const int ms
; /* cost of an MS instruction. */
69 const int msg
; /* cost of an MSG instruction. */
70 const int msgf
; /* cost of an MSGF instruction. */
71 const int msgfr
; /* cost of an MSGFR instruction. */
72 const int msgr
; /* cost of an MSGR instruction. */
73 const int msr
; /* cost of an MSR instruction. */
74 const int mult_df
; /* cost of multiplication in DFmode. */
77 const int sqxbr
; /* cost of square root in TFmode. */
78 const int sqdbr
; /* cost of square root in DFmode. */
79 const int sqebr
; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr
; /* cost of multiply and add in DFmode. */
82 const int maebr
; /* cost of multiply and add in SFmode. */
94 const struct processor_costs
*s390_cost
;
97 struct processor_costs z900_cost
=
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
129 struct processor_costs z990_cost
=
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
161 struct processor_costs z9_109_cost
=
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
193 struct processor_costs z10_cost
=
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
225 struct processor_costs z196_cost
=
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
257 struct processor_costs zEC12_cost
=
259 COSTS_N_INSNS (7), /* M */
260 COSTS_N_INSNS (5), /* MGHI */
261 COSTS_N_INSNS (5), /* MH */
262 COSTS_N_INSNS (5), /* MHI */
263 COSTS_N_INSNS (7), /* ML */
264 COSTS_N_INSNS (7), /* MR */
265 COSTS_N_INSNS (6), /* MS */
266 COSTS_N_INSNS (8), /* MSG */
267 COSTS_N_INSNS (6), /* MSGF */
268 COSTS_N_INSNS (6), /* MSGFR */
269 COSTS_N_INSNS (8), /* MSGR */
270 COSTS_N_INSNS (6), /* MSR */
271 COSTS_N_INSNS (1) , /* multiplication in DFmode */
272 COSTS_N_INSNS (40), /* MXBR B+40 */
273 COSTS_N_INSNS (100), /* SQXBR B+100 */
274 COSTS_N_INSNS (42), /* SQDBR B+42 */
275 COSTS_N_INSNS (28), /* SQEBR B+28 */
276 COSTS_N_INSNS (1), /* MADBR B */
277 COSTS_N_INSNS (1), /* MAEBR B */
278 COSTS_N_INSNS (131), /* DXBR B+131 */
279 COSTS_N_INSNS (29), /* DDBR */
280 COSTS_N_INSNS (22), /* DEBR */
281 COSTS_N_INSNS (160), /* DLGR cracked */
282 COSTS_N_INSNS (160), /* DLR cracked */
283 COSTS_N_INSNS (160), /* DR expanded */
284 COSTS_N_INSNS (160), /* DSGFR cracked */
285 COSTS_N_INSNS (160), /* DSGR cracked */
288 extern int reload_completed
;
290 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
291 static rtx last_scheduled_insn
;
293 /* Structure used to hold the components of a S/390 memory
294 address. A legitimate address on S/390 is of the general
296 base + index + displacement
297 where any of the components is optional.
299 base and index are registers of the class ADDR_REGS,
300 displacement is an unsigned 12-bit immediate constant. */
311 /* The following structure is embedded in the machine
312 specific part of struct function. */
314 struct GTY (()) s390_frame_layout
316 /* Offset within stack frame. */
317 HOST_WIDE_INT gprs_offset
;
318 HOST_WIDE_INT f0_offset
;
319 HOST_WIDE_INT f4_offset
;
320 HOST_WIDE_INT f8_offset
;
321 HOST_WIDE_INT backchain_offset
;
323 /* Number of first and last gpr where slots in the register
324 save area are reserved for. */
325 int first_save_gpr_slot
;
326 int last_save_gpr_slot
;
328 /* Number of first and last gpr to be saved, restored. */
330 int first_restore_gpr
;
332 int last_restore_gpr
;
334 /* Bits standing for floating point registers. Set, if the
335 respective register has to be saved. Starting with reg 16 (f0)
336 at the rightmost bit.
337 Bit 15 - 8 7 6 5 4 3 2 1 0
338 fpr 15 - 8 7 5 3 1 6 4 2 0
339 reg 31 - 24 23 22 21 20 19 18 17 16 */
340 unsigned int fpr_bitmap
;
342 /* Number of floating point registers f8-f15 which must be saved. */
345 /* Set if return address needs to be saved.
346 This flag is set by s390_return_addr_rtx if it could not use
347 the initial value of r14 and therefore depends on r14 saved
349 bool save_return_addr_p
;
351 /* Size of stack frame. */
352 HOST_WIDE_INT frame_size
;
355 /* Define the structure for the machine field in struct function. */
357 struct GTY(()) machine_function
359 struct s390_frame_layout frame_layout
;
361 /* Literal pool base register. */
364 /* True if we may need to perform branch splitting. */
365 bool split_branches_pending_p
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 bool has_landing_pad_p
;
373 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
375 #define cfun_frame_layout (cfun->machine->frame_layout)
376 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
377 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
378 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
379 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
381 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
384 /* Number of GPRs and FPRs used for argument passing. */
385 #define GP_ARG_NUM_REG 5
386 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
388 /* A couple of shortcuts. */
389 #define CONST_OK_FOR_J(x) \
390 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
391 #define CONST_OK_FOR_K(x) \
392 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
393 #define CONST_OK_FOR_Os(x) \
394 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
395 #define CONST_OK_FOR_Op(x) \
396 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
397 #define CONST_OK_FOR_On(x) \
398 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
400 #define REGNO_PAIR_OK(REGNO, MODE) \
401 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
403 /* That's the read ahead of the dynamic branch prediction unit in
404 bytes on a z10 (or higher) CPU. */
405 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
407 /* Return the alignment for LABEL. We default to the -falign-labels
408 value except for the literal pool base label. */
410 s390_label_align (rtx label
)
412 rtx prev_insn
= prev_active_insn (label
);
414 if (prev_insn
== NULL_RTX
)
417 prev_insn
= single_set (prev_insn
);
419 if (prev_insn
== NULL_RTX
)
422 prev_insn
= SET_SRC (prev_insn
);
424 /* Don't align literal pool base labels. */
425 if (GET_CODE (prev_insn
) == UNSPEC
426 && XINT (prev_insn
, 1) == UNSPEC_MAIN_BASE
)
430 return align_labels_log
;
433 static enum machine_mode
434 s390_libgcc_cmp_return_mode (void)
436 return TARGET_64BIT
? DImode
: SImode
;
439 static enum machine_mode
440 s390_libgcc_shift_count_mode (void)
442 return TARGET_64BIT
? DImode
: SImode
;
445 static enum machine_mode
446 s390_unwind_word_mode (void)
448 return TARGET_64BIT
? DImode
: SImode
;
451 /* Return true if the back end supports mode MODE. */
453 s390_scalar_mode_supported_p (enum machine_mode mode
)
455 /* In contrast to the default implementation reject TImode constants on 31bit
456 TARGET_ZARCH for ABI compliance. */
457 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
460 if (DECIMAL_FLOAT_MODE_P (mode
))
461 return default_decimal_float_supported_p ();
463 return default_scalar_mode_supported_p (mode
);
466 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
469 s390_set_has_landing_pad_p (bool value
)
471 cfun
->machine
->has_landing_pad_p
= value
;
474 /* If two condition code modes are compatible, return a condition code
475 mode which is compatible with both. Otherwise, return
478 static enum machine_mode
479 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
487 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
488 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
509 /* Return true if SET either doesn't set the CC register, or else
510 the source and destination have matching CC modes and that
511 CC mode is at least as constrained as REQ_MODE. */
514 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
516 enum machine_mode set_mode
;
518 gcc_assert (GET_CODE (set
) == SET
);
520 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
523 set_mode
= GET_MODE (SET_DEST (set
));
537 if (req_mode
!= set_mode
)
542 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
543 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
549 if (req_mode
!= CCAmode
)
557 return (GET_MODE (SET_SRC (set
)) == set_mode
);
560 /* Return true if every SET in INSN that sets the CC register
561 has source and destination with matching CC modes and that
562 CC mode is at least as constrained as REQ_MODE.
563 If REQ_MODE is VOIDmode, always return false. */
566 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
570 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
571 if (req_mode
== VOIDmode
)
574 if (GET_CODE (PATTERN (insn
)) == SET
)
575 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
577 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
578 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
580 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
581 if (GET_CODE (set
) == SET
)
582 if (!s390_match_ccmode_set (set
, req_mode
))
589 /* If a test-under-mask instruction can be used to implement
590 (compare (and ... OP1) OP2), return the CC mode required
591 to do that. Otherwise, return VOIDmode.
592 MIXED is true if the instruction can distinguish between
593 CC1 and CC2 for mixed selected bits (TMxx), it is false
594 if the instruction cannot (TM). */
597 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
601 /* ??? Fixme: should work on CONST_DOUBLE as well. */
602 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
605 /* Selected bits all zero: CC0.
606 e.g.: int a; if ((a & (16 + 128)) == 0) */
607 if (INTVAL (op2
) == 0)
610 /* Selected bits all one: CC3.
611 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
612 if (INTVAL (op2
) == INTVAL (op1
))
615 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
617 if ((a & (16 + 128)) == 16) -> CCT1
618 if ((a & (16 + 128)) == 128) -> CCT2 */
621 bit1
= exact_log2 (INTVAL (op2
));
622 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
623 if (bit0
!= -1 && bit1
!= -1)
624 return bit0
> bit1
? CCT1mode
: CCT2mode
;
630 /* Given a comparison code OP (EQ, NE, etc.) and the operands
631 OP0 and OP1 of a COMPARE, return the mode to be used for the
635 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
641 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
642 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
644 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
645 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
647 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
648 || GET_CODE (op1
) == NEG
)
649 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
652 if (GET_CODE (op0
) == AND
)
654 /* Check whether we can potentially do it via TM. */
655 enum machine_mode ccmode
;
656 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
657 if (ccmode
!= VOIDmode
)
659 /* Relax CCTmode to CCZmode to allow fall-back to AND
660 if that turns out to be beneficial. */
661 return ccmode
== CCTmode
? CCZmode
: ccmode
;
665 if (register_operand (op0
, HImode
)
666 && GET_CODE (op1
) == CONST_INT
667 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
669 if (register_operand (op0
, QImode
)
670 && GET_CODE (op1
) == CONST_INT
671 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
680 /* The only overflow condition of NEG and ABS happens when
681 -INT_MAX is used as parameter, which stays negative. So
682 we have an overflow from a positive value to a negative.
683 Using CCAP mode the resulting cc can be used for comparisons. */
684 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
685 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
688 /* If constants are involved in an add instruction it is possible to use
689 the resulting cc for comparisons with zero. Knowing the sign of the
690 constant the overflow behavior gets predictable. e.g.:
691 int a, b; if ((b = a + c) > 0)
692 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
693 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
694 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
696 if (INTVAL (XEXP((op0
), 1)) < 0)
710 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
711 && GET_CODE (op1
) != CONST_INT
)
717 if (GET_CODE (op0
) == PLUS
718 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
721 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
722 && GET_CODE (op1
) != CONST_INT
)
728 if (GET_CODE (op0
) == MINUS
729 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
732 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
733 && GET_CODE (op1
) != CONST_INT
)
742 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
743 that we can implement more efficiently. */
746 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
748 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
749 if ((*code
== EQ
|| *code
== NE
)
750 && *op1
== const0_rtx
751 && GET_CODE (*op0
) == ZERO_EXTRACT
752 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
753 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
754 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
756 rtx inner
= XEXP (*op0
, 0);
757 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
758 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
759 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
761 if (len
> 0 && len
< modesize
762 && pos
>= 0 && pos
+ len
<= modesize
763 && modesize
<= HOST_BITS_PER_WIDE_INT
)
765 unsigned HOST_WIDE_INT block
;
766 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
767 block
<<= modesize
- pos
- len
;
769 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
770 gen_int_mode (block
, GET_MODE (inner
)));
774 /* Narrow AND of memory against immediate to enable TM. */
775 if ((*code
== EQ
|| *code
== NE
)
776 && *op1
== const0_rtx
777 && GET_CODE (*op0
) == AND
778 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
779 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
781 rtx inner
= XEXP (*op0
, 0);
782 rtx mask
= XEXP (*op0
, 1);
784 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
785 if (GET_CODE (inner
) == SUBREG
786 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
787 && (GET_MODE_SIZE (GET_MODE (inner
))
788 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
790 & GET_MODE_MASK (GET_MODE (inner
))
791 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
793 inner
= SUBREG_REG (inner
);
795 /* Do not change volatile MEMs. */
796 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
798 int part
= s390_single_part (XEXP (*op0
, 1),
799 GET_MODE (inner
), QImode
, 0);
802 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
803 inner
= adjust_address_nv (inner
, QImode
, part
);
804 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
809 /* Narrow comparisons against 0xffff to HImode if possible. */
810 if ((*code
== EQ
|| *code
== NE
)
811 && GET_CODE (*op1
) == CONST_INT
812 && INTVAL (*op1
) == 0xffff
813 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
814 && (nonzero_bits (*op0
, GET_MODE (*op0
))
815 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
817 *op0
= gen_lowpart (HImode
, *op0
);
821 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
822 if (GET_CODE (*op0
) == UNSPEC
823 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
824 && XVECLEN (*op0
, 0) == 1
825 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
826 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
827 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
828 && *op1
== const0_rtx
)
830 enum rtx_code new_code
= UNKNOWN
;
833 case EQ
: new_code
= EQ
; break;
834 case NE
: new_code
= NE
; break;
835 case LT
: new_code
= GTU
; break;
836 case GT
: new_code
= LTU
; break;
837 case LE
: new_code
= GEU
; break;
838 case GE
: new_code
= LEU
; break;
842 if (new_code
!= UNKNOWN
)
844 *op0
= XVECEXP (*op0
, 0, 0);
849 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
850 if (GET_CODE (*op0
) == UNSPEC
851 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
852 && XVECLEN (*op0
, 0) == 1
853 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
854 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
855 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
856 && *op1
== const0_rtx
)
858 enum rtx_code new_code
= UNKNOWN
;
861 case EQ
: new_code
= EQ
; break;
862 case NE
: new_code
= NE
; break;
866 if (new_code
!= UNKNOWN
)
868 *op0
= XVECEXP (*op0
, 0, 0);
873 /* Simplify cascaded EQ, NE with const0_rtx. */
874 if ((*code
== NE
|| *code
== EQ
)
875 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
876 && GET_MODE (*op0
) == SImode
877 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
878 && REG_P (XEXP (*op0
, 0))
879 && XEXP (*op0
, 1) == const0_rtx
880 && *op1
== const0_rtx
)
882 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
883 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
887 *op0
= XEXP (*op0
, 0);
890 /* Prefer register over memory as first operand. */
891 if (MEM_P (*op0
) && REG_P (*op1
))
893 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
894 *code
= swap_condition (*code
);
898 /* Emit a compare instruction suitable to implement the comparison
899 OP0 CODE OP1. Return the correct condition RTL to be placed in
900 the IF_THEN_ELSE of the conditional branch testing the result. */
903 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
905 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
908 /* Do not output a redundant compare instruction if a compare_and_swap
909 pattern already computed the result and the machine modes are compatible. */
910 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
912 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
918 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
919 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
922 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
925 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
927 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
928 conditional branch testing the result. */
931 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
932 rtx cmp
, rtx new_rtx
)
934 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
, new_rtx
));
935 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
),
939 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
940 unconditional jump, else a conditional jump under condition COND. */
943 s390_emit_jump (rtx target
, rtx cond
)
947 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
949 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
951 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
952 emit_jump_insn (insn
);
955 /* Return branch condition mask to implement a branch
956 specified by CODE. Return -1 for invalid comparisons. */
959 s390_branch_condition_mask (rtx code
)
961 const int CC0
= 1 << 3;
962 const int CC1
= 1 << 2;
963 const int CC2
= 1 << 1;
964 const int CC3
= 1 << 0;
966 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
967 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
968 gcc_assert (XEXP (code
, 1) == const0_rtx
);
970 switch (GET_MODE (XEXP (code
, 0)))
974 switch (GET_CODE (code
))
977 case NE
: return CC1
| CC2
| CC3
;
983 switch (GET_CODE (code
))
986 case NE
: return CC0
| CC2
| CC3
;
992 switch (GET_CODE (code
))
995 case NE
: return CC0
| CC1
| CC3
;
1001 switch (GET_CODE (code
))
1003 case EQ
: return CC3
;
1004 case NE
: return CC0
| CC1
| CC2
;
1010 switch (GET_CODE (code
))
1012 case EQ
: return CC0
| CC2
;
1013 case NE
: return CC1
| CC3
;
1019 switch (GET_CODE (code
))
1021 case LTU
: return CC2
| CC3
; /* carry */
1022 case GEU
: return CC0
| CC1
; /* no carry */
1028 switch (GET_CODE (code
))
1030 case GTU
: return CC0
| CC1
; /* borrow */
1031 case LEU
: return CC2
| CC3
; /* no borrow */
1037 switch (GET_CODE (code
))
1039 case EQ
: return CC0
| CC2
;
1040 case NE
: return CC1
| CC3
;
1041 case LTU
: return CC1
;
1042 case GTU
: return CC3
;
1043 case LEU
: return CC1
| CC2
;
1044 case GEU
: return CC2
| CC3
;
1049 switch (GET_CODE (code
))
1051 case EQ
: return CC0
;
1052 case NE
: return CC1
| CC2
| CC3
;
1053 case LTU
: return CC1
;
1054 case GTU
: return CC2
;
1055 case LEU
: return CC0
| CC1
;
1056 case GEU
: return CC0
| CC2
;
1062 switch (GET_CODE (code
))
1064 case EQ
: return CC0
;
1065 case NE
: return CC2
| CC1
| CC3
;
1066 case LTU
: return CC2
;
1067 case GTU
: return CC1
;
1068 case LEU
: return CC0
| CC2
;
1069 case GEU
: return CC0
| CC1
;
1075 switch (GET_CODE (code
))
1077 case EQ
: return CC0
;
1078 case NE
: return CC1
| CC2
| CC3
;
1079 case LT
: return CC1
| CC3
;
1080 case GT
: return CC2
;
1081 case LE
: return CC0
| CC1
| CC3
;
1082 case GE
: return CC0
| CC2
;
1088 switch (GET_CODE (code
))
1090 case EQ
: return CC0
;
1091 case NE
: return CC1
| CC2
| CC3
;
1092 case LT
: return CC1
;
1093 case GT
: return CC2
| CC3
;
1094 case LE
: return CC0
| CC1
;
1095 case GE
: return CC0
| CC2
| CC3
;
1101 switch (GET_CODE (code
))
1103 case EQ
: return CC0
;
1104 case NE
: return CC1
| CC2
| CC3
;
1105 case LT
: return CC1
;
1106 case GT
: return CC2
;
1107 case LE
: return CC0
| CC1
;
1108 case GE
: return CC0
| CC2
;
1109 case UNORDERED
: return CC3
;
1110 case ORDERED
: return CC0
| CC1
| CC2
;
1111 case UNEQ
: return CC0
| CC3
;
1112 case UNLT
: return CC1
| CC3
;
1113 case UNGT
: return CC2
| CC3
;
1114 case UNLE
: return CC0
| CC1
| CC3
;
1115 case UNGE
: return CC0
| CC2
| CC3
;
1116 case LTGT
: return CC1
| CC2
;
1122 switch (GET_CODE (code
))
1124 case EQ
: return CC0
;
1125 case NE
: return CC2
| CC1
| CC3
;
1126 case LT
: return CC2
;
1127 case GT
: return CC1
;
1128 case LE
: return CC0
| CC2
;
1129 case GE
: return CC0
| CC1
;
1130 case UNORDERED
: return CC3
;
1131 case ORDERED
: return CC0
| CC2
| CC1
;
1132 case UNEQ
: return CC0
| CC3
;
1133 case UNLT
: return CC2
| CC3
;
1134 case UNGT
: return CC1
| CC3
;
1135 case UNLE
: return CC0
| CC2
| CC3
;
1136 case UNGE
: return CC0
| CC1
| CC3
;
1137 case LTGT
: return CC2
| CC1
;
1148 /* Return branch condition mask to implement a compare and branch
1149 specified by CODE. Return -1 for invalid comparisons. */
1152 s390_compare_and_branch_condition_mask (rtx code
)
1154 const int CC0
= 1 << 3;
1155 const int CC1
= 1 << 2;
1156 const int CC2
= 1 << 1;
1158 switch (GET_CODE (code
))
1182 /* If INV is false, return assembler mnemonic string to implement
1183 a branch specified by CODE. If INV is true, return mnemonic
1184 for the corresponding inverted branch. */
1187 s390_branch_condition_mnemonic (rtx code
, int inv
)
1191 static const char *const mnemonic
[16] =
1193 NULL
, "o", "h", "nle",
1194 "l", "nhe", "lh", "ne",
1195 "e", "nlh", "he", "nl",
1196 "le", "nh", "no", NULL
1199 if (GET_CODE (XEXP (code
, 0)) == REG
1200 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1201 && XEXP (code
, 1) == const0_rtx
)
1202 mask
= s390_branch_condition_mask (code
);
1204 mask
= s390_compare_and_branch_condition_mask (code
);
1206 gcc_assert (mask
>= 0);
1211 gcc_assert (mask
>= 1 && mask
<= 14);
1213 return mnemonic
[mask
];
1216 /* Return the part of op which has a value different from def.
1217 The size of the part is determined by mode.
1218 Use this function only if you already know that op really
1219 contains such a part. */
1221 unsigned HOST_WIDE_INT
1222 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1224 unsigned HOST_WIDE_INT value
= 0;
1225 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1226 int part_bits
= GET_MODE_BITSIZE (mode
);
1227 unsigned HOST_WIDE_INT part_mask
1228 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1231 for (i
= 0; i
< max_parts
; i
++)
1234 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1236 value
>>= part_bits
;
1238 if ((value
& part_mask
) != (def
& part_mask
))
1239 return value
& part_mask
;
1245 /* If OP is an integer constant of mode MODE with exactly one
1246 part of mode PART_MODE unequal to DEF, return the number of that
1247 part. Otherwise, return -1. */
1250 s390_single_part (rtx op
,
1251 enum machine_mode mode
,
1252 enum machine_mode part_mode
,
1255 unsigned HOST_WIDE_INT value
= 0;
1256 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1257 unsigned HOST_WIDE_INT part_mask
1258 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1261 if (GET_CODE (op
) != CONST_INT
)
1264 for (i
= 0; i
< n_parts
; i
++)
1267 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1269 value
>>= GET_MODE_BITSIZE (part_mode
);
1271 if ((value
& part_mask
) != (def
& part_mask
))
1279 return part
== -1 ? -1 : n_parts
- 1 - part
;
1282 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1283 bits and no other bits are set in IN. POS and LENGTH can be used
1284 to obtain the start position and the length of the bitfield.
1286 POS gives the position of the first bit of the bitfield counting
1287 from the lowest order bit starting with zero. In order to use this
1288 value for S/390 instructions this has to be converted to "bits big
1292 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1293 int *pos
, int *length
)
1298 unsigned HOST_WIDE_INT mask
= 1ULL;
1299 bool contiguous
= false;
1301 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1325 /* Calculate a mask for all bits beyond the contiguous bits. */
1326 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1331 if (tmp_length
+ tmp_pos
- 1 > size
)
1335 *length
= tmp_length
;
1343 /* Check whether we can (and want to) split a double-word
1344 move in mode MODE from SRC to DST into two single-word
1345 moves, moving the subword FIRST_SUBWORD first. */
1348 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1350 /* Floating point registers cannot be split. */
1351 if (FP_REG_P (src
) || FP_REG_P (dst
))
1354 /* We don't need to split if operands are directly accessible. */
1355 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1358 /* Non-offsettable memory references cannot be split. */
1359 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1360 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1363 /* Moving the first subword must not clobber a register
1364 needed to move the second subword. */
1365 if (register_operand (dst
, mode
))
1367 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1368 if (reg_overlap_mentioned_p (subreg
, src
))
1375 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1376 and [MEM2, MEM2 + SIZE] do overlap and false
1380 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1382 rtx addr1
, addr2
, addr_delta
;
1383 HOST_WIDE_INT delta
;
1385 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1391 addr1
= XEXP (mem1
, 0);
1392 addr2
= XEXP (mem2
, 0);
1394 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1396 /* This overlapping check is used by peepholes merging memory block operations.
1397 Overlapping operations would otherwise be recognized by the S/390 hardware
1398 and would fall back to a slower implementation. Allowing overlapping
1399 operations would lead to slow code but not to wrong code. Therefore we are
1400 somewhat optimistic if we cannot prove that the memory blocks are
1402 That's why we return false here although this may accept operations on
1403 overlapping memory areas. */
1404 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1407 delta
= INTVAL (addr_delta
);
1410 || (delta
> 0 && delta
< size
)
1411 || (delta
< 0 && -delta
< size
))
1417 /* Check whether the address of memory reference MEM2 equals exactly
1418 the address of memory reference MEM1 plus DELTA. Return true if
1419 we can prove this to be the case, false otherwise. */
1422 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1424 rtx addr1
, addr2
, addr_delta
;
1426 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1429 addr1
= XEXP (mem1
, 0);
1430 addr2
= XEXP (mem2
, 0);
1432 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1433 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1439 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1442 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1445 enum machine_mode wmode
= mode
;
1446 rtx dst
= operands
[0];
1447 rtx src1
= operands
[1];
1448 rtx src2
= operands
[2];
1451 /* If we cannot handle the operation directly, use a temp register. */
1452 if (!s390_logical_operator_ok_p (operands
))
1453 dst
= gen_reg_rtx (mode
);
1455 /* QImode and HImode patterns make sense only if we have a destination
1456 in memory. Otherwise perform the operation in SImode. */
1457 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1460 /* Widen operands if required. */
1463 if (GET_CODE (dst
) == SUBREG
1464 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1466 else if (REG_P (dst
))
1467 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1469 dst
= gen_reg_rtx (wmode
);
1471 if (GET_CODE (src1
) == SUBREG
1472 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1474 else if (GET_MODE (src1
) != VOIDmode
)
1475 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1477 if (GET_CODE (src2
) == SUBREG
1478 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1480 else if (GET_MODE (src2
) != VOIDmode
)
1481 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1484 /* Emit the instruction. */
1485 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1486 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1487 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1489 /* Fix up the destination if needed. */
1490 if (dst
!= operands
[0])
1491 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1494 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1497 s390_logical_operator_ok_p (rtx
*operands
)
1499 /* If the destination operand is in memory, it needs to coincide
1500 with one of the source operands. After reload, it has to be
1501 the first source operand. */
1502 if (GET_CODE (operands
[0]) == MEM
)
1503 return rtx_equal_p (operands
[0], operands
[1])
1504 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1509 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1510 operand IMMOP to switch from SS to SI type instructions. */
1513 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1515 int def
= code
== AND
? -1 : 0;
1519 gcc_assert (GET_CODE (*memop
) == MEM
);
1520 gcc_assert (!MEM_VOLATILE_P (*memop
));
1522 mask
= s390_extract_part (*immop
, QImode
, def
);
1523 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1524 gcc_assert (part
>= 0);
1526 *memop
= adjust_address (*memop
, QImode
, part
);
1527 *immop
= gen_int_mode (mask
, QImode
);
1531 /* How to allocate a 'struct machine_function'. */
1533 static struct machine_function
*
1534 s390_init_machine_status (void)
1536 return ggc_alloc_cleared_machine_function ();
1540 s390_option_override (void)
1542 /* Set up function hooks. */
1543 init_machine_status
= s390_init_machine_status
;
1545 /* Architecture mode defaults according to ABI. */
1546 if (!(target_flags_explicit
& MASK_ZARCH
))
1549 target_flags
|= MASK_ZARCH
;
1551 target_flags
&= ~MASK_ZARCH
;
1554 /* Set the march default in case it hasn't been specified on
1556 if (s390_arch
== PROCESSOR_max
)
1558 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1559 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
1560 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
1563 /* Determine processor to tune for. */
1564 if (s390_tune
== PROCESSOR_max
)
1566 s390_tune
= s390_arch
;
1567 s390_tune_flags
= s390_arch_flags
;
1570 /* Sanity checks. */
1571 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1572 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1573 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1574 error ("64-bit ABI not supported in ESA/390 mode");
1576 /* Use hardware DFP if available and not explicitly disabled by
1577 user. E.g. with -m31 -march=z10 -mzarch */
1578 if (!(target_flags_explicit
& MASK_HARD_DFP
) && TARGET_DFP
)
1579 target_flags
|= MASK_HARD_DFP
;
1581 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1583 if (target_flags_explicit
& MASK_HARD_DFP
)
1585 if (!TARGET_CPU_DFP
)
1586 error ("hardware decimal floating point instructions"
1587 " not available on %s", s390_arch_string
);
1589 error ("hardware decimal floating point instructions"
1590 " not available in ESA/390 mode");
1593 target_flags
&= ~MASK_HARD_DFP
;
1596 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1598 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1599 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1601 target_flags
&= ~MASK_HARD_DFP
;
1604 /* Set processor cost function. */
1607 case PROCESSOR_2084_Z990
:
1608 s390_cost
= &z990_cost
;
1610 case PROCESSOR_2094_Z9_109
:
1611 s390_cost
= &z9_109_cost
;
1613 case PROCESSOR_2097_Z10
:
1614 s390_cost
= &z10_cost
;
1616 case PROCESSOR_2817_Z196
:
1617 s390_cost
= &z196_cost
;
1619 case PROCESSOR_2827_ZEC12
:
1620 s390_cost
= &zEC12_cost
;
1623 s390_cost
= &z900_cost
;
1626 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1627 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1630 if (s390_stack_size
)
1632 if (s390_stack_guard
>= s390_stack_size
)
1633 error ("stack size must be greater than the stack guard value");
1634 else if (s390_stack_size
> 1 << 16)
1635 error ("stack size must not be greater than 64k");
1637 else if (s390_stack_guard
)
1638 error ("-mstack-guard implies use of -mstack-size");
1640 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1641 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1642 target_flags
|= MASK_LONG_DOUBLE_128
;
1645 if (s390_tune
== PROCESSOR_2097_Z10
1646 || s390_tune
== PROCESSOR_2817_Z196
1647 || s390_tune
== PROCESSOR_2827_ZEC12
)
1649 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1650 global_options
.x_param_values
,
1651 global_options_set
.x_param_values
);
1652 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1653 global_options
.x_param_values
,
1654 global_options_set
.x_param_values
);
1655 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1656 global_options
.x_param_values
,
1657 global_options_set
.x_param_values
);
1658 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1659 global_options
.x_param_values
,
1660 global_options_set
.x_param_values
);
1663 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1664 global_options
.x_param_values
,
1665 global_options_set
.x_param_values
);
1666 /* values for loop prefetching */
1667 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1668 global_options
.x_param_values
,
1669 global_options_set
.x_param_values
);
1670 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1671 global_options
.x_param_values
,
1672 global_options_set
.x_param_values
);
1673 /* s390 has more than 2 levels and the size is much larger. Since
1674 we are always running virtualized assume that we only get a small
1675 part of the caches above l1. */
1676 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1677 global_options
.x_param_values
,
1678 global_options_set
.x_param_values
);
1679 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1680 global_options
.x_param_values
,
1681 global_options_set
.x_param_values
);
1682 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1683 global_options
.x_param_values
,
1684 global_options_set
.x_param_values
);
1686 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1687 requires the arch flags to be evaluated already. Since prefetching
1688 is beneficial on s390, we enable it if available. */
1689 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1690 flag_prefetch_loop_arrays
= 1;
1692 /* Use the alternative scheduling-pressure algorithm by default. */
1693 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
1694 global_options
.x_param_values
,
1695 global_options_set
.x_param_values
);
1699 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1700 debuggers do not yet support DWARF 3/4. */
1701 if (!global_options_set
.x_dwarf_strict
)
1703 if (!global_options_set
.x_dwarf_version
)
1708 /* Map for smallest class containing reg regno. */
1710 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1711 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1712 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1713 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1714 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1715 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1716 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1717 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1718 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1719 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1720 ACCESS_REGS
, ACCESS_REGS
1723 /* Return attribute type of insn. */
1725 static enum attr_type
1726 s390_safe_attr_type (rtx insn
)
1728 if (recog_memoized (insn
) >= 0)
1729 return get_attr_type (insn
);
1734 /* Return true if DISP is a valid short displacement. */
1737 s390_short_displacement (rtx disp
)
1739 /* No displacement is OK. */
1743 /* Without the long displacement facility we don't need to
1744 distingiush between long and short displacement. */
1745 if (!TARGET_LONG_DISPLACEMENT
)
1748 /* Integer displacement in range. */
1749 if (GET_CODE (disp
) == CONST_INT
)
1750 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1752 /* GOT offset is not OK, the GOT can be large. */
1753 if (GET_CODE (disp
) == CONST
1754 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1755 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1756 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1759 /* All other symbolic constants are literal pool references,
1760 which are OK as the literal pool must be small. */
1761 if (GET_CODE (disp
) == CONST
)
1767 /* Decompose a RTL expression ADDR for a memory address into
1768 its components, returned in OUT.
1770 Returns false if ADDR is not a valid memory address, true
1771 otherwise. If OUT is NULL, don't return the components,
1772 but check for validity only.
1774 Note: Only addresses in canonical form are recognized.
1775 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1776 canonical form so that they will be recognized. */
1779 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1781 HOST_WIDE_INT offset
= 0;
1782 rtx base
= NULL_RTX
;
1783 rtx indx
= NULL_RTX
;
1784 rtx disp
= NULL_RTX
;
1786 bool pointer
= false;
1787 bool base_ptr
= false;
1788 bool indx_ptr
= false;
1789 bool literal_pool
= false;
1791 /* We may need to substitute the literal pool base register into the address
1792 below. However, at this point we do not know which register is going to
1793 be used as base, so we substitute the arg pointer register. This is going
1794 to be treated as holding a pointer below -- it shouldn't be used for any
1796 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1798 /* Decompose address into base + index + displacement. */
1800 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1803 else if (GET_CODE (addr
) == PLUS
)
1805 rtx op0
= XEXP (addr
, 0);
1806 rtx op1
= XEXP (addr
, 1);
1807 enum rtx_code code0
= GET_CODE (op0
);
1808 enum rtx_code code1
= GET_CODE (op1
);
1810 if (code0
== REG
|| code0
== UNSPEC
)
1812 if (code1
== REG
|| code1
== UNSPEC
)
1814 indx
= op0
; /* index + base */
1820 base
= op0
; /* base + displacement */
1825 else if (code0
== PLUS
)
1827 indx
= XEXP (op0
, 0); /* index + base + disp */
1828 base
= XEXP (op0
, 1);
1839 disp
= addr
; /* displacement */
1841 /* Extract integer part of displacement. */
1845 if (GET_CODE (disp
) == CONST_INT
)
1847 offset
= INTVAL (disp
);
1850 else if (GET_CODE (disp
) == CONST
1851 && GET_CODE (XEXP (disp
, 0)) == PLUS
1852 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1854 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1855 disp
= XEXP (XEXP (disp
, 0), 0);
1859 /* Strip off CONST here to avoid special case tests later. */
1860 if (disp
&& GET_CODE (disp
) == CONST
)
1861 disp
= XEXP (disp
, 0);
1863 /* We can convert literal pool addresses to
1864 displacements by basing them off the base register. */
1865 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1867 /* Either base or index must be free to hold the base register. */
1869 base
= fake_pool_base
, literal_pool
= true;
1871 indx
= fake_pool_base
, literal_pool
= true;
1875 /* Mark up the displacement. */
1876 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1877 UNSPEC_LTREL_OFFSET
);
1880 /* Validate base register. */
1883 if (GET_CODE (base
) == UNSPEC
)
1884 switch (XINT (base
, 1))
1888 disp
= gen_rtx_UNSPEC (Pmode
,
1889 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1890 UNSPEC_LTREL_OFFSET
);
1894 base
= XVECEXP (base
, 0, 1);
1897 case UNSPEC_LTREL_BASE
:
1898 if (XVECLEN (base
, 0) == 1)
1899 base
= fake_pool_base
, literal_pool
= true;
1901 base
= XVECEXP (base
, 0, 1);
1909 || (GET_MODE (base
) != SImode
1910 && GET_MODE (base
) != Pmode
))
1913 if (REGNO (base
) == STACK_POINTER_REGNUM
1914 || REGNO (base
) == FRAME_POINTER_REGNUM
1915 || ((reload_completed
|| reload_in_progress
)
1916 && frame_pointer_needed
1917 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1918 || REGNO (base
) == ARG_POINTER_REGNUM
1920 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1921 pointer
= base_ptr
= true;
1923 if ((reload_completed
|| reload_in_progress
)
1924 && base
== cfun
->machine
->base_reg
)
1925 pointer
= base_ptr
= literal_pool
= true;
1928 /* Validate index register. */
1931 if (GET_CODE (indx
) == UNSPEC
)
1932 switch (XINT (indx
, 1))
1936 disp
= gen_rtx_UNSPEC (Pmode
,
1937 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1938 UNSPEC_LTREL_OFFSET
);
1942 indx
= XVECEXP (indx
, 0, 1);
1945 case UNSPEC_LTREL_BASE
:
1946 if (XVECLEN (indx
, 0) == 1)
1947 indx
= fake_pool_base
, literal_pool
= true;
1949 indx
= XVECEXP (indx
, 0, 1);
1957 || (GET_MODE (indx
) != SImode
1958 && GET_MODE (indx
) != Pmode
))
1961 if (REGNO (indx
) == STACK_POINTER_REGNUM
1962 || REGNO (indx
) == FRAME_POINTER_REGNUM
1963 || ((reload_completed
|| reload_in_progress
)
1964 && frame_pointer_needed
1965 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1966 || REGNO (indx
) == ARG_POINTER_REGNUM
1968 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1969 pointer
= indx_ptr
= true;
1971 if ((reload_completed
|| reload_in_progress
)
1972 && indx
== cfun
->machine
->base_reg
)
1973 pointer
= indx_ptr
= literal_pool
= true;
1976 /* Prefer to use pointer as base, not index. */
1977 if (base
&& indx
&& !base_ptr
1978 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1985 /* Validate displacement. */
1988 /* If virtual registers are involved, the displacement will change later
1989 anyway as the virtual registers get eliminated. This could make a
1990 valid displacement invalid, but it is more likely to make an invalid
1991 displacement valid, because we sometimes access the register save area
1992 via negative offsets to one of those registers.
1993 Thus we don't check the displacement for validity here. If after
1994 elimination the displacement turns out to be invalid after all,
1995 this is fixed up by reload in any case. */
1996 if (base
!= arg_pointer_rtx
1997 && indx
!= arg_pointer_rtx
1998 && base
!= return_address_pointer_rtx
1999 && indx
!= return_address_pointer_rtx
2000 && base
!= frame_pointer_rtx
2001 && indx
!= frame_pointer_rtx
2002 && base
!= virtual_stack_vars_rtx
2003 && indx
!= virtual_stack_vars_rtx
)
2004 if (!DISP_IN_RANGE (offset
))
2009 /* All the special cases are pointers. */
2012 /* In the small-PIC case, the linker converts @GOT
2013 and @GOTNTPOFF offsets to possible displacements. */
2014 if (GET_CODE (disp
) == UNSPEC
2015 && (XINT (disp
, 1) == UNSPEC_GOT
2016 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2022 /* Accept pool label offsets. */
2023 else if (GET_CODE (disp
) == UNSPEC
2024 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2027 /* Accept literal pool references. */
2028 else if (GET_CODE (disp
) == UNSPEC
2029 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2031 /* In case CSE pulled a non literal pool reference out of
2032 the pool we have to reject the address. This is
2033 especially important when loading the GOT pointer on non
2034 zarch CPUs. In this case the literal pool contains an lt
2035 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2036 will most likely exceed the displacement. */
2037 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2038 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2041 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2044 /* If we have an offset, make sure it does not
2045 exceed the size of the constant pool entry. */
2046 rtx sym
= XVECEXP (disp
, 0, 0);
2047 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2050 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2065 out
->disp
= orig_disp
;
2066 out
->pointer
= pointer
;
2067 out
->literal_pool
= literal_pool
;
2073 /* Decompose a RTL expression OP for a shift count into its components,
2074 and return the base register in BASE and the offset in OFFSET.
2076 Return true if OP is a valid shift count, false if not. */
2079 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2081 HOST_WIDE_INT off
= 0;
2083 /* We can have an integer constant, an address register,
2084 or a sum of the two. */
2085 if (GET_CODE (op
) == CONST_INT
)
2090 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2092 off
= INTVAL (XEXP (op
, 1));
2095 while (op
&& GET_CODE (op
) == SUBREG
)
2096 op
= SUBREG_REG (op
);
2098 if (op
&& GET_CODE (op
) != REG
)
2110 /* Return true if CODE is a valid address without index. */
2113 s390_legitimate_address_without_index_p (rtx op
)
2115 struct s390_address addr
;
2117 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2126 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2127 and return these parts in SYMREF and ADDEND. You can pass NULL in
2128 SYMREF and/or ADDEND if you are not interested in these values.
2129 Literal pool references are *not* considered symbol references. */
2132 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2134 HOST_WIDE_INT tmpaddend
= 0;
2136 if (GET_CODE (addr
) == CONST
)
2137 addr
= XEXP (addr
, 0);
2139 if (GET_CODE (addr
) == PLUS
)
2141 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2142 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2143 && CONST_INT_P (XEXP (addr
, 1)))
2145 tmpaddend
= INTVAL (XEXP (addr
, 1));
2146 addr
= XEXP (addr
, 0);
2152 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2158 *addend
= tmpaddend
;
2163 /* Return TRUE if ADDR is an operand valid for a load/store relative
2164 instructions. Be aware that the alignment of the operand needs to
2165 be checked separately. */
2167 s390_loadrelative_operand_p (rtx addr
)
2169 if (GET_CODE (addr
) == CONST
)
2170 addr
= XEXP (addr
, 0);
2172 /* Enable load relative for symbol@GOTENT. */
2173 if (GET_CODE (addr
) == UNSPEC
2174 && XINT (addr
, 1) == UNSPEC_GOTENT
)
2177 return s390_symref_operand_p (addr
, NULL
, NULL
);
2180 /* Return true if the address in OP is valid for constraint letter C
2181 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2182 pool MEMs should be accepted. Only the Q, R, S, T constraint
2183 letters are allowed for C. */
2186 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2188 struct s390_address addr
;
2189 bool decomposed
= false;
2191 /* This check makes sure that no symbolic address (except literal
2192 pool references) are accepted by the R or T constraints. */
2193 if (s390_loadrelative_operand_p (op
))
2196 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2199 if (!s390_decompose_address (op
, &addr
))
2201 if (addr
.literal_pool
)
2208 case 'Q': /* no index short displacement */
2209 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2213 if (!s390_short_displacement (addr
.disp
))
2217 case 'R': /* with index short displacement */
2218 if (TARGET_LONG_DISPLACEMENT
)
2220 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2222 if (!s390_short_displacement (addr
.disp
))
2225 /* Any invalid address here will be fixed up by reload,
2226 so accept it for the most generic constraint. */
2229 case 'S': /* no index long displacement */
2230 if (!TARGET_LONG_DISPLACEMENT
)
2232 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2236 if (s390_short_displacement (addr
.disp
))
2240 case 'T': /* with index long displacement */
2241 if (!TARGET_LONG_DISPLACEMENT
)
2243 /* Any invalid address here will be fixed up by reload,
2244 so accept it for the most generic constraint. */
2245 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2246 && s390_short_displacement (addr
.disp
))
2256 /* Evaluates constraint strings described by the regular expression
2257 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2258 the constraint given in STR, or 0 else. */
2261 s390_mem_constraint (const char *str
, rtx op
)
2268 /* Check for offsettable variants of memory constraints. */
2269 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2271 if ((reload_completed
|| reload_in_progress
)
2272 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2274 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2276 /* Check for non-literal-pool variants of memory constraints. */
2279 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2284 if (GET_CODE (op
) != MEM
)
2286 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2288 return (s390_check_qrst_address ('Q', op
, true)
2289 || s390_check_qrst_address ('R', op
, true));
2291 return (s390_check_qrst_address ('S', op
, true)
2292 || s390_check_qrst_address ('T', op
, true));
2294 /* Simply check for the basic form of a shift count. Reload will
2295 take care of making sure we have a proper base register. */
2296 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2300 return s390_check_qrst_address (str
[1], op
, true);
2308 /* Evaluates constraint strings starting with letter O. Input
2309 parameter C is the second letter following the "O" in the constraint
2310 string. Returns 1 if VALUE meets the respective constraint and 0
2314 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2322 return trunc_int_for_mode (value
, SImode
) == value
;
2326 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2329 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2337 /* Evaluates constraint strings starting with letter N. Parameter STR
2338 contains the letters following letter "N" in the constraint string.
2339 Returns true if VALUE matches the constraint. */
2342 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2344 enum machine_mode mode
, part_mode
;
2346 int part
, part_goal
;
2352 part_goal
= str
[0] - '0';
2396 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2399 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2402 if (part_goal
!= -1 && part_goal
!= part
)
2409 /* Returns true if the input parameter VALUE is a float zero. */
2412 s390_float_const_zero_p (rtx value
)
2414 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2415 && value
== CONST0_RTX (GET_MODE (value
)));
2418 /* Implement TARGET_REGISTER_MOVE_COST. */
2421 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2422 reg_class_t from
, reg_class_t to
)
2424 /* On s390, copy between fprs and gprs is expensive. */
2425 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2426 && reg_classes_intersect_p (to
, FP_REGS
))
2427 || (reg_classes_intersect_p (from
, FP_REGS
)
2428 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
2434 /* Implement TARGET_MEMORY_MOVE_COST. */
2437 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2438 reg_class_t rclass ATTRIBUTE_UNUSED
,
2439 bool in ATTRIBUTE_UNUSED
)
2444 /* Compute a (partial) cost for rtx X. Return true if the complete
2445 cost has been computed, and false if subexpressions should be
2446 scanned. In either case, *TOTAL contains the cost result.
2447 CODE contains GET_CODE (x), OUTER_CODE contains the code
2448 of the superexpression of x. */
2451 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2452 int *total
, bool speed ATTRIBUTE_UNUSED
)
2475 *total
= COSTS_N_INSNS (1);
2480 *total
= COSTS_N_INSNS (1);
2484 switch (GET_MODE (x
))
2488 rtx left
= XEXP (x
, 0);
2489 rtx right
= XEXP (x
, 1);
2490 if (GET_CODE (right
) == CONST_INT
2491 && CONST_OK_FOR_K (INTVAL (right
)))
2492 *total
= s390_cost
->mhi
;
2493 else if (GET_CODE (left
) == SIGN_EXTEND
)
2494 *total
= s390_cost
->mh
;
2496 *total
= s390_cost
->ms
; /* msr, ms, msy */
2501 rtx left
= XEXP (x
, 0);
2502 rtx right
= XEXP (x
, 1);
2505 if (GET_CODE (right
) == CONST_INT
2506 && CONST_OK_FOR_K (INTVAL (right
)))
2507 *total
= s390_cost
->mghi
;
2508 else if (GET_CODE (left
) == SIGN_EXTEND
)
2509 *total
= s390_cost
->msgf
;
2511 *total
= s390_cost
->msg
; /* msgr, msg */
2513 else /* TARGET_31BIT */
2515 if (GET_CODE (left
) == SIGN_EXTEND
2516 && GET_CODE (right
) == SIGN_EXTEND
)
2517 /* mulsidi case: mr, m */
2518 *total
= s390_cost
->m
;
2519 else if (GET_CODE (left
) == ZERO_EXTEND
2520 && GET_CODE (right
) == ZERO_EXTEND
2521 && TARGET_CPU_ZARCH
)
2522 /* umulsidi case: ml, mlr */
2523 *total
= s390_cost
->ml
;
2525 /* Complex calculation is required. */
2526 *total
= COSTS_N_INSNS (40);
2532 *total
= s390_cost
->mult_df
;
2535 *total
= s390_cost
->mxbr
;
2543 switch (GET_MODE (x
))
2546 *total
= s390_cost
->madbr
;
2549 *total
= s390_cost
->maebr
;
2554 /* Negate in the third argument is free: FMSUB. */
2555 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2557 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
2558 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
2559 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
2566 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2567 *total
= s390_cost
->dlgr
;
2568 else if (GET_MODE (x
) == DImode
)
2570 rtx right
= XEXP (x
, 1);
2571 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2572 *total
= s390_cost
->dlr
;
2573 else /* 64 by 64 bit division */
2574 *total
= s390_cost
->dlgr
;
2576 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2577 *total
= s390_cost
->dlr
;
2582 if (GET_MODE (x
) == DImode
)
2584 rtx right
= XEXP (x
, 1);
2585 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2587 *total
= s390_cost
->dsgfr
;
2589 *total
= s390_cost
->dr
;
2590 else /* 64 by 64 bit division */
2591 *total
= s390_cost
->dsgr
;
2593 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2594 *total
= s390_cost
->dlr
;
2595 else if (GET_MODE (x
) == SFmode
)
2597 *total
= s390_cost
->debr
;
2599 else if (GET_MODE (x
) == DFmode
)
2601 *total
= s390_cost
->ddbr
;
2603 else if (GET_MODE (x
) == TFmode
)
2605 *total
= s390_cost
->dxbr
;
2610 if (GET_MODE (x
) == SFmode
)
2611 *total
= s390_cost
->sqebr
;
2612 else if (GET_MODE (x
) == DFmode
)
2613 *total
= s390_cost
->sqdbr
;
2615 *total
= s390_cost
->sqxbr
;
2620 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2621 || outer_code
== PLUS
|| outer_code
== MINUS
2622 || outer_code
== COMPARE
)
2627 *total
= COSTS_N_INSNS (1);
2628 if (GET_CODE (XEXP (x
, 0)) == AND
2629 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2630 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2632 rtx op0
= XEXP (XEXP (x
, 0), 0);
2633 rtx op1
= XEXP (XEXP (x
, 0), 1);
2634 rtx op2
= XEXP (x
, 1);
2636 if (memory_operand (op0
, GET_MODE (op0
))
2637 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2639 if (register_operand (op0
, GET_MODE (op0
))
2640 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2650 /* Return the cost of an address rtx ADDR. */
2653 s390_address_cost (rtx addr
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2654 addr_space_t as ATTRIBUTE_UNUSED
,
2655 bool speed ATTRIBUTE_UNUSED
)
2657 struct s390_address ad
;
2658 if (!s390_decompose_address (addr
, &ad
))
2661 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2664 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2665 otherwise return 0. */
2668 tls_symbolic_operand (rtx op
)
2670 if (GET_CODE (op
) != SYMBOL_REF
)
2672 return SYMBOL_REF_TLS_MODEL (op
);
2675 /* Split DImode access register reference REG (on 64-bit) into its constituent
2676 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2677 gen_highpart cannot be used as they assume all registers are word-sized,
2678 while our access registers have only half that size. */
2681 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2683 gcc_assert (TARGET_64BIT
);
2684 gcc_assert (ACCESS_REG_P (reg
));
2685 gcc_assert (GET_MODE (reg
) == DImode
);
2686 gcc_assert (!(REGNO (reg
) & 1));
2688 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2689 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2692 /* Return true if OP contains a symbol reference */
2695 symbolic_reference_mentioned_p (rtx op
)
2700 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2703 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2704 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2710 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2711 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2715 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2722 /* Return true if OP contains a reference to a thread-local symbol. */
2725 tls_symbolic_reference_mentioned_p (rtx op
)
2730 if (GET_CODE (op
) == SYMBOL_REF
)
2731 return tls_symbolic_operand (op
);
2733 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2734 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2740 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2741 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2745 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2753 /* Return true if OP is a legitimate general operand when
2754 generating PIC code. It is given that flag_pic is on
2755 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2758 legitimate_pic_operand_p (rtx op
)
2760 /* Accept all non-symbolic constants. */
2761 if (!SYMBOLIC_CONST (op
))
2764 /* Reject everything else; must be handled
2765 via emit_symbolic_move. */
2769 /* Returns true if the constant value OP is a legitimate general operand.
2770 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2773 s390_legitimate_constant_p (enum machine_mode mode
, rtx op
)
2775 /* Accept all non-symbolic constants. */
2776 if (!SYMBOLIC_CONST (op
))
2779 /* Accept immediate LARL operands. */
2780 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
2783 /* Thread-local symbols are never legal constants. This is
2784 so that emit_call knows that computing such addresses
2785 might require a function call. */
2786 if (TLS_SYMBOLIC_CONST (op
))
2789 /* In the PIC case, symbolic constants must *not* be
2790 forced into the literal pool. We accept them here,
2791 so that they will be handled by emit_symbolic_move. */
2795 /* All remaining non-PIC symbolic constants are
2796 forced into the literal pool. */
2800 /* Determine if it's legal to put X into the constant pool. This
2801 is not possible if X contains the address of a symbol that is
2802 not constant (TLS) or not known at final link time (PIC). */
2805 s390_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2807 switch (GET_CODE (x
))
2811 /* Accept all non-symbolic constants. */
2815 /* Labels are OK iff we are non-PIC. */
2816 return flag_pic
!= 0;
2819 /* 'Naked' TLS symbol references are never OK,
2820 non-TLS symbols are OK iff we are non-PIC. */
2821 if (tls_symbolic_operand (x
))
2824 return flag_pic
!= 0;
2827 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2830 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2831 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2834 switch (XINT (x
, 1))
2836 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2837 case UNSPEC_LTREL_OFFSET
:
2845 case UNSPEC_GOTNTPOFF
:
2846 case UNSPEC_INDNTPOFF
:
2849 /* If the literal pool shares the code section, be put
2850 execute template placeholders into the pool as well. */
2852 return TARGET_CPU_ZARCH
;
2864 /* Returns true if the constant value OP is a legitimate general
2865 operand during and after reload. The difference to
2866 legitimate_constant_p is that this function will not accept
2867 a constant that would need to be forced to the literal pool
2868 before it can be used as operand.
2869 This function accepts all constants which can be loaded directly
2873 legitimate_reload_constant_p (rtx op
)
2875 /* Accept la(y) operands. */
2876 if (GET_CODE (op
) == CONST_INT
2877 && DISP_IN_RANGE (INTVAL (op
)))
2880 /* Accept l(g)hi/l(g)fi operands. */
2881 if (GET_CODE (op
) == CONST_INT
2882 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2885 /* Accept lliXX operands. */
2887 && GET_CODE (op
) == CONST_INT
2888 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2889 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2893 && GET_CODE (op
) == CONST_INT
2894 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2895 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2898 /* Accept larl operands. */
2899 if (TARGET_CPU_ZARCH
2900 && larl_operand (op
, VOIDmode
))
2903 /* Accept floating-point zero operands that fit into a single GPR. */
2904 if (GET_CODE (op
) == CONST_DOUBLE
2905 && s390_float_const_zero_p (op
)
2906 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2909 /* Accept double-word operands that can be split. */
2910 if (GET_CODE (op
) == CONST_INT
2911 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2913 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2914 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2915 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2916 return legitimate_reload_constant_p (hi
)
2917 && legitimate_reload_constant_p (lo
);
2920 /* Everything else cannot be handled without reload. */
2924 /* Returns true if the constant value OP is a legitimate fp operand
2925 during and after reload.
2926 This function accepts all constants which can be loaded directly
2930 legitimate_reload_fp_constant_p (rtx op
)
2932 /* Accept floating-point zero operands if the load zero instruction
2933 can be used. Prior to z196 the load fp zero instruction caused a
2934 performance penalty if the result is used as BFP number. */
2936 && GET_CODE (op
) == CONST_DOUBLE
2937 && s390_float_const_zero_p (op
))
2943 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2944 return the class of reg to actually use. */
2947 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2949 switch (GET_CODE (op
))
2951 /* Constants we cannot reload into general registers
2952 must be forced into the literal pool. */
2955 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2956 && legitimate_reload_constant_p (op
))
2957 return GENERAL_REGS
;
2958 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2959 && legitimate_reload_constant_p (op
))
2961 else if (reg_class_subset_p (FP_REGS
, rclass
)
2962 && legitimate_reload_fp_constant_p (op
))
2966 /* If a symbolic constant or a PLUS is reloaded,
2967 it is most likely being used as an address, so
2968 prefer ADDR_REGS. If 'class' is not a superset
2969 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2973 if (!legitimate_reload_constant_p (op
))
2977 /* load address will be used. */
2978 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2990 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2991 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2995 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2997 HOST_WIDE_INT addend
;
3000 /* Accept symbol@GOTENT with pointer size alignment. */
3001 if (GET_CODE (addr
) == CONST
3002 && GET_CODE (XEXP (addr
, 0)) == UNSPEC
3003 && XINT (XEXP (addr
, 0), 1) == UNSPEC_GOTENT
3004 && alignment
<= UNITS_PER_LONG
)
3007 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3010 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
3011 && !(addend
& (alignment
- 1)));
3014 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3015 operand SCRATCH is used to reload the even part of the address and
3019 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3021 HOST_WIDE_INT addend
;
3024 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3028 /* Easy case. The addend is even so larl will do fine. */
3029 emit_move_insn (reg
, addr
);
3032 /* We can leave the scratch register untouched if the target
3033 register is a valid base register. */
3034 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3035 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3038 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3039 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3042 emit_move_insn (scratch
,
3043 gen_rtx_CONST (Pmode
,
3044 gen_rtx_PLUS (Pmode
, symref
,
3045 GEN_INT (addend
- 1))));
3047 emit_move_insn (scratch
, symref
);
3049 /* Increment the address using la in order to avoid clobbering cc. */
3050 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3054 /* Generate what is necessary to move between REG and MEM using
3055 SCRATCH. The direction is given by TOMEM. */
3058 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3060 /* Reload might have pulled a constant out of the literal pool.
3061 Force it back in. */
3062 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3063 || GET_CODE (mem
) == CONST
)
3064 mem
= force_const_mem (GET_MODE (reg
), mem
);
3066 gcc_assert (MEM_P (mem
));
3068 /* For a load from memory we can leave the scratch register
3069 untouched if the target register is a valid base register. */
3071 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3072 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3073 && GET_MODE (reg
) == GET_MODE (scratch
))
3076 /* Load address into scratch register. Since we can't have a
3077 secondary reload for a secondary reload we have to cover the case
3078 where larl would need a secondary reload here as well. */
3079 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3081 /* Now we can use a standard load/store to do the move. */
3083 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3085 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3088 /* Inform reload about cases where moving X with a mode MODE to a register in
3089 RCLASS requires an extra scratch or immediate register. Return the class
3090 needed for the immediate register. */
3093 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3094 enum machine_mode mode
, secondary_reload_info
*sri
)
3096 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3098 /* Intermediate register needed. */
3099 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3100 return GENERAL_REGS
;
3104 HOST_WIDE_INT offset
;
3107 /* On z10 several optimizer steps may generate larl operands with
3110 && s390_symref_operand_p (x
, &symref
, &offset
)
3112 && !SYMBOL_REF_ALIGN1_P (symref
)
3113 && (offset
& 1) == 1)
3114 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3115 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3117 /* On z10 we need a scratch register when moving QI, TI or floating
3118 point mode values from or to a memory location with a SYMBOL_REF
3119 or if the symref addend of a SI or DI move is not aligned to the
3120 width of the access. */
3122 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3123 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3124 || (!TARGET_ZARCH
&& mode
== DImode
)
3125 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3126 && (!s390_check_symref_alignment (XEXP (x
, 0),
3127 GET_MODE_SIZE (mode
))))))
3129 #define __SECONDARY_RELOAD_CASE(M,m) \
3132 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3133 CODE_FOR_reload##m##di_tomem_z10; \
3135 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3136 CODE_FOR_reload##m##si_tomem_z10; \
3139 switch (GET_MODE (x
))
3141 __SECONDARY_RELOAD_CASE (QI
, qi
);
3142 __SECONDARY_RELOAD_CASE (HI
, hi
);
3143 __SECONDARY_RELOAD_CASE (SI
, si
);
3144 __SECONDARY_RELOAD_CASE (DI
, di
);
3145 __SECONDARY_RELOAD_CASE (TI
, ti
);
3146 __SECONDARY_RELOAD_CASE (SF
, sf
);
3147 __SECONDARY_RELOAD_CASE (DF
, df
);
3148 __SECONDARY_RELOAD_CASE (TF
, tf
);
3149 __SECONDARY_RELOAD_CASE (SD
, sd
);
3150 __SECONDARY_RELOAD_CASE (DD
, dd
);
3151 __SECONDARY_RELOAD_CASE (TD
, td
);
3156 #undef __SECONDARY_RELOAD_CASE
3160 /* We need a scratch register when loading a PLUS expression which
3161 is not a legitimate operand of the LOAD ADDRESS instruction. */
3162 if (in_p
&& s390_plus_operand (x
, mode
))
3163 sri
->icode
= (TARGET_64BIT
?
3164 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3166 /* Performing a multiword move from or to memory we have to make sure the
3167 second chunk in memory is addressable without causing a displacement
3168 overflow. If that would be the case we calculate the address in
3169 a scratch register. */
3171 && GET_CODE (XEXP (x
, 0)) == PLUS
3172 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3173 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3174 + GET_MODE_SIZE (mode
) - 1))
3176 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3177 in a s_operand address since we may fallback to lm/stm. So we only
3178 have to care about overflows in the b+i+d case. */
3179 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3180 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3181 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3182 /* For FP_REGS no lm/stm is available so this check is triggered
3183 for displacement overflows in b+i+d and b+d like addresses. */
3184 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3185 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3188 sri
->icode
= (TARGET_64BIT
?
3189 CODE_FOR_reloaddi_nonoffmem_in
:
3190 CODE_FOR_reloadsi_nonoffmem_in
);
3192 sri
->icode
= (TARGET_64BIT
?
3193 CODE_FOR_reloaddi_nonoffmem_out
:
3194 CODE_FOR_reloadsi_nonoffmem_out
);
3198 /* A scratch address register is needed when a symbolic constant is
3199 copied to r0 compiling with -fPIC. In other cases the target
3200 register might be used as temporary (see legitimize_pic_address). */
3201 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3202 sri
->icode
= (TARGET_64BIT
?
3203 CODE_FOR_reloaddi_PIC_addr
:
3204 CODE_FOR_reloadsi_PIC_addr
);
3206 /* Either scratch or no register needed. */
3210 /* Generate code to load SRC, which is PLUS that is not a
3211 legitimate operand for the LA instruction, into TARGET.
3212 SCRATCH may be used as scratch register. */
3215 s390_expand_plus_operand (rtx target
, rtx src
,
3219 struct s390_address ad
;
3221 /* src must be a PLUS; get its two operands. */
3222 gcc_assert (GET_CODE (src
) == PLUS
);
3223 gcc_assert (GET_MODE (src
) == Pmode
);
3225 /* Check if any of the two operands is already scheduled
3226 for replacement by reload. This can happen e.g. when
3227 float registers occur in an address. */
3228 sum1
= find_replacement (&XEXP (src
, 0));
3229 sum2
= find_replacement (&XEXP (src
, 1));
3230 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3232 /* If the address is already strictly valid, there's nothing to do. */
3233 if (!s390_decompose_address (src
, &ad
)
3234 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3235 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3237 /* Otherwise, one of the operands cannot be an address register;
3238 we reload its value into the scratch register. */
3239 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3241 emit_move_insn (scratch
, sum1
);
3244 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3246 emit_move_insn (scratch
, sum2
);
3250 /* According to the way these invalid addresses are generated
3251 in reload.c, it should never happen (at least on s390) that
3252 *neither* of the PLUS components, after find_replacements
3253 was applied, is an address register. */
3254 if (sum1
== scratch
&& sum2
== scratch
)
3260 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3263 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3264 is only ever performed on addresses, so we can mark the
3265 sum as legitimate for LA in any case. */
3266 s390_load_address (target
, src
);
3270 /* Return true if ADDR is a valid memory address.
3271 STRICT specifies whether strict register checking applies. */
3274 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3276 struct s390_address ad
;
3279 && larl_operand (addr
, VOIDmode
)
3280 && (mode
== VOIDmode
3281 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3284 if (!s390_decompose_address (addr
, &ad
))
3289 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3292 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3298 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3299 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3303 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3304 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3310 /* Return true if OP is a valid operand for the LA instruction.
3311 In 31-bit, we need to prove that the result is used as an
3312 address, as LA performs only a 31-bit addition. */
3315 legitimate_la_operand_p (rtx op
)
3317 struct s390_address addr
;
3318 if (!s390_decompose_address (op
, &addr
))
3321 return (TARGET_64BIT
|| addr
.pointer
);
3324 /* Return true if it is valid *and* preferable to use LA to
3325 compute the sum of OP1 and OP2. */
3328 preferred_la_operand_p (rtx op1
, rtx op2
)
3330 struct s390_address addr
;
3332 if (op2
!= const0_rtx
)
3333 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3335 if (!s390_decompose_address (op1
, &addr
))
3337 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3339 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3342 /* Avoid LA instructions with index register on z196; it is
3343 preferable to use regular add instructions when possible.
3344 Starting with zEC12 the la with index register is "uncracked"
3346 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3349 if (!TARGET_64BIT
&& !addr
.pointer
)
3355 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3356 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3362 /* Emit a forced load-address operation to load SRC into DST.
3363 This will use the LOAD ADDRESS instruction even in situations
3364 where legitimate_la_operand_p (SRC) returns false. */
3367 s390_load_address (rtx dst
, rtx src
)
3370 emit_move_insn (dst
, src
);
3372 emit_insn (gen_force_la_31 (dst
, src
));
3375 /* Return a legitimate reference for ORIG (an address) using the
3376 register REG. If REG is 0, a new pseudo is generated.
3378 There are two types of references that must be handled:
3380 1. Global data references must load the address from the GOT, via
3381 the PIC reg. An insn is emitted to do this load, and the reg is
3384 2. Static data references, constant pool addresses, and code labels
3385 compute the address as an offset from the GOT, whose base is in
3386 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3387 differentiate them from global data objects. The returned
3388 address is the PIC reg + an unspec constant.
3390 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3391 reg also appears in the address. */
3394 legitimize_pic_address (rtx orig
, rtx reg
)
3400 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3402 if (GET_CODE (addr
) == LABEL_REF
3403 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3405 /* This is a local symbol. */
3406 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3408 /* Access local symbols PC-relative via LARL.
3409 This is the same as in the non-PIC case, so it is
3410 handled automatically ... */
3414 /* Access local symbols relative to the GOT. */
3416 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3418 if (reload_in_progress
|| reload_completed
)
3419 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3421 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3422 addr
= gen_rtx_CONST (Pmode
, addr
);
3423 addr
= force_const_mem (Pmode
, addr
);
3424 emit_move_insn (temp
, addr
);
3426 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3429 s390_load_address (reg
, new_rtx
);
3434 else if (GET_CODE (addr
) == SYMBOL_REF
)
3437 reg
= gen_reg_rtx (Pmode
);
3441 /* Assume GOT offset < 4k. This is handled the same way
3442 in both 31- and 64-bit code (@GOT). */
3444 if (reload_in_progress
|| reload_completed
)
3445 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3447 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3448 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3449 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3450 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3451 emit_move_insn (reg
, new_rtx
);
3454 else if (TARGET_CPU_ZARCH
)
3456 /* If the GOT offset might be >= 4k, we determine the position
3457 of the GOT entry via a PC-relative LARL (@GOTENT). */
3459 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3461 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3462 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3464 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3465 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3469 emit_move_insn (temp
, new_rtx
);
3470 new_rtx
= gen_const_mem (Pmode
, temp
);
3473 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
3474 emit_move_insn (reg
, new_rtx
);
3479 /* If the GOT offset might be >= 4k, we have to load it
3480 from the literal pool (@GOT). */
3482 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3484 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3485 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3487 if (reload_in_progress
|| reload_completed
)
3488 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3490 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3491 addr
= gen_rtx_CONST (Pmode
, addr
);
3492 addr
= force_const_mem (Pmode
, addr
);
3493 emit_move_insn (temp
, addr
);
3495 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3496 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3497 emit_move_insn (reg
, new_rtx
);
3503 if (GET_CODE (addr
) == CONST
)
3505 addr
= XEXP (addr
, 0);
3506 if (GET_CODE (addr
) == UNSPEC
)
3508 gcc_assert (XVECLEN (addr
, 0) == 1);
3509 switch (XINT (addr
, 1))
3511 /* If someone moved a GOT-relative UNSPEC
3512 out of the literal pool, force them back in. */
3515 new_rtx
= force_const_mem (Pmode
, orig
);
3518 /* @GOT is OK as is if small. */
3521 new_rtx
= force_const_mem (Pmode
, orig
);
3524 /* @GOTENT is OK as is. */
3528 /* @PLT is OK as is on 64-bit, must be converted to
3529 GOT-relative @PLTOFF on 31-bit. */
3531 if (!TARGET_CPU_ZARCH
)
3533 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3535 if (reload_in_progress
|| reload_completed
)
3536 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3538 addr
= XVECEXP (addr
, 0, 0);
3539 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3541 addr
= gen_rtx_CONST (Pmode
, addr
);
3542 addr
= force_const_mem (Pmode
, addr
);
3543 emit_move_insn (temp
, addr
);
3545 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3548 s390_load_address (reg
, new_rtx
);
3554 /* Everything else cannot happen. */
3560 gcc_assert (GET_CODE (addr
) == PLUS
);
3562 if (GET_CODE (addr
) == PLUS
)
3564 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3566 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3567 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3569 /* Check first to see if this is a constant offset
3570 from a local symbol reference. */
3571 if ((GET_CODE (op0
) == LABEL_REF
3572 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3573 && GET_CODE (op1
) == CONST_INT
)
3575 if (TARGET_CPU_ZARCH
3576 && larl_operand (op0
, VOIDmode
)
3577 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3578 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3580 if (INTVAL (op1
) & 1)
3582 /* LARL can't handle odd offsets, so emit a
3583 pair of LARL and LA. */
3584 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3586 if (!DISP_IN_RANGE (INTVAL (op1
)))
3588 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3589 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3590 op0
= gen_rtx_CONST (Pmode
, op0
);
3594 emit_move_insn (temp
, op0
);
3595 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3599 s390_load_address (reg
, new_rtx
);
3605 /* If the offset is even, we can just use LARL.
3606 This will happen automatically. */
3611 /* Access local symbols relative to the GOT. */
3613 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3615 if (reload_in_progress
|| reload_completed
)
3616 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3618 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3620 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3621 addr
= gen_rtx_CONST (Pmode
, addr
);
3622 addr
= force_const_mem (Pmode
, addr
);
3623 emit_move_insn (temp
, addr
);
3625 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3628 s390_load_address (reg
, new_rtx
);
3634 /* Now, check whether it is a GOT relative symbol plus offset
3635 that was pulled out of the literal pool. Force it back in. */
3637 else if (GET_CODE (op0
) == UNSPEC
3638 && GET_CODE (op1
) == CONST_INT
3639 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3641 gcc_assert (XVECLEN (op0
, 0) == 1);
3643 new_rtx
= force_const_mem (Pmode
, orig
);
3646 /* Otherwise, compute the sum. */
3649 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3650 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3651 base
== reg
? NULL_RTX
: reg
);
3652 if (GET_CODE (new_rtx
) == CONST_INT
)
3653 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
3656 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3658 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3659 new_rtx
= XEXP (new_rtx
, 1);
3661 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3664 if (GET_CODE (new_rtx
) == CONST
)
3665 new_rtx
= XEXP (new_rtx
, 0);
3666 new_rtx
= force_operand (new_rtx
, 0);
3673 /* Load the thread pointer into a register. */
3676 s390_get_thread_pointer (void)
3678 rtx tp
= gen_reg_rtx (Pmode
);
3680 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3681 mark_reg_pointer (tp
, BITS_PER_WORD
);
3686 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3687 in s390_tls_symbol which always refers to __tls_get_offset.
3688 The returned offset is written to RESULT_REG and an USE rtx is
3689 generated for TLS_CALL. */
3691 static GTY(()) rtx s390_tls_symbol
;
3694 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3699 emit_insn (s390_load_got ());
3701 if (!s390_tls_symbol
)
3702 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3704 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3705 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3707 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3708 RTL_CONST_CALL_P (insn
) = 1;
3711 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3712 this (thread-local) address. REG may be used as temporary. */
3715 legitimize_tls_address (rtx addr
, rtx reg
)
3717 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3719 if (GET_CODE (addr
) == SYMBOL_REF
)
3720 switch (tls_symbolic_operand (addr
))
3722 case TLS_MODEL_GLOBAL_DYNAMIC
:
3724 r2
= gen_rtx_REG (Pmode
, 2);
3725 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3726 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3727 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3728 emit_move_insn (r2
, new_rtx
);
3729 s390_emit_tls_call_insn (r2
, tls_call
);
3730 insn
= get_insns ();
3733 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3734 temp
= gen_reg_rtx (Pmode
);
3735 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3737 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3740 s390_load_address (reg
, new_rtx
);
3745 case TLS_MODEL_LOCAL_DYNAMIC
:
3747 r2
= gen_rtx_REG (Pmode
, 2);
3748 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3749 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3750 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3751 emit_move_insn (r2
, new_rtx
);
3752 s390_emit_tls_call_insn (r2
, tls_call
);
3753 insn
= get_insns ();
3756 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3757 temp
= gen_reg_rtx (Pmode
);
3758 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3760 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3761 base
= gen_reg_rtx (Pmode
);
3762 s390_load_address (base
, new_rtx
);
3764 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3765 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3766 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3767 temp
= gen_reg_rtx (Pmode
);
3768 emit_move_insn (temp
, new_rtx
);
3770 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3773 s390_load_address (reg
, new_rtx
);
3778 case TLS_MODEL_INITIAL_EXEC
:
3781 /* Assume GOT offset < 4k. This is handled the same way
3782 in both 31- and 64-bit code. */
3784 if (reload_in_progress
|| reload_completed
)
3785 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3787 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3788 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3789 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3790 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3791 temp
= gen_reg_rtx (Pmode
);
3792 emit_move_insn (temp
, new_rtx
);
3794 else if (TARGET_CPU_ZARCH
)
3796 /* If the GOT offset might be >= 4k, we determine the position
3797 of the GOT entry via a PC-relative LARL. */
3799 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3800 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3801 temp
= gen_reg_rtx (Pmode
);
3802 emit_move_insn (temp
, new_rtx
);
3804 new_rtx
= gen_const_mem (Pmode
, temp
);
3805 temp
= gen_reg_rtx (Pmode
);
3806 emit_move_insn (temp
, new_rtx
);
3810 /* If the GOT offset might be >= 4k, we have to load it
3811 from the literal pool. */
3813 if (reload_in_progress
|| reload_completed
)
3814 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3816 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3817 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3818 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3819 temp
= gen_reg_rtx (Pmode
);
3820 emit_move_insn (temp
, new_rtx
);
3822 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3823 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3825 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3826 temp
= gen_reg_rtx (Pmode
);
3827 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3831 /* In position-dependent code, load the absolute address of
3832 the GOT entry from the literal pool. */
3834 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3835 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3836 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3837 temp
= gen_reg_rtx (Pmode
);
3838 emit_move_insn (temp
, new_rtx
);
3841 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3842 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3843 temp
= gen_reg_rtx (Pmode
);
3844 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3847 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3850 s390_load_address (reg
, new_rtx
);
3855 case TLS_MODEL_LOCAL_EXEC
:
3856 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3857 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3858 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3859 temp
= gen_reg_rtx (Pmode
);
3860 emit_move_insn (temp
, new_rtx
);
3862 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3865 s390_load_address (reg
, new_rtx
);
3874 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3876 switch (XINT (XEXP (addr
, 0), 1))
3878 case UNSPEC_INDNTPOFF
:
3879 gcc_assert (TARGET_CPU_ZARCH
);
3888 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3889 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3891 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3892 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3893 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3895 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3896 new_rtx
= plus_constant (Pmode
, new_rtx
,
3897 INTVAL (XEXP (XEXP (addr
, 0), 1)));
3898 new_rtx
= force_operand (new_rtx
, 0);
3902 gcc_unreachable (); /* for now ... */
3907 /* Emit insns making the address in operands[1] valid for a standard
3908 move to operands[0]. operands[1] is replaced by an address which
3909 should be used instead of the former RTX to emit the move
3913 emit_symbolic_move (rtx
*operands
)
3915 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3917 if (GET_CODE (operands
[0]) == MEM
)
3918 operands
[1] = force_reg (Pmode
, operands
[1]);
3919 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3920 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3922 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3925 /* Try machine-dependent ways of modifying an illegitimate address X
3926 to be legitimate. If we find one, return the new, valid address.
3928 OLDX is the address as it was before break_out_memory_refs was called.
3929 In some cases it is useful to look at this to decide what needs to be done.
3931 MODE is the mode of the operand pointed to by X.
3933 When -fpic is used, special handling is needed for symbolic references.
3934 See comments by legitimize_pic_address for details. */
3937 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3938 enum machine_mode mode ATTRIBUTE_UNUSED
)
3940 rtx constant_term
= const0_rtx
;
3942 if (TLS_SYMBOLIC_CONST (x
))
3944 x
= legitimize_tls_address (x
, 0);
3946 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3949 else if (GET_CODE (x
) == PLUS
3950 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3951 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3957 if (SYMBOLIC_CONST (x
)
3958 || (GET_CODE (x
) == PLUS
3959 && (SYMBOLIC_CONST (XEXP (x
, 0))
3960 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3961 x
= legitimize_pic_address (x
, 0);
3963 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3967 x
= eliminate_constant_term (x
, &constant_term
);
3969 /* Optimize loading of large displacements by splitting them
3970 into the multiple of 4K and the rest; this allows the
3971 former to be CSE'd if possible.
3973 Don't do this if the displacement is added to a register
3974 pointing into the stack frame, as the offsets will
3975 change later anyway. */
3977 if (GET_CODE (constant_term
) == CONST_INT
3978 && !TARGET_LONG_DISPLACEMENT
3979 && !DISP_IN_RANGE (INTVAL (constant_term
))
3980 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3982 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3983 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3985 rtx temp
= gen_reg_rtx (Pmode
);
3986 rtx val
= force_operand (GEN_INT (upper
), temp
);
3988 emit_move_insn (temp
, val
);
3990 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3991 constant_term
= GEN_INT (lower
);
3994 if (GET_CODE (x
) == PLUS
)
3996 if (GET_CODE (XEXP (x
, 0)) == REG
)
3998 rtx temp
= gen_reg_rtx (Pmode
);
3999 rtx val
= force_operand (XEXP (x
, 1), temp
);
4001 emit_move_insn (temp
, val
);
4003 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
4006 else if (GET_CODE (XEXP (x
, 1)) == REG
)
4008 rtx temp
= gen_reg_rtx (Pmode
);
4009 rtx val
= force_operand (XEXP (x
, 0), temp
);
4011 emit_move_insn (temp
, val
);
4013 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4017 if (constant_term
!= const0_rtx
)
4018 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4023 /* Try a machine-dependent way of reloading an illegitimate address AD
4024 operand. If we find one, push the reload and return the new address.
4026 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4027 and TYPE is the reload type of the current reload. */
4030 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
4031 int opnum
, int type
)
4033 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
4036 if (GET_CODE (ad
) == PLUS
)
4038 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
4039 XEXP (ad
, 0), XEXP (ad
, 1));
4044 if (GET_CODE (ad
) == PLUS
4045 && GET_CODE (XEXP (ad
, 0)) == REG
4046 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4047 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4049 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4050 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4051 rtx cst
, tem
, new_rtx
;
4053 cst
= GEN_INT (upper
);
4054 if (!legitimate_reload_constant_p (cst
))
4055 cst
= force_const_mem (Pmode
, cst
);
4057 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4058 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4060 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4061 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4062 opnum
, (enum reload_type
) type
);
4069 /* Emit code to move LEN bytes from DST to SRC. */
4072 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4074 /* When tuning for z10 or higher we rely on the Glibc functions to
4075 do the right thing. Only for constant lengths below 64k we will
4076 generate inline code. */
4077 if (s390_tune
>= PROCESSOR_2097_Z10
4078 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4081 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4083 if (INTVAL (len
) > 0)
4084 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4087 else if (TARGET_MVCLE
)
4089 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4094 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4095 rtx loop_start_label
= gen_label_rtx ();
4096 rtx loop_end_label
= gen_label_rtx ();
4097 rtx end_label
= gen_label_rtx ();
4098 enum machine_mode mode
;
4100 mode
= GET_MODE (len
);
4101 if (mode
== VOIDmode
)
4104 dst_addr
= gen_reg_rtx (Pmode
);
4105 src_addr
= gen_reg_rtx (Pmode
);
4106 count
= gen_reg_rtx (mode
);
4107 blocks
= gen_reg_rtx (mode
);
4109 convert_move (count
, len
, 1);
4110 emit_cmp_and_jump_insns (count
, const0_rtx
,
4111 EQ
, NULL_RTX
, mode
, 1, end_label
);
4113 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4114 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4115 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4116 src
= change_address (src
, VOIDmode
, src_addr
);
4118 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4121 emit_move_insn (count
, temp
);
4123 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4126 emit_move_insn (blocks
, temp
);
4128 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4129 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4131 emit_label (loop_start_label
);
4134 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4138 /* Issue a read prefetch for the +3 cache line. */
4139 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4140 const0_rtx
, const0_rtx
);
4141 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4142 emit_insn (prefetch
);
4144 /* Issue a write prefetch for the +3 cache line. */
4145 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4146 const1_rtx
, const0_rtx
);
4147 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4148 emit_insn (prefetch
);
4151 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4152 s390_load_address (dst_addr
,
4153 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4154 s390_load_address (src_addr
,
4155 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4157 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4160 emit_move_insn (blocks
, temp
);
4162 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4163 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4165 emit_jump (loop_start_label
);
4166 emit_label (loop_end_label
);
4168 emit_insn (gen_movmem_short (dst
, src
,
4169 convert_to_mode (Pmode
, count
, 1)));
4170 emit_label (end_label
);
4175 /* Emit code to set LEN bytes at DST to VAL.
4176 Make use of clrmem if VAL is zero. */
4179 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4181 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4184 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4186 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4188 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4189 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4192 /* Initialize memory by storing the first byte. */
4193 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4195 if (INTVAL (len
) > 1)
4197 /* Initiate 1 byte overlap move.
4198 The first byte of DST is propagated through DSTP1.
4199 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4200 DST is set to size 1 so the rest of the memory location
4201 does not count as source operand. */
4202 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4203 set_mem_size (dst
, 1);
4205 emit_insn (gen_movmem_short (dstp1
, dst
,
4206 GEN_INT (INTVAL (len
) - 2)));
4211 else if (TARGET_MVCLE
)
4213 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4214 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4219 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4220 rtx loop_start_label
= gen_label_rtx ();
4221 rtx loop_end_label
= gen_label_rtx ();
4222 rtx end_label
= gen_label_rtx ();
4223 enum machine_mode mode
;
4225 mode
= GET_MODE (len
);
4226 if (mode
== VOIDmode
)
4229 dst_addr
= gen_reg_rtx (Pmode
);
4230 count
= gen_reg_rtx (mode
);
4231 blocks
= gen_reg_rtx (mode
);
4233 convert_move (count
, len
, 1);
4234 emit_cmp_and_jump_insns (count
, const0_rtx
,
4235 EQ
, NULL_RTX
, mode
, 1, end_label
);
4237 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4238 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4240 if (val
== const0_rtx
)
4241 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4245 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4246 set_mem_size (dst
, 1);
4248 /* Initialize memory by storing the first byte. */
4249 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4251 /* If count is 1 we are done. */
4252 emit_cmp_and_jump_insns (count
, const1_rtx
,
4253 EQ
, NULL_RTX
, mode
, 1, end_label
);
4255 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4259 emit_move_insn (count
, temp
);
4261 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4264 emit_move_insn (blocks
, temp
);
4266 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4267 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4269 emit_label (loop_start_label
);
4272 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4274 /* Issue a write prefetch for the +4 cache line. */
4275 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4277 const1_rtx
, const0_rtx
);
4278 emit_insn (prefetch
);
4279 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4282 if (val
== const0_rtx
)
4283 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4285 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4286 s390_load_address (dst_addr
,
4287 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4289 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4292 emit_move_insn (blocks
, temp
);
4294 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4295 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4297 emit_jump (loop_start_label
);
4298 emit_label (loop_end_label
);
4300 if (val
== const0_rtx
)
4301 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4303 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4304 emit_label (end_label
);
4308 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4309 and return the result in TARGET. */
4312 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4314 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4317 /* When tuning for z10 or higher we rely on the Glibc functions to
4318 do the right thing. Only for constant lengths below 64k we will
4319 generate inline code. */
4320 if (s390_tune
>= PROCESSOR_2097_Z10
4321 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
4324 /* As the result of CMPINT is inverted compared to what we need,
4325 we have to swap the operands. */
4326 tmp
= op0
; op0
= op1
; op1
= tmp
;
4328 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4330 if (INTVAL (len
) > 0)
4332 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4333 emit_insn (gen_cmpint (target
, ccreg
));
4336 emit_move_insn (target
, const0_rtx
);
4338 else if (TARGET_MVCLE
)
4340 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4341 emit_insn (gen_cmpint (target
, ccreg
));
4345 rtx addr0
, addr1
, count
, blocks
, temp
;
4346 rtx loop_start_label
= gen_label_rtx ();
4347 rtx loop_end_label
= gen_label_rtx ();
4348 rtx end_label
= gen_label_rtx ();
4349 enum machine_mode mode
;
4351 mode
= GET_MODE (len
);
4352 if (mode
== VOIDmode
)
4355 addr0
= gen_reg_rtx (Pmode
);
4356 addr1
= gen_reg_rtx (Pmode
);
4357 count
= gen_reg_rtx (mode
);
4358 blocks
= gen_reg_rtx (mode
);
4360 convert_move (count
, len
, 1);
4361 emit_cmp_and_jump_insns (count
, const0_rtx
,
4362 EQ
, NULL_RTX
, mode
, 1, end_label
);
4364 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4365 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4366 op0
= change_address (op0
, VOIDmode
, addr0
);
4367 op1
= change_address (op1
, VOIDmode
, addr1
);
4369 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4372 emit_move_insn (count
, temp
);
4374 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4377 emit_move_insn (blocks
, temp
);
4379 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4380 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4382 emit_label (loop_start_label
);
4385 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4389 /* Issue a read prefetch for the +2 cache line of operand 1. */
4390 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4391 const0_rtx
, const0_rtx
);
4392 emit_insn (prefetch
);
4393 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4395 /* Issue a read prefetch for the +2 cache line of operand 2. */
4396 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4397 const0_rtx
, const0_rtx
);
4398 emit_insn (prefetch
);
4399 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4402 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4403 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4404 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4405 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4406 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4407 emit_jump_insn (temp
);
4409 s390_load_address (addr0
,
4410 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4411 s390_load_address (addr1
,
4412 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4414 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4417 emit_move_insn (blocks
, temp
);
4419 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4420 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4422 emit_jump (loop_start_label
);
4423 emit_label (loop_end_label
);
4425 emit_insn (gen_cmpmem_short (op0
, op1
,
4426 convert_to_mode (Pmode
, count
, 1)));
4427 emit_label (end_label
);
4429 emit_insn (gen_cmpint (target
, ccreg
));
4435 /* Expand conditional increment or decrement using alc/slb instructions.
4436 Should generate code setting DST to either SRC or SRC + INCREMENT,
4437 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4438 Returns true if successful, false otherwise.
4440 That makes it possible to implement some if-constructs without jumps e.g.:
4441 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4442 unsigned int a, b, c;
4443 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4444 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4445 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4446 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4448 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4449 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4450 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4451 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4452 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4455 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4456 rtx dst
, rtx src
, rtx increment
)
4458 enum machine_mode cmp_mode
;
4459 enum machine_mode cc_mode
;
4465 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4466 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4468 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4469 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4474 /* Try ADD LOGICAL WITH CARRY. */
4475 if (increment
== const1_rtx
)
4477 /* Determine CC mode to use. */
4478 if (cmp_code
== EQ
|| cmp_code
== NE
)
4480 if (cmp_op1
!= const0_rtx
)
4482 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4483 NULL_RTX
, 0, OPTAB_WIDEN
);
4484 cmp_op1
= const0_rtx
;
4487 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4490 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4495 cmp_code
= swap_condition (cmp_code
);
4512 /* Emit comparison instruction pattern. */
4513 if (!register_operand (cmp_op0
, cmp_mode
))
4514 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4516 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4517 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4518 /* We use insn_invalid_p here to add clobbers if required. */
4519 ret
= insn_invalid_p (emit_insn (insn
), false);
4522 /* Emit ALC instruction pattern. */
4523 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4524 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4527 if (src
!= const0_rtx
)
4529 if (!register_operand (src
, GET_MODE (dst
)))
4530 src
= force_reg (GET_MODE (dst
), src
);
4532 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4533 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4536 p
= rtvec_alloc (2);
4538 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4540 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4541 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4546 /* Try SUBTRACT LOGICAL WITH BORROW. */
4547 if (increment
== constm1_rtx
)
4549 /* Determine CC mode to use. */
4550 if (cmp_code
== EQ
|| cmp_code
== NE
)
4552 if (cmp_op1
!= const0_rtx
)
4554 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4555 NULL_RTX
, 0, OPTAB_WIDEN
);
4556 cmp_op1
= const0_rtx
;
4559 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4562 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4567 cmp_code
= swap_condition (cmp_code
);
4584 /* Emit comparison instruction pattern. */
4585 if (!register_operand (cmp_op0
, cmp_mode
))
4586 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4588 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4589 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4590 /* We use insn_invalid_p here to add clobbers if required. */
4591 ret
= insn_invalid_p (emit_insn (insn
), false);
4594 /* Emit SLB instruction pattern. */
4595 if (!register_operand (src
, GET_MODE (dst
)))
4596 src
= force_reg (GET_MODE (dst
), src
);
4598 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4599 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4600 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4601 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4603 p
= rtvec_alloc (2);
4605 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4607 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4608 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4616 /* Expand code for the insv template. Return true if successful. */
4619 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4621 int bitsize
= INTVAL (op1
);
4622 int bitpos
= INTVAL (op2
);
4623 enum machine_mode mode
= GET_MODE (dest
);
4624 enum machine_mode smode
;
4625 int smode_bsize
, mode_bsize
;
4628 /* Generate INSERT IMMEDIATE (IILL et al). */
4629 /* (set (ze (reg)) (const_int)). */
4631 && register_operand (dest
, word_mode
)
4632 && (bitpos
% 16) == 0
4633 && (bitsize
% 16) == 0
4634 && const_int_operand (src
, VOIDmode
))
4636 HOST_WIDE_INT val
= INTVAL (src
);
4637 int regpos
= bitpos
+ bitsize
;
4639 while (regpos
> bitpos
)
4641 enum machine_mode putmode
;
4644 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4649 putsize
= GET_MODE_BITSIZE (putmode
);
4651 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4654 gen_int_mode (val
, putmode
));
4657 gcc_assert (regpos
== bitpos
);
4661 smode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4662 smode_bsize
= GET_MODE_BITSIZE (smode
);
4663 mode_bsize
= GET_MODE_BITSIZE (mode
);
4665 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4667 && (bitsize
% BITS_PER_UNIT
) == 0
4669 && (register_operand (src
, word_mode
)
4670 || const_int_operand (src
, VOIDmode
)))
4672 /* Emit standard pattern if possible. */
4673 if (smode_bsize
== bitsize
)
4675 emit_move_insn (adjust_address (dest
, smode
, 0),
4676 gen_lowpart (smode
, src
));
4680 /* (set (ze (mem)) (const_int)). */
4681 else if (const_int_operand (src
, VOIDmode
))
4683 int size
= bitsize
/ BITS_PER_UNIT
;
4684 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
4686 UNITS_PER_WORD
- size
);
4688 dest
= adjust_address (dest
, BLKmode
, 0);
4689 set_mem_size (dest
, size
);
4690 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4694 /* (set (ze (mem)) (reg)). */
4695 else if (register_operand (src
, word_mode
))
4698 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4702 /* Emit st,stcmh sequence. */
4703 int stcmh_width
= bitsize
- 32;
4704 int size
= stcmh_width
/ BITS_PER_UNIT
;
4706 emit_move_insn (adjust_address (dest
, SImode
, size
),
4707 gen_lowpart (SImode
, src
));
4708 set_mem_size (dest
, size
);
4709 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4710 GEN_INT (stcmh_width
),
4712 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
4718 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4719 if ((bitpos
% BITS_PER_UNIT
) == 0
4720 && (bitsize
% BITS_PER_UNIT
) == 0
4721 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
4723 && (mode
== DImode
|| mode
== SImode
)
4724 && register_operand (dest
, mode
))
4726 /* Emit a strict_low_part pattern if possible. */
4727 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
4729 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
4730 op
= gen_rtx_SET (VOIDmode
, op
, gen_lowpart (smode
, src
));
4731 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4732 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4736 /* ??? There are more powerful versions of ICM that are not
4737 completely represented in the md file. */
4740 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4741 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
4743 enum machine_mode mode_s
= GET_MODE (src
);
4745 if (mode_s
== VOIDmode
)
4747 /* Assume const_int etc already in the proper mode. */
4748 src
= force_reg (mode
, src
);
4750 else if (mode_s
!= mode
)
4752 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
4753 src
= force_reg (mode_s
, src
);
4754 src
= gen_lowpart (mode
, src
);
4757 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
4758 op
= gen_rtx_SET (VOIDmode
, op
, src
);
4762 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4763 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
4773 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4774 register that holds VAL of mode MODE shifted by COUNT bits. */
4777 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4779 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4780 NULL_RTX
, 1, OPTAB_DIRECT
);
4781 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4782 NULL_RTX
, 1, OPTAB_DIRECT
);
4785 /* Structure to hold the initial parameters for a compare_and_swap operation
4786 in HImode and QImode. */
4788 struct alignment_context
4790 rtx memsi
; /* SI aligned memory location. */
4791 rtx shift
; /* Bit offset with regard to lsb. */
4792 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4793 rtx modemaski
; /* ~modemask */
4794 bool aligned
; /* True if memory is aligned, false else. */
4797 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4798 structure AC for transparent simplifying, if the memory alignment is known
4799 to be at least 32bit. MEM is the memory location for the actual operation
4800 and MODE its mode. */
4803 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4804 enum machine_mode mode
)
4806 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4807 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4810 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4813 /* Alignment is unknown. */
4814 rtx byteoffset
, addr
, align
;
4816 /* Force the address into a register. */
4817 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4819 /* Align it to SImode. */
4820 align
= expand_simple_binop (Pmode
, AND
, addr
,
4821 GEN_INT (-GET_MODE_SIZE (SImode
)),
4822 NULL_RTX
, 1, OPTAB_DIRECT
);
4824 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4825 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4826 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4827 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4829 /* Calculate shiftcount. */
4830 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4831 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4832 NULL_RTX
, 1, OPTAB_DIRECT
);
4833 /* As we already have some offset, evaluate the remaining distance. */
4834 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4835 NULL_RTX
, 1, OPTAB_DIRECT
);
4838 /* Shift is the byte count, but we need the bitcount. */
4839 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
4840 NULL_RTX
, 1, OPTAB_DIRECT
);
4842 /* Calculate masks. */
4843 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4844 GEN_INT (GET_MODE_MASK (mode
)),
4845 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
4846 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
4850 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4851 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4852 perform the merge in SEQ2. */
4855 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
4856 enum machine_mode mode
, rtx val
, rtx ins
)
4863 tmp
= copy_to_mode_reg (SImode
, val
);
4864 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
4868 *seq2
= get_insns ();
4875 /* Failed to use insv. Generate a two part shift and mask. */
4877 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
4878 *seq1
= get_insns ();
4882 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
4883 *seq2
= get_insns ();
4889 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4890 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4891 value to set if CMP == MEM. */
4894 s390_expand_cs_hqi (enum machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
4895 rtx cmp
, rtx new_rtx
, bool is_weak
)
4897 struct alignment_context ac
;
4898 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
4899 rtx res
= gen_reg_rtx (SImode
);
4900 rtx csloop
= NULL
, csend
= NULL
;
4902 gcc_assert (MEM_P (mem
));
4904 init_alignment_context (&ac
, mem
, mode
);
4906 /* Load full word. Subsequent loads are performed by CS. */
4907 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4908 NULL_RTX
, 1, OPTAB_DIRECT
);
4910 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4911 possible, we try to use insv to make this happen efficiently. If
4912 that fails we'll generate code both inside and outside the loop. */
4913 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
4914 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
4921 /* Start CS loop. */
4924 /* Begin assuming success. */
4925 emit_move_insn (btarget
, const1_rtx
);
4927 csloop
= gen_label_rtx ();
4928 csend
= gen_label_rtx ();
4929 emit_label (csloop
);
4932 /* val = "<mem>00..0<mem>"
4933 * cmp = "00..0<cmp>00..0"
4934 * new = "00..0<new>00..0"
4940 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
);
4942 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
4947 /* Jump to end if we're done (likely?). */
4948 s390_emit_jump (csend
, cc
);
4950 /* Check for changes outside mode, and loop internal if so.
4951 Arrange the moves so that the compare is adjacent to the
4952 branch so that we can generate CRJ. */
4953 tmp
= copy_to_reg (val
);
4954 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
4956 cc
= s390_emit_compare (NE
, val
, tmp
);
4957 s390_emit_jump (csloop
, cc
);
4960 emit_move_insn (btarget
, const0_rtx
);
4964 /* Return the correct part of the bitfield. */
4965 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4966 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4969 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4970 and VAL the value to play with. If AFTER is true then store the value
4971 MEM holds after the operation, if AFTER is false then store the value MEM
4972 holds before the operation. If TARGET is zero then discard that value, else
4973 store it to TARGET. */
4976 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4977 rtx target
, rtx mem
, rtx val
, bool after
)
4979 struct alignment_context ac
;
4981 rtx new_rtx
= gen_reg_rtx (SImode
);
4982 rtx orig
= gen_reg_rtx (SImode
);
4983 rtx csloop
= gen_label_rtx ();
4985 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4986 gcc_assert (MEM_P (mem
));
4988 init_alignment_context (&ac
, mem
, mode
);
4990 /* Shift val to the correct bit positions.
4991 Preserve "icm", but prevent "ex icm". */
4992 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4993 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4995 /* Further preparation insns. */
4996 if (code
== PLUS
|| code
== MINUS
)
4997 emit_move_insn (orig
, val
);
4998 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4999 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
5000 NULL_RTX
, 1, OPTAB_DIRECT
);
5002 /* Load full word. Subsequent loads are performed by CS. */
5003 cmp
= force_reg (SImode
, ac
.memsi
);
5005 /* Start CS loop. */
5006 emit_label (csloop
);
5007 emit_move_insn (new_rtx
, cmp
);
5009 /* Patch new with val at correct position. */
5014 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
5015 NULL_RTX
, 1, OPTAB_DIRECT
);
5016 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
5017 NULL_RTX
, 1, OPTAB_DIRECT
);
5020 if (ac
.aligned
&& MEM_P (val
))
5021 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
5025 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
5026 NULL_RTX
, 1, OPTAB_DIRECT
);
5027 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
5028 NULL_RTX
, 1, OPTAB_DIRECT
);
5034 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
5035 NULL_RTX
, 1, OPTAB_DIRECT
);
5037 case MULT
: /* NAND */
5038 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
5039 NULL_RTX
, 1, OPTAB_DIRECT
);
5040 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
5041 NULL_RTX
, 1, OPTAB_DIRECT
);
5047 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
5048 ac
.memsi
, cmp
, new_rtx
));
5050 /* Return the correct part of the bitfield. */
5052 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
5053 after
? new_rtx
: cmp
, ac
.shift
,
5054 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
5057 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5058 We need to emit DTP-relative relocations. */
5060 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
5063 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5068 fputs ("\t.long\t", file
);
5071 fputs ("\t.quad\t", file
);
5076 output_addr_const (file
, x
);
5077 fputs ("@DTPOFF", file
);
5080 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5081 /* Implement TARGET_MANGLE_TYPE. */
5084 s390_mangle_type (const_tree type
)
5086 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
5087 && TARGET_LONG_DOUBLE_128
)
5090 /* For all other types, use normal C++ mangling. */
5095 /* In the name of slightly smaller debug output, and to cater to
5096 general assembler lossage, recognize various UNSPEC sequences
5097 and turn them back into a direct symbol reference. */
5100 s390_delegitimize_address (rtx orig_x
)
5104 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5107 /* Extract the symbol ref from:
5108 (plus:SI (reg:SI 12 %r12)
5109 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5110 UNSPEC_GOTOFF/PLTOFF)))
5112 (plus:SI (reg:SI 12 %r12)
5113 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5114 UNSPEC_GOTOFF/PLTOFF)
5115 (const_int 4 [0x4])))) */
5116 if (GET_CODE (x
) == PLUS
5117 && REG_P (XEXP (x
, 0))
5118 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
5119 && GET_CODE (XEXP (x
, 1)) == CONST
)
5121 HOST_WIDE_INT offset
= 0;
5123 /* The const operand. */
5124 y
= XEXP (XEXP (x
, 1), 0);
5126 if (GET_CODE (y
) == PLUS
5127 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
5129 offset
= INTVAL (XEXP (y
, 1));
5133 if (GET_CODE (y
) == UNSPEC
5134 && (XINT (y
, 1) == UNSPEC_GOTOFF
5135 || XINT (y
, 1) == UNSPEC_PLTOFF
))
5136 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
5139 if (GET_CODE (x
) != MEM
)
5143 if (GET_CODE (x
) == PLUS
5144 && GET_CODE (XEXP (x
, 1)) == CONST
5145 && GET_CODE (XEXP (x
, 0)) == REG
5146 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5148 y
= XEXP (XEXP (x
, 1), 0);
5149 if (GET_CODE (y
) == UNSPEC
5150 && XINT (y
, 1) == UNSPEC_GOT
)
5151 y
= XVECEXP (y
, 0, 0);
5155 else if (GET_CODE (x
) == CONST
)
5157 /* Extract the symbol ref from:
5158 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5159 UNSPEC_PLT/GOTENT))) */
5162 if (GET_CODE (y
) == UNSPEC
5163 && (XINT (y
, 1) == UNSPEC_GOTENT
5164 || XINT (y
, 1) == UNSPEC_PLT
))
5165 y
= XVECEXP (y
, 0, 0);
5172 if (GET_MODE (orig_x
) != Pmode
)
5174 if (GET_MODE (orig_x
) == BLKmode
)
5176 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
5183 /* Output operand OP to stdio stream FILE.
5184 OP is an address (register + offset) which is not used to address data;
5185 instead the rightmost bits are interpreted as the value. */
5188 print_shift_count_operand (FILE *file
, rtx op
)
5190 HOST_WIDE_INT offset
;
5193 /* Extract base register and offset. */
5194 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5200 gcc_assert (GET_CODE (base
) == REG
);
5201 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5202 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5205 /* Offsets are constricted to twelve bits. */
5206 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5208 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5211 /* See 'get_some_local_dynamic_name'. */
5214 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5218 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5220 x
= get_pool_constant (x
);
5221 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5224 if (GET_CODE (x
) == SYMBOL_REF
5225 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5227 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5234 /* Locate some local-dynamic symbol still in use by this function
5235 so that we can print its name in local-dynamic base patterns. */
5238 get_some_local_dynamic_name (void)
5242 if (cfun
->machine
->some_ld_name
)
5243 return cfun
->machine
->some_ld_name
;
5245 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5247 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5248 return cfun
->machine
->some_ld_name
;
5253 /* Output machine-dependent UNSPECs occurring in address constant X
5254 in assembler syntax to stdio stream FILE. Returns true if the
5255 constant X could be recognized, false otherwise. */
5258 s390_output_addr_const_extra (FILE *file
, rtx x
)
5260 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5261 switch (XINT (x
, 1))
5264 output_addr_const (file
, XVECEXP (x
, 0, 0));
5265 fprintf (file
, "@GOTENT");
5268 output_addr_const (file
, XVECEXP (x
, 0, 0));
5269 fprintf (file
, "@GOT");
5272 output_addr_const (file
, XVECEXP (x
, 0, 0));
5273 fprintf (file
, "@GOTOFF");
5276 output_addr_const (file
, XVECEXP (x
, 0, 0));
5277 fprintf (file
, "@PLT");
5280 output_addr_const (file
, XVECEXP (x
, 0, 0));
5281 fprintf (file
, "@PLTOFF");
5284 output_addr_const (file
, XVECEXP (x
, 0, 0));
5285 fprintf (file
, "@TLSGD");
5288 assemble_name (file
, get_some_local_dynamic_name ());
5289 fprintf (file
, "@TLSLDM");
5292 output_addr_const (file
, XVECEXP (x
, 0, 0));
5293 fprintf (file
, "@DTPOFF");
5296 output_addr_const (file
, XVECEXP (x
, 0, 0));
5297 fprintf (file
, "@NTPOFF");
5299 case UNSPEC_GOTNTPOFF
:
5300 output_addr_const (file
, XVECEXP (x
, 0, 0));
5301 fprintf (file
, "@GOTNTPOFF");
5303 case UNSPEC_INDNTPOFF
:
5304 output_addr_const (file
, XVECEXP (x
, 0, 0));
5305 fprintf (file
, "@INDNTPOFF");
5309 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5310 switch (XINT (x
, 1))
5312 case UNSPEC_POOL_OFFSET
:
5313 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5314 output_addr_const (file
, x
);
5320 /* Output address operand ADDR in assembler syntax to
5321 stdio stream FILE. */
5324 print_operand_address (FILE *file
, rtx addr
)
5326 struct s390_address ad
;
5328 if (s390_loadrelative_operand_p (addr
))
5332 output_operand_lossage ("symbolic memory references are "
5333 "only supported on z10 or later");
5336 output_addr_const (file
, addr
);
5340 if (!s390_decompose_address (addr
, &ad
)
5341 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5342 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5343 output_operand_lossage ("cannot decompose address");
5346 output_addr_const (file
, ad
.disp
);
5348 fprintf (file
, "0");
5350 if (ad
.base
&& ad
.indx
)
5351 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5352 reg_names
[REGNO (ad
.base
)]);
5354 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5357 /* Output operand X in assembler syntax to stdio stream FILE.
5358 CODE specified the format flag. The following format flags
5361 'C': print opcode suffix for branch condition.
5362 'D': print opcode suffix for inverse branch condition.
5363 'E': print opcode suffix for branch on index instruction.
5364 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5365 'G': print the size of the operand in bytes.
5366 'O': print only the displacement of a memory reference.
5367 'R': print only the base register of a memory reference.
5368 'S': print S-type memory reference (base+displacement).
5369 'N': print the second word of a DImode operand.
5370 'M': print the second word of a TImode operand.
5371 'Y': print shift count operand.
5373 'b': print integer X as if it's an unsigned byte.
5374 'c': print integer X as if it's an signed byte.
5375 'x': print integer X as if it's an unsigned halfword.
5376 'h': print integer X as if it's a signed halfword.
5377 'i': print the first nonzero HImode part of X.
5378 'j': print the first HImode part unequal to -1 of X.
5379 'k': print the first nonzero SImode part of X.
5380 'm': print the first SImode part unequal to -1 of X.
5381 'o': print integer X as if it's an unsigned 32bit word. */
5384 print_operand (FILE *file
, rtx x
, int code
)
5389 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5393 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5397 if (GET_CODE (x
) == LE
)
5398 fprintf (file
, "l");
5399 else if (GET_CODE (x
) == GT
)
5400 fprintf (file
, "h");
5402 output_operand_lossage ("invalid comparison operator "
5403 "for 'E' output modifier");
5407 if (GET_CODE (x
) == SYMBOL_REF
)
5409 fprintf (file
, "%s", ":tls_load:");
5410 output_addr_const (file
, x
);
5412 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5414 fprintf (file
, "%s", ":tls_gdcall:");
5415 output_addr_const (file
, XVECEXP (x
, 0, 0));
5417 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5419 fprintf (file
, "%s", ":tls_ldcall:");
5420 assemble_name (file
, get_some_local_dynamic_name ());
5423 output_operand_lossage ("invalid reference for 'J' output modifier");
5427 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5432 struct s390_address ad
;
5437 output_operand_lossage ("memory reference expected for "
5438 "'O' output modifier");
5442 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5445 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5448 output_operand_lossage ("invalid address for 'O' output modifier");
5453 output_addr_const (file
, ad
.disp
);
5455 fprintf (file
, "0");
5461 struct s390_address ad
;
5466 output_operand_lossage ("memory reference expected for "
5467 "'R' output modifier");
5471 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5474 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5477 output_operand_lossage ("invalid address for 'R' output modifier");
5482 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5484 fprintf (file
, "0");
5490 struct s390_address ad
;
5495 output_operand_lossage ("memory reference expected for "
5496 "'S' output modifier");
5499 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5502 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5505 output_operand_lossage ("invalid address for 'S' output modifier");
5510 output_addr_const (file
, ad
.disp
);
5512 fprintf (file
, "0");
5515 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5520 if (GET_CODE (x
) == REG
)
5521 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5522 else if (GET_CODE (x
) == MEM
)
5523 x
= change_address (x
, VOIDmode
,
5524 plus_constant (Pmode
, XEXP (x
, 0), 4));
5526 output_operand_lossage ("register or memory expression expected "
5527 "for 'N' output modifier");
5531 if (GET_CODE (x
) == REG
)
5532 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5533 else if (GET_CODE (x
) == MEM
)
5534 x
= change_address (x
, VOIDmode
,
5535 plus_constant (Pmode
, XEXP (x
, 0), 8));
5537 output_operand_lossage ("register or memory expression expected "
5538 "for 'M' output modifier");
5542 print_shift_count_operand (file
, x
);
5546 switch (GET_CODE (x
))
5549 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5553 output_address (XEXP (x
, 0));
5560 output_addr_const (file
, x
);
5565 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5566 else if (code
== 'c')
5567 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5568 else if (code
== 'x')
5569 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5570 else if (code
== 'h')
5571 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5572 else if (code
== 'i')
5573 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5574 s390_extract_part (x
, HImode
, 0));
5575 else if (code
== 'j')
5576 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5577 s390_extract_part (x
, HImode
, -1));
5578 else if (code
== 'k')
5579 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5580 s390_extract_part (x
, SImode
, 0));
5581 else if (code
== 'm')
5582 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5583 s390_extract_part (x
, SImode
, -1));
5584 else if (code
== 'o')
5585 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5587 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5591 gcc_assert (GET_MODE (x
) == VOIDmode
);
5593 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5594 else if (code
== 'x')
5595 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5596 else if (code
== 'h')
5597 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5598 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5602 output_operand_lossage ("invalid constant - try using "
5603 "an output modifier");
5605 output_operand_lossage ("invalid constant for output modifier '%c'",
5612 output_operand_lossage ("invalid expression - try using "
5613 "an output modifier");
5615 output_operand_lossage ("invalid expression for output "
5616 "modifier '%c'", code
);
5621 /* Target hook for assembling integer objects. We need to define it
5622 here to work a round a bug in some versions of GAS, which couldn't
5623 handle values smaller than INT_MIN when printed in decimal. */
5626 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5628 if (size
== 8 && aligned_p
5629 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5631 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5635 return default_assemble_integer (x
, size
, aligned_p
);
5638 /* Returns true if register REGNO is used for forming
5639 a memory address in expression X. */
5642 reg_used_in_mem_p (int regno
, rtx x
)
5644 enum rtx_code code
= GET_CODE (x
);
5650 if (refers_to_regno_p (regno
, regno
+1,
5654 else if (code
== SET
5655 && GET_CODE (SET_DEST (x
)) == PC
)
5657 if (refers_to_regno_p (regno
, regno
+1,
5662 fmt
= GET_RTX_FORMAT (code
);
5663 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5666 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5669 else if (fmt
[i
] == 'E')
5670 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5671 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5677 /* Returns true if expression DEP_RTX sets an address register
5678 used by instruction INSN to address memory. */
5681 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5685 if (GET_CODE (dep_rtx
) == INSN
)
5686 dep_rtx
= PATTERN (dep_rtx
);
5688 if (GET_CODE (dep_rtx
) == SET
)
5690 target
= SET_DEST (dep_rtx
);
5691 if (GET_CODE (target
) == STRICT_LOW_PART
)
5692 target
= XEXP (target
, 0);
5693 while (GET_CODE (target
) == SUBREG
)
5694 target
= SUBREG_REG (target
);
5696 if (GET_CODE (target
) == REG
)
5698 int regno
= REGNO (target
);
5700 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5702 pat
= PATTERN (insn
);
5703 if (GET_CODE (pat
) == PARALLEL
)
5705 gcc_assert (XVECLEN (pat
, 0) == 2);
5706 pat
= XVECEXP (pat
, 0, 0);
5708 gcc_assert (GET_CODE (pat
) == SET
);
5709 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5711 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5712 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5718 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5721 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5723 rtx dep_rtx
= PATTERN (dep_insn
);
5726 if (GET_CODE (dep_rtx
) == SET
5727 && addr_generation_dependency_p (dep_rtx
, insn
))
5729 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5731 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5733 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5741 /* A C statement (sans semicolon) to update the integer scheduling priority
5742 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5743 reduce the priority to execute INSN later. Do not define this macro if
5744 you do not need to adjust the scheduling priorities of insns.
5746 A STD instruction should be scheduled earlier,
5747 in order to use the bypass. */
5749 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5751 if (! INSN_P (insn
))
5754 if (s390_tune
!= PROCESSOR_2084_Z990
5755 && s390_tune
!= PROCESSOR_2094_Z9_109
5756 && s390_tune
!= PROCESSOR_2097_Z10
5757 && s390_tune
!= PROCESSOR_2817_Z196
5758 && s390_tune
!= PROCESSOR_2827_ZEC12
)
5761 switch (s390_safe_attr_type (insn
))
5765 priority
= priority
<< 3;
5769 priority
= priority
<< 1;
5778 /* The number of instructions that can be issued per cycle. */
5781 s390_issue_rate (void)
5785 case PROCESSOR_2084_Z990
:
5786 case PROCESSOR_2094_Z9_109
:
5787 case PROCESSOR_2817_Z196
:
5789 case PROCESSOR_2097_Z10
:
5790 case PROCESSOR_2827_ZEC12
:
5798 s390_first_cycle_multipass_dfa_lookahead (void)
5803 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5804 Fix up MEMs as required. */
5807 annotate_constant_pool_refs (rtx
*x
)
5812 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5813 || !CONSTANT_POOL_ADDRESS_P (*x
));
5815 /* Literal pool references can only occur inside a MEM ... */
5816 if (GET_CODE (*x
) == MEM
)
5818 rtx memref
= XEXP (*x
, 0);
5820 if (GET_CODE (memref
) == SYMBOL_REF
5821 && CONSTANT_POOL_ADDRESS_P (memref
))
5823 rtx base
= cfun
->machine
->base_reg
;
5824 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5827 *x
= replace_equiv_address (*x
, addr
);
5831 if (GET_CODE (memref
) == CONST
5832 && GET_CODE (XEXP (memref
, 0)) == PLUS
5833 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5834 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5835 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5837 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5838 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5839 rtx base
= cfun
->machine
->base_reg
;
5840 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5843 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
5848 /* ... or a load-address type pattern. */
5849 if (GET_CODE (*x
) == SET
)
5851 rtx addrref
= SET_SRC (*x
);
5853 if (GET_CODE (addrref
) == SYMBOL_REF
5854 && CONSTANT_POOL_ADDRESS_P (addrref
))
5856 rtx base
= cfun
->machine
->base_reg
;
5857 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5860 SET_SRC (*x
) = addr
;
5864 if (GET_CODE (addrref
) == CONST
5865 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5866 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5867 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5868 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5870 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5871 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5872 rtx base
= cfun
->machine
->base_reg
;
5873 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5876 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
5881 /* Annotate LTREL_BASE as well. */
5882 if (GET_CODE (*x
) == UNSPEC
5883 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5885 rtx base
= cfun
->machine
->base_reg
;
5886 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5891 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5892 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5896 annotate_constant_pool_refs (&XEXP (*x
, i
));
5898 else if (fmt
[i
] == 'E')
5900 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5901 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5906 /* Split all branches that exceed the maximum distance.
5907 Returns true if this created a new literal pool entry. */
5910 s390_split_branches (void)
5912 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5913 int new_literal
= 0, ret
;
5914 rtx insn
, pat
, tmp
, target
;
5917 /* We need correct insn addresses. */
5919 shorten_branches (get_insns ());
5921 /* Find all branches that exceed 64KB, and split them. */
5923 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5925 if (GET_CODE (insn
) != JUMP_INSN
)
5928 pat
= PATTERN (insn
);
5929 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5930 pat
= XVECEXP (pat
, 0, 0);
5931 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5934 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5936 label
= &SET_SRC (pat
);
5938 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5940 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5941 label
= &XEXP (SET_SRC (pat
), 1);
5942 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5943 label
= &XEXP (SET_SRC (pat
), 2);
5950 if (get_attr_length (insn
) <= 4)
5953 /* We are going to use the return register as scratch register,
5954 make sure it will be saved/restored by the prologue/epilogue. */
5955 cfun_frame_layout
.save_return_addr_p
= 1;
5960 tmp
= force_const_mem (Pmode
, *label
);
5961 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5962 INSN_ADDRESSES_NEW (tmp
, -1);
5963 annotate_constant_pool_refs (&PATTERN (tmp
));
5970 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5971 UNSPEC_LTREL_OFFSET
);
5972 target
= gen_rtx_CONST (Pmode
, target
);
5973 target
= force_const_mem (Pmode
, target
);
5974 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5975 INSN_ADDRESSES_NEW (tmp
, -1);
5976 annotate_constant_pool_refs (&PATTERN (tmp
));
5978 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5979 cfun
->machine
->base_reg
),
5981 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5984 ret
= validate_change (insn
, label
, target
, 0);
5992 /* Find an annotated literal pool symbol referenced in RTX X,
5993 and store it at REF. Will abort if X contains references to
5994 more than one such pool symbol; multiple references to the same
5995 symbol are allowed, however.
5997 The rtx pointed to by REF must be initialized to NULL_RTX
5998 by the caller before calling this routine. */
6001 find_constant_pool_ref (rtx x
, rtx
*ref
)
6006 /* Ignore LTREL_BASE references. */
6007 if (GET_CODE (x
) == UNSPEC
6008 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6010 /* Likewise POOL_ENTRY insns. */
6011 if (GET_CODE (x
) == UNSPEC_VOLATILE
6012 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
6015 gcc_assert (GET_CODE (x
) != SYMBOL_REF
6016 || !CONSTANT_POOL_ADDRESS_P (x
));
6018 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
6020 rtx sym
= XVECEXP (x
, 0, 0);
6021 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
6022 && CONSTANT_POOL_ADDRESS_P (sym
));
6024 if (*ref
== NULL_RTX
)
6027 gcc_assert (*ref
== sym
);
6032 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6033 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6037 find_constant_pool_ref (XEXP (x
, i
), ref
);
6039 else if (fmt
[i
] == 'E')
6041 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6042 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
6047 /* Replace every reference to the annotated literal pool
6048 symbol REF in X by its base plus OFFSET. */
6051 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
6056 gcc_assert (*x
!= ref
);
6058 if (GET_CODE (*x
) == UNSPEC
6059 && XINT (*x
, 1) == UNSPEC_LTREF
6060 && XVECEXP (*x
, 0, 0) == ref
)
6062 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
6066 if (GET_CODE (*x
) == PLUS
6067 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
6068 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
6069 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
6070 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
6072 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
6073 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
6077 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6078 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6082 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
6084 else if (fmt
[i
] == 'E')
6086 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6087 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
6092 /* Check whether X contains an UNSPEC_LTREL_BASE.
6093 Return its constant pool symbol if found, NULL_RTX otherwise. */
6096 find_ltrel_base (rtx x
)
6101 if (GET_CODE (x
) == UNSPEC
6102 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6103 return XVECEXP (x
, 0, 0);
6105 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6106 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6110 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
6114 else if (fmt
[i
] == 'E')
6116 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6118 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
6128 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6131 replace_ltrel_base (rtx
*x
)
6136 if (GET_CODE (*x
) == UNSPEC
6137 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
6139 *x
= XVECEXP (*x
, 0, 1);
6143 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6144 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6148 replace_ltrel_base (&XEXP (*x
, i
));
6150 else if (fmt
[i
] == 'E')
6152 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6153 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
6159 /* We keep a list of constants which we have to add to internal
6160 constant tables in the middle of large functions. */
6162 #define NR_C_MODES 11
6163 enum machine_mode constant_modes
[NR_C_MODES
] =
6165 TFmode
, TImode
, TDmode
,
6166 DFmode
, DImode
, DDmode
,
6167 SFmode
, SImode
, SDmode
,
6174 struct constant
*next
;
6179 struct constant_pool
6181 struct constant_pool
*next
;
6185 rtx emit_pool_after
;
6187 struct constant
*constants
[NR_C_MODES
];
6188 struct constant
*execute
;
6193 /* Allocate new constant_pool structure. */
6195 static struct constant_pool
*
6196 s390_alloc_pool (void)
6198 struct constant_pool
*pool
;
6201 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6203 for (i
= 0; i
< NR_C_MODES
; i
++)
6204 pool
->constants
[i
] = NULL
;
6206 pool
->execute
= NULL
;
6207 pool
->label
= gen_label_rtx ();
6208 pool
->first_insn
= NULL_RTX
;
6209 pool
->pool_insn
= NULL_RTX
;
6210 pool
->insns
= BITMAP_ALLOC (NULL
);
6212 pool
->emit_pool_after
= NULL_RTX
;
6217 /* Create new constant pool covering instructions starting at INSN
6218 and chain it to the end of POOL_LIST. */
6220 static struct constant_pool
*
6221 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
6223 struct constant_pool
*pool
, **prev
;
6225 pool
= s390_alloc_pool ();
6226 pool
->first_insn
= insn
;
6228 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6235 /* End range of instructions covered by POOL at INSN and emit
6236 placeholder insn representing the pool. */
6239 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
6241 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6244 insn
= get_last_insn ();
6246 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6247 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6250 /* Add INSN to the list of insns covered by POOL. */
6253 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6255 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6258 /* Return pool out of POOL_LIST that covers INSN. */
6260 static struct constant_pool
*
6261 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6263 struct constant_pool
*pool
;
6265 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6266 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6272 /* Add constant VAL of mode MODE to the constant pool POOL. */
6275 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6280 for (i
= 0; i
< NR_C_MODES
; i
++)
6281 if (constant_modes
[i
] == mode
)
6283 gcc_assert (i
!= NR_C_MODES
);
6285 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6286 if (rtx_equal_p (val
, c
->value
))
6291 c
= (struct constant
*) xmalloc (sizeof *c
);
6293 c
->label
= gen_label_rtx ();
6294 c
->next
= pool
->constants
[i
];
6295 pool
->constants
[i
] = c
;
6296 pool
->size
+= GET_MODE_SIZE (mode
);
6300 /* Return an rtx that represents the offset of X from the start of
6304 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6308 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6309 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6310 UNSPEC_POOL_OFFSET
);
6311 return gen_rtx_CONST (GET_MODE (x
), x
);
6314 /* Find constant VAL of mode MODE in the constant pool POOL.
6315 Return an RTX describing the distance from the start of
6316 the pool to the location of the new constant. */
6319 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6320 enum machine_mode mode
)
6325 for (i
= 0; i
< NR_C_MODES
; i
++)
6326 if (constant_modes
[i
] == mode
)
6328 gcc_assert (i
!= NR_C_MODES
);
6330 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6331 if (rtx_equal_p (val
, c
->value
))
6336 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6339 /* Check whether INSN is an execute. Return the label_ref to its
6340 execute target template if so, NULL_RTX otherwise. */
6343 s390_execute_label (rtx insn
)
6345 if (GET_CODE (insn
) == INSN
6346 && GET_CODE (PATTERN (insn
)) == PARALLEL
6347 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6348 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6349 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6354 /* Add execute target for INSN to the constant pool POOL. */
6357 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6361 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6362 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6367 c
= (struct constant
*) xmalloc (sizeof *c
);
6369 c
->label
= gen_label_rtx ();
6370 c
->next
= pool
->execute
;
6376 /* Find execute target for INSN in the constant pool POOL.
6377 Return an RTX describing the distance from the start of
6378 the pool to the location of the execute target. */
6381 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6385 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6386 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6391 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6394 /* For an execute INSN, extract the execute target template. */
6397 s390_execute_target (rtx insn
)
6399 rtx pattern
= PATTERN (insn
);
6400 gcc_assert (s390_execute_label (insn
));
6402 if (XVECLEN (pattern
, 0) == 2)
6404 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6408 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6411 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6412 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6414 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6420 /* Indicate that INSN cannot be duplicated. This is the case for
6421 execute insns that carry a unique label. */
6424 s390_cannot_copy_insn_p (rtx insn
)
6426 rtx label
= s390_execute_label (insn
);
6427 return label
&& label
!= const0_rtx
;
6430 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6431 do not emit the pool base label. */
6434 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6437 rtx insn
= pool
->pool_insn
;
6440 /* Switch to rodata section. */
6441 if (TARGET_CPU_ZARCH
)
6443 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6444 INSN_ADDRESSES_NEW (insn
, -1);
6447 /* Ensure minimum pool alignment. */
6448 if (TARGET_CPU_ZARCH
)
6449 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6451 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6452 INSN_ADDRESSES_NEW (insn
, -1);
6454 /* Emit pool base label. */
6457 insn
= emit_label_after (pool
->label
, insn
);
6458 INSN_ADDRESSES_NEW (insn
, -1);
6461 /* Dump constants in descending alignment requirement order,
6462 ensuring proper alignment for every constant. */
6463 for (i
= 0; i
< NR_C_MODES
; i
++)
6464 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6466 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6467 rtx value
= copy_rtx (c
->value
);
6468 if (GET_CODE (value
) == CONST
6469 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6470 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6471 && XVECLEN (XEXP (value
, 0), 0) == 1)
6472 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6474 insn
= emit_label_after (c
->label
, insn
);
6475 INSN_ADDRESSES_NEW (insn
, -1);
6477 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6478 gen_rtvec (1, value
),
6479 UNSPECV_POOL_ENTRY
);
6480 insn
= emit_insn_after (value
, insn
);
6481 INSN_ADDRESSES_NEW (insn
, -1);
6484 /* Ensure minimum alignment for instructions. */
6485 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6486 INSN_ADDRESSES_NEW (insn
, -1);
6488 /* Output in-pool execute template insns. */
6489 for (c
= pool
->execute
; c
; c
= c
->next
)
6491 insn
= emit_label_after (c
->label
, insn
);
6492 INSN_ADDRESSES_NEW (insn
, -1);
6494 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6495 INSN_ADDRESSES_NEW (insn
, -1);
6498 /* Switch back to previous section. */
6499 if (TARGET_CPU_ZARCH
)
6501 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6502 INSN_ADDRESSES_NEW (insn
, -1);
6505 insn
= emit_barrier_after (insn
);
6506 INSN_ADDRESSES_NEW (insn
, -1);
6508 /* Remove placeholder insn. */
6509 remove_insn (pool
->pool_insn
);
6512 /* Free all memory used by POOL. */
6515 s390_free_pool (struct constant_pool
*pool
)
6517 struct constant
*c
, *next
;
6520 for (i
= 0; i
< NR_C_MODES
; i
++)
6521 for (c
= pool
->constants
[i
]; c
; c
= next
)
6527 for (c
= pool
->execute
; c
; c
= next
)
6533 BITMAP_FREE (pool
->insns
);
6538 /* Collect main literal pool. Return NULL on overflow. */
6540 static struct constant_pool
*
6541 s390_mainpool_start (void)
6543 struct constant_pool
*pool
;
6546 pool
= s390_alloc_pool ();
6548 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6550 if (GET_CODE (insn
) == INSN
6551 && GET_CODE (PATTERN (insn
)) == SET
6552 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6553 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6555 gcc_assert (!pool
->pool_insn
);
6556 pool
->pool_insn
= insn
;
6559 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6561 s390_add_execute (pool
, insn
);
6563 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6565 rtx pool_ref
= NULL_RTX
;
6566 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6569 rtx constant
= get_pool_constant (pool_ref
);
6570 enum machine_mode mode
= get_pool_mode (pool_ref
);
6571 s390_add_constant (pool
, constant
, mode
);
6575 /* If hot/cold partitioning is enabled we have to make sure that
6576 the literal pool is emitted in the same section where the
6577 initialization of the literal pool base pointer takes place.
6578 emit_pool_after is only used in the non-overflow case on non
6579 Z cpus where we can emit the literal pool at the end of the
6580 function body within the text section. */
6582 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6583 && !pool
->emit_pool_after
)
6584 pool
->emit_pool_after
= PREV_INSN (insn
);
6587 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6589 if (pool
->size
>= 4096)
6591 /* We're going to chunkify the pool, so remove the main
6592 pool placeholder insn. */
6593 remove_insn (pool
->pool_insn
);
6595 s390_free_pool (pool
);
6599 /* If the functions ends with the section where the literal pool
6600 should be emitted set the marker to its end. */
6601 if (pool
&& !pool
->emit_pool_after
)
6602 pool
->emit_pool_after
= get_last_insn ();
6607 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6608 Modify the current function to output the pool constants as well as
6609 the pool register setup instruction. */
6612 s390_mainpool_finish (struct constant_pool
*pool
)
6614 rtx base_reg
= cfun
->machine
->base_reg
;
6617 /* If the pool is empty, we're done. */
6618 if (pool
->size
== 0)
6620 /* We don't actually need a base register after all. */
6621 cfun
->machine
->base_reg
= NULL_RTX
;
6623 if (pool
->pool_insn
)
6624 remove_insn (pool
->pool_insn
);
6625 s390_free_pool (pool
);
6629 /* We need correct insn addresses. */
6630 shorten_branches (get_insns ());
6632 /* On zSeries, we use a LARL to load the pool register. The pool is
6633 located in the .rodata section, so we emit it after the function. */
6634 if (TARGET_CPU_ZARCH
)
6636 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6637 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6638 INSN_ADDRESSES_NEW (insn
, -1);
6639 remove_insn (pool
->pool_insn
);
6641 insn
= get_last_insn ();
6642 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6643 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6645 s390_dump_pool (pool
, 0);
6648 /* On S/390, if the total size of the function's code plus literal pool
6649 does not exceed 4096 bytes, we use BASR to set up a function base
6650 pointer, and emit the literal pool at the end of the function. */
6651 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6652 + pool
->size
+ 8 /* alignment slop */ < 4096)
6654 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6655 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6656 INSN_ADDRESSES_NEW (insn
, -1);
6657 remove_insn (pool
->pool_insn
);
6659 insn
= emit_label_after (pool
->label
, insn
);
6660 INSN_ADDRESSES_NEW (insn
, -1);
6662 /* emit_pool_after will be set by s390_mainpool_start to the
6663 last insn of the section where the literal pool should be
6665 insn
= pool
->emit_pool_after
;
6667 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6668 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6670 s390_dump_pool (pool
, 1);
6673 /* Otherwise, we emit an inline literal pool and use BASR to branch
6674 over it, setting up the pool register at the same time. */
6677 rtx pool_end
= gen_label_rtx ();
6679 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6680 insn
= emit_jump_insn_after (insn
, pool
->pool_insn
);
6681 JUMP_LABEL (insn
) = pool_end
;
6682 INSN_ADDRESSES_NEW (insn
, -1);
6683 remove_insn (pool
->pool_insn
);
6685 insn
= emit_label_after (pool
->label
, insn
);
6686 INSN_ADDRESSES_NEW (insn
, -1);
6688 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6689 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6691 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6692 INSN_ADDRESSES_NEW (insn
, -1);
6694 s390_dump_pool (pool
, 1);
6698 /* Replace all literal pool references. */
6700 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6703 replace_ltrel_base (&PATTERN (insn
));
6705 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6707 rtx addr
, pool_ref
= NULL_RTX
;
6708 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6711 if (s390_execute_label (insn
))
6712 addr
= s390_find_execute (pool
, insn
);
6714 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6715 get_pool_mode (pool_ref
));
6717 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6718 INSN_CODE (insn
) = -1;
6724 /* Free the pool. */
6725 s390_free_pool (pool
);
6728 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6729 We have decided we cannot use this pool, so revert all changes
6730 to the current function that were done by s390_mainpool_start. */
6732 s390_mainpool_cancel (struct constant_pool
*pool
)
6734 /* We didn't actually change the instruction stream, so simply
6735 free the pool memory. */
6736 s390_free_pool (pool
);
6740 /* Chunkify the literal pool. */
6742 #define S390_POOL_CHUNK_MIN 0xc00
6743 #define S390_POOL_CHUNK_MAX 0xe00
6745 static struct constant_pool
*
6746 s390_chunkify_start (void)
6748 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6751 rtx pending_ltrel
= NULL_RTX
;
6754 rtx (*gen_reload_base
) (rtx
, rtx
) =
6755 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6758 /* We need correct insn addresses. */
6760 shorten_branches (get_insns ());
6762 /* Scan all insns and move literals to pool chunks. */
6764 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6766 bool section_switch_p
= false;
6768 /* Check for pending LTREL_BASE. */
6771 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6774 gcc_assert (ltrel_base
== pending_ltrel
);
6775 pending_ltrel
= NULL_RTX
;
6779 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6782 curr_pool
= s390_start_pool (&pool_list
, insn
);
6784 s390_add_execute (curr_pool
, insn
);
6785 s390_add_pool_insn (curr_pool
, insn
);
6787 else if (GET_CODE (insn
) == INSN
|| CALL_P (insn
))
6789 rtx pool_ref
= NULL_RTX
;
6790 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6793 rtx constant
= get_pool_constant (pool_ref
);
6794 enum machine_mode mode
= get_pool_mode (pool_ref
);
6797 curr_pool
= s390_start_pool (&pool_list
, insn
);
6799 s390_add_constant (curr_pool
, constant
, mode
);
6800 s390_add_pool_insn (curr_pool
, insn
);
6802 /* Don't split the pool chunk between a LTREL_OFFSET load
6803 and the corresponding LTREL_BASE. */
6804 if (GET_CODE (constant
) == CONST
6805 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6806 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6808 gcc_assert (!pending_ltrel
);
6809 pending_ltrel
= pool_ref
;
6814 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6817 s390_add_pool_insn (curr_pool
, insn
);
6818 /* An LTREL_BASE must follow within the same basic block. */
6819 gcc_assert (!pending_ltrel
);
6823 switch (NOTE_KIND (insn
))
6825 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
6826 section_switch_p
= true;
6828 case NOTE_INSN_VAR_LOCATION
:
6829 case NOTE_INSN_CALL_ARG_LOCATION
:
6836 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6837 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6840 if (TARGET_CPU_ZARCH
)
6842 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6845 s390_end_pool (curr_pool
, NULL_RTX
);
6850 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6851 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6854 /* We will later have to insert base register reload insns.
6855 Those will have an effect on code size, which we need to
6856 consider here. This calculation makes rather pessimistic
6857 worst-case assumptions. */
6858 if (GET_CODE (insn
) == CODE_LABEL
)
6861 if (chunk_size
< S390_POOL_CHUNK_MIN
6862 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6863 && !section_switch_p
)
6866 /* Pool chunks can only be inserted after BARRIERs ... */
6867 if (GET_CODE (insn
) == BARRIER
)
6869 s390_end_pool (curr_pool
, insn
);
6874 /* ... so if we don't find one in time, create one. */
6875 else if (chunk_size
> S390_POOL_CHUNK_MAX
6876 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6877 || section_switch_p
)
6879 rtx label
, jump
, barrier
, next
, prev
;
6881 if (!section_switch_p
)
6883 /* We can insert the barrier only after a 'real' insn. */
6884 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6886 if (get_attr_length (insn
) == 0)
6888 /* Don't separate LTREL_BASE from the corresponding
6889 LTREL_OFFSET load. */
6896 next
= NEXT_INSN (insn
);
6900 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
6901 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
6905 gcc_assert (!pending_ltrel
);
6907 /* The old pool has to end before the section switch
6908 note in order to make it part of the current
6910 insn
= PREV_INSN (insn
);
6913 label
= gen_label_rtx ();
6915 if (prev
&& NOTE_P (prev
))
6916 prev
= prev_nonnote_insn (prev
);
6918 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
6919 INSN_LOCATION (prev
));
6921 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
6922 barrier
= emit_barrier_after (jump
);
6923 insn
= emit_label_after (label
, barrier
);
6924 JUMP_LABEL (jump
) = label
;
6925 LABEL_NUSES (label
) = 1;
6927 INSN_ADDRESSES_NEW (jump
, -1);
6928 INSN_ADDRESSES_NEW (barrier
, -1);
6929 INSN_ADDRESSES_NEW (insn
, -1);
6931 s390_end_pool (curr_pool
, barrier
);
6939 s390_end_pool (curr_pool
, NULL_RTX
);
6940 gcc_assert (!pending_ltrel
);
6942 /* Find all labels that are branched into
6943 from an insn belonging to a different chunk. */
6945 far_labels
= BITMAP_ALLOC (NULL
);
6947 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6949 /* Labels marked with LABEL_PRESERVE_P can be target
6950 of non-local jumps, so we have to mark them.
6951 The same holds for named labels.
6953 Don't do that, however, if it is the label before
6956 if (GET_CODE (insn
) == CODE_LABEL
6957 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6959 rtx vec_insn
= next_real_insn (insn
);
6960 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6961 PATTERN (vec_insn
) : NULL_RTX
;
6963 || !(GET_CODE (vec_pat
) == ADDR_VEC
6964 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6965 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6968 /* If we have a direct jump (conditional or unconditional)
6969 or a casesi jump, check all potential targets. */
6970 else if (GET_CODE (insn
) == JUMP_INSN
)
6972 rtx pat
= PATTERN (insn
);
6973 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6974 pat
= XVECEXP (pat
, 0, 0);
6976 if (GET_CODE (pat
) == SET
)
6978 rtx label
= JUMP_LABEL (insn
);
6981 if (s390_find_pool (pool_list
, label
)
6982 != s390_find_pool (pool_list
, insn
))
6983 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6986 else if (GET_CODE (pat
) == PARALLEL
6987 && XVECLEN (pat
, 0) == 2
6988 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6989 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6990 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6992 /* Find the jump table used by this casesi jump. */
6993 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6994 rtx vec_insn
= next_real_insn (vec_label
);
6995 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6996 PATTERN (vec_insn
) : NULL_RTX
;
6998 && (GET_CODE (vec_pat
) == ADDR_VEC
6999 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
7001 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
7003 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
7005 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
7007 if (s390_find_pool (pool_list
, label
)
7008 != s390_find_pool (pool_list
, insn
))
7009 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
7016 /* Insert base register reload insns before every pool. */
7018 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7020 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7022 rtx insn
= curr_pool
->first_insn
;
7023 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
7026 /* Insert base register reload insns at every far label. */
7028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7029 if (GET_CODE (insn
) == CODE_LABEL
7030 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
7032 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
7035 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
7037 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
7042 BITMAP_FREE (far_labels
);
7045 /* Recompute insn addresses. */
7047 init_insn_lengths ();
7048 shorten_branches (get_insns ());
7053 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7054 After we have decided to use this list, finish implementing
7055 all changes to the current function as required. */
7058 s390_chunkify_finish (struct constant_pool
*pool_list
)
7060 struct constant_pool
*curr_pool
= NULL
;
7064 /* Replace all literal pool references. */
7066 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7069 replace_ltrel_base (&PATTERN (insn
));
7071 curr_pool
= s390_find_pool (pool_list
, insn
);
7075 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
7077 rtx addr
, pool_ref
= NULL_RTX
;
7078 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
7081 if (s390_execute_label (insn
))
7082 addr
= s390_find_execute (curr_pool
, insn
);
7084 addr
= s390_find_constant (curr_pool
,
7085 get_pool_constant (pool_ref
),
7086 get_pool_mode (pool_ref
));
7088 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
7089 INSN_CODE (insn
) = -1;
7094 /* Dump out all literal pools. */
7096 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7097 s390_dump_pool (curr_pool
, 0);
7099 /* Free pool list. */
7103 struct constant_pool
*next
= pool_list
->next
;
7104 s390_free_pool (pool_list
);
7109 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7110 We have decided we cannot use this list, so revert all changes
7111 to the current function that were done by s390_chunkify_start. */
7114 s390_chunkify_cancel (struct constant_pool
*pool_list
)
7116 struct constant_pool
*curr_pool
= NULL
;
7119 /* Remove all pool placeholder insns. */
7121 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7123 /* Did we insert an extra barrier? Remove it. */
7124 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
7125 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
7126 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
7128 if (jump
&& GET_CODE (jump
) == JUMP_INSN
7129 && barrier
&& GET_CODE (barrier
) == BARRIER
7130 && label
&& GET_CODE (label
) == CODE_LABEL
7131 && GET_CODE (PATTERN (jump
)) == SET
7132 && SET_DEST (PATTERN (jump
)) == pc_rtx
7133 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
7134 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
7137 remove_insn (barrier
);
7138 remove_insn (label
);
7141 remove_insn (curr_pool
->pool_insn
);
7144 /* Remove all base register reload insns. */
7146 for (insn
= get_insns (); insn
; )
7148 rtx next_insn
= NEXT_INSN (insn
);
7150 if (GET_CODE (insn
) == INSN
7151 && GET_CODE (PATTERN (insn
)) == SET
7152 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
7153 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
7159 /* Free pool list. */
7163 struct constant_pool
*next
= pool_list
->next
;
7164 s390_free_pool (pool_list
);
7169 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7172 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
7176 switch (GET_MODE_CLASS (mode
))
7179 case MODE_DECIMAL_FLOAT
:
7180 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
7182 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
7183 assemble_real (r
, mode
, align
);
7187 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
7188 mark_symbol_refs_as_used (exp
);
7197 /* Return an RTL expression representing the value of the return address
7198 for the frame COUNT steps up from the current frame. FRAME is the
7199 frame pointer of that frame. */
7202 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7207 /* Without backchain, we fail for all but the current frame. */
7209 if (!TARGET_BACKCHAIN
&& count
> 0)
7212 /* For the current frame, we need to make sure the initial
7213 value of RETURN_REGNUM is actually saved. */
7217 /* On non-z architectures branch splitting could overwrite r14. */
7218 if (TARGET_CPU_ZARCH
)
7219 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7222 cfun_frame_layout
.save_return_addr_p
= true;
7223 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7227 if (TARGET_PACKED_STACK
)
7228 offset
= -2 * UNITS_PER_LONG
;
7230 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7232 addr
= plus_constant (Pmode
, frame
, offset
);
7233 addr
= memory_address (Pmode
, addr
);
7234 return gen_rtx_MEM (Pmode
, addr
);
7237 /* Return an RTL expression representing the back chain stored in
7238 the current stack frame. */
7241 s390_back_chain_rtx (void)
7245 gcc_assert (TARGET_BACKCHAIN
);
7247 if (TARGET_PACKED_STACK
)
7248 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
7249 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7251 chain
= stack_pointer_rtx
;
7253 chain
= gen_rtx_MEM (Pmode
, chain
);
7257 /* Find first call clobbered register unused in a function.
7258 This could be used as base register in a leaf function
7259 or for holding the return address before epilogue. */
7262 find_unused_clobbered_reg (void)
7265 for (i
= 0; i
< 6; i
++)
7266 if (!df_regs_ever_live_p (i
))
7272 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7273 clobbered hard regs in SETREG. */
7276 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7278 int *regs_ever_clobbered
= (int *)data
;
7279 unsigned int i
, regno
;
7280 enum machine_mode mode
= GET_MODE (setreg
);
7282 if (GET_CODE (setreg
) == SUBREG
)
7284 rtx inner
= SUBREG_REG (setreg
);
7285 if (!GENERAL_REG_P (inner
))
7287 regno
= subreg_regno (setreg
);
7289 else if (GENERAL_REG_P (setreg
))
7290 regno
= REGNO (setreg
);
7295 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7297 regs_ever_clobbered
[i
] = 1;
7300 /* Walks through all basic blocks of the current function looking
7301 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7302 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7303 each of those regs. */
7306 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7312 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7314 /* For non-leaf functions we have to consider all call clobbered regs to be
7318 for (i
= 0; i
< 16; i
++)
7319 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7322 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7323 this work is done by liveness analysis (mark_regs_live_at_end).
7324 Special care is needed for functions containing landing pads. Landing pads
7325 may use the eh registers, but the code which sets these registers is not
7326 contained in that function. Hence s390_regs_ever_clobbered is not able to
7327 deal with this automatically. */
7328 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7329 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7330 if (crtl
->calls_eh_return
7331 || (cfun
->machine
->has_landing_pad_p
7332 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7333 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7335 /* For nonlocal gotos all call-saved registers have to be saved.
7336 This flag is also set for the unwinding code in libgcc.
7337 See expand_builtin_unwind_init. For regs_ever_live this is done by
7339 if (cfun
->has_nonlocal_label
)
7340 for (i
= 0; i
< 16; i
++)
7341 if (!call_really_used_regs
[i
])
7342 regs_ever_clobbered
[i
] = 1;
7344 FOR_EACH_BB (cur_bb
)
7346 FOR_BB_INSNS (cur_bb
, cur_insn
)
7348 if (INSN_P (cur_insn
))
7349 note_stores (PATTERN (cur_insn
),
7350 s390_reg_clobbered_rtx
,
7351 regs_ever_clobbered
);
7356 /* Determine the frame area which actually has to be accessed
7357 in the function epilogue. The values are stored at the
7358 given pointers AREA_BOTTOM (address of the lowest used stack
7359 address) and AREA_TOP (address of the first item which does
7360 not belong to the stack frame). */
7363 s390_frame_area (int *area_bottom
, int *area_top
)
7371 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7373 b
= (cfun_frame_layout
.gprs_offset
7374 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7375 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7376 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7379 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7381 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7382 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7383 + cfun_frame_layout
.high_fprs
* 8));
7387 for (i
= 2; i
< 4; i
++)
7388 if (cfun_fpr_bit_p (i
))
7390 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7391 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7398 /* Fill cfun->machine with info about register usage of current function.
7399 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7402 s390_register_info (int clobbered_regs
[])
7406 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7407 cfun_frame_layout
.fpr_bitmap
= 0;
7408 cfun_frame_layout
.high_fprs
= 0;
7410 for (i
= 24; i
< 32; i
++)
7411 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7413 cfun_set_fpr_bit (i
- 16);
7414 cfun_frame_layout
.high_fprs
++;
7417 /* Find first and last gpr to be saved. We trust regs_ever_live
7418 data, except that we don't save and restore global registers.
7420 Also, all registers with special meaning to the compiler need
7421 to be handled extra. */
7423 s390_regs_ever_clobbered (clobbered_regs
);
7425 for (i
= 0; i
< 16; i
++)
7426 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7428 if (frame_pointer_needed
)
7429 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7432 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7433 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7435 clobbered_regs
[BASE_REGNUM
]
7436 |= (cfun
->machine
->base_reg
7437 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7439 clobbered_regs
[RETURN_REGNUM
]
7441 || TARGET_TPF_PROFILING
7442 || cfun
->machine
->split_branches_pending_p
7443 || cfun_frame_layout
.save_return_addr_p
7444 || crtl
->calls_eh_return
7447 clobbered_regs
[STACK_POINTER_REGNUM
]
7449 || TARGET_TPF_PROFILING
7450 || cfun_save_high_fprs_p
7451 || get_frame_size () > 0
7452 || cfun
->calls_alloca
7455 for (i
= 6; i
< 16; i
++)
7456 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7458 for (j
= 15; j
> i
; j
--)
7459 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7464 /* Nothing to save/restore. */
7465 cfun_frame_layout
.first_save_gpr_slot
= -1;
7466 cfun_frame_layout
.last_save_gpr_slot
= -1;
7467 cfun_frame_layout
.first_save_gpr
= -1;
7468 cfun_frame_layout
.first_restore_gpr
= -1;
7469 cfun_frame_layout
.last_save_gpr
= -1;
7470 cfun_frame_layout
.last_restore_gpr
= -1;
7474 /* Save slots for gprs from i to j. */
7475 cfun_frame_layout
.first_save_gpr_slot
= i
;
7476 cfun_frame_layout
.last_save_gpr_slot
= j
;
7478 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7479 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7481 if (clobbered_regs
[i
])
7484 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7485 if (clobbered_regs
[j
])
7488 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7490 /* Nothing to save/restore. */
7491 cfun_frame_layout
.first_save_gpr
= -1;
7492 cfun_frame_layout
.first_restore_gpr
= -1;
7493 cfun_frame_layout
.last_save_gpr
= -1;
7494 cfun_frame_layout
.last_restore_gpr
= -1;
7498 /* Save / Restore from gpr i to j. */
7499 cfun_frame_layout
.first_save_gpr
= i
;
7500 cfun_frame_layout
.first_restore_gpr
= i
;
7501 cfun_frame_layout
.last_save_gpr
= j
;
7502 cfun_frame_layout
.last_restore_gpr
= j
;
7508 /* Varargs functions need to save gprs 2 to 6. */
7509 if (cfun
->va_list_gpr_size
7510 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7512 int min_gpr
= crtl
->args
.info
.gprs
;
7513 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7514 if (max_gpr
> GP_ARG_NUM_REG
)
7515 max_gpr
= GP_ARG_NUM_REG
;
7517 if (cfun_frame_layout
.first_save_gpr
== -1
7518 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7520 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7521 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7524 if (cfun_frame_layout
.last_save_gpr
== -1
7525 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7527 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7528 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7532 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7533 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7534 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7536 int min_fpr
= crtl
->args
.info
.fprs
;
7537 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7538 if (max_fpr
> FP_ARG_NUM_REG
)
7539 max_fpr
= FP_ARG_NUM_REG
;
7541 /* ??? This is currently required to ensure proper location
7542 of the fpr save slots within the va_list save area. */
7543 if (TARGET_PACKED_STACK
)
7546 for (i
= min_fpr
; i
< max_fpr
; i
++)
7547 cfun_set_fpr_bit (i
);
7552 for (i
= 2; i
< 4; i
++)
7553 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7554 cfun_set_fpr_bit (i
);
7557 /* Fill cfun->machine with info about frame of current function. */
7560 s390_frame_info (void)
7564 cfun_frame_layout
.frame_size
= get_frame_size ();
7565 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7566 fatal_error ("total size of local variables exceeds architecture limit");
7568 if (!TARGET_PACKED_STACK
)
7570 cfun_frame_layout
.backchain_offset
= 0;
7571 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7572 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7573 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7574 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7577 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7579 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7581 cfun_frame_layout
.gprs_offset
7582 = (cfun_frame_layout
.backchain_offset
7583 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7588 cfun_frame_layout
.f4_offset
7589 = (cfun_frame_layout
.gprs_offset
7590 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7592 cfun_frame_layout
.f0_offset
7593 = (cfun_frame_layout
.f4_offset
7594 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7598 /* On 31 bit we have to care about alignment of the
7599 floating point regs to provide fastest access. */
7600 cfun_frame_layout
.f0_offset
7601 = ((cfun_frame_layout
.gprs_offset
7602 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7603 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7605 cfun_frame_layout
.f4_offset
7606 = (cfun_frame_layout
.f0_offset
7607 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7610 else /* no backchain */
7612 cfun_frame_layout
.f4_offset
7613 = (STACK_POINTER_OFFSET
7614 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7616 cfun_frame_layout
.f0_offset
7617 = (cfun_frame_layout
.f4_offset
7618 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7620 cfun_frame_layout
.gprs_offset
7621 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7625 && !TARGET_TPF_PROFILING
7626 && cfun_frame_layout
.frame_size
== 0
7627 && !cfun_save_high_fprs_p
7628 && !cfun
->calls_alloca
7632 if (!TARGET_PACKED_STACK
)
7633 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7634 + crtl
->outgoing_args_size
7635 + cfun_frame_layout
.high_fprs
* 8);
7638 if (TARGET_BACKCHAIN
)
7639 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7641 /* No alignment trouble here because f8-f15 are only saved under
7643 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7644 cfun_frame_layout
.f4_offset
),
7645 cfun_frame_layout
.gprs_offset
)
7646 - cfun_frame_layout
.high_fprs
* 8);
7648 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7650 for (i
= 0; i
< 8; i
++)
7651 if (cfun_fpr_bit_p (i
))
7652 cfun_frame_layout
.frame_size
+= 8;
7654 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7656 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7657 the frame size to sustain 8 byte alignment of stack frames. */
7658 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7659 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7660 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7662 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7666 /* Generate frame layout. Fills in register and frame data for the current
7667 function in cfun->machine. This routine can be called multiple times;
7668 it will re-do the complete frame layout every time. */
7671 s390_init_frame_layout (void)
7673 HOST_WIDE_INT frame_size
;
7675 int clobbered_regs
[16];
7677 /* On S/390 machines, we may need to perform branch splitting, which
7678 will require both base and return address register. We have no
7679 choice but to assume we're going to need them until right at the
7680 end of the machine dependent reorg phase. */
7681 if (!TARGET_CPU_ZARCH
)
7682 cfun
->machine
->split_branches_pending_p
= true;
7686 frame_size
= cfun_frame_layout
.frame_size
;
7688 /* Try to predict whether we'll need the base register. */
7689 base_used
= cfun
->machine
->split_branches_pending_p
7690 || crtl
->uses_const_pool
7691 || (!DISP_IN_RANGE (frame_size
)
7692 && !CONST_OK_FOR_K (frame_size
));
7694 /* Decide which register to use as literal pool base. In small
7695 leaf functions, try to use an unused call-clobbered register
7696 as base register to avoid save/restore overhead. */
7698 cfun
->machine
->base_reg
= NULL_RTX
;
7699 else if (crtl
->is_leaf
&& !df_regs_ever_live_p (5))
7700 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7702 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7704 s390_register_info (clobbered_regs
);
7707 while (frame_size
!= cfun_frame_layout
.frame_size
);
7710 /* Update frame layout. Recompute actual register save data based on
7711 current info and update regs_ever_live for the special registers.
7712 May be called multiple times, but may never cause *more* registers
7713 to be saved than s390_init_frame_layout allocated room for. */
7716 s390_update_frame_layout (void)
7718 int clobbered_regs
[16];
7720 s390_register_info (clobbered_regs
);
7722 df_set_regs_ever_live (BASE_REGNUM
,
7723 clobbered_regs
[BASE_REGNUM
] ? true : false);
7724 df_set_regs_ever_live (RETURN_REGNUM
,
7725 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7726 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7727 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7729 if (cfun
->machine
->base_reg
)
7730 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7733 /* Return true if it is legal to put a value with MODE into REGNO. */
7736 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7738 switch (REGNO_REG_CLASS (regno
))
7741 if (REGNO_PAIR_OK (regno
, mode
))
7743 if (mode
== SImode
|| mode
== DImode
)
7746 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7751 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7756 if (REGNO_PAIR_OK (regno
, mode
))
7759 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7764 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7768 if (REGNO_PAIR_OK (regno
, mode
))
7770 if (mode
== SImode
|| mode
== Pmode
)
7781 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7784 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7786 /* Once we've decided upon a register to use as base register, it must
7787 no longer be used for any other purpose. */
7788 if (cfun
->machine
->base_reg
)
7789 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7790 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7796 /* Maximum number of registers to represent a value of mode MODE
7797 in a register of class RCLASS. */
7800 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7805 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7806 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7808 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7810 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7814 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7817 /* Return true if register FROM can be eliminated via register TO. */
7820 s390_can_eliminate (const int from
, const int to
)
7822 /* On zSeries machines, we have not marked the base register as fixed.
7823 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7824 If a function requires the base register, we say here that this
7825 elimination cannot be performed. This will cause reload to free
7826 up the base register (as if it were fixed). On the other hand,
7827 if the current function does *not* require the base register, we
7828 say here the elimination succeeds, which in turn allows reload
7829 to allocate the base register for any other purpose. */
7830 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7832 if (TARGET_CPU_ZARCH
)
7834 s390_init_frame_layout ();
7835 return cfun
->machine
->base_reg
== NULL_RTX
;
7841 /* Everything else must point into the stack frame. */
7842 gcc_assert (to
== STACK_POINTER_REGNUM
7843 || to
== HARD_FRAME_POINTER_REGNUM
);
7845 gcc_assert (from
== FRAME_POINTER_REGNUM
7846 || from
== ARG_POINTER_REGNUM
7847 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7849 /* Make sure we actually saved the return address. */
7850 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7851 if (!crtl
->calls_eh_return
7853 && !cfun_frame_layout
.save_return_addr_p
)
7859 /* Return offset between register FROM and TO initially after prolog. */
7862 s390_initial_elimination_offset (int from
, int to
)
7864 HOST_WIDE_INT offset
;
7867 /* ??? Why are we called for non-eliminable pairs? */
7868 if (!s390_can_eliminate (from
, to
))
7873 case FRAME_POINTER_REGNUM
:
7874 offset
= (get_frame_size()
7875 + STACK_POINTER_OFFSET
7876 + crtl
->outgoing_args_size
);
7879 case ARG_POINTER_REGNUM
:
7880 s390_init_frame_layout ();
7881 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7884 case RETURN_ADDRESS_POINTER_REGNUM
:
7885 s390_init_frame_layout ();
7886 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7887 gcc_assert (index
>= 0);
7888 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7889 offset
+= index
* UNITS_PER_LONG
;
7903 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7904 to register BASE. Return generated insn. */
7907 save_fpr (rtx base
, int offset
, int regnum
)
7910 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
7912 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7913 set_mem_alias_set (addr
, get_varargs_alias_set ());
7915 set_mem_alias_set (addr
, get_frame_alias_set ());
7917 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7920 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7921 to register BASE. Return generated insn. */
7924 restore_fpr (rtx base
, int offset
, int regnum
)
7927 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
7928 set_mem_alias_set (addr
, get_frame_alias_set ());
7930 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7933 /* Return true if REGNO is a global register, but not one
7934 of the special ones that need to be saved/restored in anyway. */
7937 global_not_special_regno_p (int regno
)
7939 return (global_regs
[regno
]
7940 /* These registers are special and need to be
7941 restored in any case. */
7942 && !(regno
== STACK_POINTER_REGNUM
7943 || regno
== RETURN_REGNUM
7944 || regno
== BASE_REGNUM
7945 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7948 /* Generate insn to save registers FIRST to LAST into
7949 the register save area located at offset OFFSET
7950 relative to register BASE. */
7953 save_gprs (rtx base
, int offset
, int first
, int last
)
7955 rtx addr
, insn
, note
;
7958 addr
= plus_constant (Pmode
, base
, offset
);
7959 addr
= gen_rtx_MEM (Pmode
, addr
);
7961 set_mem_alias_set (addr
, get_frame_alias_set ());
7963 /* Special-case single register. */
7967 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7969 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7971 if (!global_not_special_regno_p (first
))
7972 RTX_FRAME_RELATED_P (insn
) = 1;
7977 insn
= gen_store_multiple (addr
,
7978 gen_rtx_REG (Pmode
, first
),
7979 GEN_INT (last
- first
+ 1));
7981 if (first
<= 6 && cfun
->stdarg
)
7982 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7984 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7987 set_mem_alias_set (mem
, get_varargs_alias_set ());
7990 /* We need to set the FRAME_RELATED flag on all SETs
7991 inside the store-multiple pattern.
7993 However, we must not emit DWARF records for registers 2..5
7994 if they are stored for use by variable arguments ...
7996 ??? Unfortunately, it is not enough to simply not the
7997 FRAME_RELATED flags for those SETs, because the first SET
7998 of the PARALLEL is always treated as if it had the flag
7999 set, even if it does not. Therefore we emit a new pattern
8000 without those registers as REG_FRAME_RELATED_EXPR note. */
8002 if (first
>= 6 && !global_not_special_regno_p (first
))
8004 rtx pat
= PATTERN (insn
);
8006 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
8007 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
8008 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
8010 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
8012 RTX_FRAME_RELATED_P (insn
) = 1;
8018 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
8019 if (!global_not_special_regno_p (start
))
8025 addr
= plus_constant (Pmode
, base
,
8026 offset
+ (start
- first
) * UNITS_PER_LONG
);
8027 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
8028 gen_rtx_REG (Pmode
, start
),
8029 GEN_INT (last
- start
+ 1));
8030 note
= PATTERN (note
);
8032 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
8034 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
8035 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
8036 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
8038 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
8040 RTX_FRAME_RELATED_P (insn
) = 1;
8046 /* Generate insn to restore registers FIRST to LAST from
8047 the register save area located at offset OFFSET
8048 relative to register BASE. */
8051 restore_gprs (rtx base
, int offset
, int first
, int last
)
8055 addr
= plus_constant (Pmode
, base
, offset
);
8056 addr
= gen_rtx_MEM (Pmode
, addr
);
8057 set_mem_alias_set (addr
, get_frame_alias_set ());
8059 /* Special-case single register. */
8063 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
8065 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
8070 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
8072 GEN_INT (last
- first
+ 1));
8076 /* Return insn sequence to load the GOT register. */
8078 static GTY(()) rtx got_symbol
;
8080 s390_load_got (void)
8084 /* We cannot use pic_offset_table_rtx here since we use this
8085 function also for non-pic if __tls_get_offset is called and in
8086 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8088 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
8092 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8093 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
8098 if (TARGET_CPU_ZARCH
)
8100 emit_move_insn (got_rtx
, got_symbol
);
8106 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
8107 UNSPEC_LTREL_OFFSET
);
8108 offset
= gen_rtx_CONST (Pmode
, offset
);
8109 offset
= force_const_mem (Pmode
, offset
);
8111 emit_move_insn (got_rtx
, offset
);
8113 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
8115 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
8117 emit_move_insn (got_rtx
, offset
);
8120 insns
= get_insns ();
8125 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8126 and the change to the stack pointer. */
8129 s390_emit_stack_tie (void)
8131 rtx mem
= gen_frame_mem (BLKmode
,
8132 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
8134 emit_insn (gen_stack_tie (mem
));
8137 /* Expand the prologue into a bunch of separate insns. */
8140 s390_emit_prologue (void)
8148 /* Complete frame layout. */
8150 s390_update_frame_layout ();
8152 /* Annotate all constant pool references to let the scheduler know
8153 they implicitly use the base register. */
8155 push_topmost_sequence ();
8157 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8160 annotate_constant_pool_refs (&PATTERN (insn
));
8161 df_insn_rescan (insn
);
8164 pop_topmost_sequence ();
8166 /* Choose best register to use for temp use within prologue.
8167 See below for why TPF must use the register 1. */
8169 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
8171 && !TARGET_TPF_PROFILING
)
8172 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8174 temp_reg
= gen_rtx_REG (Pmode
, 1);
8176 /* Save call saved gprs. */
8177 if (cfun_frame_layout
.first_save_gpr
!= -1)
8179 insn
= save_gprs (stack_pointer_rtx
,
8180 cfun_frame_layout
.gprs_offset
+
8181 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
8182 - cfun_frame_layout
.first_save_gpr_slot
),
8183 cfun_frame_layout
.first_save_gpr
,
8184 cfun_frame_layout
.last_save_gpr
);
8188 /* Dummy insn to mark literal pool slot. */
8190 if (cfun
->machine
->base_reg
)
8191 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8193 offset
= cfun_frame_layout
.f0_offset
;
8195 /* Save f0 and f2. */
8196 for (i
= 0; i
< 2; i
++)
8198 if (cfun_fpr_bit_p (i
))
8200 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8203 else if (!TARGET_PACKED_STACK
)
8207 /* Save f4 and f6. */
8208 offset
= cfun_frame_layout
.f4_offset
;
8209 for (i
= 2; i
< 4; i
++)
8211 if (cfun_fpr_bit_p (i
))
8213 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8216 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8217 therefore are not frame related. */
8218 if (!call_really_used_regs
[i
+ 16])
8219 RTX_FRAME_RELATED_P (insn
) = 1;
8221 else if (!TARGET_PACKED_STACK
)
8225 if (TARGET_PACKED_STACK
8226 && cfun_save_high_fprs_p
8227 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8229 offset
= (cfun_frame_layout
.f8_offset
8230 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8232 for (i
= 15; i
> 7 && offset
>= 0; i
--)
8233 if (cfun_fpr_bit_p (i
))
8235 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8237 RTX_FRAME_RELATED_P (insn
) = 1;
8240 if (offset
>= cfun_frame_layout
.f8_offset
)
8244 if (!TARGET_PACKED_STACK
)
8245 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
8247 if (flag_stack_usage_info
)
8248 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8250 /* Decrement stack pointer. */
8252 if (cfun_frame_layout
.frame_size
> 0)
8254 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8257 if (s390_stack_size
)
8259 HOST_WIDE_INT stack_guard
;
8261 if (s390_stack_guard
)
8262 stack_guard
= s390_stack_guard
;
8265 /* If no value for stack guard is provided the smallest power of 2
8266 larger than the current frame size is chosen. */
8268 while (stack_guard
< cfun_frame_layout
.frame_size
)
8272 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8274 warning (0, "frame size of function %qs is %wd"
8275 " bytes exceeding user provided stack limit of "
8277 "An unconditional trap is added.",
8278 current_function_name(), cfun_frame_layout
.frame_size
,
8280 emit_insn (gen_trap ());
8284 /* stack_guard has to be smaller than s390_stack_size.
8285 Otherwise we would emit an AND with zero which would
8286 not match the test under mask pattern. */
8287 if (stack_guard
>= s390_stack_size
)
8289 warning (0, "frame size of function %qs is %wd"
8290 " bytes which is more than half the stack size. "
8291 "The dynamic check would not be reliable. "
8292 "No check emitted for this function.",
8293 current_function_name(),
8294 cfun_frame_layout
.frame_size
);
8298 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8299 & ~(stack_guard
- 1));
8301 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8302 GEN_INT (stack_check_mask
));
8304 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8306 t
, const0_rtx
, const0_rtx
));
8308 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8310 t
, const0_rtx
, const0_rtx
));
8315 if (s390_warn_framesize
> 0
8316 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8317 warning (0, "frame size of %qs is %wd bytes",
8318 current_function_name (), cfun_frame_layout
.frame_size
);
8320 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8321 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8323 /* Save incoming stack pointer into temp reg. */
8324 if (TARGET_BACKCHAIN
|| next_fpr
)
8325 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8327 /* Subtract frame size from stack pointer. */
8329 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8331 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8332 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8334 insn
= emit_insn (insn
);
8338 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8339 frame_off
= force_const_mem (Pmode
, frame_off
);
8341 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8342 annotate_constant_pool_refs (&PATTERN (insn
));
8345 RTX_FRAME_RELATED_P (insn
) = 1;
8346 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8347 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8348 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8349 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8352 /* Set backchain. */
8354 if (TARGET_BACKCHAIN
)
8356 if (cfun_frame_layout
.backchain_offset
)
8357 addr
= gen_rtx_MEM (Pmode
,
8358 plus_constant (Pmode
, stack_pointer_rtx
,
8359 cfun_frame_layout
.backchain_offset
));
8361 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8362 set_mem_alias_set (addr
, get_frame_alias_set ());
8363 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8366 /* If we support non-call exceptions (e.g. for Java),
8367 we need to make sure the backchain pointer is set up
8368 before any possibly trapping memory access. */
8369 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8371 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8372 emit_clobber (addr
);
8376 /* Save fprs 8 - 15 (64 bit ABI). */
8378 if (cfun_save_high_fprs_p
&& next_fpr
)
8380 /* If the stack might be accessed through a different register
8381 we have to make sure that the stack pointer decrement is not
8382 moved below the use of the stack slots. */
8383 s390_emit_stack_tie ();
8385 insn
= emit_insn (gen_add2_insn (temp_reg
,
8386 GEN_INT (cfun_frame_layout
.f8_offset
)));
8390 for (i
= 24; i
<= next_fpr
; i
++)
8391 if (cfun_fpr_bit_p (i
- 16))
8393 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
8394 cfun_frame_layout
.frame_size
8395 + cfun_frame_layout
.f8_offset
8398 insn
= save_fpr (temp_reg
, offset
, i
);
8400 RTX_FRAME_RELATED_P (insn
) = 1;
8401 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8402 gen_rtx_SET (VOIDmode
,
8403 gen_rtx_MEM (DFmode
, addr
),
8404 gen_rtx_REG (DFmode
, i
)));
8408 /* Set frame pointer, if needed. */
8410 if (frame_pointer_needed
)
8412 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8413 RTX_FRAME_RELATED_P (insn
) = 1;
8416 /* Set up got pointer, if needed. */
8418 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8420 rtx insns
= s390_load_got ();
8422 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8423 annotate_constant_pool_refs (&PATTERN (insn
));
8428 if (TARGET_TPF_PROFILING
)
8430 /* Generate a BAS instruction to serve as a function
8431 entry intercept to facilitate the use of tracing
8432 algorithms located at the branch target. */
8433 emit_insn (gen_prologue_tpf ());
8435 /* Emit a blockage here so that all code
8436 lies between the profiling mechanisms. */
8437 emit_insn (gen_blockage ());
8441 /* Expand the epilogue into a bunch of separate insns. */
8444 s390_emit_epilogue (bool sibcall
)
8446 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8447 int area_bottom
, area_top
, offset
= 0;
8452 if (TARGET_TPF_PROFILING
)
8455 /* Generate a BAS instruction to serve as a function
8456 entry intercept to facilitate the use of tracing
8457 algorithms located at the branch target. */
8459 /* Emit a blockage here so that all code
8460 lies between the profiling mechanisms. */
8461 emit_insn (gen_blockage ());
8463 emit_insn (gen_epilogue_tpf ());
8466 /* Check whether to use frame or stack pointer for restore. */
8468 frame_pointer
= (frame_pointer_needed
8469 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8471 s390_frame_area (&area_bottom
, &area_top
);
8473 /* Check whether we can access the register save area.
8474 If not, increment the frame pointer as required. */
8476 if (area_top
<= area_bottom
)
8478 /* Nothing to restore. */
8480 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8481 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8483 /* Area is in range. */
8484 offset
= cfun_frame_layout
.frame_size
;
8488 rtx insn
, frame_off
, cfa
;
8490 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8491 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8493 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8494 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8495 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8497 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8498 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8499 insn
= emit_insn (insn
);
8503 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8504 frame_off
= force_const_mem (Pmode
, frame_off
);
8506 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8507 annotate_constant_pool_refs (&PATTERN (insn
));
8509 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8510 RTX_FRAME_RELATED_P (insn
) = 1;
8513 /* Restore call saved fprs. */
8517 if (cfun_save_high_fprs_p
)
8519 next_offset
= cfun_frame_layout
.f8_offset
;
8520 for (i
= 24; i
< 32; i
++)
8522 if (cfun_fpr_bit_p (i
- 16))
8524 restore_fpr (frame_pointer
,
8525 offset
+ next_offset
, i
);
8527 = alloc_reg_note (REG_CFA_RESTORE
,
8528 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8537 next_offset
= cfun_frame_layout
.f4_offset
;
8538 for (i
= 18; i
< 20; i
++)
8540 if (cfun_fpr_bit_p (i
- 16))
8542 restore_fpr (frame_pointer
,
8543 offset
+ next_offset
, i
);
8545 = alloc_reg_note (REG_CFA_RESTORE
,
8546 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8549 else if (!TARGET_PACKED_STACK
)
8555 /* Return register. */
8557 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8559 /* Restore call saved gprs. */
8561 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8566 /* Check for global register and save them
8567 to stack location from where they get restored. */
8569 for (i
= cfun_frame_layout
.first_restore_gpr
;
8570 i
<= cfun_frame_layout
.last_restore_gpr
;
8573 if (global_not_special_regno_p (i
))
8575 addr
= plus_constant (Pmode
, frame_pointer
,
8576 offset
+ cfun_frame_layout
.gprs_offset
8577 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8579 addr
= gen_rtx_MEM (Pmode
, addr
);
8580 set_mem_alias_set (addr
, get_frame_alias_set ());
8581 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8585 = alloc_reg_note (REG_CFA_RESTORE
,
8586 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8591 /* Fetch return address from stack before load multiple,
8592 this will do good for scheduling. */
8594 if (cfun_frame_layout
.save_return_addr_p
8595 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8596 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8598 int return_regnum
= find_unused_clobbered_reg();
8601 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8603 addr
= plus_constant (Pmode
, frame_pointer
,
8604 offset
+ cfun_frame_layout
.gprs_offset
8606 - cfun_frame_layout
.first_save_gpr_slot
)
8608 addr
= gen_rtx_MEM (Pmode
, addr
);
8609 set_mem_alias_set (addr
, get_frame_alias_set ());
8610 emit_move_insn (return_reg
, addr
);
8614 insn
= restore_gprs (frame_pointer
,
8615 offset
+ cfun_frame_layout
.gprs_offset
8616 + (cfun_frame_layout
.first_restore_gpr
8617 - cfun_frame_layout
.first_save_gpr_slot
)
8619 cfun_frame_layout
.first_restore_gpr
,
8620 cfun_frame_layout
.last_restore_gpr
);
8621 insn
= emit_insn (insn
);
8622 REG_NOTES (insn
) = cfa_restores
;
8623 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8624 plus_constant (Pmode
, stack_pointer_rtx
,
8625 STACK_POINTER_OFFSET
));
8626 RTX_FRAME_RELATED_P (insn
) = 1;
8632 /* Return to caller. */
8634 p
= rtvec_alloc (2);
8636 RTVEC_ELT (p
, 0) = ret_rtx
;
8637 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8638 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8643 /* Return the size in bytes of a function argument of
8644 type TYPE and/or mode MODE. At least one of TYPE or
8645 MODE must be specified. */
8648 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8651 return int_size_in_bytes (type
);
8653 /* No type info available for some library calls ... */
8654 if (mode
!= BLKmode
)
8655 return GET_MODE_SIZE (mode
);
8657 /* If we have neither type nor mode, abort */
8661 /* Return true if a function argument of type TYPE and mode MODE
8662 is to be passed in a floating-point register, if available. */
8665 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8667 int size
= s390_function_arg_size (mode
, type
);
8671 /* Soft-float changes the ABI: no floating-point registers are used. */
8672 if (TARGET_SOFT_FLOAT
)
8675 /* No type info available for some library calls ... */
8677 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8679 /* The ABI says that record types with a single member are treated
8680 just like that member would be. */
8681 while (TREE_CODE (type
) == RECORD_TYPE
)
8683 tree field
, single
= NULL_TREE
;
8685 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8687 if (TREE_CODE (field
) != FIELD_DECL
)
8690 if (single
== NULL_TREE
)
8691 single
= TREE_TYPE (field
);
8696 if (single
== NULL_TREE
)
8702 return TREE_CODE (type
) == REAL_TYPE
;
8705 /* Return true if a function argument of type TYPE and mode MODE
8706 is to be passed in an integer register, or a pair of integer
8707 registers, if available. */
8710 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8712 int size
= s390_function_arg_size (mode
, type
);
8716 /* No type info available for some library calls ... */
8718 return GET_MODE_CLASS (mode
) == MODE_INT
8719 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8721 /* We accept small integral (and similar) types. */
8722 if (INTEGRAL_TYPE_P (type
)
8723 || POINTER_TYPE_P (type
)
8724 || TREE_CODE (type
) == NULLPTR_TYPE
8725 || TREE_CODE (type
) == OFFSET_TYPE
8726 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8729 /* We also accept structs of size 1, 2, 4, 8 that are not
8730 passed in floating-point registers. */
8731 if (AGGREGATE_TYPE_P (type
)
8732 && exact_log2 (size
) >= 0
8733 && !s390_function_arg_float (mode
, type
))
8739 /* Return 1 if a function argument of type TYPE and mode MODE
8740 is to be passed by reference. The ABI specifies that only
8741 structures of size 1, 2, 4, or 8 bytes are passed by value,
8742 all other structures (and complex numbers) are passed by
8746 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
8747 enum machine_mode mode
, const_tree type
,
8748 bool named ATTRIBUTE_UNUSED
)
8750 int size
= s390_function_arg_size (mode
, type
);
8756 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8759 if (TREE_CODE (type
) == COMPLEX_TYPE
8760 || TREE_CODE (type
) == VECTOR_TYPE
)
8767 /* Update the data in CUM to advance over an argument of mode MODE and
8768 data type TYPE. (TYPE is null for libcalls where that information
8769 may not be available.). The boolean NAMED specifies whether the
8770 argument is a named argument (as opposed to an unnamed argument
8771 matching an ellipsis). */
8774 s390_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
8775 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8777 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8779 if (s390_function_arg_float (mode
, type
))
8783 else if (s390_function_arg_integer (mode
, type
))
8785 int size
= s390_function_arg_size (mode
, type
);
8786 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8792 /* Define where to put the arguments to a function.
8793 Value is zero to push the argument on the stack,
8794 or a hard register in which to store the argument.
8796 MODE is the argument's machine mode.
8797 TYPE is the data type of the argument (as a tree).
8798 This is null for libcalls where that information may
8800 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8801 the preceding args and about the function being called.
8802 NAMED is nonzero if this argument is a named parameter
8803 (otherwise it is an extra parameter matching an ellipsis).
8805 On S/390, we use general purpose registers 2 through 6 to
8806 pass integer, pointer, and certain structure arguments, and
8807 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8808 to pass floating point arguments. All remaining arguments
8809 are pushed to the stack. */
8812 s390_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8813 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8815 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8817 if (s390_function_arg_float (mode
, type
))
8819 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8822 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8824 else if (s390_function_arg_integer (mode
, type
))
8826 int size
= s390_function_arg_size (mode
, type
);
8827 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8829 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8831 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8832 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8833 else if (n_gprs
== 2)
8835 rtvec p
= rtvec_alloc (2);
8838 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8841 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8844 return gen_rtx_PARALLEL (mode
, p
);
8848 /* After the real arguments, expand_call calls us once again
8849 with a void_type_node type. Whatever we return here is
8850 passed as operand 2 to the call expanders.
8852 We don't need this feature ... */
8853 else if (type
== void_type_node
)
8859 /* Return true if return values of type TYPE should be returned
8860 in a memory buffer whose address is passed by the caller as
8861 hidden first argument. */
8864 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8866 /* We accept small integral (and similar) types. */
8867 if (INTEGRAL_TYPE_P (type
)
8868 || POINTER_TYPE_P (type
)
8869 || TREE_CODE (type
) == OFFSET_TYPE
8870 || TREE_CODE (type
) == REAL_TYPE
)
8871 return int_size_in_bytes (type
) > 8;
8873 /* Aggregates and similar constructs are always returned
8875 if (AGGREGATE_TYPE_P (type
)
8876 || TREE_CODE (type
) == COMPLEX_TYPE
8877 || TREE_CODE (type
) == VECTOR_TYPE
)
8880 /* ??? We get called on all sorts of random stuff from
8881 aggregate_value_p. We can't abort, but it's not clear
8882 what's safe to return. Pretend it's a struct I guess. */
8886 /* Function arguments and return values are promoted to word size. */
8888 static enum machine_mode
8889 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8891 const_tree fntype ATTRIBUTE_UNUSED
,
8892 int for_return ATTRIBUTE_UNUSED
)
8894 if (INTEGRAL_MODE_P (mode
)
8895 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8897 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
8898 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8905 /* Define where to return a (scalar) value of type RET_TYPE.
8906 If RET_TYPE is null, define where to return a (scalar)
8907 value of mode MODE from a libcall. */
8910 s390_function_and_libcall_value (enum machine_mode mode
,
8911 const_tree ret_type
,
8912 const_tree fntype_or_decl
,
8913 bool outgoing ATTRIBUTE_UNUSED
)
8915 /* For normal functions perform the promotion as
8916 promote_function_mode would do. */
8919 int unsignedp
= TYPE_UNSIGNED (ret_type
);
8920 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
8924 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8925 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8927 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8928 return gen_rtx_REG (mode
, 16);
8929 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8930 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8931 return gen_rtx_REG (mode
, 2);
8932 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8934 /* This case is triggered when returning a 64 bit value with
8935 -m31 -mzarch. Although the value would fit into a single
8936 register it has to be forced into a 32 bit register pair in
8937 order to match the ABI. */
8938 rtvec p
= rtvec_alloc (2);
8941 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8943 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8945 return gen_rtx_PARALLEL (mode
, p
);
8951 /* Define where to return a scalar return value of type RET_TYPE. */
8954 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
8957 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
8958 fn_decl_or_type
, outgoing
);
8961 /* Define where to return a scalar libcall return value of mode
8965 s390_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8967 return s390_function_and_libcall_value (mode
, NULL_TREE
,
8972 /* Create and return the va_list datatype.
8974 On S/390, va_list is an array type equivalent to
8976 typedef struct __va_list_tag
8980 void *__overflow_arg_area;
8981 void *__reg_save_area;
8984 where __gpr and __fpr hold the number of general purpose
8985 or floating point arguments used up to now, respectively,
8986 __overflow_arg_area points to the stack location of the
8987 next argument passed on the stack, and __reg_save_area
8988 always points to the start of the register area in the
8989 call frame of the current function. The function prologue
8990 saves all registers used for argument passing into this
8991 area if the function uses variable arguments. */
8994 s390_build_builtin_va_list (void)
8996 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8998 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
9001 build_decl (BUILTINS_LOCATION
,
9002 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
9004 f_gpr
= build_decl (BUILTINS_LOCATION
,
9005 FIELD_DECL
, get_identifier ("__gpr"),
9006 long_integer_type_node
);
9007 f_fpr
= build_decl (BUILTINS_LOCATION
,
9008 FIELD_DECL
, get_identifier ("__fpr"),
9009 long_integer_type_node
);
9010 f_ovf
= build_decl (BUILTINS_LOCATION
,
9011 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
9013 f_sav
= build_decl (BUILTINS_LOCATION
,
9014 FIELD_DECL
, get_identifier ("__reg_save_area"),
9017 va_list_gpr_counter_field
= f_gpr
;
9018 va_list_fpr_counter_field
= f_fpr
;
9020 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9021 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9022 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9023 DECL_FIELD_CONTEXT (f_sav
) = record
;
9025 TYPE_STUB_DECL (record
) = type_decl
;
9026 TYPE_NAME (record
) = type_decl
;
9027 TYPE_FIELDS (record
) = f_gpr
;
9028 DECL_CHAIN (f_gpr
) = f_fpr
;
9029 DECL_CHAIN (f_fpr
) = f_ovf
;
9030 DECL_CHAIN (f_ovf
) = f_sav
;
9032 layout_type (record
);
9034 /* The correct type is an array type of one element. */
9035 return build_array_type (record
, build_index_type (size_zero_node
));
9038 /* Implement va_start by filling the va_list structure VALIST.
9039 STDARG_P is always true, and ignored.
9040 NEXTARG points to the first anonymous stack argument.
9042 The following global variables are used to initialize
9043 the va_list structure:
9046 holds number of gprs and fprs used for named arguments.
9047 crtl->args.arg_offset_rtx:
9048 holds the offset of the first anonymous stack argument
9049 (relative to the virtual arg pointer). */
9052 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
9054 HOST_WIDE_INT n_gpr
, n_fpr
;
9056 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9057 tree gpr
, fpr
, ovf
, sav
, t
;
9059 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9060 f_fpr
= DECL_CHAIN (f_gpr
);
9061 f_ovf
= DECL_CHAIN (f_fpr
);
9062 f_sav
= DECL_CHAIN (f_ovf
);
9064 valist
= build_simple_mem_ref (valist
);
9065 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9066 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9067 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9068 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9070 /* Count number of gp and fp argument registers used. */
9072 n_gpr
= crtl
->args
.info
.gprs
;
9073 n_fpr
= crtl
->args
.info
.fprs
;
9075 if (cfun
->va_list_gpr_size
)
9077 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9078 build_int_cst (NULL_TREE
, n_gpr
));
9079 TREE_SIDE_EFFECTS (t
) = 1;
9080 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9083 if (cfun
->va_list_fpr_size
)
9085 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9086 build_int_cst (NULL_TREE
, n_fpr
));
9087 TREE_SIDE_EFFECTS (t
) = 1;
9088 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9091 /* Find the overflow area. */
9092 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
9093 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
9095 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9097 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
9098 off
= off
< 0 ? 0 : off
;
9099 if (TARGET_DEBUG_ARG
)
9100 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9101 (int)n_gpr
, (int)n_fpr
, off
);
9103 t
= fold_build_pointer_plus_hwi (t
, off
);
9105 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9106 TREE_SIDE_EFFECTS (t
) = 1;
9107 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9110 /* Find the register save area. */
9111 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
9112 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
9114 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
9115 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
9117 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9118 TREE_SIDE_EFFECTS (t
) = 1;
9119 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9123 /* Implement va_arg by updating the va_list structure
9124 VALIST as required to retrieve an argument of type
9125 TYPE, and returning that argument.
9127 Generates code equivalent to:
9129 if (integral value) {
9130 if (size <= 4 && args.gpr < 5 ||
9131 size > 4 && args.gpr < 4 )
9132 ret = args.reg_save_area[args.gpr+8]
9134 ret = *args.overflow_arg_area++;
9135 } else if (float value) {
9137 ret = args.reg_save_area[args.fpr+64]
9139 ret = *args.overflow_arg_area++;
9140 } else if (aggregate value) {
9142 ret = *args.reg_save_area[args.gpr]
9144 ret = **args.overflow_arg_area++;
9148 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9149 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
9151 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9152 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9153 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
9154 tree lab_false
, lab_over
, addr
;
9156 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9157 f_fpr
= DECL_CHAIN (f_gpr
);
9158 f_ovf
= DECL_CHAIN (f_fpr
);
9159 f_sav
= DECL_CHAIN (f_ovf
);
9161 valist
= build_va_arg_indirect_ref (valist
);
9162 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9163 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9164 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9166 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9167 both appear on a lhs. */
9168 valist
= unshare_expr (valist
);
9169 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9171 size
= int_size_in_bytes (type
);
9173 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9175 if (TARGET_DEBUG_ARG
)
9177 fprintf (stderr
, "va_arg: aggregate type");
9181 /* Aggregates are passed by reference. */
9186 /* kernel stack layout on 31 bit: It is assumed here that no padding
9187 will be added by s390_frame_info because for va_args always an even
9188 number of gprs has to be saved r15-r2 = 14 regs. */
9189 sav_ofs
= 2 * UNITS_PER_LONG
;
9190 sav_scale
= UNITS_PER_LONG
;
9191 size
= UNITS_PER_LONG
;
9192 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9194 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9196 if (TARGET_DEBUG_ARG
)
9198 fprintf (stderr
, "va_arg: float type");
9202 /* FP args go in FP registers, if present. */
9206 sav_ofs
= 16 * UNITS_PER_LONG
;
9208 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9212 if (TARGET_DEBUG_ARG
)
9214 fprintf (stderr
, "va_arg: other type");
9218 /* Otherwise into GP registers. */
9221 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9223 /* kernel stack layout on 31 bit: It is assumed here that no padding
9224 will be added by s390_frame_info because for va_args always an even
9225 number of gprs has to be saved r15-r2 = 14 regs. */
9226 sav_ofs
= 2 * UNITS_PER_LONG
;
9228 if (size
< UNITS_PER_LONG
)
9229 sav_ofs
+= UNITS_PER_LONG
- size
;
9231 sav_scale
= UNITS_PER_LONG
;
9232 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9235 /* Pull the value out of the saved registers ... */
9237 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9238 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9239 addr
= create_tmp_var (ptr_type_node
, "addr");
9241 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9242 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9243 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9244 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9245 gimplify_and_add (t
, pre_p
);
9247 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9248 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9249 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9250 t
= fold_build_pointer_plus (t
, u
);
9252 gimplify_assign (addr
, t
, pre_p
);
9254 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9256 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9259 /* ... Otherwise out of the overflow area. */
9262 if (size
< UNITS_PER_LONG
)
9263 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
9265 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9267 gimplify_assign (addr
, t
, pre_p
);
9269 t
= fold_build_pointer_plus_hwi (t
, size
);
9270 gimplify_assign (ovf
, t
, pre_p
);
9272 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9275 /* Increment register save count. */
9277 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9278 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9279 gimplify_and_add (u
, pre_p
);
9283 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9285 addr
= fold_convert (t
, addr
);
9286 addr
= build_va_arg_indirect_ref (addr
);
9290 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9291 addr
= fold_convert (t
, addr
);
9294 return build_va_arg_indirect_ref (addr
);
9297 /* Output assembly code for the trampoline template to
9300 On S/390, we use gpr 1 internally in the trampoline code;
9301 gpr 0 is used to hold the static chain. */
9304 s390_asm_trampoline_template (FILE *file
)
9307 op
[0] = gen_rtx_REG (Pmode
, 0);
9308 op
[1] = gen_rtx_REG (Pmode
, 1);
9312 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9313 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
9314 output_asm_insn ("br\t%1", op
); /* 2 byte */
9315 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9319 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9320 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
9321 output_asm_insn ("br\t%1", op
); /* 2 byte */
9322 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9326 /* Emit RTL insns to initialize the variable parts of a trampoline.
9327 FNADDR is an RTX for the address of the function's pure code.
9328 CXT is an RTX for the static chain value for the function. */
9331 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9333 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9336 emit_block_move (m_tramp
, assemble_trampoline_template (),
9337 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
9339 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
9340 emit_move_insn (mem
, cxt
);
9341 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
9342 emit_move_insn (mem
, fnaddr
);
9345 /* Output assembler code to FILE to increment profiler label # LABELNO
9346 for profiling a function entry. */
9349 s390_function_profiler (FILE *file
, int labelno
)
9354 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9356 fprintf (file
, "# function profiler \n");
9358 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9359 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9360 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
9362 op
[2] = gen_rtx_REG (Pmode
, 1);
9363 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9364 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9366 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9369 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9370 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9375 output_asm_insn ("stg\t%0,%1", op
);
9376 output_asm_insn ("larl\t%2,%3", op
);
9377 output_asm_insn ("brasl\t%0,%4", op
);
9378 output_asm_insn ("lg\t%0,%1", op
);
9382 op
[6] = gen_label_rtx ();
9384 output_asm_insn ("st\t%0,%1", op
);
9385 output_asm_insn ("bras\t%2,%l6", op
);
9386 output_asm_insn (".long\t%4", op
);
9387 output_asm_insn (".long\t%3", op
);
9388 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9389 output_asm_insn ("l\t%0,0(%2)", op
);
9390 output_asm_insn ("l\t%2,4(%2)", op
);
9391 output_asm_insn ("basr\t%0,%0", op
);
9392 output_asm_insn ("l\t%0,%1", op
);
9396 op
[5] = gen_label_rtx ();
9397 op
[6] = gen_label_rtx ();
9399 output_asm_insn ("st\t%0,%1", op
);
9400 output_asm_insn ("bras\t%2,%l6", op
);
9401 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9402 output_asm_insn (".long\t%4-%l5", op
);
9403 output_asm_insn (".long\t%3-%l5", op
);
9404 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9405 output_asm_insn ("lr\t%0,%2", op
);
9406 output_asm_insn ("a\t%0,0(%2)", op
);
9407 output_asm_insn ("a\t%2,4(%2)", op
);
9408 output_asm_insn ("basr\t%0,%0", op
);
9409 output_asm_insn ("l\t%0,%1", op
);
9413 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9414 into its SYMBOL_REF_FLAGS. */
9417 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9419 default_encode_section_info (decl
, rtl
, first
);
9421 if (TREE_CODE (decl
) == VAR_DECL
)
9423 /* If a variable has a forced alignment to < 2 bytes, mark it
9424 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9426 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9427 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9428 if (!DECL_SIZE (decl
)
9429 || !DECL_ALIGN (decl
)
9430 || !host_integerp (DECL_SIZE (decl
), 0)
9431 || (DECL_ALIGN (decl
) <= 64
9432 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9433 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9436 /* Literal pool references don't have a decl so they are handled
9437 differently here. We rely on the information in the MEM_ALIGN
9438 entry to decide upon natural alignment. */
9440 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9441 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9442 && (MEM_ALIGN (rtl
) == 0
9443 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9444 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9445 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9448 /* Output thunk to FILE that implements a C++ virtual function call (with
9449 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9450 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9451 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9452 relative to the resulting this pointer. */
9455 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9456 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9462 /* Make sure unwind info is emitted for the thunk if needed. */
9463 final_start_function (emit_barrier (), file
, 1);
9465 /* Operand 0 is the target function. */
9466 op
[0] = XEXP (DECL_RTL (function
), 0);
9467 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9470 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9471 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9472 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9475 /* Operand 1 is the 'this' pointer. */
9476 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9477 op
[1] = gen_rtx_REG (Pmode
, 3);
9479 op
[1] = gen_rtx_REG (Pmode
, 2);
9481 /* Operand 2 is the delta. */
9482 op
[2] = GEN_INT (delta
);
9484 /* Operand 3 is the vcall_offset. */
9485 op
[3] = GEN_INT (vcall_offset
);
9487 /* Operand 4 is the temporary register. */
9488 op
[4] = gen_rtx_REG (Pmode
, 1);
9490 /* Operands 5 to 8 can be used as labels. */
9496 /* Operand 9 can be used for temporary register. */
9499 /* Generate code. */
9502 /* Setup literal pool pointer if required. */
9503 if ((!DISP_IN_RANGE (delta
)
9504 && !CONST_OK_FOR_K (delta
)
9505 && !CONST_OK_FOR_Os (delta
))
9506 || (!DISP_IN_RANGE (vcall_offset
)
9507 && !CONST_OK_FOR_K (vcall_offset
)
9508 && !CONST_OK_FOR_Os (vcall_offset
)))
9510 op
[5] = gen_label_rtx ();
9511 output_asm_insn ("larl\t%4,%5", op
);
9514 /* Add DELTA to this pointer. */
9517 if (CONST_OK_FOR_J (delta
))
9518 output_asm_insn ("la\t%1,%2(%1)", op
);
9519 else if (DISP_IN_RANGE (delta
))
9520 output_asm_insn ("lay\t%1,%2(%1)", op
);
9521 else if (CONST_OK_FOR_K (delta
))
9522 output_asm_insn ("aghi\t%1,%2", op
);
9523 else if (CONST_OK_FOR_Os (delta
))
9524 output_asm_insn ("agfi\t%1,%2", op
);
9527 op
[6] = gen_label_rtx ();
9528 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9532 /* Perform vcall adjustment. */
9535 if (DISP_IN_RANGE (vcall_offset
))
9537 output_asm_insn ("lg\t%4,0(%1)", op
);
9538 output_asm_insn ("ag\t%1,%3(%4)", op
);
9540 else if (CONST_OK_FOR_K (vcall_offset
))
9542 output_asm_insn ("lghi\t%4,%3", op
);
9543 output_asm_insn ("ag\t%4,0(%1)", op
);
9544 output_asm_insn ("ag\t%1,0(%4)", op
);
9546 else if (CONST_OK_FOR_Os (vcall_offset
))
9548 output_asm_insn ("lgfi\t%4,%3", op
);
9549 output_asm_insn ("ag\t%4,0(%1)", op
);
9550 output_asm_insn ("ag\t%1,0(%4)", op
);
9554 op
[7] = gen_label_rtx ();
9555 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9556 output_asm_insn ("ag\t%4,0(%1)", op
);
9557 output_asm_insn ("ag\t%1,0(%4)", op
);
9561 /* Jump to target. */
9562 output_asm_insn ("jg\t%0", op
);
9564 /* Output literal pool if required. */
9567 output_asm_insn (".align\t4", op
);
9568 targetm
.asm_out
.internal_label (file
, "L",
9569 CODE_LABEL_NUMBER (op
[5]));
9573 targetm
.asm_out
.internal_label (file
, "L",
9574 CODE_LABEL_NUMBER (op
[6]));
9575 output_asm_insn (".long\t%2", op
);
9579 targetm
.asm_out
.internal_label (file
, "L",
9580 CODE_LABEL_NUMBER (op
[7]));
9581 output_asm_insn (".long\t%3", op
);
9586 /* Setup base pointer if required. */
9588 || (!DISP_IN_RANGE (delta
)
9589 && !CONST_OK_FOR_K (delta
)
9590 && !CONST_OK_FOR_Os (delta
))
9591 || (!DISP_IN_RANGE (delta
)
9592 && !CONST_OK_FOR_K (vcall_offset
)
9593 && !CONST_OK_FOR_Os (vcall_offset
)))
9595 op
[5] = gen_label_rtx ();
9596 output_asm_insn ("basr\t%4,0", op
);
9597 targetm
.asm_out
.internal_label (file
, "L",
9598 CODE_LABEL_NUMBER (op
[5]));
9601 /* Add DELTA to this pointer. */
9604 if (CONST_OK_FOR_J (delta
))
9605 output_asm_insn ("la\t%1,%2(%1)", op
);
9606 else if (DISP_IN_RANGE (delta
))
9607 output_asm_insn ("lay\t%1,%2(%1)", op
);
9608 else if (CONST_OK_FOR_K (delta
))
9609 output_asm_insn ("ahi\t%1,%2", op
);
9610 else if (CONST_OK_FOR_Os (delta
))
9611 output_asm_insn ("afi\t%1,%2", op
);
9614 op
[6] = gen_label_rtx ();
9615 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9619 /* Perform vcall adjustment. */
9622 if (CONST_OK_FOR_J (vcall_offset
))
9624 output_asm_insn ("l\t%4,0(%1)", op
);
9625 output_asm_insn ("a\t%1,%3(%4)", op
);
9627 else if (DISP_IN_RANGE (vcall_offset
))
9629 output_asm_insn ("l\t%4,0(%1)", op
);
9630 output_asm_insn ("ay\t%1,%3(%4)", op
);
9632 else if (CONST_OK_FOR_K (vcall_offset
))
9634 output_asm_insn ("lhi\t%4,%3", op
);
9635 output_asm_insn ("a\t%4,0(%1)", op
);
9636 output_asm_insn ("a\t%1,0(%4)", op
);
9638 else if (CONST_OK_FOR_Os (vcall_offset
))
9640 output_asm_insn ("iilf\t%4,%3", op
);
9641 output_asm_insn ("a\t%4,0(%1)", op
);
9642 output_asm_insn ("a\t%1,0(%4)", op
);
9646 op
[7] = gen_label_rtx ();
9647 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9648 output_asm_insn ("a\t%4,0(%1)", op
);
9649 output_asm_insn ("a\t%1,0(%4)", op
);
9652 /* We had to clobber the base pointer register.
9653 Re-setup the base pointer (with a different base). */
9654 op
[5] = gen_label_rtx ();
9655 output_asm_insn ("basr\t%4,0", op
);
9656 targetm
.asm_out
.internal_label (file
, "L",
9657 CODE_LABEL_NUMBER (op
[5]));
9660 /* Jump to target. */
9661 op
[8] = gen_label_rtx ();
9664 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9666 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9667 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9668 else if (flag_pic
== 1)
9670 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9671 output_asm_insn ("l\t%4,%0(%4)", op
);
9673 else if (flag_pic
== 2)
9675 op
[9] = gen_rtx_REG (Pmode
, 0);
9676 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9677 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9678 output_asm_insn ("ar\t%4,%9", op
);
9679 output_asm_insn ("l\t%4,0(%4)", op
);
9682 output_asm_insn ("br\t%4", op
);
9684 /* Output literal pool. */
9685 output_asm_insn (".align\t4", op
);
9687 if (nonlocal
&& flag_pic
== 2)
9688 output_asm_insn (".long\t%0", op
);
9691 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9692 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9695 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9697 output_asm_insn (".long\t%0", op
);
9699 output_asm_insn (".long\t%0-%5", op
);
9703 targetm
.asm_out
.internal_label (file
, "L",
9704 CODE_LABEL_NUMBER (op
[6]));
9705 output_asm_insn (".long\t%2", op
);
9709 targetm
.asm_out
.internal_label (file
, "L",
9710 CODE_LABEL_NUMBER (op
[7]));
9711 output_asm_insn (".long\t%3", op
);
9714 final_end_function ();
9718 s390_valid_pointer_mode (enum machine_mode mode
)
9720 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9723 /* Checks whether the given CALL_EXPR would use a caller
9724 saved register. This is used to decide whether sibling call
9725 optimization could be performed on the respective function
9729 s390_call_saved_register_used (tree call_expr
)
9731 CUMULATIVE_ARGS cum_v
;
9732 cumulative_args_t cum
;
9734 enum machine_mode mode
;
9739 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
9740 cum
= pack_cumulative_args (&cum_v
);
9742 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9744 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9745 gcc_assert (parameter
);
9747 /* For an undeclared variable passed as parameter we will get
9748 an ERROR_MARK node here. */
9749 if (TREE_CODE (parameter
) == ERROR_MARK
)
9752 type
= TREE_TYPE (parameter
);
9755 mode
= TYPE_MODE (type
);
9758 if (pass_by_reference (&cum_v
, mode
, type
, true))
9761 type
= build_pointer_type (type
);
9764 parm_rtx
= s390_function_arg (cum
, mode
, type
, 0);
9766 s390_function_arg_advance (cum
, mode
, type
, 0);
9771 if (REG_P (parm_rtx
))
9774 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9776 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9780 if (GET_CODE (parm_rtx
) == PARALLEL
)
9784 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9786 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9788 gcc_assert (REG_P (r
));
9791 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9793 if (!call_used_regs
[reg
+ REGNO (r
)])
9802 /* Return true if the given call expression can be
9803 turned into a sibling call.
9804 DECL holds the declaration of the function to be called whereas
9805 EXP is the call expression itself. */
9808 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9810 /* The TPF epilogue uses register 1. */
9811 if (TARGET_TPF_PROFILING
)
9814 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9815 which would have to be restored before the sibcall. */
9816 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9819 /* Register 6 on s390 is available as an argument register but unfortunately
9820 "caller saved". This makes functions needing this register for arguments
9821 not suitable for sibcalls. */
9822 return !s390_call_saved_register_used (exp
);
9825 /* Return the fixed registers used for condition codes. */
9828 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9831 *p2
= INVALID_REGNUM
;
9836 /* This function is used by the call expanders of the machine description.
9837 It emits the call insn itself together with the necessary operations
9838 to adjust the target address and returns the emitted insn.
9839 ADDR_LOCATION is the target address rtx
9840 TLS_CALL the location of the thread-local symbol
9841 RESULT_REG the register where the result of the call should be stored
9842 RETADDR_REG the register where the return address should be stored
9843 If this parameter is NULL_RTX the call is considered
9844 to be a sibling call. */
9847 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9850 bool plt_call
= false;
9856 /* Direct function calls need special treatment. */
9857 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9859 /* When calling a global routine in PIC mode, we must
9860 replace the symbol itself with the PLT stub. */
9861 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9863 if (retaddr_reg
!= NULL_RTX
)
9865 addr_location
= gen_rtx_UNSPEC (Pmode
,
9866 gen_rtvec (1, addr_location
),
9868 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9872 /* For -fpic code the PLT entries might use r12 which is
9873 call-saved. Therefore we cannot do a sibcall when
9874 calling directly using a symbol ref. When reaching
9875 this point we decided (in s390_function_ok_for_sibcall)
9876 to do a sibcall for a function pointer but one of the
9877 optimizers was able to get rid of the function pointer
9878 by propagating the symbol ref into the call. This
9879 optimization is illegal for S/390 so we turn the direct
9880 call into a indirect call again. */
9881 addr_location
= force_reg (Pmode
, addr_location
);
9884 /* Unless we can use the bras(l) insn, force the
9885 routine address into a register. */
9886 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9889 addr_location
= legitimize_pic_address (addr_location
, 0);
9891 addr_location
= force_reg (Pmode
, addr_location
);
9895 /* If it is already an indirect call or the code above moved the
9896 SYMBOL_REF to somewhere else make sure the address can be found in
9898 if (retaddr_reg
== NULL_RTX
9899 && GET_CODE (addr_location
) != SYMBOL_REF
9902 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9903 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9906 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9907 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9909 if (result_reg
!= NULL_RTX
)
9910 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9912 if (retaddr_reg
!= NULL_RTX
)
9914 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9916 if (tls_call
!= NULL_RTX
)
9917 vec
= gen_rtvec (3, call
, clobber
,
9918 gen_rtx_USE (VOIDmode
, tls_call
));
9920 vec
= gen_rtvec (2, call
, clobber
);
9922 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9925 insn
= emit_call_insn (call
);
9927 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9928 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9930 /* s390_function_ok_for_sibcall should
9931 have denied sibcalls in this case. */
9932 gcc_assert (retaddr_reg
!= NULL_RTX
);
9933 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
9938 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9941 s390_conditional_register_usage (void)
9947 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9948 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9950 if (TARGET_CPU_ZARCH
)
9952 fixed_regs
[BASE_REGNUM
] = 0;
9953 call_used_regs
[BASE_REGNUM
] = 0;
9954 fixed_regs
[RETURN_REGNUM
] = 0;
9955 call_used_regs
[RETURN_REGNUM
] = 0;
9959 for (i
= 24; i
< 32; i
++)
9960 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9964 for (i
= 18; i
< 20; i
++)
9965 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9968 if (TARGET_SOFT_FLOAT
)
9970 for (i
= 16; i
< 32; i
++)
9971 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9975 /* Corresponding function to eh_return expander. */
9977 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9979 s390_emit_tpf_eh_return (rtx target
)
9983 if (!s390_tpf_eh_return_symbol
)
9984 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9986 reg
= gen_rtx_REG (Pmode
, 2);
9988 emit_move_insn (reg
, target
);
9989 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9990 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9991 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9993 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9996 /* Rework the prologue/epilogue to avoid saving/restoring
9997 registers unnecessarily. */
10000 s390_optimize_prologue (void)
10002 rtx insn
, new_insn
, next_insn
;
10004 /* Do a final recompute of the frame-related data. */
10006 s390_update_frame_layout ();
10008 /* If all special registers are in fact used, there's nothing we
10009 can do, so no point in walking the insn list. */
10011 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
10012 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
10013 && (TARGET_CPU_ZARCH
10014 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
10015 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
10018 /* Search for prologue/epilogue insns and replace them. */
10020 for (insn
= get_insns (); insn
; insn
= next_insn
)
10022 int first
, last
, off
;
10023 rtx set
, base
, offset
;
10025 next_insn
= NEXT_INSN (insn
);
10027 if (GET_CODE (insn
) != INSN
)
10030 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10031 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
10033 set
= XVECEXP (PATTERN (insn
), 0, 0);
10034 first
= REGNO (SET_SRC (set
));
10035 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10036 offset
= const0_rtx
;
10037 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10038 off
= INTVAL (offset
);
10040 if (GET_CODE (base
) != REG
|| off
< 0)
10042 if (cfun_frame_layout
.first_save_gpr
!= -1
10043 && (cfun_frame_layout
.first_save_gpr
< first
10044 || cfun_frame_layout
.last_save_gpr
> last
))
10046 if (REGNO (base
) != STACK_POINTER_REGNUM
10047 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10049 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10052 if (cfun_frame_layout
.first_save_gpr
!= -1)
10054 new_insn
= save_gprs (base
,
10055 off
+ (cfun_frame_layout
.first_save_gpr
10056 - first
) * UNITS_PER_LONG
,
10057 cfun_frame_layout
.first_save_gpr
,
10058 cfun_frame_layout
.last_save_gpr
);
10059 new_insn
= emit_insn_before (new_insn
, insn
);
10060 INSN_ADDRESSES_NEW (new_insn
, -1);
10063 remove_insn (insn
);
10067 if (cfun_frame_layout
.first_save_gpr
== -1
10068 && GET_CODE (PATTERN (insn
)) == SET
10069 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
10070 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
10071 || (!TARGET_CPU_ZARCH
10072 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
10073 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
10075 set
= PATTERN (insn
);
10076 first
= REGNO (SET_SRC (set
));
10077 offset
= const0_rtx
;
10078 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10079 off
= INTVAL (offset
);
10081 if (GET_CODE (base
) != REG
|| off
< 0)
10083 if (REGNO (base
) != STACK_POINTER_REGNUM
10084 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10087 remove_insn (insn
);
10091 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10092 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
10094 set
= XVECEXP (PATTERN (insn
), 0, 0);
10095 first
= REGNO (SET_DEST (set
));
10096 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10097 offset
= const0_rtx
;
10098 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10099 off
= INTVAL (offset
);
10101 if (GET_CODE (base
) != REG
|| off
< 0)
10103 if (cfun_frame_layout
.first_restore_gpr
!= -1
10104 && (cfun_frame_layout
.first_restore_gpr
< first
10105 || cfun_frame_layout
.last_restore_gpr
> last
))
10107 if (REGNO (base
) != STACK_POINTER_REGNUM
10108 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10110 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10113 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10115 new_insn
= restore_gprs (base
,
10116 off
+ (cfun_frame_layout
.first_restore_gpr
10117 - first
) * UNITS_PER_LONG
,
10118 cfun_frame_layout
.first_restore_gpr
,
10119 cfun_frame_layout
.last_restore_gpr
);
10120 new_insn
= emit_insn_before (new_insn
, insn
);
10121 INSN_ADDRESSES_NEW (new_insn
, -1);
10124 remove_insn (insn
);
10128 if (cfun_frame_layout
.first_restore_gpr
== -1
10129 && GET_CODE (PATTERN (insn
)) == SET
10130 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
10131 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
10132 || (!TARGET_CPU_ZARCH
10133 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
10134 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
10136 set
= PATTERN (insn
);
10137 first
= REGNO (SET_DEST (set
));
10138 offset
= const0_rtx
;
10139 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10140 off
= INTVAL (offset
);
10142 if (GET_CODE (base
) != REG
|| off
< 0)
10144 if (REGNO (base
) != STACK_POINTER_REGNUM
10145 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10148 remove_insn (insn
);
10154 /* On z10 and later the dynamic branch prediction must see the
10155 backward jump within a certain windows. If not it falls back to
10156 the static prediction. This function rearranges the loop backward
10157 branch in a way which makes the static prediction always correct.
10158 The function returns true if it added an instruction. */
10160 s390_fix_long_loop_prediction (rtx insn
)
10162 rtx set
= single_set (insn
);
10163 rtx code_label
, label_ref
, new_label
;
10169 /* This will exclude branch on count and branch on index patterns
10170 since these are correctly statically predicted. */
10172 || SET_DEST (set
) != pc_rtx
10173 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
10176 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
10177 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
10179 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
10181 code_label
= XEXP (label_ref
, 0);
10183 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
10184 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
10185 || (INSN_ADDRESSES (INSN_UID (insn
))
10186 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
10189 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
10190 distance
< PREDICT_DISTANCE
- 6;
10191 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
10192 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
10195 new_label
= gen_label_rtx ();
10196 uncond_jump
= emit_jump_insn_after (
10197 gen_rtx_SET (VOIDmode
, pc_rtx
,
10198 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
10200 emit_label_after (new_label
, uncond_jump
);
10202 tmp
= XEXP (SET_SRC (set
), 1);
10203 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10204 XEXP (SET_SRC (set
), 2) = tmp
;
10205 INSN_CODE (insn
) = -1;
10207 XEXP (label_ref
, 0) = new_label
;
10208 JUMP_LABEL (insn
) = new_label
;
10209 JUMP_LABEL (uncond_jump
) = code_label
;
10214 /* Returns 1 if INSN reads the value of REG for purposes not related
10215 to addressing of memory, and 0 otherwise. */
10217 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10219 return reg_referenced_p (reg
, PATTERN (insn
))
10220 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10223 /* Starting from INSN find_cond_jump looks downwards in the insn
10224 stream for a single jump insn which is the last user of the
10225 condition code set in INSN. */
10227 find_cond_jump (rtx insn
)
10229 for (; insn
; insn
= NEXT_INSN (insn
))
10233 if (LABEL_P (insn
))
10236 if (!JUMP_P (insn
))
10238 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10243 /* This will be triggered by a return. */
10244 if (GET_CODE (PATTERN (insn
)) != SET
)
10247 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10248 ite
= SET_SRC (PATTERN (insn
));
10250 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10253 cc
= XEXP (XEXP (ite
, 0), 0);
10254 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10257 if (find_reg_note (insn
, REG_DEAD
, cc
))
10265 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10266 the semantics does not change. If NULL_RTX is passed as COND the
10267 function tries to find the conditional jump starting with INSN. */
10269 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10273 if (cond
== NULL_RTX
)
10275 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10276 jump
= jump
? single_set (jump
) : NULL_RTX
;
10278 if (jump
== NULL_RTX
)
10281 cond
= XEXP (XEXP (jump
, 1), 0);
10286 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10289 /* On z10, instructions of the compare-and-branch family have the
10290 property to access the register occurring as second operand with
10291 its bits complemented. If such a compare is grouped with a second
10292 instruction that accesses the same register non-complemented, and
10293 if that register's value is delivered via a bypass, then the
10294 pipeline recycles, thereby causing significant performance decline.
10295 This function locates such situations and exchanges the two
10296 operands of the compare. The function return true whenever it
10299 s390_z10_optimize_cmp (rtx insn
)
10301 rtx prev_insn
, next_insn
;
10302 bool insn_added_p
= false;
10303 rtx cond
, *op0
, *op1
;
10305 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10307 /* Handle compare and branch and branch on count
10309 rtx pattern
= single_set (insn
);
10312 || SET_DEST (pattern
) != pc_rtx
10313 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10316 cond
= XEXP (SET_SRC (pattern
), 0);
10317 op0
= &XEXP (cond
, 0);
10318 op1
= &XEXP (cond
, 1);
10320 else if (GET_CODE (PATTERN (insn
)) == SET
)
10324 /* Handle normal compare instructions. */
10325 src
= SET_SRC (PATTERN (insn
));
10326 dest
= SET_DEST (PATTERN (insn
));
10329 || !CC_REGNO_P (REGNO (dest
))
10330 || GET_CODE (src
) != COMPARE
)
10333 /* s390_swap_cmp will try to find the conditional
10334 jump when passing NULL_RTX as condition. */
10336 op0
= &XEXP (src
, 0);
10337 op1
= &XEXP (src
, 1);
10342 if (!REG_P (*op0
) || !REG_P (*op1
))
10345 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10348 /* Swap the COMPARE arguments and its mask if there is a
10349 conflicting access in the previous insn. */
10350 prev_insn
= prev_active_insn (insn
);
10351 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10352 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10353 s390_swap_cmp (cond
, op0
, op1
, insn
);
10355 /* Check if there is a conflict with the next insn. If there
10356 was no conflict with the previous insn, then swap the
10357 COMPARE arguments and its mask. If we already swapped
10358 the operands, or if swapping them would cause a conflict
10359 with the previous insn, issue a NOP after the COMPARE in
10360 order to separate the two instuctions. */
10361 next_insn
= next_active_insn (insn
);
10362 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10363 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10365 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10366 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10368 if (REGNO (*op1
) == 0)
10369 emit_insn_after (gen_nop1 (), insn
);
10371 emit_insn_after (gen_nop (), insn
);
10372 insn_added_p
= true;
10375 s390_swap_cmp (cond
, op0
, op1
, insn
);
10377 return insn_added_p
;
10380 /* Perform machine-dependent processing. */
10385 bool pool_overflow
= false;
10387 /* Make sure all splits have been performed; splits after
10388 machine_dependent_reorg might confuse insn length counts. */
10389 split_all_insns_noflow ();
10391 /* Install the main literal pool and the associated base
10392 register load insns.
10394 In addition, there are two problematic situations we need
10397 - the literal pool might be > 4096 bytes in size, so that
10398 some of its elements cannot be directly accessed
10400 - a branch target might be > 64K away from the branch, so that
10401 it is not possible to use a PC-relative instruction.
10403 To fix those, we split the single literal pool into multiple
10404 pool chunks, reloading the pool base register at various
10405 points throughout the function to ensure it always points to
10406 the pool chunk the following code expects, and / or replace
10407 PC-relative branches by absolute branches.
10409 However, the two problems are interdependent: splitting the
10410 literal pool can move a branch further away from its target,
10411 causing the 64K limit to overflow, and on the other hand,
10412 replacing a PC-relative branch by an absolute branch means
10413 we need to put the branch target address into the literal
10414 pool, possibly causing it to overflow.
10416 So, we loop trying to fix up both problems until we manage
10417 to satisfy both conditions at the same time. Note that the
10418 loop is guaranteed to terminate as every pass of the loop
10419 strictly decreases the total number of PC-relative branches
10420 in the function. (This is not completely true as there
10421 might be branch-over-pool insns introduced by chunkify_start.
10422 Those never need to be split however.) */
10426 struct constant_pool
*pool
= NULL
;
10428 /* Collect the literal pool. */
10429 if (!pool_overflow
)
10431 pool
= s390_mainpool_start ();
10433 pool_overflow
= true;
10436 /* If literal pool overflowed, start to chunkify it. */
10438 pool
= s390_chunkify_start ();
10440 /* Split out-of-range branches. If this has created new
10441 literal pool entries, cancel current chunk list and
10442 recompute it. zSeries machines have large branch
10443 instructions, so we never need to split a branch. */
10444 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10447 s390_chunkify_cancel (pool
);
10449 s390_mainpool_cancel (pool
);
10454 /* If we made it up to here, both conditions are satisfied.
10455 Finish up literal pool related changes. */
10457 s390_chunkify_finish (pool
);
10459 s390_mainpool_finish (pool
);
10461 /* We're done splitting branches. */
10462 cfun
->machine
->split_branches_pending_p
= false;
10466 /* Generate out-of-pool execute target insns. */
10467 if (TARGET_CPU_ZARCH
)
10469 rtx insn
, label
, target
;
10471 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10473 label
= s390_execute_label (insn
);
10477 gcc_assert (label
!= const0_rtx
);
10479 target
= emit_label (XEXP (label
, 0));
10480 INSN_ADDRESSES_NEW (target
, -1);
10482 target
= emit_insn (s390_execute_target (insn
));
10483 INSN_ADDRESSES_NEW (target
, -1);
10487 /* Try to optimize prologue and epilogue further. */
10488 s390_optimize_prologue ();
10490 /* Walk over the insns and do some >=z10 specific changes. */
10491 if (s390_tune
== PROCESSOR_2097_Z10
10492 || s390_tune
== PROCESSOR_2817_Z196
10493 || s390_tune
== PROCESSOR_2827_ZEC12
)
10496 bool insn_added_p
= false;
10498 /* The insn lengths and addresses have to be up to date for the
10499 following manipulations. */
10500 shorten_branches (get_insns ());
10502 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10504 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10508 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10510 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10511 || GET_CODE (PATTERN (insn
)) == SET
)
10512 && s390_tune
== PROCESSOR_2097_Z10
)
10513 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10516 /* Adjust branches if we added new instructions. */
10518 shorten_branches (get_insns ());
10522 /* Return true if INSN is a fp load insn writing register REGNO. */
10524 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10527 enum attr_type flag
= s390_safe_attr_type (insn
);
10529 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10532 set
= single_set (insn
);
10534 if (set
== NULL_RTX
)
10537 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10540 if (REGNO (SET_DEST (set
)) != regno
)
10546 /* This value describes the distance to be avoided between an
10547 aritmetic fp instruction and an fp load writing the same register.
10548 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10549 fine but the exact value has to be avoided. Otherwise the FP
10550 pipeline will throw an exception causing a major penalty. */
10551 #define Z10_EARLYLOAD_DISTANCE 7
10553 /* Rearrange the ready list in order to avoid the situation described
10554 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10555 moved to the very end of the ready list. */
10557 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10559 unsigned int regno
;
10560 int nready
= *nready_p
;
10565 enum attr_type flag
;
10568 /* Skip DISTANCE - 1 active insns. */
10569 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10570 distance
> 0 && insn
!= NULL_RTX
;
10571 distance
--, insn
= prev_active_insn (insn
))
10572 if (CALL_P (insn
) || JUMP_P (insn
))
10575 if (insn
== NULL_RTX
)
10578 set
= single_set (insn
);
10580 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10581 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10584 flag
= s390_safe_attr_type (insn
);
10586 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10589 regno
= REGNO (SET_DEST (set
));
10592 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10599 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10604 /* The s390_sched_state variable tracks the state of the current or
10605 the last instruction group.
10607 0,1,2 number of instructions scheduled in the current group
10608 3 the last group is complete - normal insns
10609 4 the last group was a cracked/expanded insn */
10611 static int s390_sched_state
;
10613 #define S390_OOO_SCHED_STATE_NORMAL 3
10614 #define S390_OOO_SCHED_STATE_CRACKED 4
10616 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
10617 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
10618 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
10619 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
10621 static unsigned int
10622 s390_get_sched_attrmask (rtx insn
)
10624 unsigned int mask
= 0;
10626 if (get_attr_ooo_cracked (insn
))
10627 mask
|= S390_OOO_SCHED_ATTR_MASK_CRACKED
;
10628 if (get_attr_ooo_expanded (insn
))
10629 mask
|= S390_OOO_SCHED_ATTR_MASK_EXPANDED
;
10630 if (get_attr_ooo_endgroup (insn
))
10631 mask
|= S390_OOO_SCHED_ATTR_MASK_ENDGROUP
;
10632 if (get_attr_ooo_groupalone (insn
))
10633 mask
|= S390_OOO_SCHED_ATTR_MASK_GROUPALONE
;
10637 /* Return the scheduling score for INSN. The higher the score the
10638 better. The score is calculated from the OOO scheduling attributes
10639 of INSN and the scheduling state s390_sched_state. */
10641 s390_sched_score (rtx insn
)
10643 unsigned int mask
= s390_get_sched_attrmask (insn
);
10646 switch (s390_sched_state
)
10649 /* Try to put insns into the first slot which would otherwise
10651 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
10652 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
10654 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
10657 /* Prefer not cracked insns while trying to put together a
10659 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
10660 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
10661 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
10663 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) == 0)
10667 /* Prefer not cracked insns while trying to put together a
10669 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
10670 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
10671 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
10673 /* Prefer endgroup insns in the last slot. */
10674 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0)
10677 case S390_OOO_SCHED_STATE_NORMAL
:
10678 /* Prefer not cracked insns if the last was not cracked. */
10679 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
10680 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0)
10682 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
10685 case S390_OOO_SCHED_STATE_CRACKED
:
10686 /* Try to keep cracked insns together to prevent them from
10687 interrupting groups. */
10688 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
10689 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
10696 /* This function is called via hook TARGET_SCHED_REORDER before
10697 issueing one insn from list READY which contains *NREADYP entries.
10698 For target z10 it reorders load instructions to avoid early load
10699 conflicts in the floating point pipeline */
10701 s390_sched_reorder (FILE *file
, int verbose
,
10702 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10704 if (s390_tune
== PROCESSOR_2097_Z10
)
10705 if (reload_completed
&& *nreadyp
> 1)
10706 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10708 if (s390_tune
== PROCESSOR_2827_ZEC12
10709 && reload_completed
10713 int last_index
= *nreadyp
- 1;
10714 int max_index
= -1;
10715 int max_score
= -1;
10718 /* Just move the insn with the highest score to the top (the
10719 end) of the list. A full sort is not needed since a conflict
10720 in the hazard recognition cannot happen. So the top insn in
10721 the ready list will always be taken. */
10722 for (i
= last_index
; i
>= 0; i
--)
10726 if (recog_memoized (ready
[i
]) < 0)
10729 score
= s390_sched_score (ready
[i
]);
10730 if (score
> max_score
)
10737 if (max_index
!= -1)
10739 if (max_index
!= last_index
)
10741 tmp
= ready
[max_index
];
10742 ready
[max_index
] = ready
[last_index
];
10743 ready
[last_index
] = tmp
;
10747 "move insn %d to the top of list\n",
10748 INSN_UID (ready
[last_index
]));
10750 else if (verbose
> 5)
10752 "best insn %d already on top\n",
10753 INSN_UID (ready
[last_index
]));
10758 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
10761 for (i
= last_index
; i
>= 0; i
--)
10763 if (recog_memoized (ready
[i
]) < 0)
10765 fprintf (file
, "insn %d score: %d: ", INSN_UID (ready
[i
]),
10766 s390_sched_score (ready
[i
]));
10767 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
10768 PRINT_OOO_ATTR (ooo_cracked
);
10769 PRINT_OOO_ATTR (ooo_expanded
);
10770 PRINT_OOO_ATTR (ooo_endgroup
);
10771 PRINT_OOO_ATTR (ooo_groupalone
);
10772 #undef PRINT_OOO_ATTR
10773 fprintf (file
, "\n");
10778 return s390_issue_rate ();
10782 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10783 the scheduler has issued INSN. It stores the last issued insn into
10784 last_scheduled_insn in order to make it available for
10785 s390_sched_reorder. */
10787 s390_sched_variable_issue (FILE *file
, int verbose
, rtx insn
, int more
)
10789 last_scheduled_insn
= insn
;
10791 if (s390_tune
== PROCESSOR_2827_ZEC12
10792 && reload_completed
10793 && recog_memoized (insn
) >= 0)
10795 unsigned int mask
= s390_get_sched_attrmask (insn
);
10797 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
10798 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
10799 s390_sched_state
= S390_OOO_SCHED_STATE_CRACKED
;
10800 else if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0
10801 || (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
10802 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
10805 /* Only normal insns are left (mask == 0). */
10806 switch (s390_sched_state
)
10811 case S390_OOO_SCHED_STATE_NORMAL
:
10812 if (s390_sched_state
== S390_OOO_SCHED_STATE_NORMAL
)
10813 s390_sched_state
= 1;
10815 s390_sched_state
++;
10818 case S390_OOO_SCHED_STATE_CRACKED
:
10819 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
10825 fprintf (file
, "insn %d: ", INSN_UID (insn
));
10826 #define PRINT_OOO_ATTR(ATTR) \
10827 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
10828 PRINT_OOO_ATTR (ooo_cracked
);
10829 PRINT_OOO_ATTR (ooo_expanded
);
10830 PRINT_OOO_ATTR (ooo_endgroup
);
10831 PRINT_OOO_ATTR (ooo_groupalone
);
10832 #undef PRINT_OOO_ATTR
10833 fprintf (file
, "\n");
10834 fprintf (file
, "sched state: %d\n", s390_sched_state
);
10838 if (GET_CODE (PATTERN (insn
)) != USE
10839 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10846 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10847 int verbose ATTRIBUTE_UNUSED
,
10848 int max_ready ATTRIBUTE_UNUSED
)
10850 last_scheduled_insn
= NULL_RTX
;
10851 s390_sched_state
= 0;
10854 /* This function checks the whole of insn X for memory references. The
10855 function always returns zero because the framework it is called
10856 from would stop recursively analyzing the insn upon a return value
10857 other than zero. The real result of this function is updating
10858 counter variable MEM_COUNT. */
10860 check_dpu (rtx
*x
, unsigned *mem_count
)
10862 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10867 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10868 a new number struct loop *loop should be unrolled if tuned for cpus with
10869 a built-in stride prefetcher.
10870 The loop is analyzed for memory accesses by calling check_dpu for
10871 each rtx of the loop. Depending on the loop_depth and the amount of
10872 memory accesses a new number <=nunroll is returned to improve the
10873 behaviour of the hardware prefetch unit. */
10875 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10880 unsigned mem_count
= 0;
10882 if (s390_tune
!= PROCESSOR_2097_Z10
10883 && s390_tune
!= PROCESSOR_2817_Z196
10884 && s390_tune
!= PROCESSOR_2827_ZEC12
)
10887 /* Count the number of memory references within the loop body. */
10888 bbs
= get_loop_body (loop
);
10889 for (i
= 0; i
< loop
->num_nodes
; i
++)
10891 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10892 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10893 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10897 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10898 if (mem_count
== 0)
10901 switch (loop_depth(loop
))
10904 return MIN (nunroll
, 28 / mem_count
);
10906 return MIN (nunroll
, 22 / mem_count
);
10908 return MIN (nunroll
, 16 / mem_count
);
10912 /* Initialize GCC target structure. */
10914 #undef TARGET_ASM_ALIGNED_HI_OP
10915 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10916 #undef TARGET_ASM_ALIGNED_DI_OP
10917 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10918 #undef TARGET_ASM_INTEGER
10919 #define TARGET_ASM_INTEGER s390_assemble_integer
10921 #undef TARGET_ASM_OPEN_PAREN
10922 #define TARGET_ASM_OPEN_PAREN ""
10924 #undef TARGET_ASM_CLOSE_PAREN
10925 #define TARGET_ASM_CLOSE_PAREN ""
10927 #undef TARGET_OPTION_OVERRIDE
10928 #define TARGET_OPTION_OVERRIDE s390_option_override
10930 #undef TARGET_ENCODE_SECTION_INFO
10931 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10933 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10934 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10937 #undef TARGET_HAVE_TLS
10938 #define TARGET_HAVE_TLS true
10940 #undef TARGET_CANNOT_FORCE_CONST_MEM
10941 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10943 #undef TARGET_DELEGITIMIZE_ADDRESS
10944 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10946 #undef TARGET_LEGITIMIZE_ADDRESS
10947 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10949 #undef TARGET_RETURN_IN_MEMORY
10950 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10952 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10953 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10955 #undef TARGET_ASM_OUTPUT_MI_THUNK
10956 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10957 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10958 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10960 #undef TARGET_SCHED_ADJUST_PRIORITY
10961 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10962 #undef TARGET_SCHED_ISSUE_RATE
10963 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10964 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10965 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10967 #undef TARGET_SCHED_VARIABLE_ISSUE
10968 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10969 #undef TARGET_SCHED_REORDER
10970 #define TARGET_SCHED_REORDER s390_sched_reorder
10971 #undef TARGET_SCHED_INIT
10972 #define TARGET_SCHED_INIT s390_sched_init
10974 #undef TARGET_CANNOT_COPY_INSN_P
10975 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10976 #undef TARGET_RTX_COSTS
10977 #define TARGET_RTX_COSTS s390_rtx_costs
10978 #undef TARGET_ADDRESS_COST
10979 #define TARGET_ADDRESS_COST s390_address_cost
10980 #undef TARGET_REGISTER_MOVE_COST
10981 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10982 #undef TARGET_MEMORY_MOVE_COST
10983 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10985 #undef TARGET_MACHINE_DEPENDENT_REORG
10986 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10988 #undef TARGET_VALID_POINTER_MODE
10989 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10991 #undef TARGET_BUILD_BUILTIN_VA_LIST
10992 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10993 #undef TARGET_EXPAND_BUILTIN_VA_START
10994 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10995 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10996 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10998 #undef TARGET_PROMOTE_FUNCTION_MODE
10999 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
11000 #undef TARGET_PASS_BY_REFERENCE
11001 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
11003 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11004 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
11005 #undef TARGET_FUNCTION_ARG
11006 #define TARGET_FUNCTION_ARG s390_function_arg
11007 #undef TARGET_FUNCTION_ARG_ADVANCE
11008 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
11009 #undef TARGET_FUNCTION_VALUE
11010 #define TARGET_FUNCTION_VALUE s390_function_value
11011 #undef TARGET_LIBCALL_VALUE
11012 #define TARGET_LIBCALL_VALUE s390_libcall_value
11014 #undef TARGET_FIXED_CONDITION_CODE_REGS
11015 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
11017 #undef TARGET_CC_MODES_COMPATIBLE
11018 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
11020 #undef TARGET_INVALID_WITHIN_DOLOOP
11021 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
11024 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
11025 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
11028 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11029 #undef TARGET_MANGLE_TYPE
11030 #define TARGET_MANGLE_TYPE s390_mangle_type
11033 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11034 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11036 #undef TARGET_PREFERRED_RELOAD_CLASS
11037 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
11039 #undef TARGET_SECONDARY_RELOAD
11040 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
11042 #undef TARGET_LIBGCC_CMP_RETURN_MODE
11043 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
11045 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
11046 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
11048 #undef TARGET_LEGITIMATE_ADDRESS_P
11049 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
11051 #undef TARGET_LEGITIMATE_CONSTANT_P
11052 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
11054 #undef TARGET_CAN_ELIMINATE
11055 #define TARGET_CAN_ELIMINATE s390_can_eliminate
11057 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11058 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
11060 #undef TARGET_LOOP_UNROLL_ADJUST
11061 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
11063 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11064 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
11065 #undef TARGET_TRAMPOLINE_INIT
11066 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
11068 #undef TARGET_UNWIND_WORD_MODE
11069 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
11071 struct gcc_target targetm
= TARGET_INITIALIZER
;
11073 #include "gt-s390.h"