1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
38 #include "hard-reg-set.h"
39 #include "function-abi.h"
41 /* Forward declarations */
42 static void set_of_1 (rtx
, const_rtx
, void *);
43 static bool covers_regno_p (const_rtx
, unsigned int);
44 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
45 static int computed_jump_p_1 (const_rtx
);
46 static void parms_set (rtx
, const_rtx
, void *);
48 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
52 const_rtx
, machine_mode
,
53 unsigned HOST_WIDE_INT
);
54 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
55 const_rtx
, machine_mode
,
57 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
58 const_rtx
, machine_mode
,
61 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
62 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
64 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
65 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
66 SIGN_EXTEND then while narrowing we also have to enforce the
67 representation and sign-extend the value to mode DESTINATION_REP.
69 If the value is already sign-extended to DESTINATION_REP mode we
70 can just switch to DESTINATION mode on it. For each pair of
71 integral modes SOURCE and DESTINATION, when truncating from SOURCE
72 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
73 contains the number of high-order bits in SOURCE that have to be
74 copies of the sign-bit so that we can do this mode-switch to
78 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
80 /* Store X into index I of ARRAY. ARRAY is known to have at least I
81 elements. Return the new base of ARRAY. */
84 typename
T::value_type
*
85 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
87 size_t i
, value_type x
)
89 if (base
== array
.stack
)
96 gcc_checking_assert (i
== LOCAL_ELEMS
);
97 /* A previous iteration might also have moved from the stack to the
98 heap, in which case the heap array will already be big enough. */
99 if (vec_safe_length (array
.heap
) <= i
)
100 vec_safe_grow (array
.heap
, i
+ 1);
101 base
= array
.heap
->address ();
102 memcpy (base
, array
.stack
, sizeof (array
.stack
));
103 base
[LOCAL_ELEMS
] = x
;
106 unsigned int length
= array
.heap
->length ();
109 gcc_checking_assert (base
== array
.heap
->address ());
115 gcc_checking_assert (i
== length
);
116 vec_safe_push (array
.heap
, x
);
117 return array
.heap
->address ();
121 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
122 number of elements added to the worklist. */
124 template <typename T
>
126 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
128 size_t end
, rtx_type x
)
130 enum rtx_code code
= GET_CODE (x
);
131 const char *format
= GET_RTX_FORMAT (code
);
132 size_t orig_end
= end
;
133 if (__builtin_expect (INSN_P (x
), false))
135 /* Put the pattern at the top of the queue, since that's what
136 we're likely to want most. It also allows for the SEQUENCE
138 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
139 if (format
[i
] == 'e')
141 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
142 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
145 base
= add_single_to_queue (array
, base
, end
++, subx
);
149 for (int i
= 0; format
[i
]; ++i
)
150 if (format
[i
] == 'e')
152 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
153 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
156 base
= add_single_to_queue (array
, base
, end
++, subx
);
158 else if (format
[i
] == 'E')
160 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
161 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
162 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
163 for (unsigned int j
= 0; j
< length
; j
++)
164 base
[end
++] = T::get_value (vec
[j
]);
166 for (unsigned int j
= 0; j
< length
; j
++)
167 base
= add_single_to_queue (array
, base
, end
++,
168 T::get_value (vec
[j
]));
169 if (code
== SEQUENCE
&& end
== length
)
170 /* If the subrtxes of the sequence fill the entire array then
171 we know that no other parts of a containing insn are queued.
172 The caller is therefore iterating over the sequence as a
173 PATTERN (...), so we also want the patterns of the
175 for (unsigned int j
= 0; j
< length
; j
++)
177 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
179 base
[j
] = T::get_value (PATTERN (x
));
182 return end
- orig_end
;
185 template <typename T
>
187 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
189 vec_free (array
.heap
);
192 template <typename T
>
193 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
195 template class generic_subrtx_iterator
<const_rtx_accessor
>;
196 template class generic_subrtx_iterator
<rtx_var_accessor
>;
197 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
199 /* Return 1 if the value of X is unstable
200 (would be different at a different point in the program).
201 The frame pointer, arg pointer, etc. are considered stable
202 (within one function) and so is anything marked `unchanging'. */
205 rtx_unstable_p (const_rtx x
)
207 const RTX_CODE code
= GET_CODE (x
);
214 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
223 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
224 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
225 /* The arg pointer varies if it is not a fixed register. */
226 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
228 /* ??? When call-clobbered, the value is stable modulo the restore
229 that must happen after a call. This currently screws up local-alloc
230 into believing that the restore is not needed. */
231 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
236 if (MEM_VOLATILE_P (x
))
245 fmt
= GET_RTX_FORMAT (code
);
246 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
249 if (rtx_unstable_p (XEXP (x
, i
)))
252 else if (fmt
[i
] == 'E')
255 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
256 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
263 /* Return 1 if X has a value that can vary even between two
264 executions of the program. 0 means X can be compared reliably
265 against certain constants or near-constants.
266 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
267 zero, we are slightly more conservative.
268 The frame pointer and the arg pointer are considered constant. */
271 rtx_varies_p (const_rtx x
, bool for_alias
)
284 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
293 /* Note that we have to test for the actual rtx used for the frame
294 and arg pointers and not just the register number in case we have
295 eliminated the frame and/or arg pointer and are using it
297 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
298 /* The arg pointer varies if it is not a fixed register. */
299 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
301 if (x
== pic_offset_table_rtx
302 /* ??? When call-clobbered, the value is stable modulo the restore
303 that must happen after a call. This currently screws up
304 local-alloc into believing that the restore is not needed, so we
305 must return 0 only if we are called from alias analysis. */
306 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
311 /* The operand 0 of a LO_SUM is considered constant
312 (in fact it is related specifically to operand 1)
313 during alias analysis. */
314 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
315 || rtx_varies_p (XEXP (x
, 1), for_alias
);
318 if (MEM_VOLATILE_P (x
))
327 fmt
= GET_RTX_FORMAT (code
);
328 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
331 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
334 else if (fmt
[i
] == 'E')
337 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
338 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
345 /* Compute an approximation for the offset between the register
346 FROM and TO for the current function, as it was at the start
350 get_initial_register_offset (int from
, int to
)
352 static const struct elim_table_t
356 } table
[] = ELIMINABLE_REGS
;
357 poly_int64 offset1
, offset2
;
363 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
364 is completed, but we need to give at least an estimate for the stack
365 pointer based on the frame size. */
366 if (!epilogue_completed
)
368 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
369 #if !STACK_GROWS_DOWNWARD
372 if (to
== STACK_POINTER_REGNUM
)
374 else if (from
== STACK_POINTER_REGNUM
)
380 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
381 if (table
[i
].from
== from
)
383 if (table
[i
].to
== to
)
385 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
389 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
391 if (table
[j
].to
== to
392 && table
[j
].from
== table
[i
].to
)
394 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
396 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
398 return offset1
+ offset2
;
400 if (table
[j
].from
== to
401 && table
[j
].to
== table
[i
].to
)
403 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
405 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
407 return offset1
- offset2
;
411 else if (table
[i
].to
== from
)
413 if (table
[i
].from
== to
)
415 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
419 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
421 if (table
[j
].to
== to
422 && table
[j
].from
== table
[i
].from
)
424 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
426 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
428 return - offset1
+ offset2
;
430 if (table
[j
].from
== to
431 && table
[j
].to
== table
[i
].from
)
433 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
435 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
437 return - offset1
- offset2
;
442 /* If the requested register combination was not found,
443 try a different more simple combination. */
444 if (from
== ARG_POINTER_REGNUM
)
445 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
446 else if (to
== ARG_POINTER_REGNUM
)
447 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
448 else if (from
== HARD_FRAME_POINTER_REGNUM
)
449 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
450 else if (to
== HARD_FRAME_POINTER_REGNUM
)
451 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
456 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
457 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
458 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
459 references on strict alignment machines. */
462 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
463 machine_mode mode
, bool unaligned_mems
)
465 enum rtx_code code
= GET_CODE (x
);
466 gcc_checking_assert (mode
== BLKmode
|| known_size_p (size
));
469 /* The offset must be a multiple of the mode size if we are considering
470 unaligned memory references on strict alignment machines. */
471 if (STRICT_ALIGNMENT
&& unaligned_mems
&& mode
!= BLKmode
)
473 poly_int64 actual_offset
= offset
;
475 #ifdef SPARC_STACK_BOUNDARY_HACK
476 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
477 the real alignment of %sp. However, when it does this, the
478 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
479 if (SPARC_STACK_BOUNDARY_HACK
480 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
481 actual_offset
-= STACK_POINTER_OFFSET
;
484 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
491 if (SYMBOL_REF_WEAK (x
))
493 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
496 poly_int64 decl_size
;
498 if (maybe_lt (offset
, 0))
500 if (!known_size_p (size
))
501 return maybe_ne (offset
, 0);
503 /* If the size of the access or of the symbol is unknown,
505 decl
= SYMBOL_REF_DECL (x
);
507 /* Else check that the access is in bounds. TODO: restructure
508 expr_size/tree_expr_size/int_expr_size and just use the latter. */
511 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
513 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
516 else if (TREE_CODE (decl
) == STRING_CST
)
517 decl_size
= TREE_STRING_LENGTH (decl
);
518 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
519 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
523 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
524 ? maybe_ne (offset
, 0)
525 : !known_subrange_p (offset
, size
, 0, decl_size
));
534 /* Stack references are assumed not to trap, but we need to deal with
535 nonsensical offsets. */
536 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
537 || x
== stack_pointer_rtx
538 /* The arg pointer varies if it is not a fixed register. */
539 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
542 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
544 poly_int64 red_zone_size
= 0;
546 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
547 poly_int64 low_bound
, high_bound
;
549 if (!known_size_p (size
))
552 if (x
== frame_pointer_rtx
)
554 if (FRAME_GROWS_DOWNWARD
)
556 high_bound
= targetm
.starting_frame_offset ();
557 low_bound
= high_bound
- get_frame_size ();
561 low_bound
= targetm
.starting_frame_offset ();
562 high_bound
= low_bound
+ get_frame_size ();
565 else if (x
== hard_frame_pointer_rtx
)
568 = get_initial_register_offset (STACK_POINTER_REGNUM
,
569 HARD_FRAME_POINTER_REGNUM
);
571 = get_initial_register_offset (ARG_POINTER_REGNUM
,
572 HARD_FRAME_POINTER_REGNUM
);
574 #if STACK_GROWS_DOWNWARD
575 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
576 high_bound
= ap_offset
577 + FIRST_PARM_OFFSET (current_function_decl
)
578 #if !ARGS_GROW_DOWNWARD
583 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
584 low_bound
= ap_offset
585 + FIRST_PARM_OFFSET (current_function_decl
)
586 #if ARGS_GROW_DOWNWARD
592 else if (x
== stack_pointer_rtx
)
595 = get_initial_register_offset (ARG_POINTER_REGNUM
,
596 STACK_POINTER_REGNUM
);
598 #if STACK_GROWS_DOWNWARD
599 low_bound
= - red_zone_size
- stack_boundary
;
600 high_bound
= ap_offset
601 + FIRST_PARM_OFFSET (current_function_decl
)
602 #if !ARGS_GROW_DOWNWARD
607 high_bound
= red_zone_size
+ stack_boundary
;
608 low_bound
= ap_offset
609 + FIRST_PARM_OFFSET (current_function_decl
)
610 #if ARGS_GROW_DOWNWARD
618 /* We assume that accesses are safe to at least the
620 Examples are varargs and __builtin_return_address. */
621 #if ARGS_GROW_DOWNWARD
622 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
625 - crtl
->args
.size
- stack_boundary
;
627 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
629 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
630 + crtl
->args
.size
+ stack_boundary
;
634 if (known_ge (offset
, low_bound
)
635 && known_le (offset
, high_bound
- size
))
639 /* All of the virtual frame registers are stack references. */
640 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
641 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
646 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
647 mode
, unaligned_mems
);
650 /* An address is assumed not to trap if:
651 - it is the pic register plus a const unspec without offset. */
652 if (XEXP (x
, 0) == pic_offset_table_rtx
653 && GET_CODE (XEXP (x
, 1)) == CONST
654 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
655 && known_eq (offset
, 0))
658 /* - or it is an address that can't trap plus a constant integer. */
659 if (poly_int_rtx_p (XEXP (x
, 1), &const_x1
)
660 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ const_x1
,
661 size
, mode
, unaligned_mems
))
668 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
669 mode
, unaligned_mems
);
676 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
677 mode
, unaligned_mems
);
683 /* If it isn't one of the case above, it can cause a trap. */
687 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
690 rtx_addr_can_trap_p (const_rtx x
)
692 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
695 /* Return true if X contains a MEM subrtx. */
698 contains_mem_rtx_p (rtx x
)
700 subrtx_iterator::array_type array
;
701 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
708 /* Return true if X is an address that is known to not be zero. */
711 nonzero_address_p (const_rtx x
)
713 const enum rtx_code code
= GET_CODE (x
);
718 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
724 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
725 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
726 || x
== stack_pointer_rtx
727 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
729 /* All of the virtual frame registers are stack references. */
730 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
731 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
736 return nonzero_address_p (XEXP (x
, 0));
739 /* Handle PIC references. */
740 if (XEXP (x
, 0) == pic_offset_table_rtx
741 && CONSTANT_P (XEXP (x
, 1)))
746 /* Similar to the above; allow positive offsets. Further, since
747 auto-inc is only allowed in memories, the register must be a
749 if (CONST_INT_P (XEXP (x
, 1))
750 && INTVAL (XEXP (x
, 1)) > 0)
752 return nonzero_address_p (XEXP (x
, 0));
755 /* Similarly. Further, the offset is always positive. */
762 return nonzero_address_p (XEXP (x
, 0));
765 return nonzero_address_p (XEXP (x
, 1));
771 /* If it isn't one of the case above, might be zero. */
775 /* Return 1 if X refers to a memory location whose address
776 cannot be compared reliably with constant addresses,
777 or if X refers to a BLKmode memory object.
778 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
779 zero, we are slightly more conservative. */
782 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
793 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
795 fmt
= GET_RTX_FORMAT (code
);
796 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
799 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
802 else if (fmt
[i
] == 'E')
805 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
806 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
812 /* Return the CALL in X if there is one. */
815 get_call_rtx_from (const rtx_insn
*insn
)
817 rtx x
= PATTERN (insn
);
818 if (GET_CODE (x
) == PARALLEL
)
819 x
= XVECEXP (x
, 0, 0);
820 if (GET_CODE (x
) == SET
)
822 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
827 /* Get the declaration of the function called by INSN. */
830 get_call_fndecl (const rtx_insn
*insn
)
834 note
= find_reg_note (insn
, REG_CALL_DECL
, NULL_RTX
);
835 if (note
== NULL_RTX
)
838 datum
= XEXP (note
, 0);
839 if (datum
!= NULL_RTX
)
840 return SYMBOL_REF_DECL (datum
);
845 /* Return the value of the integer term in X, if one is apparent;
847 Only obvious integer terms are detected.
848 This is used in cse.c with the `related_value' field. */
851 get_integer_term (const_rtx x
)
853 if (GET_CODE (x
) == CONST
)
856 if (GET_CODE (x
) == MINUS
857 && CONST_INT_P (XEXP (x
, 1)))
858 return - INTVAL (XEXP (x
, 1));
859 if (GET_CODE (x
) == PLUS
860 && CONST_INT_P (XEXP (x
, 1)))
861 return INTVAL (XEXP (x
, 1));
865 /* If X is a constant, return the value sans apparent integer term;
867 Only obvious integer terms are detected. */
870 get_related_value (const_rtx x
)
872 if (GET_CODE (x
) != CONST
)
875 if (GET_CODE (x
) == PLUS
876 && CONST_INT_P (XEXP (x
, 1)))
878 else if (GET_CODE (x
) == MINUS
879 && CONST_INT_P (XEXP (x
, 1)))
884 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
885 to somewhere in the same object or object_block as SYMBOL. */
888 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
892 if (GET_CODE (symbol
) != SYMBOL_REF
)
900 if (CONSTANT_POOL_ADDRESS_P (symbol
)
901 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
904 decl
= SYMBOL_REF_DECL (symbol
);
905 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
909 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
910 && SYMBOL_REF_BLOCK (symbol
)
911 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
912 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
913 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
919 /* Split X into a base and a constant offset, storing them in *BASE_OUT
920 and *OFFSET_OUT respectively. */
923 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
925 if (GET_CODE (x
) == CONST
)
928 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
930 *base_out
= XEXP (x
, 0);
931 *offset_out
= XEXP (x
, 1);
936 *offset_out
= const0_rtx
;
939 /* Express integer value X as some value Y plus a polynomial offset,
940 where Y is either const0_rtx, X or something within X (as opposed
941 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
944 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
946 rtx base
= const0_rtx
;
948 if (GET_CODE (test
) == CONST
)
949 test
= XEXP (test
, 0);
950 if (GET_CODE (test
) == PLUS
)
952 base
= XEXP (test
, 0);
953 test
= XEXP (test
, 1);
955 if (poly_int_rtx_p (test
, offset_out
))
961 /* Return the argument size in REG_ARGS_SIZE note X. */
964 get_args_size (const_rtx x
)
966 gcc_checking_assert (REG_NOTE_KIND (x
) == REG_ARGS_SIZE
);
967 return rtx_to_poly_int64 (XEXP (x
, 0));
970 /* Return the number of places FIND appears within X. If COUNT_DEST is
971 zero, we do not count occurrences inside the destination of a SET. */
974 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
978 const char *format_ptr
;
997 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
999 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
1003 if (MEM_P (find
) && rtx_equal_p (x
, find
))
1008 if (SET_DEST (x
) == find
&& ! count_dest
)
1009 return count_occurrences (SET_SRC (x
), find
, count_dest
);
1016 format_ptr
= GET_RTX_FORMAT (code
);
1019 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
1021 switch (*format_ptr
++)
1024 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
1028 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1029 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1037 /* Return TRUE if OP is a register or subreg of a register that
1038 holds an unsigned quantity. Otherwise, return FALSE. */
1041 unsigned_reg_p (rtx op
)
1045 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1048 if (GET_CODE (op
) == SUBREG
1049 && SUBREG_PROMOTED_SIGN (op
))
1056 /* Nonzero if register REG appears somewhere within IN.
1057 Also works if REG is not a register; in this case it checks
1058 for a subexpression of IN that is Lisp "equal" to REG. */
1061 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1073 if (GET_CODE (in
) == LABEL_REF
)
1074 return reg
== label_ref_label (in
);
1076 code
= GET_CODE (in
);
1080 /* Compare registers by number. */
1082 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1084 /* These codes have no constituent expressions
1092 /* These are kept unique for a given value. */
1099 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1102 fmt
= GET_RTX_FORMAT (code
);
1104 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1109 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1110 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1113 else if (fmt
[i
] == 'e'
1114 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1120 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1121 no CODE_LABEL insn. */
1124 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1129 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1135 /* Nonzero if register REG is used in an insn between
1136 FROM_INSN and TO_INSN (exclusive of those two). */
1139 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1140 const rtx_insn
*to_insn
)
1144 if (from_insn
== to_insn
)
1147 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1148 if (NONDEBUG_INSN_P (insn
)
1149 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1150 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1155 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1156 is entirely replaced by a new value and the only use is as a SET_DEST,
1157 we do not consider it a reference. */
1160 reg_referenced_p (const_rtx x
, const_rtx body
)
1164 switch (GET_CODE (body
))
1167 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1170 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1171 of a REG that occupies all of the REG, the insn references X if
1172 it is mentioned in the destination. */
1173 if (GET_CODE (SET_DEST (body
)) != CC0
1174 && GET_CODE (SET_DEST (body
)) != PC
1175 && !REG_P (SET_DEST (body
))
1176 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1177 && REG_P (SUBREG_REG (SET_DEST (body
)))
1178 && !read_modify_subreg_p (SET_DEST (body
)))
1179 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1184 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1185 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1192 return reg_overlap_mentioned_p (x
, body
);
1195 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1198 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1201 case UNSPEC_VOLATILE
:
1202 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1203 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1208 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1209 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1214 if (MEM_P (XEXP (body
, 0)))
1215 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1220 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1222 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1229 /* Nonzero if register REG is set or clobbered in an insn between
1230 FROM_INSN and TO_INSN (exclusive of those two). */
1233 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1234 const rtx_insn
*to_insn
)
1236 const rtx_insn
*insn
;
1238 if (from_insn
== to_insn
)
1241 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1242 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1247 /* Return true if REG is set or clobbered inside INSN. */
1250 reg_set_p (const_rtx reg
, const_rtx insn
)
1252 /* After delay slot handling, call and branch insns might be in a
1253 sequence. Check all the elements there. */
1254 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1256 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1257 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1263 /* We can be passed an insn or part of one. If we are passed an insn,
1264 check if a side-effect of the insn clobbers REG. */
1266 && (FIND_REG_INC_NOTE (insn
, reg
)
1269 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1270 && (insn_callee_abi (as_a
<const rtx_insn
*> (insn
))
1271 .clobbers_reg_p (GET_MODE (reg
), REGNO (reg
))))
1273 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1276 /* There are no REG_INC notes for SP autoinc. */
1277 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1279 subrtx_var_iterator::array_type array
;
1280 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1285 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1287 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1289 iter
.skip_subrtxes ();
1294 return set_of (reg
, insn
) != NULL_RTX
;
1297 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1298 only if none of them are modified between START and END. Return 1 if
1299 X contains a MEM; this routine does use memory aliasing. */
1302 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1304 const enum rtx_code code
= GET_CODE (x
);
1325 if (modified_between_p (XEXP (x
, 0), start
, end
))
1327 if (MEM_READONLY_P (x
))
1329 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1330 if (memory_modified_in_insn_p (x
, insn
))
1335 return reg_set_between_p (x
, start
, end
);
1341 fmt
= GET_RTX_FORMAT (code
);
1342 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1344 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1347 else if (fmt
[i
] == 'E')
1348 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1349 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1356 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1357 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1358 does use memory aliasing. */
1361 modified_in_p (const_rtx x
, const_rtx insn
)
1363 const enum rtx_code code
= GET_CODE (x
);
1380 if (modified_in_p (XEXP (x
, 0), insn
))
1382 if (MEM_READONLY_P (x
))
1384 if (memory_modified_in_insn_p (x
, insn
))
1389 return reg_set_p (x
, insn
);
1395 fmt
= GET_RTX_FORMAT (code
);
1396 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1398 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1401 else if (fmt
[i
] == 'E')
1402 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1403 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1410 /* Return true if X is a SUBREG and if storing a value to X would
1411 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1412 target, using a SUBREG to store to one half of a DImode REG would
1413 preserve the other half. */
1416 read_modify_subreg_p (const_rtx x
)
1418 if (GET_CODE (x
) != SUBREG
)
1420 poly_uint64 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1421 poly_uint64 osize
= GET_MODE_SIZE (GET_MODE (x
));
1422 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1423 /* The inner and outer modes of a subreg must be ordered, so that we
1424 can tell whether they're paradoxical or partial. */
1425 gcc_checking_assert (ordered_p (isize
, osize
));
1426 return (maybe_gt (isize
, osize
) && maybe_gt (isize
, regsize
));
1429 /* Helper function for set_of. */
1437 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1439 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1440 if (rtx_equal_p (x
, data
->pat
)
1441 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1445 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1446 (either directly or via STRICT_LOW_PART and similar modifiers). */
1448 set_of (const_rtx pat
, const_rtx insn
)
1450 struct set_of_data data
;
1451 data
.found
= NULL_RTX
;
1453 note_pattern_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1457 /* Add all hard register in X to *PSET. */
1459 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1461 subrtx_iterator::array_type array
;
1462 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1464 const_rtx x
= *iter
;
1465 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1466 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1470 /* This function, called through note_stores, collects sets and
1471 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1474 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1476 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1477 if (REG_P (x
) && HARD_REGISTER_P (x
))
1478 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1481 /* Examine INSN, and compute the set of hard registers written by it.
1482 Store it in *PSET. Should only be called after reload.
1484 IMPLICIT is true if we should include registers that are fully-clobbered
1485 by calls. This should be used with caution, since it doesn't include
1486 partially-clobbered registers. */
1488 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1492 CLEAR_HARD_REG_SET (*pset
);
1493 note_stores (insn
, record_hard_reg_sets
, pset
);
1494 if (CALL_P (insn
) && implicit
)
1495 *pset
|= insn_callee_abi (insn
).full_reg_clobbers ();
1496 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1497 if (REG_NOTE_KIND (link
) == REG_INC
)
1498 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1501 /* Like record_hard_reg_sets, but called through note_uses. */
1503 record_hard_reg_uses (rtx
*px
, void *data
)
1505 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1508 /* Given an INSN, return a SET expression if this insn has only a single SET.
1509 It may also have CLOBBERs, USEs, or SET whose output
1510 will not be used, which we ignore. */
1513 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1516 int set_verified
= 1;
1519 if (GET_CODE (pat
) == PARALLEL
)
1521 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1523 rtx sub
= XVECEXP (pat
, 0, i
);
1524 switch (GET_CODE (sub
))
1531 /* We can consider insns having multiple sets, where all
1532 but one are dead as single set insns. In common case
1533 only single set is present in the pattern so we want
1534 to avoid checking for REG_UNUSED notes unless necessary.
1536 When we reach set first time, we just expect this is
1537 the single set we are looking for and only when more
1538 sets are found in the insn, we check them. */
1541 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1542 && !side_effects_p (set
))
1548 set
= sub
, set_verified
= 0;
1549 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1550 || side_effects_p (sub
))
1562 /* Given an INSN, return nonzero if it has more than one SET, else return
1566 multiple_sets (const_rtx insn
)
1571 /* INSN must be an insn. */
1572 if (! INSN_P (insn
))
1575 /* Only a PARALLEL can have multiple SETs. */
1576 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1578 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1579 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1581 /* If we have already found a SET, then return now. */
1589 /* Either zero or one SET. */
1593 /* Return nonzero if the destination of SET equals the source
1594 and there are no side effects. */
1597 set_noop_p (const_rtx set
)
1599 rtx src
= SET_SRC (set
);
1600 rtx dst
= SET_DEST (set
);
1602 if (dst
== pc_rtx
&& src
== pc_rtx
)
1605 if (MEM_P (dst
) && MEM_P (src
))
1606 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1608 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1609 return rtx_equal_p (XEXP (dst
, 0), src
)
1610 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1611 && !side_effects_p (src
);
1613 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1614 dst
= XEXP (dst
, 0);
1616 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1618 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1620 src
= SUBREG_REG (src
);
1621 dst
= SUBREG_REG (dst
);
1624 /* It is a NOOP if destination overlaps with selected src vector
1626 if (GET_CODE (src
) == VEC_SELECT
1627 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1628 && HARD_REGISTER_P (XEXP (src
, 0))
1629 && HARD_REGISTER_P (dst
))
1632 rtx par
= XEXP (src
, 1);
1633 rtx src0
= XEXP (src
, 0);
1634 poly_int64 c0
= rtx_to_poly_int64 (XVECEXP (par
, 0, 0));
1635 poly_int64 offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1637 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1638 if (maybe_ne (rtx_to_poly_int64 (XVECEXP (par
, 0, i
)), c0
+ i
))
1641 REG_CAN_CHANGE_MODE_P (REGNO (dst
), GET_MODE (src0
), GET_MODE (dst
))
1642 && simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1643 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1646 return (REG_P (src
) && REG_P (dst
)
1647 && REGNO (src
) == REGNO (dst
));
1650 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1654 noop_move_p (const rtx_insn
*insn
)
1656 rtx pat
= PATTERN (insn
);
1658 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1661 /* Insns carrying these notes are useful later on. */
1662 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1665 /* Check the code to be executed for COND_EXEC. */
1666 if (GET_CODE (pat
) == COND_EXEC
)
1667 pat
= COND_EXEC_CODE (pat
);
1669 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1672 if (GET_CODE (pat
) == PARALLEL
)
1675 /* If nothing but SETs of registers to themselves,
1676 this insn can also be deleted. */
1677 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1679 rtx tem
= XVECEXP (pat
, 0, i
);
1681 if (GET_CODE (tem
) == USE
|| GET_CODE (tem
) == CLOBBER
)
1684 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1694 /* Return nonzero if register in range [REGNO, ENDREGNO)
1695 appears either explicitly or implicitly in X
1696 other than being stored into.
1698 References contained within the substructure at LOC do not count.
1699 LOC may be zero, meaning don't ignore anything. */
1702 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1706 unsigned int x_regno
;
1711 /* The contents of a REG_NONNEG note is always zero, so we must come here
1712 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1716 code
= GET_CODE (x
);
1721 x_regno
= REGNO (x
);
1723 /* If we modifying the stack, frame, or argument pointer, it will
1724 clobber a virtual register. In fact, we could be more precise,
1725 but it isn't worth it. */
1726 if ((x_regno
== STACK_POINTER_REGNUM
1727 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1728 && x_regno
== ARG_POINTER_REGNUM
)
1729 || x_regno
== FRAME_POINTER_REGNUM
)
1730 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1733 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1736 /* If this is a SUBREG of a hard reg, we can see exactly which
1737 registers are being modified. Otherwise, handle normally. */
1738 if (REG_P (SUBREG_REG (x
))
1739 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1741 unsigned int inner_regno
= subreg_regno (x
);
1742 unsigned int inner_endregno
1743 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1744 ? subreg_nregs (x
) : 1);
1746 return endregno
> inner_regno
&& regno
< inner_endregno
;
1752 if (&SET_DEST (x
) != loc
1753 /* Note setting a SUBREG counts as referring to the REG it is in for
1754 a pseudo but not for hard registers since we can
1755 treat each word individually. */
1756 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1757 && loc
!= &SUBREG_REG (SET_DEST (x
))
1758 && REG_P (SUBREG_REG (SET_DEST (x
)))
1759 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1760 && refers_to_regno_p (regno
, endregno
,
1761 SUBREG_REG (SET_DEST (x
)), loc
))
1762 || (!REG_P (SET_DEST (x
))
1763 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1766 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1775 /* X does not match, so try its subexpressions. */
1777 fmt
= GET_RTX_FORMAT (code
);
1778 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1780 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1788 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1791 else if (fmt
[i
] == 'E')
1794 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1795 if (loc
!= &XVECEXP (x
, i
, j
)
1796 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1803 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1804 we check if any register number in X conflicts with the relevant register
1805 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1806 contains a MEM (we don't bother checking for memory addresses that can't
1807 conflict because we expect this to be a rare case. */
1810 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1812 unsigned int regno
, endregno
;
1814 /* If either argument is a constant, then modifying X cannot
1815 affect IN. Here we look at IN, we can profitably combine
1816 CONSTANT_P (x) with the switch statement below. */
1817 if (CONSTANT_P (in
))
1821 switch (GET_CODE (x
))
1824 case STRICT_LOW_PART
:
1827 /* Overly conservative. */
1832 regno
= REGNO (SUBREG_REG (x
));
1833 if (regno
< FIRST_PSEUDO_REGISTER
)
1834 regno
= subreg_regno (x
);
1835 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1836 ? subreg_nregs (x
) : 1);
1841 endregno
= END_REGNO (x
);
1843 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1853 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1854 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1857 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1860 else if (fmt
[i
] == 'E')
1863 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1864 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1874 return reg_mentioned_p (x
, in
);
1880 /* If any register in here refers to it we return true. */
1881 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1882 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1883 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1889 gcc_assert (CONSTANT_P (x
));
1894 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1895 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1896 ignored by note_stores, but passed to FUN.
1898 FUN receives three arguments:
1899 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1900 2. the SET or CLOBBER rtx that does the store,
1901 3. the pointer DATA provided to note_stores.
1903 If the item being stored in or clobbered is a SUBREG of a hard register,
1904 the SUBREG will be passed. */
1907 note_pattern_stores (const_rtx x
,
1908 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1912 if (GET_CODE (x
) == COND_EXEC
)
1913 x
= COND_EXEC_CODE (x
);
1915 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1917 rtx dest
= SET_DEST (x
);
1919 while ((GET_CODE (dest
) == SUBREG
1920 && (!REG_P (SUBREG_REG (dest
))
1921 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1922 || GET_CODE (dest
) == ZERO_EXTRACT
1923 || GET_CODE (dest
) == STRICT_LOW_PART
)
1924 dest
= XEXP (dest
, 0);
1926 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1927 each of whose first operand is a register. */
1928 if (GET_CODE (dest
) == PARALLEL
)
1930 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1931 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1932 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1935 (*fun
) (dest
, x
, data
);
1938 else if (GET_CODE (x
) == PARALLEL
)
1939 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1940 note_pattern_stores (XVECEXP (x
, 0, i
), fun
, data
);
1943 /* Same, but for an instruction. If the instruction is a call, include
1944 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1947 note_stores (const rtx_insn
*insn
,
1948 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1951 for (rtx link
= CALL_INSN_FUNCTION_USAGE (insn
);
1952 link
; link
= XEXP (link
, 1))
1953 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1954 note_pattern_stores (XEXP (link
, 0), fun
, data
);
1955 note_pattern_stores (PATTERN (insn
), fun
, data
);
1958 /* Like notes_stores, but call FUN for each expression that is being
1959 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1960 FUN for each expression, not any interior subexpressions. FUN receives a
1961 pointer to the expression and the DATA passed to this function.
1963 Note that this is not quite the same test as that done in reg_referenced_p
1964 since that considers something as being referenced if it is being
1965 partially set, while we do not. */
1968 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1973 switch (GET_CODE (body
))
1976 (*fun
) (&COND_EXEC_TEST (body
), data
);
1977 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1981 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1982 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1986 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1987 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1991 (*fun
) (&XEXP (body
, 0), data
);
1995 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1996 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
2000 (*fun
) (&TRAP_CONDITION (body
), data
);
2004 (*fun
) (&XEXP (body
, 0), data
);
2008 case UNSPEC_VOLATILE
:
2009 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2010 (*fun
) (&XVECEXP (body
, 0, i
), data
);
2014 if (MEM_P (XEXP (body
, 0)))
2015 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
2020 rtx dest
= SET_DEST (body
);
2022 /* For sets we replace everything in source plus registers in memory
2023 expression in store and operands of a ZERO_EXTRACT. */
2024 (*fun
) (&SET_SRC (body
), data
);
2026 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2028 (*fun
) (&XEXP (dest
, 1), data
);
2029 (*fun
) (&XEXP (dest
, 2), data
);
2032 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
2033 dest
= XEXP (dest
, 0);
2036 (*fun
) (&XEXP (dest
, 0), data
);
2041 /* All the other possibilities never store. */
2042 (*fun
) (pbody
, data
);
2047 /* Return nonzero if X's old contents don't survive after INSN.
2048 This will be true if X is (cc0) or if X is a register and
2049 X dies in INSN or because INSN entirely sets X.
2051 "Entirely set" means set directly and not through a SUBREG, or
2052 ZERO_EXTRACT, so no trace of the old contents remains.
2053 Likewise, REG_INC does not count.
2055 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2056 but for this use that makes no difference, since regs don't overlap
2057 during their lifetimes. Therefore, this function may be used
2058 at any time after deaths have been computed.
2060 If REG is a hard reg that occupies multiple machine registers, this
2061 function will only return 1 if each of those registers will be replaced
2065 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2067 unsigned int regno
, end_regno
;
2070 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2071 if (GET_CODE (x
) == CC0
)
2074 gcc_assert (REG_P (x
));
2077 end_regno
= END_REGNO (x
);
2078 for (i
= regno
; i
< end_regno
; i
++)
2079 if (! dead_or_set_regno_p (insn
, i
))
2085 /* Return TRUE iff DEST is a register or subreg of a register, is a
2086 complete rather than read-modify-write destination, and contains
2087 register TEST_REGNO. */
2090 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2092 unsigned int regno
, endregno
;
2094 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2095 dest
= SUBREG_REG (dest
);
2100 regno
= REGNO (dest
);
2101 endregno
= END_REGNO (dest
);
2102 return (test_regno
>= regno
&& test_regno
< endregno
);
2105 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2106 any member matches the covers_regno_no_parallel_p criteria. */
2109 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2111 if (GET_CODE (dest
) == PARALLEL
)
2113 /* Some targets place small structures in registers for return
2114 values of functions, and those registers are wrapped in
2115 PARALLELs that we may see as the destination of a SET. */
2118 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2120 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2121 if (inner
!= NULL_RTX
2122 && covers_regno_no_parallel_p (inner
, test_regno
))
2129 return covers_regno_no_parallel_p (dest
, test_regno
);
2132 /* Utility function for dead_or_set_p to check an individual register. */
2135 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2139 /* See if there is a death note for something that includes TEST_REGNO. */
2140 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2144 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2147 pattern
= PATTERN (insn
);
2149 /* If a COND_EXEC is not executed, the value survives. */
2150 if (GET_CODE (pattern
) == COND_EXEC
)
2153 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2154 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2155 else if (GET_CODE (pattern
) == PARALLEL
)
2159 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2161 rtx body
= XVECEXP (pattern
, 0, i
);
2163 if (GET_CODE (body
) == COND_EXEC
)
2164 body
= COND_EXEC_CODE (body
);
2166 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2167 && covers_regno_p (SET_DEST (body
), test_regno
))
2175 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2176 If DATUM is nonzero, look for one whose datum is DATUM. */
2179 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2183 gcc_checking_assert (insn
);
2185 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2186 if (! INSN_P (insn
))
2190 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2191 if (REG_NOTE_KIND (link
) == kind
)
2196 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2197 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2202 /* Return the reg-note of kind KIND in insn INSN which applies to register
2203 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2204 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2205 it might be the case that the note overlaps REGNO. */
2208 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2212 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2213 if (! INSN_P (insn
))
2216 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2217 if (REG_NOTE_KIND (link
) == kind
2218 /* Verify that it is a register, so that scratch and MEM won't cause a
2220 && REG_P (XEXP (link
, 0))
2221 && REGNO (XEXP (link
, 0)) <= regno
2222 && END_REGNO (XEXP (link
, 0)) > regno
)
2227 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2231 find_reg_equal_equiv_note (const_rtx insn
)
2238 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2239 if (REG_NOTE_KIND (link
) == REG_EQUAL
2240 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2242 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2243 insns that have multiple sets. Checking single_set to
2244 make sure of this is not the proper check, as explained
2245 in the comment in set_unique_reg_note.
2247 This should be changed into an assert. */
2248 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2255 /* Check whether INSN is a single_set whose source is known to be
2256 equivalent to a constant. Return that constant if so, otherwise
2260 find_constant_src (const rtx_insn
*insn
)
2264 set
= single_set (insn
);
2267 x
= avoid_constant_pool_reference (SET_SRC (set
));
2272 note
= find_reg_equal_equiv_note (insn
);
2273 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2274 return XEXP (note
, 0);
2279 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2280 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2283 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2285 /* If it's not a CALL_INSN, it can't possibly have a
2286 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2296 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2298 link
= XEXP (link
, 1))
2299 if (GET_CODE (XEXP (link
, 0)) == code
2300 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2305 unsigned int regno
= REGNO (datum
);
2307 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2308 to pseudo registers, so don't bother checking. */
2310 if (regno
< FIRST_PSEUDO_REGISTER
)
2312 unsigned int end_regno
= END_REGNO (datum
);
2315 for (i
= regno
; i
< end_regno
; i
++)
2316 if (find_regno_fusage (insn
, code
, i
))
2324 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2325 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2328 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2332 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2333 to pseudo registers, so don't bother checking. */
2335 if (regno
>= FIRST_PSEUDO_REGISTER
2339 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2343 if (GET_CODE (op
= XEXP (link
, 0)) == code
2344 && REG_P (reg
= XEXP (op
, 0))
2345 && REGNO (reg
) <= regno
2346 && END_REGNO (reg
) > regno
)
2354 /* Return true if KIND is an integer REG_NOTE. */
2357 int_reg_note_p (enum reg_note kind
)
2359 return kind
== REG_BR_PROB
;
2362 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2363 stored as the pointer to the next register note. */
2366 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2370 gcc_checking_assert (!int_reg_note_p (kind
));
2375 case REG_LABEL_TARGET
:
2376 case REG_LABEL_OPERAND
:
2378 /* These types of register notes use an INSN_LIST rather than an
2379 EXPR_LIST, so that copying is done right and dumps look
2381 note
= alloc_INSN_LIST (datum
, list
);
2382 PUT_REG_NOTE_KIND (note
, kind
);
2386 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2393 /* Add register note with kind KIND and datum DATUM to INSN. */
2396 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2398 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2401 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2404 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2406 gcc_checking_assert (int_reg_note_p (kind
));
2407 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2408 datum
, REG_NOTES (insn
));
2411 /* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2414 add_args_size_note (rtx_insn
*insn
, poly_int64 value
)
2416 gcc_checking_assert (!find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
));
2417 add_reg_note (insn
, REG_ARGS_SIZE
, gen_int_mode (value
, Pmode
));
2420 /* Add a register note like NOTE to INSN. */
2423 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2425 if (GET_CODE (note
) == INT_LIST
)
2426 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2428 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2431 /* Duplicate NOTE and return the copy. */
2433 duplicate_reg_note (rtx note
)
2435 reg_note kind
= REG_NOTE_KIND (note
);
2437 if (GET_CODE (note
) == INT_LIST
)
2438 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2439 else if (GET_CODE (note
) == EXPR_LIST
)
2440 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2442 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2445 /* Remove register note NOTE from the REG_NOTES of INSN. */
2448 remove_note (rtx_insn
*insn
, const_rtx note
)
2452 if (note
== NULL_RTX
)
2455 if (REG_NOTES (insn
) == note
)
2456 REG_NOTES (insn
) = XEXP (note
, 1);
2458 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2459 if (XEXP (link
, 1) == note
)
2461 XEXP (link
, 1) = XEXP (note
, 1);
2465 switch (REG_NOTE_KIND (note
))
2469 df_notes_rescan (insn
);
2476 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2477 Return true if any note has been removed. */
2480 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2485 loc
= ®_NOTES (insn
);
2488 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2489 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2491 *loc
= XEXP (*loc
, 1);
2495 loc
= &XEXP (*loc
, 1);
2500 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2503 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2510 /* This loop is a little tricky. We cannot just go down the chain because
2511 it is being modified by some actions in the loop. So we just iterate
2512 over the head. We plan to drain the list anyway. */
2513 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2515 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2516 rtx note
= find_reg_equal_equiv_note (insn
);
2518 /* This assert is generally triggered when someone deletes a REG_EQUAL
2519 or REG_EQUIV note by hacking the list manually rather than calling
2523 remove_note (insn
, note
);
2527 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2528 return 1 if it is found. A simple equality test is used to determine if
2532 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2536 for (x
= listp
; x
; x
= XEXP (x
, 1))
2537 if (node
== XEXP (x
, 0))
2543 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2544 remove that entry from the list if it is found.
2546 A simple equality test is used to determine if NODE matches. */
2549 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2551 rtx_expr_list
*temp
= *listp
;
2552 rtx_expr_list
*prev
= NULL
;
2556 if (node
== temp
->element ())
2558 /* Splice the node out of the list. */
2560 XEXP (prev
, 1) = temp
->next ();
2562 *listp
= temp
->next ();
2568 temp
= temp
->next ();
2572 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2573 remove that entry from the list if it is found.
2575 A simple equality test is used to determine if NODE matches. */
2578 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2580 rtx_insn_list
*temp
= *listp
;
2581 rtx_insn_list
*prev
= NULL
;
2585 if (node
== temp
->insn ())
2587 /* Splice the node out of the list. */
2589 XEXP (prev
, 1) = temp
->next ();
2591 *listp
= temp
->next ();
2597 temp
= temp
->next ();
2601 /* Nonzero if X contains any volatile instructions. These are instructions
2602 which may cause unpredictable machine state instructions, and thus no
2603 instructions or register uses should be moved or combined across them.
2604 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2607 volatile_insn_p (const_rtx x
)
2609 const RTX_CODE code
= GET_CODE (x
);
2627 case UNSPEC_VOLATILE
:
2632 if (MEM_VOLATILE_P (x
))
2639 /* Recursively scan the operands of this expression. */
2642 const char *const fmt
= GET_RTX_FORMAT (code
);
2645 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2649 if (volatile_insn_p (XEXP (x
, i
)))
2652 else if (fmt
[i
] == 'E')
2655 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2656 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2664 /* Nonzero if X contains any volatile memory references
2665 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2668 volatile_refs_p (const_rtx x
)
2670 const RTX_CODE code
= GET_CODE (x
);
2686 case UNSPEC_VOLATILE
:
2692 if (MEM_VOLATILE_P (x
))
2699 /* Recursively scan the operands of this expression. */
2702 const char *const fmt
= GET_RTX_FORMAT (code
);
2705 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2709 if (volatile_refs_p (XEXP (x
, i
)))
2712 else if (fmt
[i
] == 'E')
2715 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2716 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2724 /* Similar to above, except that it also rejects register pre- and post-
2728 side_effects_p (const_rtx x
)
2730 const RTX_CODE code
= GET_CODE (x
);
2747 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2748 when some combination can't be done. If we see one, don't think
2749 that we can simplify the expression. */
2750 return (GET_MODE (x
) != VOIDmode
);
2759 case UNSPEC_VOLATILE
:
2765 if (MEM_VOLATILE_P (x
))
2772 /* Recursively scan the operands of this expression. */
2775 const char *fmt
= GET_RTX_FORMAT (code
);
2778 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2782 if (side_effects_p (XEXP (x
, i
)))
2785 else if (fmt
[i
] == 'E')
2788 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2789 if (side_effects_p (XVECEXP (x
, i
, j
)))
2797 /* Return nonzero if evaluating rtx X might cause a trap.
2798 FLAGS controls how to consider MEMs. A nonzero means the context
2799 of the access may have changed from the original, such that the
2800 address may have become invalid. */
2803 may_trap_p_1 (const_rtx x
, unsigned flags
)
2809 /* We make no distinction currently, but this function is part of
2810 the internal target-hooks ABI so we keep the parameter as
2811 "unsigned flags". */
2812 bool code_changed
= flags
!= 0;
2816 code
= GET_CODE (x
);
2819 /* Handle these cases quickly. */
2831 return targetm
.unspec_may_trap_p (x
, flags
);
2833 case UNSPEC_VOLATILE
:
2839 return MEM_VOLATILE_P (x
);
2841 /* Memory ref can trap unless it's a static var or a stack slot. */
2843 /* Recognize specific pattern of stack checking probes. */
2844 if (flag_stack_check
2845 && MEM_VOLATILE_P (x
)
2846 && XEXP (x
, 0) == stack_pointer_rtx
)
2848 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2849 reference; moving it out of context such as when moving code
2850 when optimizing, might cause its address to become invalid. */
2852 || !MEM_NOTRAP_P (x
))
2854 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
2855 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2856 GET_MODE (x
), code_changed
);
2861 /* Division by a non-constant might trap. */
2866 if (HONOR_SNANS (x
))
2868 if (FLOAT_MODE_P (GET_MODE (x
)))
2869 return flag_trapping_math
;
2870 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2872 if (GET_CODE (XEXP (x
, 1)) == CONST_VECTOR
)
2874 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
2875 unsigned int n_elts
;
2876 rtx op
= XEXP (x
, 1);
2877 if (!GET_MODE_NUNITS (GET_MODE (op
)).is_constant (&n_elts
))
2879 if (!CONST_VECTOR_DUPLICATE_P (op
))
2881 for (unsigned i
= 0; i
< (unsigned int) XVECLEN (op
, 0); i
++)
2882 if (CONST_VECTOR_ENCODED_ELT (op
, i
) == const0_rtx
)
2886 for (unsigned i
= 0; i
< n_elts
; i
++)
2887 if (CONST_VECTOR_ELT (op
, i
) == const0_rtx
)
2893 /* An EXPR_LIST is used to represent a function call. This
2894 certainly may trap. */
2903 /* Some floating point comparisons may trap. */
2904 if (!flag_trapping_math
)
2906 /* ??? There is no machine independent way to check for tests that trap
2907 when COMPARE is used, though many targets do make this distinction.
2908 For instance, sparc uses CCFPE for compares which generate exceptions
2909 and CCFP for compares which do not generate exceptions. */
2912 /* But often the compare has some CC mode, so check operand
2914 if (HONOR_NANS (XEXP (x
, 0))
2915 || HONOR_NANS (XEXP (x
, 1)))
2921 if (HONOR_SNANS (x
))
2923 /* Often comparison is CC mode, so check operand modes. */
2924 if (HONOR_SNANS (XEXP (x
, 0))
2925 || HONOR_SNANS (XEXP (x
, 1)))
2930 /* Conversion of floating point might trap. */
2931 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2942 /* These operations don't trap even with floating point. */
2946 /* Any floating arithmetic may trap. */
2947 if (FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2951 fmt
= GET_RTX_FORMAT (code
);
2952 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2956 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2959 else if (fmt
[i
] == 'E')
2962 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2963 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2970 /* Return nonzero if evaluating rtx X might cause a trap. */
2973 may_trap_p (const_rtx x
)
2975 return may_trap_p_1 (x
, 0);
2978 /* Same as above, but additionally return nonzero if evaluating rtx X might
2979 cause a fault. We define a fault for the purpose of this function as a
2980 erroneous execution condition that cannot be encountered during the normal
2981 execution of a valid program; the typical example is an unaligned memory
2982 access on a strict alignment machine. The compiler guarantees that it
2983 doesn't generate code that will fault from a valid program, but this
2984 guarantee doesn't mean anything for individual instructions. Consider
2985 the following example:
2987 struct S { int d; union { char *cp; int *ip; }; };
2989 int foo(struct S *s)
2997 on a strict alignment machine. In a valid program, foo will never be
2998 invoked on a structure for which d is equal to 1 and the underlying
2999 unique field of the union not aligned on a 4-byte boundary, but the
3000 expression *s->ip might cause a fault if considered individually.
3002 At the RTL level, potentially problematic expressions will almost always
3003 verify may_trap_p; for example, the above dereference can be emitted as
3004 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3005 However, suppose that foo is inlined in a caller that causes s->cp to
3006 point to a local character variable and guarantees that s->d is not set
3007 to 1; foo may have been effectively translated into pseudo-RTL as:
3010 (set (reg:SI) (mem:SI (%fp - 7)))
3012 (set (reg:QI) (mem:QI (%fp - 7)))
3014 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3015 memory reference to a stack slot, but it will certainly cause a fault
3016 on a strict alignment machine. */
3019 may_trap_or_fault_p (const_rtx x
)
3021 return may_trap_p_1 (x
, 1);
3024 /* Replace any occurrence of FROM in X with TO. The function does
3025 not enter into CONST_DOUBLE for the replace.
3027 Note that copying is not done so X must not be shared unless all copies
3030 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3031 those pointer-equal ones. */
3034 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3042 /* Allow this function to make replacements in EXPR_LISTs. */
3049 && REGNO (x
) == REGNO (from
))
3051 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3054 else if (GET_CODE (x
) == SUBREG
)
3056 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3058 if (CONST_INT_P (new_rtx
))
3060 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3061 GET_MODE (SUBREG_REG (x
)),
3066 SUBREG_REG (x
) = new_rtx
;
3070 else if (GET_CODE (x
) == ZERO_EXTEND
)
3072 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3074 if (CONST_INT_P (new_rtx
))
3076 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3077 new_rtx
, GET_MODE (XEXP (x
, 0)));
3081 XEXP (x
, 0) = new_rtx
;
3086 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3087 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3090 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3091 else if (fmt
[i
] == 'E')
3092 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3093 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3094 from
, to
, all_regs
);
3100 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3101 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3104 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3106 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3108 if (JUMP_TABLE_DATA_P (x
))
3111 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3112 int len
= GET_NUM_ELEM (vec
);
3113 for (int i
= 0; i
< len
; ++i
)
3115 rtx ref
= RTVEC_ELT (vec
, i
);
3116 if (XEXP (ref
, 0) == old_label
)
3118 XEXP (ref
, 0) = new_label
;
3119 if (update_label_nuses
)
3121 ++LABEL_NUSES (new_label
);
3122 --LABEL_NUSES (old_label
);
3129 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3130 field. This is not handled by the iterator because it doesn't
3131 handle unprinted ('0') fields. */
3132 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3133 JUMP_LABEL (x
) = new_label
;
3135 subrtx_ptr_iterator::array_type array
;
3136 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3141 if (GET_CODE (x
) == SYMBOL_REF
3142 && CONSTANT_POOL_ADDRESS_P (x
))
3144 rtx c
= get_pool_constant (x
);
3145 if (rtx_referenced_p (old_label
, c
))
3147 /* Create a copy of constant C; replace the label inside
3148 but do not update LABEL_NUSES because uses in constant pool
3150 rtx new_c
= copy_rtx (c
);
3151 replace_label (&new_c
, old_label
, new_label
, false);
3153 /* Add the new constant NEW_C to constant pool and replace
3154 the old reference to constant by new reference. */
3155 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3156 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3160 if ((GET_CODE (x
) == LABEL_REF
3161 || GET_CODE (x
) == INSN_LIST
)
3162 && XEXP (x
, 0) == old_label
)
3164 XEXP (x
, 0) = new_label
;
3165 if (update_label_nuses
)
3167 ++LABEL_NUSES (new_label
);
3168 --LABEL_NUSES (old_label
);
3176 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3177 rtx_insn
*new_label
, bool update_label_nuses
)
3179 rtx insn_as_rtx
= insn
;
3180 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3181 gcc_checking_assert (insn_as_rtx
== insn
);
3184 /* Return true if X is referenced in BODY. */
3187 rtx_referenced_p (const_rtx x
, const_rtx body
)
3189 subrtx_iterator::array_type array
;
3190 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3191 if (const_rtx y
= *iter
)
3193 /* Check if a label_ref Y refers to label X. */
3194 if (GET_CODE (y
) == LABEL_REF
3196 && label_ref_label (y
) == x
)
3199 if (rtx_equal_p (x
, y
))
3202 /* If Y is a reference to pool constant traverse the constant. */
3203 if (GET_CODE (y
) == SYMBOL_REF
3204 && CONSTANT_POOL_ADDRESS_P (y
))
3205 iter
.substitute (get_pool_constant (y
));
3210 /* If INSN is a tablejump return true and store the label (before jump table) to
3211 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3214 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3215 rtx_jump_table_data
**tablep
)
3220 rtx target
= JUMP_LABEL (insn
);
3221 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3224 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3225 rtx_insn
*table
= next_insn (label
);
3226 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3232 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3236 /* For INSN known to satisfy tablejump_p, determine if it actually is a
3237 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3240 tablejump_casesi_pattern (const rtx_insn
*insn
)
3244 if ((tmp
= single_set (insn
)) != NULL
3245 && SET_DEST (tmp
) == pc_rtx
3246 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3247 && GET_CODE (XEXP (SET_SRC (tmp
), 2)) == LABEL_REF
)
3253 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3254 constant that is not in the constant pool and not in the condition
3255 of an IF_THEN_ELSE. */
3258 computed_jump_p_1 (const_rtx x
)
3260 const enum rtx_code code
= GET_CODE (x
);
3277 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3278 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3281 return (computed_jump_p_1 (XEXP (x
, 1))
3282 || computed_jump_p_1 (XEXP (x
, 2)));
3288 fmt
= GET_RTX_FORMAT (code
);
3289 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3292 && computed_jump_p_1 (XEXP (x
, i
)))
3295 else if (fmt
[i
] == 'E')
3296 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3297 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3304 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3306 Tablejumps and casesi insns are not considered indirect jumps;
3307 we can recognize them by a (use (label_ref)). */
3310 computed_jump_p (const rtx_insn
*insn
)
3315 rtx pat
= PATTERN (insn
);
3317 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3318 if (JUMP_LABEL (insn
) != NULL
)
3321 if (GET_CODE (pat
) == PARALLEL
)
3323 int len
= XVECLEN (pat
, 0);
3324 int has_use_labelref
= 0;
3326 for (i
= len
- 1; i
>= 0; i
--)
3327 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3328 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3331 has_use_labelref
= 1;
3335 if (! has_use_labelref
)
3336 for (i
= len
- 1; i
>= 0; i
--)
3337 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3338 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3339 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3342 else if (GET_CODE (pat
) == SET
3343 && SET_DEST (pat
) == pc_rtx
3344 && computed_jump_p_1 (SET_SRC (pat
)))
3352 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3353 the equivalent add insn and pass the result to FN, using DATA as the
3357 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3359 rtx x
= XEXP (mem
, 0);
3360 switch (GET_CODE (x
))
3365 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3366 rtx r1
= XEXP (x
, 0);
3367 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3368 return fn (mem
, x
, r1
, r1
, c
, data
);
3374 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3375 rtx r1
= XEXP (x
, 0);
3376 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3377 return fn (mem
, x
, r1
, r1
, c
, data
);
3383 rtx r1
= XEXP (x
, 0);
3384 rtx add
= XEXP (x
, 1);
3385 return fn (mem
, x
, r1
, add
, NULL
, data
);
3393 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3394 For each such autoinc operation found, call FN, passing it
3395 the innermost enclosing MEM, the operation itself, the RTX modified
3396 by the operation, two RTXs (the second may be NULL) that, once
3397 added, represent the value to be held by the modified RTX
3398 afterwards, and DATA. FN is to return 0 to continue the
3399 traversal or any other value to have it returned to the caller of
3400 for_each_inc_dec. */
3403 for_each_inc_dec (rtx x
,
3404 for_each_inc_dec_fn fn
,
3407 subrtx_var_iterator::array_type array
;
3408 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3413 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3415 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3418 iter
.skip_subrtxes ();
3425 /* Searches X for any reference to REGNO, returning the rtx of the
3426 reference found if any. Otherwise, returns NULL_RTX. */
3429 regno_use_in (unsigned int regno
, rtx x
)
3435 if (REG_P (x
) && REGNO (x
) == regno
)
3438 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3439 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3443 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3446 else if (fmt
[i
] == 'E')
3447 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3448 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3455 /* Return a value indicating whether OP, an operand of a commutative
3456 operation, is preferred as the first or second operand. The more
3457 positive the value, the stronger the preference for being the first
3461 commutative_operand_precedence (rtx op
)
3463 enum rtx_code code
= GET_CODE (op
);
3465 /* Constants always become the second operand. Prefer "nice" constants. */
3466 if (code
== CONST_INT
)
3468 if (code
== CONST_WIDE_INT
)
3470 if (code
== CONST_POLY_INT
)
3472 if (code
== CONST_DOUBLE
)
3474 if (code
== CONST_FIXED
)
3476 op
= avoid_constant_pool_reference (op
);
3477 code
= GET_CODE (op
);
3479 switch (GET_RTX_CLASS (code
))
3482 if (code
== CONST_INT
)
3484 if (code
== CONST_WIDE_INT
)
3486 if (code
== CONST_POLY_INT
)
3488 if (code
== CONST_DOUBLE
)
3490 if (code
== CONST_FIXED
)
3495 /* SUBREGs of objects should come second. */
3496 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3501 /* Complex expressions should be the first, so decrease priority
3502 of objects. Prefer pointer objects over non pointer objects. */
3503 if ((REG_P (op
) && REG_POINTER (op
))
3504 || (MEM_P (op
) && MEM_POINTER (op
)))
3508 case RTX_COMM_ARITH
:
3509 /* Prefer operands that are themselves commutative to be first.
3510 This helps to make things linear. In particular,
3511 (and (and (reg) (reg)) (not (reg))) is canonical. */
3515 /* If only one operand is a binary expression, it will be the first
3516 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3517 is canonical, although it will usually be further simplified. */
3521 /* Then prefer NEG and NOT. */
3522 if (code
== NEG
|| code
== NOT
)
3531 /* Return 1 iff it is necessary to swap operands of commutative operation
3532 in order to canonicalize expression. */
3535 swap_commutative_operands_p (rtx x
, rtx y
)
3537 return (commutative_operand_precedence (x
)
3538 < commutative_operand_precedence (y
));
3541 /* Return 1 if X is an autoincrement side effect and the register is
3542 not the stack pointer. */
3544 auto_inc_p (const_rtx x
)
3546 switch (GET_CODE (x
))
3554 /* There are no REG_INC notes for SP. */
3555 if (XEXP (x
, 0) != stack_pointer_rtx
)
3563 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3565 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3574 code
= GET_CODE (in
);
3575 fmt
= GET_RTX_FORMAT (code
);
3576 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3580 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3583 else if (fmt
[i
] == 'E')
3584 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3585 if (loc
== &XVECEXP (in
, i
, j
)
3586 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3592 /* Reinterpret a subreg as a bit extraction from an integer and return
3593 the position of the least significant bit of the extracted value.
3594 In other words, if the extraction were performed as a shift right
3595 and mask, return the number of bits to shift right.
3597 The outer value of the subreg has OUTER_BYTES bytes and starts at
3598 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3601 subreg_size_lsb (poly_uint64 outer_bytes
,
3602 poly_uint64 inner_bytes
,
3603 poly_uint64 subreg_byte
)
3605 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3607 /* A paradoxical subreg begins at bit position 0. */
3608 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3609 if (maybe_gt (outer_bytes
, inner_bytes
))
3611 gcc_checking_assert (known_eq (subreg_byte
, 0U));
3615 subreg_end
= subreg_byte
+ outer_bytes
;
3616 trailing_bytes
= inner_bytes
- subreg_end
;
3617 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3618 byte_pos
= trailing_bytes
;
3619 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3620 byte_pos
= subreg_byte
;
3623 /* When bytes and words have opposite endianness, we must be able
3624 to split offsets into words and bytes at compile time. */
3625 poly_uint64 leading_word_part
3626 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3627 poly_uint64 trailing_word_part
3628 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3629 /* If the subreg crosses a word boundary ensure that
3630 it also begins and ends on a word boundary. */
3631 gcc_assert (known_le (subreg_end
- leading_word_part
,
3632 (unsigned int) UNITS_PER_WORD
)
3633 || (known_eq (leading_word_part
, subreg_byte
)
3634 && known_eq (trailing_word_part
, trailing_bytes
)));
3635 if (WORDS_BIG_ENDIAN
)
3636 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3638 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3641 return byte_pos
* BITS_PER_UNIT
;
3644 /* Given a subreg X, return the bit offset where the subreg begins
3645 (counting from the least significant bit of the reg). */
3648 subreg_lsb (const_rtx x
)
3650 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3654 /* Return the subreg byte offset for a subreg whose outer value has
3655 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3656 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3657 lsb of the inner value. This is the inverse of the calculation
3658 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3661 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3662 poly_uint64 lsb_shift
)
3664 /* A paradoxical subreg begins at bit position 0. */
3665 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3666 if (maybe_gt (outer_bytes
, inner_bytes
))
3668 gcc_checking_assert (known_eq (lsb_shift
, 0U));
3672 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
3673 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3674 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3676 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3680 /* When bytes and words have opposite endianness, we must be able
3681 to split offsets into words and bytes at compile time. */
3682 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
3684 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
3686 if (WORDS_BIG_ENDIAN
)
3687 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3689 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3693 /* Fill in information about a subreg of a hard register.
3694 xregno - A regno of an inner hard subreg_reg (or what will become one).
3695 xmode - The mode of xregno.
3696 offset - The byte offset.
3697 ymode - The mode of a top level SUBREG (or what may become one).
3698 info - Pointer to structure to fill in.
3700 Rather than considering one particular inner register (and thus one
3701 particular "outer" register) in isolation, this function really uses
3702 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3703 function does not check whether adding INFO->offset to XREGNO gives
3704 a valid hard register; even if INFO->offset + XREGNO is out of range,
3705 there might be another register of the same type that is in range.
3706 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
3707 the new register, since that can depend on things like whether the final
3708 register number is even or odd. Callers that want to check whether
3709 this particular subreg can be replaced by a simple (reg ...) should
3710 use simplify_subreg_regno. */
3713 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3714 poly_uint64 offset
, machine_mode ymode
,
3715 struct subreg_info
*info
)
3717 unsigned int nregs_xmode
, nregs_ymode
;
3719 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3721 poly_uint64 xsize
= GET_MODE_SIZE (xmode
);
3722 poly_uint64 ysize
= GET_MODE_SIZE (ymode
);
3724 bool rknown
= false;
3726 /* If the register representation of a non-scalar mode has holes in it,
3727 we expect the scalar units to be concatenated together, with the holes
3728 distributed evenly among the scalar units. Each scalar unit must occupy
3729 at least one register. */
3730 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3732 /* As a consequence, we must be dealing with a constant number of
3733 scalars, and thus a constant offset and number of units. */
3734 HOST_WIDE_INT coffset
= offset
.to_constant ();
3735 HOST_WIDE_INT cysize
= ysize
.to_constant ();
3736 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3737 unsigned int nunits
= GET_MODE_NUNITS (xmode
).to_constant ();
3738 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
3739 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3740 gcc_assert (nregs_xmode
3742 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3743 gcc_assert (hard_regno_nregs (xregno
, xmode
)
3744 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
3746 /* You can only ask for a SUBREG of a value with holes in the middle
3747 if you don't cross the holes. (Such a SUBREG should be done by
3748 picking a different register class, or doing it in memory if
3749 necessary.) An example of a value with holes is XCmode on 32-bit
3750 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3751 3 for each part, but in memory it's two 128-bit parts.
3752 Padding is assumed to be at the end (not necessarily the 'high part')
3754 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3755 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
3756 != ((coffset
+ cysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3758 info
->representable_p
= false;
3763 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
3765 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
3767 /* Subreg sizes must be ordered, so that we can tell whether they are
3768 partial, paradoxical or complete. */
3769 gcc_checking_assert (ordered_p (xsize
, ysize
));
3771 /* Paradoxical subregs are otherwise valid. */
3772 if (!rknown
&& known_eq (offset
, 0U) && maybe_gt (ysize
, xsize
))
3774 info
->representable_p
= true;
3775 /* If this is a big endian paradoxical subreg, which uses more
3776 actual hard registers than the original register, we must
3777 return a negative offset so that we find the proper highpart
3780 We assume that the ordering of registers within a multi-register
3781 value has a consistent endianness: if bytes and register words
3782 have different endianness, the hard registers that make up a
3783 multi-register value must be at least word-sized. */
3784 if (REG_WORDS_BIG_ENDIAN
)
3785 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3788 info
->nregs
= nregs_ymode
;
3792 /* If registers store different numbers of bits in the different
3793 modes, we cannot generally form this subreg. */
3794 poly_uint64 regsize_xmode
, regsize_ymode
;
3795 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3796 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3797 && multiple_p (xsize
, nregs_xmode
, ®size_xmode
)
3798 && multiple_p (ysize
, nregs_ymode
, ®size_ymode
))
3801 && ((nregs_ymode
> 1 && maybe_gt (regsize_xmode
, regsize_ymode
))
3802 || (nregs_xmode
> 1 && maybe_gt (regsize_ymode
, regsize_xmode
))))
3804 info
->representable_p
= false;
3805 if (!can_div_away_from_zero_p (ysize
, regsize_xmode
, &info
->nregs
)
3806 || !can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3807 /* Checked by validate_subreg. We must know at compile time
3808 which inner registers are being accessed. */
3812 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3813 would go outside of XMODE. */
3814 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
3816 info
->representable_p
= false;
3817 info
->nregs
= nregs_ymode
;
3818 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3819 /* Checked by validate_subreg. We must know at compile time
3820 which inner registers are being accessed. */
3824 /* Quick exit for the simple and common case of extracting whole
3825 subregisters from a multiregister value. */
3826 /* ??? It would be better to integrate this into the code below,
3827 if we can generalize the concept enough and figure out how
3828 odd-sized modes can coexist with the other weird cases we support. */
3829 HOST_WIDE_INT count
;
3831 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3832 && known_eq (regsize_xmode
, regsize_ymode
)
3833 && constant_multiple_p (offset
, regsize_ymode
, &count
))
3835 info
->representable_p
= true;
3836 info
->nregs
= nregs_ymode
;
3837 info
->offset
= count
;
3838 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3843 /* Lowpart subregs are otherwise valid. */
3844 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
3846 info
->representable_p
= true;
3849 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
3852 info
->nregs
= nregs_ymode
;
3857 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3858 values there are in (reg:XMODE XREGNO). We can view the register
3859 as consisting of this number of independent "blocks", where each
3860 block occupies NREGS_YMODE registers and contains exactly one
3861 representable YMODE value. */
3862 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3863 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3865 /* Calculate the number of bytes in each block. This must always
3866 be exact, otherwise we don't know how to verify the constraint.
3867 These conditions may be relaxed but subreg_regno_offset would
3868 need to be redesigned. */
3869 poly_uint64 bytes_per_block
= exact_div (xsize
, num_blocks
);
3871 /* Get the number of the first block that contains the subreg and the byte
3872 offset of the subreg from the start of that block. */
3873 unsigned int block_number
;
3874 poly_uint64 subblock_offset
;
3875 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
3877 /* Checked by validate_subreg. We must know at compile time which
3878 inner registers are being accessed. */
3883 /* Only the lowpart of each block is representable. */
3884 info
->representable_p
3885 = known_eq (subblock_offset
,
3886 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3890 /* We assume that the ordering of registers within a multi-register
3891 value has a consistent endianness: if bytes and register words
3892 have different endianness, the hard registers that make up a
3893 multi-register value must be at least word-sized. */
3894 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3895 /* The block number we calculated above followed memory endianness.
3896 Convert it to register endianness by counting back from the end.
3897 (Note that, because of the assumption above, each block must be
3898 at least word-sized.) */
3899 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3901 info
->offset
= block_number
* nregs_ymode
;
3902 info
->nregs
= nregs_ymode
;
3905 /* This function returns the regno offset of a subreg expression.
3906 xregno - A regno of an inner hard subreg_reg (or what will become one).
3907 xmode - The mode of xregno.
3908 offset - The byte offset.
3909 ymode - The mode of a top level SUBREG (or what may become one).
3910 RETURN - The regno offset which would be used. */
3912 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3913 poly_uint64 offset
, machine_mode ymode
)
3915 struct subreg_info info
;
3916 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3920 /* This function returns true when the offset is representable via
3921 subreg_offset in the given regno.
3922 xregno - A regno of an inner hard subreg_reg (or what will become one).
3923 xmode - The mode of xregno.
3924 offset - The byte offset.
3925 ymode - The mode of a top level SUBREG (or what may become one).
3926 RETURN - Whether the offset is representable. */
3928 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3929 poly_uint64 offset
, machine_mode ymode
)
3931 struct subreg_info info
;
3932 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3933 return info
.representable_p
;
3936 /* Return the number of a YMODE register to which
3938 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3940 can be simplified. Return -1 if the subreg can't be simplified.
3942 XREGNO is a hard register number. */
3945 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3946 poly_uint64 offset
, machine_mode ymode
)
3948 struct subreg_info info
;
3949 unsigned int yregno
;
3951 /* Give the backend a chance to disallow the mode change. */
3952 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3953 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3954 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
))
3957 /* We shouldn't simplify stack-related registers. */
3958 if ((!reload_completed
|| frame_pointer_needed
)
3959 && xregno
== FRAME_POINTER_REGNUM
)
3962 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3963 && xregno
== ARG_POINTER_REGNUM
)
3966 if (xregno
== STACK_POINTER_REGNUM
3967 /* We should convert hard stack register in LRA if it is
3969 && ! lra_in_progress
)
3972 /* Try to get the register offset. */
3973 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3974 if (!info
.representable_p
)
3977 /* Make sure that the offsetted register value is in range. */
3978 yregno
= xregno
+ info
.offset
;
3979 if (!HARD_REGISTER_NUM_P (yregno
))
3982 /* See whether (reg:YMODE YREGNO) is valid.
3984 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3985 This is a kludge to work around how complex FP arguments are passed
3986 on IA-64 and should be fixed. See PR target/49226. */
3987 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
3988 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
3991 return (int) yregno
;
3994 /* Return the final regno that a subreg expression refers to. */
3996 subreg_regno (const_rtx x
)
3999 rtx subreg
= SUBREG_REG (x
);
4000 int regno
= REGNO (subreg
);
4002 ret
= regno
+ subreg_regno_offset (regno
,
4010 /* Return the number of registers that a subreg expression refers
4013 subreg_nregs (const_rtx x
)
4015 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
4018 /* Return the number of registers that a subreg REG with REGNO
4019 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
4020 changed so that the regno can be passed in. */
4023 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
4025 struct subreg_info info
;
4026 rtx subreg
= SUBREG_REG (x
);
4028 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
4033 struct parms_set_data
4039 /* Helper function for noticing stores to parameter registers. */
4041 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
4043 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
4044 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
4045 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4047 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4052 /* Look backward for first parameter to be loaded.
4053 Note that loads of all parameters will not necessarily be
4054 found if CSE has eliminated some of them (e.g., an argument
4055 to the outer function is passed down as a parameter).
4056 Do not skip BOUNDARY. */
4058 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4060 struct parms_set_data parm
;
4062 rtx_insn
*before
, *first_set
;
4064 /* Since different machines initialize their parameter registers
4065 in different orders, assume nothing. Collect the set of all
4066 parameter registers. */
4067 CLEAR_HARD_REG_SET (parm
.regs
);
4069 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4070 if (GET_CODE (XEXP (p
, 0)) == USE
4071 && REG_P (XEXP (XEXP (p
, 0), 0))
4072 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4074 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4076 /* We only care about registers which can hold function
4078 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4081 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4085 first_set
= call_insn
;
4087 /* Search backward for the first set of a register in this set. */
4088 while (parm
.nregs
&& before
!= boundary
)
4090 before
= PREV_INSN (before
);
4092 /* It is possible that some loads got CSEed from one call to
4093 another. Stop in that case. */
4094 if (CALL_P (before
))
4097 /* Our caller needs either ensure that we will find all sets
4098 (in case code has not been optimized yet), or take care
4099 for possible labels in a way by setting boundary to preceding
4101 if (LABEL_P (before
))
4103 gcc_assert (before
== boundary
);
4107 if (INSN_P (before
))
4109 int nregs_old
= parm
.nregs
;
4110 note_stores (before
, parms_set
, &parm
);
4111 /* If we found something that did not set a parameter reg,
4112 we're done. Do not keep going, as that might result
4113 in hoisting an insn before the setting of a pseudo
4114 that is used by the hoisted insn. */
4115 if (nregs_old
!= parm
.nregs
)
4124 /* Return true if we should avoid inserting code between INSN and preceding
4125 call instruction. */
4128 keep_with_call_p (const rtx_insn
*insn
)
4132 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4134 if (REG_P (SET_DEST (set
))
4135 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4136 && fixed_regs
[REGNO (SET_DEST (set
))]
4137 && general_operand (SET_SRC (set
), VOIDmode
))
4139 if (REG_P (SET_SRC (set
))
4140 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4141 && REG_P (SET_DEST (set
))
4142 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4144 /* There may be a stack pop just after the call and before the store
4145 of the return register. Search for the actual store when deciding
4146 if we can break or not. */
4147 if (SET_DEST (set
) == stack_pointer_rtx
)
4149 /* This CONST_CAST is okay because next_nonnote_insn just
4150 returns its argument and we assign it to a const_rtx
4153 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4154 if (i2
&& keep_with_call_p (i2
))
4161 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4162 to non-complex jumps. That is, direct unconditional, conditional,
4163 and tablejumps, but not computed jumps or returns. It also does
4164 not apply to the fallthru case of a conditional jump. */
4167 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4169 rtx tmp
= JUMP_LABEL (jump_insn
);
4170 rtx_jump_table_data
*table
;
4175 if (tablejump_p (jump_insn
, NULL
, &table
))
4177 rtvec vec
= table
->get_labels ();
4178 int i
, veclen
= GET_NUM_ELEM (vec
);
4180 for (i
= 0; i
< veclen
; ++i
)
4181 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4185 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4192 /* Return an estimate of the cost of computing rtx X.
4193 One use is in cse, to decide which expression to keep in the hash table.
4194 Another is in rtl generation, to pick the cheapest way to multiply.
4195 Other uses like the latter are expected in the future.
4197 X appears as operand OPNO in an expression with code OUTER_CODE.
4198 SPEED specifies whether costs optimized for speed or size should
4202 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4203 int opno
, bool speed
)
4214 if (GET_MODE (x
) != VOIDmode
)
4215 mode
= GET_MODE (x
);
4217 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4218 many insns, taking N times as long. */
4219 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4223 /* Compute the default costs of certain things.
4224 Note that targetm.rtx_costs can override the defaults. */
4226 code
= GET_CODE (x
);
4230 /* Multiplication has time-complexity O(N*N), where N is the
4231 number of units (translated from digits) when using
4232 schoolbook long multiplication. */
4233 total
= factor
* factor
* COSTS_N_INSNS (5);
4239 /* Similarly, complexity for schoolbook long division. */
4240 total
= factor
* factor
* COSTS_N_INSNS (7);
4243 /* Used in combine.c as a marker. */
4247 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4248 the mode for the factor. */
4249 mode
= GET_MODE (SET_DEST (x
));
4250 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4255 total
= factor
* COSTS_N_INSNS (1);
4265 /* If we can't tie these modes, make this expensive. The larger
4266 the mode, the more expensive it is. */
4267 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4268 return COSTS_N_INSNS (2 + factor
);
4272 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4279 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4284 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4285 which is already in total. */
4287 fmt
= GET_RTX_FORMAT (code
);
4288 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4290 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4291 else if (fmt
[i
] == 'E')
4292 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4293 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4298 /* Fill in the structure C with information about both speed and size rtx
4299 costs for X, which is operand OPNO in an expression with code OUTER. */
4302 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4303 struct full_rtx_costs
*c
)
4305 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4306 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4310 /* Return cost of address expression X.
4311 Expect that X is properly formed address reference.
4313 SPEED parameter specify whether costs optimized for speed or size should
4317 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4319 /* We may be asked for cost of various unusual addresses, such as operands
4320 of push instruction. It is not worthwhile to complicate writing
4321 of the target hook by such cases. */
4323 if (!memory_address_addr_space_p (mode
, x
, as
))
4326 return targetm
.address_cost (x
, mode
, as
, speed
);
4329 /* If the target doesn't override, compute the cost as with arithmetic. */
4332 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4334 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4338 unsigned HOST_WIDE_INT
4339 nonzero_bits (const_rtx x
, machine_mode mode
)
4341 if (mode
== VOIDmode
)
4342 mode
= GET_MODE (x
);
4343 scalar_int_mode int_mode
;
4344 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4345 return GET_MODE_MASK (mode
);
4346 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4350 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4352 if (mode
== VOIDmode
)
4353 mode
= GET_MODE (x
);
4354 scalar_int_mode int_mode
;
4355 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4357 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4360 /* Return true if nonzero_bits1 might recurse into both operands
4364 nonzero_bits_binary_arith_p (const_rtx x
)
4366 if (!ARITHMETIC_P (x
))
4368 switch (GET_CODE (x
))
4390 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4391 It avoids exponential behavior in nonzero_bits1 when X has
4392 identical subexpressions on the first or the second level. */
4394 static unsigned HOST_WIDE_INT
4395 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4396 machine_mode known_mode
,
4397 unsigned HOST_WIDE_INT known_ret
)
4399 if (x
== known_x
&& mode
== known_mode
)
4402 /* Try to find identical subexpressions. If found call
4403 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4404 precomputed value for the subexpression as KNOWN_RET. */
4406 if (nonzero_bits_binary_arith_p (x
))
4408 rtx x0
= XEXP (x
, 0);
4409 rtx x1
= XEXP (x
, 1);
4411 /* Check the first level. */
4413 return nonzero_bits1 (x
, mode
, x0
, mode
,
4414 cached_nonzero_bits (x0
, mode
, known_x
,
4415 known_mode
, known_ret
));
4417 /* Check the second level. */
4418 if (nonzero_bits_binary_arith_p (x0
)
4419 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4420 return nonzero_bits1 (x
, mode
, x1
, mode
,
4421 cached_nonzero_bits (x1
, mode
, known_x
,
4422 known_mode
, known_ret
));
4424 if (nonzero_bits_binary_arith_p (x1
)
4425 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4426 return nonzero_bits1 (x
, mode
, x0
, mode
,
4427 cached_nonzero_bits (x0
, mode
, known_x
,
4428 known_mode
, known_ret
));
4431 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4434 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4435 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4436 is less useful. We can't allow both, because that results in exponential
4437 run time recursion. There is a nullstone testcase that triggered
4438 this. This macro avoids accidental uses of num_sign_bit_copies. */
4439 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4441 /* Given an expression, X, compute which bits in X can be nonzero.
4442 We don't care about bits outside of those defined in MODE.
4444 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4445 an arithmetic operation, we can do better. */
4447 static unsigned HOST_WIDE_INT
4448 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4449 machine_mode known_mode
,
4450 unsigned HOST_WIDE_INT known_ret
)
4452 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4453 unsigned HOST_WIDE_INT inner_nz
;
4454 enum rtx_code code
= GET_CODE (x
);
4455 machine_mode inner_mode
;
4456 unsigned int inner_width
;
4457 scalar_int_mode xmode
;
4459 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4461 if (CONST_INT_P (x
))
4463 if (SHORT_IMMEDIATES_SIGN_EXTEND
4465 && mode_width
< BITS_PER_WORD
4466 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4467 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4472 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4474 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4476 /* If X is wider than MODE, use its mode instead. */
4477 if (xmode_width
> mode_width
)
4480 nonzero
= GET_MODE_MASK (mode
);
4481 mode_width
= xmode_width
;
4484 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4485 /* Our only callers in this case look for single bit values. So
4486 just return the mode mask. Those tests will then be false. */
4489 /* If MODE is wider than X, but both are a single word for both the host
4490 and target machines, we can compute this from which bits of the object
4491 might be nonzero in its own mode, taking into account the fact that, on
4492 CISC machines, accessing an object in a wider mode generally causes the
4493 high-order bits to become undefined, so they are not known to be zero.
4494 We extend this reasoning to RISC machines for operations that might not
4495 operate on the full registers. */
4496 if (mode_width
> xmode_width
4497 && xmode_width
<= BITS_PER_WORD
4498 && xmode_width
<= HOST_BITS_PER_WIDE_INT
4499 && !(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
4501 nonzero
&= cached_nonzero_bits (x
, xmode
,
4502 known_x
, known_mode
, known_ret
);
4503 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4507 /* Please keep nonzero_bits_binary_arith_p above in sync with
4508 the code in the switch below. */
4512 #if defined(POINTERS_EXTEND_UNSIGNED)
4513 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4514 all the bits above ptr_mode are known to be zero. */
4515 /* As we do not know which address space the pointer is referring to,
4516 we can do this only if the target does not support different pointer
4517 or address modes depending on the address space. */
4518 if (target_default_pointer_address_modes_p ()
4519 && POINTERS_EXTEND_UNSIGNED
4522 && !targetm
.have_ptr_extend ())
4523 nonzero
&= GET_MODE_MASK (ptr_mode
);
4526 /* Include declared information about alignment of pointers. */
4527 /* ??? We don't properly preserve REG_POINTER changes across
4528 pointer-to-integer casts, so we can't trust it except for
4529 things that we know must be pointers. See execute/960116-1.c. */
4530 if ((x
== stack_pointer_rtx
4531 || x
== frame_pointer_rtx
4532 || x
== arg_pointer_rtx
)
4533 && REGNO_POINTER_ALIGN (REGNO (x
)))
4535 unsigned HOST_WIDE_INT alignment
4536 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4538 #ifdef PUSH_ROUNDING
4539 /* If PUSH_ROUNDING is defined, it is possible for the
4540 stack to be momentarily aligned only to that amount,
4541 so we pick the least alignment. */
4542 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4544 poly_uint64 rounded_1
= PUSH_ROUNDING (poly_int64 (1));
4545 alignment
= MIN (known_alignment (rounded_1
), alignment
);
4549 nonzero
&= ~(alignment
- 1);
4553 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4554 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4558 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4559 known_mode
, known_ret
);
4561 return nonzero_for_hook
;
4565 /* In many, if not most, RISC machines, reading a byte from memory
4566 zeros the rest of the register. Noticing that fact saves a lot
4567 of extra zero-extends. */
4568 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4569 nonzero
&= GET_MODE_MASK (xmode
);
4573 case UNEQ
: case LTGT
:
4574 case GT
: case GTU
: case UNGT
:
4575 case LT
: case LTU
: case UNLT
:
4576 case GE
: case GEU
: case UNGE
:
4577 case LE
: case LEU
: case UNLE
:
4578 case UNORDERED
: case ORDERED
:
4579 /* If this produces an integer result, we know which bits are set.
4580 Code here used to clear bits outside the mode of X, but that is
4582 /* Mind that MODE is the mode the caller wants to look at this
4583 operation in, and not the actual operation mode. We can wind
4584 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4585 that describes the results of a vector compare. */
4586 if (GET_MODE_CLASS (xmode
) == MODE_INT
4587 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4588 nonzero
= STORE_FLAG_VALUE
;
4593 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4594 and num_sign_bit_copies. */
4595 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4599 if (xmode_width
< mode_width
)
4600 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4605 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4606 and num_sign_bit_copies. */
4607 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4613 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4614 known_x
, known_mode
, known_ret
)
4615 & GET_MODE_MASK (mode
));
4619 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4620 known_x
, known_mode
, known_ret
);
4621 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4622 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4626 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4627 Otherwise, show all the bits in the outer mode but not the inner
4629 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4630 known_x
, known_mode
, known_ret
);
4631 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4633 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4634 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4635 inner_nz
|= (GET_MODE_MASK (mode
)
4636 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4639 nonzero
&= inner_nz
;
4643 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4644 known_x
, known_mode
, known_ret
)
4645 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4646 known_x
, known_mode
, known_ret
);
4650 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4652 unsigned HOST_WIDE_INT nonzero0
4653 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4654 known_x
, known_mode
, known_ret
);
4656 /* Don't call nonzero_bits for the second time if it cannot change
4658 if ((nonzero
& nonzero0
) != nonzero
)
4660 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4661 known_x
, known_mode
, known_ret
);
4665 case PLUS
: case MINUS
:
4667 case DIV
: case UDIV
:
4668 case MOD
: case UMOD
:
4669 /* We can apply the rules of arithmetic to compute the number of
4670 high- and low-order zero bits of these operations. We start by
4671 computing the width (position of the highest-order nonzero bit)
4672 and the number of low-order zero bits for each value. */
4674 unsigned HOST_WIDE_INT nz0
4675 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4676 known_x
, known_mode
, known_ret
);
4677 unsigned HOST_WIDE_INT nz1
4678 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4679 known_x
, known_mode
, known_ret
);
4680 int sign_index
= xmode_width
- 1;
4681 int width0
= floor_log2 (nz0
) + 1;
4682 int width1
= floor_log2 (nz1
) + 1;
4683 int low0
= ctz_or_zero (nz0
);
4684 int low1
= ctz_or_zero (nz1
);
4685 unsigned HOST_WIDE_INT op0_maybe_minusp
4686 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4687 unsigned HOST_WIDE_INT op1_maybe_minusp
4688 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4689 unsigned int result_width
= mode_width
;
4695 result_width
= MAX (width0
, width1
) + 1;
4696 result_low
= MIN (low0
, low1
);
4699 result_low
= MIN (low0
, low1
);
4702 result_width
= width0
+ width1
;
4703 result_low
= low0
+ low1
;
4708 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4709 result_width
= width0
;
4714 result_width
= width0
;
4719 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4720 result_width
= MIN (width0
, width1
);
4721 result_low
= MIN (low0
, low1
);
4726 result_width
= MIN (width0
, width1
);
4727 result_low
= MIN (low0
, low1
);
4733 if (result_width
< mode_width
)
4734 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4737 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4742 if (CONST_INT_P (XEXP (x
, 1))
4743 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4744 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4748 /* If this is a SUBREG formed for a promoted variable that has
4749 been zero-extended, we know that at least the high-order bits
4750 are zero, though others might be too. */
4751 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4752 nonzero
= GET_MODE_MASK (xmode
)
4753 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
4754 known_x
, known_mode
, known_ret
);
4756 /* If the inner mode is a single word for both the host and target
4757 machines, we can compute this from which bits of the inner
4758 object might be nonzero. */
4759 inner_mode
= GET_MODE (SUBREG_REG (x
));
4760 if (GET_MODE_PRECISION (inner_mode
).is_constant (&inner_width
)
4761 && inner_width
<= BITS_PER_WORD
4762 && inner_width
<= HOST_BITS_PER_WIDE_INT
)
4764 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4765 known_x
, known_mode
, known_ret
);
4767 /* On a typical CISC machine, accessing an object in a wider mode
4768 causes the high-order bits to become undefined. So they are
4769 not known to be zero.
4771 On a typical RISC machine, we only have to worry about the way
4772 loads are extended. Otherwise, if we get a reload for the inner
4773 part, it may be loaded from the stack, and then we may lose all
4774 the zero bits that existed before the store to the stack. */
4776 if ((!WORD_REGISTER_OPERATIONS
4777 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4778 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4779 : extend_op
!= ZERO_EXTEND
)
4780 || !MEM_P (SUBREG_REG (x
)))
4781 && xmode_width
> inner_width
)
4783 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4792 /* The nonzero bits are in two classes: any bits within MODE
4793 that aren't in xmode are always significant. The rest of the
4794 nonzero bits are those that are significant in the operand of
4795 the shift when shifted the appropriate number of bits. This
4796 shows that high-order bits are cleared by the right shift and
4797 low-order bits by left shifts. */
4798 if (CONST_INT_P (XEXP (x
, 1))
4799 && INTVAL (XEXP (x
, 1)) >= 0
4800 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4801 && INTVAL (XEXP (x
, 1)) < xmode_width
)
4803 int count
= INTVAL (XEXP (x
, 1));
4804 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
4805 unsigned HOST_WIDE_INT op_nonzero
4806 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4807 known_x
, known_mode
, known_ret
);
4808 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4809 unsigned HOST_WIDE_INT outer
= 0;
4811 if (mode_width
> xmode_width
)
4812 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4827 /* If the sign bit may have been nonzero before the shift, we
4828 need to mark all the places it could have been copied to
4829 by the shift as possibly nonzero. */
4830 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
4831 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
4832 << (xmode_width
- count
));
4836 inner
= (inner
<< (count
% xmode_width
)
4837 | (inner
>> (xmode_width
- (count
% xmode_width
))))
4842 inner
= (inner
>> (count
% xmode_width
)
4843 | (inner
<< (xmode_width
- (count
% xmode_width
))))
4851 nonzero
&= (outer
| inner
);
4857 /* This is at most the number of bits in the mode. */
4858 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4862 /* If CLZ has a known value at zero, then the nonzero bits are
4863 that value, plus the number of bits in the mode minus one. */
4864 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4866 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4872 /* If CTZ has a known value at zero, then the nonzero bits are
4873 that value, plus the number of bits in the mode minus one. */
4874 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4876 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4882 /* This is at most the number of bits in the mode minus 1. */
4883 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4892 unsigned HOST_WIDE_INT nonzero_true
4893 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4894 known_x
, known_mode
, known_ret
);
4896 /* Don't call nonzero_bits for the second time if it cannot change
4898 if ((nonzero
& nonzero_true
) != nonzero
)
4899 nonzero
&= nonzero_true
4900 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4901 known_x
, known_mode
, known_ret
);
4912 /* See the macro definition above. */
4913 #undef cached_num_sign_bit_copies
4916 /* Return true if num_sign_bit_copies1 might recurse into both operands
4920 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4922 if (!ARITHMETIC_P (x
))
4924 switch (GET_CODE (x
))
4942 /* The function cached_num_sign_bit_copies is a wrapper around
4943 num_sign_bit_copies1. It avoids exponential behavior in
4944 num_sign_bit_copies1 when X has identical subexpressions on the
4945 first or the second level. */
4948 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
4949 const_rtx known_x
, machine_mode known_mode
,
4950 unsigned int known_ret
)
4952 if (x
== known_x
&& mode
== known_mode
)
4955 /* Try to find identical subexpressions. If found call
4956 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4957 the precomputed value for the subexpression as KNOWN_RET. */
4959 if (num_sign_bit_copies_binary_arith_p (x
))
4961 rtx x0
= XEXP (x
, 0);
4962 rtx x1
= XEXP (x
, 1);
4964 /* Check the first level. */
4967 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4968 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4972 /* Check the second level. */
4973 if (num_sign_bit_copies_binary_arith_p (x0
)
4974 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4976 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4977 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4981 if (num_sign_bit_copies_binary_arith_p (x1
)
4982 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4984 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4985 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4990 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4993 /* Return the number of bits at the high-order end of X that are known to
4994 be equal to the sign bit. X will be used in mode MODE. The returned
4995 value will always be between 1 and the number of bits in MODE. */
4998 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4999 machine_mode known_mode
,
5000 unsigned int known_ret
)
5002 enum rtx_code code
= GET_CODE (x
);
5003 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
5004 int num0
, num1
, result
;
5005 unsigned HOST_WIDE_INT nonzero
;
5007 if (CONST_INT_P (x
))
5009 /* If the constant is negative, take its 1's complement and remask.
5010 Then see how many zero bits we have. */
5011 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
5012 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5013 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5014 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5016 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5019 scalar_int_mode xmode
, inner_mode
;
5020 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
5023 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
5025 /* For a smaller mode, just ignore the high bits. */
5026 if (bitwidth
< xmode_width
)
5028 num0
= cached_num_sign_bit_copies (x
, xmode
,
5029 known_x
, known_mode
, known_ret
);
5030 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
5033 if (bitwidth
> xmode_width
)
5035 /* If this machine does not do all register operations on the entire
5036 register and MODE is wider than the mode of X, we can say nothing
5037 at all about the high-order bits. We extend this reasoning to RISC
5038 machines for operations that might not operate on full registers. */
5039 if (!(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
5042 /* Likewise on machines that do, if the mode of the object is smaller
5043 than a word and loads of that size don't sign extend, we can say
5044 nothing about the high order bits. */
5045 if (xmode_width
< BITS_PER_WORD
5046 && load_extend_op (xmode
) != SIGN_EXTEND
)
5050 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5051 the code in the switch below. */
5056 #if defined(POINTERS_EXTEND_UNSIGNED)
5057 /* If pointers extend signed and this is a pointer in Pmode, say that
5058 all the bits above ptr_mode are known to be sign bit copies. */
5059 /* As we do not know which address space the pointer is referring to,
5060 we can do this only if the target does not support different pointer
5061 or address modes depending on the address space. */
5062 if (target_default_pointer_address_modes_p ()
5063 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
5064 && mode
== Pmode
&& REG_POINTER (x
)
5065 && !targetm
.have_ptr_extend ())
5066 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
5070 unsigned int copies_for_hook
= 1, copies
= 1;
5071 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5075 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5076 known_mode
, known_ret
);
5078 if (copies
> 1 || copies_for_hook
> 1)
5079 return MAX (copies
, copies_for_hook
);
5081 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5086 /* Some RISC machines sign-extend all loads of smaller than a word. */
5087 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5088 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5092 /* If this is a SUBREG for a promoted object that is sign-extended
5093 and we are looking at it in a wider mode, we know that at least the
5094 high-order bits are known to be sign bit copies. */
5096 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5098 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5099 known_x
, known_mode
, known_ret
);
5100 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5103 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5105 /* For a smaller object, just ignore the high bits. */
5106 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5108 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5109 known_x
, known_mode
,
5111 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5115 /* For paradoxical SUBREGs on machines where all register operations
5116 affect the entire register, just look inside. Note that we are
5117 passing MODE to the recursive call, so the number of sign bit
5118 copies will remain relative to that mode, not the inner mode.
5120 This works only if loads sign extend. Otherwise, if we get a
5121 reload for the inner part, it may be loaded from the stack, and
5122 then we lose all sign bit copies that existed before the store
5124 if (WORD_REGISTER_OPERATIONS
5125 && load_extend_op (inner_mode
) == SIGN_EXTEND
5126 && paradoxical_subreg_p (x
)
5127 && MEM_P (SUBREG_REG (x
)))
5128 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5129 known_x
, known_mode
, known_ret
);
5134 if (CONST_INT_P (XEXP (x
, 1)))
5135 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5139 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5140 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5141 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5142 known_x
, known_mode
, known_ret
));
5146 /* For a smaller object, just ignore the high bits. */
5147 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5148 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5149 known_x
, known_mode
, known_ret
);
5150 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5154 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5155 known_x
, known_mode
, known_ret
);
5157 case ROTATE
: case ROTATERT
:
5158 /* If we are rotating left by a number of bits less than the number
5159 of sign bit copies, we can just subtract that amount from the
5161 if (CONST_INT_P (XEXP (x
, 1))
5162 && INTVAL (XEXP (x
, 1)) >= 0
5163 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5165 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5166 known_x
, known_mode
, known_ret
);
5167 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5168 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5173 /* In general, this subtracts one sign bit copy. But if the value
5174 is known to be positive, the number of sign bit copies is the
5175 same as that of the input. Finally, if the input has just one bit
5176 that might be nonzero, all the bits are copies of the sign bit. */
5177 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5178 known_x
, known_mode
, known_ret
);
5179 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5180 return num0
> 1 ? num0
- 1 : 1;
5182 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5187 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5192 case IOR
: case AND
: case XOR
:
5193 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5194 /* Logical operations will preserve the number of sign-bit copies.
5195 MIN and MAX operations always return one of the operands. */
5196 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5197 known_x
, known_mode
, known_ret
);
5198 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5199 known_x
, known_mode
, known_ret
);
5201 /* If num1 is clearing some of the top bits then regardless of
5202 the other term, we are guaranteed to have at least that many
5203 high-order zero bits. */
5206 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5207 && CONST_INT_P (XEXP (x
, 1))
5208 && (UINTVAL (XEXP (x
, 1))
5209 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5212 /* Similarly for IOR when setting high-order bits. */
5215 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5216 && CONST_INT_P (XEXP (x
, 1))
5217 && (UINTVAL (XEXP (x
, 1))
5218 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5221 return MIN (num0
, num1
);
5223 case PLUS
: case MINUS
:
5224 /* For addition and subtraction, we can have a 1-bit carry. However,
5225 if we are subtracting 1 from a positive number, there will not
5226 be such a carry. Furthermore, if the positive number is known to
5227 be 0 or 1, we know the result is either -1 or 0. */
5229 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5230 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5232 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5233 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5234 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5235 : bitwidth
- floor_log2 (nonzero
) - 1);
5238 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5239 known_x
, known_mode
, known_ret
);
5240 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5241 known_x
, known_mode
, known_ret
);
5242 result
= MAX (1, MIN (num0
, num1
) - 1);
5247 /* The number of bits of the product is the sum of the number of
5248 bits of both terms. However, unless one of the terms if known
5249 to be positive, we must allow for an additional bit since negating
5250 a negative number can remove one sign bit copy. */
5252 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5253 known_x
, known_mode
, known_ret
);
5254 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5255 known_x
, known_mode
, known_ret
);
5257 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5259 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5260 || (((nonzero_bits (XEXP (x
, 0), mode
)
5261 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5262 && ((nonzero_bits (XEXP (x
, 1), mode
)
5263 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5267 return MAX (1, result
);
5270 /* The result must be <= the first operand. If the first operand
5271 has the high bit set, we know nothing about the number of sign
5273 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5275 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5276 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5279 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5280 known_x
, known_mode
, known_ret
);
5283 /* The result must be <= the second operand. If the second operand
5284 has (or just might have) the high bit set, we know nothing about
5285 the number of sign bit copies. */
5286 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5288 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5289 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5292 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5293 known_x
, known_mode
, known_ret
);
5296 /* Similar to unsigned division, except that we have to worry about
5297 the case where the divisor is negative, in which case we have
5299 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5300 known_x
, known_mode
, known_ret
);
5302 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5303 || (nonzero_bits (XEXP (x
, 1), mode
)
5304 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5310 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5311 known_x
, known_mode
, known_ret
);
5313 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5314 || (nonzero_bits (XEXP (x
, 1), mode
)
5315 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5321 /* Shifts by a constant add to the number of bits equal to the
5323 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5324 known_x
, known_mode
, known_ret
);
5325 if (CONST_INT_P (XEXP (x
, 1))
5326 && INTVAL (XEXP (x
, 1)) > 0
5327 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5328 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5333 /* Left shifts destroy copies. */
5334 if (!CONST_INT_P (XEXP (x
, 1))
5335 || INTVAL (XEXP (x
, 1)) < 0
5336 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5337 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5340 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5341 known_x
, known_mode
, known_ret
);
5342 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5345 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5346 known_x
, known_mode
, known_ret
);
5347 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5348 known_x
, known_mode
, known_ret
);
5349 return MIN (num0
, num1
);
5351 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5352 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5353 case GEU
: case GTU
: case LEU
: case LTU
:
5354 case UNORDERED
: case ORDERED
:
5355 /* If the constant is negative, take its 1's complement and remask.
5356 Then see how many zero bits we have. */
5357 nonzero
= STORE_FLAG_VALUE
;
5358 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5359 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5360 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5362 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5368 /* If we haven't been able to figure it out by one of the above rules,
5369 see if some of the high-order bits are known to be zero. If so,
5370 count those bits and return one less than that amount. If we can't
5371 safely compute the mask for this mode, always return BITWIDTH. */
5373 bitwidth
= GET_MODE_PRECISION (mode
);
5374 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5377 nonzero
= nonzero_bits (x
, mode
);
5378 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5379 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5382 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5383 zero indicates an instruction pattern without a known cost. */
5386 pattern_cost (rtx pat
, bool speed
)
5391 /* Extract the single set rtx from the instruction pattern. We
5392 can't use single_set since we only have the pattern. We also
5393 consider PARALLELs of a normal set and a single comparison. In
5394 that case we use the cost of the non-comparison SET operation,
5395 which is most-likely to be the real cost of this operation. */
5396 if (GET_CODE (pat
) == SET
)
5398 else if (GET_CODE (pat
) == PARALLEL
)
5401 rtx comparison
= NULL_RTX
;
5403 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5405 rtx x
= XVECEXP (pat
, 0, i
);
5406 if (GET_CODE (x
) == SET
)
5408 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5423 if (!set
&& comparison
)
5432 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5433 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5436 /* Calculate the cost of a single instruction. A return value of zero
5437 indicates an instruction pattern without a known cost. */
5440 insn_cost (rtx_insn
*insn
, bool speed
)
5442 if (targetm
.insn_cost
)
5443 return targetm
.insn_cost (insn
, speed
);
5445 return pattern_cost (PATTERN (insn
), speed
);
5448 /* Returns estimate on cost of computing SEQ. */
5451 seq_cost (const rtx_insn
*seq
, bool speed
)
5456 for (; seq
; seq
= NEXT_INSN (seq
))
5458 set
= single_set (seq
);
5460 cost
+= set_rtx_cost (set
, speed
);
5461 else if (NONDEBUG_INSN_P (seq
))
5463 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5474 /* Given an insn INSN and condition COND, return the condition in a
5475 canonical form to simplify testing by callers. Specifically:
5477 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5478 (2) Both operands will be machine operands; (cc0) will have been replaced.
5479 (3) If an operand is a constant, it will be the second operand.
5480 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5481 for GE, GEU, and LEU.
5483 If the condition cannot be understood, or is an inequality floating-point
5484 comparison which needs to be reversed, 0 will be returned.
5486 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5488 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5489 insn used in locating the condition was found. If a replacement test
5490 of the condition is desired, it should be placed in front of that
5491 insn and we will be sure that the inputs are still valid.
5493 If WANT_REG is nonzero, we wish the condition to be relative to that
5494 register, if possible. Therefore, do not canonicalize the condition
5495 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5496 to be a compare to a CC mode register.
5498 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5502 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5503 rtx_insn
**earliest
,
5504 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5507 rtx_insn
*prev
= insn
;
5511 int reverse_code
= 0;
5513 basic_block bb
= BLOCK_FOR_INSN (insn
);
5515 code
= GET_CODE (cond
);
5516 mode
= GET_MODE (cond
);
5517 op0
= XEXP (cond
, 0);
5518 op1
= XEXP (cond
, 1);
5521 code
= reversed_comparison_code (cond
, insn
);
5522 if (code
== UNKNOWN
)
5528 /* If we are comparing a register with zero, see if the register is set
5529 in the previous insn to a COMPARE or a comparison operation. Perform
5530 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5533 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5534 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5535 && op1
== CONST0_RTX (GET_MODE (op0
))
5538 /* Set nonzero when we find something of interest. */
5541 /* If comparison with cc0, import actual comparison from compare
5545 if ((prev
= prev_nonnote_insn (prev
)) == 0
5546 || !NONJUMP_INSN_P (prev
)
5547 || (set
= single_set (prev
)) == 0
5548 || SET_DEST (set
) != cc0_rtx
)
5551 op0
= SET_SRC (set
);
5552 op1
= CONST0_RTX (GET_MODE (op0
));
5557 /* If this is a COMPARE, pick up the two things being compared. */
5558 if (GET_CODE (op0
) == COMPARE
)
5560 op1
= XEXP (op0
, 1);
5561 op0
= XEXP (op0
, 0);
5564 else if (!REG_P (op0
))
5567 /* Go back to the previous insn. Stop if it is not an INSN. We also
5568 stop if it isn't a single set or if it has a REG_INC note because
5569 we don't want to bother dealing with it. */
5571 prev
= prev_nonnote_nondebug_insn (prev
);
5574 || !NONJUMP_INSN_P (prev
)
5575 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5576 /* In cfglayout mode, there do not have to be labels at the
5577 beginning of a block, or jumps at the end, so the previous
5578 conditions would not stop us when we reach bb boundary. */
5579 || BLOCK_FOR_INSN (prev
) != bb
)
5582 set
= set_of (op0
, prev
);
5585 && (GET_CODE (set
) != SET
5586 || !rtx_equal_p (SET_DEST (set
), op0
)))
5589 /* If this is setting OP0, get what it sets it to if it looks
5593 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5594 #ifdef FLOAT_STORE_FLAG_VALUE
5595 REAL_VALUE_TYPE fsfv
;
5598 /* ??? We may not combine comparisons done in a CCmode with
5599 comparisons not done in a CCmode. This is to aid targets
5600 like Alpha that have an IEEE compliant EQ instruction, and
5601 a non-IEEE compliant BEQ instruction. The use of CCmode is
5602 actually artificial, simply to prevent the combination, but
5603 should not affect other platforms.
5605 However, we must allow VOIDmode comparisons to match either
5606 CCmode or non-CCmode comparison, because some ports have
5607 modeless comparisons inside branch patterns.
5609 ??? This mode check should perhaps look more like the mode check
5610 in simplify_comparison in combine. */
5611 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5612 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5614 && inner_mode
!= VOIDmode
)
5616 if (GET_CODE (SET_SRC (set
)) == COMPARE
5619 && val_signbit_known_set_p (inner_mode
,
5621 #ifdef FLOAT_STORE_FLAG_VALUE
5623 && SCALAR_FLOAT_MODE_P (inner_mode
)
5624 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5625 REAL_VALUE_NEGATIVE (fsfv
)))
5628 && COMPARISON_P (SET_SRC (set
))))
5630 else if (((code
== EQ
5632 && val_signbit_known_set_p (inner_mode
,
5634 #ifdef FLOAT_STORE_FLAG_VALUE
5636 && SCALAR_FLOAT_MODE_P (inner_mode
)
5637 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5638 REAL_VALUE_NEGATIVE (fsfv
)))
5641 && COMPARISON_P (SET_SRC (set
)))
5646 else if ((code
== EQ
|| code
== NE
)
5647 && GET_CODE (SET_SRC (set
)) == XOR
)
5648 /* Handle sequences like:
5651 ...(eq|ne op0 (const_int 0))...
5655 (eq op0 (const_int 0)) reduces to (eq X Y)
5656 (ne op0 (const_int 0)) reduces to (ne X Y)
5658 This is the form used by MIPS16, for example. */
5664 else if (reg_set_p (op0
, prev
))
5665 /* If this sets OP0, but not directly, we have to give up. */
5670 /* If the caller is expecting the condition to be valid at INSN,
5671 make sure X doesn't change before INSN. */
5672 if (valid_at_insn_p
)
5673 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5675 if (COMPARISON_P (x
))
5676 code
= GET_CODE (x
);
5679 code
= reversed_comparison_code (x
, prev
);
5680 if (code
== UNKNOWN
)
5685 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5691 /* If constant is first, put it last. */
5692 if (CONSTANT_P (op0
))
5693 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5695 /* If OP0 is the result of a comparison, we weren't able to find what
5696 was really being compared, so fail. */
5698 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5701 /* Canonicalize any ordered comparison with integers involving equality
5702 if we can do computations in the relevant mode and we do not
5705 scalar_int_mode op0_mode
;
5706 if (CONST_INT_P (op1
)
5707 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
5708 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
5710 HOST_WIDE_INT const_val
= INTVAL (op1
);
5711 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5712 unsigned HOST_WIDE_INT max_val
5713 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
5718 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5719 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
5722 /* When cross-compiling, const_val might be sign-extended from
5723 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5725 if ((const_val
& max_val
)
5726 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
5727 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
5731 if (uconst_val
< max_val
)
5732 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
5736 if (uconst_val
!= 0)
5737 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
5745 /* Never return CC0; return zero instead. */
5749 /* We promised to return a comparison. */
5750 rtx ret
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5751 if (COMPARISON_P (ret
))
5756 /* Given a jump insn JUMP, return the condition that will cause it to branch
5757 to its JUMP_LABEL. If the condition cannot be understood, or is an
5758 inequality floating-point comparison which needs to be reversed, 0 will
5761 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5762 insn used in locating the condition was found. If a replacement test
5763 of the condition is desired, it should be placed in front of that
5764 insn and we will be sure that the inputs are still valid. If EARLIEST
5765 is null, the returned condition will be valid at INSN.
5767 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5768 compare CC mode register.
5770 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5773 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5774 int valid_at_insn_p
)
5780 /* If this is not a standard conditional jump, we can't parse it. */
5782 || ! any_condjump_p (jump
))
5784 set
= pc_set (jump
);
5786 cond
= XEXP (SET_SRC (set
), 0);
5788 /* If this branches to JUMP_LABEL when the condition is false, reverse
5791 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5792 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5794 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5795 allow_cc_mode
, valid_at_insn_p
);
5798 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5799 TARGET_MODE_REP_EXTENDED.
5801 Note that we assume that the property of
5802 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5803 narrower than mode B. I.e., if A is a mode narrower than B then in
5804 order to be able to operate on it in mode B, mode A needs to
5805 satisfy the requirements set by the representation of mode B. */
5808 init_num_sign_bit_copies_in_rep (void)
5810 opt_scalar_int_mode in_mode_iter
;
5811 scalar_int_mode mode
;
5813 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
5814 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
5816 scalar_int_mode in_mode
= in_mode_iter
.require ();
5819 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5820 extends to the next widest mode. */
5821 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5822 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
5824 /* We are in in_mode. Count how many bits outside of mode
5825 have to be copies of the sign-bit. */
5826 FOR_EACH_MODE (i
, mode
, in_mode
)
5828 /* This must always exist (for the last iteration it will be
5830 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
5832 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5833 /* We can only check sign-bit copies starting from the
5834 top-bit. In order to be able to check the bits we
5835 have already seen we pretend that subsequent bits
5836 have to be sign-bit copies too. */
5837 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5838 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5839 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5844 /* Suppose that truncation from the machine mode of X to MODE is not a
5845 no-op. See if there is anything special about X so that we can
5846 assume it already contains a truncated value of MODE. */
5849 truncated_to_mode (machine_mode mode
, const_rtx x
)
5851 /* This register has already been used in MODE without explicit
5853 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5856 /* See if we already satisfy the requirements of MODE. If yes we
5857 can just switch to MODE. */
5858 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5859 && (num_sign_bit_copies (x
, GET_MODE (x
))
5860 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5866 /* Return true if RTX code CODE has a single sequence of zero or more
5867 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5868 entry in that case. */
5871 setup_reg_subrtx_bounds (unsigned int code
)
5873 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5875 for (; format
[i
] != 'e'; ++i
)
5878 /* No subrtxes. Leave start and count as 0. */
5880 if (format
[i
] == 'E' || format
[i
] == 'V')
5884 /* Record the sequence of 'e's. */
5885 rtx_all_subrtx_bounds
[code
].start
= i
;
5888 while (format
[i
] == 'e');
5889 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5890 /* rtl-iter.h relies on this. */
5891 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5893 for (; format
[i
]; ++i
)
5894 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5900 /* Initialize rtx_all_subrtx_bounds. */
5905 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5907 if (!setup_reg_subrtx_bounds (i
))
5908 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5909 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5910 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5913 init_num_sign_bit_copies_in_rep ();
5916 /* Check whether this is a constant pool constant. */
5918 constant_pool_constant_p (rtx x
)
5920 x
= avoid_constant_pool_reference (x
);
5921 return CONST_DOUBLE_P (x
);
5924 /* If M is a bitmask that selects a field of low-order bits within an item but
5925 not the entire word, return the length of the field. Return -1 otherwise.
5926 M is used in machine mode MODE. */
5929 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5931 if (mode
!= VOIDmode
)
5933 if (!HWI_COMPUTABLE_MODE_P (mode
))
5935 m
&= GET_MODE_MASK (mode
);
5938 return exact_log2 (m
+ 1);
5941 /* Return the mode of MEM's address. */
5944 get_address_mode (rtx mem
)
5948 gcc_assert (MEM_P (mem
));
5949 mode
= GET_MODE (XEXP (mem
, 0));
5950 if (mode
!= VOIDmode
)
5951 return as_a
<scalar_int_mode
> (mode
);
5952 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5955 /* Split up a CONST_DOUBLE or integer constant rtx
5956 into two rtx's for single words,
5957 storing in *FIRST the word that comes first in memory in the target
5958 and in *SECOND the other.
5960 TODO: This function needs to be rewritten to work on any size
5964 split_double (rtx value
, rtx
*first
, rtx
*second
)
5966 if (CONST_INT_P (value
))
5968 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5970 /* In this case the CONST_INT holds both target words.
5971 Extract the bits from it into two word-sized pieces.
5972 Sign extend each half to HOST_WIDE_INT. */
5973 unsigned HOST_WIDE_INT low
, high
;
5974 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5975 unsigned bits_per_word
= BITS_PER_WORD
;
5977 /* Set sign_bit to the most significant bit of a word. */
5979 sign_bit
<<= bits_per_word
- 1;
5981 /* Set mask so that all bits of the word are set. We could
5982 have used 1 << BITS_PER_WORD instead of basing the
5983 calculation on sign_bit. However, on machines where
5984 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5985 compiler warning, even though the code would never be
5987 mask
= sign_bit
<< 1;
5990 /* Set sign_extend as any remaining bits. */
5991 sign_extend
= ~mask
;
5993 /* Pick the lower word and sign-extend it. */
5994 low
= INTVAL (value
);
5999 /* Pick the higher word, shifted to the least significant
6000 bits, and sign-extend it. */
6001 high
= INTVAL (value
);
6002 high
>>= bits_per_word
- 1;
6005 if (high
& sign_bit
)
6006 high
|= sign_extend
;
6008 /* Store the words in the target machine order. */
6009 if (WORDS_BIG_ENDIAN
)
6011 *first
= GEN_INT (high
);
6012 *second
= GEN_INT (low
);
6016 *first
= GEN_INT (low
);
6017 *second
= GEN_INT (high
);
6022 /* The rule for using CONST_INT for a wider mode
6023 is that we regard the value as signed.
6024 So sign-extend it. */
6025 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
6026 if (WORDS_BIG_ENDIAN
)
6038 else if (GET_CODE (value
) == CONST_WIDE_INT
)
6040 /* All of this is scary code and needs to be converted to
6041 properly work with any size integer. */
6042 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
6043 if (WORDS_BIG_ENDIAN
)
6045 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6046 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6050 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6051 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6054 else if (!CONST_DOUBLE_P (value
))
6056 if (WORDS_BIG_ENDIAN
)
6058 *first
= const0_rtx
;
6064 *second
= const0_rtx
;
6067 else if (GET_MODE (value
) == VOIDmode
6068 /* This is the old way we did CONST_DOUBLE integers. */
6069 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
6071 /* In an integer, the words are defined as most and least significant.
6072 So order them by the target's convention. */
6073 if (WORDS_BIG_ENDIAN
)
6075 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6076 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6080 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6081 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6088 /* Note, this converts the REAL_VALUE_TYPE to the target's
6089 format, splits up the floating point double and outputs
6090 exactly 32 bits of it into each of l[0] and l[1] --
6091 not necessarily BITS_PER_WORD bits. */
6092 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6094 /* If 32 bits is an entire word for the target, but not for the host,
6095 then sign-extend on the host so that the number will look the same
6096 way on the host that it would on the target. See for instance
6097 simplify_unary_operation. The #if is needed to avoid compiler
6100 #if HOST_BITS_PER_LONG > 32
6101 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6103 if (l
[0] & ((long) 1 << 31))
6104 l
[0] |= ((unsigned long) (-1) << 32);
6105 if (l
[1] & ((long) 1 << 31))
6106 l
[1] |= ((unsigned long) (-1) << 32);
6110 *first
= GEN_INT (l
[0]);
6111 *second
= GEN_INT (l
[1]);
6115 /* Return true if X is a sign_extract or zero_extract from the least
6119 lsb_bitfield_op_p (rtx x
)
6121 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6123 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6124 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6125 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6126 poly_int64 remaining_bits
= GET_MODE_PRECISION (mode
) - len
;
6128 return known_eq (pos
, BITS_BIG_ENDIAN
? remaining_bits
: 0);
6133 /* Strip outer address "mutations" from LOC and return a pointer to the
6134 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6135 stripped expression there.
6137 "Mutations" either convert between modes or apply some kind of
6138 extension, truncation or alignment. */
6141 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6145 enum rtx_code code
= GET_CODE (*loc
);
6146 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6147 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6148 used to convert between pointer sizes. */
6149 loc
= &XEXP (*loc
, 0);
6150 else if (lsb_bitfield_op_p (*loc
))
6151 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6152 acts as a combined truncation and extension. */
6153 loc
= &XEXP (*loc
, 0);
6154 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6155 /* (and ... (const_int -X)) is used to align to X bytes. */
6156 loc
= &XEXP (*loc
, 0);
6157 else if (code
== SUBREG
6158 && !OBJECT_P (SUBREG_REG (*loc
))
6159 && subreg_lowpart_p (*loc
))
6160 /* (subreg (operator ...) ...) inside and is used for mode
6162 loc
= &SUBREG_REG (*loc
);
6170 /* Return true if CODE applies some kind of scale. The scaled value is
6171 is the first operand and the scale is the second. */
6174 binary_scale_code_p (enum rtx_code code
)
6176 return (code
== MULT
6178 /* Needed by ARM targets. */
6182 || code
== ROTATERT
);
6185 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6186 (see address_info). Return null otherwise. */
6189 get_base_term (rtx
*inner
)
6191 if (GET_CODE (*inner
) == LO_SUM
)
6192 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6195 || GET_CODE (*inner
) == SUBREG
6196 || GET_CODE (*inner
) == SCRATCH
)
6201 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6202 (see address_info). Return null otherwise. */
6205 get_index_term (rtx
*inner
)
6207 /* At present, only constant scales are allowed. */
6208 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6209 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6212 || GET_CODE (*inner
) == SUBREG
6213 || GET_CODE (*inner
) == SCRATCH
)
6218 /* Set the segment part of address INFO to LOC, given that INNER is the
6222 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6224 gcc_assert (!info
->segment
);
6225 info
->segment
= loc
;
6226 info
->segment_term
= inner
;
6229 /* Set the base part of address INFO to LOC, given that INNER is the
6233 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6235 gcc_assert (!info
->base
);
6237 info
->base_term
= inner
;
6240 /* Set the index part of address INFO to LOC, given that INNER is the
6244 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6246 gcc_assert (!info
->index
);
6248 info
->index_term
= inner
;
6251 /* Set the displacement part of address INFO to LOC, given that INNER
6252 is the constant term. */
6255 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6257 gcc_assert (!info
->disp
);
6259 info
->disp_term
= inner
;
6262 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6263 rest of INFO accordingly. */
6266 decompose_incdec_address (struct address_info
*info
)
6268 info
->autoinc_p
= true;
6270 rtx
*base
= &XEXP (*info
->inner
, 0);
6271 set_address_base (info
, base
, base
);
6272 gcc_checking_assert (info
->base
== info
->base_term
);
6274 /* These addresses are only valid when the size of the addressed
6276 gcc_checking_assert (info
->mode
!= VOIDmode
);
6279 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6280 of INFO accordingly. */
6283 decompose_automod_address (struct address_info
*info
)
6285 info
->autoinc_p
= true;
6287 rtx
*base
= &XEXP (*info
->inner
, 0);
6288 set_address_base (info
, base
, base
);
6289 gcc_checking_assert (info
->base
== info
->base_term
);
6291 rtx plus
= XEXP (*info
->inner
, 1);
6292 gcc_assert (GET_CODE (plus
) == PLUS
);
6294 info
->base_term2
= &XEXP (plus
, 0);
6295 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6297 rtx
*step
= &XEXP (plus
, 1);
6298 rtx
*inner_step
= strip_address_mutations (step
);
6299 if (CONSTANT_P (*inner_step
))
6300 set_address_disp (info
, step
, inner_step
);
6302 set_address_index (info
, step
, inner_step
);
6305 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6306 values in [PTR, END). Return a pointer to the end of the used array. */
6309 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6312 if (GET_CODE (x
) == PLUS
)
6314 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6315 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6319 gcc_assert (ptr
!= end
);
6325 /* Evaluate the likelihood of X being a base or index value, returning
6326 positive if it is likely to be a base, negative if it is likely to be
6327 an index, and 0 if we can't tell. Make the magnitude of the return
6328 value reflect the amount of confidence we have in the answer.
6330 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6333 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6334 enum rtx_code outer_code
, enum rtx_code index_code
)
6336 /* Believe *_POINTER unless the address shape requires otherwise. */
6337 if (REG_P (x
) && REG_POINTER (x
))
6339 if (MEM_P (x
) && MEM_POINTER (x
))
6342 if (REG_P (x
) && HARD_REGISTER_P (x
))
6344 /* X is a hard register. If it only fits one of the base
6345 or index classes, choose that interpretation. */
6346 int regno
= REGNO (x
);
6347 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6348 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6349 if (base_p
!= index_p
)
6350 return base_p
? 1 : -1;
6355 /* INFO->INNER describes a normal, non-automodified address.
6356 Fill in the rest of INFO accordingly. */
6359 decompose_normal_address (struct address_info
*info
)
6361 /* Treat the address as the sum of up to four values. */
6363 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6364 ops
+ ARRAY_SIZE (ops
)) - ops
;
6366 /* If there is more than one component, any base component is in a PLUS. */
6368 info
->base_outer_code
= PLUS
;
6370 /* Try to classify each sum operand now. Leave those that could be
6371 either a base or an index in OPS. */
6374 for (size_t in
= 0; in
< n_ops
; ++in
)
6377 rtx
*inner
= strip_address_mutations (loc
);
6378 if (CONSTANT_P (*inner
))
6379 set_address_disp (info
, loc
, inner
);
6380 else if (GET_CODE (*inner
) == UNSPEC
)
6381 set_address_segment (info
, loc
, inner
);
6384 /* The only other possibilities are a base or an index. */
6385 rtx
*base_term
= get_base_term (inner
);
6386 rtx
*index_term
= get_index_term (inner
);
6387 gcc_assert (base_term
|| index_term
);
6389 set_address_index (info
, loc
, index_term
);
6390 else if (!index_term
)
6391 set_address_base (info
, loc
, base_term
);
6394 gcc_assert (base_term
== index_term
);
6396 inner_ops
[out
] = base_term
;
6402 /* Classify the remaining OPS members as bases and indexes. */
6405 /* If we haven't seen a base or an index yet, assume that this is
6406 the base. If we were confident that another term was the base
6407 or index, treat the remaining operand as the other kind. */
6409 set_address_base (info
, ops
[0], inner_ops
[0]);
6411 set_address_index (info
, ops
[0], inner_ops
[0]);
6415 /* In the event of a tie, assume the base comes first. */
6416 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6418 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6419 GET_CODE (*ops
[0])))
6421 set_address_base (info
, ops
[0], inner_ops
[0]);
6422 set_address_index (info
, ops
[1], inner_ops
[1]);
6426 set_address_base (info
, ops
[1], inner_ops
[1]);
6427 set_address_index (info
, ops
[0], inner_ops
[0]);
6431 gcc_assert (out
== 0);
6434 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6435 or VOIDmode if not known. AS is the address space associated with LOC.
6436 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6439 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6440 addr_space_t as
, enum rtx_code outer_code
)
6442 memset (info
, 0, sizeof (*info
));
6445 info
->addr_outer_code
= outer_code
;
6447 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6448 info
->base_outer_code
= outer_code
;
6449 switch (GET_CODE (*info
->inner
))
6455 decompose_incdec_address (info
);
6460 decompose_automod_address (info
);
6464 decompose_normal_address (info
);
6469 /* Describe address operand LOC in INFO. */
6472 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6474 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6477 /* Describe the address of MEM X in INFO. */
6480 decompose_mem_address (struct address_info
*info
, rtx x
)
6482 gcc_assert (MEM_P (x
));
6483 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6484 MEM_ADDR_SPACE (x
), MEM
);
6487 /* Update INFO after a change to the address it describes. */
6490 update_address (struct address_info
*info
)
6492 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6493 info
->addr_outer_code
);
6496 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6497 more complicated than that. */
6500 get_index_scale (const struct address_info
*info
)
6502 rtx index
= *info
->index
;
6503 if (GET_CODE (index
) == MULT
6504 && CONST_INT_P (XEXP (index
, 1))
6505 && info
->index_term
== &XEXP (index
, 0))
6506 return INTVAL (XEXP (index
, 1));
6508 if (GET_CODE (index
) == ASHIFT
6509 && CONST_INT_P (XEXP (index
, 1))
6510 && info
->index_term
== &XEXP (index
, 0))
6511 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6513 if (info
->index
== info
->index_term
)
6519 /* Return the "index code" of INFO, in the form required by
6523 get_index_code (const struct address_info
*info
)
6526 return GET_CODE (*info
->index
);
6529 return GET_CODE (*info
->disp
);
6534 /* Return true if RTL X contains a SYMBOL_REF. */
6537 contains_symbol_ref_p (const_rtx x
)
6539 subrtx_iterator::array_type array
;
6540 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6541 if (SYMBOL_REF_P (*iter
))
6547 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6550 contains_symbolic_reference_p (const_rtx x
)
6552 subrtx_iterator::array_type array
;
6553 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6554 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6560 /* Return true if RTL X contains a constant pool address. */
6563 contains_constant_pool_address_p (const_rtx x
)
6565 subrtx_iterator::array_type array
;
6566 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6567 if (SYMBOL_REF_P (*iter
) && CONSTANT_POOL_ADDRESS_P (*iter
))
6574 /* Return true if X contains a thread-local symbol. */
6577 tls_referenced_p (const_rtx x
)
6579 if (!targetm
.have_tls
)
6582 subrtx_iterator::array_type array
;
6583 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6584 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)