1 /* Check that the XF registers are not clobbered by an integer division
2 that is done using double precision FPU division. */
4 /* { dg-do run { target { default_single_fpu && has_xf_regs } } } */
5 /* { dg-options "-O1 -mdiv=call-fp" } */
10 extern void __set_fpscr (int);
15 __asm__
__volatile__ ("frchg; fmov.s @%0,fr0; frchg" : : "r" (f
) : "memory");
21 __asm__
__volatile__ ("frchg; fmov.s fr0,@%0; frchg" : : "r" (f
) : "memory");
24 int __attribute__ ((noinline
))
25 test_00 (int a
, int b
)
30 unsigned int __attribute__ ((noinline
))
31 test_01 (unsigned a
, unsigned b
)
36 int __attribute__ ((noinline
))
48 /* Set FPSCR.FR to 1. */
49 __set_fpscr (0x200000);
52 write_xf0 (&test_value
);
54 read_xf0 (&test_value
);
55 assert (test_value
== 123);
58 write_xf0 (&test_value
);
60 read_xf0 (&test_value
);
61 assert (test_value
== 321);