gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2" } */
   3
   4 /* The integer variable shift and rotate instructions truncate their
   5    shift amounts by the datasize.  Make sure that we don't emit a redundant
   6    masking operation.  */
   7
   8 unsigned
   9 f1 (unsigned x, int y)
  10 {
  11   return x << (y & 31);
  12 }
  13
  14 unsigned long long
  15 f2 (unsigned long long x, int y)
  16 {
  17   return x << (y & 63);
  18 }
  19
  20 unsigned long long
  21 f3 (unsigned long long bit_addr, int y)
  22 {
  23   unsigned long bitnumb = bit_addr & 63;
  24   return (1LL << bitnumb);
  25 }
  26
  27 unsigned int
  28 f4 (unsigned int x, unsigned int y)
  29 {
  30   y &= 31;
  31   return x >> y | (x << (32 - y));
  32 }
  33
  34 unsigned long long
  35 f5 (unsigned long long x, unsigned long long y)
  36 {
  37   y &= 63;
  38   return x >> y | (x << (64 - y));
  39 }
  40
  41 unsigned int
  42 f6 (unsigned int x, unsigned int y)
  43 {
  44   return (x << (32 - (y & 31)));
  45 }
  46
  47 unsigned long long
  48 f7 (unsigned long long x, unsigned long long y)
  49 {
  50   return (x << (64 - (y & 63)));
  51 }
  52
  53 unsigned long long
  54 f8 (unsigned long long x, unsigned long long y)
  55 {
  56   return (x << -(y & 63));
  57 }
  58
  59 /* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
  60 /* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */
  61 /* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */
  62 /* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */
  63 /* { dg-final { scan-assembler-not "and\tw\[0-9\]+, w\[0-9\]+, 31" } } */
  64 /* { dg-final { scan-assembler-not "and\tx\[0-9\]+, x\[0-9\]+, 63" } } */
  65 /* { dg-final { scan-assembler-not "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */