2011-10-08 Paul Thomas <pault@gcc.gnu.org>
[official-gcc.git] / gcc / postreload.c
blob8994366d922f8ddfac4df8498f636f3bd88a1605
1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010, 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
27 #include "machmode.h"
28 #include "hard-reg-set.h"
29 #include "rtl.h"
30 #include "tm_p.h"
31 #include "obstack.h"
32 #include "insn-config.h"
33 #include "flags.h"
34 #include "function.h"
35 #include "expr.h"
36 #include "optabs.h"
37 #include "regs.h"
38 #include "basic-block.h"
39 #include "reload.h"
40 #include "recog.h"
41 #include "output.h"
42 #include "cselib.h"
43 #include "diagnostic-core.h"
44 #include "except.h"
45 #include "tree.h"
46 #include "target.h"
47 #include "timevar.h"
48 #include "tree-pass.h"
49 #include "df.h"
50 #include "dbgcnt.h"
52 static int reload_cse_noop_set_p (rtx);
53 static void reload_cse_simplify (rtx, rtx);
54 static void reload_cse_regs_1 (rtx);
55 static int reload_cse_simplify_set (rtx, rtx);
56 static int reload_cse_simplify_operands (rtx, rtx);
58 static void reload_combine (void);
59 static void reload_combine_note_use (rtx *, rtx, int, rtx);
60 static void reload_combine_note_store (rtx, const_rtx, void *);
62 static bool reload_cse_move2add (rtx);
63 static void move2add_note_store (rtx, const_rtx, void *);
65 /* Call cse / combine like post-reload optimization phases.
66 FIRST is the first instruction. */
67 void
68 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
70 bool moves_converted;
71 reload_cse_regs_1 (first);
72 reload_combine ();
73 moves_converted = reload_cse_move2add (first);
74 if (flag_expensive_optimizations)
76 if (moves_converted)
77 reload_combine ();
78 reload_cse_regs_1 (first);
82 /* See whether a single set SET is a noop. */
83 static int
84 reload_cse_noop_set_p (rtx set)
86 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
87 return 0;
89 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
92 /* Try to simplify INSN. */
93 static void
94 reload_cse_simplify (rtx insn, rtx testreg)
96 rtx body = PATTERN (insn);
98 if (GET_CODE (body) == SET)
100 int count = 0;
102 /* Simplify even if we may think it is a no-op.
103 We may think a memory load of a value smaller than WORD_SIZE
104 is redundant because we haven't taken into account possible
105 implicit extension. reload_cse_simplify_set() will bring
106 this out, so it's safer to simplify before we delete. */
107 count += reload_cse_simplify_set (body, insn);
109 if (!count && reload_cse_noop_set_p (body))
111 rtx value = SET_DEST (body);
112 if (REG_P (value)
113 && ! REG_FUNCTION_VALUE_P (value))
114 value = 0;
115 check_for_inc_dec (insn);
116 delete_insn_and_edges (insn);
117 return;
120 if (count > 0)
121 apply_change_group ();
122 else
123 reload_cse_simplify_operands (insn, testreg);
125 else if (GET_CODE (body) == PARALLEL)
127 int i;
128 int count = 0;
129 rtx value = NULL_RTX;
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body) >= 0)
136 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
138 rtx part = XVECEXP (body, 0, i);
139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
140 cselib_invalidate_rtx (XEXP (part, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
148 rtx part = XVECEXP (body, 0, i);
149 if (GET_CODE (part) == SET)
151 if (! reload_cse_noop_set_p (part))
152 break;
153 if (REG_P (SET_DEST (part))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
156 if (value)
157 break;
158 value = SET_DEST (part);
161 else if (GET_CODE (part) != CLOBBER)
162 break;
165 if (i < 0)
167 check_for_inc_dec (insn);
168 delete_insn_and_edges (insn);
169 /* We're done with this insn. */
170 return;
173 /* It's not a no-op, but we can try to simplify it. */
174 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
175 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
176 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
178 if (count > 0)
179 apply_change_group ();
180 else
181 reload_cse_simplify_operands (insn, testreg);
185 /* Do a very simple CSE pass over the hard registers.
187 This function detects no-op moves where we happened to assign two
188 different pseudo-registers to the same hard register, and then
189 copied one to the other. Reload will generate a useless
190 instruction copying a register to itself.
192 This function also detects cases where we load a value from memory
193 into two different registers, and (if memory is more expensive than
194 registers) changes it to simply copy the first register into the
195 second register.
197 Another optimization is performed that scans the operands of each
198 instruction to see whether the value is already available in a
199 hard register. It then replaces the operand with the hard register
200 if possible, much like an optional reload would. */
202 static void
203 reload_cse_regs_1 (rtx first)
205 rtx insn;
206 rtx testreg = gen_rtx_REG (VOIDmode, -1);
208 cselib_init (CSELIB_RECORD_MEMORY);
209 init_alias_analysis ();
211 for (insn = first; insn; insn = NEXT_INSN (insn))
213 if (INSN_P (insn))
214 reload_cse_simplify (insn, testreg);
216 cselib_process_insn (insn);
219 /* Clean up. */
220 end_alias_analysis ();
221 cselib_finish ();
224 /* Try to simplify a single SET instruction. SET is the set pattern.
225 INSN is the instruction it came from.
226 This function only handles one case: if we set a register to a value
227 which is not a register, we try to find that value in some other register
228 and change the set into a register copy. */
230 static int
231 reload_cse_simplify_set (rtx set, rtx insn)
233 int did_change = 0;
234 int dreg;
235 rtx src;
236 reg_class_t dclass;
237 int old_cost;
238 cselib_val *val;
239 struct elt_loc_list *l;
240 #ifdef LOAD_EXTEND_OP
241 enum rtx_code extend_op = UNKNOWN;
242 #endif
243 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
245 dreg = true_regnum (SET_DEST (set));
246 if (dreg < 0)
247 return 0;
249 src = SET_SRC (set);
250 if (side_effects_p (src) || true_regnum (src) >= 0)
251 return 0;
253 dclass = REGNO_REG_CLASS (dreg);
255 #ifdef LOAD_EXTEND_OP
256 /* When replacing a memory with a register, we need to honor assumptions
257 that combine made wrt the contents of sign bits. We'll do this by
258 generating an extend instruction instead of a reg->reg copy. Thus
259 the destination must be a register that we can widen. */
260 if (MEM_P (src)
261 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
262 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
263 && !REG_P (SET_DEST (set)))
264 return 0;
265 #endif
267 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
268 if (! val)
269 return 0;
271 /* If memory loads are cheaper than register copies, don't change them. */
272 if (MEM_P (src))
273 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
274 else if (REG_P (src))
275 old_cost = register_move_cost (GET_MODE (src),
276 REGNO_REG_CLASS (REGNO (src)), dclass);
277 else
278 old_cost = set_src_cost (src, speed);
280 for (l = val->locs; l; l = l->next)
282 rtx this_rtx = l->loc;
283 int this_cost;
285 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
287 #ifdef LOAD_EXTEND_OP
288 if (extend_op != UNKNOWN)
290 HOST_WIDE_INT this_val;
292 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
293 constants, such as SYMBOL_REF, cannot be extended. */
294 if (!CONST_INT_P (this_rtx))
295 continue;
297 this_val = INTVAL (this_rtx);
298 switch (extend_op)
300 case ZERO_EXTEND:
301 this_val &= GET_MODE_MASK (GET_MODE (src));
302 break;
303 case SIGN_EXTEND:
304 /* ??? In theory we're already extended. */
305 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
306 break;
307 default:
308 gcc_unreachable ();
310 this_rtx = GEN_INT (this_val);
312 #endif
313 this_cost = set_src_cost (this_rtx, speed);
315 else if (REG_P (this_rtx))
317 #ifdef LOAD_EXTEND_OP
318 if (extend_op != UNKNOWN)
320 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
321 this_cost = set_src_cost (this_rtx, speed);
323 else
324 #endif
325 this_cost = register_move_cost (GET_MODE (this_rtx),
326 REGNO_REG_CLASS (REGNO (this_rtx)),
327 dclass);
329 else
330 continue;
332 /* If equal costs, prefer registers over anything else. That
333 tends to lead to smaller instructions on some machines. */
334 if (this_cost < old_cost
335 || (this_cost == old_cost
336 && REG_P (this_rtx)
337 && !REG_P (SET_SRC (set))))
339 #ifdef LOAD_EXTEND_OP
340 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
341 && extend_op != UNKNOWN
342 #ifdef CANNOT_CHANGE_MODE_CLASS
343 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
344 word_mode,
345 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
346 #endif
349 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
350 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
351 validate_change (insn, &SET_DEST (set), wide_dest, 1);
353 #endif
355 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
356 old_cost = this_cost, did_change = 1;
360 return did_change;
363 /* Try to replace operands in INSN with equivalent values that are already
364 in registers. This can be viewed as optional reloading.
366 For each non-register operand in the insn, see if any hard regs are
367 known to be equivalent to that operand. Record the alternatives which
368 can accept these hard registers. Among all alternatives, select the
369 ones which are better or equal to the one currently matching, where
370 "better" is in terms of '?' and '!' constraints. Among the remaining
371 alternatives, select the one which replaces most operands with
372 hard registers. */
374 static int
375 reload_cse_simplify_operands (rtx insn, rtx testreg)
377 int i, j;
379 /* For each operand, all registers that are equivalent to it. */
380 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
382 const char *constraints[MAX_RECOG_OPERANDS];
384 /* Vector recording how bad an alternative is. */
385 int *alternative_reject;
386 /* Vector recording how many registers can be introduced by choosing
387 this alternative. */
388 int *alternative_nregs;
389 /* Array of vectors recording, for each operand and each alternative,
390 which hard register to substitute, or -1 if the operand should be
391 left as it is. */
392 int *op_alt_regno[MAX_RECOG_OPERANDS];
393 /* Array of alternatives, sorted in order of decreasing desirability. */
394 int *alternative_order;
396 extract_insn (insn);
398 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
399 return 0;
401 /* Figure out which alternative currently matches. */
402 if (! constrain_operands (1))
403 fatal_insn_not_found (insn);
405 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
406 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
407 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
408 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
409 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
411 /* For each operand, find out which regs are equivalent. */
412 for (i = 0; i < recog_data.n_operands; i++)
414 cselib_val *v;
415 struct elt_loc_list *l;
416 rtx op;
418 CLEAR_HARD_REG_SET (equiv_regs[i]);
420 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
421 right, so avoid the problem here. Likewise if we have a constant
422 and the insn pattern doesn't tell us the mode we need. */
423 if (LABEL_P (recog_data.operand[i])
424 || (CONSTANT_P (recog_data.operand[i])
425 && recog_data.operand_mode[i] == VOIDmode))
426 continue;
428 op = recog_data.operand[i];
429 #ifdef LOAD_EXTEND_OP
430 if (MEM_P (op)
431 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
432 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
434 rtx set = single_set (insn);
436 /* We might have multiple sets, some of which do implicit
437 extension. Punt on this for now. */
438 if (! set)
439 continue;
440 /* If the destination is also a MEM or a STRICT_LOW_PART, no
441 extension applies.
442 Also, if there is an explicit extension, we don't have to
443 worry about an implicit one. */
444 else if (MEM_P (SET_DEST (set))
445 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
446 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
447 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
448 ; /* Continue ordinary processing. */
449 #ifdef CANNOT_CHANGE_MODE_CLASS
450 /* If the register cannot change mode to word_mode, it follows that
451 it cannot have been used in word_mode. */
452 else if (REG_P (SET_DEST (set))
453 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
454 word_mode,
455 REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
456 ; /* Continue ordinary processing. */
457 #endif
458 /* If this is a straight load, make the extension explicit. */
459 else if (REG_P (SET_DEST (set))
460 && recog_data.n_operands == 2
461 && SET_SRC (set) == op
462 && SET_DEST (set) == recog_data.operand[1-i])
464 validate_change (insn, recog_data.operand_loc[i],
465 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
466 word_mode, op),
468 validate_change (insn, recog_data.operand_loc[1-i],
469 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
471 if (! apply_change_group ())
472 return 0;
473 return reload_cse_simplify_operands (insn, testreg);
475 else
476 /* ??? There might be arithmetic operations with memory that are
477 safe to optimize, but is it worth the trouble? */
478 continue;
480 #endif /* LOAD_EXTEND_OP */
481 if (side_effects_p (op))
482 continue;
483 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
484 if (! v)
485 continue;
487 for (l = v->locs; l; l = l->next)
488 if (REG_P (l->loc))
489 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
492 for (i = 0; i < recog_data.n_operands; i++)
494 enum machine_mode mode;
495 int regno;
496 const char *p;
498 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
499 for (j = 0; j < recog_data.n_alternatives; j++)
500 op_alt_regno[i][j] = -1;
502 p = constraints[i] = recog_data.constraints[i];
503 mode = recog_data.operand_mode[i];
505 /* Add the reject values for each alternative given by the constraints
506 for this operand. */
507 j = 0;
508 while (*p != '\0')
510 char c = *p++;
511 if (c == ',')
512 j++;
513 else if (c == '?')
514 alternative_reject[j] += 3;
515 else if (c == '!')
516 alternative_reject[j] += 300;
519 /* We won't change operands which are already registers. We
520 also don't want to modify output operands. */
521 regno = true_regnum (recog_data.operand[i]);
522 if (regno >= 0
523 || constraints[i][0] == '='
524 || constraints[i][0] == '+')
525 continue;
527 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
529 enum reg_class rclass = NO_REGS;
531 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
532 continue;
534 SET_REGNO_RAW (testreg, regno);
535 PUT_MODE (testreg, mode);
537 /* We found a register equal to this operand. Now look for all
538 alternatives that can accept this register and have not been
539 assigned a register they can use yet. */
540 j = 0;
541 p = constraints[i];
542 for (;;)
544 char c = *p;
546 switch (c)
548 case '=': case '+': case '?':
549 case '#': case '&': case '!':
550 case '*': case '%':
551 case '0': case '1': case '2': case '3': case '4':
552 case '5': case '6': case '7': case '8': case '9':
553 case '<': case '>': case 'V': case 'o':
554 case 'E': case 'F': case 'G': case 'H':
555 case 's': case 'i': case 'n':
556 case 'I': case 'J': case 'K': case 'L':
557 case 'M': case 'N': case 'O': case 'P':
558 case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
559 /* These don't say anything we care about. */
560 break;
562 case 'g': case 'r':
563 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
564 break;
566 default:
567 rclass
568 = (reg_class_subunion
569 [(int) rclass]
570 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
571 break;
573 case ',': case '\0':
574 /* See if REGNO fits this alternative, and set it up as the
575 replacement register if we don't have one for this
576 alternative yet and the operand being replaced is not
577 a cheap CONST_INT. */
578 if (op_alt_regno[i][j] == -1
579 && recog_data.alternative_enabled_p[j]
580 && reg_fits_class_p (testreg, rclass, 0, mode)
581 && (!CONST_INT_P (recog_data.operand[i])
582 || (set_src_cost (recog_data.operand[i],
583 optimize_bb_for_speed_p
584 (BLOCK_FOR_INSN (insn)))
585 > set_src_cost (testreg,
586 optimize_bb_for_speed_p
587 (BLOCK_FOR_INSN (insn))))))
589 alternative_nregs[j]++;
590 op_alt_regno[i][j] = regno;
592 j++;
593 rclass = NO_REGS;
594 break;
596 p += CONSTRAINT_LEN (c, p);
598 if (c == '\0')
599 break;
604 /* Record all alternatives which are better or equal to the currently
605 matching one in the alternative_order array. */
606 for (i = j = 0; i < recog_data.n_alternatives; i++)
607 if (alternative_reject[i] <= alternative_reject[which_alternative])
608 alternative_order[j++] = i;
609 recog_data.n_alternatives = j;
611 /* Sort it. Given a small number of alternatives, a dumb algorithm
612 won't hurt too much. */
613 for (i = 0; i < recog_data.n_alternatives - 1; i++)
615 int best = i;
616 int best_reject = alternative_reject[alternative_order[i]];
617 int best_nregs = alternative_nregs[alternative_order[i]];
618 int tmp;
620 for (j = i + 1; j < recog_data.n_alternatives; j++)
622 int this_reject = alternative_reject[alternative_order[j]];
623 int this_nregs = alternative_nregs[alternative_order[j]];
625 if (this_reject < best_reject
626 || (this_reject == best_reject && this_nregs > best_nregs))
628 best = j;
629 best_reject = this_reject;
630 best_nregs = this_nregs;
634 tmp = alternative_order[best];
635 alternative_order[best] = alternative_order[i];
636 alternative_order[i] = tmp;
639 /* Substitute the operands as determined by op_alt_regno for the best
640 alternative. */
641 j = alternative_order[0];
643 for (i = 0; i < recog_data.n_operands; i++)
645 enum machine_mode mode = recog_data.operand_mode[i];
646 if (op_alt_regno[i][j] == -1)
647 continue;
649 validate_change (insn, recog_data.operand_loc[i],
650 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
653 for (i = recog_data.n_dups - 1; i >= 0; i--)
655 int op = recog_data.dup_num[i];
656 enum machine_mode mode = recog_data.operand_mode[op];
658 if (op_alt_regno[op][j] == -1)
659 continue;
661 validate_change (insn, recog_data.dup_loc[i],
662 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
665 return apply_change_group ();
668 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
669 addressing now.
670 This code might also be useful when reload gave up on reg+reg addressing
671 because of clashes between the return register and INDEX_REG_CLASS. */
673 /* The maximum number of uses of a register we can keep track of to
674 replace them with reg+reg addressing. */
675 #define RELOAD_COMBINE_MAX_USES 16
677 /* Describes a recorded use of a register. */
678 struct reg_use
680 /* The insn where a register has been used. */
681 rtx insn;
682 /* Points to the memory reference enclosing the use, if any, NULL_RTX
683 otherwise. */
684 rtx containing_mem;
685 /* Location of the register withing INSN. */
686 rtx *usep;
687 /* The reverse uid of the insn. */
688 int ruid;
691 /* If the register is used in some unknown fashion, USE_INDEX is negative.
692 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
693 indicates where it is first set or clobbered.
694 Otherwise, USE_INDEX is the index of the last encountered use of the
695 register (which is first among these we have seen since we scan backwards).
696 USE_RUID indicates the first encountered, i.e. last, of these uses.
697 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
698 with a constant offset; OFFSET contains this constant in that case.
699 STORE_RUID is always meaningful if we only want to use a value in a
700 register in a different place: it denotes the next insn in the insn
701 stream (i.e. the last encountered) that sets or clobbers the register.
702 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
703 static struct
705 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
706 rtx offset;
707 int use_index;
708 int store_ruid;
709 int real_store_ruid;
710 int use_ruid;
711 bool all_offsets_match;
712 } reg_state[FIRST_PSEUDO_REGISTER];
714 /* Reverse linear uid. This is increased in reload_combine while scanning
715 the instructions from last to first. It is used to set last_label_ruid
716 and the store_ruid / use_ruid fields in reg_state. */
717 static int reload_combine_ruid;
719 /* The RUID of the last label we encountered in reload_combine. */
720 static int last_label_ruid;
722 /* The RUID of the last jump we encountered in reload_combine. */
723 static int last_jump_ruid;
725 /* The register numbers of the first and last index register. A value of
726 -1 in LAST_INDEX_REG indicates that we've previously computed these
727 values and found no suitable index registers. */
728 static int first_index_reg = -1;
729 static int last_index_reg;
731 #define LABEL_LIVE(LABEL) \
732 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
734 /* Subroutine of reload_combine_split_ruids, called to fix up a single
735 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
737 static inline void
738 reload_combine_split_one_ruid (int *pruid, int split_ruid)
740 if (*pruid > split_ruid)
741 (*pruid)++;
744 /* Called when we insert a new insn in a position we've already passed in
745 the scan. Examine all our state, increasing all ruids that are higher
746 than SPLIT_RUID by one in order to make room for a new insn. */
748 static void
749 reload_combine_split_ruids (int split_ruid)
751 unsigned i;
753 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
754 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
755 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
759 int j, idx = reg_state[i].use_index;
760 reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
761 reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
762 reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
763 split_ruid);
764 if (idx < 0)
765 continue;
766 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
768 reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
769 split_ruid);
774 /* Called when we are about to rescan a previously encountered insn with
775 reload_combine_note_use after modifying some part of it. This clears all
776 information about uses in that particular insn. */
778 static void
779 reload_combine_purge_insn_uses (rtx insn)
781 unsigned i;
783 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
785 int j, k, idx = reg_state[i].use_index;
786 if (idx < 0)
787 continue;
788 j = k = RELOAD_COMBINE_MAX_USES;
789 while (j-- > idx)
791 if (reg_state[i].reg_use[j].insn != insn)
793 k--;
794 if (k != j)
795 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
798 reg_state[i].use_index = k;
802 /* Called when we need to forget about all uses of REGNO after an insn
803 which is identified by RUID. */
805 static void
806 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
808 int j, k, idx = reg_state[regno].use_index;
809 if (idx < 0)
810 return;
811 j = k = RELOAD_COMBINE_MAX_USES;
812 while (j-- > idx)
814 if (reg_state[regno].reg_use[j].ruid >= ruid)
816 k--;
817 if (k != j)
818 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
821 reg_state[regno].use_index = k;
824 /* Find the use of REGNO with the ruid that is highest among those
825 lower than RUID_LIMIT, and return it if it is the only use of this
826 reg in the insn. Return NULL otherwise. */
828 static struct reg_use *
829 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
831 int i, best_ruid = 0;
832 int use_idx = reg_state[regno].use_index;
833 struct reg_use *retval;
835 if (use_idx < 0)
836 return NULL;
837 retval = NULL;
838 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
840 struct reg_use *use = reg_state[regno].reg_use + i;
841 int this_ruid = use->ruid;
842 if (this_ruid >= ruid_limit)
843 continue;
844 if (this_ruid > best_ruid)
846 best_ruid = this_ruid;
847 retval = use;
849 else if (this_ruid == best_ruid)
850 retval = NULL;
852 if (last_label_ruid >= best_ruid)
853 return NULL;
854 return retval;
857 /* After we've moved an add insn, fix up any debug insns that occur
858 between the old location of the add and the new location. REG is
859 the destination register of the add insn; REPLACEMENT is the
860 SET_SRC of the add. FROM and TO specify the range in which we
861 should make this change on debug insns. */
863 static void
864 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
866 rtx insn;
867 for (insn = from; insn != to; insn = NEXT_INSN (insn))
869 rtx t;
871 if (!DEBUG_INSN_P (insn))
872 continue;
874 t = INSN_VAR_LOCATION_LOC (insn);
875 t = simplify_replace_rtx (t, reg, replacement);
876 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
880 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
881 with SRC in the insn described by USE, taking costs into account. Return
882 true if we made the replacement. */
884 static bool
885 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
887 rtx use_insn = use->insn;
888 rtx mem = use->containing_mem;
889 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
891 if (mem != NULL_RTX)
893 addr_space_t as = MEM_ADDR_SPACE (mem);
894 rtx oldaddr = XEXP (mem, 0);
895 rtx newaddr = NULL_RTX;
896 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
897 int new_cost;
899 newaddr = simplify_replace_rtx (oldaddr, reg, src);
900 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
902 XEXP (mem, 0) = newaddr;
903 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
904 XEXP (mem, 0) = oldaddr;
905 if (new_cost <= old_cost
906 && validate_change (use_insn,
907 &XEXP (mem, 0), newaddr, 0))
908 return true;
911 else
913 rtx new_set = single_set (use_insn);
914 if (new_set
915 && REG_P (SET_DEST (new_set))
916 && GET_CODE (SET_SRC (new_set)) == PLUS
917 && REG_P (XEXP (SET_SRC (new_set), 0))
918 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
920 rtx new_src;
921 int old_cost = set_src_cost (SET_SRC (new_set), speed);
923 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
924 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
926 if (set_src_cost (new_src, speed) <= old_cost
927 && validate_change (use_insn, &SET_SRC (new_set),
928 new_src, 0))
929 return true;
932 return false;
935 /* Called by reload_combine when scanning INSN. This function tries to detect
936 patterns where a constant is added to a register, and the result is used
937 in an address.
938 Return true if no further processing is needed on INSN; false if it wasn't
939 recognized and should be handled normally. */
941 static bool
942 reload_combine_recognize_const_pattern (rtx insn)
944 int from_ruid = reload_combine_ruid;
945 rtx set, pat, reg, src, addreg;
946 unsigned int regno;
947 struct reg_use *use;
948 bool must_move_add;
949 rtx add_moved_after_insn = NULL_RTX;
950 int add_moved_after_ruid = 0;
951 int clobbered_regno = -1;
953 set = single_set (insn);
954 if (set == NULL_RTX)
955 return false;
957 reg = SET_DEST (set);
958 src = SET_SRC (set);
959 if (!REG_P (reg)
960 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
961 || GET_MODE (reg) != Pmode
962 || reg == stack_pointer_rtx)
963 return false;
965 regno = REGNO (reg);
967 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
968 uses of REG1 inside an address, or inside another add insn. If
969 possible and profitable, merge the addition into subsequent
970 uses. */
971 if (GET_CODE (src) != PLUS
972 || !REG_P (XEXP (src, 0))
973 || !CONSTANT_P (XEXP (src, 1)))
974 return false;
976 addreg = XEXP (src, 0);
977 must_move_add = rtx_equal_p (reg, addreg);
979 pat = PATTERN (insn);
980 if (must_move_add && set != pat)
982 /* We have to be careful when moving the add; apart from the
983 single_set there may also be clobbers. Recognize one special
984 case, that of one clobber alongside the set (likely a clobber
985 of the CC register). */
986 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
987 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
988 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
989 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
990 return false;
991 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
996 use = reload_combine_closest_single_use (regno, from_ruid);
998 if (use)
999 /* Start the search for the next use from here. */
1000 from_ruid = use->ruid;
1002 if (use && GET_MODE (*use->usep) == Pmode)
1004 bool delete_add = false;
1005 rtx use_insn = use->insn;
1006 int use_ruid = use->ruid;
1008 /* Avoid moving the add insn past a jump. */
1009 if (must_move_add && use_ruid <= last_jump_ruid)
1010 break;
1012 /* If the add clobbers another hard reg in parallel, don't move
1013 it past a real set of this hard reg. */
1014 if (must_move_add && clobbered_regno >= 0
1015 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
1016 break;
1018 #ifdef HAVE_cc0
1019 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1020 if (must_move_add && sets_cc0_p (PATTERN (use_insn)))
1021 break;
1022 #endif
1024 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
1025 /* Avoid moving a use of ADDREG past a point where it is stored. */
1026 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1027 break;
1029 /* We also must not move the addition past an insn that sets
1030 the same register, unless we can combine two add insns. */
1031 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1033 if (use->containing_mem == NULL_RTX)
1034 delete_add = true;
1035 else
1036 break;
1039 if (try_replace_in_use (use, reg, src))
1041 reload_combine_purge_insn_uses (use_insn);
1042 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1043 use_ruid, NULL_RTX);
1045 if (delete_add)
1047 fixup_debug_insns (reg, src, insn, use_insn);
1048 delete_insn (insn);
1049 return true;
1051 if (must_move_add)
1053 add_moved_after_insn = use_insn;
1054 add_moved_after_ruid = use_ruid;
1056 continue;
1059 /* If we get here, we couldn't handle this use. */
1060 if (must_move_add)
1061 break;
1063 while (use);
1065 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1066 /* Process the add normally. */
1067 return false;
1069 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1071 reorder_insns (insn, insn, add_moved_after_insn);
1072 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1073 reload_combine_split_ruids (add_moved_after_ruid - 1);
1074 reload_combine_note_use (&PATTERN (insn), insn,
1075 add_moved_after_ruid, NULL_RTX);
1076 reg_state[regno].store_ruid = add_moved_after_ruid;
1078 return true;
1081 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1082 can handle and improve. Return true if no further processing is needed on
1083 INSN; false if it wasn't recognized and should be handled normally. */
1085 static bool
1086 reload_combine_recognize_pattern (rtx insn)
1088 rtx set, reg, src;
1089 unsigned int regno;
1091 set = single_set (insn);
1092 if (set == NULL_RTX)
1093 return false;
1095 reg = SET_DEST (set);
1096 src = SET_SRC (set);
1097 if (!REG_P (reg)
1098 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
1099 return false;
1101 regno = REGNO (reg);
1103 /* Look for (set (REGX) (CONST_INT))
1104 (set (REGX) (PLUS (REGX) (REGY)))
1106 ... (MEM (REGX)) ...
1107 and convert it to
1108 (set (REGZ) (CONST_INT))
1110 ... (MEM (PLUS (REGZ) (REGY)))... .
1112 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1113 and that we know all uses of REGX before it dies.
1114 Also, explicitly check that REGX != REGY; our life information
1115 does not yet show whether REGY changes in this insn. */
1117 if (GET_CODE (src) == PLUS
1118 && reg_state[regno].all_offsets_match
1119 && last_index_reg != -1
1120 && REG_P (XEXP (src, 1))
1121 && rtx_equal_p (XEXP (src, 0), reg)
1122 && !rtx_equal_p (XEXP (src, 1), reg)
1123 && reg_state[regno].use_index >= 0
1124 && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
1125 && last_label_ruid < reg_state[regno].use_ruid)
1127 rtx base = XEXP (src, 1);
1128 rtx prev = prev_nonnote_nondebug_insn (insn);
1129 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1130 rtx index_reg = NULL_RTX;
1131 rtx reg_sum = NULL_RTX;
1132 int i;
1134 /* Now we need to set INDEX_REG to an index register (denoted as
1135 REGZ in the illustration above) and REG_SUM to the expression
1136 register+register that we want to use to substitute uses of REG
1137 (typically in MEMs) with. First check REG and BASE for being
1138 index registers; we can use them even if they are not dead. */
1139 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1140 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1141 REGNO (base)))
1143 index_reg = reg;
1144 reg_sum = src;
1146 else
1148 /* Otherwise, look for a free index register. Since we have
1149 checked above that neither REG nor BASE are index registers,
1150 if we find anything at all, it will be different from these
1151 two registers. */
1152 for (i = first_index_reg; i <= last_index_reg; i++)
1154 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1155 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1156 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1157 && (call_used_regs[i] || df_regs_ever_live_p (i))
1158 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1159 && !fixed_regs[i] && !global_regs[i]
1160 && hard_regno_nregs[i][GET_MODE (reg)] == 1
1161 && targetm.hard_regno_scratch_ok (i))
1163 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1164 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1165 break;
1170 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1171 (REGY), i.e. BASE, is not clobbered before the last use we'll
1172 create. */
1173 if (reg_sum
1174 && prev_set
1175 && CONST_INT_P (SET_SRC (prev_set))
1176 && rtx_equal_p (SET_DEST (prev_set), reg)
1177 && (reg_state[REGNO (base)].store_ruid
1178 <= reg_state[regno].use_ruid))
1180 /* Change destination register and, if necessary, the constant
1181 value in PREV, the constant loading instruction. */
1182 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1183 if (reg_state[regno].offset != const0_rtx)
1184 validate_change (prev,
1185 &SET_SRC (prev_set),
1186 GEN_INT (INTVAL (SET_SRC (prev_set))
1187 + INTVAL (reg_state[regno].offset)),
1190 /* Now for every use of REG that we have recorded, replace REG
1191 with REG_SUM. */
1192 for (i = reg_state[regno].use_index;
1193 i < RELOAD_COMBINE_MAX_USES; i++)
1194 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1195 reg_state[regno].reg_use[i].usep,
1196 /* Each change must have its own
1197 replacement. */
1198 reg_sum, 1);
1200 if (apply_change_group ())
1202 struct reg_use *lowest_ruid = NULL;
1204 /* For every new use of REG_SUM, we have to record the use
1205 of BASE therein, i.e. operand 1. */
1206 for (i = reg_state[regno].use_index;
1207 i < RELOAD_COMBINE_MAX_USES; i++)
1209 struct reg_use *use = reg_state[regno].reg_use + i;
1210 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1211 use->ruid, use->containing_mem);
1212 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1213 lowest_ruid = use;
1216 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1218 /* Delete the reg-reg addition. */
1219 delete_insn (insn);
1221 if (reg_state[regno].offset != const0_rtx)
1222 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1223 are now invalid. */
1224 remove_reg_equal_equiv_notes (prev);
1226 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1227 return true;
1231 return false;
1234 static void
1235 reload_combine (void)
1237 rtx insn, prev;
1238 basic_block bb;
1239 unsigned int r;
1240 int min_labelno, n_labels;
1241 HARD_REG_SET ever_live_at_start, *label_live;
1243 /* To avoid wasting too much time later searching for an index register,
1244 determine the minimum and maximum index register numbers. */
1245 if (INDEX_REG_CLASS == NO_REGS)
1246 last_index_reg = -1;
1247 else if (first_index_reg == -1 && last_index_reg == 0)
1249 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1250 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1252 if (first_index_reg == -1)
1253 first_index_reg = r;
1255 last_index_reg = r;
1258 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1259 to -1 so we'll know to quit early the next time we get here. */
1260 if (first_index_reg == -1)
1262 last_index_reg = -1;
1263 return;
1267 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1268 information is a bit fuzzy immediately after reload, but it's
1269 still good enough to determine which registers are live at a jump
1270 destination. */
1271 min_labelno = get_first_label_num ();
1272 n_labels = max_label_num () - min_labelno;
1273 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1274 CLEAR_HARD_REG_SET (ever_live_at_start);
1276 FOR_EACH_BB_REVERSE (bb)
1278 insn = BB_HEAD (bb);
1279 if (LABEL_P (insn))
1281 HARD_REG_SET live;
1282 bitmap live_in = df_get_live_in (bb);
1284 REG_SET_TO_HARD_REG_SET (live, live_in);
1285 compute_use_by_pseudos (&live, live_in);
1286 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
1287 IOR_HARD_REG_SET (ever_live_at_start, live);
1291 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1292 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1293 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1295 reg_state[r].store_ruid = 0;
1296 reg_state[r].real_store_ruid = 0;
1297 if (fixed_regs[r])
1298 reg_state[r].use_index = -1;
1299 else
1300 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1303 for (insn = get_last_insn (); insn; insn = prev)
1305 bool control_flow_insn;
1306 rtx note;
1308 prev = PREV_INSN (insn);
1310 /* We cannot do our optimization across labels. Invalidating all the use
1311 information we have would be costly, so we just note where the label
1312 is and then later disable any optimization that would cross it. */
1313 if (LABEL_P (insn))
1314 last_label_ruid = reload_combine_ruid;
1315 else if (BARRIER_P (insn)
1316 || (INSN_P (insn) && volatile_insn_p (PATTERN (insn))))
1317 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1318 if (! fixed_regs[r])
1319 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1321 if (! NONDEBUG_INSN_P (insn))
1322 continue;
1324 reload_combine_ruid++;
1326 control_flow_insn = control_flow_insn_p (insn);
1327 if (control_flow_insn)
1328 last_jump_ruid = reload_combine_ruid;
1330 if (reload_combine_recognize_const_pattern (insn)
1331 || reload_combine_recognize_pattern (insn))
1332 continue;
1334 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1336 if (CALL_P (insn))
1338 rtx link;
1340 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1341 if (call_used_regs[r])
1343 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1344 reg_state[r].store_ruid = reload_combine_ruid;
1347 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1348 link = XEXP (link, 1))
1350 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
1351 if (REG_P (usage_rtx))
1353 unsigned int i;
1354 unsigned int start_reg = REGNO (usage_rtx);
1355 unsigned int num_regs
1356 = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)];
1357 unsigned int end_reg = start_reg + num_regs - 1;
1358 for (i = start_reg; i <= end_reg; i++)
1359 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1361 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1362 reg_state[i].store_ruid = reload_combine_ruid;
1364 else
1365 reg_state[i].use_index = -1;
1370 if (control_flow_insn && GET_CODE (PATTERN (insn)) != RETURN)
1372 /* Non-spill registers might be used at the call destination in
1373 some unknown fashion, so we have to mark the unknown use. */
1374 HARD_REG_SET *live;
1376 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1377 && JUMP_LABEL (insn))
1378 live = &LABEL_LIVE (JUMP_LABEL (insn));
1379 else
1380 live = &ever_live_at_start;
1382 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1383 if (TEST_HARD_REG_BIT (*live, r))
1384 reg_state[r].use_index = -1;
1387 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1388 NULL_RTX);
1390 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1392 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1394 int regno = REGNO (XEXP (note, 0));
1395 reg_state[regno].store_ruid = reload_combine_ruid;
1396 reg_state[regno].real_store_ruid = reload_combine_ruid;
1397 reg_state[regno].use_index = -1;
1402 free (label_live);
1405 /* Check if DST is a register or a subreg of a register; if it is,
1406 update store_ruid, real_store_ruid and use_index in the reg_state
1407 structure accordingly. Called via note_stores from reload_combine. */
1409 static void
1410 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1412 int regno = 0;
1413 int i;
1414 enum machine_mode mode = GET_MODE (dst);
1416 if (GET_CODE (dst) == SUBREG)
1418 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1419 GET_MODE (SUBREG_REG (dst)),
1420 SUBREG_BYTE (dst),
1421 GET_MODE (dst));
1422 dst = SUBREG_REG (dst);
1425 /* Some targets do argument pushes without adding REG_INC notes. */
1427 if (MEM_P (dst))
1429 dst = XEXP (dst, 0);
1430 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
1431 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC
1432 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY)
1434 regno = REGNO (XEXP (dst, 0));
1435 mode = GET_MODE (XEXP (dst, 0));
1436 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1438 /* We could probably do better, but for now mark the register
1439 as used in an unknown fashion and set/clobbered at this
1440 insn. */
1441 reg_state[i].use_index = -1;
1442 reg_state[i].store_ruid = reload_combine_ruid;
1443 reg_state[i].real_store_ruid = reload_combine_ruid;
1446 else
1447 return;
1450 if (!REG_P (dst))
1451 return;
1452 regno += REGNO (dst);
1454 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1455 careful with registers / register parts that are not full words.
1456 Similarly for ZERO_EXTRACT. */
1457 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1458 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1460 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1462 reg_state[i].use_index = -1;
1463 reg_state[i].store_ruid = reload_combine_ruid;
1464 reg_state[i].real_store_ruid = reload_combine_ruid;
1467 else
1469 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1471 reg_state[i].store_ruid = reload_combine_ruid;
1472 if (GET_CODE (set) == SET)
1473 reg_state[i].real_store_ruid = reload_combine_ruid;
1474 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1479 /* XP points to a piece of rtl that has to be checked for any uses of
1480 registers.
1481 *XP is the pattern of INSN, or a part of it.
1482 Called from reload_combine, and recursively by itself. */
1483 static void
1484 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1486 rtx x = *xp;
1487 enum rtx_code code = x->code;
1488 const char *fmt;
1489 int i, j;
1490 rtx offset = const0_rtx; /* For the REG case below. */
1492 switch (code)
1494 case SET:
1495 if (REG_P (SET_DEST (x)))
1497 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1498 return;
1500 break;
1502 case USE:
1503 /* If this is the USE of a return value, we can't change it. */
1504 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1506 /* Mark the return register as used in an unknown fashion. */
1507 rtx reg = XEXP (x, 0);
1508 int regno = REGNO (reg);
1509 int nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1511 while (--nregs >= 0)
1512 reg_state[regno + nregs].use_index = -1;
1513 return;
1515 break;
1517 case CLOBBER:
1518 if (REG_P (SET_DEST (x)))
1520 /* No spurious CLOBBERs of pseudo registers may remain. */
1521 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1522 return;
1524 break;
1526 case PLUS:
1527 /* We are interested in (plus (reg) (const_int)) . */
1528 if (!REG_P (XEXP (x, 0))
1529 || !CONST_INT_P (XEXP (x, 1)))
1530 break;
1531 offset = XEXP (x, 1);
1532 x = XEXP (x, 0);
1533 /* Fall through. */
1534 case REG:
1536 int regno = REGNO (x);
1537 int use_index;
1538 int nregs;
1540 /* No spurious USEs of pseudo registers may remain. */
1541 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1543 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1545 /* We can't substitute into multi-hard-reg uses. */
1546 if (nregs > 1)
1548 while (--nregs >= 0)
1549 reg_state[regno + nregs].use_index = -1;
1550 return;
1553 /* We may be called to update uses in previously seen insns.
1554 Don't add uses beyond the last store we saw. */
1555 if (ruid < reg_state[regno].store_ruid)
1556 return;
1558 /* If this register is already used in some unknown fashion, we
1559 can't do anything.
1560 If we decrement the index from zero to -1, we can't store more
1561 uses, so this register becomes used in an unknown fashion. */
1562 use_index = --reg_state[regno].use_index;
1563 if (use_index < 0)
1564 return;
1566 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1568 /* This is the first use of this register we have seen since we
1569 marked it as dead. */
1570 reg_state[regno].offset = offset;
1571 reg_state[regno].all_offsets_match = true;
1572 reg_state[regno].use_ruid = ruid;
1574 else
1576 if (reg_state[regno].use_ruid > ruid)
1577 reg_state[regno].use_ruid = ruid;
1579 if (! rtx_equal_p (offset, reg_state[regno].offset))
1580 reg_state[regno].all_offsets_match = false;
1583 reg_state[regno].reg_use[use_index].insn = insn;
1584 reg_state[regno].reg_use[use_index].ruid = ruid;
1585 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1586 reg_state[regno].reg_use[use_index].usep = xp;
1587 return;
1590 case MEM:
1591 containing_mem = x;
1592 break;
1594 default:
1595 break;
1598 /* Recursively process the components of X. */
1599 fmt = GET_RTX_FORMAT (code);
1600 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1602 if (fmt[i] == 'e')
1603 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1604 else if (fmt[i] == 'E')
1606 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1607 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1608 containing_mem);
1613 /* See if we can reduce the cost of a constant by replacing a move
1614 with an add. We track situations in which a register is set to a
1615 constant or to a register plus a constant. */
1616 /* We cannot do our optimization across labels. Invalidating all the
1617 information about register contents we have would be costly, so we
1618 use move2add_last_label_luid to note where the label is and then
1619 later disable any optimization that would cross it.
1620 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1621 are only valid if reg_set_luid[n] is greater than
1622 move2add_last_label_luid. */
1623 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1625 /* If reg_base_reg[n] is negative, register n has been set to
1626 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1627 If reg_base_reg[n] is non-negative, register n has been set to the
1628 sum of reg_offset[n] and the value of register reg_base_reg[n]
1629 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1630 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1631 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1632 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1633 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1635 /* move2add_luid is linearly increased while scanning the instructions
1636 from first to last. It is used to set reg_set_luid in
1637 reload_cse_move2add and move2add_note_store. */
1638 static int move2add_luid;
1640 /* move2add_last_label_luid is set whenever a label is found. Labels
1641 invalidate all previously collected reg_offset data. */
1642 static int move2add_last_label_luid;
1644 /* ??? We don't know how zero / sign extension is handled, hence we
1645 can't go from a narrower to a wider mode. */
1646 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1647 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1648 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1649 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1651 /* This function is called with INSN that sets REG to (SYM + OFF),
1652 while REG is known to already have value (SYM + offset).
1653 This function tries to change INSN into an add instruction
1654 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1655 It also updates the information about REG's known value.
1656 Return true if we made a change. */
1658 static bool
1659 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1661 rtx pat = PATTERN (insn);
1662 rtx src = SET_SRC (pat);
1663 int regno = REGNO (reg);
1664 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1665 GET_MODE (reg));
1666 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1667 bool changed = false;
1669 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1670 use (set (reg) (reg)) instead.
1671 We don't delete this insn, nor do we convert it into a
1672 note, to avoid losing register notes or the return
1673 value flag. jump2 already knows how to get rid of
1674 no-op moves. */
1675 if (new_src == const0_rtx)
1677 /* If the constants are different, this is a
1678 truncation, that, if turned into (set (reg)
1679 (reg)), would be discarded. Maybe we should
1680 try a truncMN pattern? */
1681 if (INTVAL (off) == reg_offset [regno])
1682 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1684 else
1686 struct full_rtx_costs oldcst, newcst;
1687 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1689 get_full_set_rtx_cost (pat, &oldcst);
1690 SET_SRC (pat) = tem;
1691 get_full_set_rtx_cost (pat, &newcst);
1692 SET_SRC (pat) = src;
1694 if (costs_lt_p (&newcst, &oldcst, speed)
1695 && have_add2_insn (reg, new_src))
1696 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1697 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1699 enum machine_mode narrow_mode;
1700 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
1701 narrow_mode != VOIDmode
1702 && narrow_mode != GET_MODE (reg);
1703 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
1705 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1706 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1707 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1709 rtx narrow_reg = gen_rtx_REG (narrow_mode,
1710 REGNO (reg));
1711 rtx narrow_src = gen_int_mode (INTVAL (off),
1712 narrow_mode);
1713 rtx new_set
1714 = gen_rtx_SET (VOIDmode,
1715 gen_rtx_STRICT_LOW_PART (VOIDmode,
1716 narrow_reg),
1717 narrow_src);
1718 changed = validate_change (insn, &PATTERN (insn),
1719 new_set, 0);
1720 if (changed)
1721 break;
1726 reg_set_luid[regno] = move2add_luid;
1727 reg_base_reg[regno] = -1;
1728 reg_mode[regno] = GET_MODE (reg);
1729 reg_symbol_ref[regno] = sym;
1730 reg_offset[regno] = INTVAL (off);
1731 return changed;
1735 /* This function is called with INSN that sets REG to (SYM + OFF),
1736 but REG doesn't have known value (SYM + offset). This function
1737 tries to find another register which is known to already have
1738 value (SYM + offset) and change INSN into an add instruction
1739 (set (REG) (plus (the found register) (OFF - offset))) if such
1740 a register is found. It also updates the information about
1741 REG's known value.
1742 Return true iff we made a change. */
1744 static bool
1745 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1747 rtx pat = PATTERN (insn);
1748 rtx src = SET_SRC (pat);
1749 int regno = REGNO (reg);
1750 int min_regno = 0;
1751 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1752 int i;
1753 bool changed = false;
1754 struct full_rtx_costs oldcst, newcst, mincst;
1755 rtx plus_expr;
1757 init_costs_to_max (&mincst);
1758 get_full_set_rtx_cost (pat, &oldcst);
1760 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1761 SET_SRC (pat) = plus_expr;
1763 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1764 if (reg_set_luid[i] > move2add_last_label_luid
1765 && reg_mode[i] == GET_MODE (reg)
1766 && reg_base_reg[i] < 0
1767 && reg_symbol_ref[i] != NULL_RTX
1768 && rtx_equal_p (sym, reg_symbol_ref[i]))
1770 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
1771 GET_MODE (reg));
1772 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1773 use (set (reg) (reg)) instead.
1774 We don't delete this insn, nor do we convert it into a
1775 note, to avoid losing register notes or the return
1776 value flag. jump2 already knows how to get rid of
1777 no-op moves. */
1778 if (new_src == const0_rtx)
1780 init_costs_to_zero (&mincst);
1781 min_regno = i;
1782 break;
1784 else
1786 XEXP (plus_expr, 1) = new_src;
1787 get_full_set_rtx_cost (pat, &newcst);
1789 if (costs_lt_p (&newcst, &mincst, speed))
1791 mincst = newcst;
1792 min_regno = i;
1796 SET_SRC (pat) = src;
1798 if (costs_lt_p (&mincst, &oldcst, speed))
1800 rtx tem;
1802 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1803 if (i != min_regno)
1805 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
1806 GET_MODE (reg));
1807 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1809 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1810 changed = true;
1812 reg_set_luid[regno] = move2add_luid;
1813 reg_base_reg[regno] = -1;
1814 reg_mode[regno] = GET_MODE (reg);
1815 reg_symbol_ref[regno] = sym;
1816 reg_offset[regno] = INTVAL (off);
1817 return changed;
1820 /* Convert move insns with constant inputs to additions if they are cheaper.
1821 Return true if any changes were made. */
1822 static bool
1823 reload_cse_move2add (rtx first)
1825 int i;
1826 rtx insn;
1827 bool changed = false;
1829 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1831 reg_set_luid[i] = 0;
1832 reg_offset[i] = 0;
1833 reg_base_reg[i] = 0;
1834 reg_symbol_ref[i] = NULL_RTX;
1835 reg_mode[i] = VOIDmode;
1838 move2add_last_label_luid = 0;
1839 move2add_luid = 2;
1840 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1842 rtx pat, note;
1844 if (LABEL_P (insn))
1846 move2add_last_label_luid = move2add_luid;
1847 /* We're going to increment move2add_luid twice after a
1848 label, so that we can use move2add_last_label_luid + 1 as
1849 the luid for constants. */
1850 move2add_luid++;
1851 continue;
1853 if (! INSN_P (insn))
1854 continue;
1855 pat = PATTERN (insn);
1856 /* For simplicity, we only perform this optimization on
1857 straightforward SETs. */
1858 if (GET_CODE (pat) == SET
1859 && REG_P (SET_DEST (pat)))
1861 rtx reg = SET_DEST (pat);
1862 int regno = REGNO (reg);
1863 rtx src = SET_SRC (pat);
1865 /* Check if we have valid information on the contents of this
1866 register in the mode of REG. */
1867 if (reg_set_luid[regno] > move2add_last_label_luid
1868 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1869 && dbg_cnt (cse2_move2add))
1871 /* Try to transform (set (REGX) (CONST_INT A))
1873 (set (REGX) (CONST_INT B))
1875 (set (REGX) (CONST_INT A))
1877 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1879 (set (REGX) (CONST_INT A))
1881 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1884 if (CONST_INT_P (src)
1885 && reg_base_reg[regno] < 0
1886 && reg_symbol_ref[regno] == NULL_RTX)
1888 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1889 continue;
1892 /* Try to transform (set (REGX) (REGY))
1893 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1895 (set (REGX) (REGY))
1896 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1898 (set (REGX) (REGY))
1899 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1901 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1902 else if (REG_P (src)
1903 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1904 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1905 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
1906 reg_mode[REGNO (src)]))
1908 rtx next = next_nonnote_nondebug_insn (insn);
1909 rtx set = NULL_RTX;
1910 if (next)
1911 set = single_set (next);
1912 if (set
1913 && SET_DEST (set) == reg
1914 && GET_CODE (SET_SRC (set)) == PLUS
1915 && XEXP (SET_SRC (set), 0) == reg
1916 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1918 rtx src3 = XEXP (SET_SRC (set), 1);
1919 HOST_WIDE_INT added_offset = INTVAL (src3);
1920 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1921 HOST_WIDE_INT regno_offset = reg_offset[regno];
1922 rtx new_src =
1923 gen_int_mode (added_offset
1924 + base_offset
1925 - regno_offset,
1926 GET_MODE (reg));
1927 bool success = false;
1928 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1930 if (new_src == const0_rtx)
1931 /* See above why we create (set (reg) (reg)) here. */
1932 success
1933 = validate_change (next, &SET_SRC (set), reg, 0);
1934 else
1936 rtx old_src = SET_SRC (set);
1937 struct full_rtx_costs oldcst, newcst;
1938 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1940 get_full_set_rtx_cost (set, &oldcst);
1941 SET_SRC (set) = tem;
1942 get_full_set_src_cost (tem, &newcst);
1943 SET_SRC (set) = old_src;
1944 costs_add_n_insns (&oldcst, 1);
1946 if (costs_lt_p (&newcst, &oldcst, speed)
1947 && have_add2_insn (reg, new_src))
1949 rtx newpat = gen_rtx_SET (VOIDmode, reg, tem);
1950 success
1951 = validate_change (next, &PATTERN (next),
1952 newpat, 0);
1955 if (success)
1956 delete_insn (insn);
1957 changed |= success;
1958 insn = next;
1959 reg_mode[regno] = GET_MODE (reg);
1960 reg_offset[regno] =
1961 trunc_int_for_mode (added_offset + base_offset,
1962 GET_MODE (reg));
1963 continue;
1968 /* Try to transform
1969 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1971 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1973 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1975 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1976 if ((GET_CODE (src) == SYMBOL_REF
1977 || (GET_CODE (src) == CONST
1978 && GET_CODE (XEXP (src, 0)) == PLUS
1979 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
1980 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
1981 && dbg_cnt (cse2_move2add))
1983 rtx sym, off;
1985 if (GET_CODE (src) == SYMBOL_REF)
1987 sym = src;
1988 off = const0_rtx;
1990 else
1992 sym = XEXP (XEXP (src, 0), 0);
1993 off = XEXP (XEXP (src, 0), 1);
1996 /* If the reg already contains the value which is sum of
1997 sym and some constant value, we can use an add2 insn. */
1998 if (reg_set_luid[regno] > move2add_last_label_luid
1999 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
2000 && reg_base_reg[regno] < 0
2001 && reg_symbol_ref[regno] != NULL_RTX
2002 && rtx_equal_p (sym, reg_symbol_ref[regno]))
2003 changed |= move2add_use_add2_insn (reg, sym, off, insn);
2005 /* Otherwise, we have to find a register whose value is sum
2006 of sym and some constant value. */
2007 else
2008 changed |= move2add_use_add3_insn (reg, sym, off, insn);
2010 continue;
2014 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2016 if (REG_NOTE_KIND (note) == REG_INC
2017 && REG_P (XEXP (note, 0)))
2019 /* Reset the information about this register. */
2020 int regno = REGNO (XEXP (note, 0));
2021 if (regno < FIRST_PSEUDO_REGISTER)
2022 reg_set_luid[regno] = 0;
2025 note_stores (PATTERN (insn), move2add_note_store, insn);
2027 /* If INSN is a conditional branch, we try to extract an
2028 implicit set out of it. */
2029 if (any_condjump_p (insn))
2031 rtx cnd = fis_get_condition (insn);
2033 if (cnd != NULL_RTX
2034 && GET_CODE (cnd) == NE
2035 && REG_P (XEXP (cnd, 0))
2036 && !reg_set_p (XEXP (cnd, 0), insn)
2037 /* The following two checks, which are also in
2038 move2add_note_store, are intended to reduce the
2039 number of calls to gen_rtx_SET to avoid memory
2040 allocation if possible. */
2041 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2042 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
2043 && CONST_INT_P (XEXP (cnd, 1)))
2045 rtx implicit_set =
2046 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
2047 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2051 /* If this is a CALL_INSN, all call used registers are stored with
2052 unknown values. */
2053 if (CALL_P (insn))
2055 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2057 if (call_used_regs[i])
2058 /* Reset the information about this register. */
2059 reg_set_luid[i] = 0;
2063 return changed;
2066 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2067 contains SET.
2068 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2069 Called from reload_cse_move2add via note_stores. */
2071 static void
2072 move2add_note_store (rtx dst, const_rtx set, void *data)
2074 rtx insn = (rtx) data;
2075 unsigned int regno = 0;
2076 unsigned int nregs = 0;
2077 unsigned int i;
2078 enum machine_mode mode = GET_MODE (dst);
2080 if (GET_CODE (dst) == SUBREG)
2082 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
2083 GET_MODE (SUBREG_REG (dst)),
2084 SUBREG_BYTE (dst),
2085 GET_MODE (dst));
2086 nregs = subreg_nregs (dst);
2087 dst = SUBREG_REG (dst);
2090 /* Some targets do argument pushes without adding REG_INC notes. */
2092 if (MEM_P (dst))
2094 dst = XEXP (dst, 0);
2095 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2096 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2097 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
2098 return;
2100 if (!REG_P (dst))
2101 return;
2103 regno += REGNO (dst);
2104 if (!nregs)
2105 nregs = hard_regno_nregs[regno][mode];
2107 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2108 && nregs == 1 && GET_CODE (set) == SET)
2110 rtx note, sym = NULL_RTX;
2111 HOST_WIDE_INT off;
2113 note = find_reg_equal_equiv_note (insn);
2114 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2116 sym = XEXP (note, 0);
2117 off = 0;
2119 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2120 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2121 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2122 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2124 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2125 off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
2128 if (sym != NULL_RTX)
2130 reg_base_reg[regno] = -1;
2131 reg_symbol_ref[regno] = sym;
2132 reg_offset[regno] = off;
2133 reg_mode[regno] = mode;
2134 reg_set_luid[regno] = move2add_luid;
2135 return;
2139 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2140 && nregs == 1 && GET_CODE (set) == SET
2141 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2142 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2144 rtx src = SET_SRC (set);
2145 rtx base_reg;
2146 HOST_WIDE_INT offset;
2147 int base_regno;
2148 /* This may be different from mode, if SET_DEST (set) is a
2149 SUBREG. */
2150 enum machine_mode dst_mode = GET_MODE (dst);
2152 switch (GET_CODE (src))
2154 case PLUS:
2155 if (REG_P (XEXP (src, 0)))
2157 base_reg = XEXP (src, 0);
2159 if (CONST_INT_P (XEXP (src, 1)))
2160 offset = INTVAL (XEXP (src, 1));
2161 else if (REG_P (XEXP (src, 1))
2162 && (reg_set_luid[REGNO (XEXP (src, 1))]
2163 > move2add_last_label_luid)
2164 && (MODES_OK_FOR_MOVE2ADD
2165 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
2167 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2168 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2169 offset = reg_offset[REGNO (XEXP (src, 1))];
2170 /* Maybe the first register is known to be a
2171 constant. */
2172 else if (reg_set_luid[REGNO (base_reg)]
2173 > move2add_last_label_luid
2174 && (MODES_OK_FOR_MOVE2ADD
2175 (dst_mode, reg_mode[REGNO (base_reg)]))
2176 && reg_base_reg[REGNO (base_reg)] < 0
2177 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2179 offset = reg_offset[REGNO (base_reg)];
2180 base_reg = XEXP (src, 1);
2182 else
2183 goto invalidate;
2185 else
2186 goto invalidate;
2188 break;
2191 goto invalidate;
2193 case REG:
2194 base_reg = src;
2195 offset = 0;
2196 break;
2198 case CONST_INT:
2199 /* Start tracking the register as a constant. */
2200 reg_base_reg[regno] = -1;
2201 reg_symbol_ref[regno] = NULL_RTX;
2202 reg_offset[regno] = INTVAL (SET_SRC (set));
2203 /* We assign the same luid to all registers set to constants. */
2204 reg_set_luid[regno] = move2add_last_label_luid + 1;
2205 reg_mode[regno] = mode;
2206 return;
2208 default:
2209 invalidate:
2210 /* Invalidate the contents of the register. */
2211 reg_set_luid[regno] = 0;
2212 return;
2215 base_regno = REGNO (base_reg);
2216 /* If information about the base register is not valid, set it
2217 up as a new base register, pretending its value is known
2218 starting from the current insn. */
2219 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
2221 reg_base_reg[base_regno] = base_regno;
2222 reg_symbol_ref[base_regno] = NULL_RTX;
2223 reg_offset[base_regno] = 0;
2224 reg_set_luid[base_regno] = move2add_luid;
2225 reg_mode[base_regno] = mode;
2227 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
2228 reg_mode[base_regno]))
2229 goto invalidate;
2231 reg_mode[regno] = mode;
2233 /* Copy base information from our base register. */
2234 reg_set_luid[regno] = reg_set_luid[base_regno];
2235 reg_base_reg[regno] = reg_base_reg[base_regno];
2236 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2238 /* Compute the sum of the offsets or constants. */
2239 reg_offset[regno] = trunc_int_for_mode (offset
2240 + reg_offset[base_regno],
2241 dst_mode);
2243 else
2245 unsigned int endregno = regno + nregs;
2247 for (i = regno; i < endregno; i++)
2248 /* Reset the information about this register. */
2249 reg_set_luid[i] = 0;
2253 static bool
2254 gate_handle_postreload (void)
2256 return (optimize > 0 && reload_completed);
2260 static unsigned int
2261 rest_of_handle_postreload (void)
2263 if (!dbg_cnt (postreload_cse))
2264 return 0;
2266 /* Do a very simple CSE pass over just the hard registers. */
2267 reload_cse_regs (get_insns ());
2268 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2269 Remove any EH edges associated with them. */
2270 if (cfun->can_throw_non_call_exceptions)
2271 purge_all_dead_edges ();
2273 return 0;
2276 struct rtl_opt_pass pass_postreload_cse =
2279 RTL_PASS,
2280 "postreload", /* name */
2281 gate_handle_postreload, /* gate */
2282 rest_of_handle_postreload, /* execute */
2283 NULL, /* sub */
2284 NULL, /* next */
2285 0, /* static_pass_number */
2286 TV_RELOAD_CSE_REGS, /* tv_id */
2287 0, /* properties_required */
2288 0, /* properties_provided */
2289 0, /* properties_destroyed */
2290 0, /* todo_flags_start */
2291 TODO_df_finish | TODO_verify_rtl_sharing |
2292 0 /* todo_flags_finish */