1 /* { dg-require-effective-target vect_int } */
9 unsigned int in
[N
] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
11 __attribute__ ((noinline
)) int
12 main1 (unsigned int x
, unsigned int y
, unsigned int *pin
, unsigned int *pout
)
15 unsigned int a0
, a1
, a2
, a3
;
17 /* pin and pout may alias. But since all the loads are before the first
18 store the basic block is vectorizable. */
30 __asm__
volatile ("" : : : "memory");
33 if (out
[0] != (in
[0] + 23) * x
34 || out
[1] != (in
[1] + 142) * y
35 || out
[2] != (in
[2] + 2) * x
36 || out
[3] != (in
[3] + 31) * y
)
46 main1 (2, 3, &in
[0], &out
[0]);
51 /* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_hw_misalign } } } */