Tighten condition in vect/pr85586.c (PR 85654)
[official-gcc.git] / gcc / testsuite / gcc.dg / combine_ashiftrt_1.c
blobf4e53c83d67fdc17313376ba3177508300aba8a6
1 /* Target architectures which have been found to produce the expected RTL
2 (neg:DI (ge:DI ...)) when compiling for LP64. */
3 /* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* ia64-*-* powerpc*-*-* sparc*-*-* x86_64-*-* } } */
4 /* { dg-require-effective-target lp64 } */
5 /* { dg-options "-O2 -fdump-rtl-combine-all" } */
7 typedef long long int int64_t;
9 int64_t
10 foo (int64_t a)
12 return (~a) >> 63;
15 /* The combine phase will try to combine not & ashiftrt, and
16 combine_simplify_rtx should transform (ashiftrt (not x) 63)
17 to (not (ashiftrt x 63)) and then to (neg (ge x 0)). We look for
18 the *attempt* to match this RTL pattern, regardless of whether an
19 actual insn may be found on the platform. */
20 /* { dg-final { scan-rtl-dump "\\(neg:DI \\(ge:DI" "combine" } } */