gcc/testsuite/gcc.dg/arm-mmx-1.c

   1 /* Verify that if IP is saved to ensure stack alignment, we don't load
   2    it into sp.  */
   3 /* { dg-do compile } */
   4 /* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */
   5 /* { dg-skip-if "" { *-*-* } { "-mfloat-abi=softfp" } { "" } } */
   6 /* { dg-require-effective-target arm32 } */
   7 /* { dg-final { scan-assembler "ldmfd\[         ]sp!.*ip,\[ ]*pc" } } */
   8
   9 /* This function uses all the call-saved registers, namely r4, r5, r6,
  10    r7, r8, r9, sl, fp.  Since we also save lr, that leaves an odd
  11    number of registers, and the compiler will push ip to align the
  12    stack.  Make sure that we restore ip into ip, not into sp as is
  13    done when using a frame pointer.  The -mno-apcs-frame option
  14    permits the frame pointer to be used as an ordinary register.  */
  15
  16 void
  17 foo(void)
  18 {
  19   __asm volatile ("" : : :
  20                   "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr");
  21 }