gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #ifdef __STDC__
  79 #include <stdarg.h>
  80 #else
  81 #include <varargs.h>
  82 #endif
  83
  84 /* Must precede rtl.h for FFS.  */
  85 #include <stdio.h>
  86
  87 #include "rtl.h"
  88 #include "flags.h"
  89 #include "regs.h"
  90 #include "hard-reg-set.h"
  91 #include "expr.h"
  92 #include "basic-block.h"
  93 #include "insn-config.h"
  94 #include "insn-flags.h"
  95 #include "insn-codes.h"
  96 #include "insn-attr.h"
  97 #include "recog.h"
  98 #include "real.h"
  99
 100 /* It is not safe to use ordinary gen_lowpart in combine.
 101    Use gen_lowpart_for_combine instead.  See comments there.  */
 102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
 103
 104 /* Number of attempts to combine instructions in this function.  */
 105
 106 static int combine_attempts;
 107
 108 /* Number of attempts that got as far as substitution in this function.  */
 109
 110 static int combine_merges;
 111
 112 /* Number of instructions combined with added SETs in this function.  */
 113
 114 static int combine_extras;
 115
 116 /* Number of instructions combined in this function.  */
 117
 118 static int combine_successes;
 119
 120 /* Totals over entire compilation.  */
 121
 122 static int total_attempts, total_merges, total_extras, total_successes;
 123
 124 /* Define a default value for REVERSIBLE_CC_MODE.
 125    We can never assume that a condition code mode is safe to reverse unless
 126    the md tells us so.  */
 127 #ifndef REVERSIBLE_CC_MODE
 128 #define REVERSIBLE_CC_MODE(MODE) 0
 129 #endif
 130 \f
 131 /* Vector mapping INSN_UIDs to cuids.
 132    The cuids are like uids but increase monotonically always.
 133    Combine always uses cuids so that it can compare them.
 134    But actually renumbering the uids, which we used to do,
 135    proves to be a bad idea because it makes it hard to compare
 136    the dumps produced by earlier passes with those from later passes.  */
 137
 138 static int *uid_cuid;
 139 static int max_uid_cuid;
 140
 141 /* Get the cuid of an insn.  */
 142
 143 #define INSN_CUID(INSN) \
 144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 145
 146 /* Maximum register number, which is the size of the tables below.  */
 147
 148 static int combine_max_regno;
 149
 150 /* Record last point of death of (hard or pseudo) register n.  */
 151
 152 static rtx *reg_last_death;
 153
 154 /* Record last point of modification of (hard or pseudo) register n.  */
 155
 156 static rtx *reg_last_set;
 157
 158 /* Record the cuid of the last insn that invalidated memory
 159    (anything that writes memory, and subroutine calls, but not pushes).  */
 160
 161 static int mem_last_set;
 162
 163 /* Record the cuid of the last CALL_INSN
 164    so we can tell whether a potential combination crosses any calls.  */
 165
 166 static int last_call_cuid;
 167
 168 /* When `subst' is called, this is the insn that is being modified
 169    (by combining in a previous insn).  The PATTERN of this insn
 170    is still the old pattern partially modified and it should not be
 171    looked at, but this may be used to examine the successors of the insn
 172    to judge whether a simplification is valid.  */
 173
 174 static rtx subst_insn;
 175
 176 /* This is an insn that belongs before subst_insn, but is not currently
 177    on the insn chain.  */
 178
 179 static rtx subst_prev_insn;
 180
 181 /* This is the lowest CUID that `subst' is currently dealing with.
 182    get_last_value will not return a value if the register was set at or
 183    after this CUID.  If not for this mechanism, we could get confused if
 184    I2 or I1 in try_combine were an insn that used the old value of a register
 185    to obtain a new value.  In that case, we might erroneously get the
 186    new value of the register when we wanted the old one.  */
 187
 188 static int subst_low_cuid;
 189
 190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 191    must consider all these registers to be always live.  */
 192
 193 static HARD_REG_SET newpat_used_regs;
 194
 195 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 196    insn is the earlier than I2 or I3, combine should rescan starting at
 197    that location.  */
 198
 199 static rtx added_links_insn;
 200
 201 /* Basic block number of the block in which we are performing combines.  */
 202 static int this_basic_block;
 203 \f
 204 /* The next group of arrays allows the recording of the last value assigned
 205    to (hard or pseudo) register n.  We use this information to see if a
 206    operation being processed is redundant given a prior operation performed
 207    on the register.  For example, an `and' with a constant is redundant if
 208    all the zero bits are already known to be turned off.
 209
 210    We use an approach similar to that used by cse, but change it in the
 211    following ways:
 212
 213    (1) We do not want to reinitialize at each label.
 214    (2) It is useful, but not critical, to know the actual value assigned
 215        to a register.  Often just its form is helpful.
 216
 217    Therefore, we maintain the following arrays:
 218
 219    reg_last_set_value           the last value assigned
 220    reg_last_set_label           records the value of label_tick when the
 221                                 register was assigned
 222    reg_last_set_table_tick      records the value of label_tick when a
 223                                 value using the register is assigned
 224    reg_last_set_invalid         set to non-zero when it is not valid
 225                                 to use the value of this register in some
 226                                 register's value
 227
 228    To understand the usage of these tables, it is important to understand
 229    the distinction between the value in reg_last_set_value being valid
 230    and the register being validly contained in some other expression in the
 231    table.
 232
 233    Entry I in reg_last_set_value is valid if it is non-zero, and either
 234    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 235
 236    Register I may validly appear in any expression returned for the value
 237    of another register if reg_n_sets[i] is 1.  It may also appear in the
 238    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 239    reg_last_set_invalid[j] is zero.
 240
 241    If an expression is found in the table containing a register which may
 242    not validly appear in an expression, the register is replaced by
 243    something that won't match, (clobber (const_int 0)).
 244
 245    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 246    to and reg_last_set_table_tick[i] == label_tick.  */
 247
 248 /* Record last value assigned to (hard or pseudo) register n.  */
 249
 250 static rtx *reg_last_set_value;
 251
 252 /* Record the value of label_tick when the value for register n is placed in
 253    reg_last_set_value[n].  */
 254
 255 static int *reg_last_set_label;
 256
 257 /* Record the value of label_tick when an expression involving register n
 258    is placed in reg_last_set_value.  */
 259
 260 static int *reg_last_set_table_tick;
 261
 262 /* Set non-zero if references to register n in expressions should not be
 263    used.  */
 264
 265 static char *reg_last_set_invalid;
 266
 267 /* Incremented for each label.  */
 268
 269 static int label_tick;
 270
 271 /* Some registers that are set more than once and used in more than one
 272    basic block are nevertheless always set in similar ways.  For example,
 273    a QImode register may be loaded from memory in two places on a machine
 274    where byte loads zero extend.
 275
 276    We record in the following array what we know about the nonzero
 277    bits of a register, specifically which bits are known to be zero.
 278
 279    If an entry is zero, it means that we don't know anything special.  */
 280
 281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 282
 283 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 284    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 285
 286 static enum machine_mode nonzero_bits_mode;
 287
 288 /* Nonzero if we know that a register has some leading bits that are always
 289    equal to the sign bit.  */
 290
 291 static char *reg_sign_bit_copies;
 292
 293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 294    It is zero while computing them and after combine has completed.  This
 295    former test prevents propagating values based on previously set values,
 296    which can be incorrect if a variable is modified in a loop.  */
 297
 298 static int nonzero_sign_valid;
 299
 300 /* These arrays are maintained in parallel with reg_last_set_value
 301    and are used to store the mode in which the register was last set,
 302    the bits that were known to be zero when it was last set, and the
 303    number of sign bits copies it was known to have when it was last set.  */
 304
 305 static enum machine_mode *reg_last_set_mode;
 306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 307 static char *reg_last_set_sign_bit_copies;
 308 \f
 309 /* Record one modification to rtl structure
 310    to be undone by storing old_contents into *where.
 311    is_int is 1 if the contents are an int.  */
 312
 313 struct undo
 314 {
 315   struct undo *next;
 316   int is_int;
 317   union {rtx r; int i;} old_contents;
 318   union {rtx *r; int *i;} where;
 319 };
 320
 321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 322    num_undo says how many are currently recorded.
 323
 324    storage is nonzero if we must undo the allocation of new storage.
 325    The value of storage is what to pass to obfree.
 326
 327    other_insn is nonzero if we have modified some other insn in the process
 328    of working on subst_insn.  It must be verified too.
 329
 330    previous_undos is the value of undobuf.undos when we started processing
 331    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 332    from the previous expression.  Doing so can produce circular rtl
 333    structures.  */
 334
 335 struct undobuf
 336 {
 337   char *storage;
 338   struct undo *undos;
 339   struct undo *frees;
 340   struct undo *previous_undos;
 341   rtx other_insn;
 342 };
 343
 344 static struct undobuf undobuf;
 345
 346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 347    insn.  The substitution can be undone by undo_all.  If INTO is already
 348    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 349    also call SUBST, we have to compute it before we put anything into
 350    the undo table.  */
 351
 352 #define SUBST(INTO, NEWVAL)  \
 353  do { rtx _new = (NEWVAL);                                      \
 354       struct undo *_buf;                                        \
 355                                                                 \
 356       if (undobuf.frees)                                        \
 357         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 358       else                                                      \
 359         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 360                                                                 \
 361       _buf->is_int = 0;                                         \
 362       _buf->where.r = &INTO;                                    \
 363       _buf->old_contents.r = INTO;                              \
 364       INTO = _new;                                              \
 365       if (_buf->old_contents.r == INTO)                         \
 366         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 367       else                                                      \
 368         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 369     } while (0)
 370
 371 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 372    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 373    not safe.  */
 374
 375 #define SUBST_INT(INTO, NEWVAL)  \
 376  do { struct undo *_buf;                                        \
 377                                                                 \
 378       if (undobuf.frees)                                        \
 379         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 380       else                                                      \
 381         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 382                                                                 \
 383       _buf->is_int = 1;                                         \
 384       _buf->where.i = (int *) &INTO;                            \
 385       _buf->old_contents.i = INTO;                              \
 386       INTO = NEWVAL;                                            \
 387       if (_buf->old_contents.i == INTO)                         \
 388         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 389       else                                                      \
 390         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 391      } while (0)
 392
 393 /* Number of times the pseudo being substituted for
 394    was found and replaced.  */
 395
 396 static int n_occurrences;
 397
 398 static void init_reg_last_arrays        PROTO((void));
 399 static void setup_incoming_promotions   PROTO((void));
 400 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
 401 static int can_combine_p        PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
 402 static int combinable_i3pat     PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
 403 static rtx try_combine          PROTO((rtx, rtx, rtx));
 404 static void undo_all            PROTO((void));
 405 static rtx *find_split_point    PROTO((rtx *, rtx));
 406 static rtx subst                PROTO((rtx, rtx, rtx, int, int));
 407 static rtx simplify_rtx         PROTO((rtx, enum machine_mode, int, int));
 408 static rtx simplify_if_then_else  PROTO((rtx));
 409 static rtx simplify_set         PROTO((rtx));
 410 static rtx simplify_logical     PROTO((rtx, int));
 411 static rtx expand_compound_operation  PROTO((rtx));
 412 static rtx expand_field_assignment  PROTO((rtx));
 413 static rtx make_extraction      PROTO((enum machine_mode, rtx, int, rtx, int,
 414                                        int, int, int));
 415 static rtx extract_left_shift   PROTO((rtx, int));
 416 static rtx make_compound_operation  PROTO((rtx, enum rtx_code));
 417 static int get_pos_from_mask    PROTO((unsigned HOST_WIDE_INT, int *));
 418 static rtx force_to_mode        PROTO((rtx, enum machine_mode,
 419                                        unsigned HOST_WIDE_INT, rtx, int));
 420 static rtx if_then_else_cond    PROTO((rtx, rtx *, rtx *));
 421 static rtx known_cond           PROTO((rtx, enum rtx_code, rtx, rtx));
 422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
 423 static rtx make_field_assignment  PROTO((rtx));
 424 static rtx apply_distributive_law  PROTO((rtx));
 425 static rtx simplify_and_const_int  PROTO((rtx, enum machine_mode, rtx,
 426                                           unsigned HOST_WIDE_INT));
 427 static unsigned HOST_WIDE_INT nonzero_bits  PROTO((rtx, enum machine_mode));
 428 static int num_sign_bit_copies  PROTO((rtx, enum machine_mode));
 429 static int merge_outer_ops      PROTO((enum rtx_code *, HOST_WIDE_INT *,
 430                                        enum rtx_code, HOST_WIDE_INT,
 431                                        enum machine_mode, int *));
 432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
 433                                        rtx, int));
 434 static int recog_for_combine    PROTO((rtx *, rtx, rtx *, int *));
 435 static rtx gen_lowpart_for_combine  PROTO((enum machine_mode, rtx));
 436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
 437                                   ...));
 438 static rtx gen_binary           PROTO((enum rtx_code, enum machine_mode,
 439                                        rtx, rtx));
 440 static rtx gen_unary            PROTO((enum rtx_code, enum machine_mode,
 441                                        enum machine_mode, rtx));
 442 static enum rtx_code simplify_comparison  PROTO((enum rtx_code, rtx *, rtx *));
 443 static int reversible_comparison_p  PROTO((rtx));
 444 static void update_table_tick   PROTO((rtx));
 445 static void record_value_for_reg  PROTO((rtx, rtx, rtx));
 446 static void record_dead_and_set_regs_1  PROTO((rtx, rtx));
 447 static void record_dead_and_set_regs  PROTO((rtx));
 448 static int get_last_value_validate  PROTO((rtx *, rtx, int, int));
 449 static rtx get_last_value       PROTO((rtx));
 450 static int use_crosses_set_p    PROTO((rtx, int));
 451 static void reg_dead_at_p_1     PROTO((rtx, rtx));
 452 static int reg_dead_at_p        PROTO((rtx, rtx));
 453 static void move_deaths         PROTO((rtx, rtx, int, rtx, rtx *));
 454 static int reg_bitfield_target_p  PROTO((rtx, rtx));
 455 static void distribute_notes    PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 456 static void distribute_links    PROTO((rtx));
 457 static void mark_used_regs_combine PROTO((rtx));
 458 static int insn_cuid            PROTO((rtx));
 459 \f
 460 /* Main entry point for combiner.  F is the first insn of the function.
 461    NREGS is the first unused pseudo-reg number.  */
 462
 463 void
 464 combine_instructions (f, nregs)
 465      rtx f;
 466      int nregs;
 467 {
 468   register rtx insn, next, prev;
 469   register int i;
 470   register rtx links, nextlinks;
 471
 472   combine_attempts = 0;
 473   combine_merges = 0;
 474   combine_extras = 0;
 475   combine_successes = 0;
 476   undobuf.undos = undobuf.previous_undos = 0;
 477
 478   combine_max_regno = nregs;
 479
 480   reg_nonzero_bits
 481     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 482   reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
 483
 484   bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 485   bzero (reg_sign_bit_copies, nregs * sizeof (char));
 486
 487   reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
 488   reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
 489   reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
 490   reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
 491   reg_last_set_label = (int *) alloca (nregs * sizeof (int));
 492   reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
 493   reg_last_set_mode
 494     = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
 495   reg_last_set_nonzero_bits
 496     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 497   reg_last_set_sign_bit_copies
 498     = (char *) alloca (nregs * sizeof (char));
 499
 500   init_reg_last_arrays ();
 501
 502   init_recog_no_volatile ();
 503
 504   /* Compute maximum uid value so uid_cuid can be allocated.  */
 505
 506   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 507     if (INSN_UID (insn) > i)
 508       i = INSN_UID (insn);
 509
 510   uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
 511   max_uid_cuid = i;
 512
 513   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 514
 515   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 516      when, for example, we have j <<= 1 in a loop.  */
 517
 518   nonzero_sign_valid = 0;
 519
 520   /* Compute the mapping from uids to cuids.
 521      Cuids are numbers assigned to insns, like uids,
 522      except that cuids increase monotonically through the code.
 523
 524      Scan all SETs and see if we can deduce anything about what
 525      bits are known to be zero for some registers and how many copies
 526      of the sign bit are known to exist for those registers.
 527
 528      Also set any known values so that we can use it while searching
 529      for what bits are known to be set.  */
 530
 531   label_tick = 1;
 532
 533   /* We need to initialize it here, because record_dead_and_set_regs may call
 534      get_last_value.  */
 535   subst_prev_insn = NULL_RTX;
 536
 537   setup_incoming_promotions ();
 538
 539   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 540     {
 541       uid_cuid[INSN_UID (insn)] = ++i;
 542       subst_low_cuid = i;
 543       subst_insn = insn;
 544
 545       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 546         {
 547           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
 548           record_dead_and_set_regs (insn);
 549
 550 #ifdef AUTO_INC_DEC
 551           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 552             if (REG_NOTE_KIND (links) == REG_INC)
 553               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
 554 #endif
 555         }
 556
 557       if (GET_CODE (insn) == CODE_LABEL)
 558         label_tick++;
 559     }
 560
 561   nonzero_sign_valid = 1;
 562
 563   /* Now scan all the insns in forward order.  */
 564
 565   this_basic_block = -1;
 566   label_tick = 1;
 567   last_call_cuid = 0;
 568   mem_last_set = 0;
 569   init_reg_last_arrays ();
 570   setup_incoming_promotions ();
 571
 572   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 573     {
 574       next = 0;
 575
 576       /* If INSN starts a new basic block, update our basic block number.  */
 577       if (this_basic_block + 1 < n_basic_blocks
 578           && basic_block_head[this_basic_block + 1] == insn)
 579         this_basic_block++;
 580
 581       if (GET_CODE (insn) == CODE_LABEL)
 582         label_tick++;
 583
 584       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 585         {
 586           /* Try this insn with each insn it links back to.  */
 587
 588           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 589             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 590               goto retry;
 591
 592           /* Try each sequence of three linked insns ending with this one.  */
 593
 594           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 595             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 596                  nextlinks = XEXP (nextlinks, 1))
 597               if ((next = try_combine (insn, XEXP (links, 0),
 598                                        XEXP (nextlinks, 0))) != 0)
 599                 goto retry;
 600
 601 #ifdef HAVE_cc0
 602           /* Try to combine a jump insn that uses CC0
 603              with a preceding insn that sets CC0, and maybe with its
 604              logical predecessor as well.
 605              This is how we make decrement-and-branch insns.
 606              We need this special code because data flow connections
 607              via CC0 do not get entered in LOG_LINKS.  */
 608
 609           if (GET_CODE (insn) == JUMP_INSN
 610               && (prev = prev_nonnote_insn (insn)) != 0
 611               && GET_CODE (prev) == INSN
 612               && sets_cc0_p (PATTERN (prev)))
 613             {
 614               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 615                 goto retry;
 616
 617               for (nextlinks = LOG_LINKS (prev); nextlinks;
 618                    nextlinks = XEXP (nextlinks, 1))
 619                 if ((next = try_combine (insn, prev,
 620                                          XEXP (nextlinks, 0))) != 0)
 621                   goto retry;
 622             }
 623
 624           /* Do the same for an insn that explicitly references CC0.  */
 625           if (GET_CODE (insn) == INSN
 626               && (prev = prev_nonnote_insn (insn)) != 0
 627               && GET_CODE (prev) == INSN
 628               && sets_cc0_p (PATTERN (prev))
 629               && GET_CODE (PATTERN (insn)) == SET
 630               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 631             {
 632               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 633                 goto retry;
 634
 635               for (nextlinks = LOG_LINKS (prev); nextlinks;
 636                    nextlinks = XEXP (nextlinks, 1))
 637                 if ((next = try_combine (insn, prev,
 638                                          XEXP (nextlinks, 0))) != 0)
 639                   goto retry;
 640             }
 641
 642           /* Finally, see if any of the insns that this insn links to
 643              explicitly references CC0.  If so, try this insn, that insn,
 644              and its predecessor if it sets CC0.  */
 645           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 646             if (GET_CODE (XEXP (links, 0)) == INSN
 647                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 648                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 649                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 650                 && GET_CODE (prev) == INSN
 651                 && sets_cc0_p (PATTERN (prev))
 652                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 653               goto retry;
 654 #endif
 655
 656           /* Try combining an insn with two different insns whose results it
 657              uses.  */
 658           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 659             for (nextlinks = XEXP (links, 1); nextlinks;
 660                  nextlinks = XEXP (nextlinks, 1))
 661               if ((next = try_combine (insn, XEXP (links, 0),
 662                                        XEXP (nextlinks, 0))) != 0)
 663                 goto retry;
 664
 665           if (GET_CODE (insn) != NOTE)
 666             record_dead_and_set_regs (insn);
 667
 668         retry:
 669           ;
 670         }
 671     }
 672
 673   total_attempts += combine_attempts;
 674   total_merges += combine_merges;
 675   total_extras += combine_extras;
 676   total_successes += combine_successes;
 677
 678   nonzero_sign_valid = 0;
 679 }
 680
 681 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 682
 683 static void
 684 init_reg_last_arrays ()
 685 {
 686   int nregs = combine_max_regno;
 687
 688   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 689   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 690   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 691   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 692   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 693   bzero (reg_last_set_invalid, nregs * sizeof (char));
 694   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 695   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 696   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 697 }
 698 \f
 699 /* Set up any promoted values for incoming argument registers.  */
 700
 701 static void
 702 setup_incoming_promotions ()
 703 {
 704 #ifdef PROMOTE_FUNCTION_ARGS
 705   int regno;
 706   rtx reg;
 707   enum machine_mode mode;
 708   int unsignedp;
 709   rtx first = get_insns ();
 710
 711   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 712     if (FUNCTION_ARG_REGNO_P (regno)
 713         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 714       record_value_for_reg (reg, first,
 715                             gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
 716                                      GET_MODE (reg),
 717                                      gen_rtx (CLOBBER, mode, const0_rtx)));
 718 #endif
 719 }
 720 \f
 721 /* Called via note_stores.  If X is a pseudo that is narrower than
 722    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 723
 724    If we are setting only a portion of X and we can't figure out what
 725    portion, assume all bits will be used since we don't know what will
 726    be happening.
 727
 728    Similarly, set how many bits of X are known to be copies of the sign bit
 729    at all locations in the function.  This is the smallest number implied
 730    by any set of X.  */
 731
 732 static void
 733 set_nonzero_bits_and_sign_copies (x, set)
 734      rtx x;
 735      rtx set;
 736 {
 737   int num;
 738
 739   if (GET_CODE (x) == REG
 740       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 741       /* If this register is undefined at the start of the file, we can't
 742          say what its contents were.  */
 743       && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
 744       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 745     {
 746       if (set == 0 || GET_CODE (set) == CLOBBER)
 747         {
 748           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 749           reg_sign_bit_copies[REGNO (x)] = 1;
 750           return;
 751         }
 752
 753       /* If this is a complex assignment, see if we can convert it into a
 754          simple assignment.  */
 755       set = expand_field_assignment (set);
 756
 757       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 758          set what we know about X.  */
 759
 760       if (SET_DEST (set) == x
 761           || (GET_CODE (SET_DEST (set)) == SUBREG
 762               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 763                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 764               && SUBREG_REG (SET_DEST (set)) == x))
 765         {
 766           rtx src = SET_SRC (set);
 767
 768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 769           /* If X is narrower than a word and SRC is a non-negative
 770              constant that would appear negative in the mode of X,
 771              sign-extend it for use in reg_nonzero_bits because some
 772              machines (maybe most) will actually do the sign-extension
 773              and this is the conservative approach.
 774
 775              ??? For 2.5, try to tighten up the MD files in this regard
 776              instead of this kludge.  */
 777
 778           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 779               && GET_CODE (src) == CONST_INT
 780               && INTVAL (src) > 0
 781               && 0 != (INTVAL (src)
 782                        & ((HOST_WIDE_INT) 1
 783                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 784             src = GEN_INT (INTVAL (src)
 785                            | ((HOST_WIDE_INT) (-1)
 786                               << GET_MODE_BITSIZE (GET_MODE (x))));
 787 #endif
 788
 789           reg_nonzero_bits[REGNO (x)]
 790             |= nonzero_bits (src, nonzero_bits_mode);
 791           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 792           if (reg_sign_bit_copies[REGNO (x)] == 0
 793               || reg_sign_bit_copies[REGNO (x)] > num)
 794             reg_sign_bit_copies[REGNO (x)] = num;
 795         }
 796       else
 797         {
 798           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 799           reg_sign_bit_copies[REGNO (x)] = 1;
 800         }
 801     }
 802 }
 803 \f
 804 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 805    insns that were previously combined into I3 or that will be combined
 806    into the merger of INSN and I3.
 807
 808    Return 0 if the combination is not allowed for any reason.
 809
 810    If the combination is allowed, *PDEST will be set to the single
 811    destination of INSN and *PSRC to the single source, and this function
 812    will return 1.  */
 813
 814 static int
 815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 816      rtx insn;
 817      rtx i3;
 818      rtx pred, succ;
 819      rtx *pdest, *psrc;
 820 {
 821   int i;
 822   rtx set = 0, src, dest;
 823   rtx p, link;
 824   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 825                               && next_active_insn (succ) == i3)
 826                       : next_active_insn (insn) == i3);
 827
 828   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 829      or a PARALLEL consisting of such a SET and CLOBBERs.
 830
 831      If INSN has CLOBBER parallel parts, ignore them for our processing.
 832      By definition, these happen during the execution of the insn.  When it
 833      is merged with another insn, all bets are off.  If they are, in fact,
 834      needed and aren't also supplied in I3, they may be added by
 835      recog_for_combine.  Otherwise, it won't match.
 836
 837      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 838      note.
 839
 840      Get the source and destination of INSN.  If more than one, can't
 841      combine.  */
 842
 843   if (GET_CODE (PATTERN (insn)) == SET)
 844     set = PATTERN (insn);
 845   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 846            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 847     {
 848       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 849         {
 850           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 851
 852           switch (GET_CODE (elt))
 853             {
 854               /* We can ignore CLOBBERs.  */
 855             case CLOBBER:
 856               break;
 857
 858             case SET:
 859               /* Ignore SETs whose result isn't used but not those that
 860                  have side-effects.  */
 861               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 862                   && ! side_effects_p (elt))
 863                 break;
 864
 865               /* If we have already found a SET, this is a second one and
 866                  so we cannot combine with this insn.  */
 867               if (set)
 868                 return 0;
 869
 870               set = elt;
 871               break;
 872
 873             default:
 874               /* Anything else means we can't combine.  */
 875               return 0;
 876             }
 877         }
 878
 879       if (set == 0
 880           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 881              so don't do anything with it.  */
 882           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
 883         return 0;
 884     }
 885   else
 886     return 0;
 887
 888   if (set == 0)
 889     return 0;
 890
 891   set = expand_field_assignment (set);
 892   src = SET_SRC (set), dest = SET_DEST (set);
 893
 894   /* Don't eliminate a store in the stack pointer.  */
 895   if (dest == stack_pointer_rtx
 896       /* If we couldn't eliminate a field assignment, we can't combine.  */
 897       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
 898       /* Don't combine with an insn that sets a register to itself if it has
 899          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
 900       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
 901       /* Can't merge a function call.  */
 902       || GET_CODE (src) == CALL
 903       /* Don't eliminate a function call argument.  */
 904       || (GET_CODE (i3) == CALL_INSN
 905           && (find_reg_fusage (i3, USE, dest)
 906               || (GET_CODE (dest) == REG
 907                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
 908                   && global_regs[REGNO (dest)])))
 909       /* Don't substitute into an incremented register.  */
 910       || FIND_REG_INC_NOTE (i3, dest)
 911       || (succ && FIND_REG_INC_NOTE (succ, dest))
 912       /* Don't combine the end of a libcall into anything.  */
 913       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
 914       /* Make sure that DEST is not used after SUCC but before I3.  */
 915       || (succ && ! all_adjacent
 916           && reg_used_between_p (dest, succ, i3))
 917       /* Make sure that the value that is to be substituted for the register
 918          does not use any registers whose values alter in between.  However,
 919          If the insns are adjacent, a use can't cross a set even though we
 920          think it might (this can happen for a sequence of insns each setting
 921          the same destination; reg_last_set of that register might point to
 922          a NOTE).  If INSN has a REG_EQUIV note, the register is always
 923          equivalent to the memory so the substitution is valid even if there
 924          are intervening stores.  Also, don't move a volatile asm or
 925          UNSPEC_VOLATILE across any other insns.  */
 926       || (! all_adjacent
 927           && (((GET_CODE (src) != MEM
 928                 || ! find_reg_note (insn, REG_EQUIV, src))
 929                && use_crosses_set_p (src, INSN_CUID (insn)))
 930               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
 931               || GET_CODE (src) == UNSPEC_VOLATILE))
 932       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
 933          better register allocation by not doing the combine.  */
 934       || find_reg_note (i3, REG_NO_CONFLICT, dest)
 935       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
 936       /* Don't combine across a CALL_INSN, because that would possibly
 937          change whether the life span of some REGs crosses calls or not,
 938          and it is a pain to update that information.
 939          Exception: if source is a constant, moving it later can't hurt.
 940          Accept that special case, because it helps -fforce-addr a lot.  */
 941       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
 942     return 0;
 943
 944   /* DEST must either be a REG or CC0.  */
 945   if (GET_CODE (dest) == REG)
 946     {
 947       /* If register alignment is being enforced for multi-word items in all
 948          cases except for parameters, it is possible to have a register copy
 949          insn referencing a hard register that is not allowed to contain the
 950          mode being copied and which would not be valid as an operand of most
 951          insns.  Eliminate this problem by not combining with such an insn.
 952
 953          Also, on some machines we don't want to extend the life of a hard
 954          register.
 955
 956          This is the same test done in can_combine except that we don't test
 957          if SRC is a CALL operation to permit a hard register with
 958          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
 959          into account.  */
 960
 961       if (GET_CODE (src) == REG
 962           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
 963                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
 964               /* Don't extend the life of a hard register unless it is
 965                  user variable (if we have few registers) or it can't
 966                  fit into the desired register (meaning something special
 967                  is going on).
 968                  Also avoid substituting a return register into I3, because
 969                  reload can't handle a conflict with constraints of other
 970                  inputs.  */
 971               || (REGNO (src) < FIRST_PSEUDO_REGISTER
 972                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
 973                       || (SMALL_REGISTER_CLASSES
 974                           && ((! all_adjacent && ! REG_USERVAR_P (src))
 975                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
 976                                   && ! REG_USERVAR_P (src))))))))
 977         return 0;
 978     }
 979   else if (GET_CODE (dest) != CC0)
 980     return 0;
 981
 982   /* Don't substitute for a register intended as a clobberable operand.
 983      Similarly, don't substitute an expression containing a register that
 984      will be clobbered in I3.  */
 985   if (GET_CODE (PATTERN (i3)) == PARALLEL)
 986     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
 987       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
 988           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
 989                                        src)
 990               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
 991         return 0;
 992
 993   /* If INSN contains anything volatile, or is an `asm' (whether volatile
 994      or not), reject, unless nothing volatile comes between it and I3,
 995      with the exception of SUCC.  */
 996
 997   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
 998     for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
 999       if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1000           && p != succ && volatile_refs_p (PATTERN (p)))
1001         return 0;
1002
1003   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1004      to be an explicit register variable, and was chosen for a reason.  */
1005
1006   if (GET_CODE (src) == ASM_OPERANDS
1007       && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1008     return 0;
1009
1010   /* If there are any volatile insns between INSN and I3, reject, because
1011      they might affect machine state.  */
1012
1013   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1014     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1015         && p != succ && volatile_insn_p (PATTERN (p)))
1016       return 0;
1017
1018   /* If INSN or I2 contains an autoincrement or autodecrement,
1019      make sure that register is not used between there and I3,
1020      and not already used in I3 either.
1021      Also insist that I3 not be a jump; if it were one
1022      and the incremented register were spilled, we would lose.  */
1023
1024 #ifdef AUTO_INC_DEC
1025   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1026     if (REG_NOTE_KIND (link) == REG_INC
1027         && (GET_CODE (i3) == JUMP_INSN
1028             || reg_used_between_p (XEXP (link, 0), insn, i3)
1029             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1030       return 0;
1031 #endif
1032
1033 #ifdef HAVE_cc0
1034   /* Don't combine an insn that follows a CC0-setting insn.
1035      An insn that uses CC0 must not be separated from the one that sets it.
1036      We do, however, allow I2 to follow a CC0-setting insn if that insn
1037      is passed as I1; in that case it will be deleted also.
1038      We also allow combining in this case if all the insns are adjacent
1039      because that would leave the two CC0 insns adjacent as well.
1040      It would be more logical to test whether CC0 occurs inside I1 or I2,
1041      but that would be much slower, and this ought to be equivalent.  */
1042
1043   p = prev_nonnote_insn (insn);
1044   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1045       && ! all_adjacent)
1046     return 0;
1047 #endif
1048
1049   /* If we get here, we have passed all the tests and the combination is
1050      to be allowed.  */
1051
1052   *pdest = dest;
1053   *psrc = src;
1054
1055   return 1;
1056 }
1057 \f
1058 /* LOC is the location within I3 that contains its pattern or the component
1059    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1060
1061    One problem is if I3 modifies its output, as opposed to replacing it
1062    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1063    so would produce an insn that is not equivalent to the original insns.
1064
1065    Consider:
1066
1067          (set (reg:DI 101) (reg:DI 100))
1068          (set (subreg:SI (reg:DI 101) 0) <foo>)
1069
1070    This is NOT equivalent to:
1071
1072          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1073                     (set (reg:DI 101) (reg:DI 100))])
1074
1075    Not only does this modify 100 (in which case it might still be valid
1076    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1077
1078    We can also run into a problem if I2 sets a register that I1
1079    uses and I1 gets directly substituted into I3 (not via I2).  In that
1080    case, we would be getting the wrong value of I2DEST into I3, so we
1081    must reject the combination.  This case occurs when I2 and I1 both
1082    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1083    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1084    of a SET must prevent combination from occurring.
1085
1086    On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1087    if the destination of a SET is a hard register that isn't a user
1088    variable.
1089
1090    Before doing the above check, we first try to expand a field assignment
1091    into a set of logical operations.
1092
1093    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1094    we place a register that is both set and used within I3.  If more than one
1095    such register is detected, we fail.
1096
1097    Return 1 if the combination is valid, zero otherwise.  */
1098
1099 static int
1100 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1101      rtx i3;
1102      rtx *loc;
1103      rtx i2dest;
1104      rtx i1dest;
1105      int i1_not_in_src;
1106      rtx *pi3dest_killed;
1107 {
1108   rtx x = *loc;
1109
1110   if (GET_CODE (x) == SET)
1111     {
1112       rtx set = expand_field_assignment (x);
1113       rtx dest = SET_DEST (set);
1114       rtx src = SET_SRC (set);
1115       rtx inner_dest = dest, inner_src = src;
1116
1117       SUBST (*loc, set);
1118
1119       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1120              || GET_CODE (inner_dest) == SUBREG
1121              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1122         inner_dest = XEXP (inner_dest, 0);
1123
1124   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1125      was added.  */
1126 #if 0
1127       while (GET_CODE (inner_src) == STRICT_LOW_PART
1128              || GET_CODE (inner_src) == SUBREG
1129              || GET_CODE (inner_src) == ZERO_EXTRACT)
1130         inner_src = XEXP (inner_src, 0);
1131
1132       /* If it is better that two different modes keep two different pseudos,
1133          avoid combining them.  This avoids producing the following pattern
1134          on a 386:
1135           (set (subreg:SI (reg/v:QI 21) 0)
1136                (lshiftrt:SI (reg/v:SI 20)
1137                    (const_int 24)))
1138          If that were made, reload could not handle the pair of
1139          reg 20/21, since it would try to get any GENERAL_REGS
1140          but some of them don't handle QImode.  */
1141
1142       if (rtx_equal_p (inner_src, i2dest)
1143           && GET_CODE (inner_dest) == REG
1144           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1145         return 0;
1146 #endif
1147
1148       /* Check for the case where I3 modifies its output, as
1149          discussed above.  */
1150       if ((inner_dest != dest
1151            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1152                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1153           /* This is the same test done in can_combine_p except that we
1154              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1155              CALL operation.
1156              Moreover, we can't test all_adjacent; we don't have to, since
1157              this instruction will stay in place, thus we are not considering
1158              to increase the lifetime of INNER_DEST.  */
1159           || (GET_CODE (inner_dest) == REG
1160               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1161               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1162                                         GET_MODE (inner_dest))
1163                  || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1164                      && ! REG_USERVAR_P (inner_dest)
1165                      && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))))
1166           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1167         return 0;
1168
1169       /* If DEST is used in I3, it is being killed in this insn,
1170          so record that for later.
1171          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1172          STACK_POINTER_REGNUM, since these are always considered to be
1173          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1174       if (pi3dest_killed && GET_CODE (dest) == REG
1175           && reg_referenced_p (dest, PATTERN (i3))
1176           && REGNO (dest) != FRAME_POINTER_REGNUM
1177 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1178           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1179 #endif
1180 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1181           && (REGNO (dest) != ARG_POINTER_REGNUM
1182               || ! fixed_regs [REGNO (dest)])
1183 #endif
1184           && REGNO (dest) != STACK_POINTER_REGNUM)
1185         {
1186           if (*pi3dest_killed)
1187             return 0;
1188
1189           *pi3dest_killed = dest;
1190         }
1191     }
1192
1193   else if (GET_CODE (x) == PARALLEL)
1194     {
1195       int i;
1196
1197       for (i = 0; i < XVECLEN (x, 0); i++)
1198         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1199                                 i1_not_in_src, pi3dest_killed))
1200           return 0;
1201     }
1202
1203   return 1;
1204 }
1205 \f
1206 /* Try to combine the insns I1 and I2 into I3.
1207    Here I1 and I2 appear earlier than I3.
1208    I1 can be zero; then we combine just I2 into I3.
1209
1210    It we are combining three insns and the resulting insn is not recognized,
1211    try splitting it into two insns.  If that happens, I2 and I3 are retained
1212    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1213    are pseudo-deleted.
1214
1215    Return 0 if the combination does not work.  Then nothing is changed.
1216    If we did the combination, return the insn at which combine should
1217    resume scanning.  */
1218
1219 static rtx
1220 try_combine (i3, i2, i1)
1221      register rtx i3, i2, i1;
1222 {
1223   /* New patterns for I3 and I3, respectively.  */
1224   rtx newpat, newi2pat = 0;
1225   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1226   int added_sets_1, added_sets_2;
1227   /* Total number of SETs to put into I3.  */
1228   int total_sets;
1229   /* Nonzero is I2's body now appears in I3.  */
1230   int i2_is_used;
1231   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1232   int insn_code_number, i2_code_number, other_code_number;
1233   /* Contains I3 if the destination of I3 is used in its source, which means
1234      that the old life of I3 is being killed.  If that usage is placed into
1235      I2 and not in I3, a REG_DEAD note must be made.  */
1236   rtx i3dest_killed = 0;
1237   /* SET_DEST and SET_SRC of I2 and I1.  */
1238   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1239   /* PATTERN (I2), or a copy of it in certain cases.  */
1240   rtx i2pat;
1241   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1242   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1243   int i1_feeds_i3 = 0;
1244   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1245   rtx new_i3_notes, new_i2_notes;
1246   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1247   int i3_subst_into_i2 = 0;
1248   /* Notes that I1, I2 or I3 is a MULT operation.  */
1249   int have_mult = 0;
1250   /* Number of clobbers of SCRATCH we had to add.  */
1251   int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1252
1253   int maxreg;
1254   rtx temp;
1255   register rtx link;
1256   int i;
1257
1258   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1259      This can occur when flow deletes an insn that it has merged into an
1260      auto-increment address.  We also can't do anything if I3 has a
1261      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1262      libcall.  */
1263
1264   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1265       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1266       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1267       || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1268     return 0;
1269
1270   combine_attempts++;
1271
1272   undobuf.undos = undobuf.previous_undos = 0;
1273   undobuf.other_insn = 0;
1274
1275   /* Save the current high-water-mark so we can free storage if we didn't
1276      accept this combination.  */
1277   undobuf.storage = (char *) oballoc (0);
1278
1279   /* Reset the hard register usage information.  */
1280   CLEAR_HARD_REG_SET (newpat_used_regs);
1281
1282   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1283      code below, set I1 to be the earlier of the two insns.  */
1284   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1285     temp = i1, i1 = i2, i2 = temp;
1286
1287   added_links_insn = 0;
1288
1289   /* First check for one important special-case that the code below will
1290      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1291      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1292      we may be able to replace that destination with the destination of I3.
1293      This occurs in the common code where we compute both a quotient and
1294      remainder into a structure, in which case we want to do the computation
1295      directly into the structure to avoid register-register copies.
1296
1297      We make very conservative checks below and only try to handle the
1298      most common cases of this.  For example, we only handle the case
1299      where I2 and I3 are adjacent to avoid making difficult register
1300      usage tests.  */
1301
1302   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1303       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1304       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1305       && (! SMALL_REGISTER_CLASSES
1306           || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1307               || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1308               || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1309       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1310       && GET_CODE (PATTERN (i2)) == PARALLEL
1311       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1312       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1313          below would need to check what is inside (and reg_overlap_mentioned_p
1314          doesn't support those codes anyway).  Don't allow those destinations;
1315          the resulting insn isn't likely to be recognized anyway.  */
1316       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1317       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1318       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1319                                     SET_DEST (PATTERN (i3)))
1320       && next_real_insn (i2) == i3)
1321     {
1322       rtx p2 = PATTERN (i2);
1323
1324       /* Make sure that the destination of I3,
1325          which we are going to substitute into one output of I2,
1326          is not used within another output of I2.  We must avoid making this:
1327          (parallel [(set (mem (reg 69)) ...)
1328                     (set (reg 69) ...)])
1329          which is not well-defined as to order of actions.
1330          (Besides, reload can't handle output reloads for this.)
1331
1332          The problem can also happen if the dest of I3 is a memory ref,
1333          if another dest in I2 is an indirect memory ref.  */
1334       for (i = 0; i < XVECLEN (p2, 0); i++)
1335         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1336              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1337             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1338                                         SET_DEST (XVECEXP (p2, 0, i))))
1339           break;
1340
1341       if (i == XVECLEN (p2, 0))
1342         for (i = 0; i < XVECLEN (p2, 0); i++)
1343           if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1344             {
1345               combine_merges++;
1346
1347               subst_insn = i3;
1348               subst_low_cuid = INSN_CUID (i2);
1349
1350               added_sets_2 = added_sets_1 = 0;
1351               i2dest = SET_SRC (PATTERN (i3));
1352
1353               /* Replace the dest in I2 with our dest and make the resulting
1354                  insn the new pattern for I3.  Then skip to where we
1355                  validate the pattern.  Everything was set up above.  */
1356               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1357                      SET_DEST (PATTERN (i3)));
1358
1359               newpat = p2;
1360               i3_subst_into_i2 = 1;
1361               goto validate_replacement;
1362             }
1363     }
1364
1365 #ifndef HAVE_cc0
1366   /* If we have no I1 and I2 looks like:
1367         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1368                    (set Y OP)])
1369      make up a dummy I1 that is
1370         (set Y OP)
1371      and change I2 to be
1372         (set (reg:CC X) (compare:CC Y (const_int 0)))
1373
1374      (We can ignore any trailing CLOBBERs.)
1375
1376      This undoes a previous combination and allows us to match a branch-and-
1377      decrement insn.  */
1378
1379   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1380       && XVECLEN (PATTERN (i2), 0) >= 2
1381       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1382       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1383           == MODE_CC)
1384       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1385       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1386       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1387       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1388       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1389                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1390     {
1391       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1392         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1393           break;
1394
1395       if (i == 1)
1396         {
1397           /* We make I1 with the same INSN_UID as I2.  This gives it
1398              the same INSN_CUID for value tracking.  Our fake I1 will
1399              never appear in the insn stream so giving it the same INSN_UID
1400              as I2 will not cause a problem.  */
1401
1402           subst_prev_insn = i1
1403             = gen_rtx (INSN, VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1404                        XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, NULL_RTX);
1405
1406           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1407           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1408                  SET_DEST (PATTERN (i1)));
1409         }
1410     }
1411 #endif
1412
1413   /* Verify that I2 and I1 are valid for combining.  */
1414   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1415       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1416     {
1417       undo_all ();
1418       return 0;
1419     }
1420
1421   /* Record whether I2DEST is used in I2SRC and similarly for the other
1422      cases.  Knowing this will help in register status updating below.  */
1423   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1424   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1425   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1426
1427   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1428      in I2SRC.  */
1429   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1430
1431   /* Ensure that I3's pattern can be the destination of combines.  */
1432   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1433                           i1 && i2dest_in_i1src && i1_feeds_i3,
1434                           &i3dest_killed))
1435     {
1436       undo_all ();
1437       return 0;
1438     }
1439
1440   /* See if any of the insns is a MULT operation.  Unless one is, we will
1441      reject a combination that is, since it must be slower.  Be conservative
1442      here.  */
1443   if (GET_CODE (i2src) == MULT
1444       || (i1 != 0 && GET_CODE (i1src) == MULT)
1445       || (GET_CODE (PATTERN (i3)) == SET
1446           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1447     have_mult = 1;
1448
1449   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1450      We used to do this EXCEPT in one case: I3 has a post-inc in an
1451      output operand.  However, that exception can give rise to insns like
1452         mov r3,(r3)+
1453      which is a famous insn on the PDP-11 where the value of r3 used as the
1454      source was model-dependent.  Avoid this sort of thing.  */
1455
1456 #if 0
1457   if (!(GET_CODE (PATTERN (i3)) == SET
1458         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1459         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1460         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1461             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1462     /* It's not the exception.  */
1463 #endif
1464 #ifdef AUTO_INC_DEC
1465     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1466       if (REG_NOTE_KIND (link) == REG_INC
1467           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1468               || (i1 != 0
1469                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1470         {
1471           undo_all ();
1472           return 0;
1473         }
1474 #endif
1475
1476   /* See if the SETs in I1 or I2 need to be kept around in the merged
1477      instruction: whenever the value set there is still needed past I3.
1478      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1479
1480      For the SET in I1, we have two cases:  If I1 and I2 independently
1481      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1482      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1483      in I1 needs to be kept around unless I1DEST dies or is set in either
1484      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1485      I1DEST.  If so, we know I1 feeds into I2.  */
1486
1487   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1488
1489   added_sets_1
1490     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1491                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1492
1493   /* If the set in I2 needs to be kept around, we must make a copy of
1494      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1495      PATTERN (I2), we are only substituting for the original I1DEST, not into
1496      an already-substituted copy.  This also prevents making self-referential
1497      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1498      I2DEST.  */
1499
1500   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1501            ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1502            : PATTERN (i2));
1503
1504   if (added_sets_2)
1505     i2pat = copy_rtx (i2pat);
1506
1507   combine_merges++;
1508
1509   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1510
1511   maxreg = max_reg_num ();
1512
1513   subst_insn = i3;
1514
1515   /* It is possible that the source of I2 or I1 may be performing an
1516      unneeded operation, such as a ZERO_EXTEND of something that is known
1517      to have the high part zero.  Handle that case by letting subst look at
1518      the innermost one of them.
1519
1520      Another way to do this would be to have a function that tries to
1521      simplify a single insn instead of merging two or more insns.  We don't
1522      do this because of the potential of infinite loops and because
1523      of the potential extra memory required.  However, doing it the way
1524      we are is a bit of a kludge and doesn't catch all cases.
1525
1526      But only do this if -fexpensive-optimizations since it slows things down
1527      and doesn't usually win.  */
1528
1529   if (flag_expensive_optimizations)
1530     {
1531       /* Pass pc_rtx so no substitutions are done, just simplifications.
1532          The cases that we are interested in here do not involve the few
1533          cases were is_replaced is checked.  */
1534       if (i1)
1535         {
1536           subst_low_cuid = INSN_CUID (i1);
1537           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1538         }
1539       else
1540         {
1541           subst_low_cuid = INSN_CUID (i2);
1542           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1543         }
1544
1545       undobuf.previous_undos = undobuf.undos;
1546     }
1547
1548 #ifndef HAVE_cc0
1549   /* Many machines that don't use CC0 have insns that can both perform an
1550      arithmetic operation and set the condition code.  These operations will
1551      be represented as a PARALLEL with the first element of the vector
1552      being a COMPARE of an arithmetic operation with the constant zero.
1553      The second element of the vector will set some pseudo to the result
1554      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1555      match such a pattern and so will generate an extra insn.   Here we test
1556      for this case, where both the comparison and the operation result are
1557      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1558      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1559
1560   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1561       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1562       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1563       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1564     {
1565       rtx *cc_use;
1566       enum machine_mode compare_mode;
1567
1568       newpat = PATTERN (i3);
1569       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1570
1571       i2_is_used = 1;
1572
1573 #ifdef EXTRA_CC_MODES
1574       /* See if a COMPARE with the operand we substituted in should be done
1575          with the mode that is currently being used.  If not, do the same
1576          processing we do in `subst' for a SET; namely, if the destination
1577          is used only once, try to replace it with a register of the proper
1578          mode and also replace the COMPARE.  */
1579       if (undobuf.other_insn == 0
1580           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1581                                         &undobuf.other_insn))
1582           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1583                                               i2src, const0_rtx))
1584               != GET_MODE (SET_DEST (newpat))))
1585         {
1586           int regno = REGNO (SET_DEST (newpat));
1587           rtx new_dest = gen_rtx (REG, compare_mode, regno);
1588
1589           if (regno < FIRST_PSEUDO_REGISTER
1590               || (REG_N_SETS (regno) == 1 && ! added_sets_2
1591                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1592             {
1593               if (regno >= FIRST_PSEUDO_REGISTER)
1594                 SUBST (regno_reg_rtx[regno], new_dest);
1595
1596               SUBST (SET_DEST (newpat), new_dest);
1597               SUBST (XEXP (*cc_use, 0), new_dest);
1598               SUBST (SET_SRC (newpat),
1599                      gen_rtx_combine (COMPARE, compare_mode,
1600                                       i2src, const0_rtx));
1601             }
1602           else
1603             undobuf.other_insn = 0;
1604         }
1605 #endif
1606     }
1607   else
1608 #endif
1609     {
1610       n_occurrences = 0;                /* `subst' counts here */
1611
1612       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1613          need to make a unique copy of I2SRC each time we substitute it
1614          to avoid self-referential rtl.  */
1615
1616       subst_low_cuid = INSN_CUID (i2);
1617       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1618                       ! i1_feeds_i3 && i1dest_in_i1src);
1619       undobuf.previous_undos = undobuf.undos;
1620
1621       /* Record whether i2's body now appears within i3's body.  */
1622       i2_is_used = n_occurrences;
1623     }
1624
1625   /* If we already got a failure, don't try to do more.  Otherwise,
1626      try to substitute in I1 if we have it.  */
1627
1628   if (i1 && GET_CODE (newpat) != CLOBBER)
1629     {
1630       /* Before we can do this substitution, we must redo the test done
1631          above (see detailed comments there) that ensures  that I1DEST
1632          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1633
1634       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1635                               0, NULL_PTR))
1636         {
1637           undo_all ();
1638           return 0;
1639         }
1640
1641       n_occurrences = 0;
1642       subst_low_cuid = INSN_CUID (i1);
1643       newpat = subst (newpat, i1dest, i1src, 0, 0);
1644       undobuf.previous_undos = undobuf.undos;
1645     }
1646
1647   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1648      to count all the ways that I2SRC and I1SRC can be used.  */
1649   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1650        && i2_is_used + added_sets_2 > 1)
1651       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1652           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1653               > 1))
1654       /* Fail if we tried to make a new register (we used to abort, but there's
1655          really no reason to).  */
1656       || max_reg_num () != maxreg
1657       /* Fail if we couldn't do something and have a CLOBBER.  */
1658       || GET_CODE (newpat) == CLOBBER
1659       /* Fail if this new pattern is a MULT and we didn't have one before
1660          at the outer level.  */
1661       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1662           && ! have_mult))
1663     {
1664       undo_all ();
1665       return 0;
1666     }
1667
1668   /* If the actions of the earlier insns must be kept
1669      in addition to substituting them into the latest one,
1670      we must make a new PARALLEL for the latest insn
1671      to hold additional the SETs.  */
1672
1673   if (added_sets_1 || added_sets_2)
1674     {
1675       combine_extras++;
1676
1677       if (GET_CODE (newpat) == PARALLEL)
1678         {
1679           rtvec old = XVEC (newpat, 0);
1680           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1681           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1682           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1683                  sizeof (old->elem[0]) * old->num_elem);
1684         }
1685       else
1686         {
1687           rtx old = newpat;
1688           total_sets = 1 + added_sets_1 + added_sets_2;
1689           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1690           XVECEXP (newpat, 0, 0) = old;
1691         }
1692
1693      if (added_sets_1)
1694        XVECEXP (newpat, 0, --total_sets)
1695          = (GET_CODE (PATTERN (i1)) == PARALLEL
1696             ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1697
1698      if (added_sets_2)
1699         {
1700           /* If there is no I1, use I2's body as is.  We used to also not do
1701              the subst call below if I2 was substituted into I3,
1702              but that could lose a simplification.  */
1703           if (i1 == 0)
1704             XVECEXP (newpat, 0, --total_sets) = i2pat;
1705           else
1706             /* See comment where i2pat is assigned.  */
1707             XVECEXP (newpat, 0, --total_sets)
1708               = subst (i2pat, i1dest, i1src, 0, 0);
1709         }
1710     }
1711
1712   /* We come here when we are replacing a destination in I2 with the
1713      destination of I3.  */
1714  validate_replacement:
1715
1716   /* Note which hard regs this insn has as inputs.  */
1717   mark_used_regs_combine (newpat);
1718
1719   /* Is the result of combination a valid instruction?  */
1720   insn_code_number
1721     = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1722
1723   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1724      the second SET's destination is a register that is unused.  In that case,
1725      we just need the first SET.   This can occur when simplifying a divmod
1726      insn.  We *must* test for this case here because the code below that
1727      splits two independent SETs doesn't handle this case correctly when it
1728      updates the register status.  Also check the case where the first
1729      SET's destination is unused.  That would not cause incorrect code, but
1730      does cause an unneeded insn to remain.  */
1731
1732   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1733       && XVECLEN (newpat, 0) == 2
1734       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1735       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1736       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1737       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1738       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1739       && asm_noperands (newpat) < 0)
1740     {
1741       newpat = XVECEXP (newpat, 0, 0);
1742       insn_code_number
1743         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1744     }
1745
1746   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1747            && XVECLEN (newpat, 0) == 2
1748            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1749            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1750            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1751            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1752            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1753            && asm_noperands (newpat) < 0)
1754     {
1755       newpat = XVECEXP (newpat, 0, 1);
1756       insn_code_number
1757         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1758     }
1759
1760   /* If we were combining three insns and the result is a simple SET
1761      with no ASM_OPERANDS that wasn't recognized, try to split it into two
1762      insns.  There are two ways to do this.  It can be split using a
1763      machine-specific method (like when you have an addition of a large
1764      constant) or by combine in the function find_split_point.  */
1765
1766   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1767       && asm_noperands (newpat) < 0)
1768     {
1769       rtx m_split, *split;
1770       rtx ni2dest = i2dest;
1771
1772       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
1773          use I2DEST as a scratch register will help.  In the latter case,
1774          convert I2DEST to the mode of the source of NEWPAT if we can.  */
1775
1776       m_split = split_insns (newpat, i3);
1777
1778       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1779          inputs of NEWPAT.  */
1780
1781       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1782          possible to try that as a scratch reg.  This would require adding
1783          more code to make it work though.  */
1784
1785       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1786         {
1787           /* If I2DEST is a hard register or the only use of a pseudo,
1788              we can change its mode.  */
1789           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1790               && GET_MODE (SET_DEST (newpat)) != VOIDmode
1791               && GET_CODE (i2dest) == REG
1792               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1793                   || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1794                       && ! REG_USERVAR_P (i2dest))))
1795             ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1796                                REGNO (i2dest));
1797
1798           m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1799                                           gen_rtvec (2, newpat,
1800                                                      gen_rtx (CLOBBER,
1801                                                               VOIDmode,
1802                                                               ni2dest))),
1803                                  i3);
1804         }
1805
1806       if (m_split && GET_CODE (m_split) == SEQUENCE
1807           && XVECLEN (m_split, 0) == 2
1808           && (next_real_insn (i2) == i3
1809               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1810                                       INSN_CUID (i2))))
1811         {
1812           rtx i2set, i3set;
1813           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1814           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1815
1816           i3set = single_set (XVECEXP (m_split, 0, 1));
1817           i2set = single_set (XVECEXP (m_split, 0, 0));
1818
1819           /* In case we changed the mode of I2DEST, replace it in the
1820              pseudo-register table here.  We can't do it above in case this
1821              code doesn't get executed and we do a split the other way.  */
1822
1823           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1824             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1825
1826           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1827                                               &i2_scratches);
1828
1829           /* If I2 or I3 has multiple SETs, we won't know how to track
1830              register status, so don't use these insns.  If I2's destination
1831              is used between I2 and I3, we also can't use these insns.  */
1832
1833           if (i2_code_number >= 0 && i2set && i3set
1834               && (next_real_insn (i2) == i3
1835                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1836             insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1837                                                   &i3_scratches);
1838           if (insn_code_number >= 0)
1839             newpat = newi3pat;
1840
1841           /* It is possible that both insns now set the destination of I3.
1842              If so, we must show an extra use of it.  */
1843
1844           if (insn_code_number >= 0)
1845             {
1846               rtx new_i3_dest = SET_DEST (i3set);
1847               rtx new_i2_dest = SET_DEST (i2set);
1848
1849               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1850                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1851                      || GET_CODE (new_i3_dest) == SUBREG)
1852                 new_i3_dest = XEXP (new_i3_dest, 0);
1853
1854               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1855                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1856                      || GET_CODE (new_i2_dest) == SUBREG)
1857                 new_i2_dest = XEXP (new_i2_dest, 0);
1858
1859               if (GET_CODE (new_i3_dest) == REG
1860                   && GET_CODE (new_i2_dest) == REG
1861                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1862                 REG_N_SETS (REGNO (new_i2_dest))++;
1863             }
1864         }
1865
1866       /* If we can split it and use I2DEST, go ahead and see if that
1867          helps things be recognized.  Verify that none of the registers
1868          are set between I2 and I3.  */
1869       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1870 #ifdef HAVE_cc0
1871           && GET_CODE (i2dest) == REG
1872 #endif
1873           /* We need I2DEST in the proper mode.  If it is a hard register
1874              or the only use of a pseudo, we can change its mode.  */
1875           && (GET_MODE (*split) == GET_MODE (i2dest)
1876               || GET_MODE (*split) == VOIDmode
1877               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1878               || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1879                   && ! REG_USERVAR_P (i2dest)))
1880           && (next_real_insn (i2) == i3
1881               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1882           /* We can't overwrite I2DEST if its value is still used by
1883              NEWPAT.  */
1884           && ! reg_referenced_p (i2dest, newpat))
1885         {
1886           rtx newdest = i2dest;
1887           enum rtx_code split_code = GET_CODE (*split);
1888           enum machine_mode split_mode = GET_MODE (*split);
1889
1890           /* Get NEWDEST as a register in the proper mode.  We have already
1891              validated that we can do this.  */
1892           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1893             {
1894               newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1895
1896               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1897                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1898             }
1899
1900           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1901              an ASHIFT.  This can occur if it was inside a PLUS and hence
1902              appeared to be a memory address.  This is a kludge.  */
1903           if (split_code == MULT
1904               && GET_CODE (XEXP (*split, 1)) == CONST_INT
1905               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1906             {
1907               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1908                                               XEXP (*split, 0), GEN_INT (i)));
1909               /* Update split_code because we may not have a multiply
1910                  anymore.  */
1911               split_code = GET_CODE (*split);
1912             }
1913
1914 #ifdef INSN_SCHEDULING
1915           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1916              be written as a ZERO_EXTEND.  */
1917           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1918             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1919                                             XEXP (*split, 0)));
1920 #endif
1921
1922           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1923           SUBST (*split, newdest);
1924           i2_code_number
1925             = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1926
1927           /* If the split point was a MULT and we didn't have one before,
1928              don't use one now.  */
1929           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1930             insn_code_number
1931               = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1932         }
1933     }
1934
1935   /* Check for a case where we loaded from memory in a narrow mode and
1936      then sign extended it, but we need both registers.  In that case,
1937      we have a PARALLEL with both loads from the same memory location.
1938      We can split this into a load from memory followed by a register-register
1939      copy.  This saves at least one insn, more if register allocation can
1940      eliminate the copy.
1941
1942      We cannot do this if the destination of the second assignment is
1943      a register that we have already assumed is zero-extended.  Similarly
1944      for a SUBREG of such a register.  */
1945
1946   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1947            && GET_CODE (newpat) == PARALLEL
1948            && XVECLEN (newpat, 0) == 2
1949            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1950            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1951            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1952            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1953                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1954            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1955                                    INSN_CUID (i2))
1956            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1957            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1958            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1959                  (GET_CODE (temp) == REG
1960                   && reg_nonzero_bits[REGNO (temp)] != 0
1961                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1962                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1963                   && (reg_nonzero_bits[REGNO (temp)]
1964                       != GET_MODE_MASK (word_mode))))
1965            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1966                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1967                      (GET_CODE (temp) == REG
1968                       && reg_nonzero_bits[REGNO (temp)] != 0
1969                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1970                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1971                       && (reg_nonzero_bits[REGNO (temp)]
1972                           != GET_MODE_MASK (word_mode)))))
1973            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1974                                          SET_SRC (XVECEXP (newpat, 0, 1)))
1975            && ! find_reg_note (i3, REG_UNUSED,
1976                                SET_DEST (XVECEXP (newpat, 0, 0))))
1977     {
1978       rtx ni2dest;
1979
1980       newi2pat = XVECEXP (newpat, 0, 0);
1981       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1982       newpat = XVECEXP (newpat, 0, 1);
1983       SUBST (SET_SRC (newpat),
1984              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1985       i2_code_number
1986         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1987
1988       if (i2_code_number >= 0)
1989         insn_code_number
1990           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1991
1992       if (insn_code_number >= 0)
1993         {
1994           rtx insn;
1995           rtx link;
1996
1997           /* If we will be able to accept this, we have made a change to the
1998              destination of I3.  This can invalidate a LOG_LINKS pointing
1999              to I3.  No other part of combine.c makes such a transformation.
2000
2001              The new I3 will have a destination that was previously the
2002              destination of I1 or I2 and which was used in i2 or I3.  Call
2003              distribute_links to make a LOG_LINK from the next use of
2004              that destination.  */
2005
2006           PATTERN (i3) = newpat;
2007           distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2008
2009           /* I3 now uses what used to be its destination and which is
2010              now I2's destination.  That means we need a LOG_LINK from
2011              I3 to I2.  But we used to have one, so we still will.
2012
2013              However, some later insn might be using I2's dest and have
2014              a LOG_LINK pointing at I3.  We must remove this link.
2015              The simplest way to remove the link is to point it at I1,
2016              which we know will be a NOTE.  */
2017
2018           for (insn = NEXT_INSN (i3);
2019                insn && (this_basic_block == n_basic_blocks - 1
2020                         || insn != basic_block_head[this_basic_block + 1]);
2021                insn = NEXT_INSN (insn))
2022             {
2023               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2024                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2025                 {
2026                   for (link = LOG_LINKS (insn); link;
2027                        link = XEXP (link, 1))
2028                     if (XEXP (link, 0) == i3)
2029                       XEXP (link, 0) = i1;
2030
2031                   break;
2032                 }
2033             }
2034         }
2035     }
2036
2037   /* Similarly, check for a case where we have a PARALLEL of two independent
2038      SETs but we started with three insns.  In this case, we can do the sets
2039      as two separate insns.  This case occurs when some SET allows two
2040      other insns to combine, but the destination of that SET is still live.  */
2041
2042   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2043            && GET_CODE (newpat) == PARALLEL
2044            && XVECLEN (newpat, 0) == 2
2045            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2046            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2047            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2048            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2049            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2050            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2051            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2052                                    INSN_CUID (i2))
2053            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2054            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2055            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2056            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2057                                   XVECEXP (newpat, 0, 0))
2058            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2059                                   XVECEXP (newpat, 0, 1)))
2060     {
2061       /* Normally, it doesn't matter which of the two is done first,
2062          but it does if one references cc0.  In that case, it has to
2063          be first.  */
2064 #ifdef HAVE_cc0
2065       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2066         {
2067           newi2pat = XVECEXP (newpat, 0, 0);
2068           newpat = XVECEXP (newpat, 0, 1);
2069         }
2070       else
2071 #endif
2072         {
2073           newi2pat = XVECEXP (newpat, 0, 1);
2074           newpat = XVECEXP (newpat, 0, 0);
2075         }
2076
2077       i2_code_number
2078         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2079
2080       if (i2_code_number >= 0)
2081         insn_code_number
2082           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2083     }
2084
2085   /* If it still isn't recognized, fail and change things back the way they
2086      were.  */
2087   if ((insn_code_number < 0
2088        /* Is the result a reasonable ASM_OPERANDS?  */
2089        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2090     {
2091       undo_all ();
2092       return 0;
2093     }
2094
2095   /* If we had to change another insn, make sure it is valid also.  */
2096   if (undobuf.other_insn)
2097     {
2098       rtx other_pat = PATTERN (undobuf.other_insn);
2099       rtx new_other_notes;
2100       rtx note, next;
2101
2102       CLEAR_HARD_REG_SET (newpat_used_regs);
2103
2104       other_code_number
2105         = recog_for_combine (&other_pat, undobuf.other_insn,
2106                              &new_other_notes, &other_scratches);
2107
2108       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2109         {
2110           undo_all ();
2111           return 0;
2112         }
2113
2114       PATTERN (undobuf.other_insn) = other_pat;
2115
2116       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2117          are still valid.  Then add any non-duplicate notes added by
2118          recog_for_combine.  */
2119       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2120         {
2121           next = XEXP (note, 1);
2122
2123           if (REG_NOTE_KIND (note) == REG_UNUSED
2124               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2125             {
2126               if (GET_CODE (XEXP (note, 0)) == REG)
2127                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2128
2129               remove_note (undobuf.other_insn, note);
2130             }
2131         }
2132
2133       for (note = new_other_notes; note; note = XEXP (note, 1))
2134         if (GET_CODE (XEXP (note, 0)) == REG)
2135           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2136
2137       distribute_notes (new_other_notes, undobuf.other_insn,
2138                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2139     }
2140
2141   /* We now know that we can do this combination.  Merge the insns and
2142      update the status of registers and LOG_LINKS.  */
2143
2144   {
2145     rtx i3notes, i2notes, i1notes = 0;
2146     rtx i3links, i2links, i1links = 0;
2147     rtx midnotes = 0;
2148     register int regno;
2149     /* Compute which registers we expect to eliminate.  newi2pat may be setting
2150        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
2151        same as i3dest, in which case newi2pat may be setting i1dest.  */
2152     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2153                    || i2dest_in_i2src || i2dest_in_i1src
2154                    ? 0 : i2dest);
2155     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2156                    || (newi2pat && reg_set_p (i1dest, newi2pat))
2157                    ? 0 : i1dest);
2158
2159     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2160        clear them.  */
2161     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2162     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2163     if (i1)
2164       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2165
2166     /* Ensure that we do not have something that should not be shared but
2167        occurs multiple times in the new insns.  Check this by first
2168        resetting all the `used' flags and then copying anything is shared.  */
2169
2170     reset_used_flags (i3notes);
2171     reset_used_flags (i2notes);
2172     reset_used_flags (i1notes);
2173     reset_used_flags (newpat);
2174     reset_used_flags (newi2pat);
2175     if (undobuf.other_insn)
2176       reset_used_flags (PATTERN (undobuf.other_insn));
2177
2178     i3notes = copy_rtx_if_shared (i3notes);
2179     i2notes = copy_rtx_if_shared (i2notes);
2180     i1notes = copy_rtx_if_shared (i1notes);
2181     newpat = copy_rtx_if_shared (newpat);
2182     newi2pat = copy_rtx_if_shared (newi2pat);
2183     if (undobuf.other_insn)
2184       reset_used_flags (PATTERN (undobuf.other_insn));
2185
2186     INSN_CODE (i3) = insn_code_number;
2187     PATTERN (i3) = newpat;
2188     if (undobuf.other_insn)
2189       INSN_CODE (undobuf.other_insn) = other_code_number;
2190
2191     /* We had one special case above where I2 had more than one set and
2192        we replaced a destination of one of those sets with the destination
2193        of I3.  In that case, we have to update LOG_LINKS of insns later
2194        in this basic block.  Note that this (expensive) case is rare.
2195
2196        Also, in this case, we must pretend that all REG_NOTEs for I2
2197        actually came from I3, so that REG_UNUSED notes from I2 will be
2198        properly handled.  */
2199
2200     if (i3_subst_into_i2)
2201       {
2202         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2203           if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2204               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2205               && ! find_reg_note (i2, REG_UNUSED,
2206                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2207             for (temp = NEXT_INSN (i2);
2208                  temp && (this_basic_block == n_basic_blocks - 1
2209                           || basic_block_head[this_basic_block] != temp);
2210                  temp = NEXT_INSN (temp))
2211               if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2212                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2213                   if (XEXP (link, 0) == i2)
2214                     XEXP (link, 0) = i3;
2215
2216         if (i3notes)
2217           {
2218             rtx link = i3notes;
2219             while (XEXP (link, 1))
2220               link = XEXP (link, 1);
2221             XEXP (link, 1) = i2notes;
2222           }
2223         else
2224           i3notes = i2notes;
2225         i2notes = 0;
2226       }
2227
2228     LOG_LINKS (i3) = 0;
2229     REG_NOTES (i3) = 0;
2230     LOG_LINKS (i2) = 0;
2231     REG_NOTES (i2) = 0;
2232
2233     if (newi2pat)
2234       {
2235         INSN_CODE (i2) = i2_code_number;
2236         PATTERN (i2) = newi2pat;
2237       }
2238     else
2239       {
2240         PUT_CODE (i2, NOTE);
2241         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2242         NOTE_SOURCE_FILE (i2) = 0;
2243       }
2244
2245     if (i1)
2246       {
2247         LOG_LINKS (i1) = 0;
2248         REG_NOTES (i1) = 0;
2249         PUT_CODE (i1, NOTE);
2250         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2251         NOTE_SOURCE_FILE (i1) = 0;
2252       }
2253
2254     /* Get death notes for everything that is now used in either I3 or
2255        I2 and used to die in a previous insn.  If we built two new
2256        patterns, move from I1 to I2 then I2 to I3 so that we get the
2257        proper movement on registers that I2 modifies.  */
2258
2259     if (newi2pat)
2260       {
2261         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2262         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2263       }
2264     else
2265       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2266                    i3, &midnotes);
2267
2268     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2269     if (i3notes)
2270       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2271                         elim_i2, elim_i1);
2272     if (i2notes)
2273       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2274                         elim_i2, elim_i1);
2275     if (i1notes)
2276       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2277                         elim_i2, elim_i1);
2278     if (midnotes)
2279       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2280                         elim_i2, elim_i1);
2281
2282     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2283        know these are REG_UNUSED and want them to go to the desired insn,
2284        so we always pass it as i3.  We have not counted the notes in
2285        reg_n_deaths yet, so we need to do so now.  */
2286
2287     if (newi2pat && new_i2_notes)
2288       {
2289         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2290           if (GET_CODE (XEXP (temp, 0)) == REG)
2291             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2292
2293         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2294       }
2295
2296     if (new_i3_notes)
2297       {
2298         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2299           if (GET_CODE (XEXP (temp, 0)) == REG)
2300             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2301
2302         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2303       }
2304
2305     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2306        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
2307        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
2308        in that case, it might delete I2.  Similarly for I2 and I1.
2309        Show an additional death due to the REG_DEAD note we make here.  If
2310        we discard it in distribute_notes, we will decrement it again.  */
2311
2312     if (i3dest_killed)
2313       {
2314         if (GET_CODE (i3dest_killed) == REG)
2315           REG_N_DEATHS (REGNO (i3dest_killed))++;
2316
2317         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2318           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2319                                      NULL_RTX),
2320                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2321         else
2322           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2323                                      NULL_RTX),
2324                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2325                             elim_i2, elim_i1);
2326       }
2327
2328     if (i2dest_in_i2src)
2329       {
2330         if (GET_CODE (i2dest) == REG)
2331           REG_N_DEATHS (REGNO (i2dest))++;
2332
2333         if (newi2pat && reg_set_p (i2dest, newi2pat))
2334           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2335                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2336         else
2337           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2338                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2339                             NULL_RTX, NULL_RTX);
2340       }
2341
2342     if (i1dest_in_i1src)
2343       {
2344         if (GET_CODE (i1dest) == REG)
2345           REG_N_DEATHS (REGNO (i1dest))++;
2346
2347         if (newi2pat && reg_set_p (i1dest, newi2pat))
2348           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2349                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2350         else
2351           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2352                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2353                             NULL_RTX, NULL_RTX);
2354       }
2355
2356     distribute_links (i3links);
2357     distribute_links (i2links);
2358     distribute_links (i1links);
2359
2360     if (GET_CODE (i2dest) == REG)
2361       {
2362         rtx link;
2363         rtx i2_insn = 0, i2_val = 0, set;
2364
2365         /* The insn that used to set this register doesn't exist, and
2366            this life of the register may not exist either.  See if one of
2367            I3's links points to an insn that sets I2DEST.  If it does,
2368            that is now the last known value for I2DEST. If we don't update
2369            this and I2 set the register to a value that depended on its old
2370            contents, we will get confused.  If this insn is used, thing
2371            will be set correctly in combine_instructions.  */
2372
2373         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2374           if ((set = single_set (XEXP (link, 0))) != 0
2375               && rtx_equal_p (i2dest, SET_DEST (set)))
2376             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2377
2378         record_value_for_reg (i2dest, i2_insn, i2_val);
2379
2380         /* If the reg formerly set in I2 died only once and that was in I3,
2381            zero its use count so it won't make `reload' do any work.  */
2382         if (! added_sets_2
2383             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2384             && ! i2dest_in_i2src)
2385           {
2386             regno = REGNO (i2dest);
2387             REG_N_SETS (regno)--;
2388             if (REG_N_SETS (regno) == 0
2389                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2390               REG_N_REFS (regno) = 0;
2391           }
2392       }
2393
2394     if (i1 && GET_CODE (i1dest) == REG)
2395       {
2396         rtx link;
2397         rtx i1_insn = 0, i1_val = 0, set;
2398
2399         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2400           if ((set = single_set (XEXP (link, 0))) != 0
2401               && rtx_equal_p (i1dest, SET_DEST (set)))
2402             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2403
2404         record_value_for_reg (i1dest, i1_insn, i1_val);
2405
2406         regno = REGNO (i1dest);
2407         if (! added_sets_1 && ! i1dest_in_i1src)
2408           {
2409             REG_N_SETS (regno)--;
2410             if (REG_N_SETS (regno) == 0
2411                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2412               REG_N_REFS (regno) = 0;
2413           }
2414       }
2415
2416     /* Update reg_nonzero_bits et al for any changes that may have been made
2417        to this insn.  */
2418
2419     note_stores (newpat, set_nonzero_bits_and_sign_copies);
2420     if (newi2pat)
2421       note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2422
2423     /* If we added any (clobber (scratch)), add them to the max for a
2424        block.  This is a very pessimistic calculation, since we might
2425        have had them already and this might not be the worst block, but
2426        it's not worth doing any better.  */
2427     max_scratch += i3_scratches + i2_scratches + other_scratches;
2428
2429     /* If I3 is now an unconditional jump, ensure that it has a
2430        BARRIER following it since it may have initially been a
2431        conditional jump.  It may also be the last nonnote insn.  */
2432
2433     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2434         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2435             || GET_CODE (temp) != BARRIER))
2436       emit_barrier_after (i3);
2437   }
2438
2439   combine_successes++;
2440
2441   /* Clear this here, so that subsequent get_last_value calls are not
2442      affected.  */
2443   subst_prev_insn = NULL_RTX;
2444
2445   if (added_links_insn
2446       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2447       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2448     return added_links_insn;
2449   else
2450     return newi2pat ? i2 : i3;
2451 }
2452 \f
2453 /* Undo all the modifications recorded in undobuf.  */
2454
2455 static void
2456 undo_all ()
2457 {
2458   struct undo *undo, *next;
2459
2460   for (undo = undobuf.undos; undo; undo = next)
2461     {
2462       next = undo->next;
2463       if (undo->is_int)
2464         *undo->where.i = undo->old_contents.i;
2465       else
2466         *undo->where.r = undo->old_contents.r;
2467
2468       undo->next = undobuf.frees;
2469       undobuf.frees = undo;
2470     }
2471
2472   obfree (undobuf.storage);
2473   undobuf.undos = undobuf.previous_undos = 0;
2474
2475   /* Clear this here, so that subsequent get_last_value calls are not
2476      affected.  */
2477   subst_prev_insn = NULL_RTX;
2478 }
2479 \f
2480 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2481    where we have an arithmetic expression and return that point.  LOC will
2482    be inside INSN.
2483
2484    try_combine will call this function to see if an insn can be split into
2485    two insns.  */
2486
2487 static rtx *
2488 find_split_point (loc, insn)
2489      rtx *loc;
2490      rtx insn;
2491 {
2492   rtx x = *loc;
2493   enum rtx_code code = GET_CODE (x);
2494   rtx *split;
2495   int len = 0, pos, unsignedp;
2496   rtx inner;
2497
2498   /* First special-case some codes.  */
2499   switch (code)
2500     {
2501     case SUBREG:
2502 #ifdef INSN_SCHEDULING
2503       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2504          point.  */
2505       if (GET_CODE (SUBREG_REG (x)) == MEM)
2506         return loc;
2507 #endif
2508       return find_split_point (&SUBREG_REG (x), insn);
2509
2510     case MEM:
2511 #ifdef HAVE_lo_sum
2512       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2513          using LO_SUM and HIGH.  */
2514       if (GET_CODE (XEXP (x, 0)) == CONST
2515           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2516         {
2517           SUBST (XEXP (x, 0),
2518                  gen_rtx_combine (LO_SUM, Pmode,
2519                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2520                                   XEXP (x, 0)));
2521           return &XEXP (XEXP (x, 0), 0);
2522         }
2523 #endif
2524
2525       /* If we have a PLUS whose second operand is a constant and the
2526          address is not valid, perhaps will can split it up using
2527          the machine-specific way to split large constants.  We use
2528          the first pseudo-reg (one of the virtual regs) as a placeholder;
2529          it will not remain in the result.  */
2530       if (GET_CODE (XEXP (x, 0)) == PLUS
2531           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2532           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2533         {
2534           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2535           rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2536                                  subst_insn);
2537
2538           /* This should have produced two insns, each of which sets our
2539              placeholder.  If the source of the second is a valid address,
2540              we can make put both sources together and make a split point
2541              in the middle.  */
2542
2543           if (seq && XVECLEN (seq, 0) == 2
2544               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2545               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2546               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2547               && ! reg_mentioned_p (reg,
2548                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2549               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2550               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2551               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2552               && memory_address_p (GET_MODE (x),
2553                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2554             {
2555               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2556               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2557
2558               /* Replace the placeholder in SRC2 with SRC1.  If we can
2559                  find where in SRC2 it was placed, that can become our
2560                  split point and we can replace this address with SRC2.
2561                  Just try two obvious places.  */
2562
2563               src2 = replace_rtx (src2, reg, src1);
2564               split = 0;
2565               if (XEXP (src2, 0) == src1)
2566                 split = &XEXP (src2, 0);
2567               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2568                        && XEXP (XEXP (src2, 0), 0) == src1)
2569                 split = &XEXP (XEXP (src2, 0), 0);
2570
2571               if (split)
2572                 {
2573                   SUBST (XEXP (x, 0), src2);
2574                   return split;
2575                 }
2576             }
2577
2578           /* If that didn't work, perhaps the first operand is complex and
2579              needs to be computed separately, so make a split point there.
2580              This will occur on machines that just support REG + CONST
2581              and have a constant moved through some previous computation.  */
2582
2583           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2584                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2585                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2586                              == 'o')))
2587             return &XEXP (XEXP (x, 0), 0);
2588         }
2589       break;
2590
2591     case SET:
2592 #ifdef HAVE_cc0
2593       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2594          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2595          we need to put the operand into a register.  So split at that
2596          point.  */
2597
2598       if (SET_DEST (x) == cc0_rtx
2599           && GET_CODE (SET_SRC (x)) != COMPARE
2600           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2601           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2602           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2603                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2604         return &SET_SRC (x);
2605 #endif
2606
2607       /* See if we can split SET_SRC as it stands.  */
2608       split = find_split_point (&SET_SRC (x), insn);
2609       if (split && split != &SET_SRC (x))
2610         return split;
2611
2612       /* See if we can split SET_DEST as it stands.  */
2613       split = find_split_point (&SET_DEST (x), insn);
2614       if (split && split != &SET_DEST (x))
2615         return split;
2616
2617       /* See if this is a bitfield assignment with everything constant.  If
2618          so, this is an IOR of an AND, so split it into that.  */
2619       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2620           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2621               <= HOST_BITS_PER_WIDE_INT)
2622           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2623           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2624           && GET_CODE (SET_SRC (x)) == CONST_INT
2625           && ((INTVAL (XEXP (SET_DEST (x), 1))
2626               + INTVAL (XEXP (SET_DEST (x), 2)))
2627               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2628           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2629         {
2630           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2631           int len = INTVAL (XEXP (SET_DEST (x), 1));
2632           int src = INTVAL (SET_SRC (x));
2633           rtx dest = XEXP (SET_DEST (x), 0);
2634           enum machine_mode mode = GET_MODE (dest);
2635           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2636
2637           if (BITS_BIG_ENDIAN)
2638             pos = GET_MODE_BITSIZE (mode) - len - pos;
2639
2640           if (src == mask)
2641             SUBST (SET_SRC (x),
2642                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2643           else
2644             SUBST (SET_SRC (x),
2645                    gen_binary (IOR, mode,
2646                                gen_binary (AND, mode, dest,
2647                                            GEN_INT (~ (mask << pos)
2648                                                     & GET_MODE_MASK (mode))),
2649                                GEN_INT (src << pos)));
2650
2651           SUBST (SET_DEST (x), dest);
2652
2653           split = find_split_point (&SET_SRC (x), insn);
2654           if (split && split != &SET_SRC (x))
2655             return split;
2656         }
2657
2658       /* Otherwise, see if this is an operation that we can split into two.
2659          If so, try to split that.  */
2660       code = GET_CODE (SET_SRC (x));
2661
2662       switch (code)
2663         {
2664         case AND:
2665           /* If we are AND'ing with a large constant that is only a single
2666              bit and the result is only being used in a context where we
2667              need to know if it is zero or non-zero, replace it with a bit
2668              extraction.  This will avoid the large constant, which might
2669              have taken more than one insn to make.  If the constant were
2670              not a valid argument to the AND but took only one insn to make,
2671              this is no worse, but if it took more than one insn, it will
2672              be better.  */
2673
2674           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2675               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2676               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2677               && GET_CODE (SET_DEST (x)) == REG
2678               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2679               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2680               && XEXP (*split, 0) == SET_DEST (x)
2681               && XEXP (*split, 1) == const0_rtx)
2682             {
2683               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2684                                                 XEXP (SET_SRC (x), 0),
2685                                                 pos, NULL_RTX, 1, 1, 0, 0);
2686               if (extraction != 0)
2687                 {
2688                   SUBST (SET_SRC (x), extraction);
2689                   return find_split_point (loc, insn);
2690                 }
2691             }
2692           break;
2693
2694         case NE:
2695           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2696              is known to be on, this can be converted into a NEG of a shift. */
2697           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2698               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2699               && 1 <= (pos = exact_log2
2700                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2701                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2702             {
2703               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2704
2705               SUBST (SET_SRC (x),
2706                      gen_rtx_combine (NEG, mode,
2707                                       gen_rtx_combine (LSHIFTRT, mode,
2708                                                        XEXP (SET_SRC (x), 0),
2709                                                        GEN_INT (pos))));
2710
2711               split = find_split_point (&SET_SRC (x), insn);
2712               if (split && split != &SET_SRC (x))
2713                 return split;
2714             }
2715           break;
2716
2717         case SIGN_EXTEND:
2718           inner = XEXP (SET_SRC (x), 0);
2719
2720           /* We can't optimize if either mode is a partial integer
2721              mode as we don't know how many bits are significant
2722              in those modes.  */
2723           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2724               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2725             break;
2726
2727           pos = 0;
2728           len = GET_MODE_BITSIZE (GET_MODE (inner));
2729           unsignedp = 0;
2730           break;
2731
2732         case SIGN_EXTRACT:
2733         case ZERO_EXTRACT:
2734           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2735               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2736             {
2737               inner = XEXP (SET_SRC (x), 0);
2738               len = INTVAL (XEXP (SET_SRC (x), 1));
2739               pos = INTVAL (XEXP (SET_SRC (x), 2));
2740
2741               if (BITS_BIG_ENDIAN)
2742                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2743               unsignedp = (code == ZERO_EXTRACT);
2744             }
2745           break;
2746
2747         default:
2748           break;
2749         }
2750
2751       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2752         {
2753           enum machine_mode mode = GET_MODE (SET_SRC (x));
2754
2755           /* For unsigned, we have a choice of a shift followed by an
2756              AND or two shifts.  Use two shifts for field sizes where the
2757              constant might be too large.  We assume here that we can
2758              always at least get 8-bit constants in an AND insn, which is
2759              true for every current RISC.  */
2760
2761           if (unsignedp && len <= 8)
2762             {
2763               SUBST (SET_SRC (x),
2764                      gen_rtx_combine
2765                      (AND, mode,
2766                       gen_rtx_combine (LSHIFTRT, mode,
2767                                        gen_lowpart_for_combine (mode, inner),
2768                                        GEN_INT (pos)),
2769                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2770
2771               split = find_split_point (&SET_SRC (x), insn);
2772               if (split && split != &SET_SRC (x))
2773                 return split;
2774             }
2775           else
2776             {
2777               SUBST (SET_SRC (x),
2778                      gen_rtx_combine
2779                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2780                       gen_rtx_combine (ASHIFT, mode,
2781                                        gen_lowpart_for_combine (mode, inner),
2782                                        GEN_INT (GET_MODE_BITSIZE (mode)
2783                                                 - len - pos)),
2784                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2785
2786               split = find_split_point (&SET_SRC (x), insn);
2787               if (split && split != &SET_SRC (x))
2788                 return split;
2789             }
2790         }
2791
2792       /* See if this is a simple operation with a constant as the second
2793          operand.  It might be that this constant is out of range and hence
2794          could be used as a split point.  */
2795       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2796            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2797            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2798           && CONSTANT_P (XEXP (SET_SRC (x), 1))
2799           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2800               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2801                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2802                       == 'o'))))
2803         return &XEXP (SET_SRC (x), 1);
2804
2805       /* Finally, see if this is a simple operation with its first operand
2806          not in a register.  The operation might require this operand in a
2807          register, so return it as a split point.  We can always do this
2808          because if the first operand were another operation, we would have
2809          already found it as a split point.  */
2810       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2811            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2812            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2813            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2814           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2815         return &XEXP (SET_SRC (x), 0);
2816
2817       return 0;
2818
2819     case AND:
2820     case IOR:
2821       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2822          it is better to write this as (not (ior A B)) so we can split it.
2823          Similarly for IOR.  */
2824       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2825         {
2826           SUBST (*loc,
2827                  gen_rtx_combine (NOT, GET_MODE (x),
2828                                   gen_rtx_combine (code == IOR ? AND : IOR,
2829                                                    GET_MODE (x),
2830                                                    XEXP (XEXP (x, 0), 0),
2831                                                    XEXP (XEXP (x, 1), 0))));
2832           return find_split_point (loc, insn);
2833         }
2834
2835       /* Many RISC machines have a large set of logical insns.  If the
2836          second operand is a NOT, put it first so we will try to split the
2837          other operand first.  */
2838       if (GET_CODE (XEXP (x, 1)) == NOT)
2839         {
2840           rtx tem = XEXP (x, 0);
2841           SUBST (XEXP (x, 0), XEXP (x, 1));
2842           SUBST (XEXP (x, 1), tem);
2843         }
2844       break;
2845
2846     default:
2847       break;
2848     }
2849
2850   /* Otherwise, select our actions depending on our rtx class.  */
2851   switch (GET_RTX_CLASS (code))
2852     {
2853     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
2854     case '3':
2855       split = find_split_point (&XEXP (x, 2), insn);
2856       if (split)
2857         return split;
2858       /* ... fall through ...  */
2859     case '2':
2860     case 'c':
2861     case '<':
2862       split = find_split_point (&XEXP (x, 1), insn);
2863       if (split)
2864         return split;
2865       /* ... fall through ...  */
2866     case '1':
2867       /* Some machines have (and (shift ...) ...) insns.  If X is not
2868          an AND, but XEXP (X, 0) is, use it as our split point.  */
2869       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2870         return &XEXP (x, 0);
2871
2872       split = find_split_point (&XEXP (x, 0), insn);
2873       if (split)
2874         return split;
2875       return loc;
2876     }
2877
2878   /* Otherwise, we don't have a split point.  */
2879   return 0;
2880 }
2881 \f
2882 /* Throughout X, replace FROM with TO, and return the result.
2883    The result is TO if X is FROM;
2884    otherwise the result is X, but its contents may have been modified.
2885    If they were modified, a record was made in undobuf so that
2886    undo_all will (among other things) return X to its original state.
2887
2888    If the number of changes necessary is too much to record to undo,
2889    the excess changes are not made, so the result is invalid.
2890    The changes already made can still be undone.
2891    undobuf.num_undo is incremented for such changes, so by testing that
2892    the caller can tell whether the result is valid.
2893
2894    `n_occurrences' is incremented each time FROM is replaced.
2895
2896    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2897
2898    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
2899    by copying if `n_occurrences' is non-zero.  */
2900
2901 static rtx
2902 subst (x, from, to, in_dest, unique_copy)
2903      register rtx x, from, to;
2904      int in_dest;
2905      int unique_copy;
2906 {
2907   register enum rtx_code code = GET_CODE (x);
2908   enum machine_mode op0_mode = VOIDmode;
2909   register char *fmt;
2910   register int len, i;
2911   rtx new;
2912
2913 /* Two expressions are equal if they are identical copies of a shared
2914    RTX or if they are both registers with the same register number
2915    and mode.  */
2916
2917 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
2918   ((X) == (Y)                                           \
2919    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
2920        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2921
2922   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2923     {
2924       n_occurrences++;
2925       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2926     }
2927
2928   /* If X and FROM are the same register but different modes, they will
2929      not have been seen as equal above.  However, flow.c will make a
2930      LOG_LINKS entry for that case.  If we do nothing, we will try to
2931      rerecognize our original insn and, when it succeeds, we will
2932      delete the feeding insn, which is incorrect.
2933
2934      So force this insn not to match in this (rare) case.  */
2935   if (! in_dest && code == REG && GET_CODE (from) == REG
2936       && REGNO (x) == REGNO (from))
2937     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2938
2939   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2940      of which may contain things that can be combined.  */
2941   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2942     return x;
2943
2944   /* It is possible to have a subexpression appear twice in the insn.
2945      Suppose that FROM is a register that appears within TO.
2946      Then, after that subexpression has been scanned once by `subst',
2947      the second time it is scanned, TO may be found.  If we were
2948      to scan TO here, we would find FROM within it and create a
2949      self-referent rtl structure which is completely wrong.  */
2950   if (COMBINE_RTX_EQUAL_P (x, to))
2951     return to;
2952
2953   len = GET_RTX_LENGTH (code);
2954   fmt = GET_RTX_FORMAT (code);
2955
2956   /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2957      set up to skip this common case.  All other cases where we want to
2958      suppress replacing something inside a SET_SRC are handled via the
2959      IN_DEST operand.  */
2960   if (code == SET
2961       && (GET_CODE (SET_DEST (x)) == REG
2962         || GET_CODE (SET_DEST (x)) == CC0
2963         || GET_CODE (SET_DEST (x)) == PC))
2964     fmt = "ie";
2965
2966   /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2967      constant.  */
2968   if (fmt[0] == 'e')
2969     op0_mode = GET_MODE (XEXP (x, 0));
2970
2971   for (i = 0; i < len; i++)
2972     {
2973       if (fmt[i] == 'E')
2974         {
2975           register int j;
2976           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2977             {
2978               if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2979                 {
2980                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2981                   n_occurrences++;
2982                 }
2983               else
2984                 {
2985                   new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2986
2987                   /* If this substitution failed, this whole thing fails.  */
2988                   if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2989                     return new;
2990                 }
2991
2992               SUBST (XVECEXP (x, i, j), new);
2993             }
2994         }
2995       else if (fmt[i] == 'e')
2996         {
2997           if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2998             {
2999               /* In general, don't install a subreg involving two modes not
3000                  tieable.  It can worsen register allocation, and can even
3001                  make invalid reload insns, since the reg inside may need to
3002                  be copied from in the outside mode, and that may be invalid
3003                  if it is an fp reg copied in integer mode.
3004
3005                  We allow two exceptions to this: It is valid if it is inside
3006                  another SUBREG and the mode of that SUBREG and the mode of
3007                  the inside of TO is tieable and it is valid if X is a SET
3008                  that copies FROM to CC0.  */
3009               if (GET_CODE (to) == SUBREG
3010                   && ! MODES_TIEABLE_P (GET_MODE (to),
3011                                         GET_MODE (SUBREG_REG (to)))
3012                   && ! (code == SUBREG
3013                         && MODES_TIEABLE_P (GET_MODE (x),
3014                                             GET_MODE (SUBREG_REG (to))))
3015 #ifdef HAVE_cc0
3016                   && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3017 #endif
3018                   )
3019                 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3020
3021               new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3022               n_occurrences++;
3023             }
3024           else
3025             /* If we are in a SET_DEST, suppress most cases unless we
3026                have gone inside a MEM, in which case we want to
3027                simplify the address.  We assume here that things that
3028                are actually part of the destination have their inner
3029                parts in the first expression.  This is true for SUBREG,
3030                STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3031                things aside from REG and MEM that should appear in a
3032                SET_DEST.  */
3033             new = subst (XEXP (x, i), from, to,
3034                          (((in_dest
3035                             && (code == SUBREG || code == STRICT_LOW_PART
3036                                 || code == ZERO_EXTRACT))
3037                            || code == SET)
3038                           && i == 0), unique_copy);
3039
3040           /* If we found that we will have to reject this combination,
3041              indicate that by returning the CLOBBER ourselves, rather than
3042              an expression containing it.  This will speed things up as
3043              well as prevent accidents where two CLOBBERs are considered
3044              to be equal, thus producing an incorrect simplification.  */
3045
3046           if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3047             return new;
3048
3049           SUBST (XEXP (x, i), new);
3050         }
3051     }
3052
3053   /* Try to simplify X.  If the simplification changed the code, it is likely
3054      that further simplification will help, so loop, but limit the number
3055      of repetitions that will be performed.  */
3056
3057   for (i = 0; i < 4; i++)
3058     {
3059       /* If X is sufficiently simple, don't bother trying to do anything
3060          with it.  */
3061       if (code != CONST_INT && code != REG && code != CLOBBER)
3062         x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3063
3064       if (GET_CODE (x) == code)
3065         break;
3066
3067       code = GET_CODE (x);
3068
3069       /* We no longer know the original mode of operand 0 since we
3070          have changed the form of X)  */
3071       op0_mode = VOIDmode;
3072     }
3073
3074   return x;
3075 }
3076 \f
3077 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3078    outer level; call `subst' to simplify recursively.  Return the new
3079    expression.
3080
3081    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3082    will be the iteration even if an expression with a code different from
3083    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3084
3085 static rtx
3086 simplify_rtx (x, op0_mode, last, in_dest)
3087      rtx x;
3088      enum machine_mode op0_mode;
3089      int last;
3090      int in_dest;
3091 {
3092   enum rtx_code code = GET_CODE (x);
3093   enum machine_mode mode = GET_MODE (x);
3094   rtx temp;
3095   int i;
3096
3097   /* If this is a commutative operation, put a constant last and a complex
3098      expression first.  We don't need to do this for comparisons here.  */
3099   if (GET_RTX_CLASS (code) == 'c'
3100       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3101           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3102               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3103           || (GET_CODE (XEXP (x, 0)) == SUBREG
3104               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3105               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3106     {
3107       temp = XEXP (x, 0);
3108       SUBST (XEXP (x, 0), XEXP (x, 1));
3109       SUBST (XEXP (x, 1), temp);
3110     }
3111
3112   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3113      sign extension of a PLUS with a constant, reverse the order of the sign
3114      extension and the addition. Note that this not the same as the original
3115      code, but overflow is undefined for signed values.  Also note that the
3116      PLUS will have been partially moved "inside" the sign-extension, so that
3117      the first operand of X will really look like:
3118          (ashiftrt (plus (ashift A C4) C5) C4).
3119      We convert this to
3120          (plus (ashiftrt (ashift A C4) C2) C4)
3121      and replace the first operand of X with that expression.  Later parts
3122      of this function may simplify the expression further.
3123
3124      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3125      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3126      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3127
3128      We do this to simplify address expressions.  */
3129
3130   if ((code == PLUS || code == MINUS || code == MULT)
3131       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3132       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3133       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3134       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3135       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3136       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3137       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3138       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3139                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3140                                             XEXP (XEXP (x, 0), 1))) != 0)
3141     {
3142       rtx new
3143         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3144                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3145                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3146
3147       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3148                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3149
3150       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3151     }
3152
3153   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3154      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3155      things.  Check for cases where both arms are testing the same
3156      condition.
3157
3158      Don't do anything if all operands are very simple.  */
3159
3160   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3161         || GET_RTX_CLASS (code) == '<')
3162        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3163             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3164                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3165                       == 'o')))
3166            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3167                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3168                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3169                          == 'o')))))
3170       || (GET_RTX_CLASS (code) == '1'
3171           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3172                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3173                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3174                          == 'o'))))))
3175     {
3176       rtx cond, true, false;
3177
3178       cond = if_then_else_cond (x, &true, &false);
3179       if (cond != 0
3180           /* If everything is a comparison, what we have is highly unlikely
3181              to be simpler, so don't use it.  */
3182           && ! (GET_RTX_CLASS (code) == '<'
3183                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3184                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3185         {
3186           rtx cop1 = const0_rtx;
3187           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3188
3189           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3190             return x;
3191
3192           /* Simplify the alternative arms; this may collapse the true and
3193              false arms to store-flag values.  */
3194           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3195           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3196
3197           /* Restarting if we generate a store-flag expression will cause
3198              us to loop.  Just drop through in this case.  */
3199
3200           /* If the result values are STORE_FLAG_VALUE and zero, we can
3201              just make the comparison operation.  */
3202           if (true == const_true_rtx && false == const0_rtx)
3203             x = gen_binary (cond_code, mode, cond, cop1);
3204           else if (true == const0_rtx && false == const_true_rtx)
3205             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3206
3207           /* Likewise, we can make the negate of a comparison operation
3208              if the result values are - STORE_FLAG_VALUE and zero.  */
3209           else if (GET_CODE (true) == CONST_INT
3210                    && INTVAL (true) == - STORE_FLAG_VALUE
3211                    && false == const0_rtx)
3212             x = gen_unary (NEG, mode, mode,
3213                            gen_binary (cond_code, mode, cond, cop1));
3214           else if (GET_CODE (false) == CONST_INT
3215                    && INTVAL (false) == - STORE_FLAG_VALUE
3216                    && true == const0_rtx)
3217             x = gen_unary (NEG, mode, mode,
3218                            gen_binary (reverse_condition (cond_code),
3219                                        mode, cond, cop1));
3220           else
3221             return gen_rtx (IF_THEN_ELSE, mode,
3222                             gen_binary (cond_code, VOIDmode, cond, cop1),
3223                             true, false);
3224
3225           code = GET_CODE (x);
3226           op0_mode = VOIDmode;
3227         }
3228     }
3229
3230   /* Try to fold this expression in case we have constants that weren't
3231      present before.  */
3232   temp = 0;
3233   switch (GET_RTX_CLASS (code))
3234     {
3235     case '1':
3236       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3237       break;
3238     case '<':
3239       temp = simplify_relational_operation (code, op0_mode,
3240                                             XEXP (x, 0), XEXP (x, 1));
3241 #ifdef FLOAT_STORE_FLAG_VALUE
3242       if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3243         temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3244                 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3245 #endif
3246       break;
3247     case 'c':
3248     case '2':
3249       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3250       break;
3251     case 'b':
3252     case '3':
3253       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3254                                          XEXP (x, 1), XEXP (x, 2));
3255       break;
3256     }
3257
3258   if (temp)
3259     x = temp, code = GET_CODE (temp);
3260
3261   /* First see if we can apply the inverse distributive law.  */
3262   if (code == PLUS || code == MINUS
3263       || code == AND || code == IOR || code == XOR)
3264     {
3265       x = apply_distributive_law (x);
3266       code = GET_CODE (x);
3267     }
3268
3269   /* If CODE is an associative operation not otherwise handled, see if we
3270      can associate some operands.  This can win if they are constants or
3271      if they are logically related (i.e. (a & b) & a.  */
3272   if ((code == PLUS || code == MINUS
3273        || code == MULT || code == AND || code == IOR || code == XOR
3274        || code == DIV || code == UDIV
3275        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3276       && INTEGRAL_MODE_P (mode))
3277     {
3278       if (GET_CODE (XEXP (x, 0)) == code)
3279         {
3280           rtx other = XEXP (XEXP (x, 0), 0);
3281           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3282           rtx inner_op1 = XEXP (x, 1);
3283           rtx inner;
3284
3285           /* Make sure we pass the constant operand if any as the second
3286              one if this is a commutative operation.  */
3287           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3288             {
3289               rtx tem = inner_op0;
3290               inner_op0 = inner_op1;
3291               inner_op1 = tem;
3292             }
3293           inner = simplify_binary_operation (code == MINUS ? PLUS
3294                                              : code == DIV ? MULT
3295                                              : code == UDIV ? MULT
3296                                              : code,
3297                                              mode, inner_op0, inner_op1);
3298
3299           /* For commutative operations, try the other pair if that one
3300              didn't simplify.  */
3301           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3302             {
3303               other = XEXP (XEXP (x, 0), 1);
3304               inner = simplify_binary_operation (code, mode,
3305                                                  XEXP (XEXP (x, 0), 0),
3306                                                  XEXP (x, 1));
3307             }
3308
3309           if (inner)
3310             return gen_binary (code, mode, other, inner);
3311         }
3312     }
3313
3314   /* A little bit of algebraic simplification here.  */
3315   switch (code)
3316     {
3317     case MEM:
3318       /* Ensure that our address has any ASHIFTs converted to MULT in case
3319          address-recognizing predicates are called later.  */
3320       temp = make_compound_operation (XEXP (x, 0), MEM);
3321       SUBST (XEXP (x, 0), temp);
3322       break;
3323
3324     case SUBREG:
3325       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3326          is paradoxical.  If we can't do that safely, then it becomes
3327          something nonsensical so that this combination won't take place.  */
3328
3329       if (GET_CODE (SUBREG_REG (x)) == MEM
3330           && (GET_MODE_SIZE (mode)
3331               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3332         {
3333           rtx inner = SUBREG_REG (x);
3334           int endian_offset = 0;
3335           /* Don't change the mode of the MEM
3336              if that would change the meaning of the address.  */
3337           if (MEM_VOLATILE_P (SUBREG_REG (x))
3338               || mode_dependent_address_p (XEXP (inner, 0)))
3339             return gen_rtx (CLOBBER, mode, const0_rtx);
3340
3341           if (BYTES_BIG_ENDIAN)
3342             {
3343               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3344                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3345               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3346                 endian_offset -= (UNITS_PER_WORD
3347                                   - GET_MODE_SIZE (GET_MODE (inner)));
3348             }
3349           /* Note if the plus_constant doesn't make a valid address
3350              then this combination won't be accepted.  */
3351           x = gen_rtx (MEM, mode,
3352                        plus_constant (XEXP (inner, 0),
3353                                       (SUBREG_WORD (x) * UNITS_PER_WORD
3354                                        + endian_offset)));
3355           MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3356           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3357           MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3358           return x;
3359         }
3360
3361       /* If we are in a SET_DEST, these other cases can't apply.  */
3362       if (in_dest)
3363         return x;
3364
3365       /* Changing mode twice with SUBREG => just change it once,
3366          or not at all if changing back to starting mode.  */
3367       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3368         {
3369           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3370               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3371             return SUBREG_REG (SUBREG_REG (x));
3372
3373           SUBST_INT (SUBREG_WORD (x),
3374                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3375           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3376         }
3377
3378       /* SUBREG of a hard register => just change the register number
3379          and/or mode.  If the hard register is not valid in that mode,
3380          suppress this combination.  If the hard register is the stack,
3381          frame, or argument pointer, leave this as a SUBREG.  */
3382
3383       if (GET_CODE (SUBREG_REG (x)) == REG
3384           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3385           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3386 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3387           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3388 #endif
3389 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3390           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3391 #endif
3392           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3393         {
3394           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3395                                   mode))
3396             return gen_rtx (REG, mode,
3397                             REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3398           else
3399             return gen_rtx (CLOBBER, mode, const0_rtx);
3400         }
3401
3402       /* For a constant, try to pick up the part we want.  Handle a full
3403          word and low-order part.  Only do this if we are narrowing
3404          the constant; if it is being widened, we have no idea what
3405          the extra bits will have been set to.  */
3406
3407       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3408           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3409           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3410           && GET_MODE_CLASS (mode) == MODE_INT)
3411         {
3412           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3413                                   0, op0_mode);
3414           if (temp)
3415             return temp;
3416         }
3417
3418       /* If we want a subreg of a constant, at offset 0,
3419          take the low bits.  On a little-endian machine, that's
3420          always valid.  On a big-endian machine, it's valid
3421          only if the constant's mode fits in one word.   Note that we
3422          cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode.  */
3423       if (CONSTANT_P (SUBREG_REG (x))
3424           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3425               || ! WORDS_BIG_ENDIAN)
3426               ? SUBREG_WORD (x) == 0
3427               : (SUBREG_WORD (x)
3428                  == ((GET_MODE_SIZE (op0_mode)
3429                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3430                      / UNITS_PER_WORD)))
3431           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3432           && (! WORDS_BIG_ENDIAN
3433               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3434         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3435
3436       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3437          since we are saying that the high bits don't matter.  */
3438       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3439           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3440         return SUBREG_REG (x);
3441
3442       /* Note that we cannot do any narrowing for non-constants since
3443          we might have been counting on using the fact that some bits were
3444          zero.  We now do this in the SET.  */
3445
3446       break;
3447
3448     case NOT:
3449       /* (not (plus X -1)) can become (neg X).  */
3450       if (GET_CODE (XEXP (x, 0)) == PLUS
3451           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3452         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3453
3454       /* Similarly, (not (neg X)) is (plus X -1).  */
3455       if (GET_CODE (XEXP (x, 0)) == NEG)
3456         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3457                                 constm1_rtx);
3458
3459       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3460       if (GET_CODE (XEXP (x, 0)) == XOR
3461           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3462           && (temp = simplify_unary_operation (NOT, mode,
3463                                                XEXP (XEXP (x, 0), 1),
3464                                                mode)) != 0)
3465         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3466
3467       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3468          other than 1, but that is not valid.  We could do a similar
3469          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3470          but this doesn't seem common enough to bother with.  */
3471       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3472           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3473         return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3474                         XEXP (XEXP (x, 0), 1));
3475
3476       if (GET_CODE (XEXP (x, 0)) == SUBREG
3477           && subreg_lowpart_p (XEXP (x, 0))
3478           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3479               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3480           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3481           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3482         {
3483           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3484
3485           x = gen_rtx (ROTATE, inner_mode,
3486                        gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3487                        XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3488           return gen_lowpart_for_combine (mode, x);
3489         }
3490
3491       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3492          reversing the comparison code if valid.  */
3493       if (STORE_FLAG_VALUE == -1
3494           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3495           && reversible_comparison_p (XEXP (x, 0)))
3496         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3497                                 mode, XEXP (XEXP (x, 0), 0),
3498                                 XEXP (XEXP (x, 0), 1));
3499
3500       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3501          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3502          perform the above simplification.  */
3503
3504       if (STORE_FLAG_VALUE == -1
3505           && XEXP (x, 1) == const1_rtx
3506           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3507           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3508           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3509         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3510
3511       /* Apply De Morgan's laws to reduce number of patterns for machines
3512          with negating logical insns (and-not, nand, etc.).  If result has
3513          only one NOT, put it first, since that is how the patterns are
3514          coded.  */
3515
3516       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3517         {
3518          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3519
3520          if (GET_CODE (in1) == NOT)
3521            in1 = XEXP (in1, 0);
3522          else
3523            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3524
3525          if (GET_CODE (in2) == NOT)
3526            in2 = XEXP (in2, 0);
3527          else if (GET_CODE (in2) == CONST_INT
3528                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3529            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3530          else
3531            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3532
3533          if (GET_CODE (in2) == NOT)
3534            {
3535              rtx tem = in2;
3536              in2 = in1; in1 = tem;
3537            }
3538
3539          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3540                                  mode, in1, in2);
3541        }
3542       break;
3543
3544     case NEG:
3545       /* (neg (plus X 1)) can become (not X).  */
3546       if (GET_CODE (XEXP (x, 0)) == PLUS
3547           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3548         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3549
3550       /* Similarly, (neg (not X)) is (plus X 1).  */
3551       if (GET_CODE (XEXP (x, 0)) == NOT)
3552         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3553
3554       /* (neg (minus X Y)) can become (minus Y X).  */
3555       if (GET_CODE (XEXP (x, 0)) == MINUS
3556           && (! FLOAT_MODE_P (mode)
3557               /* x-y != -(y-x) with IEEE floating point.  */
3558               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3559               || flag_fast_math))
3560         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3561                            XEXP (XEXP (x, 0), 0));
3562
3563       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3564       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3565           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3566         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3567
3568       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3569          if we can then eliminate the NEG (e.g.,
3570          if the operand is a constant).  */
3571
3572       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3573         {
3574           temp = simplify_unary_operation (NEG, mode,
3575                                            XEXP (XEXP (x, 0), 0), mode);
3576           if (temp)
3577             {
3578               SUBST (XEXP (XEXP (x, 0), 0), temp);
3579               return XEXP (x, 0);
3580             }
3581         }
3582
3583       temp = expand_compound_operation (XEXP (x, 0));
3584
3585       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3586          replaced by (lshiftrt X C).  This will convert
3587          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3588
3589       if (GET_CODE (temp) == ASHIFTRT
3590           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3591           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3592         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3593                                      INTVAL (XEXP (temp, 1)));
3594
3595       /* If X has only a single bit that might be nonzero, say, bit I, convert
3596          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3597          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3598          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3599          or a SUBREG of one since we'd be making the expression more
3600          complex if it was just a register.  */
3601
3602       if (GET_CODE (temp) != REG
3603           && ! (GET_CODE (temp) == SUBREG
3604                 && GET_CODE (SUBREG_REG (temp)) == REG)
3605           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3606         {
3607           rtx temp1 = simplify_shift_const
3608             (NULL_RTX, ASHIFTRT, mode,
3609              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3610                                    GET_MODE_BITSIZE (mode) - 1 - i),
3611              GET_MODE_BITSIZE (mode) - 1 - i);
3612
3613           /* If all we did was surround TEMP with the two shifts, we
3614              haven't improved anything, so don't use it.  Otherwise,
3615              we are better off with TEMP1.  */
3616           if (GET_CODE (temp1) != ASHIFTRT
3617               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3618               || XEXP (XEXP (temp1, 0), 0) != temp)
3619             return temp1;
3620         }
3621       break;
3622
3623     case TRUNCATE:
3624       /* We can't handle truncation to a partial integer mode here
3625          because we don't know the real bitsize of the partial
3626          integer mode.  */
3627       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3628         break;
3629
3630       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3631         SUBST (XEXP (x, 0),
3632                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3633                               GET_MODE_MASK (mode), NULL_RTX, 0));
3634
3635       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3636       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3637            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3638           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3639         return XEXP (XEXP (x, 0), 0);
3640
3641       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3642          (OP:SI foo:SI) if OP is NEG or ABS.  */
3643       if ((GET_CODE (XEXP (x, 0)) == ABS
3644            || GET_CODE (XEXP (x, 0)) == NEG)
3645           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3646               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3647           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3648         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3649                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3650
3651       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3652          (truncate:SI x).  */
3653       if (GET_CODE (XEXP (x, 0)) == SUBREG
3654           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3655           && subreg_lowpart_p (XEXP (x, 0)))
3656         return SUBREG_REG (XEXP (x, 0));
3657
3658       /* If we know that the value is already truncated, we can
3659          replace the TRUNCATE with a SUBREG.  */
3660       if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3661           && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3662               &~ GET_MODE_MASK (mode)) == 0)
3663         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3664
3665       /* A truncate of a comparison can be replaced with a subreg if
3666          STORE_FLAG_VALUE permits.  This is like the previous test,
3667          but it works even if the comparison is done in a mode larger
3668          than HOST_BITS_PER_WIDE_INT.  */
3669       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3670           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3671           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3672         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3673
3674       /* Similarly, a truncate of a register whose value is a
3675          comparison can be replaced with a subreg if STORE_FLAG_VALUE
3676          permits.  */
3677       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3678           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3679           && (temp = get_last_value (XEXP (x, 0)))
3680           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3681         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3682
3683       break;
3684
3685     case FLOAT_TRUNCATE:
3686       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
3687       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3688           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3689         return XEXP (XEXP (x, 0), 0);
3690
3691       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3692          (OP:SF foo:SF) if OP is NEG or ABS.  */
3693       if ((GET_CODE (XEXP (x, 0)) == ABS
3694            || GET_CODE (XEXP (x, 0)) == NEG)
3695           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3696           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3697         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3698                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3699
3700       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3701          is (float_truncate:SF x).  */
3702       if (GET_CODE (XEXP (x, 0)) == SUBREG
3703           && subreg_lowpart_p (XEXP (x, 0))
3704           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3705         return SUBREG_REG (XEXP (x, 0));
3706       break;
3707
3708 #ifdef HAVE_cc0
3709     case COMPARE:
3710       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3711          using cc0, in which case we want to leave it as a COMPARE
3712          so we can distinguish it from a register-register-copy.  */
3713       if (XEXP (x, 1) == const0_rtx)
3714         return XEXP (x, 0);
3715
3716       /* In IEEE floating point, x-0 is not the same as x.  */
3717       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3718            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3719            || flag_fast_math)
3720           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3721         return XEXP (x, 0);
3722       break;
3723 #endif
3724
3725     case CONST:
3726       /* (const (const X)) can become (const X).  Do it this way rather than
3727          returning the inner CONST since CONST can be shared with a
3728          REG_EQUAL note.  */
3729       if (GET_CODE (XEXP (x, 0)) == CONST)
3730         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3731       break;
3732
3733 #ifdef HAVE_lo_sum
3734     case LO_SUM:
3735       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
3736          can add in an offset.  find_split_point will split this address up
3737          again if it doesn't match.  */
3738       if (GET_CODE (XEXP (x, 0)) == HIGH
3739           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3740         return XEXP (x, 1);
3741       break;
3742 #endif
3743
3744     case PLUS:
3745       /* If we have (plus (plus (A const) B)), associate it so that CONST is
3746          outermost.  That's because that's the way indexed addresses are
3747          supposed to appear.  This code used to check many more cases, but
3748          they are now checked elsewhere.  */
3749       if (GET_CODE (XEXP (x, 0)) == PLUS
3750           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3751         return gen_binary (PLUS, mode,
3752                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3753                                        XEXP (x, 1)),
3754                            XEXP (XEXP (x, 0), 1));
3755
3756       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3757          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3758          bit-field and can be replaced by either a sign_extend or a
3759          sign_extract.  The `and' may be a zero_extend.  */
3760       if (GET_CODE (XEXP (x, 0)) == XOR
3761           && GET_CODE (XEXP (x, 1)) == CONST_INT
3762           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3763           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3764           && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3765           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3766           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3767                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3768                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3769                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3770               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3771                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3772                       == i + 1))))
3773         return simplify_shift_const
3774           (NULL_RTX, ASHIFTRT, mode,
3775            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3776                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
3777                                  GET_MODE_BITSIZE (mode) - (i + 1)),
3778            GET_MODE_BITSIZE (mode) - (i + 1));
3779
3780       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3781          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3782          is 1.  This produces better code than the alternative immediately
3783          below.  */
3784       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3785           && reversible_comparison_p (XEXP (x, 0))
3786           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3787               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3788         return
3789           gen_unary (NEG, mode, mode,
3790                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3791                                  mode, XEXP (XEXP (x, 0), 0),
3792                                  XEXP (XEXP (x, 0), 1)));
3793
3794       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3795          can become (ashiftrt (ashift (xor x 1) C) C) where C is
3796          the bitsize of the mode - 1.  This allows simplification of
3797          "a = (b & 8) == 0;"  */
3798       if (XEXP (x, 1) == constm1_rtx
3799           && GET_CODE (XEXP (x, 0)) != REG
3800           && ! (GET_CODE (XEXP (x,0)) == SUBREG
3801                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3802           && nonzero_bits (XEXP (x, 0), mode) == 1)
3803         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3804            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3805                                  gen_rtx_combine (XOR, mode,
3806                                                   XEXP (x, 0), const1_rtx),
3807                                  GET_MODE_BITSIZE (mode) - 1),
3808            GET_MODE_BITSIZE (mode) - 1);
3809
3810       /* If we are adding two things that have no bits in common, convert
3811          the addition into an IOR.  This will often be further simplified,
3812          for example in cases like ((a & 1) + (a & 2)), which can
3813          become a & 3.  */
3814
3815       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3816           && (nonzero_bits (XEXP (x, 0), mode)
3817               & nonzero_bits (XEXP (x, 1), mode)) == 0)
3818         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3819       break;
3820
3821     case MINUS:
3822       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3823          by reversing the comparison code if valid.  */
3824       if (STORE_FLAG_VALUE == 1
3825           && XEXP (x, 0) == const1_rtx
3826           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3827           && reversible_comparison_p (XEXP (x, 1)))
3828         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3829                            mode, XEXP (XEXP (x, 1), 0),
3830                                 XEXP (XEXP (x, 1), 1));
3831
3832       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3833          (and <foo> (const_int pow2-1))  */
3834       if (GET_CODE (XEXP (x, 1)) == AND
3835           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3836           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3837           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3838         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3839                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3840
3841       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3842          integers.  */
3843       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3844         return gen_binary (MINUS, mode,
3845                            gen_binary (MINUS, mode, XEXP (x, 0),
3846                                        XEXP (XEXP (x, 1), 0)),
3847                            XEXP (XEXP (x, 1), 1));
3848       break;
3849
3850     case MULT:
3851       /* If we have (mult (plus A B) C), apply the distributive law and then
3852          the inverse distributive law to see if things simplify.  This
3853          occurs mostly in addresses, often when unrolling loops.  */
3854
3855       if (GET_CODE (XEXP (x, 0)) == PLUS)
3856         {
3857           x = apply_distributive_law
3858             (gen_binary (PLUS, mode,
3859                          gen_binary (MULT, mode,
3860                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3861                          gen_binary (MULT, mode,
3862                                      XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3863
3864           if (GET_CODE (x) != MULT)
3865             return x;
3866         }
3867       break;
3868
3869     case UDIV:
3870       /* If this is a divide by a power of two, treat it as a shift if
3871          its first operand is a shift.  */
3872       if (GET_CODE (XEXP (x, 1)) == CONST_INT
3873           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3874           && (GET_CODE (XEXP (x, 0)) == ASHIFT
3875               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3876               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3877               || GET_CODE (XEXP (x, 0)) == ROTATE
3878               || GET_CODE (XEXP (x, 0)) == ROTATERT))
3879         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3880       break;
3881
3882     case EQ:  case NE:
3883     case GT:  case GTU:  case GE:  case GEU:
3884     case LT:  case LTU:  case LE:  case LEU:
3885       /* If the first operand is a condition code, we can't do anything
3886          with it.  */
3887       if (GET_CODE (XEXP (x, 0)) == COMPARE
3888           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3889 #ifdef HAVE_cc0
3890               && XEXP (x, 0) != cc0_rtx
3891 #endif
3892                ))
3893         {
3894           rtx op0 = XEXP (x, 0);
3895           rtx op1 = XEXP (x, 1);
3896           enum rtx_code new_code;
3897
3898           if (GET_CODE (op0) == COMPARE)
3899             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3900
3901           /* Simplify our comparison, if possible.  */
3902           new_code = simplify_comparison (code, &op0, &op1);
3903
3904           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3905              if only the low-order bit is possibly nonzero in X (such as when
3906              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
3907              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
3908              known to be either 0 or -1, NE becomes a NEG and EQ becomes
3909              (plus X 1).
3910
3911              Remove any ZERO_EXTRACT we made when thinking this was a
3912              comparison.  It may now be simpler to use, e.g., an AND.  If a
3913              ZERO_EXTRACT is indeed appropriate, it will be placed back by
3914              the call to make_compound_operation in the SET case.  */
3915
3916           if (STORE_FLAG_VALUE == 1
3917               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3918               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3919             return gen_lowpart_for_combine (mode,
3920                                             expand_compound_operation (op0));
3921
3922           else if (STORE_FLAG_VALUE == 1
3923                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3924                    && op1 == const0_rtx
3925                    && (num_sign_bit_copies (op0, mode)
3926                        == GET_MODE_BITSIZE (mode)))
3927             {
3928               op0 = expand_compound_operation (op0);
3929               return gen_unary (NEG, mode, mode,
3930                                 gen_lowpart_for_combine (mode, op0));
3931             }
3932
3933           else if (STORE_FLAG_VALUE == 1
3934                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3935                    && op1 == const0_rtx
3936                    && nonzero_bits (op0, mode) == 1)
3937             {
3938               op0 = expand_compound_operation (op0);
3939               return gen_binary (XOR, mode,
3940                                  gen_lowpart_for_combine (mode, op0),
3941                                  const1_rtx);
3942             }
3943
3944           else if (STORE_FLAG_VALUE == 1
3945                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3946                    && op1 == const0_rtx
3947                    && (num_sign_bit_copies (op0, mode)
3948                        == GET_MODE_BITSIZE (mode)))
3949             {
3950               op0 = expand_compound_operation (op0);
3951               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3952             }
3953
3954           /* If STORE_FLAG_VALUE is -1, we have cases similar to
3955              those above.  */
3956           if (STORE_FLAG_VALUE == -1
3957               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3958               && op1 == const0_rtx
3959               && (num_sign_bit_copies (op0, mode)
3960                   == GET_MODE_BITSIZE (mode)))
3961             return gen_lowpart_for_combine (mode,
3962                                             expand_compound_operation (op0));
3963
3964           else if (STORE_FLAG_VALUE == -1
3965                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3966                    && op1 == const0_rtx
3967                    && nonzero_bits (op0, mode) == 1)
3968             {
3969               op0 = expand_compound_operation (op0);
3970               return gen_unary (NEG, mode, mode,
3971                                 gen_lowpart_for_combine (mode, op0));
3972             }
3973
3974           else if (STORE_FLAG_VALUE == -1
3975                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3976                    && op1 == const0_rtx
3977                    && (num_sign_bit_copies (op0, mode)
3978                        == GET_MODE_BITSIZE (mode)))
3979             {
3980               op0 = expand_compound_operation (op0);
3981               return gen_unary (NOT, mode, mode,
3982                                 gen_lowpart_for_combine (mode, op0));
3983             }
3984
3985           /* If X is 0/1, (eq X 0) is X-1.  */
3986           else if (STORE_FLAG_VALUE == -1
3987                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3988                    && op1 == const0_rtx
3989                    && nonzero_bits (op0, mode) == 1)
3990             {
3991               op0 = expand_compound_operation (op0);
3992               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3993             }
3994
3995           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3996              one bit that might be nonzero, we can convert (ne x 0) to
3997              (ashift x c) where C puts the bit in the sign bit.  Remove any
3998              AND with STORE_FLAG_VALUE when we are done, since we are only
3999              going to test the sign bit.  */
4000           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4001               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4002               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4003                   == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4004               && op1 == const0_rtx
4005               && mode == GET_MODE (op0)
4006               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4007             {
4008               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4009                                         expand_compound_operation (op0),
4010                                         GET_MODE_BITSIZE (mode) - 1 - i);
4011               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4012                 return XEXP (x, 0);
4013               else
4014                 return x;
4015             }
4016
4017           /* If the code changed, return a whole new comparison.  */
4018           if (new_code != code)
4019             return gen_rtx_combine (new_code, mode, op0, op1);
4020
4021           /* Otherwise, keep this operation, but maybe change its operands.
4022              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4023           SUBST (XEXP (x, 0), op0);
4024           SUBST (XEXP (x, 1), op1);
4025         }
4026       break;
4027
4028     case IF_THEN_ELSE:
4029       return simplify_if_then_else (x);
4030
4031     case ZERO_EXTRACT:
4032     case SIGN_EXTRACT:
4033     case ZERO_EXTEND:
4034     case SIGN_EXTEND:
4035       /* If we are processing SET_DEST, we are done.  */
4036       if (in_dest)
4037         return x;
4038
4039       return expand_compound_operation (x);
4040
4041     case SET:
4042       return simplify_set (x);
4043
4044     case AND:
4045     case IOR:
4046     case XOR:
4047       return simplify_logical (x, last);
4048
4049     case ABS:
4050       /* (abs (neg <foo>)) -> (abs <foo>) */
4051       if (GET_CODE (XEXP (x, 0)) == NEG)
4052         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4053
4054       /* If operand is something known to be positive, ignore the ABS.  */
4055       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4056           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4057                <= HOST_BITS_PER_WIDE_INT)
4058               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4059                    & ((HOST_WIDE_INT) 1
4060                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4061                   == 0)))
4062         return XEXP (x, 0);
4063
4064
4065       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4066       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4067         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4068
4069       break;
4070
4071     case FFS:
4072       /* (ffs (*_extend <X>)) = (ffs <X>) */
4073       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4074           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4075         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4076       break;
4077
4078     case FLOAT:
4079       /* (float (sign_extend <X>)) = (float <X>).  */
4080       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4081         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4082       break;
4083
4084     case ASHIFT:
4085     case LSHIFTRT:
4086     case ASHIFTRT:
4087     case ROTATE:
4088     case ROTATERT:
4089       /* If this is a shift by a constant amount, simplify it.  */
4090       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4091         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4092                                      INTVAL (XEXP (x, 1)));
4093
4094 #ifdef SHIFT_COUNT_TRUNCATED
4095       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4096         SUBST (XEXP (x, 1),
4097                force_to_mode (XEXP (x, 1), GET_MODE (x),
4098                               ((HOST_WIDE_INT) 1
4099                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4100                               - 1,
4101                               NULL_RTX, 0));
4102 #endif
4103
4104       break;
4105
4106     default:
4107       break;
4108     }
4109
4110   return x;
4111 }
4112 \f
4113 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4114
4115 static rtx
4116 simplify_if_then_else (x)
4117      rtx x;
4118 {
4119   enum machine_mode mode = GET_MODE (x);
4120   rtx cond = XEXP (x, 0);
4121   rtx true = XEXP (x, 1);
4122   rtx false = XEXP (x, 2);
4123   enum rtx_code true_code = GET_CODE (cond);
4124   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4125   rtx temp;
4126   int i;
4127
4128   /* Simplify storing of the truth value.  */
4129   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4130     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4131
4132   /* Also when the truth value has to be reversed.  */
4133   if (comparison_p && reversible_comparison_p (cond)
4134       && true == const0_rtx && false == const_true_rtx)
4135     return gen_binary (reverse_condition (true_code),
4136                        mode, XEXP (cond, 0), XEXP (cond, 1));
4137
4138   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4139      in it is being compared against certain values.  Get the true and false
4140      comparisons and see if that says anything about the value of each arm.  */
4141
4142   if (comparison_p && reversible_comparison_p (cond)
4143       && GET_CODE (XEXP (cond, 0)) == REG)
4144     {
4145       HOST_WIDE_INT nzb;
4146       rtx from = XEXP (cond, 0);
4147       enum rtx_code false_code = reverse_condition (true_code);
4148       rtx true_val = XEXP (cond, 1);
4149       rtx false_val = true_val;
4150       int swapped = 0;
4151
4152       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4153
4154       if (false_code == EQ)
4155         {
4156           swapped = 1, true_code = EQ, false_code = NE;
4157           temp = true, true = false, false = temp;
4158         }
4159
4160       /* If we are comparing against zero and the expression being tested has
4161          only a single bit that might be nonzero, that is its value when it is
4162          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4163
4164       if (true_code == EQ && true_val == const0_rtx
4165           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4166         false_code = EQ, false_val = GEN_INT (nzb);
4167       else if (true_code == EQ && true_val == const0_rtx
4168                && (num_sign_bit_copies (from, GET_MODE (from))
4169                    == GET_MODE_BITSIZE (GET_MODE (from))))
4170         false_code = EQ, false_val = constm1_rtx;
4171
4172       /* Now simplify an arm if we know the value of the register in the
4173          branch and it is used in the arm.  Be careful due to the potential
4174          of locally-shared RTL.  */
4175
4176       if (reg_mentioned_p (from, true))
4177         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4178                       pc_rtx, pc_rtx, 0, 0);
4179       if (reg_mentioned_p (from, false))
4180         false = subst (known_cond (copy_rtx (false), false_code,
4181                                    from, false_val),
4182                        pc_rtx, pc_rtx, 0, 0);
4183
4184       SUBST (XEXP (x, 1), swapped ? false : true);
4185       SUBST (XEXP (x, 2), swapped ? true : false);
4186
4187       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4188     }
4189
4190   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4191      reversed, do so to avoid needing two sets of patterns for
4192      subtract-and-branch insns.  Similarly if we have a constant in the true
4193      arm, the false arm is the same as the first operand of the comparison, or
4194      the false arm is more complicated than the true arm.  */
4195
4196   if (comparison_p && reversible_comparison_p (cond)
4197       && (true == pc_rtx
4198           || (CONSTANT_P (true)
4199               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4200           || true == const0_rtx
4201           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4202               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4203           || (GET_CODE (true) == SUBREG
4204               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4205               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4206           || reg_mentioned_p (true, false)
4207           || rtx_equal_p (false, XEXP (cond, 0))))
4208     {
4209       true_code = reverse_condition (true_code);
4210       SUBST (XEXP (x, 0),
4211              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4212                          XEXP (cond, 1)));
4213
4214       SUBST (XEXP (x, 1), false);
4215       SUBST (XEXP (x, 2), true);
4216
4217       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4218
4219       /* It is possible that the conditional has been simplified out.  */
4220       true_code = GET_CODE (cond);
4221       comparison_p = GET_RTX_CLASS (true_code) == '<';
4222     }
4223
4224   /* If the two arms are identical, we don't need the comparison.  */
4225
4226   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4227     return true;
4228
4229   /* Convert a == b ? b : a to "a".  */
4230   if (true_code == EQ && ! side_effects_p (cond)
4231       && rtx_equal_p (XEXP (cond, 0), false)
4232       && rtx_equal_p (XEXP (cond, 1), true))
4233     return false;
4234   else if (true_code == NE && ! side_effects_p (cond)
4235            && rtx_equal_p (XEXP (cond, 0), true)
4236            && rtx_equal_p (XEXP (cond, 1), false))
4237     return true;
4238
4239   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4240
4241   if (GET_MODE_CLASS (mode) == MODE_INT
4242       && GET_CODE (false) == NEG
4243       && rtx_equal_p (true, XEXP (false, 0))
4244       && comparison_p
4245       && rtx_equal_p (true, XEXP (cond, 0))
4246       && ! side_effects_p (true))
4247     switch (true_code)
4248       {
4249       case GT:
4250       case GE:
4251         return gen_unary (ABS, mode, mode, true);
4252       case LT:
4253       case LE:
4254         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4255     default:
4256       break;
4257       }
4258
4259   /* Look for MIN or MAX.  */
4260
4261   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4262       && comparison_p
4263       && rtx_equal_p (XEXP (cond, 0), true)
4264       && rtx_equal_p (XEXP (cond, 1), false)
4265       && ! side_effects_p (cond))
4266     switch (true_code)
4267       {
4268       case GE:
4269       case GT:
4270         return gen_binary (SMAX, mode, true, false);
4271       case LE:
4272       case LT:
4273         return gen_binary (SMIN, mode, true, false);
4274       case GEU:
4275       case GTU:
4276         return gen_binary (UMAX, mode, true, false);
4277       case LEU:
4278       case LTU:
4279         return gen_binary (UMIN, mode, true, false);
4280       default:
4281         break;
4282       }
4283
4284   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4285      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4286      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4287      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4288      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4289      neither 1 or -1, but it isn't worth checking for.  */
4290
4291   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4292       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4293     {
4294       rtx t = make_compound_operation (true, SET);
4295       rtx f = make_compound_operation (false, SET);
4296       rtx cond_op0 = XEXP (cond, 0);
4297       rtx cond_op1 = XEXP (cond, 1);
4298       enum rtx_code op, extend_op = NIL;
4299       enum machine_mode m = mode;
4300       rtx z = 0, c1;
4301
4302       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4303            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4304            || GET_CODE (t) == ASHIFT
4305            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4306           && rtx_equal_p (XEXP (t, 0), f))
4307         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4308
4309       /* If an identity-zero op is commutative, check whether there
4310          would be a match if we swapped the operands.  */
4311       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4312                 || GET_CODE (t) == XOR)
4313                && rtx_equal_p (XEXP (t, 1), f))
4314         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4315       else if (GET_CODE (t) == SIGN_EXTEND
4316                && (GET_CODE (XEXP (t, 0)) == PLUS
4317                    || GET_CODE (XEXP (t, 0)) == MINUS
4318                    || GET_CODE (XEXP (t, 0)) == IOR
4319                    || GET_CODE (XEXP (t, 0)) == XOR
4320                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4321                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4322                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4323                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4324                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4325                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4326                && (num_sign_bit_copies (f, GET_MODE (f))
4327                    > (GET_MODE_BITSIZE (mode)
4328                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4329         {
4330           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4331           extend_op = SIGN_EXTEND;
4332           m = GET_MODE (XEXP (t, 0));
4333         }
4334       else if (GET_CODE (t) == SIGN_EXTEND
4335                && (GET_CODE (XEXP (t, 0)) == PLUS
4336                    || GET_CODE (XEXP (t, 0)) == IOR
4337                    || GET_CODE (XEXP (t, 0)) == XOR)
4338                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4339                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4340                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4341                && (num_sign_bit_copies (f, GET_MODE (f))
4342                    > (GET_MODE_BITSIZE (mode)
4343                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4344         {
4345           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4346           extend_op = SIGN_EXTEND;
4347           m = GET_MODE (XEXP (t, 0));
4348         }
4349       else if (GET_CODE (t) == ZERO_EXTEND
4350                && (GET_CODE (XEXP (t, 0)) == PLUS
4351                    || GET_CODE (XEXP (t, 0)) == MINUS
4352                    || GET_CODE (XEXP (t, 0)) == IOR
4353                    || GET_CODE (XEXP (t, 0)) == XOR
4354                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4355                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4356                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4357                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4358                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4359                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4360                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4361                && ((nonzero_bits (f, GET_MODE (f))
4362                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4363                    == 0))
4364         {
4365           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4366           extend_op = ZERO_EXTEND;
4367           m = GET_MODE (XEXP (t, 0));
4368         }
4369       else if (GET_CODE (t) == ZERO_EXTEND
4370                && (GET_CODE (XEXP (t, 0)) == PLUS
4371                    || GET_CODE (XEXP (t, 0)) == IOR
4372                    || GET_CODE (XEXP (t, 0)) == XOR)
4373                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4374                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4375                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4376                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4377                && ((nonzero_bits (f, GET_MODE (f))
4378                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4379                    == 0))
4380         {
4381           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4382           extend_op = ZERO_EXTEND;
4383           m = GET_MODE (XEXP (t, 0));
4384         }
4385
4386       if (z)
4387         {
4388           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4389                         pc_rtx, pc_rtx, 0, 0);
4390           temp = gen_binary (MULT, m, temp,
4391                              gen_binary (MULT, m, c1, const_true_rtx));
4392           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4393           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4394
4395           if (extend_op != NIL)
4396             temp = gen_unary (extend_op, mode, m, temp);
4397
4398           return temp;
4399         }
4400     }
4401
4402   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4403      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4404      negation of a single bit, we can convert this operation to a shift.  We
4405      can actually do this more generally, but it doesn't seem worth it.  */
4406
4407   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4408       && false == const0_rtx && GET_CODE (true) == CONST_INT
4409       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4410            && (i = exact_log2 (INTVAL (true))) >= 0)
4411           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4412                == GET_MODE_BITSIZE (mode))
4413               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4414     return
4415       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4416                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4417
4418   return x;
4419 }
4420 \f
4421 /* Simplify X, a SET expression.  Return the new expression.  */
4422
4423 static rtx
4424 simplify_set (x)
4425      rtx x;
4426 {
4427   rtx src = SET_SRC (x);
4428   rtx dest = SET_DEST (x);
4429   enum machine_mode mode
4430     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4431   rtx other_insn;
4432   rtx *cc_use;
4433
4434   /* (set (pc) (return)) gets written as (return).  */
4435   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4436     return src;
4437
4438   /* Now that we know for sure which bits of SRC we are using, see if we can
4439      simplify the expression for the object knowing that we only need the
4440      low-order bits.  */
4441
4442   if (GET_MODE_CLASS (mode) == MODE_INT)
4443     src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4444
4445   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4446      the comparison result and try to simplify it unless we already have used
4447      undobuf.other_insn.  */
4448   if ((GET_CODE (src) == COMPARE
4449 #ifdef HAVE_cc0
4450        || dest == cc0_rtx
4451 #endif
4452        )
4453       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4454       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4455       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4456       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4457     {
4458       enum rtx_code old_code = GET_CODE (*cc_use);
4459       enum rtx_code new_code;
4460       rtx op0, op1;
4461       int other_changed = 0;
4462       enum machine_mode compare_mode = GET_MODE (dest);
4463
4464       if (GET_CODE (src) == COMPARE)
4465         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4466       else
4467         op0 = src, op1 = const0_rtx;
4468
4469       /* Simplify our comparison, if possible.  */
4470       new_code = simplify_comparison (old_code, &op0, &op1);
4471
4472 #ifdef EXTRA_CC_MODES
4473       /* If this machine has CC modes other than CCmode, check to see if we
4474          need to use a different CC mode here.  */
4475       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4476 #endif /* EXTRA_CC_MODES */
4477
4478 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4479       /* If the mode changed, we have to change SET_DEST, the mode in the
4480          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4481          a hard register, just build new versions with the proper mode.  If it
4482          is a pseudo, we lose unless it is only time we set the pseudo, in
4483          which case we can safely change its mode.  */
4484       if (compare_mode != GET_MODE (dest))
4485         {
4486           int regno = REGNO (dest);
4487           rtx new_dest = gen_rtx (REG, compare_mode, regno);
4488
4489           if (regno < FIRST_PSEUDO_REGISTER
4490               || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4491             {
4492               if (regno >= FIRST_PSEUDO_REGISTER)
4493                 SUBST (regno_reg_rtx[regno], new_dest);
4494
4495               SUBST (SET_DEST (x), new_dest);
4496               SUBST (XEXP (*cc_use, 0), new_dest);
4497               other_changed = 1;
4498
4499               dest = new_dest;
4500             }
4501         }
4502 #endif
4503
4504       /* If the code changed, we have to build a new comparison in
4505          undobuf.other_insn.  */
4506       if (new_code != old_code)
4507         {
4508           unsigned HOST_WIDE_INT mask;
4509
4510           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4511                                            dest, const0_rtx));
4512
4513           /* If the only change we made was to change an EQ into an NE or
4514              vice versa, OP0 has only one bit that might be nonzero, and OP1
4515              is zero, check if changing the user of the condition code will
4516              produce a valid insn.  If it won't, we can keep the original code
4517              in that insn by surrounding our operation with an XOR.  */
4518
4519           if (((old_code == NE && new_code == EQ)
4520                || (old_code == EQ && new_code == NE))
4521               && ! other_changed && op1 == const0_rtx
4522               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4523               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4524             {
4525               rtx pat = PATTERN (other_insn), note = 0;
4526               int scratches;
4527
4528               if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
4529                    && ! check_asm_operands (pat)))
4530                 {
4531                   PUT_CODE (*cc_use, old_code);
4532                   other_insn = 0;
4533
4534                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4535                 }
4536             }
4537
4538           other_changed = 1;
4539         }
4540
4541       if (other_changed)
4542         undobuf.other_insn = other_insn;
4543
4544 #ifdef HAVE_cc0
4545       /* If we are now comparing against zero, change our source if
4546          needed.  If we do not use cc0, we always have a COMPARE.  */
4547       if (op1 == const0_rtx && dest == cc0_rtx)
4548         {
4549           SUBST (SET_SRC (x), op0);
4550           src = op0;
4551         }
4552       else
4553 #endif
4554
4555       /* Otherwise, if we didn't previously have a COMPARE in the
4556          correct mode, we need one.  */
4557       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4558         {
4559           SUBST (SET_SRC (x),
4560                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4561           src = SET_SRC (x);
4562         }
4563       else
4564         {
4565           /* Otherwise, update the COMPARE if needed.  */
4566           SUBST (XEXP (src, 0), op0);
4567           SUBST (XEXP (src, 1), op1);
4568         }
4569     }
4570   else
4571     {
4572       /* Get SET_SRC in a form where we have placed back any
4573          compound expressions.  Then do the checks below.  */
4574       src = make_compound_operation (src, SET);
4575       SUBST (SET_SRC (x), src);
4576     }
4577
4578   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4579      and X being a REG or (subreg (reg)), we may be able to convert this to
4580      (set (subreg:m2 x) (op)).
4581
4582      We can always do this if M1 is narrower than M2 because that means that
4583      we only care about the low bits of the result.
4584
4585      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4586      perform a narrower operation that requested since the high-order bits will
4587      be undefined.  On machine where it is defined, this transformation is safe
4588      as long as M1 and M2 have the same number of words.  */
4589
4590   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4591       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4592       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4593            / UNITS_PER_WORD)
4594           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4595                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4596 #ifndef WORD_REGISTER_OPERATIONS
4597       && (GET_MODE_SIZE (GET_MODE (src))
4598           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4599 #endif
4600 #ifdef CLASS_CANNOT_CHANGE_SIZE
4601       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4602             && (TEST_HARD_REG_BIT
4603                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4604                  REGNO (dest)))
4605             && (GET_MODE_SIZE (GET_MODE (src))
4606                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4607 #endif
4608       && (GET_CODE (dest) == REG
4609           || (GET_CODE (dest) == SUBREG
4610               && GET_CODE (SUBREG_REG (dest)) == REG)))
4611     {
4612       SUBST (SET_DEST (x),
4613              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4614                                       dest));
4615       SUBST (SET_SRC (x), SUBREG_REG (src));
4616
4617       src = SET_SRC (x), dest = SET_DEST (x);
4618     }
4619
4620 #ifdef LOAD_EXTEND_OP
4621   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4622      would require a paradoxical subreg.  Replace the subreg with a
4623      zero_extend to avoid the reload that would otherwise be required.  */
4624
4625   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4626       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4627       && SUBREG_WORD (src) == 0
4628       && (GET_MODE_SIZE (GET_MODE (src))
4629           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4630       && GET_CODE (SUBREG_REG (src)) == MEM)
4631     {
4632       SUBST (SET_SRC (x),
4633              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4634                               GET_MODE (src), XEXP (src, 0)));
4635
4636       src = SET_SRC (x);
4637     }
4638 #endif
4639
4640   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4641      are comparing an item known to be 0 or -1 against 0, use a logical
4642      operation instead. Check for one of the arms being an IOR of the other
4643      arm with some value.  We compute three terms to be IOR'ed together.  In
4644      practice, at most two will be nonzero.  Then we do the IOR's.  */
4645
4646   if (GET_CODE (dest) != PC
4647       && GET_CODE (src) == IF_THEN_ELSE
4648       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4649       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4650       && XEXP (XEXP (src, 0), 1) == const0_rtx
4651       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4652 #ifdef HAVE_conditional_move
4653       && ! can_conditionally_move_p (GET_MODE (src))
4654 #endif
4655       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4656                                GET_MODE (XEXP (XEXP (src, 0), 0)))
4657           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4658       && ! side_effects_p (src))
4659     {
4660       rtx true = (GET_CODE (XEXP (src, 0)) == NE
4661                       ? XEXP (src, 1) : XEXP (src, 2));
4662       rtx false = (GET_CODE (XEXP (src, 0)) == NE
4663                    ? XEXP (src, 2) : XEXP (src, 1));
4664       rtx term1 = const0_rtx, term2, term3;
4665
4666       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4667         term1 = false, true = XEXP (true, 1), false = const0_rtx;
4668       else if (GET_CODE (true) == IOR
4669                && rtx_equal_p (XEXP (true, 1), false))
4670         term1 = false, true = XEXP (true, 0), false = const0_rtx;
4671       else if (GET_CODE (false) == IOR
4672                && rtx_equal_p (XEXP (false, 0), true))
4673         term1 = true, false = XEXP (false, 1), true = const0_rtx;
4674       else if (GET_CODE (false) == IOR
4675                && rtx_equal_p (XEXP (false, 1), true))
4676         term1 = true, false = XEXP (false, 0), true = const0_rtx;
4677
4678       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4679       term3 = gen_binary (AND, GET_MODE (src),
4680                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4681                                      XEXP (XEXP (src, 0), 0)),
4682                           false);
4683
4684       SUBST (SET_SRC (x),
4685              gen_binary (IOR, GET_MODE (src),
4686                          gen_binary (IOR, GET_MODE (src), term1, term2),
4687                          term3));
4688
4689       src = SET_SRC (x);
4690     }
4691
4692   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4693      whole thing fail.  */
4694   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4695     return src;
4696   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4697     return dest;
4698   else
4699     /* Convert this into a field assignment operation, if possible.  */
4700     return make_field_assignment (x);
4701 }
4702 \f
4703 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4704    result.  LAST is nonzero if this is the last retry.  */
4705
4706 static rtx
4707 simplify_logical (x, last)
4708      rtx x;
4709      int last;
4710 {
4711   enum machine_mode mode = GET_MODE (x);
4712   rtx op0 = XEXP (x, 0);
4713   rtx op1 = XEXP (x, 1);
4714
4715   switch (GET_CODE (x))
4716     {
4717     case AND:
4718       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4719          insn (and may simplify more).  */
4720       if (GET_CODE (op0) == XOR
4721           && rtx_equal_p (XEXP (op0, 0), op1)
4722           && ! side_effects_p (op1))
4723         x = gen_binary (AND, mode,
4724                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4725
4726       if (GET_CODE (op0) == XOR
4727           && rtx_equal_p (XEXP (op0, 1), op1)
4728           && ! side_effects_p (op1))
4729         x = gen_binary (AND, mode,
4730                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4731
4732       /* Similarly for (~ (A ^ B)) & A.  */
4733       if (GET_CODE (op0) == NOT
4734           && GET_CODE (XEXP (op0, 0)) == XOR
4735           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4736           && ! side_effects_p (op1))
4737         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4738
4739       if (GET_CODE (op0) == NOT
4740           && GET_CODE (XEXP (op0, 0)) == XOR
4741           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4742           && ! side_effects_p (op1))
4743         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4744
4745       if (GET_CODE (op1) == CONST_INT)
4746         {
4747           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4748
4749           /* If we have (ior (and (X C1) C2)) and the next restart would be
4750              the last, simplify this by making C1 as small as possible
4751              and then exit.  */
4752           if (last
4753               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4754               && GET_CODE (XEXP (op0, 1)) == CONST_INT
4755               && GET_CODE (op1) == CONST_INT)
4756             return gen_binary (IOR, mode,
4757                                gen_binary (AND, mode, XEXP (op0, 0),
4758                                            GEN_INT (INTVAL (XEXP (op0, 1))
4759                                                     & ~ INTVAL (op1))), op1);
4760
4761           if (GET_CODE (x) != AND)
4762             return x;
4763
4764           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4765               || GET_RTX_CLASS (GET_CODE (x)) == '2')
4766             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4767         }
4768
4769       /* Convert (A | B) & A to A.  */
4770       if (GET_CODE (op0) == IOR
4771           && (rtx_equal_p (XEXP (op0, 0), op1)
4772               || rtx_equal_p (XEXP (op0, 1), op1))
4773           && ! side_effects_p (XEXP (op0, 0))
4774           && ! side_effects_p (XEXP (op0, 1)))
4775         return op1;
4776
4777       /* In the following group of tests (and those in case IOR below),
4778          we start with some combination of logical operations and apply
4779          the distributive law followed by the inverse distributive law.
4780          Most of the time, this results in no change.  However, if some of
4781          the operands are the same or inverses of each other, simplifications
4782          will result.
4783
4784          For example, (and (ior A B) (not B)) can occur as the result of
4785          expanding a bit field assignment.  When we apply the distributive
4786          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4787          which then simplifies to (and (A (not B))).
4788
4789          If we have (and (ior A B) C), apply the distributive law and then
4790          the inverse distributive law to see if things simplify.  */
4791
4792       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4793         {
4794           x = apply_distributive_law
4795             (gen_binary (GET_CODE (op0), mode,
4796                          gen_binary (AND, mode, XEXP (op0, 0), op1),
4797                          gen_binary (AND, mode, XEXP (op0, 1), op1)));
4798           if (GET_CODE (x) != AND)
4799             return x;
4800         }
4801
4802       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4803         return apply_distributive_law
4804           (gen_binary (GET_CODE (op1), mode,
4805                        gen_binary (AND, mode, XEXP (op1, 0), op0),
4806                        gen_binary (AND, mode, XEXP (op1, 1), op0)));
4807
4808       /* Similarly, taking advantage of the fact that
4809          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
4810
4811       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4812         return apply_distributive_law
4813           (gen_binary (XOR, mode,
4814                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4815                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4816
4817       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4818         return apply_distributive_law
4819           (gen_binary (XOR, mode,
4820                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4821                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4822       break;
4823
4824     case IOR:
4825       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
4826       if (GET_CODE (op1) == CONST_INT
4827           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4828           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4829         return op1;
4830
4831       /* Convert (A & B) | A to A.  */
4832       if (GET_CODE (op0) == AND
4833           && (rtx_equal_p (XEXP (op0, 0), op1)
4834               || rtx_equal_p (XEXP (op0, 1), op1))
4835           && ! side_effects_p (XEXP (op0, 0))
4836           && ! side_effects_p (XEXP (op0, 1)))
4837         return op1;
4838
4839       /* If we have (ior (and A B) C), apply the distributive law and then
4840          the inverse distributive law to see if things simplify.  */
4841
4842       if (GET_CODE (op0) == AND)
4843         {
4844           x = apply_distributive_law
4845             (gen_binary (AND, mode,
4846                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
4847                          gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4848
4849           if (GET_CODE (x) != IOR)
4850             return x;
4851         }
4852
4853       if (GET_CODE (op1) == AND)
4854         {
4855           x = apply_distributive_law
4856             (gen_binary (AND, mode,
4857                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
4858                          gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4859
4860           if (GET_CODE (x) != IOR)
4861             return x;
4862         }
4863
4864       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4865          mode size to (rotate A CX).  */
4866
4867       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4868            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4869           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4870           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4871           && GET_CODE (XEXP (op1, 1)) == CONST_INT
4872           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4873               == GET_MODE_BITSIZE (mode)))
4874         return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4875                         (GET_CODE (op0) == ASHIFT
4876                          ? XEXP (op0, 1) : XEXP (op1, 1)));
4877
4878       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4879          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
4880          does not affect any of the bits in OP1, it can really be done
4881          as a PLUS and we can associate.  We do this by seeing if OP1
4882          can be safely shifted left C bits.  */
4883       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4884           && GET_CODE (XEXP (op0, 0)) == PLUS
4885           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4886           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4887           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4888         {
4889           int count = INTVAL (XEXP (op0, 1));
4890           HOST_WIDE_INT mask = INTVAL (op1) << count;
4891
4892           if (mask >> count == INTVAL (op1)
4893               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4894             {
4895               SUBST (XEXP (XEXP (op0, 0), 1),
4896                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4897               return op0;
4898             }
4899         }
4900       break;
4901
4902     case XOR:
4903       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4904          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4905          (NOT y).  */
4906       {
4907         int num_negated = 0;
4908
4909         if (GET_CODE (op0) == NOT)
4910           num_negated++, op0 = XEXP (op0, 0);
4911         if (GET_CODE (op1) == NOT)
4912           num_negated++, op1 = XEXP (op1, 0);
4913
4914         if (num_negated == 2)
4915           {
4916             SUBST (XEXP (x, 0), op0);
4917             SUBST (XEXP (x, 1), op1);
4918           }
4919         else if (num_negated == 1)
4920           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4921       }
4922
4923       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
4924          correspond to a machine insn or result in further simplifications
4925          if B is a constant.  */
4926
4927       if (GET_CODE (op0) == AND
4928           && rtx_equal_p (XEXP (op0, 1), op1)
4929           && ! side_effects_p (op1))
4930         return gen_binary (AND, mode,
4931                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4932                            op1);
4933
4934       else if (GET_CODE (op0) == AND
4935                && rtx_equal_p (XEXP (op0, 0), op1)
4936                && ! side_effects_p (op1))
4937         return gen_binary (AND, mode,
4938                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4939                            op1);
4940
4941       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4942          comparison if STORE_FLAG_VALUE is 1.  */
4943       if (STORE_FLAG_VALUE == 1
4944           && op1 == const1_rtx
4945           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4946           && reversible_comparison_p (op0))
4947         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4948                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4949
4950       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4951          is (lt foo (const_int 0)), so we can perform the above
4952          simplification if STORE_FLAG_VALUE is 1.  */
4953
4954       if (STORE_FLAG_VALUE == 1
4955           && op1 == const1_rtx
4956           && GET_CODE (op0) == LSHIFTRT
4957           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4958           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4959         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4960
4961       /* (xor (comparison foo bar) (const_int sign-bit))
4962          when STORE_FLAG_VALUE is the sign bit.  */
4963       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4964           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4965               == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4966           && op1 == const_true_rtx
4967           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4968           && reversible_comparison_p (op0))
4969         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4970                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4971       break;
4972
4973     default:
4974       abort ();
4975     }
4976
4977   return x;
4978 }
4979 \f
4980 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4981    operations" because they can be replaced with two more basic operations.
4982    ZERO_EXTEND is also considered "compound" because it can be replaced with
4983    an AND operation, which is simpler, though only one operation.
4984
4985    The function expand_compound_operation is called with an rtx expression
4986    and will convert it to the appropriate shifts and AND operations,
4987    simplifying at each stage.
4988
4989    The function make_compound_operation is called to convert an expression
4990    consisting of shifts and ANDs into the equivalent compound expression.
4991    It is the inverse of this function, loosely speaking.  */
4992
4993 static rtx
4994 expand_compound_operation (x)
4995      rtx x;
4996 {
4997   int pos = 0, len;
4998   int unsignedp = 0;
4999   int modewidth;
5000   rtx tem;
5001
5002   switch (GET_CODE (x))
5003     {
5004     case ZERO_EXTEND:
5005       unsignedp = 1;
5006     case SIGN_EXTEND:
5007       /* We can't necessarily use a const_int for a multiword mode;
5008          it depends on implicitly extending the value.
5009          Since we don't know the right way to extend it,
5010          we can't tell whether the implicit way is right.
5011
5012          Even for a mode that is no wider than a const_int,
5013          we can't win, because we need to sign extend one of its bits through
5014          the rest of it, and we don't know which bit.  */
5015       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5016         return x;
5017
5018       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5019          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5020          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5021          reloaded. If not for that, MEM's would very rarely be safe.
5022
5023          Reject MODEs bigger than a word, because we might not be able
5024          to reference a two-register group starting with an arbitrary register
5025          (and currently gen_lowpart might crash for a SUBREG).  */
5026
5027       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5028         return x;
5029
5030       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5031       /* If the inner object has VOIDmode (the only way this can happen
5032          is if it is a ASM_OPERANDS), we can't do anything since we don't
5033          know how much masking to do.  */
5034       if (len == 0)
5035         return x;
5036
5037       break;
5038
5039     case ZERO_EXTRACT:
5040       unsignedp = 1;
5041     case SIGN_EXTRACT:
5042       /* If the operand is a CLOBBER, just return it.  */
5043       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5044         return XEXP (x, 0);
5045
5046       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5047           || GET_CODE (XEXP (x, 2)) != CONST_INT
5048           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5049         return x;
5050
5051       len = INTVAL (XEXP (x, 1));
5052       pos = INTVAL (XEXP (x, 2));
5053
5054       /* If this goes outside the object being extracted, replace the object
5055          with a (use (mem ...)) construct that only combine understands
5056          and is used only for this purpose.  */
5057       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5058         SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5059
5060       if (BITS_BIG_ENDIAN)
5061         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5062
5063       break;
5064
5065     default:
5066       return x;
5067     }
5068
5069   /* We can optimize some special cases of ZERO_EXTEND.  */
5070   if (GET_CODE (x) == ZERO_EXTEND)
5071     {
5072       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5073          know that the last value didn't have any inappropriate bits
5074          set.  */
5075       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5076           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5077           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5078           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5079               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5080         return XEXP (XEXP (x, 0), 0);
5081
5082       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5083       if (GET_CODE (XEXP (x, 0)) == SUBREG
5084           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5085           && subreg_lowpart_p (XEXP (x, 0))
5086           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5087           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5088               & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5089         return SUBREG_REG (XEXP (x, 0));
5090
5091       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5092          is a comparison and STORE_FLAG_VALUE permits.  This is like
5093          the first case, but it works even when GET_MODE (x) is larger
5094          than HOST_WIDE_INT.  */
5095       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5096           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5097           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5098           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5099               <= HOST_BITS_PER_WIDE_INT)
5100           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5101               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5102         return XEXP (XEXP (x, 0), 0);
5103
5104       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5105       if (GET_CODE (XEXP (x, 0)) == SUBREG
5106           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5107           && subreg_lowpart_p (XEXP (x, 0))
5108           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5109           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5110               <= HOST_BITS_PER_WIDE_INT)
5111           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5112               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5113         return SUBREG_REG (XEXP (x, 0));
5114
5115       /* If sign extension is cheaper than zero extension, then use it
5116          if we know that no extraneous bits are set, and that the high
5117          bit is not set.  */
5118       if (flag_expensive_optimizations
5119           && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5120                && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5121                     & ~ (((unsigned HOST_WIDE_INT)
5122                           GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5123                          >> 1))
5124                    == 0))
5125               || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5126                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5127                       <= HOST_BITS_PER_WIDE_INT)
5128                   && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5129                        & ~ (((unsigned HOST_WIDE_INT)
5130                              GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5131                             >> 1))
5132                       == 0))))
5133         {
5134           rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5135
5136           if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5137             return expand_compound_operation (temp);
5138         }
5139     }
5140
5141   /* If we reach here, we want to return a pair of shifts.  The inner
5142      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5143      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5144      logical depending on the value of UNSIGNEDP.
5145
5146      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5147      converted into an AND of a shift.
5148
5149      We must check for the case where the left shift would have a negative
5150      count.  This can happen in a case like (x >> 31) & 255 on machines
5151      that can't shift by a constant.  On those machines, we would first
5152      combine the shift with the AND to produce a variable-position
5153      extraction.  Then the constant of 31 would be substituted in to produce
5154      a such a position.  */
5155
5156   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5157   if (modewidth >= pos - len)
5158     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5159                                 GET_MODE (x),
5160                                 simplify_shift_const (NULL_RTX, ASHIFT,
5161                                                       GET_MODE (x),
5162                                                       XEXP (x, 0),
5163                                                       modewidth - pos - len),
5164                                 modewidth - len);
5165
5166   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5167     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5168                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5169                                                         GET_MODE (x),
5170                                                         XEXP (x, 0), pos),
5171                                   ((HOST_WIDE_INT) 1 << len) - 1);
5172   else
5173     /* Any other cases we can't handle.  */
5174     return x;
5175
5176
5177   /* If we couldn't do this for some reason, return the original
5178      expression.  */
5179   if (GET_CODE (tem) == CLOBBER)
5180     return x;
5181
5182   return tem;
5183 }
5184 \f
5185 /* X is a SET which contains an assignment of one object into
5186    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5187    or certain SUBREGS). If possible, convert it into a series of
5188    logical operations.
5189
5190    We half-heartedly support variable positions, but do not at all
5191    support variable lengths.  */
5192
5193 static rtx
5194 expand_field_assignment (x)
5195      rtx x;
5196 {
5197   rtx inner;
5198   rtx pos;                      /* Always counts from low bit.  */
5199   int len;
5200   rtx mask;
5201   enum machine_mode compute_mode;
5202
5203   /* Loop until we find something we can't simplify.  */
5204   while (1)
5205     {
5206       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5207           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5208         {
5209           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5210           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5211           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5212         }
5213       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5214                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5215         {
5216           inner = XEXP (SET_DEST (x), 0);
5217           len = INTVAL (XEXP (SET_DEST (x), 1));
5218           pos = XEXP (SET_DEST (x), 2);
5219
5220           /* If the position is constant and spans the width of INNER,
5221              surround INNER  with a USE to indicate this.  */
5222           if (GET_CODE (pos) == CONST_INT
5223               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5224             inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5225
5226           if (BITS_BIG_ENDIAN)
5227             {
5228               if (GET_CODE (pos) == CONST_INT)
5229                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5230                                - INTVAL (pos));
5231               else if (GET_CODE (pos) == MINUS
5232                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5233                        && (INTVAL (XEXP (pos, 1))
5234                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5235                 /* If position is ADJUST - X, new position is X.  */
5236                 pos = XEXP (pos, 0);
5237               else
5238                 pos = gen_binary (MINUS, GET_MODE (pos),
5239                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5240                                            - len),
5241                                   pos);
5242             }
5243         }
5244
5245       /* A SUBREG between two modes that occupy the same numbers of words
5246          can be done by moving the SUBREG to the source.  */
5247       else if (GET_CODE (SET_DEST (x)) == SUBREG
5248                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5249                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5250                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5251                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5252         {
5253           x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5254                        gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5255                                                 SET_SRC (x)));
5256           continue;
5257         }
5258       else
5259         break;
5260
5261       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5262         inner = SUBREG_REG (inner);
5263
5264       compute_mode = GET_MODE (inner);
5265
5266       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5267       if (len < HOST_BITS_PER_WIDE_INT)
5268         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5269       else
5270         break;
5271
5272       /* Now compute the equivalent expression.  Make a copy of INNER
5273          for the SET_DEST in case it is a MEM into which we will substitute;
5274          we don't want shared RTL in that case.  */
5275       x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5276                    gen_binary (IOR, compute_mode,
5277                                gen_binary (AND, compute_mode,
5278                                            gen_unary (NOT, compute_mode,
5279                                                       compute_mode,
5280                                                       gen_binary (ASHIFT,
5281                                                                   compute_mode,
5282                                                                   mask, pos)),
5283                                            inner),
5284                                gen_binary (ASHIFT, compute_mode,
5285                                            gen_binary (AND, compute_mode,
5286                                                        gen_lowpart_for_combine
5287                                                        (compute_mode,
5288                                                         SET_SRC (x)),
5289                                                        mask),
5290                                            pos)));
5291     }
5292
5293   return x;
5294 }
5295 \f
5296 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5297    it is an RTX that represents a variable starting position; otherwise,
5298    POS is the (constant) starting bit position (counted from the LSB).
5299
5300    INNER may be a USE.  This will occur when we started with a bitfield
5301    that went outside the boundary of the object in memory, which is
5302    allowed on most machines.  To isolate this case, we produce a USE
5303    whose mode is wide enough and surround the MEM with it.  The only
5304    code that understands the USE is this routine.  If it is not removed,
5305    it will cause the resulting insn not to match.
5306
5307    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5308    signed reference.
5309
5310    IN_DEST is non-zero if this is a reference in the destination of a
5311    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5312    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5313    be used.
5314
5315    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5316    ZERO_EXTRACT should be built even for bits starting at bit 0.
5317
5318    MODE is the desired mode of the result (if IN_DEST == 0).
5319
5320    The result is an RTX for the extraction or NULL_RTX if the target
5321    can't handle it.  */
5322
5323 static rtx
5324 make_extraction (mode, inner, pos, pos_rtx, len,
5325                  unsignedp, in_dest, in_compare)
5326      enum machine_mode mode;
5327      rtx inner;
5328      int pos;
5329      rtx pos_rtx;
5330      int len;
5331      int unsignedp;
5332      int in_dest, in_compare;
5333 {
5334   /* This mode describes the size of the storage area
5335      to fetch the overall value from.  Within that, we
5336      ignore the POS lowest bits, etc.  */
5337   enum machine_mode is_mode = GET_MODE (inner);
5338   enum machine_mode inner_mode;
5339   enum machine_mode wanted_inner_mode = byte_mode;
5340   enum machine_mode wanted_inner_reg_mode = word_mode;
5341   enum machine_mode pos_mode = word_mode;
5342   enum machine_mode extraction_mode = word_mode;
5343   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5344   int spans_byte = 0;
5345   rtx new = 0;
5346   rtx orig_pos_rtx = pos_rtx;
5347   int orig_pos;
5348
5349   /* Get some information about INNER and get the innermost object.  */
5350   if (GET_CODE (inner) == USE)
5351     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5352     /* We don't need to adjust the position because we set up the USE
5353        to pretend that it was a full-word object.  */
5354     spans_byte = 1, inner = XEXP (inner, 0);
5355   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5356     {
5357       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5358          consider just the QI as the memory to extract from.
5359          The subreg adds or removes high bits; its mode is
5360          irrelevant to the meaning of this extraction,
5361          since POS and LEN count from the lsb.  */
5362       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5363         is_mode = GET_MODE (SUBREG_REG (inner));
5364       inner = SUBREG_REG (inner);
5365     }
5366
5367   inner_mode = GET_MODE (inner);
5368
5369   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5370     pos = INTVAL (pos_rtx), pos_rtx = 0;
5371
5372   /* See if this can be done without an extraction.  We never can if the
5373      width of the field is not the same as that of some integer mode. For
5374      registers, we can only avoid the extraction if the position is at the
5375      low-order bit and this is either not in the destination or we have the
5376      appropriate STRICT_LOW_PART operation available.
5377
5378      For MEM, we can avoid an extract if the field starts on an appropriate
5379      boundary and we can change the mode of the memory reference.  However,
5380      we cannot directly access the MEM if we have a USE and the underlying
5381      MEM is not TMODE.  This combination means that MEM was being used in a
5382      context where bits outside its mode were being referenced; that is only
5383      valid in bit-field insns.  */
5384
5385   if (tmode != BLKmode
5386       && ! (spans_byte && inner_mode != tmode)
5387       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5388            && GET_CODE (inner) != MEM
5389            && (! in_dest
5390                || (GET_CODE (inner) == REG
5391                    && (movstrict_optab->handlers[(int) tmode].insn_code
5392                        != CODE_FOR_nothing))))
5393           || (GET_CODE (inner) == MEM && pos_rtx == 0
5394               && (pos
5395                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5396                      : BITS_PER_UNIT)) == 0
5397               /* We can't do this if we are widening INNER_MODE (it
5398                  may not be aligned, for one thing).  */
5399               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5400               && (inner_mode == tmode
5401                   || (! mode_dependent_address_p (XEXP (inner, 0))
5402                       && ! MEM_VOLATILE_P (inner))))))
5403     {
5404       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5405          field.  If the original and current mode are the same, we need not
5406          adjust the offset.  Otherwise, we do if bytes big endian.
5407
5408          If INNER is not a MEM, get a piece consisting of just the field
5409          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5410
5411       if (GET_CODE (inner) == MEM)
5412         {
5413           int offset;
5414           /* POS counts from lsb, but make OFFSET count in memory order.  */
5415           if (BYTES_BIG_ENDIAN)
5416             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5417           else
5418             offset = pos / BITS_PER_UNIT;
5419
5420           new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5421           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5422           MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5423           MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5424         }
5425       else if (GET_CODE (inner) == REG)
5426         {
5427           /* We can't call gen_lowpart_for_combine here since we always want
5428              a SUBREG and it would sometimes return a new hard register.  */
5429           if (tmode != inner_mode)
5430             new = gen_rtx (SUBREG, tmode, inner,
5431                            (WORDS_BIG_ENDIAN
5432                             && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5433                             ? (((GET_MODE_SIZE (inner_mode)
5434                                  - GET_MODE_SIZE (tmode))
5435                                 / UNITS_PER_WORD)
5436                                - pos / BITS_PER_WORD)
5437                             : pos / BITS_PER_WORD));
5438           else
5439             new = inner;
5440         }
5441       else
5442         new = force_to_mode (inner, tmode,
5443                              len >= HOST_BITS_PER_WIDE_INT
5444                              ? GET_MODE_MASK (tmode)
5445                              : ((HOST_WIDE_INT) 1 << len) - 1,
5446                              NULL_RTX, 0);
5447
5448       /* If this extraction is going into the destination of a SET,
5449          make a STRICT_LOW_PART unless we made a MEM.  */
5450
5451       if (in_dest)
5452         return (GET_CODE (new) == MEM ? new
5453                 : (GET_CODE (new) != SUBREG
5454                    ? gen_rtx (CLOBBER, tmode, const0_rtx)
5455                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5456
5457       /* Otherwise, sign- or zero-extend unless we already are in the
5458          proper mode.  */
5459
5460       return (mode == tmode ? new
5461               : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5462                                  mode, new));
5463     }
5464
5465   /* Unless this is a COMPARE or we have a funny memory reference,
5466      don't do anything with zero-extending field extracts starting at
5467      the low-order bit since they are simple AND operations.  */
5468   if (pos_rtx == 0 && pos == 0 && ! in_dest
5469       && ! in_compare && ! spans_byte && unsignedp)
5470     return 0;
5471
5472   /* Unless we are allowed to span bytes, reject this if we would be
5473      spanning bytes or if the position is not a constant and the length
5474      is not 1.  In all other cases, we would only be going outside
5475      out object in cases when an original shift would have been
5476      undefined.  */
5477   if (! spans_byte
5478       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5479           || (pos_rtx != 0 && len != 1)))
5480     return 0;
5481
5482   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5483      and the mode for the result.  */
5484 #ifdef HAVE_insv
5485   if (in_dest)
5486     {
5487       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5488       pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5489       extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5490     }
5491 #endif
5492
5493 #ifdef HAVE_extzv
5494   if (! in_dest && unsignedp)
5495     {
5496       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5497       pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5498       extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5499     }
5500 #endif
5501
5502 #ifdef HAVE_extv
5503   if (! in_dest && ! unsignedp)
5504     {
5505       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5506       pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5507       extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5508     }
5509 #endif
5510
5511   /* Never narrow an object, since that might not be safe.  */
5512
5513   if (mode != VOIDmode
5514       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5515     extraction_mode = mode;
5516
5517   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5518       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5519     pos_mode = GET_MODE (pos_rtx);
5520
5521   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5522      if we have to change the mode of memory and cannot, the desired mode is
5523      EXTRACTION_MODE.  */
5524   if (GET_CODE (inner) != MEM)
5525     wanted_inner_mode = wanted_inner_reg_mode;
5526   else if (inner_mode != wanted_inner_mode
5527            && (mode_dependent_address_p (XEXP (inner, 0))
5528                || MEM_VOLATILE_P (inner)))
5529     wanted_inner_mode = extraction_mode;
5530
5531   orig_pos = pos;
5532
5533   if (BITS_BIG_ENDIAN)
5534     {
5535       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5536          BITS_BIG_ENDIAN style.  If position is constant, compute new
5537          position.  Otherwise, build subtraction.
5538          Note that POS is relative to the mode of the original argument.
5539          If it's a MEM we need to recompute POS relative to that.
5540          However, if we're extracting from (or inserting into) a register,
5541          we want to recompute POS relative to wanted_inner_mode.  */
5542       int width = (GET_CODE (inner) == MEM
5543                    ? GET_MODE_BITSIZE (is_mode)
5544                    : GET_MODE_BITSIZE (wanted_inner_mode));
5545
5546       if (pos_rtx == 0)
5547         pos = width - len - pos;
5548       else
5549         pos_rtx
5550           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5551                              GEN_INT (width - len), pos_rtx);
5552       /* POS may be less than 0 now, but we check for that below.
5553          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
5554     }
5555
5556   /* If INNER has a wider mode, make it smaller.  If this is a constant
5557      extract, try to adjust the byte to point to the byte containing
5558      the value.  */
5559   if (wanted_inner_mode != VOIDmode
5560       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5561       && ((GET_CODE (inner) == MEM
5562            && (inner_mode == wanted_inner_mode
5563                || (! mode_dependent_address_p (XEXP (inner, 0))
5564                    && ! MEM_VOLATILE_P (inner))))))
5565     {
5566       int offset = 0;
5567
5568       /* The computations below will be correct if the machine is big
5569          endian in both bits and bytes or little endian in bits and bytes.
5570          If it is mixed, we must adjust.  */
5571
5572       /* If bytes are big endian and we had a paradoxical SUBREG, we must
5573          adjust OFFSET to compensate.  */
5574       if (BYTES_BIG_ENDIAN
5575           && ! spans_byte
5576           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5577         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5578
5579       /* If this is a constant position, we can move to the desired byte.  */
5580       if (pos_rtx == 0)
5581         {
5582           offset += pos / BITS_PER_UNIT;
5583           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5584         }
5585
5586       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5587           && ! spans_byte
5588           && is_mode != wanted_inner_mode)
5589         offset = (GET_MODE_SIZE (is_mode)
5590                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
5591
5592       if (offset != 0 || inner_mode != wanted_inner_mode)
5593         {
5594           rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5595                                 plus_constant (XEXP (inner, 0), offset));
5596           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5597           MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5598           MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5599           inner = newmem;
5600         }
5601     }
5602
5603   /* If INNER is not memory, we can always get it into the proper mode.  If we
5604      are changing its mode, POS must be a constant and smaller than the size
5605      of the new mode.  */
5606   else if (GET_CODE (inner) != MEM)
5607     {
5608       if (GET_MODE (inner) != wanted_inner_mode
5609           && (pos_rtx != 0
5610               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5611         return 0;
5612
5613       inner = force_to_mode (inner, wanted_inner_mode,
5614                              pos_rtx
5615                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5616                              ? GET_MODE_MASK (wanted_inner_mode)
5617                              : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5618                              NULL_RTX, 0);
5619     }
5620
5621   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
5622      have to zero extend.  Otherwise, we can just use a SUBREG.  */
5623   if (pos_rtx != 0
5624       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5625     pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5626   else if (pos_rtx != 0
5627            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5628     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5629
5630   /* Make POS_RTX unless we already have it and it is correct.  If we don't
5631      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5632      be a CONST_INT.  */
5633   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5634     pos_rtx = orig_pos_rtx;
5635
5636   else if (pos_rtx == 0)
5637     pos_rtx = GEN_INT (pos);
5638
5639   /* Make the required operation.  See if we can use existing rtx.  */
5640   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5641                          extraction_mode, inner, GEN_INT (len), pos_rtx);
5642   if (! in_dest)
5643     new = gen_lowpart_for_combine (mode, new);
5644
5645   return new;
5646 }
5647 \f
5648 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5649    with any other operations in X.  Return X without that shift if so.  */
5650
5651 static rtx
5652 extract_left_shift (x, count)
5653      rtx x;
5654      int count;
5655 {
5656   enum rtx_code code = GET_CODE (x);
5657   enum machine_mode mode = GET_MODE (x);
5658   rtx tem;
5659
5660   switch (code)
5661     {
5662     case ASHIFT:
5663       /* This is the shift itself.  If it is wide enough, we will return
5664          either the value being shifted if the shift count is equal to
5665          COUNT or a shift for the difference.  */
5666       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5667           && INTVAL (XEXP (x, 1)) >= count)
5668         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5669                                      INTVAL (XEXP (x, 1)) - count);
5670       break;
5671
5672     case NEG:  case NOT:
5673       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5674         return gen_unary (code, mode, mode, tem);
5675
5676       break;
5677
5678     case PLUS:  case IOR:  case XOR:  case AND:
5679       /* If we can safely shift this constant and we find the inner shift,
5680          make a new operation.  */
5681       if (GET_CODE (XEXP (x,1)) == CONST_INT
5682           && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5683           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5684         return gen_binary (code, mode, tem,
5685                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5686
5687       break;
5688
5689     default:
5690       break;
5691     }
5692
5693   return 0;
5694 }
5695 \f
5696 /* Look at the expression rooted at X.  Look for expressions
5697    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5698    Form these expressions.
5699
5700    Return the new rtx, usually just X.
5701
5702    Also, for machines like the Vax that don't have logical shift insns,
5703    try to convert logical to arithmetic shift operations in cases where
5704    they are equivalent.  This undoes the canonicalizations to logical
5705    shifts done elsewhere.
5706
5707    We try, as much as possible, to re-use rtl expressions to save memory.
5708
5709    IN_CODE says what kind of expression we are processing.  Normally, it is
5710    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
5711    being kludges), it is MEM.  When processing the arguments of a comparison
5712    or a COMPARE against zero, it is COMPARE.  */
5713
5714 static rtx
5715 make_compound_operation (x, in_code)
5716      rtx x;
5717      enum rtx_code in_code;
5718 {
5719   enum rtx_code code = GET_CODE (x);
5720   enum machine_mode mode = GET_MODE (x);
5721   int mode_width = GET_MODE_BITSIZE (mode);
5722   rtx rhs, lhs;
5723   enum rtx_code next_code;
5724   int i;
5725   rtx new = 0;
5726   rtx tem;
5727   char *fmt;
5728
5729   /* Select the code to be used in recursive calls.  Once we are inside an
5730      address, we stay there.  If we have a comparison, set to COMPARE,
5731      but once inside, go back to our default of SET.  */
5732
5733   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5734                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5735                   && XEXP (x, 1) == const0_rtx) ? COMPARE
5736                : in_code == COMPARE ? SET : in_code);
5737
5738   /* Process depending on the code of this operation.  If NEW is set
5739      non-zero, it will be returned.  */
5740
5741   switch (code)
5742     {
5743     case ASHIFT:
5744       /* Convert shifts by constants into multiplications if inside
5745          an address.  */
5746       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5747           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5748           && INTVAL (XEXP (x, 1)) >= 0)
5749         {
5750           new = make_compound_operation (XEXP (x, 0), next_code);
5751           new = gen_rtx_combine (MULT, mode, new,
5752                                  GEN_INT ((HOST_WIDE_INT) 1
5753                                           << INTVAL (XEXP (x, 1))));
5754         }
5755       break;
5756
5757     case AND:
5758       /* If the second operand is not a constant, we can't do anything
5759          with it.  */
5760       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5761         break;
5762
5763       /* If the constant is a power of two minus one and the first operand
5764          is a logical right shift, make an extraction.  */
5765       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5766           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5767         {
5768           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5769           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5770                                  0, in_code == COMPARE);
5771         }
5772
5773       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
5774       else if (GET_CODE (XEXP (x, 0)) == SUBREG
5775                && subreg_lowpart_p (XEXP (x, 0))
5776                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5777                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5778         {
5779           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5780                                          next_code);
5781           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5782                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5783                                  0, in_code == COMPARE);
5784         }
5785       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
5786       else if ((GET_CODE (XEXP (x, 0)) == XOR
5787                 || GET_CODE (XEXP (x, 0)) == IOR)
5788                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5789                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5790                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5791         {
5792           /* Apply the distributive law, and then try to make extractions.  */
5793           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5794                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5795                                           XEXP (x, 1)),
5796                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5797                                           XEXP (x, 1)));
5798           new = make_compound_operation (new, in_code);
5799         }
5800
5801       /* If we are have (and (rotate X C) M) and C is larger than the number
5802          of bits in M, this is an extraction.  */
5803
5804       else if (GET_CODE (XEXP (x, 0)) == ROTATE
5805                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5806                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5807                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5808         {
5809           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5810           new = make_extraction (mode, new,
5811                                  (GET_MODE_BITSIZE (mode)
5812                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
5813                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
5814         }
5815
5816       /* On machines without logical shifts, if the operand of the AND is
5817          a logical shift and our mask turns off all the propagated sign
5818          bits, we can replace the logical shift with an arithmetic shift.  */
5819       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5820                && (lshr_optab->handlers[(int) mode].insn_code
5821                    == CODE_FOR_nothing)
5822                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5823                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5824                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5825                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5826                && mode_width <= HOST_BITS_PER_WIDE_INT)
5827         {
5828           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5829
5830           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5831           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5832             SUBST (XEXP (x, 0),
5833                    gen_rtx_combine (ASHIFTRT, mode,
5834                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
5835                                                              next_code),
5836                                     XEXP (XEXP (x, 0), 1)));
5837         }
5838
5839       /* If the constant is one less than a power of two, this might be
5840          representable by an extraction even if no shift is present.
5841          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5842          we are in a COMPARE.  */
5843       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5844         new = make_extraction (mode,
5845                                make_compound_operation (XEXP (x, 0),
5846                                                         next_code),
5847                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5848
5849       /* If we are in a comparison and this is an AND with a power of two,
5850          convert this into the appropriate bit extract.  */
5851       else if (in_code == COMPARE
5852                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5853         new = make_extraction (mode,
5854                                make_compound_operation (XEXP (x, 0),
5855                                                         next_code),
5856                                i, NULL_RTX, 1, 1, 0, 1);
5857
5858       break;
5859
5860     case LSHIFTRT:
5861       /* If the sign bit is known to be zero, replace this with an
5862          arithmetic shift.  */
5863       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5864           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5865           && mode_width <= HOST_BITS_PER_WIDE_INT
5866           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5867         {
5868           new = gen_rtx_combine (ASHIFTRT, mode,
5869                                  make_compound_operation (XEXP (x, 0),
5870                                                           next_code),
5871                                  XEXP (x, 1));
5872           break;
5873         }
5874
5875       /* ... fall through ...  */
5876
5877     case ASHIFTRT:
5878       lhs = XEXP (x, 0);
5879       rhs = XEXP (x, 1);
5880
5881       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5882          this is a SIGN_EXTRACT.  */
5883       if (GET_CODE (rhs) == CONST_INT
5884           && GET_CODE (lhs) == ASHIFT
5885           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5886           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5887         {
5888           new = make_compound_operation (XEXP (lhs, 0), next_code);
5889           new = make_extraction (mode, new,
5890                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5891                                  NULL_RTX, mode_width - INTVAL (rhs),
5892                                  code == LSHIFTRT, 0, in_code == COMPARE);
5893         }
5894
5895       /* See if we have operations between an ASHIFTRT and an ASHIFT.
5896          If so, try to merge the shifts into a SIGN_EXTEND.  We could
5897          also do this for some cases of SIGN_EXTRACT, but it doesn't
5898          seem worth the effort; the case checked for occurs on Alpha.  */
5899
5900       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5901           && ! (GET_CODE (lhs) == SUBREG
5902                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5903           && GET_CODE (rhs) == CONST_INT
5904           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5905           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5906         new = make_extraction (mode, make_compound_operation (new, next_code),
5907                                0, NULL_RTX, mode_width - INTVAL (rhs),
5908                                code == LSHIFTRT, 0, in_code == COMPARE);
5909
5910       break;
5911
5912     case SUBREG:
5913       /* Call ourselves recursively on the inner expression.  If we are
5914          narrowing the object and it has a different RTL code from
5915          what it originally did, do this SUBREG as a force_to_mode.  */
5916
5917       tem = make_compound_operation (SUBREG_REG (x), in_code);
5918       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5919           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5920           && subreg_lowpart_p (x))
5921         {
5922           rtx newer = force_to_mode (tem, mode,
5923                                      GET_MODE_MASK (mode), NULL_RTX, 0);
5924
5925           /* If we have something other than a SUBREG, we might have
5926              done an expansion, so rerun outselves.  */
5927           if (GET_CODE (newer) != SUBREG)
5928             newer = make_compound_operation (newer, in_code);
5929
5930           return newer;
5931         }
5932       break;
5933
5934     default:
5935       break;
5936     }
5937
5938   if (new)
5939     {
5940       x = gen_lowpart_for_combine (mode, new);
5941       code = GET_CODE (x);
5942     }
5943
5944   /* Now recursively process each operand of this operation.  */
5945   fmt = GET_RTX_FORMAT (code);
5946   for (i = 0; i < GET_RTX_LENGTH (code); i++)
5947     if (fmt[i] == 'e')
5948       {
5949         new = make_compound_operation (XEXP (x, i), next_code);
5950         SUBST (XEXP (x, i), new);
5951       }
5952
5953   return x;
5954 }
5955 \f
5956 /* Given M see if it is a value that would select a field of bits
5957     within an item, but not the entire word.  Return -1 if not.
5958     Otherwise, return the starting position of the field, where 0 is the
5959     low-order bit.
5960
5961    *PLEN is set to the length of the field.  */
5962
5963 static int
5964 get_pos_from_mask (m, plen)
5965      unsigned HOST_WIDE_INT m;
5966      int *plen;
5967 {
5968   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
5969   int pos = exact_log2 (m & - m);
5970
5971   if (pos < 0)
5972     return -1;
5973
5974   /* Now shift off the low-order zero bits and see if we have a power of
5975      two minus 1.  */
5976   *plen = exact_log2 ((m >> pos) + 1);
5977
5978   if (*plen <= 0)
5979     return -1;
5980
5981   return pos;
5982 }
5983 \f
5984 /* See if X can be simplified knowing that we will only refer to it in
5985    MODE and will only refer to those bits that are nonzero in MASK.
5986    If other bits are being computed or if masking operations are done
5987    that select a superset of the bits in MASK, they can sometimes be
5988    ignored.
5989
5990    Return a possibly simplified expression, but always convert X to
5991    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
5992
5993    Also, if REG is non-zero and X is a register equal in value to REG,
5994    replace X with REG.
5995
5996    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5997    are all off in X.  This is used when X will be complemented, by either
5998    NOT, NEG, or XOR.  */
5999
6000 static rtx
6001 force_to_mode (x, mode, mask, reg, just_select)
6002      rtx x;
6003      enum machine_mode mode;
6004      unsigned HOST_WIDE_INT mask;
6005      rtx reg;
6006      int just_select;
6007 {
6008   enum rtx_code code = GET_CODE (x);
6009   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6010   enum machine_mode op_mode;
6011   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6012   rtx op0, op1, temp;
6013
6014   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6015      code below will do the wrong thing since the mode of such an
6016      expression is VOIDmode.  */
6017   if (code == CALL || code == ASM_OPERANDS)
6018     return x;
6019
6020   /* We want to perform the operation is its present mode unless we know
6021      that the operation is valid in MODE, in which case we do the operation
6022      in MODE.  */
6023   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6024               && code_to_optab[(int) code] != 0
6025               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6026                   != CODE_FOR_nothing))
6027              ? mode : GET_MODE (x));
6028
6029   /* It is not valid to do a right-shift in a narrower mode
6030      than the one it came in with.  */
6031   if ((code == LSHIFTRT || code == ASHIFTRT)
6032       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6033     op_mode = GET_MODE (x);
6034
6035   /* Truncate MASK to fit OP_MODE.  */
6036   if (op_mode)
6037     mask &= GET_MODE_MASK (op_mode);
6038
6039   /* When we have an arithmetic operation, or a shift whose count we
6040      do not know, we need to assume that all bit the up to the highest-order
6041      bit in MASK will be needed.  This is how we form such a mask.  */
6042   if (op_mode)
6043     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6044                    ? GET_MODE_MASK (op_mode)
6045                    : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6046   else
6047     fuller_mask = ~ (HOST_WIDE_INT) 0;
6048
6049   /* Determine what bits of X are guaranteed to be (non)zero.  */
6050   nonzero = nonzero_bits (x, mode);
6051
6052   /* If none of the bits in X are needed, return a zero.  */
6053   if (! just_select && (nonzero & mask) == 0)
6054     return const0_rtx;
6055
6056   /* If X is a CONST_INT, return a new one.  Do this here since the
6057      test below will fail.  */
6058   if (GET_CODE (x) == CONST_INT)
6059     {
6060       HOST_WIDE_INT cval = INTVAL (x) & mask;
6061       int width = GET_MODE_BITSIZE (mode);
6062
6063       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6064          number, sign extend it.  */
6065       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6066           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6067         cval |= (HOST_WIDE_INT) -1 << width;
6068
6069       return GEN_INT (cval);
6070     }
6071
6072   /* If X is narrower than MODE and we want all the bits in X's mode, just
6073      get X in the proper mode.  */
6074   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6075       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6076     return gen_lowpart_for_combine (mode, x);
6077
6078   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6079      MASK are already known to be zero in X, we need not do anything.  */
6080   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6081     return x;
6082
6083   switch (code)
6084     {
6085     case CLOBBER:
6086       /* If X is a (clobber (const_int)), return it since we know we are
6087          generating something that won't match.  */
6088       return x;
6089
6090     case USE:
6091       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6092          spanned the boundary of the MEM.  If we are now masking so it is
6093          within that boundary, we don't need the USE any more.  */
6094       if (! BITS_BIG_ENDIAN
6095           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6096         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6097       break;
6098
6099     case SIGN_EXTEND:
6100     case ZERO_EXTEND:
6101     case ZERO_EXTRACT:
6102     case SIGN_EXTRACT:
6103       x = expand_compound_operation (x);
6104       if (GET_CODE (x) != code)
6105         return force_to_mode (x, mode, mask, reg, next_select);
6106       break;
6107
6108     case REG:
6109       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6110                        || rtx_equal_p (reg, get_last_value (x))))
6111         x = reg;
6112       break;
6113
6114     case SUBREG:
6115       if (subreg_lowpart_p (x)
6116           /* We can ignore the effect of this SUBREG if it narrows the mode or
6117              if the constant masks to zero all the bits the mode doesn't
6118              have.  */
6119           && ((GET_MODE_SIZE (GET_MODE (x))
6120                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6121               || (0 == (mask
6122                         & GET_MODE_MASK (GET_MODE (x))
6123                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6124         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6125       break;
6126
6127     case AND:
6128       /* If this is an AND with a constant, convert it into an AND
6129          whose constant is the AND of that constant with MASK.  If it
6130          remains an AND of MASK, delete it since it is redundant.  */
6131
6132       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6133         {
6134           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6135                                       mask & INTVAL (XEXP (x, 1)));
6136
6137           /* If X is still an AND, see if it is an AND with a mask that
6138              is just some low-order bits.  If so, and it is MASK, we don't
6139              need it.  */
6140
6141           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6142               && INTVAL (XEXP (x, 1)) == mask)
6143             x = XEXP (x, 0);
6144
6145           /* If it remains an AND, try making another AND with the bits
6146              in the mode mask that aren't in MASK turned on.  If the
6147              constant in the AND is wide enough, this might make a
6148              cheaper constant.  */
6149
6150           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6151               && GET_MODE_MASK (GET_MODE (x)) != mask
6152               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6153             {
6154               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6155                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6156               int width = GET_MODE_BITSIZE (GET_MODE (x));
6157               rtx y;
6158
6159               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6160                  number, sign extend it.  */
6161               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6162                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6163                 cval |= (HOST_WIDE_INT) -1 << width;
6164
6165               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6166               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6167                 x = y;
6168             }
6169
6170           break;
6171         }
6172
6173       goto binop;
6174
6175     case PLUS:
6176       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6177          low-order bits (as in an alignment operation) and FOO is already
6178          aligned to that boundary, mask C1 to that boundary as well.
6179          This may eliminate that PLUS and, later, the AND.  */
6180
6181       {
6182         int width = GET_MODE_BITSIZE (mode);
6183         unsigned HOST_WIDE_INT smask = mask;
6184
6185         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6186            number, sign extend it.  */
6187
6188         if (width < HOST_BITS_PER_WIDE_INT
6189             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6190           smask |= (HOST_WIDE_INT) -1 << width;
6191
6192         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6193             && exact_log2 (- smask) >= 0
6194             && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6195             && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6196           return force_to_mode (plus_constant (XEXP (x, 0),
6197                                                INTVAL (XEXP (x, 1)) & mask),
6198                                 mode, mask, reg, next_select);
6199       }
6200
6201       /* ... fall through ...  */
6202
6203     case MINUS:
6204     case MULT:
6205       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6206          most significant bit in MASK since carries from those bits will
6207          affect the bits we are interested in.  */
6208       mask = fuller_mask;
6209       goto binop;
6210
6211     case IOR:
6212     case XOR:
6213       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6214          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6215          operation which may be a bitfield extraction.  Ensure that the
6216          constant we form is not wider than the mode of X.  */
6217
6218       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6219           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6220           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6221           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6222           && GET_CODE (XEXP (x, 1)) == CONST_INT
6223           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6224                + floor_log2 (INTVAL (XEXP (x, 1))))
6225               < GET_MODE_BITSIZE (GET_MODE (x)))
6226           && (INTVAL (XEXP (x, 1))
6227               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6228         {
6229           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6230                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6231           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6232                              XEXP (XEXP (x, 0), 0), temp);
6233           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6234                           XEXP (XEXP (x, 0), 1));
6235           return force_to_mode (x, mode, mask, reg, next_select);
6236         }
6237
6238     binop:
6239       /* For most binary operations, just propagate into the operation and
6240          change the mode if we have an operation of that mode.   */
6241
6242       op0 = gen_lowpart_for_combine (op_mode,
6243                                      force_to_mode (XEXP (x, 0), mode, mask,
6244                                                     reg, next_select));
6245       op1 = gen_lowpart_for_combine (op_mode,
6246                                      force_to_mode (XEXP (x, 1), mode, mask,
6247                                                     reg, next_select));
6248
6249       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6250          MASK since OP1 might have been sign-extended but we never want
6251          to turn on extra bits, since combine might have previously relied
6252          on them being off.  */
6253       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6254           && (INTVAL (op1) & mask) != 0)
6255         op1 = GEN_INT (INTVAL (op1) & mask);
6256
6257       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6258         x = gen_binary (code, op_mode, op0, op1);
6259       break;
6260
6261     case ASHIFT:
6262       /* For left shifts, do the same, but just for the first operand.
6263          However, we cannot do anything with shifts where we cannot
6264          guarantee that the counts are smaller than the size of the mode
6265          because such a count will have a different meaning in a
6266          wider mode.  */
6267
6268       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6269              && INTVAL (XEXP (x, 1)) >= 0
6270              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6271           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6272                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6273                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6274         break;
6275
6276       /* If the shift count is a constant and we can do arithmetic in
6277          the mode of the shift, refine which bits we need.  Otherwise, use the
6278          conservative form of the mask.  */
6279       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6280           && INTVAL (XEXP (x, 1)) >= 0
6281           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6282           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6283         mask >>= INTVAL (XEXP (x, 1));
6284       else
6285         mask = fuller_mask;
6286
6287       op0 = gen_lowpart_for_combine (op_mode,
6288                                      force_to_mode (XEXP (x, 0), op_mode,
6289                                                     mask, reg, next_select));
6290
6291       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6292         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6293       break;
6294
6295     case LSHIFTRT:
6296       /* Here we can only do something if the shift count is a constant,
6297          this shift constant is valid for the host, and we can do arithmetic
6298          in OP_MODE.  */
6299
6300       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6301           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6302           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6303         {
6304           rtx inner = XEXP (x, 0);
6305
6306           /* Select the mask of the bits we need for the shift operand.  */
6307           mask <<= INTVAL (XEXP (x, 1));
6308
6309           /* We can only change the mode of the shift if we can do arithmetic
6310              in the mode of the shift and MASK is no wider than the width of
6311              OP_MODE.  */
6312           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6313               || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6314             op_mode = GET_MODE (x);
6315
6316           inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6317
6318           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6319             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6320         }
6321
6322       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6323          shift and AND produces only copies of the sign bit (C2 is one less
6324          than a power of two), we can do this with just a shift.  */
6325
6326       if (GET_CODE (x) == LSHIFTRT
6327           && GET_CODE (XEXP (x, 1)) == CONST_INT
6328           && ((INTVAL (XEXP (x, 1))
6329                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6330               >= GET_MODE_BITSIZE (GET_MODE (x)))
6331           && exact_log2 (mask + 1) >= 0
6332           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6333               >= exact_log2 (mask + 1)))
6334         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6335                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6336                                  - exact_log2 (mask + 1)));
6337       break;
6338
6339     case ASHIFTRT:
6340       /* If we are just looking for the sign bit, we don't need this shift at
6341          all, even if it has a variable count.  */
6342       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6343           && (mask == ((HOST_WIDE_INT) 1
6344                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6345         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6346
6347       /* If this is a shift by a constant, get a mask that contains those bits
6348          that are not copies of the sign bit.  We then have two cases:  If
6349          MASK only includes those bits, this can be a logical shift, which may
6350          allow simplifications.  If MASK is a single-bit field not within
6351          those bits, we are requesting a copy of the sign bit and hence can
6352          shift the sign bit to the appropriate location.  */
6353
6354       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6355           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6356         {
6357           int i = -1;
6358
6359           /* If the considered data is wider then HOST_WIDE_INT, we can't
6360              represent a mask for all its bits in a single scalar.
6361              But we only care about the lower bits, so calculate these.  */
6362
6363           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6364             {
6365               nonzero = ~ (HOST_WIDE_INT) 0;
6366
6367               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6368                  is the number of bits a full-width mask would have set.
6369                  We need only shift if these are fewer than nonzero can
6370                  hold.  If not, we must keep all bits set in nonzero.  */
6371
6372               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6373                   < HOST_BITS_PER_WIDE_INT)
6374                 nonzero >>= INTVAL (XEXP (x, 1))
6375                             + HOST_BITS_PER_WIDE_INT
6376                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6377             }
6378           else
6379             {
6380               nonzero = GET_MODE_MASK (GET_MODE (x));
6381               nonzero >>= INTVAL (XEXP (x, 1));
6382             }
6383
6384           if ((mask & ~ nonzero) == 0
6385               || (i = exact_log2 (mask)) >= 0)
6386             {
6387               x = simplify_shift_const
6388                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6389                  i < 0 ? INTVAL (XEXP (x, 1))
6390                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6391
6392               if (GET_CODE (x) != ASHIFTRT)
6393                 return force_to_mode (x, mode, mask, reg, next_select);
6394             }
6395         }
6396
6397       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6398          even if the shift count isn't a constant.  */
6399       if (mask == 1)
6400         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6401
6402       /* If this is a sign-extension operation that just affects bits
6403          we don't care about, remove it.  Be sure the call above returned
6404          something that is still a shift.  */
6405
6406       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6407           && GET_CODE (XEXP (x, 1)) == CONST_INT
6408           && INTVAL (XEXP (x, 1)) >= 0
6409           && (INTVAL (XEXP (x, 1))
6410               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6411           && GET_CODE (XEXP (x, 0)) == ASHIFT
6412           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6413           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6414         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6415                               reg, next_select);
6416
6417       break;
6418
6419     case ROTATE:
6420     case ROTATERT:
6421       /* If the shift count is constant and we can do computations
6422          in the mode of X, compute where the bits we care about are.
6423          Otherwise, we can't do anything.  Don't change the mode of
6424          the shift or propagate MODE into the shift, though.  */
6425       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6426           && INTVAL (XEXP (x, 1)) >= 0)
6427         {
6428           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6429                                             GET_MODE (x), GEN_INT (mask),
6430                                             XEXP (x, 1));
6431           if (temp && GET_CODE(temp) == CONST_INT)
6432             SUBST (XEXP (x, 0),
6433                    force_to_mode (XEXP (x, 0), GET_MODE (x),
6434                                   INTVAL (temp), reg, next_select));
6435         }
6436       break;
6437
6438     case NEG:
6439       /* If we just want the low-order bit, the NEG isn't needed since it
6440          won't change the low-order bit.    */
6441       if (mask == 1)
6442         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6443
6444       /* We need any bits less significant than the most significant bit in
6445          MASK since carries from those bits will affect the bits we are
6446          interested in.  */
6447       mask = fuller_mask;
6448       goto unop;
6449
6450     case NOT:
6451       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6452          same as the XOR case above.  Ensure that the constant we form is not
6453          wider than the mode of X.  */
6454
6455       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6456           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6457           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6458           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6459               < GET_MODE_BITSIZE (GET_MODE (x)))
6460           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6461         {
6462           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6463           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6464           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6465
6466           return force_to_mode (x, mode, mask, reg, next_select);
6467         }
6468
6469       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6470          use the full mask inside the NOT.  */
6471       mask = fuller_mask;
6472
6473     unop:
6474       op0 = gen_lowpart_for_combine (op_mode,
6475                                      force_to_mode (XEXP (x, 0), mode, mask,
6476                                                     reg, next_select));
6477       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6478         x = gen_unary (code, op_mode, op_mode, op0);
6479       break;
6480
6481     case NE:
6482       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6483          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6484          which is equal to STORE_FLAG_VALUE.  */
6485       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6486           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6487           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6488         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6489
6490       break;
6491
6492     case IF_THEN_ELSE:
6493       /* We have no way of knowing if the IF_THEN_ELSE can itself be
6494          written in a narrower mode.  We play it safe and do not do so.  */
6495
6496       SUBST (XEXP (x, 1),
6497              gen_lowpart_for_combine (GET_MODE (x),
6498                                       force_to_mode (XEXP (x, 1), mode,
6499                                                      mask, reg, next_select)));
6500       SUBST (XEXP (x, 2),
6501              gen_lowpart_for_combine (GET_MODE (x),
6502                                       force_to_mode (XEXP (x, 2), mode,
6503                                                      mask, reg,next_select)));
6504       break;
6505
6506     default:
6507       break;
6508     }
6509
6510   /* Ensure we return a value of the proper mode.  */
6511   return gen_lowpart_for_combine (mode, x);
6512 }
6513 \f
6514 /* Return nonzero if X is an expression that has one of two values depending on
6515    whether some other value is zero or nonzero.  In that case, we return the
6516    value that is being tested, *PTRUE is set to the value if the rtx being
6517    returned has a nonzero value, and *PFALSE is set to the other alternative.
6518
6519    If we return zero, we set *PTRUE and *PFALSE to X.  */
6520
6521 static rtx
6522 if_then_else_cond (x, ptrue, pfalse)
6523      rtx x;
6524      rtx *ptrue, *pfalse;
6525 {
6526   enum machine_mode mode = GET_MODE (x);
6527   enum rtx_code code = GET_CODE (x);
6528   int size = GET_MODE_BITSIZE (mode);
6529   rtx cond0, cond1, true0, true1, false0, false1;
6530   unsigned HOST_WIDE_INT nz;
6531
6532   /* If this is a unary operation whose operand has one of two values, apply
6533      our opcode to compute those values.  */
6534   if (GET_RTX_CLASS (code) == '1'
6535       && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6536     {
6537       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6538       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6539       return cond0;
6540     }
6541
6542   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6543      make can't possibly match and would suppress other optimizations.  */
6544   else if (code == COMPARE)
6545     ;
6546
6547   /* If this is a binary operation, see if either side has only one of two
6548      values.  If either one does or if both do and they are conditional on
6549      the same value, compute the new true and false values.  */
6550   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6551            || GET_RTX_CLASS (code) == '<')
6552     {
6553       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6554       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6555
6556       if ((cond0 != 0 || cond1 != 0)
6557           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6558         {
6559           /* If if_then_else_cond returned zero, then true/false are the
6560              same rtl.  We must copy one of them to prevent invalid rtl
6561              sharing.  */
6562           if (cond0 == 0)
6563             true0 = copy_rtx (true0);
6564           else if (cond1 == 0)
6565             true1 = copy_rtx (true1);
6566
6567           *ptrue = gen_binary (code, mode, true0, true1);
6568           *pfalse = gen_binary (code, mode, false0, false1);
6569           return cond0 ? cond0 : cond1;
6570         }
6571
6572       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6573          operands is zero when the other is non-zero, and vice-versa,
6574          and STORE_FLAG_VALUE is 1 or -1.  */
6575
6576       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6577           && (code == PLUS || code == IOR || code == XOR || code == MINUS
6578            || code == UMAX)
6579           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6580         {
6581           rtx op0 = XEXP (XEXP (x, 0), 1);
6582           rtx op1 = XEXP (XEXP (x, 1), 1);
6583
6584           cond0 = XEXP (XEXP (x, 0), 0);
6585           cond1 = XEXP (XEXP (x, 1), 0);
6586
6587           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6588               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6589               && reversible_comparison_p (cond1)
6590               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6591                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6592                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6593                   || ((swap_condition (GET_CODE (cond0))
6594                        == reverse_condition (GET_CODE (cond1)))
6595                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6596                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6597               && ! side_effects_p (x))
6598             {
6599               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6600               *pfalse = gen_binary (MULT, mode,
6601                                     (code == MINUS
6602                                      ? gen_unary (NEG, mode, mode, op1) : op1),
6603                                     const_true_rtx);
6604               return cond0;
6605             }
6606         }
6607
6608       /* Similarly for MULT, AND and UMIN, execpt that for these the result
6609          is always zero.  */
6610       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6611           && (code == MULT || code == AND || code == UMIN)
6612           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6613         {
6614           cond0 = XEXP (XEXP (x, 0), 0);
6615           cond1 = XEXP (XEXP (x, 1), 0);
6616
6617           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6618               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6619               && reversible_comparison_p (cond1)
6620               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6621                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6622                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6623                   || ((swap_condition (GET_CODE (cond0))
6624                        == reverse_condition (GET_CODE (cond1)))
6625                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6626                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6627               && ! side_effects_p (x))
6628             {
6629               *ptrue = *pfalse = const0_rtx;
6630               return cond0;
6631             }
6632         }
6633     }
6634
6635   else if (code == IF_THEN_ELSE)
6636     {
6637       /* If we have IF_THEN_ELSE already, extract the condition and
6638          canonicalize it if it is NE or EQ.  */
6639       cond0 = XEXP (x, 0);
6640       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6641       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6642         return XEXP (cond0, 0);
6643       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6644         {
6645           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6646           return XEXP (cond0, 0);
6647         }
6648       else
6649         return cond0;
6650     }
6651
6652   /* If X is a normal SUBREG with both inner and outer modes integral,
6653      we can narrow both the true and false values of the inner expression,
6654      if there is a condition.  */
6655   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6656            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6657            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6658            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6659                                                &true0, &false0)))
6660     {
6661       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6662       *pfalse
6663         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6664
6665       return cond0;
6666     }
6667
6668   /* If X is a constant, this isn't special and will cause confusions
6669      if we treat it as such.  Likewise if it is equivalent to a constant.  */
6670   else if (CONSTANT_P (x)
6671            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6672     ;
6673
6674   /* If X is known to be either 0 or -1, those are the true and
6675      false values when testing X.  */
6676   else if (num_sign_bit_copies (x, mode) == size)
6677     {
6678       *ptrue = constm1_rtx, *pfalse = const0_rtx;
6679       return x;
6680     }
6681
6682   /* Likewise for 0 or a single bit.  */
6683   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6684     {
6685       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6686       return x;
6687     }
6688
6689   /* Otherwise fail; show no condition with true and false values the same.  */
6690   *ptrue = *pfalse = x;
6691   return 0;
6692 }
6693 \f
6694 /* Return the value of expression X given the fact that condition COND
6695    is known to be true when applied to REG as its first operand and VAL
6696    as its second.  X is known to not be shared and so can be modified in
6697    place.
6698
6699    We only handle the simplest cases, and specifically those cases that
6700    arise with IF_THEN_ELSE expressions.  */
6701
6702 static rtx
6703 known_cond (x, cond, reg, val)
6704      rtx x;
6705      enum rtx_code cond;
6706      rtx reg, val;
6707 {
6708   enum rtx_code code = GET_CODE (x);
6709   rtx temp;
6710   char *fmt;
6711   int i, j;
6712
6713   if (side_effects_p (x))
6714     return x;
6715
6716   if (cond == EQ && rtx_equal_p (x, reg))
6717     return val;
6718
6719   /* If X is (abs REG) and we know something about REG's relationship
6720      with zero, we may be able to simplify this.  */
6721
6722   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6723     switch (cond)
6724       {
6725       case GE:  case GT:  case EQ:
6726         return XEXP (x, 0);
6727       case LT:  case LE:
6728         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6729                           XEXP (x, 0));
6730       default:
6731         break;
6732       }
6733
6734   /* The only other cases we handle are MIN, MAX, and comparisons if the
6735      operands are the same as REG and VAL.  */
6736
6737   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6738     {
6739       if (rtx_equal_p (XEXP (x, 0), val))
6740         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6741
6742       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6743         {
6744           if (GET_RTX_CLASS (code) == '<')
6745             return (comparison_dominates_p (cond, code) ? const_true_rtx
6746                     : (comparison_dominates_p (cond,
6747                                                reverse_condition (code))
6748                        ? const0_rtx : x));
6749
6750           else if (code == SMAX || code == SMIN
6751                    || code == UMIN || code == UMAX)
6752             {
6753               int unsignedp = (code == UMIN || code == UMAX);
6754
6755               if (code == SMAX || code == UMAX)
6756                 cond = reverse_condition (cond);
6757
6758               switch (cond)
6759                 {
6760                 case GE:   case GT:
6761                   return unsignedp ? x : XEXP (x, 1);
6762                 case LE:   case LT:
6763                   return unsignedp ? x : XEXP (x, 0);
6764                 case GEU:  case GTU:
6765                   return unsignedp ? XEXP (x, 1) : x;
6766                 case LEU:  case LTU:
6767                   return unsignedp ? XEXP (x, 0) : x;
6768                 default:
6769                   break;
6770                 }
6771             }
6772         }
6773     }
6774
6775   fmt = GET_RTX_FORMAT (code);
6776   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6777     {
6778       if (fmt[i] == 'e')
6779         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6780       else if (fmt[i] == 'E')
6781         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6782           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6783                                                 cond, reg, val));
6784     }
6785
6786   return x;
6787 }
6788 \f
6789 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6790    assignment as a field assignment.  */
6791
6792 static int
6793 rtx_equal_for_field_assignment_p (x, y)
6794      rtx x;
6795      rtx y;
6796 {
6797   rtx last_x, last_y;
6798
6799   if (x == y || rtx_equal_p (x, y))
6800     return 1;
6801
6802   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6803     return 0;
6804
6805   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6806      Note that all SUBREGs of MEM are paradoxical; otherwise they
6807      would have been rewritten.  */
6808   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6809       && GET_CODE (SUBREG_REG (y)) == MEM
6810       && rtx_equal_p (SUBREG_REG (y),
6811                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6812     return 1;
6813
6814   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6815       && GET_CODE (SUBREG_REG (x)) == MEM
6816       && rtx_equal_p (SUBREG_REG (x),
6817                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6818     return 1;
6819
6820   last_x = get_last_value (x);
6821   last_y = get_last_value (y);
6822
6823   return ((last_x != 0
6824            && GET_CODE (last_x) != CLOBBER
6825            && rtx_equal_for_field_assignment_p (last_x, y))
6826           || (last_y != 0
6827               && GET_CODE (last_y) != CLOBBER
6828               && rtx_equal_for_field_assignment_p (x, last_y))
6829           || (last_x != 0 && last_y != 0
6830               && GET_CODE (last_x) != CLOBBER
6831               && GET_CODE (last_y) != CLOBBER
6832               && rtx_equal_for_field_assignment_p (last_x, last_y)));
6833 }
6834 \f
6835 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6836    Return that assignment if so.
6837
6838    We only handle the most common cases.  */
6839
6840 static rtx
6841 make_field_assignment (x)
6842      rtx x;
6843 {
6844   rtx dest = SET_DEST (x);
6845   rtx src = SET_SRC (x);
6846   rtx assign;
6847   rtx rhs, lhs;
6848   HOST_WIDE_INT c1;
6849   int pos, len;
6850   rtx other;
6851   enum machine_mode mode;
6852
6853   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6854      a clear of a one-bit field.  We will have changed it to
6855      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
6856      for a SUBREG.  */
6857
6858   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6859       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6860       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6861       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6862     {
6863       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6864                                 1, 1, 1, 0);
6865       if (assign != 0)
6866         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6867       return x;
6868     }
6869
6870   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6871            && subreg_lowpart_p (XEXP (src, 0))
6872            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6873                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6874            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6875            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6876            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6877     {
6878       assign = make_extraction (VOIDmode, dest, 0,
6879                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6880                                 1, 1, 1, 0);
6881       if (assign != 0)
6882         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6883       return x;
6884     }
6885
6886   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6887      one-bit field.  */
6888   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6889            && XEXP (XEXP (src, 0), 0) == const1_rtx
6890            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6891     {
6892       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6893                                 1, 1, 1, 0);
6894       if (assign != 0)
6895         return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6896       return x;
6897     }
6898
6899   /* The other case we handle is assignments into a constant-position
6900      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
6901      a mask that has all one bits except for a group of zero bits and
6902      OTHER is known to have zeros where C1 has ones, this is such an
6903      assignment.  Compute the position and length from C1.  Shift OTHER
6904      to the appropriate position, force it to the required mode, and
6905      make the extraction.  Check for the AND in both operands.  */
6906
6907   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6908     return x;
6909
6910   rhs = expand_compound_operation (XEXP (src, 0));
6911   lhs = expand_compound_operation (XEXP (src, 1));
6912
6913   if (GET_CODE (rhs) == AND
6914       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6915       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6916     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6917   else if (GET_CODE (lhs) == AND
6918            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6919            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6920     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6921   else
6922     return x;
6923
6924   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6925   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6926       || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6927           && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6928     return x;
6929
6930   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6931   if (assign == 0)
6932     return x;
6933
6934   /* The mode to use for the source is the mode of the assignment, or of
6935      what is inside a possible STRICT_LOW_PART.  */
6936   mode = (GET_CODE (assign) == STRICT_LOW_PART
6937           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6938
6939   /* Shift OTHER right POS places and make it the source, restricting it
6940      to the proper length and mode.  */
6941
6942   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6943                                              GET_MODE (src), other, pos),
6944                        mode,
6945                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6946                        ? GET_MODE_MASK (mode)
6947                        : ((HOST_WIDE_INT) 1 << len) - 1,
6948                        dest, 0);
6949
6950   return gen_rtx_combine (SET, VOIDmode, assign, src);
6951 }
6952 \f
6953 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6954    if so.  */
6955
6956 static rtx
6957 apply_distributive_law (x)
6958      rtx x;
6959 {
6960   enum rtx_code code = GET_CODE (x);
6961   rtx lhs, rhs, other;
6962   rtx tem;
6963   enum rtx_code inner_code;
6964
6965   /* Distributivity is not true for floating point.
6966      It can change the value.  So don't do it.
6967      -- rms and moshier@world.std.com.  */
6968   if (FLOAT_MODE_P (GET_MODE (x)))
6969     return x;
6970
6971   /* The outer operation can only be one of the following:  */
6972   if (code != IOR && code != AND && code != XOR
6973       && code != PLUS && code != MINUS)
6974     return x;
6975
6976   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6977
6978   /* If either operand is a primitive we can't do anything, so get out
6979      fast.  */
6980   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6981       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6982     return x;
6983
6984   lhs = expand_compound_operation (lhs);
6985   rhs = expand_compound_operation (rhs);
6986   inner_code = GET_CODE (lhs);
6987   if (inner_code != GET_CODE (rhs))
6988     return x;
6989
6990   /* See if the inner and outer operations distribute.  */
6991   switch (inner_code)
6992     {
6993     case LSHIFTRT:
6994     case ASHIFTRT:
6995     case AND:
6996     case IOR:
6997       /* These all distribute except over PLUS.  */
6998       if (code == PLUS || code == MINUS)
6999         return x;
7000       break;
7001
7002     case MULT:
7003       if (code != PLUS && code != MINUS)
7004         return x;
7005       break;
7006
7007     case ASHIFT:
7008       /* This is also a multiply, so it distributes over everything.  */
7009       break;
7010
7011     case SUBREG:
7012       /* Non-paradoxical SUBREGs distributes over all operations, provided
7013          the inner modes and word numbers are the same, this is an extraction
7014          of a low-order part, we don't convert an fp operation to int or
7015          vice versa, and we would not be converting a single-word
7016          operation into a multi-word operation.  The latter test is not
7017          required, but it prevents generating unneeded multi-word operations.
7018          Some of the previous tests are redundant given the latter test, but
7019          are retained because they are required for correctness.
7020
7021          We produce the result slightly differently in this case.  */
7022
7023       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7024           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7025           || ! subreg_lowpart_p (lhs)
7026           || (GET_MODE_CLASS (GET_MODE (lhs))
7027               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7028           || (GET_MODE_SIZE (GET_MODE (lhs))
7029               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7030           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7031         return x;
7032
7033       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7034                         SUBREG_REG (lhs), SUBREG_REG (rhs));
7035       return gen_lowpart_for_combine (GET_MODE (x), tem);
7036
7037     default:
7038       return x;
7039     }
7040
7041   /* Set LHS and RHS to the inner operands (A and B in the example
7042      above) and set OTHER to the common operand (C in the example).
7043      These is only one way to do this unless the inner operation is
7044      commutative.  */
7045   if (GET_RTX_CLASS (inner_code) == 'c'
7046       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7047     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7048   else if (GET_RTX_CLASS (inner_code) == 'c'
7049            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7050     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7051   else if (GET_RTX_CLASS (inner_code) == 'c'
7052            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7053     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7054   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7055     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7056   else
7057     return x;
7058
7059   /* Form the new inner operation, seeing if it simplifies first.  */
7060   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7061
7062   /* There is one exception to the general way of distributing:
7063      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7064   if (code == XOR && inner_code == IOR)
7065     {
7066       inner_code = AND;
7067       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7068     }
7069
7070   /* We may be able to continuing distributing the result, so call
7071      ourselves recursively on the inner operation before forming the
7072      outer operation, which we return.  */
7073   return gen_binary (inner_code, GET_MODE (x),
7074                      apply_distributive_law (tem), other);
7075 }
7076 \f
7077 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7078    in MODE.
7079
7080    Return an equivalent form, if different from X.  Otherwise, return X.  If
7081    X is zero, we are to always construct the equivalent form.  */
7082
7083 static rtx
7084 simplify_and_const_int (x, mode, varop, constop)
7085      rtx x;
7086      enum machine_mode mode;
7087      rtx varop;
7088      unsigned HOST_WIDE_INT constop;
7089 {
7090   unsigned HOST_WIDE_INT nonzero;
7091   int width = GET_MODE_BITSIZE (mode);
7092   int i;
7093
7094   /* Simplify VAROP knowing that we will be only looking at some of the
7095      bits in it.  */
7096   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7097
7098   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7099      CONST_INT, we are done.  */
7100   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7101     return varop;
7102
7103   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7104      a call to nonzero_bits, here we don't care about bits outside
7105      MODE.  */
7106
7107   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7108
7109   /* If this would be an entire word for the target, but is not for
7110      the host, then sign-extend on the host so that the number will look
7111      the same way on the host that it would on the target.
7112
7113      For example, when building a 64 bit alpha hosted 32 bit sparc
7114      targeted compiler, then we want the 32 bit unsigned value -1 to be
7115      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7116      The later confuses the sparc backend.  */
7117
7118   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7119       && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7120     nonzero |= ((HOST_WIDE_INT) (-1) << width);
7121
7122   /* Turn off all bits in the constant that are known to already be zero.
7123      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7124      which is tested below.  */
7125
7126   constop &= nonzero;
7127
7128   /* If we don't have any bits left, return zero.  */
7129   if (constop == 0)
7130     return const0_rtx;
7131
7132   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7133      a power of two, we can replace this with a ASHIFT.  */
7134   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7135       && (i = exact_log2 (constop)) >= 0)
7136     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7137
7138   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7139      or XOR, then try to apply the distributive law.  This may eliminate
7140      operations if either branch can be simplified because of the AND.
7141      It may also make some cases more complex, but those cases probably
7142      won't match a pattern either with or without this.  */
7143
7144   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7145     return
7146       gen_lowpart_for_combine
7147         (mode,
7148          apply_distributive_law
7149          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7150                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7151                                               XEXP (varop, 0), constop),
7152                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7153                                               XEXP (varop, 1), constop))));
7154
7155   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7156      if we already had one (just check for the simplest cases).  */
7157   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7158       && GET_MODE (XEXP (x, 0)) == mode
7159       && SUBREG_REG (XEXP (x, 0)) == varop)
7160     varop = XEXP (x, 0);
7161   else
7162     varop = gen_lowpart_for_combine (mode, varop);
7163
7164   /* If we can't make the SUBREG, try to return what we were given.  */
7165   if (GET_CODE (varop) == CLOBBER)
7166     return x ? x : varop;
7167
7168   /* If we are only masking insignificant bits, return VAROP.  */
7169   if (constop == nonzero)
7170     x = varop;
7171
7172   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7173   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7174     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7175
7176   else
7177     {
7178       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7179           || INTVAL (XEXP (x, 1)) != constop)
7180         SUBST (XEXP (x, 1), GEN_INT (constop));
7181
7182       SUBST (XEXP (x, 0), varop);
7183     }
7184
7185   return x;
7186 }
7187 \f
7188 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7189    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7190    is less useful.  We can't allow both, because that results in exponential
7191    run time recusion.  There is a nullstone testcase that triggered
7192    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7193 #define num_sign_bit_copies()
7194
7195 /* Given an expression, X, compute which bits in X can be non-zero.
7196    We don't care about bits outside of those defined in MODE.
7197
7198    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7199    a shift, AND, or zero_extract, we can do better.  */
7200
7201 static unsigned HOST_WIDE_INT
7202 nonzero_bits (x, mode)
7203      rtx x;
7204      enum machine_mode mode;
7205 {
7206   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7207   unsigned HOST_WIDE_INT inner_nz;
7208   enum rtx_code code;
7209   int mode_width = GET_MODE_BITSIZE (mode);
7210   rtx tem;
7211
7212   /* For floating-point values, assume all bits are needed.  */
7213   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7214     return nonzero;
7215
7216   /* If X is wider than MODE, use its mode instead.  */
7217   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7218     {
7219       mode = GET_MODE (x);
7220       nonzero = GET_MODE_MASK (mode);
7221       mode_width = GET_MODE_BITSIZE (mode);
7222     }
7223
7224   if (mode_width > HOST_BITS_PER_WIDE_INT)
7225     /* Our only callers in this case look for single bit values.  So
7226        just return the mode mask.  Those tests will then be false.  */
7227     return nonzero;
7228
7229 #ifndef WORD_REGISTER_OPERATIONS
7230   /* If MODE is wider than X, but both are a single word for both the host
7231      and target machines, we can compute this from which bits of the
7232      object might be nonzero in its own mode, taking into account the fact
7233      that on many CISC machines, accessing an object in a wider mode
7234      causes the high-order bits to become undefined.  So they are
7235      not known to be zero.  */
7236
7237   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7238       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7239       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7240       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7241     {
7242       nonzero &= nonzero_bits (x, GET_MODE (x));
7243       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7244       return nonzero;
7245     }
7246 #endif
7247
7248   code = GET_CODE (x);
7249   switch (code)
7250     {
7251     case REG:
7252 #ifdef POINTERS_EXTEND_UNSIGNED
7253       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7254          all the bits above ptr_mode are known to be zero.  */
7255       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7256           && REGNO_POINTER_FLAG (REGNO (x)))
7257         nonzero &= GET_MODE_MASK (ptr_mode);
7258 #endif
7259
7260 #ifdef STACK_BOUNDARY
7261       /* If this is the stack pointer, we may know something about its
7262          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7263          stack to be momentarily aligned only to that amount, so we pick
7264          the least alignment.  */
7265
7266       /* We can't check for arg_pointer_rtx here, because it is not
7267          guaranteed to have as much alignment as the stack pointer.
7268          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7269          alignment but the argument pointer has only 64 bit alignment.  */
7270
7271       if (x == stack_pointer_rtx || x == frame_pointer_rtx
7272           || x == hard_frame_pointer_rtx
7273           || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7274               && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7275         {
7276           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7277
7278 #ifdef PUSH_ROUNDING
7279           if (REGNO (x) == STACK_POINTER_REGNUM)
7280             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7281 #endif
7282
7283           /* We must return here, otherwise we may get a worse result from
7284              one of the choices below.  There is nothing useful below as
7285              far as the stack pointer is concerned.  */
7286           return nonzero &= ~ (sp_alignment - 1);
7287         }
7288 #endif
7289
7290       /* If X is a register whose nonzero bits value is current, use it.
7291          Otherwise, if X is a register whose value we can find, use that
7292          value.  Otherwise, use the previously-computed global nonzero bits
7293          for this register.  */
7294
7295       if (reg_last_set_value[REGNO (x)] != 0
7296           && reg_last_set_mode[REGNO (x)] == mode
7297           && (REG_N_SETS (REGNO (x)) == 1
7298               || reg_last_set_label[REGNO (x)] == label_tick)
7299           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7300         return reg_last_set_nonzero_bits[REGNO (x)];
7301
7302       tem = get_last_value (x);
7303
7304       if (tem)
7305         {
7306 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7307           /* If X is narrower than MODE and TEM is a non-negative
7308              constant that would appear negative in the mode of X,
7309              sign-extend it for use in reg_nonzero_bits because some
7310              machines (maybe most) will actually do the sign-extension
7311              and this is the conservative approach.
7312
7313              ??? For 2.5, try to tighten up the MD files in this regard
7314              instead of this kludge.  */
7315
7316           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7317               && GET_CODE (tem) == CONST_INT
7318               && INTVAL (tem) > 0
7319               && 0 != (INTVAL (tem)
7320                        & ((HOST_WIDE_INT) 1
7321                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7322             tem = GEN_INT (INTVAL (tem)
7323                            | ((HOST_WIDE_INT) (-1)
7324                               << GET_MODE_BITSIZE (GET_MODE (x))));
7325 #endif
7326           return nonzero_bits (tem, mode);
7327         }
7328       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7329         return reg_nonzero_bits[REGNO (x)] & nonzero;
7330       else
7331         return nonzero;
7332
7333     case CONST_INT:
7334 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7335       /* If X is negative in MODE, sign-extend the value.  */
7336       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7337           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7338         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7339 #endif
7340
7341       return INTVAL (x);
7342
7343     case MEM:
7344 #ifdef LOAD_EXTEND_OP
7345       /* In many, if not most, RISC machines, reading a byte from memory
7346          zeros the rest of the register.  Noticing that fact saves a lot
7347          of extra zero-extends.  */
7348       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7349         nonzero &= GET_MODE_MASK (GET_MODE (x));
7350 #endif
7351       break;
7352
7353     case EQ:  case NE:
7354     case GT:  case GTU:
7355     case LT:  case LTU:
7356     case GE:  case GEU:
7357     case LE:  case LEU:
7358
7359       /* If this produces an integer result, we know which bits are set.
7360          Code here used to clear bits outside the mode of X, but that is
7361          now done above.  */
7362
7363       if (GET_MODE_CLASS (mode) == MODE_INT
7364           && mode_width <= HOST_BITS_PER_WIDE_INT)
7365         nonzero = STORE_FLAG_VALUE;
7366       break;
7367
7368     case NEG:
7369 #if 0
7370       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7371          and num_sign_bit_copies.  */
7372       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7373           == GET_MODE_BITSIZE (GET_MODE (x)))
7374         nonzero = 1;
7375 #endif
7376
7377       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7378         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7379       break;
7380
7381     case ABS:
7382 #if 0
7383       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7384          and num_sign_bit_copies.  */
7385       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7386           == GET_MODE_BITSIZE (GET_MODE (x)))
7387         nonzero = 1;
7388 #endif
7389       break;
7390
7391     case TRUNCATE:
7392       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7393       break;
7394
7395     case ZERO_EXTEND:
7396       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7397       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7398         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7399       break;
7400
7401     case SIGN_EXTEND:
7402       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7403          Otherwise, show all the bits in the outer mode but not the inner
7404          may be non-zero.  */
7405       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7406       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7407         {
7408           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7409           if (inner_nz
7410               & (((HOST_WIDE_INT) 1
7411                   << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7412             inner_nz |= (GET_MODE_MASK (mode)
7413                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7414         }
7415
7416       nonzero &= inner_nz;
7417       break;
7418
7419     case AND:
7420       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7421                   & nonzero_bits (XEXP (x, 1), mode));
7422       break;
7423
7424     case XOR:   case IOR:
7425     case UMIN:  case UMAX:  case SMIN:  case SMAX:
7426       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7427                   | nonzero_bits (XEXP (x, 1), mode));
7428       break;
7429
7430     case PLUS:  case MINUS:
7431     case MULT:
7432     case DIV:   case UDIV:
7433     case MOD:   case UMOD:
7434       /* We can apply the rules of arithmetic to compute the number of
7435          high- and low-order zero bits of these operations.  We start by
7436          computing the width (position of the highest-order non-zero bit)
7437          and the number of low-order zero bits for each value.  */
7438       {
7439         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7440         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7441         int width0 = floor_log2 (nz0) + 1;
7442         int width1 = floor_log2 (nz1) + 1;
7443         int low0 = floor_log2 (nz0 & -nz0);
7444         int low1 = floor_log2 (nz1 & -nz1);
7445         HOST_WIDE_INT op0_maybe_minusp
7446           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7447         HOST_WIDE_INT op1_maybe_minusp
7448           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7449         int result_width = mode_width;
7450         int result_low = 0;
7451
7452         switch (code)
7453           {
7454           case PLUS:
7455             result_width = MAX (width0, width1) + 1;
7456             result_low = MIN (low0, low1);
7457             break;
7458           case MINUS:
7459             result_low = MIN (low0, low1);
7460             break;
7461           case MULT:
7462             result_width = width0 + width1;
7463             result_low = low0 + low1;
7464             break;
7465           case DIV:
7466             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7467               result_width = width0;
7468             break;
7469           case UDIV:
7470             result_width = width0;
7471             break;
7472           case MOD:
7473             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7474               result_width = MIN (width0, width1);
7475             result_low = MIN (low0, low1);
7476             break;
7477           case UMOD:
7478             result_width = MIN (width0, width1);
7479             result_low = MIN (low0, low1);
7480             break;
7481           default:
7482             abort ();
7483           }
7484
7485         if (result_width < mode_width)
7486           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7487
7488         if (result_low > 0)
7489           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7490       }
7491       break;
7492
7493     case ZERO_EXTRACT:
7494       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7495           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7496         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7497       break;
7498
7499     case SUBREG:
7500       /* If this is a SUBREG formed for a promoted variable that has
7501          been zero-extended, we know that at least the high-order bits
7502          are zero, though others might be too.  */
7503
7504       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7505         nonzero = (GET_MODE_MASK (GET_MODE (x))
7506                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7507
7508       /* If the inner mode is a single word for both the host and target
7509          machines, we can compute this from which bits of the inner
7510          object might be nonzero.  */
7511       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7512           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7513               <= HOST_BITS_PER_WIDE_INT))
7514         {
7515           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7516
7517 #ifndef WORD_REGISTER_OPERATIONS
7518           /* On many CISC machines, accessing an object in a wider mode
7519              causes the high-order bits to become undefined.  So they are
7520              not known to be zero.  */
7521           if (GET_MODE_SIZE (GET_MODE (x))
7522               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7523             nonzero |= (GET_MODE_MASK (GET_MODE (x))
7524                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7525 #endif
7526         }
7527       break;
7528
7529     case ASHIFTRT:
7530     case LSHIFTRT:
7531     case ASHIFT:
7532     case ROTATE:
7533       /* The nonzero bits are in two classes: any bits within MODE
7534          that aren't in GET_MODE (x) are always significant.  The rest of the
7535          nonzero bits are those that are significant in the operand of
7536          the shift when shifted the appropriate number of bits.  This
7537          shows that high-order bits are cleared by the right shift and
7538          low-order bits by left shifts.  */
7539       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7540           && INTVAL (XEXP (x, 1)) >= 0
7541           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7542         {
7543           enum machine_mode inner_mode = GET_MODE (x);
7544           int width = GET_MODE_BITSIZE (inner_mode);
7545           int count = INTVAL (XEXP (x, 1));
7546           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7547           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7548           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7549           unsigned HOST_WIDE_INT outer = 0;
7550
7551           if (mode_width > width)
7552             outer = (op_nonzero & nonzero & ~ mode_mask);
7553
7554           if (code == LSHIFTRT)
7555             inner >>= count;
7556           else if (code == ASHIFTRT)
7557             {
7558               inner >>= count;
7559
7560               /* If the sign bit may have been nonzero before the shift, we
7561                  need to mark all the places it could have been copied to
7562                  by the shift as possibly nonzero.  */
7563               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7564                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7565             }
7566           else if (code == ASHIFT)
7567             inner <<= count;
7568           else
7569             inner = ((inner << (count % width)
7570                       | (inner >> (width - (count % width)))) & mode_mask);
7571
7572           nonzero &= (outer | inner);
7573         }
7574       break;
7575
7576     case FFS:
7577       /* This is at most the number of bits in the mode.  */
7578       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7579       break;
7580
7581     case IF_THEN_ELSE:
7582       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7583                   | nonzero_bits (XEXP (x, 2), mode));
7584       break;
7585
7586     default:
7587       break;
7588     }
7589
7590   return nonzero;
7591 }
7592
7593 /* See the macro definition above.  */
7594 #undef num_sign_bit_copies
7595 \f
7596 /* Return the number of bits at the high-order end of X that are known to
7597    be equal to the sign bit.  X will be used in mode MODE; if MODE is
7598    VOIDmode, X will be used in its own mode.  The returned value  will always
7599    be between 1 and the number of bits in MODE.  */
7600
7601 static int
7602 num_sign_bit_copies (x, mode)
7603      rtx x;
7604      enum machine_mode mode;
7605 {
7606   enum rtx_code code = GET_CODE (x);
7607   int bitwidth;
7608   int num0, num1, result;
7609   unsigned HOST_WIDE_INT nonzero;
7610   rtx tem;
7611
7612   /* If we weren't given a mode, use the mode of X.  If the mode is still
7613      VOIDmode, we don't know anything.  Likewise if one of the modes is
7614      floating-point.  */
7615
7616   if (mode == VOIDmode)
7617     mode = GET_MODE (x);
7618
7619   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7620     return 1;
7621
7622   bitwidth = GET_MODE_BITSIZE (mode);
7623
7624   /* For a smaller object, just ignore the high bits.  */
7625   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7626     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7627                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7628
7629   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7630     {
7631 #ifndef WORD_REGISTER_OPERATIONS
7632   /* If this machine does not do all register operations on the entire
7633      register and MODE is wider than the mode of X, we can say nothing
7634      at all about the high-order bits.  */
7635       return 1;
7636 #else
7637       /* Likewise on machines that do, if the mode of the object is smaller
7638          than a word and loads of that size don't sign extend, we can say
7639          nothing about the high order bits.  */
7640       if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7641 #ifdef LOAD_EXTEND_OP
7642           && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7643 #endif
7644           )
7645         return 1;
7646 #endif
7647     }
7648
7649   switch (code)
7650     {
7651     case REG:
7652
7653 #ifdef POINTERS_EXTEND_UNSIGNED
7654       /* If pointers extend signed and this is a pointer in Pmode, say that
7655          all the bits above ptr_mode are known to be sign bit copies.  */
7656       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7657           && REGNO_POINTER_FLAG (REGNO (x)))
7658         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7659 #endif
7660
7661       if (reg_last_set_value[REGNO (x)] != 0
7662           && reg_last_set_mode[REGNO (x)] == mode
7663           && (REG_N_SETS (REGNO (x)) == 1
7664               || reg_last_set_label[REGNO (x)] == label_tick)
7665           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7666         return reg_last_set_sign_bit_copies[REGNO (x)];
7667
7668       tem =  get_last_value (x);
7669       if (tem != 0)
7670         return num_sign_bit_copies (tem, mode);
7671
7672       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7673         return reg_sign_bit_copies[REGNO (x)];
7674       break;
7675
7676     case MEM:
7677 #ifdef LOAD_EXTEND_OP
7678       /* Some RISC machines sign-extend all loads of smaller than a word.  */
7679       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7680         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7681 #endif
7682       break;
7683
7684     case CONST_INT:
7685       /* If the constant is negative, take its 1's complement and remask.
7686          Then see how many zero bits we have.  */
7687       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7688       if (bitwidth <= HOST_BITS_PER_WIDE_INT
7689           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7690         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7691
7692       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7693
7694     case SUBREG:
7695       /* If this is a SUBREG for a promoted object that is sign-extended
7696          and we are looking at it in a wider mode, we know that at least the
7697          high-order bits are known to be sign bit copies.  */
7698
7699       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7700         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7701                     num_sign_bit_copies (SUBREG_REG (x), mode));
7702
7703       /* For a smaller object, just ignore the high bits.  */
7704       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7705         {
7706           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7707           return MAX (1, (num0
7708                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7709                              - bitwidth)));
7710         }
7711
7712 #ifdef WORD_REGISTER_OPERATIONS
7713 #ifdef LOAD_EXTEND_OP
7714       /* For paradoxical SUBREGs on machines where all register operations
7715          affect the entire register, just look inside.  Note that we are
7716          passing MODE to the recursive call, so the number of sign bit copies
7717          will remain relative to that mode, not the inner mode.  */
7718
7719       /* This works only if loads sign extend.  Otherwise, if we get a
7720          reload for the inner part, it may be loaded from the stack, and
7721          then we lose all sign bit copies that existed before the store
7722          to the stack.  */
7723
7724       if ((GET_MODE_SIZE (GET_MODE (x))
7725            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7726           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7727         return num_sign_bit_copies (SUBREG_REG (x), mode);
7728 #endif
7729 #endif
7730       break;
7731
7732     case SIGN_EXTRACT:
7733       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7734         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7735       break;
7736
7737     case SIGN_EXTEND:
7738       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7739               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7740
7741     case TRUNCATE:
7742       /* For a smaller object, just ignore the high bits.  */
7743       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7744       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7745                               - bitwidth)));
7746
7747     case NOT:
7748       return num_sign_bit_copies (XEXP (x, 0), mode);
7749
7750     case ROTATE:       case ROTATERT:
7751       /* If we are rotating left by a number of bits less than the number
7752          of sign bit copies, we can just subtract that amount from the
7753          number.  */
7754       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7755           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7756         {
7757           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7758           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7759                                  : bitwidth - INTVAL (XEXP (x, 1))));
7760         }
7761       break;
7762
7763     case NEG:
7764       /* In general, this subtracts one sign bit copy.  But if the value
7765          is known to be positive, the number of sign bit copies is the
7766          same as that of the input.  Finally, if the input has just one bit
7767          that might be nonzero, all the bits are copies of the sign bit.  */
7768       nonzero = nonzero_bits (XEXP (x, 0), mode);
7769       if (nonzero == 1)
7770         return bitwidth;
7771
7772       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7773       if (num0 > 1
7774           && bitwidth <= HOST_BITS_PER_WIDE_INT
7775           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7776         num0--;
7777
7778       return num0;
7779
7780     case IOR:   case AND:   case XOR:
7781     case SMIN:  case SMAX:  case UMIN:  case UMAX:
7782       /* Logical operations will preserve the number of sign-bit copies.
7783          MIN and MAX operations always return one of the operands.  */
7784       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7785       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7786       return MIN (num0, num1);
7787
7788     case PLUS:  case MINUS:
7789       /* For addition and subtraction, we can have a 1-bit carry.  However,
7790          if we are subtracting 1 from a positive number, there will not
7791          be such a carry.  Furthermore, if the positive number is known to
7792          be 0 or 1, we know the result is either -1 or 0.  */
7793
7794       if (code == PLUS && XEXP (x, 1) == constm1_rtx
7795           && bitwidth <= HOST_BITS_PER_WIDE_INT)
7796         {
7797           nonzero = nonzero_bits (XEXP (x, 0), mode);
7798           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7799             return (nonzero == 1 || nonzero == 0 ? bitwidth
7800                     : bitwidth - floor_log2 (nonzero) - 1);
7801         }
7802
7803       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7804       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7805       return MAX (1, MIN (num0, num1) - 1);
7806
7807     case MULT:
7808       /* The number of bits of the product is the sum of the number of
7809          bits of both terms.  However, unless one of the terms if known
7810          to be positive, we must allow for an additional bit since negating
7811          a negative number can remove one sign bit copy.  */
7812
7813       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7814       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7815
7816       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7817       if (result > 0
7818           && bitwidth <= HOST_BITS_PER_WIDE_INT
7819           && ((nonzero_bits (XEXP (x, 0), mode)
7820                & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7821           && ((nonzero_bits (XEXP (x, 1), mode)
7822               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7823         result--;
7824
7825       return MAX (1, result);
7826
7827     case UDIV:
7828       /* The result must be <= the first operand.  */
7829       return num_sign_bit_copies (XEXP (x, 0), mode);
7830
7831     case UMOD:
7832       /* The result must be <= the scond operand.  */
7833       return num_sign_bit_copies (XEXP (x, 1), mode);
7834
7835     case DIV:
7836       /* Similar to unsigned division, except that we have to worry about
7837          the case where the divisor is negative, in which case we have
7838          to add 1.  */
7839       result = num_sign_bit_copies (XEXP (x, 0), mode);
7840       if (result > 1
7841           && bitwidth <= HOST_BITS_PER_WIDE_INT
7842           && (nonzero_bits (XEXP (x, 1), mode)
7843               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7844         result --;
7845
7846       return result;
7847
7848     case MOD:
7849       result = num_sign_bit_copies (XEXP (x, 1), mode);
7850       if (result > 1
7851           && bitwidth <= HOST_BITS_PER_WIDE_INT
7852           && (nonzero_bits (XEXP (x, 1), mode)
7853               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7854         result --;
7855
7856       return result;
7857
7858     case ASHIFTRT:
7859       /* Shifts by a constant add to the number of bits equal to the
7860          sign bit.  */
7861       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7862       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7863           && INTVAL (XEXP (x, 1)) > 0)
7864         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7865
7866       return num0;
7867
7868     case ASHIFT:
7869       /* Left shifts destroy copies.  */
7870       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7871           || INTVAL (XEXP (x, 1)) < 0
7872           || INTVAL (XEXP (x, 1)) >= bitwidth)
7873         return 1;
7874
7875       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7876       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7877
7878     case IF_THEN_ELSE:
7879       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7880       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7881       return MIN (num0, num1);
7882
7883     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
7884     case GEU: case GTU: case LEU: case LTU:
7885       if (STORE_FLAG_VALUE == -1)
7886         return bitwidth;
7887       break;
7888
7889     default:
7890       break;
7891     }
7892
7893   /* If we haven't been able to figure it out by one of the above rules,
7894      see if some of the high-order bits are known to be zero.  If so,
7895      count those bits and return one less than that amount.  If we can't
7896      safely compute the mask for this mode, always return BITWIDTH.  */
7897
7898   if (bitwidth > HOST_BITS_PER_WIDE_INT)
7899     return 1;
7900
7901   nonzero = nonzero_bits (x, mode);
7902   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7903           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7904 }
7905 \f
7906 /* Return the number of "extended" bits there are in X, when interpreted
7907    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
7908    unsigned quantities, this is the number of high-order zero bits.
7909    For signed quantities, this is the number of copies of the sign bit
7910    minus 1.  In both case, this function returns the number of "spare"
7911    bits.  For example, if two quantities for which this function returns
7912    at least 1 are added, the addition is known not to overflow.
7913
7914    This function will always return 0 unless called during combine, which
7915    implies that it must be called from a define_split.  */
7916
7917 int
7918 extended_count (x, mode, unsignedp)
7919      rtx x;
7920      enum machine_mode mode;
7921      int unsignedp;
7922 {
7923   if (nonzero_sign_valid == 0)
7924     return 0;
7925
7926   return (unsignedp
7927           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7928              && (GET_MODE_BITSIZE (mode) - 1
7929                  - floor_log2 (nonzero_bits (x, mode))))
7930           : num_sign_bit_copies (x, mode) - 1);
7931 }
7932 \f
7933 /* This function is called from `simplify_shift_const' to merge two
7934    outer operations.  Specifically, we have already found that we need
7935    to perform operation *POP0 with constant *PCONST0 at the outermost
7936    position.  We would now like to also perform OP1 with constant CONST1
7937    (with *POP0 being done last).
7938
7939    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7940    the resulting operation.  *PCOMP_P is set to 1 if we would need to
7941    complement the innermost operand, otherwise it is unchanged.
7942
7943    MODE is the mode in which the operation will be done.  No bits outside
7944    the width of this mode matter.  It is assumed that the width of this mode
7945    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7946
7947    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
7948    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
7949    result is simply *PCONST0.
7950
7951    If the resulting operation cannot be expressed as one operation, we
7952    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
7953
7954 static int
7955 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7956      enum rtx_code *pop0;
7957      HOST_WIDE_INT *pconst0;
7958      enum rtx_code op1;
7959      HOST_WIDE_INT const1;
7960      enum machine_mode mode;
7961      int *pcomp_p;
7962 {
7963   enum rtx_code op0 = *pop0;
7964   HOST_WIDE_INT const0 = *pconst0;
7965   int width = GET_MODE_BITSIZE (mode);
7966
7967   const0 &= GET_MODE_MASK (mode);
7968   const1 &= GET_MODE_MASK (mode);
7969
7970   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
7971   if (op0 == AND)
7972     const1 &= const0;
7973
7974   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
7975      if OP0 is SET.  */
7976
7977   if (op1 == NIL || op0 == SET)
7978     return 1;
7979
7980   else if (op0 == NIL)
7981     op0 = op1, const0 = const1;
7982
7983   else if (op0 == op1)
7984     {
7985       switch (op0)
7986         {
7987         case AND:
7988           const0 &= const1;
7989           break;
7990         case IOR:
7991           const0 |= const1;
7992           break;
7993         case XOR:
7994           const0 ^= const1;
7995           break;
7996         case PLUS:
7997           const0 += const1;
7998           break;
7999         case NEG:
8000           op0 = NIL;
8001           break;
8002         default:
8003           break;
8004         }
8005     }
8006
8007   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8008   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8009     return 0;
8010
8011   /* If the two constants aren't the same, we can't do anything.  The
8012      remaining six cases can all be done.  */
8013   else if (const0 != const1)
8014     return 0;
8015
8016   else
8017     switch (op0)
8018       {
8019       case IOR:
8020         if (op1 == AND)
8021           /* (a & b) | b == b */
8022           op0 = SET;
8023         else /* op1 == XOR */
8024           /* (a ^ b) | b == a | b */
8025           ;
8026         break;
8027
8028       case XOR:
8029         if (op1 == AND)
8030           /* (a & b) ^ b == (~a) & b */
8031           op0 = AND, *pcomp_p = 1;
8032         else /* op1 == IOR */
8033           /* (a | b) ^ b == a & ~b */
8034           op0 = AND, *pconst0 = ~ const0;
8035         break;
8036
8037       case AND:
8038         if (op1 == IOR)
8039           /* (a | b) & b == b */
8040         op0 = SET;
8041         else /* op1 == XOR */
8042           /* (a ^ b) & b) == (~a) & b */
8043           *pcomp_p = 1;
8044         break;
8045       default:
8046         break;
8047       }
8048
8049   /* Check for NO-OP cases.  */
8050   const0 &= GET_MODE_MASK (mode);
8051   if (const0 == 0
8052       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8053     op0 = NIL;
8054   else if (const0 == 0 && op0 == AND)
8055     op0 = SET;
8056   else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8057     op0 = NIL;
8058
8059   /* If this would be an entire word for the target, but is not for
8060      the host, then sign-extend on the host so that the number will look
8061      the same way on the host that it would on the target.
8062
8063      For example, when building a 64 bit alpha hosted 32 bit sparc
8064      targeted compiler, then we want the 32 bit unsigned value -1 to be
8065      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8066      The later confuses the sparc backend.  */
8067
8068   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8069       && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8070     const0 |= ((HOST_WIDE_INT) (-1) << width);
8071
8072   *pop0 = op0;
8073   *pconst0 = const0;
8074
8075   return 1;
8076 }
8077 \f
8078 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8079    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
8080    that we started with.
8081
8082    The shift is normally computed in the widest mode we find in VAROP, as
8083    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8084    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8085
8086 static rtx
8087 simplify_shift_const (x, code, result_mode, varop, count)
8088      rtx x;
8089      enum rtx_code code;
8090      enum machine_mode result_mode;
8091      rtx varop;
8092      int count;
8093 {
8094   enum rtx_code orig_code = code;
8095   int orig_count = count;
8096   enum machine_mode mode = result_mode;
8097   enum machine_mode shift_mode, tmode;
8098   int mode_words
8099     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8100   /* We form (outer_op (code varop count) (outer_const)).  */
8101   enum rtx_code outer_op = NIL;
8102   HOST_WIDE_INT outer_const = 0;
8103   rtx const_rtx;
8104   int complement_p = 0;
8105   rtx new;
8106
8107   /* If we were given an invalid count, don't do anything except exactly
8108      what was requested.  */
8109
8110   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8111     {
8112       if (x)
8113         return x;
8114
8115       return gen_rtx (code, mode, varop, GEN_INT (count));
8116     }
8117
8118   /* Unless one of the branches of the `if' in this loop does a `continue',
8119      we will `break' the loop after the `if'.  */
8120
8121   while (count != 0)
8122     {
8123       /* If we have an operand of (clobber (const_int 0)), just return that
8124          value.  */
8125       if (GET_CODE (varop) == CLOBBER)
8126         return varop;
8127
8128       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8129          here would cause an infinite loop.  */
8130       if (complement_p)
8131         break;
8132
8133       /* Convert ROTATERT to ROTATE.  */
8134       if (code == ROTATERT)
8135         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8136
8137       /* We need to determine what mode we will do the shift in.  If the
8138          shift is a right shift or a ROTATE, we must always do it in the mode
8139          it was originally done in.  Otherwise, we can do it in MODE, the
8140          widest mode encountered.  */
8141       shift_mode
8142         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8143            ? result_mode : mode);
8144
8145       /* Handle cases where the count is greater than the size of the mode
8146          minus 1.  For ASHIFT, use the size minus one as the count (this can
8147          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8148          take the count modulo the size.  For other shifts, the result is
8149          zero.
8150
8151          Since these shifts are being produced by the compiler by combining
8152          multiple operations, each of which are defined, we know what the
8153          result is supposed to be.  */
8154
8155       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8156         {
8157           if (code == ASHIFTRT)
8158             count = GET_MODE_BITSIZE (shift_mode) - 1;
8159           else if (code == ROTATE || code == ROTATERT)
8160             count %= GET_MODE_BITSIZE (shift_mode);
8161           else
8162             {
8163               /* We can't simply return zero because there may be an
8164                  outer op.  */
8165               varop = const0_rtx;
8166               count = 0;
8167               break;
8168             }
8169         }
8170
8171       /* Negative counts are invalid and should not have been made (a
8172          programmer-specified negative count should have been handled
8173          above).  */
8174       else if (count < 0)
8175         abort ();
8176
8177       /* An arithmetic right shift of a quantity known to be -1 or 0
8178          is a no-op.  */
8179       if (code == ASHIFTRT
8180           && (num_sign_bit_copies (varop, shift_mode)
8181               == GET_MODE_BITSIZE (shift_mode)))
8182         {
8183           count = 0;
8184           break;
8185         }
8186
8187       /* If we are doing an arithmetic right shift and discarding all but
8188          the sign bit copies, this is equivalent to doing a shift by the
8189          bitsize minus one.  Convert it into that shift because it will often
8190          allow other simplifications.  */
8191
8192       if (code == ASHIFTRT
8193           && (count + num_sign_bit_copies (varop, shift_mode)
8194               >= GET_MODE_BITSIZE (shift_mode)))
8195         count = GET_MODE_BITSIZE (shift_mode) - 1;
8196
8197       /* We simplify the tests below and elsewhere by converting
8198          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8199          `make_compound_operation' will convert it to a ASHIFTRT for
8200          those machines (such as Vax) that don't have a LSHIFTRT.  */
8201       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8202           && code == ASHIFTRT
8203           && ((nonzero_bits (varop, shift_mode)
8204                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8205               == 0))
8206         code = LSHIFTRT;
8207
8208       switch (GET_CODE (varop))
8209         {
8210         case SIGN_EXTEND:
8211         case ZERO_EXTEND:
8212         case SIGN_EXTRACT:
8213         case ZERO_EXTRACT:
8214           new = expand_compound_operation (varop);
8215           if (new != varop)
8216             {
8217               varop = new;
8218               continue;
8219             }
8220           break;
8221
8222         case MEM:
8223           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8224              minus the width of a smaller mode, we can do this with a
8225              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8226           if ((code == ASHIFTRT || code == LSHIFTRT)
8227               && ! mode_dependent_address_p (XEXP (varop, 0))
8228               && ! MEM_VOLATILE_P (varop)
8229               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8230                                          MODE_INT, 1)) != BLKmode)
8231             {
8232               if (BYTES_BIG_ENDIAN)
8233                 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8234               else
8235                 new = gen_rtx (MEM, tmode,
8236                                plus_constant (XEXP (varop, 0),
8237                                               count / BITS_PER_UNIT));
8238               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8239               MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8240               MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8241               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8242                                        : ZERO_EXTEND, mode, new);
8243               count = 0;
8244               continue;
8245             }
8246           break;
8247
8248         case USE:
8249           /* Similar to the case above, except that we can only do this if
8250              the resulting mode is the same as that of the underlying
8251              MEM and adjust the address depending on the *bits* endianness
8252              because of the way that bit-field extract insns are defined.  */
8253           if ((code == ASHIFTRT || code == LSHIFTRT)
8254               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8255                                          MODE_INT, 1)) != BLKmode
8256               && tmode == GET_MODE (XEXP (varop, 0)))
8257             {
8258               if (BITS_BIG_ENDIAN)
8259                 new = XEXP (varop, 0);
8260               else
8261                 {
8262                   new = copy_rtx (XEXP (varop, 0));
8263                   SUBST (XEXP (new, 0),
8264                          plus_constant (XEXP (new, 0),
8265                                         count / BITS_PER_UNIT));
8266                 }
8267
8268               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8269                                        : ZERO_EXTEND, mode, new);
8270               count = 0;
8271               continue;
8272             }
8273           break;
8274
8275         case SUBREG:
8276           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8277              the same number of words as what we've seen so far.  Then store
8278              the widest mode in MODE.  */
8279           if (subreg_lowpart_p (varop)
8280               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8281                   > GET_MODE_SIZE (GET_MODE (varop)))
8282               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8283                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8284                   == mode_words))
8285             {
8286               varop = SUBREG_REG (varop);
8287               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8288                 mode = GET_MODE (varop);
8289               continue;
8290             }
8291           break;
8292
8293         case MULT:
8294           /* Some machines use MULT instead of ASHIFT because MULT
8295              is cheaper.  But it is still better on those machines to
8296              merge two shifts into one.  */
8297           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8298               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8299             {
8300               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8301                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8302               continue;
8303             }
8304           break;
8305
8306         case UDIV:
8307           /* Similar, for when divides are cheaper.  */
8308           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8309               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8310             {
8311               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8312                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8313               continue;
8314             }
8315           break;
8316
8317         case ASHIFTRT:
8318           /* If we are extracting just the sign bit of an arithmetic right
8319              shift, that shift is not needed.  */
8320           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8321             {
8322               varop = XEXP (varop, 0);
8323               continue;
8324             }
8325
8326           /* ... fall through ...  */
8327
8328         case LSHIFTRT:
8329         case ASHIFT:
8330         case ROTATE:
8331           /* Here we have two nested shifts.  The result is usually the
8332              AND of a new shift with a mask.  We compute the result below.  */
8333           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8334               && INTVAL (XEXP (varop, 1)) >= 0
8335               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8336               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8337               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8338             {
8339               enum rtx_code first_code = GET_CODE (varop);
8340               int first_count = INTVAL (XEXP (varop, 1));
8341               unsigned HOST_WIDE_INT mask;
8342               rtx mask_rtx;
8343
8344               /* We have one common special case.  We can't do any merging if
8345                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8346                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8347                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8348                  we can convert it to
8349                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8350                  This simplifies certain SIGN_EXTEND operations.  */
8351               if (code == ASHIFT && first_code == ASHIFTRT
8352                   && (GET_MODE_BITSIZE (result_mode)
8353                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8354                 {
8355                   /* C3 has the low-order C1 bits zero.  */
8356
8357                   mask = (GET_MODE_MASK (mode)
8358                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8359
8360                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8361                                                   XEXP (varop, 0), mask);
8362                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8363                                                 varop, count);
8364                   count = first_count;
8365                   code = ASHIFTRT;
8366                   continue;
8367                 }
8368
8369               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8370                  than C1 high-order bits equal to the sign bit, we can convert
8371                  this to either an ASHIFT or a ASHIFTRT depending on the
8372                  two counts.
8373
8374                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8375
8376               if (code == ASHIFTRT && first_code == ASHIFT
8377                   && GET_MODE (varop) == shift_mode
8378                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8379                       > first_count))
8380                 {
8381                   count -= first_count;
8382                   if (count < 0)
8383                     count = - count, code = ASHIFT;
8384                   varop = XEXP (varop, 0);
8385                   continue;
8386                 }
8387
8388               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8389                  we can only do this if FIRST_CODE is also ASHIFTRT.
8390
8391                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8392                  ASHIFTRT.
8393
8394                  If the mode of this shift is not the mode of the outer shift,
8395                  we can't do this if either shift is a right shift or ROTATE.
8396
8397                  Finally, we can't do any of these if the mode is too wide
8398                  unless the codes are the same.
8399
8400                  Handle the case where the shift codes are the same
8401                  first.  */
8402
8403               if (code == first_code)
8404                 {
8405                   if (GET_MODE (varop) != result_mode
8406                       && (code == ASHIFTRT || code == LSHIFTRT
8407                           || code == ROTATE))
8408                     break;
8409
8410                   count += first_count;
8411                   varop = XEXP (varop, 0);
8412                   continue;
8413                 }
8414
8415               if (code == ASHIFTRT
8416                   || (code == ROTATE && first_code == ASHIFTRT)
8417                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8418                   || (GET_MODE (varop) != result_mode
8419                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8420                           || first_code == ROTATE
8421                           || code == ROTATE)))
8422                 break;
8423
8424               /* To compute the mask to apply after the shift, shift the
8425                  nonzero bits of the inner shift the same way the
8426                  outer shift will.  */
8427
8428               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8429
8430               mask_rtx
8431                 = simplify_binary_operation (code, result_mode, mask_rtx,
8432                                              GEN_INT (count));
8433
8434               /* Give up if we can't compute an outer operation to use.  */
8435               if (mask_rtx == 0
8436                   || GET_CODE (mask_rtx) != CONST_INT
8437                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8438                                         INTVAL (mask_rtx),
8439                                         result_mode, &complement_p))
8440                 break;
8441
8442               /* If the shifts are in the same direction, we add the
8443                  counts.  Otherwise, we subtract them.  */
8444               if ((code == ASHIFTRT || code == LSHIFTRT)
8445                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8446                 count += first_count;
8447               else
8448                 count -= first_count;
8449
8450               /* If COUNT is positive, the new shift is usually CODE,
8451                  except for the two exceptions below, in which case it is
8452                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8453                  always be used  */
8454               if (count > 0
8455                   && ((first_code == ROTATE && code == ASHIFT)
8456                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8457                 code = first_code;
8458               else if (count < 0)
8459                 code = first_code, count = - count;
8460
8461               varop = XEXP (varop, 0);
8462               continue;
8463             }
8464
8465           /* If we have (A << B << C) for any shift, we can convert this to
8466              (A << C << B).  This wins if A is a constant.  Only try this if
8467              B is not a constant.  */
8468
8469           else if (GET_CODE (varop) == code
8470                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
8471                    && 0 != (new
8472                             = simplify_binary_operation (code, mode,
8473                                                          XEXP (varop, 0),
8474                                                          GEN_INT (count))))
8475             {
8476               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8477               count = 0;
8478               continue;
8479             }
8480           break;
8481
8482         case NOT:
8483           /* Make this fit the case below.  */
8484           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8485                                    GEN_INT (GET_MODE_MASK (mode)));
8486           continue;
8487
8488         case IOR:
8489         case AND:
8490         case XOR:
8491           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8492              with C the size of VAROP - 1 and the shift is logical if
8493              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8494              we have an (le X 0) operation.   If we have an arithmetic shift
8495              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8496              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8497
8498           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8499               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8500               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8501               && (code == LSHIFTRT || code == ASHIFTRT)
8502               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8503               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8504             {
8505               count = 0;
8506               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8507                                        const0_rtx);
8508
8509               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8510                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8511
8512               continue;
8513             }
8514
8515           /* If we have (shift (logical)), move the logical to the outside
8516              to allow it to possibly combine with another logical and the
8517              shift to combine with another shift.  This also canonicalizes to
8518              what a ZERO_EXTRACT looks like.  Also, some machines have
8519              (and (shift)) insns.  */
8520
8521           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8522               && (new = simplify_binary_operation (code, result_mode,
8523                                                    XEXP (varop, 1),
8524                                                    GEN_INT (count))) != 0
8525               && GET_CODE(new) == CONST_INT
8526               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8527                                   INTVAL (new), result_mode, &complement_p))
8528             {
8529               varop = XEXP (varop, 0);
8530               continue;
8531             }
8532
8533           /* If we can't do that, try to simplify the shift in each arm of the
8534              logical expression, make a new logical expression, and apply
8535              the inverse distributive law.  */
8536           {
8537             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8538                                             XEXP (varop, 0), count);
8539             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8540                                             XEXP (varop, 1), count);
8541
8542             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8543             varop = apply_distributive_law (varop);
8544
8545             count = 0;
8546           }
8547           break;
8548
8549         case EQ:
8550           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8551              says that the sign bit can be tested, FOO has mode MODE, C is
8552              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8553              that may be nonzero.  */
8554           if (code == LSHIFTRT
8555               && XEXP (varop, 1) == const0_rtx
8556               && GET_MODE (XEXP (varop, 0)) == result_mode
8557               && count == GET_MODE_BITSIZE (result_mode) - 1
8558               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8559               && ((STORE_FLAG_VALUE
8560                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8561               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8562               && merge_outer_ops (&outer_op, &outer_const, XOR,
8563                                   (HOST_WIDE_INT) 1, result_mode,
8564                                   &complement_p))
8565             {
8566               varop = XEXP (varop, 0);
8567               count = 0;
8568               continue;
8569             }
8570           break;
8571
8572         case NEG:
8573           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8574              than the number of bits in the mode is equivalent to A.  */
8575           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8576               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8577             {
8578               varop = XEXP (varop, 0);
8579               count = 0;
8580               continue;
8581             }
8582
8583           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8584              NEG outside to allow shifts to combine.  */
8585           if (code == ASHIFT
8586               && merge_outer_ops (&outer_op, &outer_const, NEG,
8587                                   (HOST_WIDE_INT) 0, result_mode,
8588                                   &complement_p))
8589             {
8590               varop = XEXP (varop, 0);
8591               continue;
8592             }
8593           break;
8594
8595         case PLUS:
8596           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8597              is one less than the number of bits in the mode is
8598              equivalent to (xor A 1).  */
8599           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8600               && XEXP (varop, 1) == constm1_rtx
8601               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8602               && merge_outer_ops (&outer_op, &outer_const, XOR,
8603                                   (HOST_WIDE_INT) 1, result_mode,
8604                                   &complement_p))
8605             {
8606               count = 0;
8607               varop = XEXP (varop, 0);
8608               continue;
8609             }
8610
8611           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8612              that might be nonzero in BAR are those being shifted out and those
8613              bits are known zero in FOO, we can replace the PLUS with FOO.
8614              Similarly in the other operand order.  This code occurs when
8615              we are computing the size of a variable-size array.  */
8616
8617           if ((code == ASHIFTRT || code == LSHIFTRT)
8618               && count < HOST_BITS_PER_WIDE_INT
8619               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8620               && (nonzero_bits (XEXP (varop, 1), result_mode)
8621                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8622             {
8623               varop = XEXP (varop, 0);
8624               continue;
8625             }
8626           else if ((code == ASHIFTRT || code == LSHIFTRT)
8627                    && count < HOST_BITS_PER_WIDE_INT
8628                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8629                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8630                             >> count)
8631                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8632                             & nonzero_bits (XEXP (varop, 1),
8633                                                  result_mode)))
8634             {
8635               varop = XEXP (varop, 1);
8636               continue;
8637             }
8638
8639           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
8640           if (code == ASHIFT
8641               && GET_CODE (XEXP (varop, 1)) == CONST_INT
8642               && (new = simplify_binary_operation (ASHIFT, result_mode,
8643                                                    XEXP (varop, 1),
8644                                                    GEN_INT (count))) != 0
8645               && GET_CODE(new) == CONST_INT
8646               && merge_outer_ops (&outer_op, &outer_const, PLUS,
8647                                   INTVAL (new), result_mode, &complement_p))
8648             {
8649               varop = XEXP (varop, 0);
8650               continue;
8651             }
8652           break;
8653
8654         case MINUS:
8655           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8656              with C the size of VAROP - 1 and the shift is logical if
8657              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8658              we have a (gt X 0) operation.  If the shift is arithmetic with
8659              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8660              we have a (neg (gt X 0)) operation.  */
8661
8662           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8663               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8664               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8665               && (code == LSHIFTRT || code == ASHIFTRT)
8666               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8667               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8668               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8669             {
8670               count = 0;
8671               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8672                                        const0_rtx);
8673
8674               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8675                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8676
8677               continue;
8678             }
8679           break;
8680
8681         default:
8682           break;
8683         }
8684
8685       break;
8686     }
8687
8688   /* We need to determine what mode to do the shift in.  If the shift is
8689      a right shift or ROTATE, we must always do it in the mode it was
8690      originally done in.  Otherwise, we can do it in MODE, the widest mode
8691      encountered.  The code we care about is that of the shift that will
8692      actually be done, not the shift that was originally requested.  */
8693   shift_mode
8694     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8695        ? result_mode : mode);
8696
8697   /* We have now finished analyzing the shift.  The result should be
8698      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
8699      OUTER_OP is non-NIL, it is an operation that needs to be applied
8700      to the result of the shift.  OUTER_CONST is the relevant constant,
8701      but we must turn off all bits turned off in the shift.
8702
8703      If we were passed a value for X, see if we can use any pieces of
8704      it.  If not, make new rtx.  */
8705
8706   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8707       && GET_CODE (XEXP (x, 1)) == CONST_INT
8708       && INTVAL (XEXP (x, 1)) == count)
8709     const_rtx = XEXP (x, 1);
8710   else
8711     const_rtx = GEN_INT (count);
8712
8713   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8714       && GET_MODE (XEXP (x, 0)) == shift_mode
8715       && SUBREG_REG (XEXP (x, 0)) == varop)
8716     varop = XEXP (x, 0);
8717   else if (GET_MODE (varop) != shift_mode)
8718     varop = gen_lowpart_for_combine (shift_mode, varop);
8719
8720   /* If we can't make the SUBREG, try to return what we were given.  */
8721   if (GET_CODE (varop) == CLOBBER)
8722     return x ? x : varop;
8723
8724   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8725   if (new != 0)
8726     x = new;
8727   else
8728     {
8729       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8730         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8731
8732       SUBST (XEXP (x, 0), varop);
8733       SUBST (XEXP (x, 1), const_rtx);
8734     }
8735
8736   /* If we have an outer operation and we just made a shift, it is
8737      possible that we could have simplified the shift were it not
8738      for the outer operation.  So try to do the simplification
8739      recursively.  */
8740
8741   if (outer_op != NIL && GET_CODE (x) == code
8742       && GET_CODE (XEXP (x, 1)) == CONST_INT)
8743     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8744                               INTVAL (XEXP (x, 1)));
8745
8746   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8747      turn off all the bits that the shift would have turned off.  */
8748   if (orig_code == LSHIFTRT && result_mode != shift_mode)
8749     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8750                                 GET_MODE_MASK (result_mode) >> orig_count);
8751
8752   /* Do the remainder of the processing in RESULT_MODE.  */
8753   x = gen_lowpart_for_combine (result_mode, x);
8754
8755   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8756      operation.  */
8757   if (complement_p)
8758     x = gen_unary (NOT, result_mode, result_mode, x);
8759
8760   if (outer_op != NIL)
8761     {
8762       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8763         {
8764           int width = GET_MODE_BITSIZE (result_mode);
8765
8766           outer_const &= GET_MODE_MASK (result_mode);
8767
8768           /* If this would be an entire word for the target, but is not for
8769              the host, then sign-extend on the host so that the number will
8770              look the same way on the host that it would on the target.
8771
8772              For example, when building a 64 bit alpha hosted 32 bit sparc
8773              targeted compiler, then we want the 32 bit unsigned value -1 to be
8774              represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8775              The later confuses the sparc backend.  */
8776
8777           if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8778               && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8779             outer_const |= ((HOST_WIDE_INT) (-1) << width);
8780         }
8781
8782       if (outer_op == AND)
8783         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8784       else if (outer_op == SET)
8785         /* This means that we have determined that the result is
8786            equivalent to a constant.  This should be rare.  */
8787         x = GEN_INT (outer_const);
8788       else if (GET_RTX_CLASS (outer_op) == '1')
8789         x = gen_unary (outer_op, result_mode, result_mode, x);
8790       else
8791         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8792     }
8793
8794   return x;
8795 }
8796 \f
8797 /* Like recog, but we receive the address of a pointer to a new pattern.
8798    We try to match the rtx that the pointer points to.
8799    If that fails, we may try to modify or replace the pattern,
8800    storing the replacement into the same pointer object.
8801
8802    Modifications include deletion or addition of CLOBBERs.
8803
8804    PNOTES is a pointer to a location where any REG_UNUSED notes added for
8805    the CLOBBERs are placed.
8806
8807    PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8808    we had to add.
8809
8810    The value is the final insn code from the pattern ultimately matched,
8811    or -1.  */
8812
8813 static int
8814 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8815      rtx *pnewpat;
8816      rtx insn;
8817      rtx *pnotes;
8818      int *padded_scratches;
8819 {
8820   register rtx pat = *pnewpat;
8821   int insn_code_number;
8822   int num_clobbers_to_add = 0;
8823   int i;
8824   rtx notes = 0;
8825
8826   *padded_scratches = 0;
8827
8828   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8829      we use to indicate that something didn't match.  If we find such a
8830      thing, force rejection.  */
8831   if (GET_CODE (pat) == PARALLEL)
8832     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8833       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8834           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8835         return -1;
8836
8837   /* Is the result of combination a valid instruction?  */
8838   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8839
8840   /* If it isn't, there is the possibility that we previously had an insn
8841      that clobbered some register as a side effect, but the combined
8842      insn doesn't need to do that.  So try once more without the clobbers
8843      unless this represents an ASM insn.  */
8844
8845   if (insn_code_number < 0 && ! check_asm_operands (pat)
8846       && GET_CODE (pat) == PARALLEL)
8847     {
8848       int pos;
8849
8850       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8851         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8852           {
8853             if (i != pos)
8854               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8855             pos++;
8856           }
8857
8858       SUBST_INT (XVECLEN (pat, 0), pos);
8859
8860       if (pos == 1)
8861         pat = XVECEXP (pat, 0, 0);
8862
8863       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8864     }
8865
8866   /* If we had any clobbers to add, make a new pattern than contains
8867      them.  Then check to make sure that all of them are dead.  */
8868   if (num_clobbers_to_add)
8869     {
8870       rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8871                             gen_rtvec (GET_CODE (pat) == PARALLEL
8872                                        ? XVECLEN (pat, 0) + num_clobbers_to_add
8873                                        : num_clobbers_to_add + 1));
8874
8875       if (GET_CODE (pat) == PARALLEL)
8876         for (i = 0; i < XVECLEN (pat, 0); i++)
8877           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8878       else
8879         XVECEXP (newpat, 0, 0) = pat;
8880
8881       add_clobbers (newpat, insn_code_number);
8882
8883       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8884            i < XVECLEN (newpat, 0); i++)
8885         {
8886           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8887               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8888             return -1;
8889           else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8890             (*padded_scratches)++;
8891           notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8892                            XEXP (XVECEXP (newpat, 0, i), 0), notes);
8893         }
8894       pat = newpat;
8895     }
8896
8897   *pnewpat = pat;
8898   *pnotes = notes;
8899
8900   return insn_code_number;
8901 }
8902 \f
8903 /* Like gen_lowpart but for use by combine.  In combine it is not possible
8904    to create any new pseudoregs.  However, it is safe to create
8905    invalid memory addresses, because combine will try to recognize
8906    them and all they will do is make the combine attempt fail.
8907
8908    If for some reason this cannot do its job, an rtx
8909    (clobber (const_int 0)) is returned.
8910    An insn containing that will not be recognized.  */
8911
8912 #undef gen_lowpart
8913
8914 static rtx
8915 gen_lowpart_for_combine (mode, x)
8916      enum machine_mode mode;
8917      register rtx x;
8918 {
8919   rtx result;
8920
8921   if (GET_MODE (x) == mode)
8922     return x;
8923
8924   /* We can only support MODE being wider than a word if X is a
8925      constant integer or has a mode the same size.  */
8926
8927   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8928       && ! ((GET_MODE (x) == VOIDmode
8929              && (GET_CODE (x) == CONST_INT
8930                  || GET_CODE (x) == CONST_DOUBLE))
8931             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8932     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8933
8934   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
8935      won't know what to do.  So we will strip off the SUBREG here and
8936      process normally.  */
8937   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8938     {
8939       x = SUBREG_REG (x);
8940       if (GET_MODE (x) == mode)
8941         return x;
8942     }
8943
8944   result = gen_lowpart_common (mode, x);
8945   if (result != 0
8946       && GET_CODE (result) == SUBREG
8947       && GET_CODE (SUBREG_REG (result)) == REG
8948       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8949       && (GET_MODE_SIZE (GET_MODE (result))
8950           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8951     REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8952
8953   if (result)
8954     return result;
8955
8956   if (GET_CODE (x) == MEM)
8957     {
8958       register int offset = 0;
8959       rtx new;
8960
8961       /* Refuse to work on a volatile memory ref or one with a mode-dependent
8962          address.  */
8963       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8964         return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8965
8966       /* If we want to refer to something bigger than the original memref,
8967          generate a perverse subreg instead.  That will force a reload
8968          of the original memref X.  */
8969       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8970         return gen_rtx (SUBREG, mode, x, 0);
8971
8972       if (WORDS_BIG_ENDIAN)
8973         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8974                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8975       if (BYTES_BIG_ENDIAN)
8976         {
8977           /* Adjust the address so that the address-after-the-data is
8978              unchanged.  */
8979           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8980                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8981         }
8982       new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8983       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8984       MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8985       MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8986       return new;
8987     }
8988
8989   /* If X is a comparison operator, rewrite it in a new mode.  This
8990      probably won't match, but may allow further simplifications.  */
8991   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8992     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8993
8994   /* If we couldn't simplify X any other way, just enclose it in a
8995      SUBREG.  Normally, this SUBREG won't match, but some patterns may
8996      include an explicit SUBREG or we may simplify it further in combine.  */
8997   else
8998     {
8999       int word = 0;
9000
9001       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9002         word = ((GET_MODE_SIZE (GET_MODE (x))
9003                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9004                 / UNITS_PER_WORD);
9005       return gen_rtx (SUBREG, mode, x, word);
9006     }
9007 }
9008 \f
9009 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
9010    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9011
9012    If the identical expression was previously in the insn (in the undobuf),
9013    it will be returned.  Only if it is not found will a new expression
9014    be made.  */
9015
9016 /*VARARGS2*/
9017 static rtx
9018 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9019 {
9020 #ifndef __STDC__
9021   enum rtx_code code;
9022   enum machine_mode mode;
9023 #endif
9024   va_list p;
9025   int n_args;
9026   rtx args[3];
9027   int i, j;
9028   char *fmt;
9029   rtx rt;
9030   struct undo *undo;
9031
9032   VA_START (p, mode);
9033
9034 #ifndef __STDC__
9035   code = va_arg (p, enum rtx_code);
9036   mode = va_arg (p, enum machine_mode);
9037 #endif
9038
9039   n_args = GET_RTX_LENGTH (code);
9040   fmt = GET_RTX_FORMAT (code);
9041
9042   if (n_args == 0 || n_args > 3)
9043     abort ();
9044
9045   /* Get each arg and verify that it is supposed to be an expression.  */
9046   for (j = 0; j < n_args; j++)
9047     {
9048       if (*fmt++ != 'e')
9049         abort ();
9050
9051       args[j] = va_arg (p, rtx);
9052     }
9053
9054   /* See if this is in undobuf.  Be sure we don't use objects that came
9055      from another insn; this could produce circular rtl structures.  */
9056
9057   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9058     if (!undo->is_int
9059         && GET_CODE (undo->old_contents.r) == code
9060         && GET_MODE (undo->old_contents.r) == mode)
9061       {
9062         for (j = 0; j < n_args; j++)
9063           if (XEXP (undo->old_contents.r, j) != args[j])
9064             break;
9065
9066         if (j == n_args)
9067           return undo->old_contents.r;
9068       }
9069
9070   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
9071      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
9072   rt = rtx_alloc (code);
9073   PUT_MODE (rt, mode);
9074   XEXP (rt, 0) = args[0];
9075   if (n_args > 1)
9076     {
9077       XEXP (rt, 1) = args[1];
9078       if (n_args > 2)
9079         XEXP (rt, 2) = args[2];
9080     }
9081   return rt;
9082 }
9083
9084 /* These routines make binary and unary operations by first seeing if they
9085    fold; if not, a new expression is allocated.  */
9086
9087 static rtx
9088 gen_binary (code, mode, op0, op1)
9089      enum rtx_code code;
9090      enum machine_mode mode;
9091      rtx op0, op1;
9092 {
9093   rtx result;
9094   rtx tem;
9095
9096   if (GET_RTX_CLASS (code) == 'c'
9097       && (GET_CODE (op0) == CONST_INT
9098           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9099     tem = op0, op0 = op1, op1 = tem;
9100
9101   if (GET_RTX_CLASS (code) == '<')
9102     {
9103       enum machine_mode op_mode = GET_MODE (op0);
9104
9105       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9106          just (REL_OP X Y).  */
9107       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9108         {
9109           op1 = XEXP (op0, 1);
9110           op0 = XEXP (op0, 0);
9111           op_mode = GET_MODE (op0);
9112         }
9113
9114       if (op_mode == VOIDmode)
9115         op_mode = GET_MODE (op1);
9116       result = simplify_relational_operation (code, op_mode, op0, op1);
9117     }
9118   else
9119     result = simplify_binary_operation (code, mode, op0, op1);
9120
9121   if (result)
9122     return result;
9123
9124   /* Put complex operands first and constants second.  */
9125   if (GET_RTX_CLASS (code) == 'c'
9126       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9127           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9128               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9129           || (GET_CODE (op0) == SUBREG
9130               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9131               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9132     return gen_rtx_combine (code, mode, op1, op0);
9133
9134   return gen_rtx_combine (code, mode, op0, op1);
9135 }
9136
9137 static rtx
9138 gen_unary (code, mode, op0_mode, op0)
9139      enum rtx_code code;
9140      enum machine_mode mode, op0_mode;
9141      rtx op0;
9142 {
9143   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9144
9145   if (result)
9146     return result;
9147
9148   return gen_rtx_combine (code, mode, op0);
9149 }
9150 \f
9151 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9152    comparison code that will be tested.
9153
9154    The result is a possibly different comparison code to use.  *POP0 and
9155    *POP1 may be updated.
9156
9157    It is possible that we might detect that a comparison is either always
9158    true or always false.  However, we do not perform general constant
9159    folding in combine, so this knowledge isn't useful.  Such tautologies
9160    should have been detected earlier.  Hence we ignore all such cases.  */
9161
9162 static enum rtx_code
9163 simplify_comparison (code, pop0, pop1)
9164      enum rtx_code code;
9165      rtx *pop0;
9166      rtx *pop1;
9167 {
9168   rtx op0 = *pop0;
9169   rtx op1 = *pop1;
9170   rtx tem, tem1;
9171   int i;
9172   enum machine_mode mode, tmode;
9173
9174   /* Try a few ways of applying the same transformation to both operands.  */
9175   while (1)
9176     {
9177 #ifndef WORD_REGISTER_OPERATIONS
9178       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9179          so check specially.  */
9180       if (code != GTU && code != GEU && code != LTU && code != LEU
9181           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9182           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9183           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9184           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9185           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9186           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9187               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9188           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9189           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9190           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9191           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9192           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9193           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9194           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9195           && (INTVAL (XEXP (op0, 1))
9196               == (GET_MODE_BITSIZE (GET_MODE (op0))
9197                   - (GET_MODE_BITSIZE
9198                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9199         {
9200           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9201           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9202         }
9203 #endif
9204
9205       /* If both operands are the same constant shift, see if we can ignore the
9206          shift.  We can if the shift is a rotate or if the bits shifted out of
9207          this shift are known to be zero for both inputs and if the type of
9208          comparison is compatible with the shift.  */
9209       if (GET_CODE (op0) == GET_CODE (op1)
9210           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9211           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9212               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9213                   && (code != GT && code != LT && code != GE && code != LE))
9214               || (GET_CODE (op0) == ASHIFTRT
9215                   && (code != GTU && code != LTU
9216                       && code != GEU && code != GEU)))
9217           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9218           && INTVAL (XEXP (op0, 1)) >= 0
9219           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9220           && XEXP (op0, 1) == XEXP (op1, 1))
9221         {
9222           enum machine_mode mode = GET_MODE (op0);
9223           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9224           int shift_count = INTVAL (XEXP (op0, 1));
9225
9226           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9227             mask &= (mask >> shift_count) << shift_count;
9228           else if (GET_CODE (op0) == ASHIFT)
9229             mask = (mask & (mask << shift_count)) >> shift_count;
9230
9231           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9232               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9233             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9234           else
9235             break;
9236         }
9237
9238       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9239          SUBREGs are of the same mode, and, in both cases, the AND would
9240          be redundant if the comparison was done in the narrower mode,
9241          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9242          and the operand's possibly nonzero bits are 0xffffff01; in that case
9243          if we only care about QImode, we don't need the AND).  This case
9244          occurs if the output mode of an scc insn is not SImode and
9245          STORE_FLAG_VALUE == 1 (e.g., the 386).
9246
9247          Similarly, check for a case where the AND's are ZERO_EXTEND
9248          operations from some narrower mode even though a SUBREG is not
9249          present.  */
9250
9251       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9252                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9253                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9254         {
9255           rtx inner_op0 = XEXP (op0, 0);
9256           rtx inner_op1 = XEXP (op1, 0);
9257           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9258           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9259           int changed = 0;
9260
9261           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9262               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9263                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9264               && (GET_MODE (SUBREG_REG (inner_op0))
9265                   == GET_MODE (SUBREG_REG (inner_op1)))
9266               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9267                   <= HOST_BITS_PER_WIDE_INT)
9268               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9269                                              GET_MODE (SUBREG_REG (op0)))))
9270               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9271                                              GET_MODE (SUBREG_REG (inner_op1))))))
9272             {
9273               op0 = SUBREG_REG (inner_op0);
9274               op1 = SUBREG_REG (inner_op1);
9275
9276               /* The resulting comparison is always unsigned since we masked
9277                  off the original sign bit.  */
9278               code = unsigned_condition (code);
9279
9280               changed = 1;
9281             }
9282
9283           else if (c0 == c1)
9284             for (tmode = GET_CLASS_NARROWEST_MODE
9285                  (GET_MODE_CLASS (GET_MODE (op0)));
9286                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9287               if (c0 == GET_MODE_MASK (tmode))
9288                 {
9289                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9290                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9291                   code = unsigned_condition (code);
9292                   changed = 1;
9293                   break;
9294                 }
9295
9296           if (! changed)
9297             break;
9298         }
9299
9300       /* If both operands are NOT, we can strip off the outer operation
9301          and adjust the comparison code for swapped operands; similarly for
9302          NEG, except that this must be an equality comparison.  */
9303       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9304                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9305                    && (code == EQ || code == NE)))
9306         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9307
9308       else
9309         break;
9310     }
9311
9312   /* If the first operand is a constant, swap the operands and adjust the
9313      comparison code appropriately, but don't do this if the second operand
9314      is already a constant integer.  */
9315   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9316     {
9317       tem = op0, op0 = op1, op1 = tem;
9318       code = swap_condition (code);
9319     }
9320
9321   /* We now enter a loop during which we will try to simplify the comparison.
9322      For the most part, we only are concerned with comparisons with zero,
9323      but some things may really be comparisons with zero but not start
9324      out looking that way.  */
9325
9326   while (GET_CODE (op1) == CONST_INT)
9327     {
9328       enum machine_mode mode = GET_MODE (op0);
9329       int mode_width = GET_MODE_BITSIZE (mode);
9330       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9331       int equality_comparison_p;
9332       int sign_bit_comparison_p;
9333       int unsigned_comparison_p;
9334       HOST_WIDE_INT const_op;
9335
9336       /* We only want to handle integral modes.  This catches VOIDmode,
9337          CCmode, and the floating-point modes.  An exception is that we
9338          can handle VOIDmode if OP0 is a COMPARE or a comparison
9339          operation.  */
9340
9341       if (GET_MODE_CLASS (mode) != MODE_INT
9342           && ! (mode == VOIDmode
9343                 && (GET_CODE (op0) == COMPARE
9344                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9345         break;
9346
9347       /* Get the constant we are comparing against and turn off all bits
9348          not on in our mode.  */
9349       const_op = INTVAL (op1);
9350       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9351         const_op &= mask;
9352
9353       /* If we are comparing against a constant power of two and the value
9354          being compared can only have that single bit nonzero (e.g., it was
9355          `and'ed with that bit), we can replace this with a comparison
9356          with zero.  */
9357       if (const_op
9358           && (code == EQ || code == NE || code == GE || code == GEU
9359               || code == LT || code == LTU)
9360           && mode_width <= HOST_BITS_PER_WIDE_INT
9361           && exact_log2 (const_op) >= 0
9362           && nonzero_bits (op0, mode) == const_op)
9363         {
9364           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9365           op1 = const0_rtx, const_op = 0;
9366         }
9367
9368       /* Similarly, if we are comparing a value known to be either -1 or
9369          0 with -1, change it to the opposite comparison against zero.  */
9370
9371       if (const_op == -1
9372           && (code == EQ || code == NE || code == GT || code == LE
9373               || code == GEU || code == LTU)
9374           && num_sign_bit_copies (op0, mode) == mode_width)
9375         {
9376           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9377           op1 = const0_rtx, const_op = 0;
9378         }
9379
9380       /* Do some canonicalizations based on the comparison code.  We prefer
9381          comparisons against zero and then prefer equality comparisons.
9382          If we can reduce the size of a constant, we will do that too.  */
9383
9384       switch (code)
9385         {
9386         case LT:
9387           /* < C is equivalent to <= (C - 1) */
9388           if (const_op > 0)
9389             {
9390               const_op -= 1;
9391               op1 = GEN_INT (const_op);
9392               code = LE;
9393               /* ... fall through to LE case below.  */
9394             }
9395           else
9396             break;
9397
9398         case LE:
9399           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9400           if (const_op < 0)
9401             {
9402               const_op += 1;
9403               op1 = GEN_INT (const_op);
9404               code = LT;
9405             }
9406
9407           /* If we are doing a <= 0 comparison on a value known to have
9408              a zero sign bit, we can replace this with == 0.  */
9409           else if (const_op == 0
9410                    && mode_width <= HOST_BITS_PER_WIDE_INT
9411                    && (nonzero_bits (op0, mode)
9412                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9413             code = EQ;
9414           break;
9415
9416         case GE:
9417           /* >= C is equivalent to > (C - 1).  */
9418           if (const_op > 0)
9419             {
9420               const_op -= 1;
9421               op1 = GEN_INT (const_op);
9422               code = GT;
9423               /* ... fall through to GT below.  */
9424             }
9425           else
9426             break;
9427
9428         case GT:
9429           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9430           if (const_op < 0)
9431             {
9432               const_op += 1;
9433               op1 = GEN_INT (const_op);
9434               code = GE;
9435             }
9436
9437           /* If we are doing a > 0 comparison on a value known to have
9438              a zero sign bit, we can replace this with != 0.  */
9439           else if (const_op == 0
9440                    && mode_width <= HOST_BITS_PER_WIDE_INT
9441                    && (nonzero_bits (op0, mode)
9442                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9443             code = NE;
9444           break;
9445
9446         case LTU:
9447           /* < C is equivalent to <= (C - 1).  */
9448           if (const_op > 0)
9449             {
9450               const_op -= 1;
9451               op1 = GEN_INT (const_op);
9452               code = LEU;
9453               /* ... fall through ...  */
9454             }
9455
9456           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9457           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9458                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9459             {
9460               const_op = 0, op1 = const0_rtx;
9461               code = GE;
9462               break;
9463             }
9464           else
9465             break;
9466
9467         case LEU:
9468           /* unsigned <= 0 is equivalent to == 0 */
9469           if (const_op == 0)
9470             code = EQ;
9471
9472           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9473           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9474                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9475             {
9476               const_op = 0, op1 = const0_rtx;
9477               code = GE;
9478             }
9479           break;
9480
9481         case GEU:
9482           /* >= C is equivalent to < (C - 1).  */
9483           if (const_op > 1)
9484             {
9485               const_op -= 1;
9486               op1 = GEN_INT (const_op);
9487               code = GTU;
9488               /* ... fall through ...  */
9489             }
9490
9491           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9492           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9493                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9494             {
9495               const_op = 0, op1 = const0_rtx;
9496               code = LT;
9497               break;
9498             }
9499           else
9500             break;
9501
9502         case GTU:
9503           /* unsigned > 0 is equivalent to != 0 */
9504           if (const_op == 0)
9505             code = NE;
9506
9507           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9508           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9509                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9510             {
9511               const_op = 0, op1 = const0_rtx;
9512               code = LT;
9513             }
9514           break;
9515
9516         default:
9517           break;
9518         }
9519
9520       /* Compute some predicates to simplify code below.  */
9521
9522       equality_comparison_p = (code == EQ || code == NE);
9523       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9524       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9525                                || code == LEU);
9526
9527       /* If this is a sign bit comparison and we can do arithmetic in
9528          MODE, say that we will only be needing the sign bit of OP0.  */
9529       if (sign_bit_comparison_p
9530           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9531         op0 = force_to_mode (op0, mode,
9532                              ((HOST_WIDE_INT) 1
9533                               << (GET_MODE_BITSIZE (mode) - 1)),
9534                              NULL_RTX, 0);
9535
9536       /* Now try cases based on the opcode of OP0.  If none of the cases
9537          does a "continue", we exit this loop immediately after the
9538          switch.  */
9539
9540       switch (GET_CODE (op0))
9541         {
9542         case ZERO_EXTRACT:
9543           /* If we are extracting a single bit from a variable position in
9544              a constant that has only a single bit set and are comparing it
9545              with zero, we can convert this into an equality comparison
9546              between the position and the location of the single bit.  */
9547
9548           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9549               && XEXP (op0, 1) == const1_rtx
9550               && equality_comparison_p && const_op == 0
9551               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9552             {
9553               if (BITS_BIG_ENDIAN)
9554 #ifdef HAVE_extzv
9555                 i = (GET_MODE_BITSIZE
9556                      (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9557 #else
9558                 i = BITS_PER_WORD - 1 - i;
9559 #endif
9560
9561               op0 = XEXP (op0, 2);
9562               op1 = GEN_INT (i);
9563               const_op = i;
9564
9565               /* Result is nonzero iff shift count is equal to I.  */
9566               code = reverse_condition (code);
9567               continue;
9568             }
9569
9570           /* ... fall through ...  */
9571
9572         case SIGN_EXTRACT:
9573           tem = expand_compound_operation (op0);
9574           if (tem != op0)
9575             {
9576               op0 = tem;
9577               continue;
9578             }
9579           break;
9580
9581         case NOT:
9582           /* If testing for equality, we can take the NOT of the constant.  */
9583           if (equality_comparison_p
9584               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9585             {
9586               op0 = XEXP (op0, 0);
9587               op1 = tem;
9588               continue;
9589             }
9590
9591           /* If just looking at the sign bit, reverse the sense of the
9592              comparison.  */
9593           if (sign_bit_comparison_p)
9594             {
9595               op0 = XEXP (op0, 0);
9596               code = (code == GE ? LT : GE);
9597               continue;
9598             }
9599           break;
9600
9601         case NEG:
9602           /* If testing for equality, we can take the NEG of the constant.  */
9603           if (equality_comparison_p
9604               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9605             {
9606               op0 = XEXP (op0, 0);
9607               op1 = tem;
9608               continue;
9609             }
9610
9611           /* The remaining cases only apply to comparisons with zero.  */
9612           if (const_op != 0)
9613             break;
9614
9615           /* When X is ABS or is known positive,
9616              (neg X) is < 0 if and only if X != 0.  */
9617
9618           if (sign_bit_comparison_p
9619               && (GET_CODE (XEXP (op0, 0)) == ABS
9620                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9621                       && (nonzero_bits (XEXP (op0, 0), mode)
9622                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9623             {
9624               op0 = XEXP (op0, 0);
9625               code = (code == LT ? NE : EQ);
9626               continue;
9627             }
9628
9629           /* If we have NEG of something whose two high-order bits are the
9630              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9631           if (num_sign_bit_copies (op0, mode) >= 2)
9632             {
9633               op0 = XEXP (op0, 0);
9634               code = swap_condition (code);
9635               continue;
9636             }
9637           break;
9638
9639         case ROTATE:
9640           /* If we are testing equality and our count is a constant, we
9641              can perform the inverse operation on our RHS.  */
9642           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9643               && (tem = simplify_binary_operation (ROTATERT, mode,
9644                                                    op1, XEXP (op0, 1))) != 0)
9645             {
9646               op0 = XEXP (op0, 0);
9647               op1 = tem;
9648               continue;
9649             }
9650
9651           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9652              a particular bit.  Convert it to an AND of a constant of that
9653              bit.  This will be converted into a ZERO_EXTRACT.  */
9654           if (const_op == 0 && sign_bit_comparison_p
9655               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9656               && mode_width <= HOST_BITS_PER_WIDE_INT)
9657             {
9658               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9659                                             ((HOST_WIDE_INT) 1
9660                                              << (mode_width - 1
9661                                                  - INTVAL (XEXP (op0, 1)))));
9662               code = (code == LT ? NE : EQ);
9663               continue;
9664             }
9665
9666           /* ... fall through ...  */
9667
9668         case ABS:
9669           /* ABS is ignorable inside an equality comparison with zero.  */
9670           if (const_op == 0 && equality_comparison_p)
9671             {
9672               op0 = XEXP (op0, 0);
9673               continue;
9674             }
9675           break;
9676
9677
9678         case SIGN_EXTEND:
9679           /* Can simplify (compare (zero/sign_extend FOO) CONST)
9680              to (compare FOO CONST) if CONST fits in FOO's mode and we
9681              are either testing inequality or have an unsigned comparison
9682              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
9683           if (! unsigned_comparison_p
9684               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9685                   <= HOST_BITS_PER_WIDE_INT)
9686               && ((unsigned HOST_WIDE_INT) const_op
9687                   < (((HOST_WIDE_INT) 1
9688                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9689             {
9690               op0 = XEXP (op0, 0);
9691               continue;
9692             }
9693           break;
9694
9695         case SUBREG:
9696           /* Check for the case where we are comparing A - C1 with C2,
9697              both constants are smaller than 1/2 the maximum positive
9698              value in MODE, and the comparison is equality or unsigned.
9699              In that case, if A is either zero-extended to MODE or has
9700              sufficient sign bits so that the high-order bit in MODE
9701              is a copy of the sign in the inner mode, we can prove that it is
9702              safe to do the operation in the wider mode.  This simplifies
9703              many range checks.  */
9704
9705           if (mode_width <= HOST_BITS_PER_WIDE_INT
9706               && subreg_lowpart_p (op0)
9707               && GET_CODE (SUBREG_REG (op0)) == PLUS
9708               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9709               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9710               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9711                   < GET_MODE_MASK (mode) / 2)
9712               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9713               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9714                                       GET_MODE (SUBREG_REG (op0)))
9715                         & ~ GET_MODE_MASK (mode))
9716                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9717                                            GET_MODE (SUBREG_REG (op0)))
9718                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9719                          - GET_MODE_BITSIZE (mode)))))
9720             {
9721               op0 = SUBREG_REG (op0);
9722               continue;
9723             }
9724
9725           /* If the inner mode is narrower and we are extracting the low part,
9726              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
9727           if (subreg_lowpart_p (op0)
9728               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9729             /* Fall through */ ;
9730           else
9731             break;
9732
9733           /* ... fall through ...  */
9734
9735         case ZERO_EXTEND:
9736           if ((unsigned_comparison_p || equality_comparison_p)
9737               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9738                   <= HOST_BITS_PER_WIDE_INT)
9739               && ((unsigned HOST_WIDE_INT) const_op
9740                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9741             {
9742               op0 = XEXP (op0, 0);
9743               continue;
9744             }
9745           break;
9746
9747         case PLUS:
9748           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
9749              this for equality comparisons due to pathological cases involving
9750              overflows.  */
9751           if (equality_comparison_p
9752               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9753                                                         op1, XEXP (op0, 1))))
9754             {
9755               op0 = XEXP (op0, 0);
9756               op1 = tem;
9757               continue;
9758             }
9759
9760           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
9761           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9762               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9763             {
9764               op0 = XEXP (XEXP (op0, 0), 0);
9765               code = (code == LT ? EQ : NE);
9766               continue;
9767             }
9768           break;
9769
9770         case MINUS:
9771           /* (eq (minus A B) C) -> (eq A (plus B C)) or
9772              (eq B (minus A C)), whichever simplifies.  We can only do
9773              this for equality comparisons due to pathological cases involving
9774              overflows.  */
9775           if (equality_comparison_p
9776               && 0 != (tem = simplify_binary_operation (PLUS, mode,
9777                                                         XEXP (op0, 1), op1)))
9778             {
9779               op0 = XEXP (op0, 0);
9780               op1 = tem;
9781               continue;
9782             }
9783
9784           if (equality_comparison_p
9785               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9786                                                         XEXP (op0, 0), op1)))
9787             {
9788               op0 = XEXP (op0, 1);
9789               op1 = tem;
9790               continue;
9791             }
9792
9793           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9794              of bits in X minus 1, is one iff X > 0.  */
9795           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9796               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9797               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9798               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9799             {
9800               op0 = XEXP (op0, 1);
9801               code = (code == GE ? LE : GT);
9802               continue;
9803             }
9804           break;
9805
9806         case XOR:
9807           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
9808              if C is zero or B is a constant.  */
9809           if (equality_comparison_p
9810               && 0 != (tem = simplify_binary_operation (XOR, mode,
9811                                                         XEXP (op0, 1), op1)))
9812             {
9813               op0 = XEXP (op0, 0);
9814               op1 = tem;
9815               continue;
9816             }
9817           break;
9818
9819         case EQ:  case NE:
9820         case LT:  case LTU:  case LE:  case LEU:
9821         case GT:  case GTU:  case GE:  case GEU:
9822           /* We can't do anything if OP0 is a condition code value, rather
9823              than an actual data value.  */
9824           if (const_op != 0
9825 #ifdef HAVE_cc0
9826               || XEXP (op0, 0) == cc0_rtx
9827 #endif
9828               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9829             break;
9830
9831           /* Get the two operands being compared.  */
9832           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9833             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9834           else
9835             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9836
9837           /* Check for the cases where we simply want the result of the
9838              earlier test or the opposite of that result.  */
9839           if (code == NE
9840               || (code == EQ && reversible_comparison_p (op0))
9841               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9842                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9843                   && (STORE_FLAG_VALUE
9844                       & (((HOST_WIDE_INT) 1
9845                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9846                   && (code == LT
9847                       || (code == GE && reversible_comparison_p (op0)))))
9848             {
9849               code = (code == LT || code == NE
9850                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9851               op0 = tem, op1 = tem1;
9852               continue;
9853             }
9854           break;
9855
9856         case IOR:
9857           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9858              iff X <= 0.  */
9859           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9860               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9861               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9862             {
9863               op0 = XEXP (op0, 1);
9864               code = (code == GE ? GT : LE);
9865               continue;
9866             }
9867           break;
9868
9869         case AND:
9870           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
9871              will be converted to a ZERO_EXTRACT later.  */
9872           if (const_op == 0 && equality_comparison_p
9873               && GET_CODE (XEXP (op0, 0)) == ASHIFT
9874               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9875             {
9876               op0 = simplify_and_const_int
9877                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9878                                              XEXP (op0, 1),
9879                                              XEXP (XEXP (op0, 0), 1)),
9880                  (HOST_WIDE_INT) 1);
9881               continue;
9882             }
9883
9884           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9885              zero and X is a comparison and C1 and C2 describe only bits set
9886              in STORE_FLAG_VALUE, we can compare with X.  */
9887           if (const_op == 0 && equality_comparison_p
9888               && mode_width <= HOST_BITS_PER_WIDE_INT
9889               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9890               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9891               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9892               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9893               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9894             {
9895               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9896                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
9897               if ((~ STORE_FLAG_VALUE & mask) == 0
9898                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9899                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9900                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9901                 {
9902                   op0 = XEXP (XEXP (op0, 0), 0);
9903                   continue;
9904                 }
9905             }
9906
9907           /* If we are doing an equality comparison of an AND of a bit equal
9908              to the sign bit, replace this with a LT or GE comparison of
9909              the underlying value.  */
9910           if (equality_comparison_p
9911               && const_op == 0
9912               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9913               && mode_width <= HOST_BITS_PER_WIDE_INT
9914               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9915                   == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9916             {
9917               op0 = XEXP (op0, 0);
9918               code = (code == EQ ? GE : LT);
9919               continue;
9920             }
9921
9922           /* If this AND operation is really a ZERO_EXTEND from a narrower
9923              mode, the constant fits within that mode, and this is either an
9924              equality or unsigned comparison, try to do this comparison in
9925              the narrower mode.  */
9926           if ((equality_comparison_p || unsigned_comparison_p)
9927               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9928               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9929                                    & GET_MODE_MASK (mode))
9930                                   + 1)) >= 0
9931               && const_op >> i == 0
9932               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9933             {
9934               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9935               continue;
9936             }
9937           break;
9938
9939         case ASHIFT:
9940           /* If we have (compare (ashift FOO N) (const_int C)) and
9941              the high order N bits of FOO (N+1 if an inequality comparison)
9942              are known to be zero, we can do this by comparing FOO with C
9943              shifted right N bits so long as the low-order N bits of C are
9944              zero.  */
9945           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9946               && INTVAL (XEXP (op0, 1)) >= 0
9947               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9948                   < HOST_BITS_PER_WIDE_INT)
9949               && ((const_op
9950                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9951               && mode_width <= HOST_BITS_PER_WIDE_INT
9952               && (nonzero_bits (XEXP (op0, 0), mode)
9953                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
9954                                 + ! equality_comparison_p))) == 0)
9955             {
9956               const_op >>= INTVAL (XEXP (op0, 1));
9957               op1 = GEN_INT (const_op);
9958               op0 = XEXP (op0, 0);
9959               continue;
9960             }
9961
9962           /* If we are doing a sign bit comparison, it means we are testing
9963              a particular bit.  Convert it to the appropriate AND.  */
9964           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9965               && mode_width <= HOST_BITS_PER_WIDE_INT)
9966             {
9967               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9968                                             ((HOST_WIDE_INT) 1
9969                                              << (mode_width - 1
9970                                                  - INTVAL (XEXP (op0, 1)))));
9971               code = (code == LT ? NE : EQ);
9972               continue;
9973             }
9974
9975           /* If this an equality comparison with zero and we are shifting
9976              the low bit to the sign bit, we can convert this to an AND of the
9977              low-order bit.  */
9978           if (const_op == 0 && equality_comparison_p
9979               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9980               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9981             {
9982               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9983                                             (HOST_WIDE_INT) 1);
9984               continue;
9985             }
9986           break;
9987
9988         case ASHIFTRT:
9989           /* If this is an equality comparison with zero, we can do this
9990              as a logical shift, which might be much simpler.  */
9991           if (equality_comparison_p && const_op == 0
9992               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9993             {
9994               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9995                                           XEXP (op0, 0),
9996                                           INTVAL (XEXP (op0, 1)));
9997               continue;
9998             }
9999
10000           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10001              do the comparison in a narrower mode.  */
10002           if (! unsigned_comparison_p
10003               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10004               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10005               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10006               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10007                                          MODE_INT, 1)) != BLKmode
10008               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10009                   || ((unsigned HOST_WIDE_INT) - const_op
10010                       <= GET_MODE_MASK (tmode))))
10011             {
10012               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10013               continue;
10014             }
10015
10016           /* ... fall through ...  */
10017         case LSHIFTRT:
10018           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10019              the low order N bits of FOO are known to be zero, we can do this
10020              by comparing FOO with C shifted left N bits so long as no
10021              overflow occurs.  */
10022           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10023               && INTVAL (XEXP (op0, 1)) >= 0
10024               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10025               && mode_width <= HOST_BITS_PER_WIDE_INT
10026               && (nonzero_bits (XEXP (op0, 0), mode)
10027                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10028               && (const_op == 0
10029                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10030                       < mode_width)))
10031             {
10032               const_op <<= INTVAL (XEXP (op0, 1));
10033               op1 = GEN_INT (const_op);
10034               op0 = XEXP (op0, 0);
10035               continue;
10036             }
10037
10038           /* If we are using this shift to extract just the sign bit, we
10039              can replace this with an LT or GE comparison.  */
10040           if (const_op == 0
10041               && (equality_comparison_p || sign_bit_comparison_p)
10042               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10043               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10044             {
10045               op0 = XEXP (op0, 0);
10046               code = (code == NE || code == GT ? LT : GE);
10047               continue;
10048             }
10049           break;
10050
10051         default:
10052           break;
10053         }
10054
10055       break;
10056     }
10057
10058   /* Now make any compound operations involved in this comparison.  Then,
10059      check for an outmost SUBREG on OP0 that isn't doing anything or is
10060      paradoxical.  The latter case can only occur when it is known that the
10061      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
10062      We can never remove a SUBREG for a non-equality comparison because the
10063      sign bit is in a different place in the underlying object.  */
10064
10065   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10066   op1 = make_compound_operation (op1, SET);
10067
10068   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10069       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10070       && (code == NE || code == EQ)
10071       && ((GET_MODE_SIZE (GET_MODE (op0))
10072            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10073     {
10074       op0 = SUBREG_REG (op0);
10075       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10076     }
10077
10078   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10079            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10080            && (code == NE || code == EQ)
10081            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10082                <= HOST_BITS_PER_WIDE_INT)
10083            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10084                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10085            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10086                                               op1),
10087                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10088                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10089     op0 = SUBREG_REG (op0), op1 = tem;
10090
10091   /* We now do the opposite procedure: Some machines don't have compare
10092      insns in all modes.  If OP0's mode is an integer mode smaller than a
10093      word and we can't do a compare in that mode, see if there is a larger
10094      mode for which we can do the compare.  There are a number of cases in
10095      which we can use the wider mode.  */
10096
10097   mode = GET_MODE (op0);
10098   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10099       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10100       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10101     for (tmode = GET_MODE_WIDER_MODE (mode);
10102          (tmode != VOIDmode
10103           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10104          tmode = GET_MODE_WIDER_MODE (tmode))
10105       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10106         {
10107           /* If the only nonzero bits in OP0 and OP1 are those in the
10108              narrower mode and this is an equality or unsigned comparison,
10109              we can use the wider mode.  Similarly for sign-extended
10110              values, in which case it is true for all comparisons.  */
10111           if (((code == EQ || code == NE
10112                 || code == GEU || code == GTU || code == LEU || code == LTU)
10113                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10114                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10115               || ((num_sign_bit_copies (op0, tmode)
10116                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10117                   && (num_sign_bit_copies (op1, tmode)
10118                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10119             {
10120               op0 = gen_lowpart_for_combine (tmode, op0);
10121               op1 = gen_lowpart_for_combine (tmode, op1);
10122               break;
10123             }
10124
10125           /* If this is a test for negative, we can make an explicit
10126              test of the sign bit.  */
10127
10128           if (op1 == const0_rtx && (code == LT || code == GE)
10129               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10130             {
10131               op0 = gen_binary (AND, tmode,
10132                                 gen_lowpart_for_combine (tmode, op0),
10133                                 GEN_INT ((HOST_WIDE_INT) 1
10134                                          << (GET_MODE_BITSIZE (mode) - 1)));
10135               code = (code == LT) ? NE : EQ;
10136               break;
10137             }
10138         }
10139
10140 #ifdef CANONICALIZE_COMPARISON
10141   /* If this machine only supports a subset of valid comparisons, see if we
10142      can convert an unsupported one into a supported one.  */
10143   CANONICALIZE_COMPARISON (code, op0, op1);
10144 #endif
10145
10146   *pop0 = op0;
10147   *pop1 = op1;
10148
10149   return code;
10150 }
10151 \f
10152 /* Return 1 if we know that X, a comparison operation, is not operating
10153    on a floating-point value or is EQ or NE, meaning that we can safely
10154    reverse it.  */
10155
10156 static int
10157 reversible_comparison_p (x)
10158      rtx x;
10159 {
10160   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10161       || flag_fast_math
10162       || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10163     return 1;
10164
10165   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10166     {
10167     case MODE_INT:
10168     case MODE_PARTIAL_INT:
10169     case MODE_COMPLEX_INT:
10170       return 1;
10171
10172     case MODE_CC:
10173       /* If the mode of the condition codes tells us that this is safe,
10174          we need look no further.  */
10175       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10176         return 1;
10177
10178       /* Otherwise try and find where the condition codes were last set and
10179          use that.  */
10180       x = get_last_value (XEXP (x, 0));
10181       return (x && GET_CODE (x) == COMPARE
10182               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10183
10184     default:
10185       return 0;
10186     }
10187 }
10188 \f
10189 /* Utility function for following routine.  Called when X is part of a value
10190    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10191    for each register mentioned.  Similar to mention_regs in cse.c  */
10192
10193 static void
10194 update_table_tick (x)
10195      rtx x;
10196 {
10197   register enum rtx_code code = GET_CODE (x);
10198   register char *fmt = GET_RTX_FORMAT (code);
10199   register int i;
10200
10201   if (code == REG)
10202     {
10203       int regno = REGNO (x);
10204       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10205                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10206
10207       for (i = regno; i < endregno; i++)
10208         reg_last_set_table_tick[i] = label_tick;
10209
10210       return;
10211     }
10212
10213   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10214     /* Note that we can't have an "E" in values stored; see
10215        get_last_value_validate.  */
10216     if (fmt[i] == 'e')
10217       update_table_tick (XEXP (x, i));
10218 }
10219
10220 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10221    are saying that the register is clobbered and we no longer know its
10222    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10223    with VALUE also zero and is used to invalidate the register.  */
10224
10225 static void
10226 record_value_for_reg (reg, insn, value)
10227      rtx reg;
10228      rtx insn;
10229      rtx value;
10230 {
10231   int regno = REGNO (reg);
10232   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10233                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10234   int i;
10235
10236   /* If VALUE contains REG and we have a previous value for REG, substitute
10237      the previous value.  */
10238   if (value && insn && reg_overlap_mentioned_p (reg, value))
10239     {
10240       rtx tem;
10241
10242       /* Set things up so get_last_value is allowed to see anything set up to
10243          our insn.  */
10244       subst_low_cuid = INSN_CUID (insn);
10245       tem = get_last_value (reg);
10246
10247       if (tem)
10248         value = replace_rtx (copy_rtx (value), reg, tem);
10249     }
10250
10251   /* For each register modified, show we don't know its value, that
10252      we don't know about its bitwise content, that its value has been
10253      updated, and that we don't know the location of the death of the
10254      register.  */
10255   for (i = regno; i < endregno; i ++)
10256     {
10257       if (insn)
10258         reg_last_set[i] = insn;
10259       reg_last_set_value[i] = 0;
10260       reg_last_set_mode[i] = 0;
10261       reg_last_set_nonzero_bits[i] = 0;
10262       reg_last_set_sign_bit_copies[i] = 0;
10263       reg_last_death[i] = 0;
10264     }
10265
10266   /* Mark registers that are being referenced in this value.  */
10267   if (value)
10268     update_table_tick (value);
10269
10270   /* Now update the status of each register being set.
10271      If someone is using this register in this block, set this register
10272      to invalid since we will get confused between the two lives in this
10273      basic block.  This makes using this register always invalid.  In cse, we
10274      scan the table to invalidate all entries using this register, but this
10275      is too much work for us.  */
10276
10277   for (i = regno; i < endregno; i++)
10278     {
10279       reg_last_set_label[i] = label_tick;
10280       if (value && reg_last_set_table_tick[i] == label_tick)
10281         reg_last_set_invalid[i] = 1;
10282       else
10283         reg_last_set_invalid[i] = 0;
10284     }
10285
10286   /* The value being assigned might refer to X (like in "x++;").  In that
10287      case, we must replace it with (clobber (const_int 0)) to prevent
10288      infinite loops.  */
10289   if (value && ! get_last_value_validate (&value, insn,
10290                                           reg_last_set_label[regno], 0))
10291     {
10292       value = copy_rtx (value);
10293       if (! get_last_value_validate (&value, insn,
10294                                      reg_last_set_label[regno], 1))
10295         value = 0;
10296     }
10297
10298   /* For the main register being modified, update the value, the mode, the
10299      nonzero bits, and the number of sign bit copies.  */
10300
10301   reg_last_set_value[regno] = value;
10302
10303   if (value)
10304     {
10305       subst_low_cuid = INSN_CUID (insn);
10306       reg_last_set_mode[regno] = GET_MODE (reg);
10307       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10308       reg_last_set_sign_bit_copies[regno]
10309         = num_sign_bit_copies (value, GET_MODE (reg));
10310     }
10311 }
10312
10313 /* Used for communication between the following two routines.  */
10314 static rtx record_dead_insn;
10315
10316 /* Called via note_stores from record_dead_and_set_regs to handle one
10317    SET or CLOBBER in an insn.  */
10318
10319 static void
10320 record_dead_and_set_regs_1 (dest, setter)
10321      rtx dest, setter;
10322 {
10323   if (GET_CODE (dest) == SUBREG)
10324     dest = SUBREG_REG (dest);
10325
10326   if (GET_CODE (dest) == REG)
10327     {
10328       /* If we are setting the whole register, we know its value.  Otherwise
10329          show that we don't know the value.  We can handle SUBREG in
10330          some cases.  */
10331       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10332         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10333       else if (GET_CODE (setter) == SET
10334                && GET_CODE (SET_DEST (setter)) == SUBREG
10335                && SUBREG_REG (SET_DEST (setter)) == dest
10336                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10337                && subreg_lowpart_p (SET_DEST (setter)))
10338         record_value_for_reg (dest, record_dead_insn,
10339                               gen_lowpart_for_combine (GET_MODE (dest),
10340                                                        SET_SRC (setter)));
10341       else
10342         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10343     }
10344   else if (GET_CODE (dest) == MEM
10345            /* Ignore pushes, they clobber nothing.  */
10346            && ! push_operand (dest, GET_MODE (dest)))
10347     mem_last_set = INSN_CUID (record_dead_insn);
10348 }
10349
10350 /* Update the records of when each REG was most recently set or killed
10351    for the things done by INSN.  This is the last thing done in processing
10352    INSN in the combiner loop.
10353
10354    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10355    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10356    and also the similar information mem_last_set (which insn most recently
10357    modified memory) and last_call_cuid (which insn was the most recent
10358    subroutine call).  */
10359
10360 static void
10361 record_dead_and_set_regs (insn)
10362      rtx insn;
10363 {
10364   register rtx link;
10365   int i;
10366
10367   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10368     {
10369       if (REG_NOTE_KIND (link) == REG_DEAD
10370           && GET_CODE (XEXP (link, 0)) == REG)
10371         {
10372           int regno = REGNO (XEXP (link, 0));
10373           int endregno
10374             = regno + (regno < FIRST_PSEUDO_REGISTER
10375                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10376                        : 1);
10377
10378           for (i = regno; i < endregno; i++)
10379             reg_last_death[i] = insn;
10380         }
10381       else if (REG_NOTE_KIND (link) == REG_INC)
10382         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10383     }
10384
10385   if (GET_CODE (insn) == CALL_INSN)
10386     {
10387       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10388         if (call_used_regs[i])
10389           {
10390             reg_last_set_value[i] = 0;
10391             reg_last_set_mode[i] = 0;
10392             reg_last_set_nonzero_bits[i] = 0;
10393             reg_last_set_sign_bit_copies[i] = 0;
10394             reg_last_death[i] = 0;
10395           }
10396
10397       last_call_cuid = mem_last_set = INSN_CUID (insn);
10398     }
10399
10400   record_dead_insn = insn;
10401   note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10402 }
10403 \f
10404 /* Utility routine for the following function.  Verify that all the registers
10405    mentioned in *LOC are valid when *LOC was part of a value set when
10406    label_tick == TICK.  Return 0 if some are not.
10407
10408    If REPLACE is non-zero, replace the invalid reference with
10409    (clobber (const_int 0)) and return 1.  This replacement is useful because
10410    we often can get useful information about the form of a value (e.g., if
10411    it was produced by a shift that always produces -1 or 0) even though
10412    we don't know exactly what registers it was produced from.  */
10413
10414 static int
10415 get_last_value_validate (loc, insn, tick, replace)
10416      rtx *loc;
10417      rtx insn;
10418      int tick;
10419      int replace;
10420 {
10421   rtx x = *loc;
10422   char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10423   int len = GET_RTX_LENGTH (GET_CODE (x));
10424   int i;
10425
10426   if (GET_CODE (x) == REG)
10427     {
10428       int regno = REGNO (x);
10429       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10430                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10431       int j;
10432
10433       for (j = regno; j < endregno; j++)
10434         if (reg_last_set_invalid[j]
10435             /* If this is a pseudo-register that was only set once, it is
10436                always valid.  */
10437             || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10438                 && reg_last_set_label[j] > tick))
10439           {
10440             if (replace)
10441               *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10442             return replace;
10443           }
10444
10445       return 1;
10446     }
10447   /* If this is a memory reference, make sure that there were
10448      no stores after it that might have clobbered the value.  We don't
10449      have alias info, so we assume any store invalidates it.  */
10450   else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10451            && INSN_CUID (insn) <= mem_last_set)
10452     {
10453       if (replace)
10454         *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10455       return replace;
10456     }
10457
10458   for (i = 0; i < len; i++)
10459     if ((fmt[i] == 'e'
10460          && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10461         /* Don't bother with these.  They shouldn't occur anyway.  */
10462         || fmt[i] == 'E')
10463       return 0;
10464
10465   /* If we haven't found a reason for it to be invalid, it is valid.  */
10466   return 1;
10467 }
10468
10469 /* Get the last value assigned to X, if known.  Some registers
10470    in the value may be replaced with (clobber (const_int 0)) if their value
10471    is known longer known reliably.  */
10472
10473 static rtx
10474 get_last_value (x)
10475      rtx x;
10476 {
10477   int regno;
10478   rtx value;
10479
10480   /* If this is a non-paradoxical SUBREG, get the value of its operand and
10481      then convert it to the desired mode.  If this is a paradoxical SUBREG,
10482      we cannot predict what values the "extra" bits might have.  */
10483   if (GET_CODE (x) == SUBREG
10484       && subreg_lowpart_p (x)
10485       && (GET_MODE_SIZE (GET_MODE (x))
10486           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10487       && (value = get_last_value (SUBREG_REG (x))) != 0)
10488     return gen_lowpart_for_combine (GET_MODE (x), value);
10489
10490   if (GET_CODE (x) != REG)
10491     return 0;
10492
10493   regno = REGNO (x);
10494   value = reg_last_set_value[regno];
10495
10496   /* If we don't have a value or if it isn't for this basic block,
10497      return 0.  */
10498
10499   if (value == 0
10500       || (REG_N_SETS (regno) != 1
10501           && reg_last_set_label[regno] != label_tick))
10502     return 0;
10503
10504   /* If the value was set in a later insn than the ones we are processing,
10505      we can't use it even if the register was only set once, but make a quick
10506      check to see if the previous insn set it to something.  This is commonly
10507      the case when the same pseudo is used by repeated insns.
10508
10509      This does not work if there exists an instruction which is temporarily
10510      not on the insn chain.  */
10511
10512   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10513     {
10514       rtx insn, set;
10515
10516       /* We can not do anything useful in this case, because there is
10517          an instruction which is not on the insn chain.  */
10518       if (subst_prev_insn)
10519         return 0;
10520
10521       /* Skip over USE insns.  They are not useful here, and they may have
10522          been made by combine, in which case they do not have a INSN_CUID
10523          value.  We can't use prev_real_insn, because that would incorrectly
10524          take us backwards across labels.  Skip over BARRIERs also, since
10525          they could have been made by combine.  If we see one, we must be
10526          optimizing dead code, so it doesn't matter what we do.  */
10527       for (insn = prev_nonnote_insn (subst_insn);
10528            insn && ((GET_CODE (insn) == INSN
10529                      && GET_CODE (PATTERN (insn)) == USE)
10530                     || GET_CODE (insn) == BARRIER
10531                     || INSN_CUID (insn) >= subst_low_cuid);
10532            insn = prev_nonnote_insn (insn))
10533         ;
10534
10535       if (insn
10536           && (set = single_set (insn)) != 0
10537           && rtx_equal_p (SET_DEST (set), x))
10538         {
10539           value = SET_SRC (set);
10540
10541           /* Make sure that VALUE doesn't reference X.  Replace any
10542              explicit references with a CLOBBER.  If there are any remaining
10543              references (rare), don't use the value.  */
10544
10545           if (reg_mentioned_p (x, value))
10546             value = replace_rtx (copy_rtx (value), x,
10547                                  gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10548
10549           if (reg_overlap_mentioned_p (x, value))
10550             return 0;
10551         }
10552       else
10553         return 0;
10554     }
10555
10556   /* If the value has all its registers valid, return it.  */
10557   if (get_last_value_validate (&value, reg_last_set[regno],
10558                                reg_last_set_label[regno], 0))
10559     return value;
10560
10561   /* Otherwise, make a copy and replace any invalid register with
10562      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
10563
10564   value = copy_rtx (value);
10565   if (get_last_value_validate (&value, reg_last_set[regno],
10566                                reg_last_set_label[regno], 1))
10567     return value;
10568
10569   return 0;
10570 }
10571 \f
10572 /* Return nonzero if expression X refers to a REG or to memory
10573    that is set in an instruction more recent than FROM_CUID.  */
10574
10575 static int
10576 use_crosses_set_p (x, from_cuid)
10577      register rtx x;
10578      int from_cuid;
10579 {
10580   register char *fmt;
10581   register int i;
10582   register enum rtx_code code = GET_CODE (x);
10583
10584   if (code == REG)
10585     {
10586       register int regno = REGNO (x);
10587       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10588                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10589
10590 #ifdef PUSH_ROUNDING
10591       /* Don't allow uses of the stack pointer to be moved,
10592          because we don't know whether the move crosses a push insn.  */
10593       if (regno == STACK_POINTER_REGNUM)
10594         return 1;
10595 #endif
10596       for (;regno < endreg; regno++)
10597         if (reg_last_set[regno]
10598             && INSN_CUID (reg_last_set[regno]) > from_cuid)
10599           return 1;
10600       return 0;
10601     }
10602
10603   if (code == MEM && mem_last_set > from_cuid)
10604     return 1;
10605
10606   fmt = GET_RTX_FORMAT (code);
10607
10608   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10609     {
10610       if (fmt[i] == 'E')
10611         {
10612           register int j;
10613           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10614             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10615               return 1;
10616         }
10617       else if (fmt[i] == 'e'
10618                && use_crosses_set_p (XEXP (x, i), from_cuid))
10619         return 1;
10620     }
10621   return 0;
10622 }
10623 \f
10624 /* Define three variables used for communication between the following
10625    routines.  */
10626
10627 static int reg_dead_regno, reg_dead_endregno;
10628 static int reg_dead_flag;
10629
10630 /* Function called via note_stores from reg_dead_at_p.
10631
10632    If DEST is within [reg_dead_regno, reg_dead_endregno), set
10633    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
10634
10635 static void
10636 reg_dead_at_p_1 (dest, x)
10637      rtx dest;
10638      rtx x;
10639 {
10640   int regno, endregno;
10641
10642   if (GET_CODE (dest) != REG)
10643     return;
10644
10645   regno = REGNO (dest);
10646   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10647                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10648
10649   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10650     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10651 }
10652
10653 /* Return non-zero if REG is known to be dead at INSN.
10654
10655    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
10656    referencing REG, it is dead.  If we hit a SET referencing REG, it is
10657    live.  Otherwise, see if it is live or dead at the start of the basic
10658    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
10659    must be assumed to be always live.  */
10660
10661 static int
10662 reg_dead_at_p (reg, insn)
10663      rtx reg;
10664      rtx insn;
10665 {
10666   int block, i;
10667
10668   /* Set variables for reg_dead_at_p_1.  */
10669   reg_dead_regno = REGNO (reg);
10670   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10671                                         ? HARD_REGNO_NREGS (reg_dead_regno,
10672                                                             GET_MODE (reg))
10673                                         : 1);
10674
10675   reg_dead_flag = 0;
10676
10677   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
10678   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10679     {
10680       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10681         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10682           return 0;
10683     }
10684
10685   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10686      beginning of function.  */
10687   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10688        insn = prev_nonnote_insn (insn))
10689     {
10690       note_stores (PATTERN (insn), reg_dead_at_p_1);
10691       if (reg_dead_flag)
10692         return reg_dead_flag == 1 ? 1 : 0;
10693
10694       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10695         return 1;
10696     }
10697
10698   /* Get the basic block number that we were in.  */
10699   if (insn == 0)
10700     block = 0;
10701   else
10702     {
10703       for (block = 0; block < n_basic_blocks; block++)
10704         if (insn == basic_block_head[block])
10705           break;
10706
10707       if (block == n_basic_blocks)
10708         return 0;
10709     }
10710
10711   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10712     if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10713       return 0;
10714
10715   return 1;
10716 }
10717 \f
10718 /* Note hard registers in X that are used.  This code is similar to
10719    that in flow.c, but much simpler since we don't care about pseudos.  */
10720
10721 static void
10722 mark_used_regs_combine (x)
10723      rtx x;
10724 {
10725   register RTX_CODE code = GET_CODE (x);
10726   register int regno;
10727   int i;
10728
10729   switch (code)
10730     {
10731     case LABEL_REF:
10732     case SYMBOL_REF:
10733     case CONST_INT:
10734     case CONST:
10735     case CONST_DOUBLE:
10736     case PC:
10737     case ADDR_VEC:
10738     case ADDR_DIFF_VEC:
10739     case ASM_INPUT:
10740 #ifdef HAVE_cc0
10741     /* CC0 must die in the insn after it is set, so we don't need to take
10742        special note of it here.  */
10743     case CC0:
10744 #endif
10745       return;
10746
10747     case CLOBBER:
10748       /* If we are clobbering a MEM, mark any hard registers inside the
10749          address as used.  */
10750       if (GET_CODE (XEXP (x, 0)) == MEM)
10751         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10752       return;
10753
10754     case REG:
10755       regno = REGNO (x);
10756       /* A hard reg in a wide mode may really be multiple registers.
10757          If so, mark all of them just like the first.  */
10758       if (regno < FIRST_PSEUDO_REGISTER)
10759         {
10760           /* None of this applies to the stack, frame or arg pointers */
10761           if (regno == STACK_POINTER_REGNUM
10762 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10763               || regno == HARD_FRAME_POINTER_REGNUM
10764 #endif
10765 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10766               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10767 #endif
10768               || regno == FRAME_POINTER_REGNUM)
10769             return;
10770
10771           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10772           while (i-- > 0)
10773             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10774         }
10775       return;
10776
10777     case SET:
10778       {
10779         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10780            the address.  */
10781         register rtx testreg = SET_DEST (x);
10782
10783         while (GET_CODE (testreg) == SUBREG
10784                || GET_CODE (testreg) == ZERO_EXTRACT
10785                || GET_CODE (testreg) == SIGN_EXTRACT
10786                || GET_CODE (testreg) == STRICT_LOW_PART)
10787           testreg = XEXP (testreg, 0);
10788
10789         if (GET_CODE (testreg) == MEM)
10790           mark_used_regs_combine (XEXP (testreg, 0));
10791
10792         mark_used_regs_combine (SET_SRC (x));
10793       }
10794       return;
10795
10796     default:
10797       break;
10798     }
10799
10800   /* Recursively scan the operands of this expression.  */
10801
10802   {
10803     register char *fmt = GET_RTX_FORMAT (code);
10804
10805     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10806       {
10807         if (fmt[i] == 'e')
10808           mark_used_regs_combine (XEXP (x, i));
10809         else if (fmt[i] == 'E')
10810           {
10811             register int j;
10812
10813             for (j = 0; j < XVECLEN (x, i); j++)
10814               mark_used_regs_combine (XVECEXP (x, i, j));
10815           }
10816       }
10817   }
10818 }
10819
10820 \f
10821 /* Remove register number REGNO from the dead registers list of INSN.
10822
10823    Return the note used to record the death, if there was one.  */
10824
10825 rtx
10826 remove_death (regno, insn)
10827      int regno;
10828      rtx insn;
10829 {
10830   register rtx note = find_regno_note (insn, REG_DEAD, regno);
10831
10832   if (note)
10833     {
10834       REG_N_DEATHS (regno)--;
10835       remove_note (insn, note);
10836     }
10837
10838   return note;
10839 }
10840
10841 /* For each register (hardware or pseudo) used within expression X, if its
10842    death is in an instruction with cuid between FROM_CUID (inclusive) and
10843    TO_INSN (exclusive), put a REG_DEAD note for that register in the
10844    list headed by PNOTES.
10845
10846    That said, don't move registers killed by maybe_kill_insn.
10847
10848    This is done when X is being merged by combination into TO_INSN.  These
10849    notes will then be distributed as needed.  */
10850
10851 static void
10852 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10853      rtx x;
10854      rtx maybe_kill_insn;
10855      int from_cuid;
10856      rtx to_insn;
10857      rtx *pnotes;
10858 {
10859   register char *fmt;
10860   register int len, i;
10861   register enum rtx_code code = GET_CODE (x);
10862
10863   if (code == REG)
10864     {
10865       register int regno = REGNO (x);
10866       register rtx where_dead = reg_last_death[regno];
10867       register rtx before_dead, after_dead;
10868
10869       /* Don't move the register if it gets killed in between from and to */
10870       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10871           && !reg_referenced_p (x, maybe_kill_insn))
10872         return;
10873
10874       /* WHERE_DEAD could be a USE insn made by combine, so first we
10875          make sure that we have insns with valid INSN_CUID values.  */
10876       before_dead = where_dead;
10877       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10878         before_dead = PREV_INSN (before_dead);
10879       after_dead = where_dead;
10880       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10881         after_dead = NEXT_INSN (after_dead);
10882
10883       if (before_dead && after_dead
10884           && INSN_CUID (before_dead) >= from_cuid
10885           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10886               || (where_dead != after_dead
10887                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10888         {
10889           rtx note = remove_death (regno, where_dead);
10890
10891           /* It is possible for the call above to return 0.  This can occur
10892              when reg_last_death points to I2 or I1 that we combined with.
10893              In that case make a new note.
10894
10895              We must also check for the case where X is a hard register
10896              and NOTE is a death note for a range of hard registers
10897              including X.  In that case, we must put REG_DEAD notes for
10898              the remaining registers in place of NOTE.  */
10899
10900           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10901               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10902                   > GET_MODE_SIZE (GET_MODE (x))))
10903             {
10904               int deadregno = REGNO (XEXP (note, 0));
10905               int deadend
10906                 = (deadregno + HARD_REGNO_NREGS (deadregno,
10907                                                  GET_MODE (XEXP (note, 0))));
10908               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10909               int i;
10910
10911               for (i = deadregno; i < deadend; i++)
10912                 if (i < regno || i >= ourend)
10913                   REG_NOTES (where_dead)
10914                     = gen_rtx (EXPR_LIST, REG_DEAD,
10915                                gen_rtx (REG, reg_raw_mode[i], i),
10916                                REG_NOTES (where_dead));
10917             }
10918           /* If we didn't find any note, or if we found a REG_DEAD note that
10919              covers only part of the given reg, and we have a multi-reg hard
10920              register, then to be safe we must check for REG_DEAD notes
10921              for each register other than the first.  They could have
10922              their own REG_DEAD notes lying around.  */
10923           else if ((note == 0
10924                     || (note != 0
10925                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10926                             < GET_MODE_SIZE (GET_MODE (x)))))
10927                    && regno < FIRST_PSEUDO_REGISTER
10928                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10929             {
10930               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10931               int i, offset;
10932               rtx oldnotes = 0;
10933
10934               if (note)
10935                 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10936               else
10937                 offset = 1;
10938
10939               for (i = regno + offset; i < ourend; i++)
10940                 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10941                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10942             }
10943
10944           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10945             {
10946               XEXP (note, 1) = *pnotes;
10947               *pnotes = note;
10948             }
10949           else
10950             *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10951
10952           REG_N_DEATHS (regno)++;
10953         }
10954
10955       return;
10956     }
10957
10958   else if (GET_CODE (x) == SET)
10959     {
10960       rtx dest = SET_DEST (x);
10961
10962       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10963
10964       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10965          that accesses one word of a multi-word item, some
10966          piece of everything register in the expression is used by
10967          this insn, so remove any old death.  */
10968
10969       if (GET_CODE (dest) == ZERO_EXTRACT
10970           || GET_CODE (dest) == STRICT_LOW_PART
10971           || (GET_CODE (dest) == SUBREG
10972               && (((GET_MODE_SIZE (GET_MODE (dest))
10973                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10974                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10975                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10976         {
10977           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10978           return;
10979         }
10980
10981       /* If this is some other SUBREG, we know it replaces the entire
10982          value, so use that as the destination.  */
10983       if (GET_CODE (dest) == SUBREG)
10984         dest = SUBREG_REG (dest);
10985
10986       /* If this is a MEM, adjust deaths of anything used in the address.
10987          For a REG (the only other possibility), the entire value is
10988          being replaced so the old value is not used in this insn.  */
10989
10990       if (GET_CODE (dest) == MEM)
10991         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10992                      to_insn, pnotes);
10993       return;
10994     }
10995
10996   else if (GET_CODE (x) == CLOBBER)
10997     return;
10998
10999   len = GET_RTX_LENGTH (code);
11000   fmt = GET_RTX_FORMAT (code);
11001
11002   for (i = 0; i < len; i++)
11003     {
11004       if (fmt[i] == 'E')
11005         {
11006           register int j;
11007           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11008             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11009                          to_insn, pnotes);
11010         }
11011       else if (fmt[i] == 'e')
11012         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11013     }
11014 }
11015 \f
11016 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11017    pattern of an insn.  X must be a REG.  */
11018
11019 static int
11020 reg_bitfield_target_p (x, body)
11021      rtx x;
11022      rtx body;
11023 {
11024   int i;
11025
11026   if (GET_CODE (body) == SET)
11027     {
11028       rtx dest = SET_DEST (body);
11029       rtx target;
11030       int regno, tregno, endregno, endtregno;
11031
11032       if (GET_CODE (dest) == ZERO_EXTRACT)
11033         target = XEXP (dest, 0);
11034       else if (GET_CODE (dest) == STRICT_LOW_PART)
11035         target = SUBREG_REG (XEXP (dest, 0));
11036       else
11037         return 0;
11038
11039       if (GET_CODE (target) == SUBREG)
11040         target = SUBREG_REG (target);
11041
11042       if (GET_CODE (target) != REG)
11043         return 0;
11044
11045       tregno = REGNO (target), regno = REGNO (x);
11046       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11047         return target == x;
11048
11049       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11050       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11051
11052       return endregno > tregno && regno < endtregno;
11053     }
11054
11055   else if (GET_CODE (body) == PARALLEL)
11056     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11057       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11058         return 1;
11059
11060   return 0;
11061 }
11062 \f
11063 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11064    as appropriate.  I3 and I2 are the insns resulting from the combination
11065    insns including FROM (I2 may be zero).
11066
11067    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11068    not need REG_DEAD notes because they are being substituted for.  This
11069    saves searching in the most common cases.
11070
11071    Each note in the list is either ignored or placed on some insns, depending
11072    on the type of note.  */
11073
11074 static void
11075 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11076      rtx notes;
11077      rtx from_insn;
11078      rtx i3, i2;
11079      rtx elim_i2, elim_i1;
11080 {
11081   rtx note, next_note;
11082   rtx tem;
11083
11084   for (note = notes; note; note = next_note)
11085     {
11086       rtx place = 0, place2 = 0;
11087
11088       /* If this NOTE references a pseudo register, ensure it references
11089          the latest copy of that register.  */
11090       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11091           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11092         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11093
11094       next_note = XEXP (note, 1);
11095       switch (REG_NOTE_KIND (note))
11096         {
11097         case REG_BR_PROB:
11098         case REG_EXEC_COUNT:
11099           /* Doesn't matter much where we put this, as long as it's somewhere.
11100              It is preferable to keep these notes on branches, which is most
11101              likely to be i3.  */
11102           place = i3;
11103           break;
11104
11105         case REG_UNUSED:
11106           /* Any clobbers for i3 may still exist, and so we must process
11107              REG_UNUSED notes from that insn.
11108
11109              Any clobbers from i2 or i1 can only exist if they were added by
11110              recog_for_combine.  In that case, recog_for_combine created the
11111              necessary REG_UNUSED notes.  Trying to keep any original
11112              REG_UNUSED notes from these insns can cause incorrect output
11113              if it is for the same register as the original i3 dest.
11114              In that case, we will notice that the register is set in i3,
11115              and then add a REG_UNUSED note for the destination of i3, which
11116              is wrong.  However, it is possible to have REG_UNUSED notes from
11117              i2 or i1 for register which were both used and clobbered, so
11118              we keep notes from i2 or i1 if they will turn into REG_DEAD
11119              notes.  */
11120
11121           /* If this register is set or clobbered in I3, put the note there
11122              unless there is one already.  */
11123           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11124             {
11125               if (from_insn != i3)
11126                 break;
11127
11128               if (! (GET_CODE (XEXP (note, 0)) == REG
11129                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11130                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11131                 place = i3;
11132             }
11133           /* Otherwise, if this register is used by I3, then this register
11134              now dies here, so we must put a REG_DEAD note here unless there
11135              is one already.  */
11136           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11137                    && ! (GET_CODE (XEXP (note, 0)) == REG
11138                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11139                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11140             {
11141               PUT_REG_NOTE_KIND (note, REG_DEAD);
11142               place = i3;
11143             }
11144           break;
11145
11146         case REG_EQUAL:
11147         case REG_EQUIV:
11148         case REG_NONNEG:
11149         case REG_NOALIAS:
11150           /* These notes say something about results of an insn.  We can
11151              only support them if they used to be on I3 in which case they
11152              remain on I3.  Otherwise they are ignored.
11153
11154              If the note refers to an expression that is not a constant, we
11155              must also ignore the note since we cannot tell whether the
11156              equivalence is still true.  It might be possible to do
11157              slightly better than this (we only have a problem if I2DEST
11158              or I1DEST is present in the expression), but it doesn't
11159              seem worth the trouble.  */
11160
11161           if (from_insn == i3
11162               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11163             place = i3;
11164           break;
11165
11166         case REG_INC:
11167         case REG_NO_CONFLICT:
11168         case REG_LABEL:
11169           /* These notes say something about how a register is used.  They must
11170              be present on any use of the register in I2 or I3.  */
11171           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11172             place = i3;
11173
11174           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11175             {
11176               if (place)
11177                 place2 = i2;
11178               else
11179                 place = i2;
11180             }
11181           break;
11182
11183         case REG_WAS_0:
11184           /* It is too much trouble to try to see if this note is still
11185              correct in all situations.  It is better to simply delete it.  */
11186           break;
11187
11188         case REG_RETVAL:
11189           /* If the insn previously containing this note still exists,
11190              put it back where it was.  Otherwise move it to the previous
11191              insn.  Adjust the corresponding REG_LIBCALL note.  */
11192           if (GET_CODE (from_insn) != NOTE)
11193             place = from_insn;
11194           else
11195             {
11196               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11197               place = prev_real_insn (from_insn);
11198               if (tem && place)
11199                 XEXP (tem, 0) = place;
11200             }
11201           break;
11202
11203         case REG_LIBCALL:
11204           /* This is handled similarly to REG_RETVAL.  */
11205           if (GET_CODE (from_insn) != NOTE)
11206             place = from_insn;
11207           else
11208             {
11209               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11210               place = next_real_insn (from_insn);
11211               if (tem && place)
11212                 XEXP (tem, 0) = place;
11213             }
11214           break;
11215
11216         case REG_DEAD:
11217           /* If the register is used as an input in I3, it dies there.
11218              Similarly for I2, if it is non-zero and adjacent to I3.
11219
11220              If the register is not used as an input in either I3 or I2
11221              and it is not one of the registers we were supposed to eliminate,
11222              there are two possibilities.  We might have a non-adjacent I2
11223              or we might have somehow eliminated an additional register
11224              from a computation.  For example, we might have had A & B where
11225              we discover that B will always be zero.  In this case we will
11226              eliminate the reference to A.
11227
11228              In both cases, we must search to see if we can find a previous
11229              use of A and put the death note there.  */
11230
11231           if (from_insn
11232               && GET_CODE (from_insn) == CALL_INSN
11233               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11234             place = from_insn;
11235           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11236             place = i3;
11237           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11238                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11239             place = i2;
11240
11241           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11242             break;
11243
11244           /* If the register is used in both I2 and I3 and it dies in I3,
11245              we might have added another reference to it.  If reg_n_refs
11246              was 2, bump it to 3.  This has to be correct since the
11247              register must have been set somewhere.  The reason this is
11248              done is because local-alloc.c treats 2 references as a
11249              special case.  */
11250
11251           if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11252               && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11253               && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11254             REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11255
11256           if (place == 0)
11257             {
11258               for (tem = prev_nonnote_insn (i3);
11259                    place == 0 && tem
11260                    && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11261                    tem = prev_nonnote_insn (tem))
11262                 {
11263                   /* If the register is being set at TEM, see if that is all
11264                      TEM is doing.  If so, delete TEM.  Otherwise, make this
11265                      into a REG_UNUSED note instead.  */
11266                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11267                     {
11268                       rtx set = single_set (tem);
11269
11270                       /* Verify that it was the set, and not a clobber that
11271                          modified the register.  */
11272
11273                       if (set != 0 && ! side_effects_p (SET_SRC (set))
11274                           && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11275                               || (GET_CODE (SET_DEST (set)) == SUBREG
11276                                   && rtx_equal_p (XEXP (note, 0),
11277                                                   XEXP (SET_DEST (set), 0)))))
11278                         {
11279                           /* Move the notes and links of TEM elsewhere.
11280                              This might delete other dead insns recursively.
11281                              First set the pattern to something that won't use
11282                              any register.  */
11283
11284                           PATTERN (tem) = pc_rtx;
11285
11286                           distribute_notes (REG_NOTES (tem), tem, tem,
11287                                             NULL_RTX, NULL_RTX, NULL_RTX);
11288                           distribute_links (LOG_LINKS (tem));
11289
11290                           PUT_CODE (tem, NOTE);
11291                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11292                           NOTE_SOURCE_FILE (tem) = 0;
11293                         }
11294                       else
11295                         {
11296                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
11297
11298                           /*  If there isn't already a REG_UNUSED note, put one
11299                               here.  */
11300                           if (! find_regno_note (tem, REG_UNUSED,
11301                                                  REGNO (XEXP (note, 0))))
11302                             place = tem;
11303                           break;
11304                       }
11305                   }
11306                 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11307                          || (GET_CODE (tem) == CALL_INSN
11308                              && find_reg_fusage (tem, USE, XEXP (note, 0))))
11309                   {
11310                     place = tem;
11311
11312                     /* If we are doing a 3->2 combination, and we have a
11313                        register which formerly died in i3 and was not used
11314                        by i2, which now no longer dies in i3 and is used in
11315                        i2 but does not die in i2, and place is between i2
11316                        and i3, then we may need to move a link from place to
11317                        i2.  */
11318                     if (i2 && INSN_UID (place) <= max_uid_cuid
11319                         && INSN_CUID (place) > INSN_CUID (i2)
11320                         && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11321                         && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11322                       {
11323                         rtx links = LOG_LINKS (place);
11324                         LOG_LINKS (place) = 0;
11325                         distribute_links (links);
11326                       }
11327                     break;
11328                   }
11329                 }
11330
11331               /* If we haven't found an insn for the death note and it
11332                  is still a REG_DEAD note, but we have hit a CODE_LABEL,
11333                  insert a USE insn for the register at that label and
11334                  put the death node there.  This prevents problems with
11335                  call-state tracking in caller-save.c.  */
11336               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11337                 {
11338                   place
11339                     = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11340                                        tem);
11341
11342                   /* If this insn was emitted between blocks, then update
11343                      basic_block_head of the current block to include it.  */
11344                   if (basic_block_end[this_basic_block - 1] == tem)
11345                     basic_block_head[this_basic_block] = place;
11346                 }
11347             }
11348
11349           /* If the register is set or already dead at PLACE, we needn't do
11350              anything with this note if it is still a REG_DEAD note.
11351
11352              Note that we cannot use just `dead_or_set_p' here since we can
11353              convert an assignment to a register into a bit-field assignment.
11354              Therefore, we must also omit the note if the register is the
11355              target of a bitfield assignment.  */
11356
11357           if (place && REG_NOTE_KIND (note) == REG_DEAD)
11358             {
11359               int regno = REGNO (XEXP (note, 0));
11360
11361               if (dead_or_set_p (place, XEXP (note, 0))
11362                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11363                 {
11364                   /* Unless the register previously died in PLACE, clear
11365                      reg_last_death.  [I no longer understand why this is
11366                      being done.] */
11367                   if (reg_last_death[regno] != place)
11368                     reg_last_death[regno] = 0;
11369                   place = 0;
11370                 }
11371               else
11372                 reg_last_death[regno] = place;
11373
11374               /* If this is a death note for a hard reg that is occupying
11375                  multiple registers, ensure that we are still using all
11376                  parts of the object.  If we find a piece of the object
11377                  that is unused, we must add a USE for that piece before
11378                  PLACE and put the appropriate REG_DEAD note on it.
11379
11380                  An alternative would be to put a REG_UNUSED for the pieces
11381                  on the insn that set the register, but that can't be done if
11382                  it is not in the same block.  It is simpler, though less
11383                  efficient, to add the USE insns.  */
11384
11385               if (place && regno < FIRST_PSEUDO_REGISTER
11386                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11387                 {
11388                   int endregno
11389                     = regno + HARD_REGNO_NREGS (regno,
11390                                                 GET_MODE (XEXP (note, 0)));
11391                   int all_used = 1;
11392                   int i;
11393
11394                   for (i = regno; i < endregno; i++)
11395                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11396                         && ! find_regno_fusage (place, USE, i))
11397                       {
11398                         rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11399                         rtx p;
11400
11401                         /* See if we already placed a USE note for this
11402                            register in front of PLACE.  */
11403                         for (p = place;
11404                              GET_CODE (PREV_INSN (p)) == INSN
11405                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11406                              p = PREV_INSN (p))
11407                           if (rtx_equal_p (piece,
11408                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
11409                             {
11410                               p = 0;
11411                               break;
11412                             }
11413
11414                         if (p)
11415                           {
11416                             rtx use_insn
11417                               = emit_insn_before (gen_rtx (USE, VOIDmode,
11418                                                            piece),
11419                                                   p);
11420                             REG_NOTES (use_insn)
11421                               = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11422                                          REG_NOTES (use_insn));
11423                           }
11424
11425                         all_used = 0;
11426                       }
11427
11428                   /* Check for the case where the register dying partially
11429                      overlaps the register set by this insn.  */
11430                   if (all_used)
11431                     for (i = regno; i < endregno; i++)
11432                       if (dead_or_set_regno_p (place, i))
11433                           {
11434                             all_used = 0;
11435                             break;
11436                           }
11437
11438                   if (! all_used)
11439                     {
11440                       /* Put only REG_DEAD notes for pieces that are
11441                          still used and that are not already dead or set.  */
11442
11443                       for (i = regno; i < endregno; i++)
11444                         {
11445                           rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11446
11447                           if ((reg_referenced_p (piece, PATTERN (place))
11448                                || (GET_CODE (place) == CALL_INSN
11449                                    && find_reg_fusage (place, USE, piece)))
11450                               && ! dead_or_set_p (place, piece)
11451                               && ! reg_bitfield_target_p (piece,
11452                                                           PATTERN (place)))
11453                             REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11454                                                          piece,
11455                                                          REG_NOTES (place));
11456                         }
11457
11458                       place = 0;
11459                     }
11460                 }
11461             }
11462           break;
11463
11464         default:
11465           /* Any other notes should not be present at this point in the
11466              compilation.  */
11467           abort ();
11468         }
11469
11470       if (place)
11471         {
11472           XEXP (note, 1) = REG_NOTES (place);
11473           REG_NOTES (place) = note;
11474         }
11475       else if ((REG_NOTE_KIND (note) == REG_DEAD
11476                 || REG_NOTE_KIND (note) == REG_UNUSED)
11477                && GET_CODE (XEXP (note, 0)) == REG)
11478         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11479
11480       if (place2)
11481         {
11482           if ((REG_NOTE_KIND (note) == REG_DEAD
11483                || REG_NOTE_KIND (note) == REG_UNUSED)
11484               && GET_CODE (XEXP (note, 0)) == REG)
11485             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11486
11487           REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11488                                         XEXP (note, 0), REG_NOTES (place2));
11489         }
11490     }
11491 }
11492 \f
11493 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11494    I3, I2, and I1 to new locations.  This is also called in one case to
11495    add a link pointing at I3 when I3's destination is changed.  */
11496
11497 static void
11498 distribute_links (links)
11499      rtx links;
11500 {
11501   rtx link, next_link;
11502
11503   for (link = links; link; link = next_link)
11504     {
11505       rtx place = 0;
11506       rtx insn;
11507       rtx set, reg;
11508
11509       next_link = XEXP (link, 1);
11510
11511       /* If the insn that this link points to is a NOTE or isn't a single
11512          set, ignore it.  In the latter case, it isn't clear what we
11513          can do other than ignore the link, since we can't tell which
11514          register it was for.  Such links wouldn't be used by combine
11515          anyway.
11516
11517          It is not possible for the destination of the target of the link to
11518          have been changed by combine.  The only potential of this is if we
11519          replace I3, I2, and I1 by I3 and I2.  But in that case the
11520          destination of I2 also remains unchanged.  */
11521
11522       if (GET_CODE (XEXP (link, 0)) == NOTE
11523           || (set = single_set (XEXP (link, 0))) == 0)
11524         continue;
11525
11526       reg = SET_DEST (set);
11527       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11528              || GET_CODE (reg) == SIGN_EXTRACT
11529              || GET_CODE (reg) == STRICT_LOW_PART)
11530         reg = XEXP (reg, 0);
11531
11532       /* A LOG_LINK is defined as being placed on the first insn that uses
11533          a register and points to the insn that sets the register.  Start
11534          searching at the next insn after the target of the link and stop
11535          when we reach a set of the register or the end of the basic block.
11536
11537          Note that this correctly handles the link that used to point from
11538          I3 to I2.  Also note that not much searching is typically done here
11539          since most links don't point very far away.  */
11540
11541       for (insn = NEXT_INSN (XEXP (link, 0));
11542            (insn && (this_basic_block == n_basic_blocks - 1
11543                      || basic_block_head[this_basic_block + 1] != insn));
11544            insn = NEXT_INSN (insn))
11545         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11546             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11547           {
11548             if (reg_referenced_p (reg, PATTERN (insn)))
11549               place = insn;
11550             break;
11551           }
11552         else if (GET_CODE (insn) == CALL_INSN
11553               && find_reg_fusage (insn, USE, reg))
11554           {
11555             place = insn;
11556             break;
11557           }
11558
11559       /* If we found a place to put the link, place it there unless there
11560          is already a link to the same insn as LINK at that point.  */
11561
11562       if (place)
11563         {
11564           rtx link2;
11565
11566           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11567             if (XEXP (link2, 0) == XEXP (link, 0))
11568               break;
11569
11570           if (link2 == 0)
11571             {
11572               XEXP (link, 1) = LOG_LINKS (place);
11573               LOG_LINKS (place) = link;
11574
11575               /* Set added_links_insn to the earliest insn we added a
11576                  link to.  */
11577               if (added_links_insn == 0
11578                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
11579                 added_links_insn = place;
11580             }
11581         }
11582     }
11583 }
11584 \f
11585 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
11586
11587 static int
11588 insn_cuid (insn)
11589      rtx insn;
11590 {
11591   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11592          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11593     insn = NEXT_INSN (insn);
11594
11595   if (INSN_UID (insn) > max_uid_cuid)
11596     abort ();
11597
11598   return INSN_CUID (insn);
11599 }
11600 \f
11601 void
11602 dump_combine_stats (file)
11603      FILE *file;
11604 {
11605   fprintf
11606     (file,
11607      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11608      combine_attempts, combine_merges, combine_extras, combine_successes);
11609 }
11610
11611 void
11612 dump_combine_total_stats (file)
11613      FILE *file;
11614 {
11615   fprintf
11616     (file,
11617      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11618      total_attempts, total_merges, total_extras, total_successes);
11619 }