gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2014 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "stor-layout.h"
  85 #include "tm_p.h"
  86 #include "flags.h"
  87 #include "regs.h"
  88 #include "hard-reg-set.h"
  89 #include "basic-block.h"
  90 #include "insn-config.h"
  91 #include "function.h"
  92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  93 #include "expr.h"
  94 #include "insn-attr.h"
  95 #include "recog.h"
  96 #include "diagnostic-core.h"
  97 #include "target.h"
  98 #include "optabs.h"
  99 #include "insn-codes.h"
 100 #include "rtlhooks-def.h"
 101 #include "params.h"
 102 #include "tree-pass.h"
 103 #include "df.h"
 104 #include "valtrack.h"
 105 #include "cgraph.h"
 106 #include "obstack.h"
 107 #include "statistics.h"
 108 #include "params.h"
 109
 110 /* Number of attempts to combine instructions in this function.  */
 111
 112 static int combine_attempts;
 113
 114 /* Number of attempts that got as far as substitution in this function.  */
 115
 116 static int combine_merges;
 117
 118 /* Number of instructions combined with added SETs in this function.  */
 119
 120 static int combine_extras;
 121
 122 /* Number of instructions combined in this function.  */
 123
 124 static int combine_successes;
 125
 126 /* Totals over entire compilation.  */
 127
 128 static int total_attempts, total_merges, total_extras, total_successes;
 129
 130 /* combine_instructions may try to replace the right hand side of the
 131    second instruction with the value of an associated REG_EQUAL note
 132    before throwing it at try_combine.  That is problematic when there
 133    is a REG_DEAD note for a register used in the old right hand side
 134    and can cause distribute_notes to do wrong things.  This is the
 135    second instruction if it has been so modified, null otherwise.  */
 136
 137 static rtx i2mod;
 138
 139 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 140
 141 static rtx i2mod_old_rhs;
 142
 143 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 144
 145 static rtx i2mod_new_rhs;
 146 \f
 147 typedef struct reg_stat_struct {
 148   /* Record last point of death of (hard or pseudo) register n.  */
 149   rtx                           last_death;
 150
 151   /* Record last point of modification of (hard or pseudo) register n.  */
 152   rtx                           last_set;
 153
 154   /* The next group of fields allows the recording of the last value assigned
 155      to (hard or pseudo) register n.  We use this information to see if an
 156      operation being processed is redundant given a prior operation performed
 157      on the register.  For example, an `and' with a constant is redundant if
 158      all the zero bits are already known to be turned off.
 159
 160      We use an approach similar to that used by cse, but change it in the
 161      following ways:
 162
 163      (1) We do not want to reinitialize at each label.
 164      (2) It is useful, but not critical, to know the actual value assigned
 165          to a register.  Often just its form is helpful.
 166
 167      Therefore, we maintain the following fields:
 168
 169      last_set_value             the last value assigned
 170      last_set_label             records the value of label_tick when the
 171                                 register was assigned
 172      last_set_table_tick        records the value of label_tick when a
 173                                 value using the register is assigned
 174      last_set_invalid           set to nonzero when it is not valid
 175                                 to use the value of this register in some
 176                                 register's value
 177
 178      To understand the usage of these tables, it is important to understand
 179      the distinction between the value in last_set_value being valid and
 180      the register being validly contained in some other expression in the
 181      table.
 182
 183      (The next two parameters are out of date).
 184
 185      reg_stat[i].last_set_value is valid if it is nonzero, and either
 186      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 187
 188      Register I may validly appear in any expression returned for the value
 189      of another register if reg_n_sets[i] is 1.  It may also appear in the
 190      value for register J if reg_stat[j].last_set_invalid is zero, or
 191      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 192
 193      If an expression is found in the table containing a register which may
 194      not validly appear in an expression, the register is replaced by
 195      something that won't match, (clobber (const_int 0)).  */
 196
 197   /* Record last value assigned to (hard or pseudo) register n.  */
 198
 199   rtx                           last_set_value;
 200
 201   /* Record the value of label_tick when an expression involving register n
 202      is placed in last_set_value.  */
 203
 204   int                           last_set_table_tick;
 205
 206   /* Record the value of label_tick when the value for register n is placed in
 207      last_set_value.  */
 208
 209   int                           last_set_label;
 210
 211   /* These fields are maintained in parallel with last_set_value and are
 212      used to store the mode in which the register was last set, the bits
 213      that were known to be zero when it was last set, and the number of
 214      sign bits copies it was known to have when it was last set.  */
 215
 216   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 217   char                          last_set_sign_bit_copies;
 218   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 219
 220   /* Set nonzero if references to register n in expressions should not be
 221      used.  last_set_invalid is set nonzero when this register is being
 222      assigned to and last_set_table_tick == label_tick.  */
 223
 224   char                          last_set_invalid;
 225
 226   /* Some registers that are set more than once and used in more than one
 227      basic block are nevertheless always set in similar ways.  For example,
 228      a QImode register may be loaded from memory in two places on a machine
 229      where byte loads zero extend.
 230
 231      We record in the following fields if a register has some leading bits
 232      that are always equal to the sign bit, and what we know about the
 233      nonzero bits of a register, specifically which bits are known to be
 234      zero.
 235
 236      If an entry is zero, it means that we don't know anything special.  */
 237
 238   unsigned char                 sign_bit_copies;
 239
 240   unsigned HOST_WIDE_INT        nonzero_bits;
 241
 242   /* Record the value of the label_tick when the last truncation
 243      happened.  The field truncated_to_mode is only valid if
 244      truncation_label == label_tick.  */
 245
 246   int                           truncation_label;
 247
 248   /* Record the last truncation seen for this register.  If truncation
 249      is not a nop to this mode we might be able to save an explicit
 250      truncation if we know that value already contains a truncated
 251      value.  */
 252
 253   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 254 } reg_stat_type;
 255
 256
 257 static vec<reg_stat_type> reg_stat;
 258
 259 /* Record the luid of the last insn that invalidated memory
 260    (anything that writes memory, and subroutine calls, but not pushes).  */
 261
 262 static int mem_last_set;
 263
 264 /* Record the luid of the last CALL_INSN
 265    so we can tell whether a potential combination crosses any calls.  */
 266
 267 static int last_call_luid;
 268
 269 /* When `subst' is called, this is the insn that is being modified
 270    (by combining in a previous insn).  The PATTERN of this insn
 271    is still the old pattern partially modified and it should not be
 272    looked at, but this may be used to examine the successors of the insn
 273    to judge whether a simplification is valid.  */
 274
 275 static rtx subst_insn;
 276
 277 /* This is the lowest LUID that `subst' is currently dealing with.
 278    get_last_value will not return a value if the register was set at or
 279    after this LUID.  If not for this mechanism, we could get confused if
 280    I2 or I1 in try_combine were an insn that used the old value of a register
 281    to obtain a new value.  In that case, we might erroneously get the
 282    new value of the register when we wanted the old one.  */
 283
 284 static int subst_low_luid;
 285
 286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 287    must consider all these registers to be always live.  */
 288
 289 static HARD_REG_SET newpat_used_regs;
 290
 291 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 292    insn is the earlier than I2 or I3, combine should rescan starting at
 293    that location.  */
 294
 295 static rtx added_links_insn;
 296
 297 /* Basic block in which we are performing combines.  */
 298 static basic_block this_basic_block;
 299 static bool optimize_this_for_speed_p;
 300
 301 \f
 302 /* Length of the currently allocated uid_insn_cost array.  */
 303
 304 static int max_uid_known;
 305
 306 /* The following array records the insn_rtx_cost for every insn
 307    in the instruction stream.  */
 308
 309 static int *uid_insn_cost;
 310
 311 /* The following array records the LOG_LINKS for every insn in the
 312    instruction stream as struct insn_link pointers.  */
 313
 314 struct insn_link {
 315   rtx insn;
 316   struct insn_link *next;
 317 };
 318
 319 static struct insn_link **uid_log_links;
 320
 321 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 322 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 323
 324 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 325   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 326
 327 /* Links for LOG_LINKS are allocated from this obstack.  */
 328
 329 static struct obstack insn_link_obstack;
 330
 331 /* Allocate a link.  */
 332
 333 static inline struct insn_link *
 334 alloc_insn_link (rtx insn, struct insn_link *next)
 335 {
 336   struct insn_link *l
 337     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 338                                           sizeof (struct insn_link));
 339   l->insn = insn;
 340   l->next = next;
 341   return l;
 342 }
 343
 344 /* Incremented for each basic block.  */
 345
 346 static int label_tick;
 347
 348 /* Reset to label_tick for each extended basic block in scanning order.  */
 349
 350 static int label_tick_ebb_start;
 351
 352 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 353    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 354
 355 static enum machine_mode nonzero_bits_mode;
 356
 357 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 358    be safely used.  It is zero while computing them and after combine has
 359    completed.  This former test prevents propagating values based on
 360    previously set values, which can be incorrect if a variable is modified
 361    in a loop.  */
 362
 363 static int nonzero_sign_valid;
 364
 365 \f
 366 /* Record one modification to rtl structure
 367    to be undone by storing old_contents into *where.  */
 368
 369 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 370
 371 struct undo
 372 {
 373   struct undo *next;
 374   enum undo_kind kind;
 375   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 376   union { rtx *r; int *i; struct insn_link **l; } where;
 377 };
 378
 379 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 380    num_undo says how many are currently recorded.
 381
 382    other_insn is nonzero if we have modified some other insn in the process
 383    of working on subst_insn.  It must be verified too.  */
 384
 385 struct undobuf
 386 {
 387   struct undo *undos;
 388   struct undo *frees;
 389   rtx other_insn;
 390 };
 391
 392 static struct undobuf undobuf;
 393
 394 /* Number of times the pseudo being substituted for
 395    was found and replaced.  */
 396
 397 static int n_occurrences;
 398
 399 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 400                                          enum machine_mode,
 401                                          unsigned HOST_WIDE_INT,
 402                                          unsigned HOST_WIDE_INT *);
 403 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 404                                                 enum machine_mode,
 405                                                 unsigned int, unsigned int *);
 406 static void do_SUBST (rtx *, rtx);
 407 static void do_SUBST_INT (int *, int);
 408 static void init_reg_last (void);
 409 static void setup_incoming_promotions (rtx);
 410 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 411 static int cant_combine_insn_p (rtx);
 412 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 413 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 414 static int contains_muldiv (rtx);
 415 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 416 static void undo_all (void);
 417 static void undo_commit (void);
 418 static rtx *find_split_point (rtx *, rtx, bool);
 419 static rtx subst (rtx, rtx, rtx, int, int, int);
 420 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 421 static rtx simplify_if_then_else (rtx);
 422 static rtx simplify_set (rtx);
 423 static rtx simplify_logical (rtx);
 424 static rtx expand_compound_operation (rtx);
 425 static const_rtx expand_field_assignment (const_rtx);
 426 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 427                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 428 static rtx extract_left_shift (rtx, int);
 429 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 430                               unsigned HOST_WIDE_INT *);
 431 static rtx canon_reg_for_combine (rtx, rtx);
 432 static rtx force_to_mode (rtx, enum machine_mode,
 433                           unsigned HOST_WIDE_INT, int);
 434 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 435 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 436 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 437 static rtx make_field_assignment (rtx);
 438 static rtx apply_distributive_law (rtx);
 439 static rtx distribute_and_simplify_rtx (rtx, int);
 440 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 441                                      unsigned HOST_WIDE_INT);
 442 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 443                                    unsigned HOST_WIDE_INT);
 444 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 445                             HOST_WIDE_INT, enum machine_mode, int *);
 446 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 447 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 448                                  int);
 449 static int recog_for_combine (rtx *, rtx, rtx *);
 450 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 451 static enum rtx_code simplify_compare_const (enum rtx_code, enum machine_mode,
 452                                              rtx, rtx *);
 453 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 454 static void update_table_tick (rtx);
 455 static void record_value_for_reg (rtx, rtx, rtx);
 456 static void check_promoted_subreg (rtx, rtx);
 457 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 458 static void record_dead_and_set_regs (rtx);
 459 static int get_last_value_validate (rtx *, rtx, int, int);
 460 static rtx get_last_value (const_rtx);
 461 static int use_crosses_set_p (const_rtx, int);
 462 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 463 static int reg_dead_at_p (rtx, rtx);
 464 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 465 static int reg_bitfield_target_p (rtx, rtx);
 466 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 467 static void distribute_links (struct insn_link *);
 468 static void mark_used_regs_combine (rtx);
 469 static void record_promoted_value (rtx, rtx);
 470 static int unmentioned_reg_p_1 (rtx *, void *);
 471 static bool unmentioned_reg_p (rtx, rtx);
 472 static int record_truncated_value (rtx *, void *);
 473 static void record_truncated_values (rtx *, void *);
 474 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 475 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 476 \f
 477
 478 /* It is not safe to use ordinary gen_lowpart in combine.
 479    See comments in gen_lowpart_for_combine.  */
 480 #undef RTL_HOOKS_GEN_LOWPART
 481 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 482
 483 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 484 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 485 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 486
 487 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 488 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 489
 490 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 491 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 492
 493 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 494 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 495
 496 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 497
 498 \f
 499 /* Convenience wrapper for the canonicalize_comparison target hook.
 500    Target hooks cannot use enum rtx_code.  */
 501 static inline void
 502 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 503                                 bool op0_preserve_value)
 504 {
 505   int code_int = (int)*code;
 506   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 507   *code = (enum rtx_code)code_int;
 508 }
 509
 510 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 511    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 512    This is a wrapper around split_insns which ensures that the
 513    reg_stat vector is made larger if the splitter creates a new
 514    register.  */
 515
 516 static rtx
 517 combine_split_insns (rtx pattern, rtx insn)
 518 {
 519   rtx ret;
 520   unsigned int nregs;
 521
 522   ret = split_insns (pattern, insn);
 523   nregs = max_reg_num ();
 524   if (nregs > reg_stat.length ())
 525     reg_stat.safe_grow_cleared (nregs);
 526   return ret;
 527 }
 528
 529 /* This is used by find_single_use to locate an rtx in LOC that
 530    contains exactly one use of DEST, which is typically either a REG
 531    or CC0.  It returns a pointer to the innermost rtx expression
 532    containing DEST.  Appearances of DEST that are being used to
 533    totally replace it are not counted.  */
 534
 535 static rtx *
 536 find_single_use_1 (rtx dest, rtx *loc)
 537 {
 538   rtx x = *loc;
 539   enum rtx_code code = GET_CODE (x);
 540   rtx *result = NULL;
 541   rtx *this_result;
 542   int i;
 543   const char *fmt;
 544
 545   switch (code)
 546     {
 547     case CONST:
 548     case LABEL_REF:
 549     case SYMBOL_REF:
 550     CASE_CONST_ANY:
 551     case CLOBBER:
 552       return 0;
 553
 554     case SET:
 555       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 556          of a REG that occupies all of the REG, the insn uses DEST if
 557          it is mentioned in the destination or the source.  Otherwise, we
 558          need just check the source.  */
 559       if (GET_CODE (SET_DEST (x)) != CC0
 560           && GET_CODE (SET_DEST (x)) != PC
 561           && !REG_P (SET_DEST (x))
 562           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 563                 && REG_P (SUBREG_REG (SET_DEST (x)))
 564                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 565                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 566                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 567                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 568         break;
 569
 570       return find_single_use_1 (dest, &SET_SRC (x));
 571
 572     case MEM:
 573     case SUBREG:
 574       return find_single_use_1 (dest, &XEXP (x, 0));
 575
 576     default:
 577       break;
 578     }
 579
 580   /* If it wasn't one of the common cases above, check each expression and
 581      vector of this code.  Look for a unique usage of DEST.  */
 582
 583   fmt = GET_RTX_FORMAT (code);
 584   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 585     {
 586       if (fmt[i] == 'e')
 587         {
 588           if (dest == XEXP (x, i)
 589               || (REG_P (dest) && REG_P (XEXP (x, i))
 590                   && REGNO (dest) == REGNO (XEXP (x, i))))
 591             this_result = loc;
 592           else
 593             this_result = find_single_use_1 (dest, &XEXP (x, i));
 594
 595           if (result == NULL)
 596             result = this_result;
 597           else if (this_result)
 598             /* Duplicate usage.  */
 599             return NULL;
 600         }
 601       else if (fmt[i] == 'E')
 602         {
 603           int j;
 604
 605           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 606             {
 607               if (XVECEXP (x, i, j) == dest
 608                   || (REG_P (dest)
 609                       && REG_P (XVECEXP (x, i, j))
 610                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 611                 this_result = loc;
 612               else
 613                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 614
 615               if (result == NULL)
 616                 result = this_result;
 617               else if (this_result)
 618                 return NULL;
 619             }
 620         }
 621     }
 622
 623   return result;
 624 }
 625
 626
 627 /* See if DEST, produced in INSN, is used only a single time in the
 628    sequel.  If so, return a pointer to the innermost rtx expression in which
 629    it is used.
 630
 631    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 632
 633    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 634    care about REG_DEAD notes or LOG_LINKS.
 635
 636    Otherwise, we find the single use by finding an insn that has a
 637    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 638    only referenced once in that insn, we know that it must be the first
 639    and last insn referencing DEST.  */
 640
 641 static rtx *
 642 find_single_use (rtx dest, rtx insn, rtx *ploc)
 643 {
 644   basic_block bb;
 645   rtx next;
 646   rtx *result;
 647   struct insn_link *link;
 648
 649 #ifdef HAVE_cc0
 650   if (dest == cc0_rtx)
 651     {
 652       next = NEXT_INSN (insn);
 653       if (next == 0
 654           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 655         return 0;
 656
 657       result = find_single_use_1 (dest, &PATTERN (next));
 658       if (result && ploc)
 659         *ploc = next;
 660       return result;
 661     }
 662 #endif
 663
 664   if (!REG_P (dest))
 665     return 0;
 666
 667   bb = BLOCK_FOR_INSN (insn);
 668   for (next = NEXT_INSN (insn);
 669        next && BLOCK_FOR_INSN (next) == bb;
 670        next = NEXT_INSN (next))
 671     if (INSN_P (next) && dead_or_set_p (next, dest))
 672       {
 673         FOR_EACH_LOG_LINK (link, next)
 674           if (link->insn == insn)
 675             break;
 676
 677         if (link)
 678           {
 679             result = find_single_use_1 (dest, &PATTERN (next));
 680             if (ploc)
 681               *ploc = next;
 682             return result;
 683           }
 684       }
 685
 686   return 0;
 687 }
 688 \f
 689 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 690    insn.  The substitution can be undone by undo_all.  If INTO is already
 691    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 692    also call SUBST, we have to compute it before we put anything into
 693    the undo table.  */
 694
 695 static void
 696 do_SUBST (rtx *into, rtx newval)
 697 {
 698   struct undo *buf;
 699   rtx oldval = *into;
 700
 701   if (oldval == newval)
 702     return;
 703
 704   /* We'd like to catch as many invalid transformations here as
 705      possible.  Unfortunately, there are way too many mode changes
 706      that are perfectly valid, so we'd waste too much effort for
 707      little gain doing the checks here.  Focus on catching invalid
 708      transformations involving integer constants.  */
 709   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 710       && CONST_INT_P (newval))
 711     {
 712       /* Sanity check that we're replacing oldval with a CONST_INT
 713          that is a valid sign-extension for the original mode.  */
 714       gcc_assert (INTVAL (newval)
 715                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 716
 717       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 718          CONST_INT is not valid, because after the replacement, the
 719          original mode would be gone.  Unfortunately, we can't tell
 720          when do_SUBST is called to replace the operand thereof, so we
 721          perform this test on oldval instead, checking whether an
 722          invalid replacement took place before we got here.  */
 723       gcc_assert (!(GET_CODE (oldval) == SUBREG
 724                     && CONST_INT_P (SUBREG_REG (oldval))));
 725       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 726                     && CONST_INT_P (XEXP (oldval, 0))));
 727     }
 728
 729   if (undobuf.frees)
 730     buf = undobuf.frees, undobuf.frees = buf->next;
 731   else
 732     buf = XNEW (struct undo);
 733
 734   buf->kind = UNDO_RTX;
 735   buf->where.r = into;
 736   buf->old_contents.r = oldval;
 737   *into = newval;
 738
 739   buf->next = undobuf.undos, undobuf.undos = buf;
 740 }
 741
 742 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 743
 744 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 745    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 746    not safe.  */
 747
 748 static void
 749 do_SUBST_INT (int *into, int newval)
 750 {
 751   struct undo *buf;
 752   int oldval = *into;
 753
 754   if (oldval == newval)
 755     return;
 756
 757   if (undobuf.frees)
 758     buf = undobuf.frees, undobuf.frees = buf->next;
 759   else
 760     buf = XNEW (struct undo);
 761
 762   buf->kind = UNDO_INT;
 763   buf->where.i = into;
 764   buf->old_contents.i = oldval;
 765   *into = newval;
 766
 767   buf->next = undobuf.undos, undobuf.undos = buf;
 768 }
 769
 770 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 771
 772 /* Similar to SUBST, but just substitute the mode.  This is used when
 773    changing the mode of a pseudo-register, so that any other
 774    references to the entry in the regno_reg_rtx array will change as
 775    well.  */
 776
 777 static void
 778 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 779 {
 780   struct undo *buf;
 781   enum machine_mode oldval = GET_MODE (*into);
 782
 783   if (oldval == newval)
 784     return;
 785
 786   if (undobuf.frees)
 787     buf = undobuf.frees, undobuf.frees = buf->next;
 788   else
 789     buf = XNEW (struct undo);
 790
 791   buf->kind = UNDO_MODE;
 792   buf->where.r = into;
 793   buf->old_contents.m = oldval;
 794   adjust_reg_mode (*into, newval);
 795
 796   buf->next = undobuf.undos, undobuf.undos = buf;
 797 }
 798
 799 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 800
 801 #ifndef HAVE_cc0
 802 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 803
 804 static void
 805 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 806 {
 807   struct undo *buf;
 808   struct insn_link * oldval = *into;
 809
 810   if (oldval == newval)
 811     return;
 812
 813   if (undobuf.frees)
 814     buf = undobuf.frees, undobuf.frees = buf->next;
 815   else
 816     buf = XNEW (struct undo);
 817
 818   buf->kind = UNDO_LINKS;
 819   buf->where.l = into;
 820   buf->old_contents.l = oldval;
 821   *into = newval;
 822
 823   buf->next = undobuf.undos, undobuf.undos = buf;
 824 }
 825
 826 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 827 #endif
 828 \f
 829 /* Subroutine of try_combine.  Determine whether the replacement patterns
 830    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 831    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 832    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 833    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 834    of all the instructions can be estimated and the replacements are more
 835    expensive than the original sequence.  */
 836
 837 static bool
 838 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 839                        rtx newi2pat, rtx newotherpat)
 840 {
 841   int i0_cost, i1_cost, i2_cost, i3_cost;
 842   int new_i2_cost, new_i3_cost;
 843   int old_cost, new_cost;
 844
 845   /* Lookup the original insn_rtx_costs.  */
 846   i2_cost = INSN_COST (i2);
 847   i3_cost = INSN_COST (i3);
 848
 849   if (i1)
 850     {
 851       i1_cost = INSN_COST (i1);
 852       if (i0)
 853         {
 854           i0_cost = INSN_COST (i0);
 855           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 856                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 857         }
 858       else
 859         {
 860           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 861                       ? i1_cost + i2_cost + i3_cost : 0);
 862           i0_cost = 0;
 863         }
 864     }
 865   else
 866     {
 867       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 868       i1_cost = i0_cost = 0;
 869     }
 870
 871   /* Calculate the replacement insn_rtx_costs.  */
 872   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 873   if (newi2pat)
 874     {
 875       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 876       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 877                  ? new_i2_cost + new_i3_cost : 0;
 878     }
 879   else
 880     {
 881       new_cost = new_i3_cost;
 882       new_i2_cost = 0;
 883     }
 884
 885   if (undobuf.other_insn)
 886     {
 887       int old_other_cost, new_other_cost;
 888
 889       old_other_cost = INSN_COST (undobuf.other_insn);
 890       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 891       if (old_other_cost > 0 && new_other_cost > 0)
 892         {
 893           old_cost += old_other_cost;
 894           new_cost += new_other_cost;
 895         }
 896       else
 897         old_cost = 0;
 898     }
 899
 900   /* Disallow this combination if both new_cost and old_cost are greater than
 901      zero, and new_cost is greater than old cost.  */
 902   if (old_cost > 0 && new_cost > old_cost)
 903     {
 904       if (dump_file)
 905         {
 906           if (i0)
 907             {
 908               fprintf (dump_file,
 909                        "rejecting combination of insns %d, %d, %d and %d\n",
 910                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 911                        INSN_UID (i3));
 912               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 913                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 914             }
 915           else if (i1)
 916             {
 917               fprintf (dump_file,
 918                        "rejecting combination of insns %d, %d and %d\n",
 919                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 920               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 921                        i1_cost, i2_cost, i3_cost, old_cost);
 922             }
 923           else
 924             {
 925               fprintf (dump_file,
 926                        "rejecting combination of insns %d and %d\n",
 927                        INSN_UID (i2), INSN_UID (i3));
 928               fprintf (dump_file, "original costs %d + %d = %d\n",
 929                        i2_cost, i3_cost, old_cost);
 930             }
 931
 932           if (newi2pat)
 933             {
 934               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 935                        new_i2_cost, new_i3_cost, new_cost);
 936             }
 937           else
 938             fprintf (dump_file, "replacement cost %d\n", new_cost);
 939         }
 940
 941       return false;
 942     }
 943
 944   /* Update the uid_insn_cost array with the replacement costs.  */
 945   INSN_COST (i2) = new_i2_cost;
 946   INSN_COST (i3) = new_i3_cost;
 947   if (i1)
 948     {
 949       INSN_COST (i1) = 0;
 950       if (i0)
 951         INSN_COST (i0) = 0;
 952     }
 953
 954   return true;
 955 }
 956
 957
 958 /* Delete any insns that copy a register to itself.  */
 959
 960 static void
 961 delete_noop_moves (void)
 962 {
 963   rtx insn, next;
 964   basic_block bb;
 965
 966   FOR_EACH_BB_FN (bb, cfun)
 967     {
 968       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 969         {
 970           next = NEXT_INSN (insn);
 971           if (INSN_P (insn) && noop_move_p (insn))
 972             {
 973               if (dump_file)
 974                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 975
 976               delete_insn_and_edges (insn);
 977             }
 978         }
 979     }
 980 }
 981
 982 \f
 983 /* Fill in log links field for all insns.  */
 984
 985 static void
 986 create_log_links (void)
 987 {
 988   basic_block bb;
 989   rtx *next_use, insn;
 990   df_ref def, use;
 991
 992   next_use = XCNEWVEC (rtx, max_reg_num ());
 993
 994   /* Pass through each block from the end, recording the uses of each
 995      register and establishing log links when def is encountered.
 996      Note that we do not clear next_use array in order to save time,
 997      so we have to test whether the use is in the same basic block as def.
 998
 999      There are a few cases below when we do not consider the definition or
1000      usage -- these are taken from original flow.c did. Don't ask me why it is
1001      done this way; I don't know and if it works, I don't want to know.  */
1002
1003   FOR_EACH_BB_FN (bb, cfun)
1004     {
1005       FOR_BB_INSNS_REVERSE (bb, insn)
1006         {
1007           if (!NONDEBUG_INSN_P (insn))
1008             continue;
1009
1010           /* Log links are created only once.  */
1011           gcc_assert (!LOG_LINKS (insn));
1012
1013           FOR_EACH_INSN_DEF (def, insn)
1014             {
1015               int regno = DF_REF_REGNO (def);
1016               rtx use_insn;
1017
1018               if (!next_use[regno])
1019                 continue;
1020
1021               /* Do not consider if it is pre/post modification in MEM.  */
1022               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1023                 continue;
1024
1025               /* Do not make the log link for frame pointer.  */
1026               if ((regno == FRAME_POINTER_REGNUM
1027                    && (! reload_completed || frame_pointer_needed))
1028 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1029                   || (regno == HARD_FRAME_POINTER_REGNUM
1030                       && (! reload_completed || frame_pointer_needed))
1031 #endif
1032 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1033                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1034 #endif
1035                   )
1036                 continue;
1037
1038               use_insn = next_use[regno];
1039               if (BLOCK_FOR_INSN (use_insn) == bb)
1040                 {
1041                   /* flow.c claimed:
1042
1043                      We don't build a LOG_LINK for hard registers contained
1044                      in ASM_OPERANDs.  If these registers get replaced,
1045                      we might wind up changing the semantics of the insn,
1046                      even if reload can make what appear to be valid
1047                      assignments later.  */
1048                   if (regno >= FIRST_PSEUDO_REGISTER
1049                       || asm_noperands (PATTERN (use_insn)) < 0)
1050                     {
1051                       /* Don't add duplicate links between instructions.  */
1052                       struct insn_link *links;
1053                       FOR_EACH_LOG_LINK (links, use_insn)
1054                         if (insn == links->insn)
1055                           break;
1056
1057                       if (!links)
1058                         LOG_LINKS (use_insn)
1059                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1060                     }
1061                 }
1062               next_use[regno] = NULL_RTX;
1063             }
1064
1065           FOR_EACH_INSN_USE (use, insn)
1066             {
1067               int regno = DF_REF_REGNO (use);
1068
1069               /* Do not consider the usage of the stack pointer
1070                  by function call.  */
1071               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1072                 continue;
1073
1074               next_use[regno] = insn;
1075             }
1076         }
1077     }
1078
1079   free (next_use);
1080 }
1081
1082 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1083    true if we found a LOG_LINK that proves that A feeds B.  This only works
1084    if there are no instructions between A and B which could have a link
1085    depending on A, since in that case we would not record a link for B.
1086    We also check the implicit dependency created by a cc0 setter/user
1087    pair.  */
1088
1089 static bool
1090 insn_a_feeds_b (rtx a, rtx b)
1091 {
1092   struct insn_link *links;
1093   FOR_EACH_LOG_LINK (links, b)
1094     if (links->insn == a)
1095       return true;
1096 #ifdef HAVE_cc0
1097   if (sets_cc0_p (a))
1098     return true;
1099 #endif
1100   return false;
1101 }
1102 \f
1103 /* Main entry point for combiner.  F is the first insn of the function.
1104    NREGS is the first unused pseudo-reg number.
1105
1106    Return nonzero if the combiner has turned an indirect jump
1107    instruction into a direct jump.  */
1108 static int
1109 combine_instructions (rtx f, unsigned int nregs)
1110 {
1111   rtx insn, next;
1112 #ifdef HAVE_cc0
1113   rtx prev;
1114 #endif
1115   struct insn_link *links, *nextlinks;
1116   rtx first;
1117   basic_block last_bb;
1118
1119   int new_direct_jump_p = 0;
1120
1121   for (first = f; first && !INSN_P (first); )
1122     first = NEXT_INSN (first);
1123   if (!first)
1124     return 0;
1125
1126   combine_attempts = 0;
1127   combine_merges = 0;
1128   combine_extras = 0;
1129   combine_successes = 0;
1130
1131   rtl_hooks = combine_rtl_hooks;
1132
1133   reg_stat.safe_grow_cleared (nregs);
1134
1135   init_recog_no_volatile ();
1136
1137   /* Allocate array for insn info.  */
1138   max_uid_known = get_max_uid ();
1139   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1140   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1141   gcc_obstack_init (&insn_link_obstack);
1142
1143   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1144
1145   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1146      problems when, for example, we have j <<= 1 in a loop.  */
1147
1148   nonzero_sign_valid = 0;
1149   label_tick = label_tick_ebb_start = 1;
1150
1151   /* Scan all SETs and see if we can deduce anything about what
1152      bits are known to be zero for some registers and how many copies
1153      of the sign bit are known to exist for those registers.
1154
1155      Also set any known values so that we can use it while searching
1156      for what bits are known to be set.  */
1157
1158   setup_incoming_promotions (first);
1159   /* Allow the entry block and the first block to fall into the same EBB.
1160      Conceptually the incoming promotions are assigned to the entry block.  */
1161   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1162
1163   create_log_links ();
1164   FOR_EACH_BB_FN (this_basic_block, cfun)
1165     {
1166       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1167       last_call_luid = 0;
1168       mem_last_set = -1;
1169
1170       label_tick++;
1171       if (!single_pred_p (this_basic_block)
1172           || single_pred (this_basic_block) != last_bb)
1173         label_tick_ebb_start = label_tick;
1174       last_bb = this_basic_block;
1175
1176       FOR_BB_INSNS (this_basic_block, insn)
1177         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1178           {
1179 #ifdef AUTO_INC_DEC
1180             rtx links;
1181 #endif
1182
1183             subst_low_luid = DF_INSN_LUID (insn);
1184             subst_insn = insn;
1185
1186             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1187                          insn);
1188             record_dead_and_set_regs (insn);
1189
1190 #ifdef AUTO_INC_DEC
1191             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1192               if (REG_NOTE_KIND (links) == REG_INC)
1193                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1194                                                   insn);
1195 #endif
1196
1197             /* Record the current insn_rtx_cost of this instruction.  */
1198             if (NONJUMP_INSN_P (insn))
1199               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1200                                                 optimize_this_for_speed_p);
1201             if (dump_file)
1202               fprintf (dump_file, "insn_cost %d: %d\n",
1203                        INSN_UID (insn), INSN_COST (insn));
1204           }
1205     }
1206
1207   nonzero_sign_valid = 1;
1208
1209   /* Now scan all the insns in forward order.  */
1210   label_tick = label_tick_ebb_start = 1;
1211   init_reg_last ();
1212   setup_incoming_promotions (first);
1213   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1214   int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
1215
1216   FOR_EACH_BB_FN (this_basic_block, cfun)
1217     {
1218       rtx last_combined_insn = NULL_RTX;
1219       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1220       last_call_luid = 0;
1221       mem_last_set = -1;
1222
1223       label_tick++;
1224       if (!single_pred_p (this_basic_block)
1225           || single_pred (this_basic_block) != last_bb)
1226         label_tick_ebb_start = label_tick;
1227       last_bb = this_basic_block;
1228
1229       rtl_profile_for_bb (this_basic_block);
1230       for (insn = BB_HEAD (this_basic_block);
1231            insn != NEXT_INSN (BB_END (this_basic_block));
1232            insn = next ? next : NEXT_INSN (insn))
1233         {
1234           next = 0;
1235           if (!NONDEBUG_INSN_P (insn))
1236             continue;
1237
1238           while (last_combined_insn
1239                  && INSN_DELETED_P (last_combined_insn))
1240             last_combined_insn = PREV_INSN (last_combined_insn);
1241           if (last_combined_insn == NULL_RTX
1242               || BARRIER_P (last_combined_insn)
1243               || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1244               || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1245             last_combined_insn = insn;
1246
1247           /* See if we know about function return values before this
1248              insn based upon SUBREG flags.  */
1249           check_promoted_subreg (insn, PATTERN (insn));
1250
1251           /* See if we can find hardregs and subreg of pseudos in
1252              narrower modes.  This could help turning TRUNCATEs
1253              into SUBREGs.  */
1254           note_uses (&PATTERN (insn), record_truncated_values, NULL);
1255
1256           /* Try this insn with each insn it links back to.  */
1257
1258           FOR_EACH_LOG_LINK (links, insn)
1259             if ((next = try_combine (insn, links->insn, NULL_RTX,
1260                                      NULL_RTX, &new_direct_jump_p,
1261                                      last_combined_insn)) != 0)
1262               {
1263                 statistics_counter_event (cfun, "two-insn combine", 1);
1264                 goto retry;
1265               }
1266
1267           /* Try each sequence of three linked insns ending with this one.  */
1268
1269           if (max_combine >= 3)
1270             FOR_EACH_LOG_LINK (links, insn)
1271               {
1272                 rtx link = links->insn;
1273
1274                 /* If the linked insn has been replaced by a note, then there
1275                    is no point in pursuing this chain any further.  */
1276                 if (NOTE_P (link))
1277                   continue;
1278
1279                 FOR_EACH_LOG_LINK (nextlinks, link)
1280                   if ((next = try_combine (insn, link, nextlinks->insn,
1281                                            NULL_RTX, &new_direct_jump_p,
1282                                            last_combined_insn)) != 0)
1283                     {
1284                       statistics_counter_event (cfun, "three-insn combine", 1);
1285                       goto retry;
1286                     }
1287               }
1288
1289 #ifdef HAVE_cc0
1290           /* Try to combine a jump insn that uses CC0
1291              with a preceding insn that sets CC0, and maybe with its
1292              logical predecessor as well.
1293              This is how we make decrement-and-branch insns.
1294              We need this special code because data flow connections
1295              via CC0 do not get entered in LOG_LINKS.  */
1296
1297           if (JUMP_P (insn)
1298               && (prev = prev_nonnote_insn (insn)) != 0
1299               && NONJUMP_INSN_P (prev)
1300               && sets_cc0_p (PATTERN (prev)))
1301             {
1302               if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1303                                        &new_direct_jump_p,
1304                                        last_combined_insn)) != 0)
1305                 goto retry;
1306
1307               FOR_EACH_LOG_LINK (nextlinks, prev)
1308                   if ((next = try_combine (insn, prev, nextlinks->insn,
1309                                            NULL_RTX, &new_direct_jump_p,
1310                                            last_combined_insn)) != 0)
1311                     goto retry;
1312             }
1313
1314           /* Do the same for an insn that explicitly references CC0.  */
1315           if (NONJUMP_INSN_P (insn)
1316               && (prev = prev_nonnote_insn (insn)) != 0
1317               && NONJUMP_INSN_P (prev)
1318               && sets_cc0_p (PATTERN (prev))
1319               && GET_CODE (PATTERN (insn)) == SET
1320               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1321             {
1322               if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1323                                        &new_direct_jump_p,
1324                                        last_combined_insn)) != 0)
1325                 goto retry;
1326
1327               FOR_EACH_LOG_LINK (nextlinks, prev)
1328                   if ((next = try_combine (insn, prev, nextlinks->insn,
1329                                            NULL_RTX, &new_direct_jump_p,
1330                                            last_combined_insn)) != 0)
1331                     goto retry;
1332             }
1333
1334           /* Finally, see if any of the insns that this insn links to
1335              explicitly references CC0.  If so, try this insn, that insn,
1336              and its predecessor if it sets CC0.  */
1337           FOR_EACH_LOG_LINK (links, insn)
1338               if (NONJUMP_INSN_P (links->insn)
1339                   && GET_CODE (PATTERN (links->insn)) == SET
1340                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1341                   && (prev = prev_nonnote_insn (links->insn)) != 0
1342                   && NONJUMP_INSN_P (prev)
1343                   && sets_cc0_p (PATTERN (prev))
1344                   && (next = try_combine (insn, links->insn,
1345                                           prev, NULL_RTX, &new_direct_jump_p,
1346                                           last_combined_insn)) != 0)
1347                 goto retry;
1348 #endif
1349
1350           /* Try combining an insn with two different insns whose results it
1351              uses.  */
1352           if (max_combine >= 3)
1353             FOR_EACH_LOG_LINK (links, insn)
1354               for (nextlinks = links->next; nextlinks;
1355                    nextlinks = nextlinks->next)
1356                 if ((next = try_combine (insn, links->insn,
1357                                          nextlinks->insn, NULL_RTX,
1358                                          &new_direct_jump_p,
1359                                          last_combined_insn)) != 0)
1360
1361                   {
1362                     statistics_counter_event (cfun, "three-insn combine", 1);
1363                     goto retry;
1364                   }
1365
1366           /* Try four-instruction combinations.  */
1367           if (max_combine >= 4)
1368             FOR_EACH_LOG_LINK (links, insn)
1369               {
1370                 struct insn_link *next1;
1371                 rtx link = links->insn;
1372
1373                 /* If the linked insn has been replaced by a note, then there
1374                    is no point in pursuing this chain any further.  */
1375                 if (NOTE_P (link))
1376                   continue;
1377
1378                 FOR_EACH_LOG_LINK (next1, link)
1379                   {
1380                     rtx link1 = next1->insn;
1381                     if (NOTE_P (link1))
1382                       continue;
1383                     /* I0 -> I1 -> I2 -> I3.  */
1384                     FOR_EACH_LOG_LINK (nextlinks, link1)
1385                       if ((next = try_combine (insn, link, link1,
1386                                                nextlinks->insn,
1387                                                &new_direct_jump_p,
1388                                                last_combined_insn)) != 0)
1389                         {
1390                           statistics_counter_event (cfun, "four-insn combine", 1);
1391                           goto retry;
1392                         }
1393                     /* I0, I1 -> I2, I2 -> I3.  */
1394                     for (nextlinks = next1->next; nextlinks;
1395                          nextlinks = nextlinks->next)
1396                       if ((next = try_combine (insn, link, link1,
1397                                                nextlinks->insn,
1398                                                &new_direct_jump_p,
1399                                                last_combined_insn)) != 0)
1400                         {
1401                           statistics_counter_event (cfun, "four-insn combine", 1);
1402                           goto retry;
1403                         }
1404                   }
1405
1406                 for (next1 = links->next; next1; next1 = next1->next)
1407                   {
1408                     rtx link1 = next1->insn;
1409                     if (NOTE_P (link1))
1410                       continue;
1411                     /* I0 -> I2; I1, I2 -> I3.  */
1412                     FOR_EACH_LOG_LINK (nextlinks, link)
1413                       if ((next = try_combine (insn, link, link1,
1414                                                nextlinks->insn,
1415                                                &new_direct_jump_p,
1416                                                last_combined_insn)) != 0)
1417                         {
1418                           statistics_counter_event (cfun, "four-insn combine", 1);
1419                           goto retry;
1420                         }
1421                     /* I0 -> I1; I1, I2 -> I3.  */
1422                     FOR_EACH_LOG_LINK (nextlinks, link1)
1423                       if ((next = try_combine (insn, link, link1,
1424                                                nextlinks->insn,
1425                                                &new_direct_jump_p,
1426                                                last_combined_insn)) != 0)
1427                         {
1428                           statistics_counter_event (cfun, "four-insn combine", 1);
1429                           goto retry;
1430                         }
1431                   }
1432               }
1433
1434           /* Try this insn with each REG_EQUAL note it links back to.  */
1435           FOR_EACH_LOG_LINK (links, insn)
1436             {
1437               rtx set, note;
1438               rtx temp = links->insn;
1439               if ((set = single_set (temp)) != 0
1440                   && (note = find_reg_equal_equiv_note (temp)) != 0
1441                   && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1442                   /* Avoid using a register that may already been marked
1443                      dead by an earlier instruction.  */
1444                   && ! unmentioned_reg_p (note, SET_SRC (set))
1445                   && (GET_MODE (note) == VOIDmode
1446                       ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1447                       : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1448                 {
1449                   /* Temporarily replace the set's source with the
1450                      contents of the REG_EQUAL note.  The insn will
1451                      be deleted or recognized by try_combine.  */
1452                   rtx orig = SET_SRC (set);
1453                   SET_SRC (set) = note;
1454                   i2mod = temp;
1455                   i2mod_old_rhs = copy_rtx (orig);
1456                   i2mod_new_rhs = copy_rtx (note);
1457                   next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1458                                       &new_direct_jump_p,
1459                                       last_combined_insn);
1460                   i2mod = NULL_RTX;
1461                   if (next)
1462                     {
1463                       statistics_counter_event (cfun, "insn-with-note combine", 1);
1464                       goto retry;
1465                     }
1466                   SET_SRC (set) = orig;
1467                 }
1468             }
1469
1470           if (!NOTE_P (insn))
1471             record_dead_and_set_regs (insn);
1472
1473 retry:
1474           ;
1475         }
1476     }
1477
1478   default_rtl_profile ();
1479   clear_bb_flags ();
1480   new_direct_jump_p |= purge_all_dead_edges ();
1481   delete_noop_moves ();
1482
1483   /* Clean up.  */
1484   obstack_free (&insn_link_obstack, NULL);
1485   free (uid_log_links);
1486   free (uid_insn_cost);
1487   reg_stat.release ();
1488
1489   {
1490     struct undo *undo, *next;
1491     for (undo = undobuf.frees; undo; undo = next)
1492       {
1493         next = undo->next;
1494         free (undo);
1495       }
1496     undobuf.frees = 0;
1497   }
1498
1499   total_attempts += combine_attempts;
1500   total_merges += combine_merges;
1501   total_extras += combine_extras;
1502   total_successes += combine_successes;
1503
1504   nonzero_sign_valid = 0;
1505   rtl_hooks = general_rtl_hooks;
1506
1507   /* Make recognizer allow volatile MEMs again.  */
1508   init_recog ();
1509
1510   return new_direct_jump_p;
1511 }
1512
1513 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1514
1515 static void
1516 init_reg_last (void)
1517 {
1518   unsigned int i;
1519   reg_stat_type *p;
1520
1521   FOR_EACH_VEC_ELT (reg_stat, i, p)
1522     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1523 }
1524 \f
1525 /* Set up any promoted values for incoming argument registers.  */
1526
1527 static void
1528 setup_incoming_promotions (rtx first)
1529 {
1530   tree arg;
1531   bool strictly_local = false;
1532
1533   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1534        arg = DECL_CHAIN (arg))
1535     {
1536       rtx x, reg = DECL_INCOMING_RTL (arg);
1537       int uns1, uns3;
1538       enum machine_mode mode1, mode2, mode3, mode4;
1539
1540       /* Only continue if the incoming argument is in a register.  */
1541       if (!REG_P (reg))
1542         continue;
1543
1544       /* Determine, if possible, whether all call sites of the current
1545          function lie within the current compilation unit.  (This does
1546          take into account the exporting of a function via taking its
1547          address, and so forth.)  */
1548       strictly_local = cgraph_local_info (current_function_decl)->local;
1549
1550       /* The mode and signedness of the argument before any promotions happen
1551          (equal to the mode of the pseudo holding it at that stage).  */
1552       mode1 = TYPE_MODE (TREE_TYPE (arg));
1553       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1554
1555       /* The mode and signedness of the argument after any source language and
1556          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1557       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1558       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1559
1560       /* The mode and signedness of the argument as it is actually passed,
1561          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1562       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1563                                      TREE_TYPE (cfun->decl), 0);
1564
1565       /* The mode of the register in which the argument is being passed.  */
1566       mode4 = GET_MODE (reg);
1567
1568       /* Eliminate sign extensions in the callee when:
1569          (a) A mode promotion has occurred;  */
1570       if (mode1 == mode3)
1571         continue;
1572       /* (b) The mode of the register is the same as the mode of
1573              the argument as it is passed; */
1574       if (mode3 != mode4)
1575         continue;
1576       /* (c) There's no language level extension;  */
1577       if (mode1 == mode2)
1578         ;
1579       /* (c.1) All callers are from the current compilation unit.  If that's
1580          the case we don't have to rely on an ABI, we only have to know
1581          what we're generating right now, and we know that we will do the
1582          mode1 to mode2 promotion with the given sign.  */
1583       else if (!strictly_local)
1584         continue;
1585       /* (c.2) The combination of the two promotions is useful.  This is
1586          true when the signs match, or if the first promotion is unsigned.
1587          In the later case, (sign_extend (zero_extend x)) is the same as
1588          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1589       else if (uns1)
1590         uns3 = true;
1591       else if (uns3)
1592         continue;
1593
1594       /* Record that the value was promoted from mode1 to mode3,
1595          so that any sign extension at the head of the current
1596          function may be eliminated.  */
1597       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1598       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1599       record_value_for_reg (reg, first, x);
1600     }
1601 }
1602
1603 /* Called via note_stores.  If X is a pseudo that is narrower than
1604    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1605
1606    If we are setting only a portion of X and we can't figure out what
1607    portion, assume all bits will be used since we don't know what will
1608    be happening.
1609
1610    Similarly, set how many bits of X are known to be copies of the sign bit
1611    at all locations in the function.  This is the smallest number implied
1612    by any set of X.  */
1613
1614 static void
1615 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1616 {
1617   rtx insn = (rtx) data;
1618   unsigned int num;
1619
1620   if (REG_P (x)
1621       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1622       /* If this register is undefined at the start of the file, we can't
1623          say what its contents were.  */
1624       && ! REGNO_REG_SET_P
1625            (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1626       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1627     {
1628       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1629
1630       if (set == 0 || GET_CODE (set) == CLOBBER)
1631         {
1632           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1633           rsp->sign_bit_copies = 1;
1634           return;
1635         }
1636
1637       /* If this register is being initialized using itself, and the
1638          register is uninitialized in this basic block, and there are
1639          no LOG_LINKS which set the register, then part of the
1640          register is uninitialized.  In that case we can't assume
1641          anything about the number of nonzero bits.
1642
1643          ??? We could do better if we checked this in
1644          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1645          could avoid making assumptions about the insn which initially
1646          sets the register, while still using the information in other
1647          insns.  We would have to be careful to check every insn
1648          involved in the combination.  */
1649
1650       if (insn
1651           && reg_referenced_p (x, PATTERN (insn))
1652           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1653                                REGNO (x)))
1654         {
1655           struct insn_link *link;
1656
1657           FOR_EACH_LOG_LINK (link, insn)
1658             if (dead_or_set_p (link->insn, x))
1659               break;
1660           if (!link)
1661             {
1662               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1663               rsp->sign_bit_copies = 1;
1664               return;
1665             }
1666         }
1667
1668       /* If this is a complex assignment, see if we can convert it into a
1669          simple assignment.  */
1670       set = expand_field_assignment (set);
1671
1672       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1673          set what we know about X.  */
1674
1675       if (SET_DEST (set) == x
1676           || (paradoxical_subreg_p (SET_DEST (set))
1677               && SUBREG_REG (SET_DEST (set)) == x))
1678         {
1679           rtx src = SET_SRC (set);
1680
1681 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1682           /* If X is narrower than a word and SRC is a non-negative
1683              constant that would appear negative in the mode of X,
1684              sign-extend it for use in reg_stat[].nonzero_bits because some
1685              machines (maybe most) will actually do the sign-extension
1686              and this is the conservative approach.
1687
1688              ??? For 2.5, try to tighten up the MD files in this regard
1689              instead of this kludge.  */
1690
1691           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1692               && CONST_INT_P (src)
1693               && INTVAL (src) > 0
1694               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1695             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1696 #endif
1697
1698           /* Don't call nonzero_bits if it cannot change anything.  */
1699           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1700             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1701           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1702           if (rsp->sign_bit_copies == 0
1703               || rsp->sign_bit_copies > num)
1704             rsp->sign_bit_copies = num;
1705         }
1706       else
1707         {
1708           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1709           rsp->sign_bit_copies = 1;
1710         }
1711     }
1712 }
1713 \f
1714 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1715    optionally insns that were previously combined into I3 or that will be
1716    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1717    INSN, SUCC, SUCC2, I3.
1718
1719    Return 0 if the combination is not allowed for any reason.
1720
1721    If the combination is allowed, *PDEST will be set to the single
1722    destination of INSN and *PSRC to the single source, and this function
1723    will return 1.  */
1724
1725 static int
1726 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1727                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1728                rtx *pdest, rtx *psrc)
1729 {
1730   int i;
1731   const_rtx set = 0;
1732   rtx src, dest;
1733   rtx p;
1734 #ifdef AUTO_INC_DEC
1735   rtx link;
1736 #endif
1737   bool all_adjacent = true;
1738   int (*is_volatile_p) (const_rtx);
1739
1740   if (succ)
1741     {
1742       if (succ2)
1743         {
1744           if (next_active_insn (succ2) != i3)
1745             all_adjacent = false;
1746           if (next_active_insn (succ) != succ2)
1747             all_adjacent = false;
1748         }
1749       else if (next_active_insn (succ) != i3)
1750         all_adjacent = false;
1751       if (next_active_insn (insn) != succ)
1752         all_adjacent = false;
1753     }
1754   else if (next_active_insn (insn) != i3)
1755     all_adjacent = false;
1756
1757   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1758      or a PARALLEL consisting of such a SET and CLOBBERs.
1759
1760      If INSN has CLOBBER parallel parts, ignore them for our processing.
1761      By definition, these happen during the execution of the insn.  When it
1762      is merged with another insn, all bets are off.  If they are, in fact,
1763      needed and aren't also supplied in I3, they may be added by
1764      recog_for_combine.  Otherwise, it won't match.
1765
1766      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1767      note.
1768
1769      Get the source and destination of INSN.  If more than one, can't
1770      combine.  */
1771
1772   if (GET_CODE (PATTERN (insn)) == SET)
1773     set = PATTERN (insn);
1774   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1775            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1776     {
1777       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1778         {
1779           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1780
1781           switch (GET_CODE (elt))
1782             {
1783             /* This is important to combine floating point insns
1784                for the SH4 port.  */
1785             case USE:
1786               /* Combining an isolated USE doesn't make sense.
1787                  We depend here on combinable_i3pat to reject them.  */
1788               /* The code below this loop only verifies that the inputs of
1789                  the SET in INSN do not change.  We call reg_set_between_p
1790                  to verify that the REG in the USE does not change between
1791                  I3 and INSN.
1792                  If the USE in INSN was for a pseudo register, the matching
1793                  insn pattern will likely match any register; combining this
1794                  with any other USE would only be safe if we knew that the
1795                  used registers have identical values, or if there was
1796                  something to tell them apart, e.g. different modes.  For
1797                  now, we forgo such complicated tests and simply disallow
1798                  combining of USES of pseudo registers with any other USE.  */
1799               if (REG_P (XEXP (elt, 0))
1800                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1801                 {
1802                   rtx i3pat = PATTERN (i3);
1803                   int i = XVECLEN (i3pat, 0) - 1;
1804                   unsigned int regno = REGNO (XEXP (elt, 0));
1805
1806                   do
1807                     {
1808                       rtx i3elt = XVECEXP (i3pat, 0, i);
1809
1810                       if (GET_CODE (i3elt) == USE
1811                           && REG_P (XEXP (i3elt, 0))
1812                           && (REGNO (XEXP (i3elt, 0)) == regno
1813                               ? reg_set_between_p (XEXP (elt, 0),
1814                                                    PREV_INSN (insn), i3)
1815                               : regno >= FIRST_PSEUDO_REGISTER))
1816                         return 0;
1817                     }
1818                   while (--i >= 0);
1819                 }
1820               break;
1821
1822               /* We can ignore CLOBBERs.  */
1823             case CLOBBER:
1824               break;
1825
1826             case SET:
1827               /* Ignore SETs whose result isn't used but not those that
1828                  have side-effects.  */
1829               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1830                   && insn_nothrow_p (insn)
1831                   && !side_effects_p (elt))
1832                 break;
1833
1834               /* If we have already found a SET, this is a second one and
1835                  so we cannot combine with this insn.  */
1836               if (set)
1837                 return 0;
1838
1839               set = elt;
1840               break;
1841
1842             default:
1843               /* Anything else means we can't combine.  */
1844               return 0;
1845             }
1846         }
1847
1848       if (set == 0
1849           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1850              so don't do anything with it.  */
1851           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1852         return 0;
1853     }
1854   else
1855     return 0;
1856
1857   if (set == 0)
1858     return 0;
1859
1860   /* The simplification in expand_field_assignment may call back to
1861      get_last_value, so set safe guard here.  */
1862   subst_low_luid = DF_INSN_LUID (insn);
1863
1864   set = expand_field_assignment (set);
1865   src = SET_SRC (set), dest = SET_DEST (set);
1866
1867   /* Don't eliminate a store in the stack pointer.  */
1868   if (dest == stack_pointer_rtx
1869       /* Don't combine with an insn that sets a register to itself if it has
1870          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1871       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1872       /* Can't merge an ASM_OPERANDS.  */
1873       || GET_CODE (src) == ASM_OPERANDS
1874       /* Can't merge a function call.  */
1875       || GET_CODE (src) == CALL
1876       /* Don't eliminate a function call argument.  */
1877       || (CALL_P (i3)
1878           && (find_reg_fusage (i3, USE, dest)
1879               || (REG_P (dest)
1880                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1881                   && global_regs[REGNO (dest)])))
1882       /* Don't substitute into an incremented register.  */
1883       || FIND_REG_INC_NOTE (i3, dest)
1884       || (succ && FIND_REG_INC_NOTE (succ, dest))
1885       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1886       /* Don't substitute into a non-local goto, this confuses CFG.  */
1887       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1888       /* Make sure that DEST is not used after SUCC but before I3.  */
1889       || (!all_adjacent
1890           && ((succ2
1891                && (reg_used_between_p (dest, succ2, i3)
1892                    || reg_used_between_p (dest, succ, succ2)))
1893               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1894       /* Make sure that the value that is to be substituted for the register
1895          does not use any registers whose values alter in between.  However,
1896          If the insns are adjacent, a use can't cross a set even though we
1897          think it might (this can happen for a sequence of insns each setting
1898          the same destination; last_set of that register might point to
1899          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1900          equivalent to the memory so the substitution is valid even if there
1901          are intervening stores.  Also, don't move a volatile asm or
1902          UNSPEC_VOLATILE across any other insns.  */
1903       || (! all_adjacent
1904           && (((!MEM_P (src)
1905                 || ! find_reg_note (insn, REG_EQUIV, src))
1906                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1907               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1908               || GET_CODE (src) == UNSPEC_VOLATILE))
1909       /* Don't combine across a CALL_INSN, because that would possibly
1910          change whether the life span of some REGs crosses calls or not,
1911          and it is a pain to update that information.
1912          Exception: if source is a constant, moving it later can't hurt.
1913          Accept that as a special case.  */
1914       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1915     return 0;
1916
1917   /* DEST must either be a REG or CC0.  */
1918   if (REG_P (dest))
1919     {
1920       /* If register alignment is being enforced for multi-word items in all
1921          cases except for parameters, it is possible to have a register copy
1922          insn referencing a hard register that is not allowed to contain the
1923          mode being copied and which would not be valid as an operand of most
1924          insns.  Eliminate this problem by not combining with such an insn.
1925
1926          Also, on some machines we don't want to extend the life of a hard
1927          register.  */
1928
1929       if (REG_P (src)
1930           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1931                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1932               /* Don't extend the life of a hard register unless it is
1933                  user variable (if we have few registers) or it can't
1934                  fit into the desired register (meaning something special
1935                  is going on).
1936                  Also avoid substituting a return register into I3, because
1937                  reload can't handle a conflict with constraints of other
1938                  inputs.  */
1939               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1940                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1941         return 0;
1942     }
1943   else if (GET_CODE (dest) != CC0)
1944     return 0;
1945
1946
1947   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1948     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1949       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1950         {
1951           /* Don't substitute for a register intended as a clobberable
1952              operand.  */
1953           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1954           if (rtx_equal_p (reg, dest))
1955             return 0;
1956
1957           /* If the clobber represents an earlyclobber operand, we must not
1958              substitute an expression containing the clobbered register.
1959              As we do not analyze the constraint strings here, we have to
1960              make the conservative assumption.  However, if the register is
1961              a fixed hard reg, the clobber cannot represent any operand;
1962              we leave it up to the machine description to either accept or
1963              reject use-and-clobber patterns.  */
1964           if (!REG_P (reg)
1965               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1966               || !fixed_regs[REGNO (reg)])
1967             if (reg_overlap_mentioned_p (reg, src))
1968               return 0;
1969         }
1970
1971   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1972      or not), reject, unless nothing volatile comes between it and I3 */
1973
1974   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1975     {
1976       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1977       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1978         return 0;
1979       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1980         return 0;
1981       /* We'll check insns between INSN and I3 below.  */
1982     }
1983
1984   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1985      to be an explicit register variable, and was chosen for a reason.  */
1986
1987   if (GET_CODE (src) == ASM_OPERANDS
1988       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1989     return 0;
1990
1991   /* If INSN contains volatile references (specifically volatile MEMs),
1992      we cannot combine across any other volatile references.
1993      Even if INSN doesn't contain volatile references, any intervening
1994      volatile insn might affect machine state.  */
1995
1996   is_volatile_p = volatile_refs_p (PATTERN (insn))
1997     ? volatile_refs_p
1998     : volatile_insn_p;
1999
2000   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2001     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2002       return 0;
2003
2004   /* If INSN contains an autoincrement or autodecrement, make sure that
2005      register is not used between there and I3, and not already used in
2006      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
2007      Also insist that I3 not be a jump; if it were one
2008      and the incremented register were spilled, we would lose.  */
2009
2010 #ifdef AUTO_INC_DEC
2011   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2012     if (REG_NOTE_KIND (link) == REG_INC
2013         && (JUMP_P (i3)
2014             || reg_used_between_p (XEXP (link, 0), insn, i3)
2015             || (pred != NULL_RTX
2016                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2017             || (pred2 != NULL_RTX
2018                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2019             || (succ != NULL_RTX
2020                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2021             || (succ2 != NULL_RTX
2022                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2023             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2024       return 0;
2025 #endif
2026
2027 #ifdef HAVE_cc0
2028   /* Don't combine an insn that follows a CC0-setting insn.
2029      An insn that uses CC0 must not be separated from the one that sets it.
2030      We do, however, allow I2 to follow a CC0-setting insn if that insn
2031      is passed as I1; in that case it will be deleted also.
2032      We also allow combining in this case if all the insns are adjacent
2033      because that would leave the two CC0 insns adjacent as well.
2034      It would be more logical to test whether CC0 occurs inside I1 or I2,
2035      but that would be much slower, and this ought to be equivalent.  */
2036
2037   p = prev_nonnote_insn (insn);
2038   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2039       && ! all_adjacent)
2040     return 0;
2041 #endif
2042
2043   /* If we get here, we have passed all the tests and the combination is
2044      to be allowed.  */
2045
2046   *pdest = dest;
2047   *psrc = src;
2048
2049   return 1;
2050 }
2051 \f
2052 /* LOC is the location within I3 that contains its pattern or the component
2053    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2054
2055    One problem is if I3 modifies its output, as opposed to replacing it
2056    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2057    doing so would produce an insn that is not equivalent to the original insns.
2058
2059    Consider:
2060
2061          (set (reg:DI 101) (reg:DI 100))
2062          (set (subreg:SI (reg:DI 101) 0) <foo>)
2063
2064    This is NOT equivalent to:
2065
2066          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2067                     (set (reg:DI 101) (reg:DI 100))])
2068
2069    Not only does this modify 100 (in which case it might still be valid
2070    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2071
2072    We can also run into a problem if I2 sets a register that I1
2073    uses and I1 gets directly substituted into I3 (not via I2).  In that
2074    case, we would be getting the wrong value of I2DEST into I3, so we
2075    must reject the combination.  This case occurs when I2 and I1 both
2076    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2077    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2078    of a SET must prevent combination from occurring.  The same situation
2079    can occur for I0, in which case I0_NOT_IN_SRC is set.
2080
2081    Before doing the above check, we first try to expand a field assignment
2082    into a set of logical operations.
2083
2084    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2085    we place a register that is both set and used within I3.  If more than one
2086    such register is detected, we fail.
2087
2088    Return 1 if the combination is valid, zero otherwise.  */
2089
2090 static int
2091 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2092                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2093 {
2094   rtx x = *loc;
2095
2096   if (GET_CODE (x) == SET)
2097     {
2098       rtx set = x ;
2099       rtx dest = SET_DEST (set);
2100       rtx src = SET_SRC (set);
2101       rtx inner_dest = dest;
2102       rtx subdest;
2103
2104       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2105              || GET_CODE (inner_dest) == SUBREG
2106              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2107         inner_dest = XEXP (inner_dest, 0);
2108
2109       /* Check for the case where I3 modifies its output, as discussed
2110          above.  We don't want to prevent pseudos from being combined
2111          into the address of a MEM, so only prevent the combination if
2112          i1 or i2 set the same MEM.  */
2113       if ((inner_dest != dest &&
2114            (!MEM_P (inner_dest)
2115             || rtx_equal_p (i2dest, inner_dest)
2116             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2117             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2118            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2119                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2120                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2121
2122           /* This is the same test done in can_combine_p except we can't test
2123              all_adjacent; we don't have to, since this instruction will stay
2124              in place, thus we are not considering increasing the lifetime of
2125              INNER_DEST.
2126
2127              Also, if this insn sets a function argument, combining it with
2128              something that might need a spill could clobber a previous
2129              function argument; the all_adjacent test in can_combine_p also
2130              checks this; here, we do a more specific test for this case.  */
2131
2132           || (REG_P (inner_dest)
2133               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2134               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2135                                         GET_MODE (inner_dest))))
2136           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2137           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2138         return 0;
2139
2140       /* If DEST is used in I3, it is being killed in this insn, so
2141          record that for later.  We have to consider paradoxical
2142          subregs here, since they kill the whole register, but we
2143          ignore partial subregs, STRICT_LOW_PART, etc.
2144          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2145          STACK_POINTER_REGNUM, since these are always considered to be
2146          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2147       subdest = dest;
2148       if (GET_CODE (subdest) == SUBREG
2149           && (GET_MODE_SIZE (GET_MODE (subdest))
2150               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2151         subdest = SUBREG_REG (subdest);
2152       if (pi3dest_killed
2153           && REG_P (subdest)
2154           && reg_referenced_p (subdest, PATTERN (i3))
2155           && REGNO (subdest) != FRAME_POINTER_REGNUM
2156 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2157           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2158 #endif
2159 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2160           && (REGNO (subdest) != ARG_POINTER_REGNUM
2161               || ! fixed_regs [REGNO (subdest)])
2162 #endif
2163           && REGNO (subdest) != STACK_POINTER_REGNUM)
2164         {
2165           if (*pi3dest_killed)
2166             return 0;
2167
2168           *pi3dest_killed = subdest;
2169         }
2170     }
2171
2172   else if (GET_CODE (x) == PARALLEL)
2173     {
2174       int i;
2175
2176       for (i = 0; i < XVECLEN (x, 0); i++)
2177         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2178                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2179           return 0;
2180     }
2181
2182   return 1;
2183 }
2184 \f
2185 /* Return 1 if X is an arithmetic expression that contains a multiplication
2186    and division.  We don't count multiplications by powers of two here.  */
2187
2188 static int
2189 contains_muldiv (rtx x)
2190 {
2191   switch (GET_CODE (x))
2192     {
2193     case MOD:  case DIV:  case UMOD:  case UDIV:
2194       return 1;
2195
2196     case MULT:
2197       return ! (CONST_INT_P (XEXP (x, 1))
2198                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2199     default:
2200       if (BINARY_P (x))
2201         return contains_muldiv (XEXP (x, 0))
2202             || contains_muldiv (XEXP (x, 1));
2203
2204       if (UNARY_P (x))
2205         return contains_muldiv (XEXP (x, 0));
2206
2207       return 0;
2208     }
2209 }
2210 \f
2211 /* Determine whether INSN can be used in a combination.  Return nonzero if
2212    not.  This is used in try_combine to detect early some cases where we
2213    can't perform combinations.  */
2214
2215 static int
2216 cant_combine_insn_p (rtx insn)
2217 {
2218   rtx set;
2219   rtx src, dest;
2220
2221   /* If this isn't really an insn, we can't do anything.
2222      This can occur when flow deletes an insn that it has merged into an
2223      auto-increment address.  */
2224   if (! INSN_P (insn))
2225     return 1;
2226
2227   /* Never combine loads and stores involving hard regs that are likely
2228      to be spilled.  The register allocator can usually handle such
2229      reg-reg moves by tying.  If we allow the combiner to make
2230      substitutions of likely-spilled regs, reload might die.
2231      As an exception, we allow combinations involving fixed regs; these are
2232      not available to the register allocator so there's no risk involved.  */
2233
2234   set = single_set (insn);
2235   if (! set)
2236     return 0;
2237   src = SET_SRC (set);
2238   dest = SET_DEST (set);
2239   if (GET_CODE (src) == SUBREG)
2240     src = SUBREG_REG (src);
2241   if (GET_CODE (dest) == SUBREG)
2242     dest = SUBREG_REG (dest);
2243   if (REG_P (src) && REG_P (dest)
2244       && ((HARD_REGISTER_P (src)
2245            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2246            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2247           || (HARD_REGISTER_P (dest)
2248               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2249               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2250     return 1;
2251
2252   return 0;
2253 }
2254
2255 struct likely_spilled_retval_info
2256 {
2257   unsigned regno, nregs;
2258   unsigned mask;
2259 };
2260
2261 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2262    hard registers that are known to be written to / clobbered in full.  */
2263 static void
2264 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2265 {
2266   struct likely_spilled_retval_info *const info =
2267     (struct likely_spilled_retval_info *) data;
2268   unsigned regno, nregs;
2269   unsigned new_mask;
2270
2271   if (!REG_P (XEXP (set, 0)))
2272     return;
2273   regno = REGNO (x);
2274   if (regno >= info->regno + info->nregs)
2275     return;
2276   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2277   if (regno + nregs <= info->regno)
2278     return;
2279   new_mask = (2U << (nregs - 1)) - 1;
2280   if (regno < info->regno)
2281     new_mask >>= info->regno - regno;
2282   else
2283     new_mask <<= regno - info->regno;
2284   info->mask &= ~new_mask;
2285 }
2286
2287 /* Return nonzero iff part of the return value is live during INSN, and
2288    it is likely spilled.  This can happen when more than one insn is needed
2289    to copy the return value, e.g. when we consider to combine into the
2290    second copy insn for a complex value.  */
2291
2292 static int
2293 likely_spilled_retval_p (rtx insn)
2294 {
2295   rtx use = BB_END (this_basic_block);
2296   rtx reg, p;
2297   unsigned regno, nregs;
2298   /* We assume here that no machine mode needs more than
2299      32 hard registers when the value overlaps with a register
2300      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2301   unsigned mask;
2302   struct likely_spilled_retval_info info;
2303
2304   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2305     return 0;
2306   reg = XEXP (PATTERN (use), 0);
2307   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2308     return 0;
2309   regno = REGNO (reg);
2310   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2311   if (nregs == 1)
2312     return 0;
2313   mask = (2U << (nregs - 1)) - 1;
2314
2315   /* Disregard parts of the return value that are set later.  */
2316   info.regno = regno;
2317   info.nregs = nregs;
2318   info.mask = mask;
2319   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2320     if (INSN_P (p))
2321       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2322   mask = info.mask;
2323
2324   /* Check if any of the (probably) live return value registers is
2325      likely spilled.  */
2326   nregs --;
2327   do
2328     {
2329       if ((mask & 1 << nregs)
2330           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2331         return 1;
2332     } while (nregs--);
2333   return 0;
2334 }
2335
2336 /* Adjust INSN after we made a change to its destination.
2337
2338    Changing the destination can invalidate notes that say something about
2339    the results of the insn and a LOG_LINK pointing to the insn.  */
2340
2341 static void
2342 adjust_for_new_dest (rtx insn)
2343 {
2344   /* For notes, be conservative and simply remove them.  */
2345   remove_reg_equal_equiv_notes (insn);
2346
2347   /* The new insn will have a destination that was previously the destination
2348      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2349      the next use of that destination.  */
2350   distribute_links (alloc_insn_link (insn, NULL));
2351
2352   df_insn_rescan (insn);
2353 }
2354
2355 /* Return TRUE if combine can reuse reg X in mode MODE.
2356    ADDED_SETS is nonzero if the original set is still required.  */
2357 static bool
2358 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2359 {
2360   unsigned int regno;
2361
2362   if (!REG_P (x))
2363     return false;
2364
2365   regno = REGNO (x);
2366   /* Allow hard registers if the new mode is legal, and occupies no more
2367      registers than the old mode.  */
2368   if (regno < FIRST_PSEUDO_REGISTER)
2369     return (HARD_REGNO_MODE_OK (regno, mode)
2370             && (hard_regno_nregs[regno][GET_MODE (x)]
2371                 >= hard_regno_nregs[regno][mode]));
2372
2373   /* Or a pseudo that is only used once.  */
2374   return (REG_N_SETS (regno) == 1 && !added_sets
2375           && !REG_USERVAR_P (x));
2376 }
2377
2378
2379 /* Check whether X, the destination of a set, refers to part of
2380    the register specified by REG.  */
2381
2382 static bool
2383 reg_subword_p (rtx x, rtx reg)
2384 {
2385   /* Check that reg is an integer mode register.  */
2386   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2387     return false;
2388
2389   if (GET_CODE (x) == STRICT_LOW_PART
2390       || GET_CODE (x) == ZERO_EXTRACT)
2391     x = XEXP (x, 0);
2392
2393   return GET_CODE (x) == SUBREG
2394          && SUBREG_REG (x) == reg
2395          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2396 }
2397
2398 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2399    Note that the INSN should be deleted *after* removing dead edges, so
2400    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2401    but not for a (set (pc) (label_ref FOO)).  */
2402
2403 static void
2404 update_cfg_for_uncondjump (rtx insn)
2405 {
2406   basic_block bb = BLOCK_FOR_INSN (insn);
2407   gcc_assert (BB_END (bb) == insn);
2408
2409   purge_dead_edges (bb);
2410
2411   delete_insn (insn);
2412   if (EDGE_COUNT (bb->succs) == 1)
2413     {
2414       rtx insn;
2415
2416       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2417
2418       /* Remove barriers from the footer if there are any.  */
2419       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2420         if (BARRIER_P (insn))
2421           {
2422             if (PREV_INSN (insn))
2423               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2424             else
2425               BB_FOOTER (bb) = NEXT_INSN (insn);
2426             if (NEXT_INSN (insn))
2427               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2428           }
2429         else if (LABEL_P (insn))
2430           break;
2431     }
2432 }
2433
2434 /* Try to combine the insns I0, I1 and I2 into I3.
2435    Here I0, I1 and I2 appear earlier than I3.
2436    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2437    I3.
2438
2439    If we are combining more than two insns and the resulting insn is not
2440    recognized, try splitting it into two insns.  If that happens, I2 and I3
2441    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2442    Otherwise, I0, I1 and I2 are pseudo-deleted.
2443
2444    Return 0 if the combination does not work.  Then nothing is changed.
2445    If we did the combination, return the insn at which combine should
2446    resume scanning.
2447
2448    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2449    new direct jump instruction.
2450
2451    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2452    been I3 passed to an earlier try_combine within the same basic
2453    block.  */
2454
2455 static rtx
2456 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2457              rtx last_combined_insn)
2458 {
2459   /* New patterns for I3 and I2, respectively.  */
2460   rtx newpat, newi2pat = 0;
2461   rtvec newpat_vec_with_clobbers = 0;
2462   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2463   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2464      dead.  */
2465   int added_sets_0, added_sets_1, added_sets_2;
2466   /* Total number of SETs to put into I3.  */
2467   int total_sets;
2468   /* Nonzero if I2's or I1's body now appears in I3.  */
2469   int i2_is_used = 0, i1_is_used = 0;
2470   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2471   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2472   /* Contains I3 if the destination of I3 is used in its source, which means
2473      that the old life of I3 is being killed.  If that usage is placed into
2474      I2 and not in I3, a REG_DEAD note must be made.  */
2475   rtx i3dest_killed = 0;
2476   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2477   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2478   /* Copy of SET_SRC of I1 and I0, if needed.  */
2479   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2480   /* Set if I2DEST was reused as a scratch register.  */
2481   bool i2scratch = false;
2482   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2483   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2484   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2485   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2486   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2487   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2488   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2489   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2490   rtx new_i3_notes, new_i2_notes;
2491   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2492   int i3_subst_into_i2 = 0;
2493   /* Notes that I1, I2 or I3 is a MULT operation.  */
2494   int have_mult = 0;
2495   int swap_i2i3 = 0;
2496   int changed_i3_dest = 0;
2497
2498   int maxreg;
2499   rtx temp;
2500   struct insn_link *link;
2501   rtx other_pat = 0;
2502   rtx new_other_notes;
2503   int i;
2504
2505   /* Only try four-insn combinations when there's high likelihood of
2506      success.  Look for simple insns, such as loads of constants or
2507      binary operations involving a constant.  */
2508   if (i0)
2509     {
2510       int i;
2511       int ngood = 0;
2512       int nshift = 0;
2513
2514       if (!flag_expensive_optimizations)
2515         return 0;
2516
2517       for (i = 0; i < 4; i++)
2518         {
2519           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2520           rtx set = single_set (insn);
2521           rtx src;
2522           if (!set)
2523             continue;
2524           src = SET_SRC (set);
2525           if (CONSTANT_P (src))
2526             {
2527               ngood += 2;
2528               break;
2529             }
2530           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2531             ngood++;
2532           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2533                    || GET_CODE (src) == LSHIFTRT)
2534             nshift++;
2535         }
2536       if (ngood < 2 && nshift < 2)
2537         return 0;
2538     }
2539
2540   /* Exit early if one of the insns involved can't be used for
2541      combinations.  */
2542   if (cant_combine_insn_p (i3)
2543       || cant_combine_insn_p (i2)
2544       || (i1 && cant_combine_insn_p (i1))
2545       || (i0 && cant_combine_insn_p (i0))
2546       || likely_spilled_retval_p (i3))
2547     return 0;
2548
2549   combine_attempts++;
2550   undobuf.other_insn = 0;
2551
2552   /* Reset the hard register usage information.  */
2553   CLEAR_HARD_REG_SET (newpat_used_regs);
2554
2555   if (dump_file && (dump_flags & TDF_DETAILS))
2556     {
2557       if (i0)
2558         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2559                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2560       else if (i1)
2561         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2562                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2563       else
2564         fprintf (dump_file, "\nTrying %d -> %d:\n",
2565                  INSN_UID (i2), INSN_UID (i3));
2566     }
2567
2568   /* If multiple insns feed into one of I2 or I3, they can be in any
2569      order.  To simplify the code below, reorder them in sequence.  */
2570   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2571     temp = i2, i2 = i0, i0 = temp;
2572   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2573     temp = i1, i1 = i0, i0 = temp;
2574   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2575     temp = i1, i1 = i2, i2 = temp;
2576
2577   added_links_insn = 0;
2578
2579   /* First check for one important special case that the code below will
2580      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2581      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2582      we may be able to replace that destination with the destination of I3.
2583      This occurs in the common code where we compute both a quotient and
2584      remainder into a structure, in which case we want to do the computation
2585      directly into the structure to avoid register-register copies.
2586
2587      Note that this case handles both multiple sets in I2 and also cases
2588      where I2 has a number of CLOBBERs inside the PARALLEL.
2589
2590      We make very conservative checks below and only try to handle the
2591      most common cases of this.  For example, we only handle the case
2592      where I2 and I3 are adjacent to avoid making difficult register
2593      usage tests.  */
2594
2595   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2596       && REG_P (SET_SRC (PATTERN (i3)))
2597       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2598       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2599       && GET_CODE (PATTERN (i2)) == PARALLEL
2600       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2601       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2602          below would need to check what is inside (and reg_overlap_mentioned_p
2603          doesn't support those codes anyway).  Don't allow those destinations;
2604          the resulting insn isn't likely to be recognized anyway.  */
2605       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2606       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2607       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2608                                     SET_DEST (PATTERN (i3)))
2609       && next_active_insn (i2) == i3)
2610     {
2611       rtx p2 = PATTERN (i2);
2612
2613       /* Make sure that the destination of I3,
2614          which we are going to substitute into one output of I2,
2615          is not used within another output of I2.  We must avoid making this:
2616          (parallel [(set (mem (reg 69)) ...)
2617                     (set (reg 69) ...)])
2618          which is not well-defined as to order of actions.
2619          (Besides, reload can't handle output reloads for this.)
2620
2621          The problem can also happen if the dest of I3 is a memory ref,
2622          if another dest in I2 is an indirect memory ref.  */
2623       for (i = 0; i < XVECLEN (p2, 0); i++)
2624         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2625              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2626             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2627                                         SET_DEST (XVECEXP (p2, 0, i))))
2628           break;
2629
2630       if (i == XVECLEN (p2, 0))
2631         for (i = 0; i < XVECLEN (p2, 0); i++)
2632           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2633               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2634             {
2635               combine_merges++;
2636
2637               subst_insn = i3;
2638               subst_low_luid = DF_INSN_LUID (i2);
2639
2640               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2641               i2src = SET_SRC (XVECEXP (p2, 0, i));
2642               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2643               i2dest_killed = dead_or_set_p (i2, i2dest);
2644
2645               /* Replace the dest in I2 with our dest and make the resulting
2646                  insn the new pattern for I3.  Then skip to where we validate
2647                  the pattern.  Everything was set up above.  */
2648               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2649               newpat = p2;
2650               i3_subst_into_i2 = 1;
2651               goto validate_replacement;
2652             }
2653     }
2654
2655   /* If I2 is setting a pseudo to a constant and I3 is setting some
2656      sub-part of it to another constant, merge them by making a new
2657      constant.  */
2658   if (i1 == 0
2659       && (temp = single_set (i2)) != 0
2660       && CONST_SCALAR_INT_P (SET_SRC (temp))
2661       && GET_CODE (PATTERN (i3)) == SET
2662       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2663       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2664     {
2665       rtx dest = SET_DEST (PATTERN (i3));
2666       int offset = -1;
2667       int width = 0;
2668
2669       if (GET_CODE (dest) == ZERO_EXTRACT)
2670         {
2671           if (CONST_INT_P (XEXP (dest, 1))
2672               && CONST_INT_P (XEXP (dest, 2)))
2673             {
2674               width = INTVAL (XEXP (dest, 1));
2675               offset = INTVAL (XEXP (dest, 2));
2676               dest = XEXP (dest, 0);
2677               if (BITS_BIG_ENDIAN)
2678                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2679             }
2680         }
2681       else
2682         {
2683           if (GET_CODE (dest) == STRICT_LOW_PART)
2684             dest = XEXP (dest, 0);
2685           width = GET_MODE_PRECISION (GET_MODE (dest));
2686           offset = 0;
2687         }
2688
2689       if (offset >= 0)
2690         {
2691           /* If this is the low part, we're done.  */
2692           if (subreg_lowpart_p (dest))
2693             ;
2694           /* Handle the case where inner is twice the size of outer.  */
2695           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2696                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2697             offset += GET_MODE_PRECISION (GET_MODE (dest));
2698           /* Otherwise give up for now.  */
2699           else
2700             offset = -1;
2701         }
2702
2703       if (offset >= 0)
2704         {
2705           rtx inner = SET_SRC (PATTERN (i3));
2706           rtx outer = SET_SRC (temp);
2707
2708           wide_int o
2709             = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp))),
2710                           std::make_pair (inner, GET_MODE (dest)),
2711                           offset, width);
2712
2713           combine_merges++;
2714           subst_insn = i3;
2715           subst_low_luid = DF_INSN_LUID (i2);
2716           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2717           i2dest = SET_DEST (temp);
2718           i2dest_killed = dead_or_set_p (i2, i2dest);
2719
2720           /* Replace the source in I2 with the new constant and make the
2721              resulting insn the new pattern for I3.  Then skip to where we
2722              validate the pattern.  Everything was set up above.  */
2723           SUBST (SET_SRC (temp),
2724                  immed_wide_int_const (o, GET_MODE (SET_DEST (temp))));
2725
2726           newpat = PATTERN (i2);
2727
2728           /* The dest of I3 has been replaced with the dest of I2.  */
2729           changed_i3_dest = 1;
2730           goto validate_replacement;
2731         }
2732     }
2733
2734 #ifndef HAVE_cc0
2735   /* If we have no I1 and I2 looks like:
2736         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2737                    (set Y OP)])
2738      make up a dummy I1 that is
2739         (set Y OP)
2740      and change I2 to be
2741         (set (reg:CC X) (compare:CC Y (const_int 0)))
2742
2743      (We can ignore any trailing CLOBBERs.)
2744
2745      This undoes a previous combination and allows us to match a branch-and-
2746      decrement insn.  */
2747
2748   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2749       && XVECLEN (PATTERN (i2), 0) >= 2
2750       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2751       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2752           == MODE_CC)
2753       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2754       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2755       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2756       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2757       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2758                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2759     {
2760       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2761         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2762           break;
2763
2764       if (i == 1)
2765         {
2766           /* We make I1 with the same INSN_UID as I2.  This gives it
2767              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2768              never appear in the insn stream so giving it the same INSN_UID
2769              as I2 will not cause a problem.  */
2770
2771           i1 = gen_rtx_INSN (VOIDmode, NULL_RTX, i2, BLOCK_FOR_INSN (i2),
2772                              XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2773                              -1, NULL_RTX);
2774           INSN_UID (i1) = INSN_UID (i2);
2775
2776           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2777           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2778                  SET_DEST (PATTERN (i1)));
2779           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2780         }
2781     }
2782 #endif
2783
2784   /* Verify that I2 and I1 are valid for combining.  */
2785   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2786       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2787                                  &i1dest, &i1src))
2788       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2789                                  &i0dest, &i0src)))
2790     {
2791       undo_all ();
2792       return 0;
2793     }
2794
2795   /* Record whether I2DEST is used in I2SRC and similarly for the other
2796      cases.  Knowing this will help in register status updating below.  */
2797   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2798   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2799   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2800   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2801   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2802   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2803   i2dest_killed = dead_or_set_p (i2, i2dest);
2804   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2805   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2806
2807   /* For the earlier insns, determine which of the subsequent ones they
2808      feed.  */
2809   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2810   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2811   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2812                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2813                              && reg_overlap_mentioned_p (i0dest, i2src))));
2814
2815   /* Ensure that I3's pattern can be the destination of combines.  */
2816   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2817                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2818                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2819                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2820                           &i3dest_killed))
2821     {
2822       undo_all ();
2823       return 0;
2824     }
2825
2826   /* See if any of the insns is a MULT operation.  Unless one is, we will
2827      reject a combination that is, since it must be slower.  Be conservative
2828      here.  */
2829   if (GET_CODE (i2src) == MULT
2830       || (i1 != 0 && GET_CODE (i1src) == MULT)
2831       || (i0 != 0 && GET_CODE (i0src) == MULT)
2832       || (GET_CODE (PATTERN (i3)) == SET
2833           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2834     have_mult = 1;
2835
2836   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2837      We used to do this EXCEPT in one case: I3 has a post-inc in an
2838      output operand.  However, that exception can give rise to insns like
2839         mov r3,(r3)+
2840      which is a famous insn on the PDP-11 where the value of r3 used as the
2841      source was model-dependent.  Avoid this sort of thing.  */
2842
2843 #if 0
2844   if (!(GET_CODE (PATTERN (i3)) == SET
2845         && REG_P (SET_SRC (PATTERN (i3)))
2846         && MEM_P (SET_DEST (PATTERN (i3)))
2847         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2848             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2849     /* It's not the exception.  */
2850 #endif
2851 #ifdef AUTO_INC_DEC
2852     {
2853       rtx link;
2854       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2855         if (REG_NOTE_KIND (link) == REG_INC
2856             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2857                 || (i1 != 0
2858                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2859           {
2860             undo_all ();
2861             return 0;
2862           }
2863     }
2864 #endif
2865
2866   /* See if the SETs in I1 or I2 need to be kept around in the merged
2867      instruction: whenever the value set there is still needed past I3.
2868      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2869
2870      For the SET in I1, we have two cases: if I1 and I2 independently feed
2871      into I3, the set in I1 needs to be kept around unless I1DEST dies
2872      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2873      in I1 needs to be kept around unless I1DEST dies or is set in either
2874      I2 or I3.  The same considerations apply to I0.  */
2875
2876   added_sets_2 = !dead_or_set_p (i3, i2dest);
2877
2878   if (i1)
2879     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2880                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2881   else
2882     added_sets_1 = 0;
2883
2884   if (i0)
2885     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2886                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2887                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2888                           && dead_or_set_p (i2, i0dest)));
2889   else
2890     added_sets_0 = 0;
2891
2892   /* We are about to copy insns for the case where they need to be kept
2893      around.  Check that they can be copied in the merged instruction.  */
2894
2895   if (targetm.cannot_copy_insn_p
2896       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2897           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2898           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2899     {
2900       undo_all ();
2901       return 0;
2902     }
2903
2904   /* If the set in I2 needs to be kept around, we must make a copy of
2905      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2906      PATTERN (I2), we are only substituting for the original I1DEST, not into
2907      an already-substituted copy.  This also prevents making self-referential
2908      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2909      I2DEST.  */
2910
2911   if (added_sets_2)
2912     {
2913       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2914         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2915       else
2916         i2pat = copy_rtx (PATTERN (i2));
2917     }
2918
2919   if (added_sets_1)
2920     {
2921       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2922         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2923       else
2924         i1pat = copy_rtx (PATTERN (i1));
2925     }
2926
2927   if (added_sets_0)
2928     {
2929       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2930         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2931       else
2932         i0pat = copy_rtx (PATTERN (i0));
2933     }
2934
2935   combine_merges++;
2936
2937   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2938
2939   maxreg = max_reg_num ();
2940
2941   subst_insn = i3;
2942
2943 #ifndef HAVE_cc0
2944   /* Many machines that don't use CC0 have insns that can both perform an
2945      arithmetic operation and set the condition code.  These operations will
2946      be represented as a PARALLEL with the first element of the vector
2947      being a COMPARE of an arithmetic operation with the constant zero.
2948      The second element of the vector will set some pseudo to the result
2949      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2950      match such a pattern and so will generate an extra insn.   Here we test
2951      for this case, where both the comparison and the operation result are
2952      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2953      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2954
2955   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2956       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2957       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2958       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2959     {
2960       rtx newpat_dest;
2961       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2962       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2963       enum machine_mode compare_mode, orig_compare_mode;
2964       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2965
2966       newpat = PATTERN (i3);
2967       newpat_dest = SET_DEST (newpat);
2968       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2969
2970       if (undobuf.other_insn == 0
2971           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2972                                             &cc_use_insn)))
2973         {
2974           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2975           compare_code = simplify_compare_const (compare_code,
2976                                                  GET_MODE (i2dest), op0, &op1);
2977           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2978         }
2979
2980       /* Do the rest only if op1 is const0_rtx, which may be the
2981          result of simplification.  */
2982       if (op1 == const0_rtx)
2983         {
2984           /* If a single use of the CC is found, prepare to modify it
2985              when SELECT_CC_MODE returns a new CC-class mode, or when
2986              the above simplify_compare_const() returned a new comparison
2987              operator.  undobuf.other_insn is assigned the CC use insn
2988              when modifying it.  */
2989           if (cc_use_loc)
2990             {
2991 #ifdef SELECT_CC_MODE
2992               enum machine_mode new_mode
2993                 = SELECT_CC_MODE (compare_code, op0, op1);
2994               if (new_mode != orig_compare_mode
2995                   && can_change_dest_mode (SET_DEST (newpat),
2996                                            added_sets_2, new_mode))
2997                 {
2998                   unsigned int regno = REGNO (newpat_dest);
2999                   compare_mode = new_mode;
3000                   if (regno < FIRST_PSEUDO_REGISTER)
3001                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3002                   else
3003                     {
3004                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3005                       newpat_dest = regno_reg_rtx[regno];
3006                     }
3007                 }
3008 #endif
3009               /* Cases for modifying the CC-using comparison.  */
3010               if (compare_code != orig_compare_code
3011                   /* ??? Do we need to verify the zero rtx?  */
3012                   && XEXP (*cc_use_loc, 1) == const0_rtx)
3013                 {
3014                   /* Replace cc_use_loc with entire new RTX.  */
3015                   SUBST (*cc_use_loc,
3016                          gen_rtx_fmt_ee (compare_code, compare_mode,
3017                                          newpat_dest, const0_rtx));
3018                   undobuf.other_insn = cc_use_insn;
3019                 }
3020               else if (compare_mode != orig_compare_mode)
3021                 {
3022                   /* Just replace the CC reg with a new mode.  */
3023                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3024                   undobuf.other_insn = cc_use_insn;
3025                 }
3026             }
3027
3028           /* Now we modify the current newpat:
3029              First, SET_DEST(newpat) is updated if the CC mode has been
3030              altered. For targets without SELECT_CC_MODE, this should be
3031              optimized away.  */
3032           if (compare_mode != orig_compare_mode)
3033             SUBST (SET_DEST (newpat), newpat_dest);
3034           /* This is always done to propagate i2src into newpat.  */
3035           SUBST (SET_SRC (newpat),
3036                  gen_rtx_COMPARE (compare_mode, op0, op1));
3037           /* Create new version of i2pat if needed; the below PARALLEL
3038              creation needs this to work correctly.  */
3039           if (! rtx_equal_p (i2src, op0))
3040             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3041           i2_is_used = 1;
3042         }
3043     }
3044 #endif
3045
3046   if (i2_is_used == 0)
3047     {
3048       /* It is possible that the source of I2 or I1 may be performing
3049          an unneeded operation, such as a ZERO_EXTEND of something
3050          that is known to have the high part zero.  Handle that case
3051          by letting subst look at the inner insns.
3052
3053          Another way to do this would be to have a function that tries
3054          to simplify a single insn instead of merging two or more
3055          insns.  We don't do this because of the potential of infinite
3056          loops and because of the potential extra memory required.
3057          However, doing it the way we are is a bit of a kludge and
3058          doesn't catch all cases.
3059
3060          But only do this if -fexpensive-optimizations since it slows
3061          things down and doesn't usually win.
3062
3063          This is not done in the COMPARE case above because the
3064          unmodified I2PAT is used in the PARALLEL and so a pattern
3065          with a modified I2SRC would not match.  */
3066
3067       if (flag_expensive_optimizations)
3068         {
3069           /* Pass pc_rtx so no substitutions are done, just
3070              simplifications.  */
3071           if (i1)
3072             {
3073               subst_low_luid = DF_INSN_LUID (i1);
3074               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3075             }
3076
3077           subst_low_luid = DF_INSN_LUID (i2);
3078           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3079         }
3080
3081       n_occurrences = 0;                /* `subst' counts here */
3082       subst_low_luid = DF_INSN_LUID (i2);
3083
3084       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3085          copy of I2SRC each time we substitute it, in order to avoid creating
3086          self-referential RTL when we will be substituting I1SRC for I1DEST
3087          later.  Likewise if I0 feeds into I2, either directly or indirectly
3088          through I1, and I0DEST is in I0SRC.  */
3089       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3090                       (i1_feeds_i2_n && i1dest_in_i1src)
3091                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3092                           && i0dest_in_i0src));
3093       substed_i2 = 1;
3094
3095       /* Record whether I2's body now appears within I3's body.  */
3096       i2_is_used = n_occurrences;
3097     }
3098
3099   /* If we already got a failure, don't try to do more.  Otherwise, try to
3100      substitute I1 if we have it.  */
3101
3102   if (i1 && GET_CODE (newpat) != CLOBBER)
3103     {
3104       /* Check that an autoincrement side-effect on I1 has not been lost.
3105          This happens if I1DEST is mentioned in I2 and dies there, and
3106          has disappeared from the new pattern.  */
3107       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3108            && i1_feeds_i2_n
3109            && dead_or_set_p (i2, i1dest)
3110            && !reg_overlap_mentioned_p (i1dest, newpat))
3111            /* Before we can do this substitution, we must redo the test done
3112               above (see detailed comments there) that ensures I1DEST isn't
3113               mentioned in any SETs in NEWPAT that are field assignments.  */
3114           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3115                                 0, 0, 0))
3116         {
3117           undo_all ();
3118           return 0;
3119         }
3120
3121       n_occurrences = 0;
3122       subst_low_luid = DF_INSN_LUID (i1);
3123
3124       /* If the following substitution will modify I1SRC, make a copy of it
3125          for the case where it is substituted for I1DEST in I2PAT later.  */
3126       if (added_sets_2 && i1_feeds_i2_n)
3127         i1src_copy = copy_rtx (i1src);
3128
3129       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3130          copy of I1SRC each time we substitute it, in order to avoid creating
3131          self-referential RTL when we will be substituting I0SRC for I0DEST
3132          later.  */
3133       newpat = subst (newpat, i1dest, i1src, 0, 0,
3134                       i0_feeds_i1_n && i0dest_in_i0src);
3135       substed_i1 = 1;
3136
3137       /* Record whether I1's body now appears within I3's body.  */
3138       i1_is_used = n_occurrences;
3139     }
3140
3141   /* Likewise for I0 if we have it.  */
3142
3143   if (i0 && GET_CODE (newpat) != CLOBBER)
3144     {
3145       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3146            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3147                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3148            && !reg_overlap_mentioned_p (i0dest, newpat))
3149           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3150                                 0, 0, 0))
3151         {
3152           undo_all ();
3153           return 0;
3154         }
3155
3156       /* If the following substitution will modify I0SRC, make a copy of it
3157          for the case where it is substituted for I0DEST in I1PAT later.  */
3158       if (added_sets_1 && i0_feeds_i1_n)
3159         i0src_copy = copy_rtx (i0src);
3160       /* And a copy for I0DEST in I2PAT substitution.  */
3161       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3162                            || (i0_feeds_i2_n)))
3163         i0src_copy2 = copy_rtx (i0src);
3164
3165       n_occurrences = 0;
3166       subst_low_luid = DF_INSN_LUID (i0);
3167       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3168       substed_i0 = 1;
3169     }
3170
3171   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3172      to count all the ways that I2SRC and I1SRC can be used.  */
3173   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3174        && i2_is_used + added_sets_2 > 1)
3175       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3176           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3177               > 1))
3178       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3179           && (n_occurrences + added_sets_0
3180               + (added_sets_1 && i0_feeds_i1_n)
3181               + (added_sets_2 && i0_feeds_i2_n)
3182               > 1))
3183       /* Fail if we tried to make a new register.  */
3184       || max_reg_num () != maxreg
3185       /* Fail if we couldn't do something and have a CLOBBER.  */
3186       || GET_CODE (newpat) == CLOBBER
3187       /* Fail if this new pattern is a MULT and we didn't have one before
3188          at the outer level.  */
3189       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3190           && ! have_mult))
3191     {
3192       undo_all ();
3193       return 0;
3194     }
3195
3196   /* If the actions of the earlier insns must be kept
3197      in addition to substituting them into the latest one,
3198      we must make a new PARALLEL for the latest insn
3199      to hold additional the SETs.  */
3200
3201   if (added_sets_0 || added_sets_1 || added_sets_2)
3202     {
3203       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3204       combine_extras++;
3205
3206       if (GET_CODE (newpat) == PARALLEL)
3207         {
3208           rtvec old = XVEC (newpat, 0);
3209           total_sets = XVECLEN (newpat, 0) + extra_sets;
3210           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3211           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3212                   sizeof (old->elem[0]) * old->num_elem);
3213         }
3214       else
3215         {
3216           rtx old = newpat;
3217           total_sets = 1 + extra_sets;
3218           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3219           XVECEXP (newpat, 0, 0) = old;
3220         }
3221
3222       if (added_sets_0)
3223         XVECEXP (newpat, 0, --total_sets) = i0pat;
3224
3225       if (added_sets_1)
3226         {
3227           rtx t = i1pat;
3228           if (i0_feeds_i1_n)
3229             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3230
3231           XVECEXP (newpat, 0, --total_sets) = t;
3232         }
3233       if (added_sets_2)
3234         {
3235           rtx t = i2pat;
3236           if (i1_feeds_i2_n)
3237             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3238                        i0_feeds_i1_n && i0dest_in_i0src);
3239           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3240             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3241
3242           XVECEXP (newpat, 0, --total_sets) = t;
3243         }
3244     }
3245
3246  validate_replacement:
3247
3248   /* Note which hard regs this insn has as inputs.  */
3249   mark_used_regs_combine (newpat);
3250
3251   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3252      consider splitting this pattern, we might need these clobbers.  */
3253   if (i1 && GET_CODE (newpat) == PARALLEL
3254       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3255     {
3256       int len = XVECLEN (newpat, 0);
3257
3258       newpat_vec_with_clobbers = rtvec_alloc (len);
3259       for (i = 0; i < len; i++)
3260         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3261     }
3262
3263   /* Is the result of combination a valid instruction?  */
3264   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3265
3266   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3267      the second SET's destination is a register that is unused and isn't
3268      marked as an instruction that might trap in an EH region.  In that case,
3269      we just need the first SET.   This can occur when simplifying a divmod
3270      insn.  We *must* test for this case here because the code below that
3271      splits two independent SETs doesn't handle this case correctly when it
3272      updates the register status.
3273
3274      It's pointless doing this if we originally had two sets, one from
3275      i3, and one from i2.  Combining then splitting the parallel results
3276      in the original i2 again plus an invalid insn (which we delete).
3277      The net effect is only to move instructions around, which makes
3278      debug info less accurate.
3279
3280      Also check the case where the first SET's destination is unused.
3281      That would not cause incorrect code, but does cause an unneeded
3282      insn to remain.  */
3283
3284   if (insn_code_number < 0
3285       && !(added_sets_2 && i1 == 0)
3286       && GET_CODE (newpat) == PARALLEL
3287       && XVECLEN (newpat, 0) == 2
3288       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3289       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3290       && asm_noperands (newpat) < 0)
3291     {
3292       rtx set0 = XVECEXP (newpat, 0, 0);
3293       rtx set1 = XVECEXP (newpat, 0, 1);
3294
3295       if (((REG_P (SET_DEST (set1))
3296             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3297            || (GET_CODE (SET_DEST (set1)) == SUBREG
3298                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3299           && insn_nothrow_p (i3)
3300           && !side_effects_p (SET_SRC (set1)))
3301         {
3302           newpat = set0;
3303           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3304         }
3305
3306       else if (((REG_P (SET_DEST (set0))
3307                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3308                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3309                     && find_reg_note (i3, REG_UNUSED,
3310                                       SUBREG_REG (SET_DEST (set0)))))
3311                && insn_nothrow_p (i3)
3312                && !side_effects_p (SET_SRC (set0)))
3313         {
3314           newpat = set1;
3315           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3316
3317           if (insn_code_number >= 0)
3318             changed_i3_dest = 1;
3319         }
3320     }
3321
3322   /* If we were combining three insns and the result is a simple SET
3323      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3324      insns.  There are two ways to do this.  It can be split using a
3325      machine-specific method (like when you have an addition of a large
3326      constant) or by combine in the function find_split_point.  */
3327
3328   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3329       && asm_noperands (newpat) < 0)
3330     {
3331       rtx parallel, m_split, *split;
3332
3333       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3334          use I2DEST as a scratch register will help.  In the latter case,
3335          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3336
3337       m_split = combine_split_insns (newpat, i3);
3338
3339       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3340          inputs of NEWPAT.  */
3341
3342       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3343          possible to try that as a scratch reg.  This would require adding
3344          more code to make it work though.  */
3345
3346       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3347         {
3348           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3349
3350           /* First try to split using the original register as a
3351              scratch register.  */
3352           parallel = gen_rtx_PARALLEL (VOIDmode,
3353                                        gen_rtvec (2, newpat,
3354                                                   gen_rtx_CLOBBER (VOIDmode,
3355                                                                    i2dest)));
3356           m_split = combine_split_insns (parallel, i3);
3357
3358           /* If that didn't work, try changing the mode of I2DEST if
3359              we can.  */
3360           if (m_split == 0
3361               && new_mode != GET_MODE (i2dest)
3362               && new_mode != VOIDmode
3363               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3364             {
3365               enum machine_mode old_mode = GET_MODE (i2dest);
3366               rtx ni2dest;
3367
3368               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3369                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3370               else
3371                 {
3372                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3373                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3374                 }
3375
3376               parallel = (gen_rtx_PARALLEL
3377                           (VOIDmode,
3378                            gen_rtvec (2, newpat,
3379                                       gen_rtx_CLOBBER (VOIDmode,
3380                                                        ni2dest))));
3381               m_split = combine_split_insns (parallel, i3);
3382
3383               if (m_split == 0
3384                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3385                 {
3386                   struct undo *buf;
3387
3388                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3389                   buf = undobuf.undos;
3390                   undobuf.undos = buf->next;
3391                   buf->next = undobuf.frees;
3392                   undobuf.frees = buf;
3393                 }
3394             }
3395
3396           i2scratch = m_split != 0;
3397         }
3398
3399       /* If recog_for_combine has discarded clobbers, try to use them
3400          again for the split.  */
3401       if (m_split == 0 && newpat_vec_with_clobbers)
3402         {
3403           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3404           m_split = combine_split_insns (parallel, i3);
3405         }
3406
3407       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3408         {
3409           m_split = PATTERN (m_split);
3410           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3411           if (insn_code_number >= 0)
3412             newpat = m_split;
3413         }
3414       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3415                && (next_nonnote_nondebug_insn (i2) == i3
3416                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3417         {
3418           rtx i2set, i3set;
3419           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3420           newi2pat = PATTERN (m_split);
3421
3422           i3set = single_set (NEXT_INSN (m_split));
3423           i2set = single_set (m_split);
3424
3425           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3426
3427           /* If I2 or I3 has multiple SETs, we won't know how to track
3428              register status, so don't use these insns.  If I2's destination
3429              is used between I2 and I3, we also can't use these insns.  */
3430
3431           if (i2_code_number >= 0 && i2set && i3set
3432               && (next_nonnote_nondebug_insn (i2) == i3
3433                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3434             insn_code_number = recog_for_combine (&newi3pat, i3,
3435                                                   &new_i3_notes);
3436           if (insn_code_number >= 0)
3437             newpat = newi3pat;
3438
3439           /* It is possible that both insns now set the destination of I3.
3440              If so, we must show an extra use of it.  */
3441
3442           if (insn_code_number >= 0)
3443             {
3444               rtx new_i3_dest = SET_DEST (i3set);
3445               rtx new_i2_dest = SET_DEST (i2set);
3446
3447               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3448                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3449                      || GET_CODE (new_i3_dest) == SUBREG)
3450                 new_i3_dest = XEXP (new_i3_dest, 0);
3451
3452               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3453                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3454                      || GET_CODE (new_i2_dest) == SUBREG)
3455                 new_i2_dest = XEXP (new_i2_dest, 0);
3456
3457               if (REG_P (new_i3_dest)
3458                   && REG_P (new_i2_dest)
3459                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3460                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3461             }
3462         }
3463
3464       /* If we can split it and use I2DEST, go ahead and see if that
3465          helps things be recognized.  Verify that none of the registers
3466          are set between I2 and I3.  */
3467       if (insn_code_number < 0
3468           && (split = find_split_point (&newpat, i3, false)) != 0
3469 #ifdef HAVE_cc0
3470           && REG_P (i2dest)
3471 #endif
3472           /* We need I2DEST in the proper mode.  If it is a hard register
3473              or the only use of a pseudo, we can change its mode.
3474              Make sure we don't change a hard register to have a mode that
3475              isn't valid for it, or change the number of registers.  */
3476           && (GET_MODE (*split) == GET_MODE (i2dest)
3477               || GET_MODE (*split) == VOIDmode
3478               || can_change_dest_mode (i2dest, added_sets_2,
3479                                        GET_MODE (*split)))
3480           && (next_nonnote_nondebug_insn (i2) == i3
3481               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3482           /* We can't overwrite I2DEST if its value is still used by
3483              NEWPAT.  */
3484           && ! reg_referenced_p (i2dest, newpat))
3485         {
3486           rtx newdest = i2dest;
3487           enum rtx_code split_code = GET_CODE (*split);
3488           enum machine_mode split_mode = GET_MODE (*split);
3489           bool subst_done = false;
3490           newi2pat = NULL_RTX;
3491
3492           i2scratch = true;
3493
3494           /* *SPLIT may be part of I2SRC, so make sure we have the
3495              original expression around for later debug processing.
3496              We should not need I2SRC any more in other cases.  */
3497           if (MAY_HAVE_DEBUG_INSNS)
3498             i2src = copy_rtx (i2src);
3499           else
3500             i2src = NULL;
3501
3502           /* Get NEWDEST as a register in the proper mode.  We have already
3503              validated that we can do this.  */
3504           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3505             {
3506               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3507                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3508               else
3509                 {
3510                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3511                   newdest = regno_reg_rtx[REGNO (i2dest)];
3512                 }
3513             }
3514
3515           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3516              an ASHIFT.  This can occur if it was inside a PLUS and hence
3517              appeared to be a memory address.  This is a kludge.  */
3518           if (split_code == MULT
3519               && CONST_INT_P (XEXP (*split, 1))
3520               && INTVAL (XEXP (*split, 1)) > 0
3521               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3522             {
3523               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3524                                              XEXP (*split, 0), GEN_INT (i)));
3525               /* Update split_code because we may not have a multiply
3526                  anymore.  */
3527               split_code = GET_CODE (*split);
3528             }
3529
3530 #ifdef INSN_SCHEDULING
3531           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3532              be written as a ZERO_EXTEND.  */
3533           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3534             {
3535 #ifdef LOAD_EXTEND_OP
3536               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3537                  what it really is.  */
3538               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3539                   == SIGN_EXTEND)
3540                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3541                                                     SUBREG_REG (*split)));
3542               else
3543 #endif
3544                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3545                                                     SUBREG_REG (*split)));
3546             }
3547 #endif
3548
3549           /* Attempt to split binary operators using arithmetic identities.  */
3550           if (BINARY_P (SET_SRC (newpat))
3551               && split_mode == GET_MODE (SET_SRC (newpat))
3552               && ! side_effects_p (SET_SRC (newpat)))
3553             {
3554               rtx setsrc = SET_SRC (newpat);
3555               enum machine_mode mode = GET_MODE (setsrc);
3556               enum rtx_code code = GET_CODE (setsrc);
3557               rtx src_op0 = XEXP (setsrc, 0);
3558               rtx src_op1 = XEXP (setsrc, 1);
3559
3560               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3561               if (rtx_equal_p (src_op0, src_op1))
3562                 {
3563                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3564                   SUBST (XEXP (setsrc, 0), newdest);
3565                   SUBST (XEXP (setsrc, 1), newdest);
3566                   subst_done = true;
3567                 }
3568               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3569               else if ((code == PLUS || code == MULT)
3570                        && GET_CODE (src_op0) == code
3571                        && GET_CODE (XEXP (src_op0, 0)) == code
3572                        && (INTEGRAL_MODE_P (mode)
3573                            || (FLOAT_MODE_P (mode)
3574                                && flag_unsafe_math_optimizations)))
3575                 {
3576                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3577                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3578                   rtx r = XEXP (src_op0, 1);
3579                   rtx s = src_op1;
3580
3581                   /* Split both "((X op Y) op X) op Y" and
3582                      "((X op Y) op Y) op X" as "T op T" where T is
3583                      "X op Y".  */
3584                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3585                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3586                     {
3587                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3588                                               XEXP (src_op0, 0));
3589                       SUBST (XEXP (setsrc, 0), newdest);
3590                       SUBST (XEXP (setsrc, 1), newdest);
3591                       subst_done = true;
3592                     }
3593                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3594                      T is "X op Y".  */
3595                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3596                     {
3597                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3598                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3599                       SUBST (XEXP (setsrc, 0), newdest);
3600                       SUBST (XEXP (setsrc, 1), newdest);
3601                       subst_done = true;
3602                     }
3603                 }
3604             }
3605
3606           if (!subst_done)
3607             {
3608               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3609               SUBST (*split, newdest);
3610             }
3611
3612           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3613
3614           /* recog_for_combine might have added CLOBBERs to newi2pat.
3615              Make sure NEWPAT does not depend on the clobbered regs.  */
3616           if (GET_CODE (newi2pat) == PARALLEL)
3617             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3618               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3619                 {
3620                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3621                   if (reg_overlap_mentioned_p (reg, newpat))
3622                     {
3623                       undo_all ();
3624                       return 0;
3625                     }
3626                 }
3627
3628           /* If the split point was a MULT and we didn't have one before,
3629              don't use one now.  */
3630           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3631             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3632         }
3633     }
3634
3635   /* Check for a case where we loaded from memory in a narrow mode and
3636      then sign extended it, but we need both registers.  In that case,
3637      we have a PARALLEL with both loads from the same memory location.
3638      We can split this into a load from memory followed by a register-register
3639      copy.  This saves at least one insn, more if register allocation can
3640      eliminate the copy.
3641
3642      We cannot do this if the destination of the first assignment is a
3643      condition code register or cc0.  We eliminate this case by making sure
3644      the SET_DEST and SET_SRC have the same mode.
3645
3646      We cannot do this if the destination of the second assignment is
3647      a register that we have already assumed is zero-extended.  Similarly
3648      for a SUBREG of such a register.  */
3649
3650   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3651            && GET_CODE (newpat) == PARALLEL
3652            && XVECLEN (newpat, 0) == 2
3653            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3654            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3655            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3656                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3657            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3658            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3659                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3660            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3661                                    DF_INSN_LUID (i2))
3662            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3663            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3664            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3665                  (REG_P (temp)
3666                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3667                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3668                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3669                   && (reg_stat[REGNO (temp)].nonzero_bits
3670                       != GET_MODE_MASK (word_mode))))
3671            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3672                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3673                      (REG_P (temp)
3674                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3675                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3676                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3677                       && (reg_stat[REGNO (temp)].nonzero_bits
3678                           != GET_MODE_MASK (word_mode)))))
3679            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3680                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3681            && ! find_reg_note (i3, REG_UNUSED,
3682                                SET_DEST (XVECEXP (newpat, 0, 0))))
3683     {
3684       rtx ni2dest;
3685
3686       newi2pat = XVECEXP (newpat, 0, 0);
3687       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3688       newpat = XVECEXP (newpat, 0, 1);
3689       SUBST (SET_SRC (newpat),
3690              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3691       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3692
3693       if (i2_code_number >= 0)
3694         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3695
3696       if (insn_code_number >= 0)
3697         swap_i2i3 = 1;
3698     }
3699
3700   /* Similarly, check for a case where we have a PARALLEL of two independent
3701      SETs but we started with three insns.  In this case, we can do the sets
3702      as two separate insns.  This case occurs when some SET allows two
3703      other insns to combine, but the destination of that SET is still live.  */
3704
3705   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3706            && GET_CODE (newpat) == PARALLEL
3707            && XVECLEN (newpat, 0) == 2
3708            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3709            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3710            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3711            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3712            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3713            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3714            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3715                                   XVECEXP (newpat, 0, 0))
3716            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3717                                   XVECEXP (newpat, 0, 1))
3718            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3719                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3720     {
3721       rtx set0 = XVECEXP (newpat, 0, 0);
3722       rtx set1 = XVECEXP (newpat, 0, 1);
3723
3724       /* Normally, it doesn't matter which of the two is done first,
3725          but the one that references cc0 can't be the second, and
3726          one which uses any regs/memory set in between i2 and i3 can't
3727          be first.  The PARALLEL might also have been pre-existing in i3,
3728          so we need to make sure that we won't wrongly hoist a SET to i2
3729          that would conflict with a death note present in there.  */
3730       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3731           && !(REG_P (SET_DEST (set1))
3732                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3733           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3734                && find_reg_note (i2, REG_DEAD,
3735                                  SUBREG_REG (SET_DEST (set1))))
3736 #ifdef HAVE_cc0
3737           && !reg_referenced_p (cc0_rtx, set0)
3738 #endif
3739           /* If I3 is a jump, ensure that set0 is a jump so that
3740              we do not create invalid RTL.  */
3741           && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
3742          )
3743         {
3744           newi2pat = set1;
3745           newpat = set0;
3746         }
3747       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3748                && !(REG_P (SET_DEST (set0))
3749                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3750                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3751                     && find_reg_note (i2, REG_DEAD,
3752                                       SUBREG_REG (SET_DEST (set0))))
3753 #ifdef HAVE_cc0
3754                && !reg_referenced_p (cc0_rtx, set1)
3755 #endif
3756                /* If I3 is a jump, ensure that set1 is a jump so that
3757                   we do not create invalid RTL.  */
3758                && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
3759               )
3760         {
3761           newi2pat = set0;
3762           newpat = set1;
3763         }
3764       else
3765         {
3766           undo_all ();
3767           return 0;
3768         }
3769
3770       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3771
3772       if (i2_code_number >= 0)
3773         {
3774           /* recog_for_combine might have added CLOBBERs to newi2pat.
3775              Make sure NEWPAT does not depend on the clobbered regs.  */
3776           if (GET_CODE (newi2pat) == PARALLEL)
3777             {
3778               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3779                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3780                   {
3781                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3782                     if (reg_overlap_mentioned_p (reg, newpat))
3783                       {
3784                         undo_all ();
3785                         return 0;
3786                       }
3787                   }
3788             }
3789
3790           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3791         }
3792     }
3793
3794   /* If it still isn't recognized, fail and change things back the way they
3795      were.  */
3796   if ((insn_code_number < 0
3797        /* Is the result a reasonable ASM_OPERANDS?  */
3798        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3799     {
3800       undo_all ();
3801       return 0;
3802     }
3803
3804   /* If we had to change another insn, make sure it is valid also.  */
3805   if (undobuf.other_insn)
3806     {
3807       CLEAR_HARD_REG_SET (newpat_used_regs);
3808
3809       other_pat = PATTERN (undobuf.other_insn);
3810       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3811                                              &new_other_notes);
3812
3813       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3814         {
3815           undo_all ();
3816           return 0;
3817         }
3818     }
3819
3820 #ifdef HAVE_cc0
3821   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3822      they are adjacent to each other or not.  */
3823   {
3824     rtx p = prev_nonnote_insn (i3);
3825     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3826         && sets_cc0_p (newi2pat))
3827       {
3828         undo_all ();
3829         return 0;
3830       }
3831   }
3832 #endif
3833
3834   /* Only allow this combination if insn_rtx_costs reports that the
3835      replacement instructions are cheaper than the originals.  */
3836   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3837     {
3838       undo_all ();
3839       return 0;
3840     }
3841
3842   if (MAY_HAVE_DEBUG_INSNS)
3843     {
3844       struct undo *undo;
3845
3846       for (undo = undobuf.undos; undo; undo = undo->next)
3847         if (undo->kind == UNDO_MODE)
3848           {
3849             rtx reg = *undo->where.r;
3850             enum machine_mode new_mode = GET_MODE (reg);
3851             enum machine_mode old_mode = undo->old_contents.m;
3852
3853             /* Temporarily revert mode back.  */
3854             adjust_reg_mode (reg, old_mode);
3855
3856             if (reg == i2dest && i2scratch)
3857               {
3858                 /* If we used i2dest as a scratch register with a
3859                    different mode, substitute it for the original
3860                    i2src while its original mode is temporarily
3861                    restored, and then clear i2scratch so that we don't
3862                    do it again later.  */
3863                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3864                                      this_basic_block);
3865                 i2scratch = false;
3866                 /* Put back the new mode.  */
3867                 adjust_reg_mode (reg, new_mode);
3868               }
3869             else
3870               {
3871                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3872                 rtx first, last;
3873
3874                 if (reg == i2dest)
3875                   {
3876                     first = i2;
3877                     last = last_combined_insn;
3878                   }
3879                 else
3880                   {
3881                     first = i3;
3882                     last = undobuf.other_insn;
3883                     gcc_assert (last);
3884                     if (DF_INSN_LUID (last)
3885                         < DF_INSN_LUID (last_combined_insn))
3886                       last = last_combined_insn;
3887                   }
3888
3889                 /* We're dealing with a reg that changed mode but not
3890                    meaning, so we want to turn it into a subreg for
3891                    the new mode.  However, because of REG sharing and
3892                    because its mode had already changed, we have to do
3893                    it in two steps.  First, replace any debug uses of
3894                    reg, with its original mode temporarily restored,
3895                    with this copy we have created; then, replace the
3896                    copy with the SUBREG of the original shared reg,
3897                    once again changed to the new mode.  */
3898                 propagate_for_debug (first, last, reg, tempreg,
3899                                      this_basic_block);
3900                 adjust_reg_mode (reg, new_mode);
3901                 propagate_for_debug (first, last, tempreg,
3902                                      lowpart_subreg (old_mode, reg, new_mode),
3903                                      this_basic_block);
3904               }
3905           }
3906     }
3907
3908   /* If we will be able to accept this, we have made a
3909      change to the destination of I3.  This requires us to
3910      do a few adjustments.  */
3911
3912   if (changed_i3_dest)
3913     {
3914       PATTERN (i3) = newpat;
3915       adjust_for_new_dest (i3);
3916     }
3917
3918   /* We now know that we can do this combination.  Merge the insns and
3919      update the status of registers and LOG_LINKS.  */
3920
3921   if (undobuf.other_insn)
3922     {
3923       rtx note, next;
3924
3925       PATTERN (undobuf.other_insn) = other_pat;
3926
3927       /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3928          ensure that they are still valid.  Then add any non-duplicate
3929          notes added by recog_for_combine.  */
3930       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3931         {
3932           next = XEXP (note, 1);
3933
3934           if ((REG_NOTE_KIND (note) == REG_DEAD
3935                && !reg_referenced_p (XEXP (note, 0),
3936                                      PATTERN (undobuf.other_insn)))
3937               ||(REG_NOTE_KIND (note) == REG_UNUSED
3938                  && !reg_set_p (XEXP (note, 0),
3939                                 PATTERN (undobuf.other_insn))))
3940             remove_note (undobuf.other_insn, note);
3941         }
3942
3943       distribute_notes (new_other_notes, undobuf.other_insn,
3944                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3945                         NULL_RTX);
3946     }
3947
3948   if (swap_i2i3)
3949     {
3950       rtx insn;
3951       struct insn_link *link;
3952       rtx ni2dest;
3953
3954       /* I3 now uses what used to be its destination and which is now
3955          I2's destination.  This requires us to do a few adjustments.  */
3956       PATTERN (i3) = newpat;
3957       adjust_for_new_dest (i3);
3958
3959       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3960          so we still will.
3961
3962          However, some later insn might be using I2's dest and have
3963          a LOG_LINK pointing at I3.  We must remove this link.
3964          The simplest way to remove the link is to point it at I1,
3965          which we know will be a NOTE.  */
3966
3967       /* newi2pat is usually a SET here; however, recog_for_combine might
3968          have added some clobbers.  */
3969       if (GET_CODE (newi2pat) == PARALLEL)
3970         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3971       else
3972         ni2dest = SET_DEST (newi2pat);
3973
3974       for (insn = NEXT_INSN (i3);
3975            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
3976                     || insn != BB_HEAD (this_basic_block->next_bb));
3977            insn = NEXT_INSN (insn))
3978         {
3979           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3980             {
3981               FOR_EACH_LOG_LINK (link, insn)
3982                 if (link->insn == i3)
3983                   link->insn = i1;
3984
3985               break;
3986             }
3987         }
3988     }
3989
3990   {
3991     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3992     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3993     rtx midnotes = 0;
3994     int from_luid;
3995     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3996        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3997        same as i3dest, in which case newi2pat may be setting i1dest.  */
3998     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3999                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4000                    || !i2dest_killed
4001                    ? 0 : i2dest);
4002     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4003                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4004                    || !i1dest_killed
4005                    ? 0 : i1dest);
4006     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4007                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4008                    || !i0dest_killed
4009                    ? 0 : i0dest);
4010
4011     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4012        clear them.  */
4013     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4014     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4015     if (i1)
4016       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4017     if (i0)
4018       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4019
4020     /* Ensure that we do not have something that should not be shared but
4021        occurs multiple times in the new insns.  Check this by first
4022        resetting all the `used' flags and then copying anything is shared.  */
4023
4024     reset_used_flags (i3notes);
4025     reset_used_flags (i2notes);
4026     reset_used_flags (i1notes);
4027     reset_used_flags (i0notes);
4028     reset_used_flags (newpat);
4029     reset_used_flags (newi2pat);
4030     if (undobuf.other_insn)
4031       reset_used_flags (PATTERN (undobuf.other_insn));
4032
4033     i3notes = copy_rtx_if_shared (i3notes);
4034     i2notes = copy_rtx_if_shared (i2notes);
4035     i1notes = copy_rtx_if_shared (i1notes);
4036     i0notes = copy_rtx_if_shared (i0notes);
4037     newpat = copy_rtx_if_shared (newpat);
4038     newi2pat = copy_rtx_if_shared (newi2pat);
4039     if (undobuf.other_insn)
4040       reset_used_flags (PATTERN (undobuf.other_insn));
4041
4042     INSN_CODE (i3) = insn_code_number;
4043     PATTERN (i3) = newpat;
4044
4045     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4046       {
4047         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4048
4049         reset_used_flags (call_usage);
4050         call_usage = copy_rtx (call_usage);
4051
4052         if (substed_i2)
4053           {
4054             /* I2SRC must still be meaningful at this point.  Some splitting
4055                operations can invalidate I2SRC, but those operations do not
4056                apply to calls.  */
4057             gcc_assert (i2src);
4058             replace_rtx (call_usage, i2dest, i2src);
4059           }
4060
4061         if (substed_i1)
4062           replace_rtx (call_usage, i1dest, i1src);
4063         if (substed_i0)
4064           replace_rtx (call_usage, i0dest, i0src);
4065
4066         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4067       }
4068
4069     if (undobuf.other_insn)
4070       INSN_CODE (undobuf.other_insn) = other_code_number;
4071
4072     /* We had one special case above where I2 had more than one set and
4073        we replaced a destination of one of those sets with the destination
4074        of I3.  In that case, we have to update LOG_LINKS of insns later
4075        in this basic block.  Note that this (expensive) case is rare.
4076
4077        Also, in this case, we must pretend that all REG_NOTEs for I2
4078        actually came from I3, so that REG_UNUSED notes from I2 will be
4079        properly handled.  */
4080
4081     if (i3_subst_into_i2)
4082       {
4083         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4084           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4085                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4086               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4087               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4088               && ! find_reg_note (i2, REG_UNUSED,
4089                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4090             for (temp = NEXT_INSN (i2);
4091                  temp
4092                  && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4093                           || BB_HEAD (this_basic_block) != temp);
4094                  temp = NEXT_INSN (temp))
4095               if (temp != i3 && INSN_P (temp))
4096                 FOR_EACH_LOG_LINK (link, temp)
4097                   if (link->insn == i2)
4098                     link->insn = i3;
4099
4100         if (i3notes)
4101           {
4102             rtx link = i3notes;
4103             while (XEXP (link, 1))
4104               link = XEXP (link, 1);
4105             XEXP (link, 1) = i2notes;
4106           }
4107         else
4108           i3notes = i2notes;
4109         i2notes = 0;
4110       }
4111
4112     LOG_LINKS (i3) = NULL;
4113     REG_NOTES (i3) = 0;
4114     LOG_LINKS (i2) = NULL;
4115     REG_NOTES (i2) = 0;
4116
4117     if (newi2pat)
4118       {
4119         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4120           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4121                                this_basic_block);
4122         INSN_CODE (i2) = i2_code_number;
4123         PATTERN (i2) = newi2pat;
4124       }
4125     else
4126       {
4127         if (MAY_HAVE_DEBUG_INSNS && i2src)
4128           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4129                                this_basic_block);
4130         SET_INSN_DELETED (i2);
4131       }
4132
4133     if (i1)
4134       {
4135         LOG_LINKS (i1) = NULL;
4136         REG_NOTES (i1) = 0;
4137         if (MAY_HAVE_DEBUG_INSNS)
4138           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4139                                this_basic_block);
4140         SET_INSN_DELETED (i1);
4141       }
4142
4143     if (i0)
4144       {
4145         LOG_LINKS (i0) = NULL;
4146         REG_NOTES (i0) = 0;
4147         if (MAY_HAVE_DEBUG_INSNS)
4148           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4149                                this_basic_block);
4150         SET_INSN_DELETED (i0);
4151       }
4152
4153     /* Get death notes for everything that is now used in either I3 or
4154        I2 and used to die in a previous insn.  If we built two new
4155        patterns, move from I1 to I2 then I2 to I3 so that we get the
4156        proper movement on registers that I2 modifies.  */
4157
4158     if (i0)
4159       from_luid = DF_INSN_LUID (i0);
4160     else if (i1)
4161       from_luid = DF_INSN_LUID (i1);
4162     else
4163       from_luid = DF_INSN_LUID (i2);
4164     if (newi2pat)
4165       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4166     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4167
4168     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4169     if (i3notes)
4170       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4171                         elim_i2, elim_i1, elim_i0);
4172     if (i2notes)
4173       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4174                         elim_i2, elim_i1, elim_i0);
4175     if (i1notes)
4176       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4177                         elim_i2, elim_i1, elim_i0);
4178     if (i0notes)
4179       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4180                         elim_i2, elim_i1, elim_i0);
4181     if (midnotes)
4182       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4183                         elim_i2, elim_i1, elim_i0);
4184
4185     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4186        know these are REG_UNUSED and want them to go to the desired insn,
4187        so we always pass it as i3.  */
4188
4189     if (newi2pat && new_i2_notes)
4190       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4191                         NULL_RTX);
4192
4193     if (new_i3_notes)
4194       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4195                         NULL_RTX);
4196
4197     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4198        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4199        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4200        in that case, it might delete I2.  Similarly for I2 and I1.
4201        Show an additional death due to the REG_DEAD note we make here.  If
4202        we discard it in distribute_notes, we will decrement it again.  */
4203
4204     if (i3dest_killed)
4205       {
4206         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4207         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4208           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4209                             elim_i1, elim_i0);
4210         else
4211           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4212                             elim_i2, elim_i1, elim_i0);
4213       }
4214
4215     if (i2dest_in_i2src)
4216       {
4217         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4218         if (newi2pat && reg_set_p (i2dest, newi2pat))
4219           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4220                             NULL_RTX, NULL_RTX);
4221         else
4222           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4223                             NULL_RTX, NULL_RTX, NULL_RTX);
4224       }
4225
4226     if (i1dest_in_i1src)
4227       {
4228         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4229         if (newi2pat && reg_set_p (i1dest, newi2pat))
4230           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4231                             NULL_RTX, NULL_RTX);
4232         else
4233           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4234                             NULL_RTX, NULL_RTX, NULL_RTX);
4235       }
4236
4237     if (i0dest_in_i0src)
4238       {
4239         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4240         if (newi2pat && reg_set_p (i0dest, newi2pat))
4241           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4242                             NULL_RTX, NULL_RTX);
4243         else
4244           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4245                             NULL_RTX, NULL_RTX, NULL_RTX);
4246       }
4247
4248     distribute_links (i3links);
4249     distribute_links (i2links);
4250     distribute_links (i1links);
4251     distribute_links (i0links);
4252
4253     if (REG_P (i2dest))
4254       {
4255         struct insn_link *link;
4256         rtx i2_insn = 0, i2_val = 0, set;
4257
4258         /* The insn that used to set this register doesn't exist, and
4259            this life of the register may not exist either.  See if one of
4260            I3's links points to an insn that sets I2DEST.  If it does,
4261            that is now the last known value for I2DEST. If we don't update
4262            this and I2 set the register to a value that depended on its old
4263            contents, we will get confused.  If this insn is used, thing
4264            will be set correctly in combine_instructions.  */
4265         FOR_EACH_LOG_LINK (link, i3)
4266           if ((set = single_set (link->insn)) != 0
4267               && rtx_equal_p (i2dest, SET_DEST (set)))
4268             i2_insn = link->insn, i2_val = SET_SRC (set);
4269
4270         record_value_for_reg (i2dest, i2_insn, i2_val);
4271
4272         /* If the reg formerly set in I2 died only once and that was in I3,
4273            zero its use count so it won't make `reload' do any work.  */
4274         if (! added_sets_2
4275             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4276             && ! i2dest_in_i2src)
4277           INC_REG_N_SETS (REGNO (i2dest), -1);
4278       }
4279
4280     if (i1 && REG_P (i1dest))
4281       {
4282         struct insn_link *link;
4283         rtx i1_insn = 0, i1_val = 0, set;
4284
4285         FOR_EACH_LOG_LINK (link, i3)
4286           if ((set = single_set (link->insn)) != 0
4287               && rtx_equal_p (i1dest, SET_DEST (set)))
4288             i1_insn = link->insn, i1_val = SET_SRC (set);
4289
4290         record_value_for_reg (i1dest, i1_insn, i1_val);
4291
4292         if (! added_sets_1 && ! i1dest_in_i1src)
4293           INC_REG_N_SETS (REGNO (i1dest), -1);
4294       }
4295
4296     if (i0 && REG_P (i0dest))
4297       {
4298         struct insn_link *link;
4299         rtx i0_insn = 0, i0_val = 0, set;
4300
4301         FOR_EACH_LOG_LINK (link, i3)
4302           if ((set = single_set (link->insn)) != 0
4303               && rtx_equal_p (i0dest, SET_DEST (set)))
4304             i0_insn = link->insn, i0_val = SET_SRC (set);
4305
4306         record_value_for_reg (i0dest, i0_insn, i0_val);
4307
4308         if (! added_sets_0 && ! i0dest_in_i0src)
4309           INC_REG_N_SETS (REGNO (i0dest), -1);
4310       }
4311
4312     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4313        been made to this insn.  The order is important, because newi2pat
4314        can affect nonzero_bits of newpat.  */
4315     if (newi2pat)
4316       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4317     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4318   }
4319
4320   if (undobuf.other_insn != NULL_RTX)
4321     {
4322       if (dump_file)
4323         {
4324           fprintf (dump_file, "modifying other_insn ");
4325           dump_insn_slim (dump_file, undobuf.other_insn);
4326         }
4327       df_insn_rescan (undobuf.other_insn);
4328     }
4329
4330   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4331     {
4332       if (dump_file)
4333         {
4334           fprintf (dump_file, "modifying insn i0 ");
4335           dump_insn_slim (dump_file, i0);
4336         }
4337       df_insn_rescan (i0);
4338     }
4339
4340   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4341     {
4342       if (dump_file)
4343         {
4344           fprintf (dump_file, "modifying insn i1 ");
4345           dump_insn_slim (dump_file, i1);
4346         }
4347       df_insn_rescan (i1);
4348     }
4349
4350   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4351     {
4352       if (dump_file)
4353         {
4354           fprintf (dump_file, "modifying insn i2 ");
4355           dump_insn_slim (dump_file, i2);
4356         }
4357       df_insn_rescan (i2);
4358     }
4359
4360   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4361     {
4362       if (dump_file)
4363         {
4364           fprintf (dump_file, "modifying insn i3 ");
4365           dump_insn_slim (dump_file, i3);
4366         }
4367       df_insn_rescan (i3);
4368     }
4369
4370   /* Set new_direct_jump_p if a new return or simple jump instruction
4371      has been created.  Adjust the CFG accordingly.  */
4372   if (returnjump_p (i3) || any_uncondjump_p (i3))
4373     {
4374       *new_direct_jump_p = 1;
4375       mark_jump_label (PATTERN (i3), i3, 0);
4376       update_cfg_for_uncondjump (i3);
4377     }
4378
4379   if (undobuf.other_insn != NULL_RTX
4380       && (returnjump_p (undobuf.other_insn)
4381           || any_uncondjump_p (undobuf.other_insn)))
4382     {
4383       *new_direct_jump_p = 1;
4384       update_cfg_for_uncondjump (undobuf.other_insn);
4385     }
4386
4387   /* A noop might also need cleaning up of CFG, if it comes from the
4388      simplification of a jump.  */
4389   if (JUMP_P (i3)
4390       && GET_CODE (newpat) == SET
4391       && SET_SRC (newpat) == pc_rtx
4392       && SET_DEST (newpat) == pc_rtx)
4393     {
4394       *new_direct_jump_p = 1;
4395       update_cfg_for_uncondjump (i3);
4396     }
4397
4398   if (undobuf.other_insn != NULL_RTX
4399       && JUMP_P (undobuf.other_insn)
4400       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4401       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4402       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4403     {
4404       *new_direct_jump_p = 1;
4405       update_cfg_for_uncondjump (undobuf.other_insn);
4406     }
4407
4408   combine_successes++;
4409   undo_commit ();
4410
4411   if (added_links_insn
4412       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4413       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4414     return added_links_insn;
4415   else
4416     return newi2pat ? i2 : i3;
4417 }
4418 \f
4419 /* Undo all the modifications recorded in undobuf.  */
4420
4421 static void
4422 undo_all (void)
4423 {
4424   struct undo *undo, *next;
4425
4426   for (undo = undobuf.undos; undo; undo = next)
4427     {
4428       next = undo->next;
4429       switch (undo->kind)
4430         {
4431         case UNDO_RTX:
4432           *undo->where.r = undo->old_contents.r;
4433           break;
4434         case UNDO_INT:
4435           *undo->where.i = undo->old_contents.i;
4436           break;
4437         case UNDO_MODE:
4438           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4439           break;
4440         case UNDO_LINKS:
4441           *undo->where.l = undo->old_contents.l;
4442           break;
4443         default:
4444           gcc_unreachable ();
4445         }
4446
4447       undo->next = undobuf.frees;
4448       undobuf.frees = undo;
4449     }
4450
4451   undobuf.undos = 0;
4452 }
4453
4454 /* We've committed to accepting the changes we made.  Move all
4455    of the undos to the free list.  */
4456
4457 static void
4458 undo_commit (void)
4459 {
4460   struct undo *undo, *next;
4461
4462   for (undo = undobuf.undos; undo; undo = next)
4463     {
4464       next = undo->next;
4465       undo->next = undobuf.frees;
4466       undobuf.frees = undo;
4467     }
4468   undobuf.undos = 0;
4469 }
4470 \f
4471 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4472    where we have an arithmetic expression and return that point.  LOC will
4473    be inside INSN.
4474
4475    try_combine will call this function to see if an insn can be split into
4476    two insns.  */
4477
4478 static rtx *
4479 find_split_point (rtx *loc, rtx insn, bool set_src)
4480 {
4481   rtx x = *loc;
4482   enum rtx_code code = GET_CODE (x);
4483   rtx *split;
4484   unsigned HOST_WIDE_INT len = 0;
4485   HOST_WIDE_INT pos = 0;
4486   int unsignedp = 0;
4487   rtx inner = NULL_RTX;
4488
4489   /* First special-case some codes.  */
4490   switch (code)
4491     {
4492     case SUBREG:
4493 #ifdef INSN_SCHEDULING
4494       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4495          point.  */
4496       if (MEM_P (SUBREG_REG (x)))
4497         return loc;
4498 #endif
4499       return find_split_point (&SUBREG_REG (x), insn, false);
4500
4501     case MEM:
4502 #ifdef HAVE_lo_sum
4503       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4504          using LO_SUM and HIGH.  */
4505       if (GET_CODE (XEXP (x, 0)) == CONST
4506           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4507         {
4508           enum machine_mode address_mode = get_address_mode (x);
4509
4510           SUBST (XEXP (x, 0),
4511                  gen_rtx_LO_SUM (address_mode,
4512                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4513                                  XEXP (x, 0)));
4514           return &XEXP (XEXP (x, 0), 0);
4515         }
4516 #endif
4517
4518       /* If we have a PLUS whose second operand is a constant and the
4519          address is not valid, perhaps will can split it up using
4520          the machine-specific way to split large constants.  We use
4521          the first pseudo-reg (one of the virtual regs) as a placeholder;
4522          it will not remain in the result.  */
4523       if (GET_CODE (XEXP (x, 0)) == PLUS
4524           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4525           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4526                                             MEM_ADDR_SPACE (x)))
4527         {
4528           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4529           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4530                                                       XEXP (x, 0)),
4531                                          subst_insn);
4532
4533           /* This should have produced two insns, each of which sets our
4534              placeholder.  If the source of the second is a valid address,
4535              we can make put both sources together and make a split point
4536              in the middle.  */
4537
4538           if (seq
4539               && NEXT_INSN (seq) != NULL_RTX
4540               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4541               && NONJUMP_INSN_P (seq)
4542               && GET_CODE (PATTERN (seq)) == SET
4543               && SET_DEST (PATTERN (seq)) == reg
4544               && ! reg_mentioned_p (reg,
4545                                     SET_SRC (PATTERN (seq)))
4546               && NONJUMP_INSN_P (NEXT_INSN (seq))
4547               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4548               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4549               && memory_address_addr_space_p
4550                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4551                     MEM_ADDR_SPACE (x)))
4552             {
4553               rtx src1 = SET_SRC (PATTERN (seq));
4554               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4555
4556               /* Replace the placeholder in SRC2 with SRC1.  If we can
4557                  find where in SRC2 it was placed, that can become our
4558                  split point and we can replace this address with SRC2.
4559                  Just try two obvious places.  */
4560
4561               src2 = replace_rtx (src2, reg, src1);
4562               split = 0;
4563               if (XEXP (src2, 0) == src1)
4564                 split = &XEXP (src2, 0);
4565               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4566                        && XEXP (XEXP (src2, 0), 0) == src1)
4567                 split = &XEXP (XEXP (src2, 0), 0);
4568
4569               if (split)
4570                 {
4571                   SUBST (XEXP (x, 0), src2);
4572                   return split;
4573                 }
4574             }
4575
4576           /* If that didn't work, perhaps the first operand is complex and
4577              needs to be computed separately, so make a split point there.
4578              This will occur on machines that just support REG + CONST
4579              and have a constant moved through some previous computation.  */
4580
4581           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4582                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4583                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4584             return &XEXP (XEXP (x, 0), 0);
4585         }
4586
4587       /* If we have a PLUS whose first operand is complex, try computing it
4588          separately by making a split there.  */
4589       if (GET_CODE (XEXP (x, 0)) == PLUS
4590           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4591                                             MEM_ADDR_SPACE (x))
4592           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4593           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4594                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4595         return &XEXP (XEXP (x, 0), 0);
4596       break;
4597
4598     case SET:
4599 #ifdef HAVE_cc0
4600       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4601          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4602          we need to put the operand into a register.  So split at that
4603          point.  */
4604
4605       if (SET_DEST (x) == cc0_rtx
4606           && GET_CODE (SET_SRC (x)) != COMPARE
4607           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4608           && !OBJECT_P (SET_SRC (x))
4609           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4610                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4611         return &SET_SRC (x);
4612 #endif
4613
4614       /* See if we can split SET_SRC as it stands.  */
4615       split = find_split_point (&SET_SRC (x), insn, true);
4616       if (split && split != &SET_SRC (x))
4617         return split;
4618
4619       /* See if we can split SET_DEST as it stands.  */
4620       split = find_split_point (&SET_DEST (x), insn, false);
4621       if (split && split != &SET_DEST (x))
4622         return split;
4623
4624       /* See if this is a bitfield assignment with everything constant.  If
4625          so, this is an IOR of an AND, so split it into that.  */
4626       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4627           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4628           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4629           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4630           && CONST_INT_P (SET_SRC (x))
4631           && ((INTVAL (XEXP (SET_DEST (x), 1))
4632                + INTVAL (XEXP (SET_DEST (x), 2)))
4633               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4634           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4635         {
4636           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4637           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4638           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4639           rtx dest = XEXP (SET_DEST (x), 0);
4640           enum machine_mode mode = GET_MODE (dest);
4641           unsigned HOST_WIDE_INT mask
4642             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4643           rtx or_mask;
4644
4645           if (BITS_BIG_ENDIAN)
4646             pos = GET_MODE_PRECISION (mode) - len - pos;
4647
4648           or_mask = gen_int_mode (src << pos, mode);
4649           if (src == mask)
4650             SUBST (SET_SRC (x),
4651                    simplify_gen_binary (IOR, mode, dest, or_mask));
4652           else
4653             {
4654               rtx negmask = gen_int_mode (~(mask << pos), mode);
4655               SUBST (SET_SRC (x),
4656                      simplify_gen_binary (IOR, mode,
4657                                           simplify_gen_binary (AND, mode,
4658                                                                dest, negmask),
4659                                           or_mask));
4660             }
4661
4662           SUBST (SET_DEST (x), dest);
4663
4664           split = find_split_point (&SET_SRC (x), insn, true);
4665           if (split && split != &SET_SRC (x))
4666             return split;
4667         }
4668
4669       /* Otherwise, see if this is an operation that we can split into two.
4670          If so, try to split that.  */
4671       code = GET_CODE (SET_SRC (x));
4672
4673       switch (code)
4674         {
4675         case AND:
4676           /* If we are AND'ing with a large constant that is only a single
4677              bit and the result is only being used in a context where we
4678              need to know if it is zero or nonzero, replace it with a bit
4679              extraction.  This will avoid the large constant, which might
4680              have taken more than one insn to make.  If the constant were
4681              not a valid argument to the AND but took only one insn to make,
4682              this is no worse, but if it took more than one insn, it will
4683              be better.  */
4684
4685           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4686               && REG_P (XEXP (SET_SRC (x), 0))
4687               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4688               && REG_P (SET_DEST (x))
4689               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4690               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4691               && XEXP (*split, 0) == SET_DEST (x)
4692               && XEXP (*split, 1) == const0_rtx)
4693             {
4694               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4695                                                 XEXP (SET_SRC (x), 0),
4696                                                 pos, NULL_RTX, 1, 1, 0, 0);
4697               if (extraction != 0)
4698                 {
4699                   SUBST (SET_SRC (x), extraction);
4700                   return find_split_point (loc, insn, false);
4701                 }
4702             }
4703           break;
4704
4705         case NE:
4706           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4707              is known to be on, this can be converted into a NEG of a shift.  */
4708           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4709               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4710               && 1 <= (pos = exact_log2
4711                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4712                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4713             {
4714               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4715
4716               SUBST (SET_SRC (x),
4717                      gen_rtx_NEG (mode,
4718                                   gen_rtx_LSHIFTRT (mode,
4719                                                     XEXP (SET_SRC (x), 0),
4720                                                     GEN_INT (pos))));
4721
4722               split = find_split_point (&SET_SRC (x), insn, true);
4723               if (split && split != &SET_SRC (x))
4724                 return split;
4725             }
4726           break;
4727
4728         case SIGN_EXTEND:
4729           inner = XEXP (SET_SRC (x), 0);
4730
4731           /* We can't optimize if either mode is a partial integer
4732              mode as we don't know how many bits are significant
4733              in those modes.  */
4734           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4735               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4736             break;
4737
4738           pos = 0;
4739           len = GET_MODE_PRECISION (GET_MODE (inner));
4740           unsignedp = 0;
4741           break;
4742
4743         case SIGN_EXTRACT:
4744         case ZERO_EXTRACT:
4745           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4746               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4747             {
4748               inner = XEXP (SET_SRC (x), 0);
4749               len = INTVAL (XEXP (SET_SRC (x), 1));
4750               pos = INTVAL (XEXP (SET_SRC (x), 2));
4751
4752               if (BITS_BIG_ENDIAN)
4753                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4754               unsignedp = (code == ZERO_EXTRACT);
4755             }
4756           break;
4757
4758         default:
4759           break;
4760         }
4761
4762       if (len && pos >= 0
4763           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4764         {
4765           enum machine_mode mode = GET_MODE (SET_SRC (x));
4766
4767           /* For unsigned, we have a choice of a shift followed by an
4768              AND or two shifts.  Use two shifts for field sizes where the
4769              constant might be too large.  We assume here that we can
4770              always at least get 8-bit constants in an AND insn, which is
4771              true for every current RISC.  */
4772
4773           if (unsignedp && len <= 8)
4774             {
4775               unsigned HOST_WIDE_INT mask
4776                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4777               SUBST (SET_SRC (x),
4778                      gen_rtx_AND (mode,
4779                                   gen_rtx_LSHIFTRT
4780                                   (mode, gen_lowpart (mode, inner),
4781                                    GEN_INT (pos)),
4782                                   gen_int_mode (mask, mode)));
4783
4784               split = find_split_point (&SET_SRC (x), insn, true);
4785               if (split && split != &SET_SRC (x))
4786                 return split;
4787             }
4788           else
4789             {
4790               SUBST (SET_SRC (x),
4791                      gen_rtx_fmt_ee
4792                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4793                       gen_rtx_ASHIFT (mode,
4794                                       gen_lowpart (mode, inner),
4795                                       GEN_INT (GET_MODE_PRECISION (mode)
4796                                                - len - pos)),
4797                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4798
4799               split = find_split_point (&SET_SRC (x), insn, true);
4800               if (split && split != &SET_SRC (x))
4801                 return split;
4802             }
4803         }
4804
4805       /* See if this is a simple operation with a constant as the second
4806          operand.  It might be that this constant is out of range and hence
4807          could be used as a split point.  */
4808       if (BINARY_P (SET_SRC (x))
4809           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4810           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4811               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4812                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4813         return &XEXP (SET_SRC (x), 1);
4814
4815       /* Finally, see if this is a simple operation with its first operand
4816          not in a register.  The operation might require this operand in a
4817          register, so return it as a split point.  We can always do this
4818          because if the first operand were another operation, we would have
4819          already found it as a split point.  */
4820       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4821           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4822         return &XEXP (SET_SRC (x), 0);
4823
4824       return 0;
4825
4826     case AND:
4827     case IOR:
4828       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4829          it is better to write this as (not (ior A B)) so we can split it.
4830          Similarly for IOR.  */
4831       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4832         {
4833           SUBST (*loc,
4834                  gen_rtx_NOT (GET_MODE (x),
4835                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4836                                               GET_MODE (x),
4837                                               XEXP (XEXP (x, 0), 0),
4838                                               XEXP (XEXP (x, 1), 0))));
4839           return find_split_point (loc, insn, set_src);
4840         }
4841
4842       /* Many RISC machines have a large set of logical insns.  If the
4843          second operand is a NOT, put it first so we will try to split the
4844          other operand first.  */
4845       if (GET_CODE (XEXP (x, 1)) == NOT)
4846         {
4847           rtx tem = XEXP (x, 0);
4848           SUBST (XEXP (x, 0), XEXP (x, 1));
4849           SUBST (XEXP (x, 1), tem);
4850         }
4851       break;
4852
4853     case PLUS:
4854     case MINUS:
4855       /* Canonicalization can produce (minus A (mult B C)), where C is a
4856          constant.  It may be better to try splitting (plus (mult B -C) A)
4857          instead if this isn't a multiply by a power of two.  */
4858       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4859           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4860           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4861         {
4862           enum machine_mode mode = GET_MODE (x);
4863           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4864           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4865           SUBST (*loc, gen_rtx_PLUS (mode,
4866                                      gen_rtx_MULT (mode,
4867                                                    XEXP (XEXP (x, 1), 0),
4868                                                    gen_int_mode (other_int,
4869                                                                  mode)),
4870                                      XEXP (x, 0)));
4871           return find_split_point (loc, insn, set_src);
4872         }
4873
4874       /* Split at a multiply-accumulate instruction.  However if this is
4875          the SET_SRC, we likely do not have such an instruction and it's
4876          worthless to try this split.  */
4877       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4878         return loc;
4879
4880     default:
4881       break;
4882     }
4883
4884   /* Otherwise, select our actions depending on our rtx class.  */
4885   switch (GET_RTX_CLASS (code))
4886     {
4887     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4888     case RTX_TERNARY:
4889       split = find_split_point (&XEXP (x, 2), insn, false);
4890       if (split)
4891         return split;
4892       /* ... fall through ...  */
4893     case RTX_BIN_ARITH:
4894     case RTX_COMM_ARITH:
4895     case RTX_COMPARE:
4896     case RTX_COMM_COMPARE:
4897       split = find_split_point (&XEXP (x, 1), insn, false);
4898       if (split)
4899         return split;
4900       /* ... fall through ...  */
4901     case RTX_UNARY:
4902       /* Some machines have (and (shift ...) ...) insns.  If X is not
4903          an AND, but XEXP (X, 0) is, use it as our split point.  */
4904       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4905         return &XEXP (x, 0);
4906
4907       split = find_split_point (&XEXP (x, 0), insn, false);
4908       if (split)
4909         return split;
4910       return loc;
4911
4912     default:
4913       /* Otherwise, we don't have a split point.  */
4914       return 0;
4915     }
4916 }
4917 \f
4918 /* Throughout X, replace FROM with TO, and return the result.
4919    The result is TO if X is FROM;
4920    otherwise the result is X, but its contents may have been modified.
4921    If they were modified, a record was made in undobuf so that
4922    undo_all will (among other things) return X to its original state.
4923
4924    If the number of changes necessary is too much to record to undo,
4925    the excess changes are not made, so the result is invalid.
4926    The changes already made can still be undone.
4927    undobuf.num_undo is incremented for such changes, so by testing that
4928    the caller can tell whether the result is valid.
4929
4930    `n_occurrences' is incremented each time FROM is replaced.
4931
4932    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4933
4934    IN_COND is nonzero if we are at the top level of a condition.
4935
4936    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4937    by copying if `n_occurrences' is nonzero.  */
4938
4939 static rtx
4940 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4941 {
4942   enum rtx_code code = GET_CODE (x);
4943   enum machine_mode op0_mode = VOIDmode;
4944   const char *fmt;
4945   int len, i;
4946   rtx new_rtx;
4947
4948 /* Two expressions are equal if they are identical copies of a shared
4949    RTX or if they are both registers with the same register number
4950    and mode.  */
4951
4952 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4953   ((X) == (Y)                                           \
4954    || (REG_P (X) && REG_P (Y)   \
4955        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4956
4957   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4958     {
4959       n_occurrences++;
4960       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4961     }
4962
4963   /* If X and FROM are the same register but different modes, they
4964      will not have been seen as equal above.  However, the log links code
4965      will make a LOG_LINKS entry for that case.  If we do nothing, we
4966      will try to rerecognize our original insn and, when it succeeds,
4967      we will delete the feeding insn, which is incorrect.
4968
4969      So force this insn not to match in this (rare) case.  */
4970   if (! in_dest && code == REG && REG_P (from)
4971       && reg_overlap_mentioned_p (x, from))
4972     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4973
4974   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4975      of which may contain things that can be combined.  */
4976   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4977     return x;
4978
4979   /* It is possible to have a subexpression appear twice in the insn.
4980      Suppose that FROM is a register that appears within TO.
4981      Then, after that subexpression has been scanned once by `subst',
4982      the second time it is scanned, TO may be found.  If we were
4983      to scan TO here, we would find FROM within it and create a
4984      self-referent rtl structure which is completely wrong.  */
4985   if (COMBINE_RTX_EQUAL_P (x, to))
4986     return to;
4987
4988   /* Parallel asm_operands need special attention because all of the
4989      inputs are shared across the arms.  Furthermore, unsharing the
4990      rtl results in recognition failures.  Failure to handle this case
4991      specially can result in circular rtl.
4992
4993      Solve this by doing a normal pass across the first entry of the
4994      parallel, and only processing the SET_DESTs of the subsequent
4995      entries.  Ug.  */
4996
4997   if (code == PARALLEL
4998       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4999       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5000     {
5001       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5002
5003       /* If this substitution failed, this whole thing fails.  */
5004       if (GET_CODE (new_rtx) == CLOBBER
5005           && XEXP (new_rtx, 0) == const0_rtx)
5006         return new_rtx;
5007
5008       SUBST (XVECEXP (x, 0, 0), new_rtx);
5009
5010       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5011         {
5012           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5013
5014           if (!REG_P (dest)
5015               && GET_CODE (dest) != CC0
5016               && GET_CODE (dest) != PC)
5017             {
5018               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5019
5020               /* If this substitution failed, this whole thing fails.  */
5021               if (GET_CODE (new_rtx) == CLOBBER
5022                   && XEXP (new_rtx, 0) == const0_rtx)
5023                 return new_rtx;
5024
5025               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5026             }
5027         }
5028     }
5029   else
5030     {
5031       len = GET_RTX_LENGTH (code);
5032       fmt = GET_RTX_FORMAT (code);
5033
5034       /* We don't need to process a SET_DEST that is a register, CC0,
5035          or PC, so set up to skip this common case.  All other cases
5036          where we want to suppress replacing something inside a
5037          SET_SRC are handled via the IN_DEST operand.  */
5038       if (code == SET
5039           && (REG_P (SET_DEST (x))
5040               || GET_CODE (SET_DEST (x)) == CC0
5041               || GET_CODE (SET_DEST (x)) == PC))
5042         fmt = "ie";
5043
5044       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5045          constant.  */
5046       if (fmt[0] == 'e')
5047         op0_mode = GET_MODE (XEXP (x, 0));
5048
5049       for (i = 0; i < len; i++)
5050         {
5051           if (fmt[i] == 'E')
5052             {
5053               int j;
5054               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5055                 {
5056                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5057                     {
5058                       new_rtx = (unique_copy && n_occurrences
5059                              ? copy_rtx (to) : to);
5060                       n_occurrences++;
5061                     }
5062                   else
5063                     {
5064                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5065                                        unique_copy);
5066
5067                       /* If this substitution failed, this whole thing
5068                          fails.  */
5069                       if (GET_CODE (new_rtx) == CLOBBER
5070                           && XEXP (new_rtx, 0) == const0_rtx)
5071                         return new_rtx;
5072                     }
5073
5074                   SUBST (XVECEXP (x, i, j), new_rtx);
5075                 }
5076             }
5077           else if (fmt[i] == 'e')
5078             {
5079               /* If this is a register being set, ignore it.  */
5080               new_rtx = XEXP (x, i);
5081               if (in_dest
5082                   && i == 0
5083                   && (((code == SUBREG || code == ZERO_EXTRACT)
5084                        && REG_P (new_rtx))
5085                       || code == STRICT_LOW_PART))
5086                 ;
5087
5088               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5089                 {
5090                   /* In general, don't install a subreg involving two
5091                      modes not tieable.  It can worsen register
5092                      allocation, and can even make invalid reload
5093                      insns, since the reg inside may need to be copied
5094                      from in the outside mode, and that may be invalid
5095                      if it is an fp reg copied in integer mode.
5096
5097                      We allow two exceptions to this: It is valid if
5098                      it is inside another SUBREG and the mode of that
5099                      SUBREG and the mode of the inside of TO is
5100                      tieable and it is valid if X is a SET that copies
5101                      FROM to CC0.  */
5102
5103                   if (GET_CODE (to) == SUBREG
5104                       && ! MODES_TIEABLE_P (GET_MODE (to),
5105                                             GET_MODE (SUBREG_REG (to)))
5106                       && ! (code == SUBREG
5107                             && MODES_TIEABLE_P (GET_MODE (x),
5108                                                 GET_MODE (SUBREG_REG (to))))
5109 #ifdef HAVE_cc0
5110                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5111 #endif
5112                       )
5113                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5114
5115 #ifdef CANNOT_CHANGE_MODE_CLASS
5116                   if (code == SUBREG
5117                       && REG_P (to)
5118                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5119                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5120                                                    GET_MODE (to),
5121                                                    GET_MODE (x)))
5122                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5123 #endif
5124
5125                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5126                   n_occurrences++;
5127                 }
5128               else
5129                 /* If we are in a SET_DEST, suppress most cases unless we
5130                    have gone inside a MEM, in which case we want to
5131                    simplify the address.  We assume here that things that
5132                    are actually part of the destination have their inner
5133                    parts in the first expression.  This is true for SUBREG,
5134                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5135                    things aside from REG and MEM that should appear in a
5136                    SET_DEST.  */
5137                 new_rtx = subst (XEXP (x, i), from, to,
5138                              (((in_dest
5139                                 && (code == SUBREG || code == STRICT_LOW_PART
5140                                     || code == ZERO_EXTRACT))
5141                                || code == SET)
5142                               && i == 0),
5143                                  code == IF_THEN_ELSE && i == 0,
5144                                  unique_copy);
5145
5146               /* If we found that we will have to reject this combination,
5147                  indicate that by returning the CLOBBER ourselves, rather than
5148                  an expression containing it.  This will speed things up as
5149                  well as prevent accidents where two CLOBBERs are considered
5150                  to be equal, thus producing an incorrect simplification.  */
5151
5152               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5153                 return new_rtx;
5154
5155               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5156                 {
5157                   enum machine_mode mode = GET_MODE (x);
5158
5159                   x = simplify_subreg (GET_MODE (x), new_rtx,
5160                                        GET_MODE (SUBREG_REG (x)),
5161                                        SUBREG_BYTE (x));
5162                   if (! x)
5163                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5164                 }
5165               else if (CONST_SCALAR_INT_P (new_rtx)
5166                        && GET_CODE (x) == ZERO_EXTEND)
5167                 {
5168                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5169                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5170                   gcc_assert (x);
5171                 }
5172               else
5173                 SUBST (XEXP (x, i), new_rtx);
5174             }
5175         }
5176     }
5177
5178   /* Check if we are loading something from the constant pool via float
5179      extension; in this case we would undo compress_float_constant
5180      optimization and degenerate constant load to an immediate value.  */
5181   if (GET_CODE (x) == FLOAT_EXTEND
5182       && MEM_P (XEXP (x, 0))
5183       && MEM_READONLY_P (XEXP (x, 0)))
5184     {
5185       rtx tmp = avoid_constant_pool_reference (x);
5186       if (x != tmp)
5187         return x;
5188     }
5189
5190   /* Try to simplify X.  If the simplification changed the code, it is likely
5191      that further simplification will help, so loop, but limit the number
5192      of repetitions that will be performed.  */
5193
5194   for (i = 0; i < 4; i++)
5195     {
5196       /* If X is sufficiently simple, don't bother trying to do anything
5197          with it.  */
5198       if (code != CONST_INT && code != REG && code != CLOBBER)
5199         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5200
5201       if (GET_CODE (x) == code)
5202         break;
5203
5204       code = GET_CODE (x);
5205
5206       /* We no longer know the original mode of operand 0 since we
5207          have changed the form of X)  */
5208       op0_mode = VOIDmode;
5209     }
5210
5211   return x;
5212 }
5213 \f
5214 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5215    outer level; call `subst' to simplify recursively.  Return the new
5216    expression.
5217
5218    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5219    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5220    of a condition.  */
5221
5222 static rtx
5223 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5224                       int in_cond)
5225 {
5226   enum rtx_code code = GET_CODE (x);
5227   enum machine_mode mode = GET_MODE (x);
5228   rtx temp;
5229   int i;
5230
5231   /* If this is a commutative operation, put a constant last and a complex
5232      expression first.  We don't need to do this for comparisons here.  */
5233   if (COMMUTATIVE_ARITH_P (x)
5234       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5235     {
5236       temp = XEXP (x, 0);
5237       SUBST (XEXP (x, 0), XEXP (x, 1));
5238       SUBST (XEXP (x, 1), temp);
5239     }
5240
5241   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5242      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5243      things.  Check for cases where both arms are testing the same
5244      condition.
5245
5246      Don't do anything if all operands are very simple.  */
5247
5248   if ((BINARY_P (x)
5249        && ((!OBJECT_P (XEXP (x, 0))
5250             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5251                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5252            || (!OBJECT_P (XEXP (x, 1))
5253                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5254                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5255       || (UNARY_P (x)
5256           && (!OBJECT_P (XEXP (x, 0))
5257                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5258                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5259     {
5260       rtx cond, true_rtx, false_rtx;
5261
5262       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5263       if (cond != 0
5264           /* If everything is a comparison, what we have is highly unlikely
5265              to be simpler, so don't use it.  */
5266           && ! (COMPARISON_P (x)
5267                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5268         {
5269           rtx cop1 = const0_rtx;
5270           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5271
5272           if (cond_code == NE && COMPARISON_P (cond))
5273             return x;
5274
5275           /* Simplify the alternative arms; this may collapse the true and
5276              false arms to store-flag values.  Be careful to use copy_rtx
5277              here since true_rtx or false_rtx might share RTL with x as a
5278              result of the if_then_else_cond call above.  */
5279           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5280           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5281
5282           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5283              is unlikely to be simpler.  */
5284           if (general_operand (true_rtx, VOIDmode)
5285               && general_operand (false_rtx, VOIDmode))
5286             {
5287               enum rtx_code reversed;
5288
5289               /* Restarting if we generate a store-flag expression will cause
5290                  us to loop.  Just drop through in this case.  */
5291
5292               /* If the result values are STORE_FLAG_VALUE and zero, we can
5293                  just make the comparison operation.  */
5294               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5295                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5296                                              cond, cop1);
5297               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5298                        && ((reversed = reversed_comparison_code_parts
5299                                         (cond_code, cond, cop1, NULL))
5300                            != UNKNOWN))
5301                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5302                                              cond, cop1);
5303
5304               /* Likewise, we can make the negate of a comparison operation
5305                  if the result values are - STORE_FLAG_VALUE and zero.  */
5306               else if (CONST_INT_P (true_rtx)
5307                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5308                        && false_rtx == const0_rtx)
5309                 x = simplify_gen_unary (NEG, mode,
5310                                         simplify_gen_relational (cond_code,
5311                                                                  mode, VOIDmode,
5312                                                                  cond, cop1),
5313                                         mode);
5314               else if (CONST_INT_P (false_rtx)
5315                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5316                        && true_rtx == const0_rtx
5317                        && ((reversed = reversed_comparison_code_parts
5318                                         (cond_code, cond, cop1, NULL))
5319                            != UNKNOWN))
5320                 x = simplify_gen_unary (NEG, mode,
5321                                         simplify_gen_relational (reversed,
5322                                                                  mode, VOIDmode,
5323                                                                  cond, cop1),
5324                                         mode);
5325               else
5326                 return gen_rtx_IF_THEN_ELSE (mode,
5327                                              simplify_gen_relational (cond_code,
5328                                                                       mode,
5329                                                                       VOIDmode,
5330                                                                       cond,
5331                                                                       cop1),
5332                                              true_rtx, false_rtx);
5333
5334               code = GET_CODE (x);
5335               op0_mode = VOIDmode;
5336             }
5337         }
5338     }
5339
5340   /* Try to fold this expression in case we have constants that weren't
5341      present before.  */
5342   temp = 0;
5343   switch (GET_RTX_CLASS (code))
5344     {
5345     case RTX_UNARY:
5346       if (op0_mode == VOIDmode)
5347         op0_mode = GET_MODE (XEXP (x, 0));
5348       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5349       break;
5350     case RTX_COMPARE:
5351     case RTX_COMM_COMPARE:
5352       {
5353         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5354         if (cmp_mode == VOIDmode)
5355           {
5356             cmp_mode = GET_MODE (XEXP (x, 1));
5357             if (cmp_mode == VOIDmode)
5358               cmp_mode = op0_mode;
5359           }
5360         temp = simplify_relational_operation (code, mode, cmp_mode,
5361                                               XEXP (x, 0), XEXP (x, 1));
5362       }
5363       break;
5364     case RTX_COMM_ARITH:
5365     case RTX_BIN_ARITH:
5366       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5367       break;
5368     case RTX_BITFIELD_OPS:
5369     case RTX_TERNARY:
5370       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5371                                          XEXP (x, 1), XEXP (x, 2));
5372       break;
5373     default:
5374       break;
5375     }
5376
5377   if (temp)
5378     {
5379       x = temp;
5380       code = GET_CODE (temp);
5381       op0_mode = VOIDmode;
5382       mode = GET_MODE (temp);
5383     }
5384
5385   /* First see if we can apply the inverse distributive law.  */
5386   if (code == PLUS || code == MINUS
5387       || code == AND || code == IOR || code == XOR)
5388     {
5389       x = apply_distributive_law (x);
5390       code = GET_CODE (x);
5391       op0_mode = VOIDmode;
5392     }
5393
5394   /* If CODE is an associative operation not otherwise handled, see if we
5395      can associate some operands.  This can win if they are constants or
5396      if they are logically related (i.e. (a & b) & a).  */
5397   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5398        || code == AND || code == IOR || code == XOR
5399        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5400       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5401           || (flag_associative_math && FLOAT_MODE_P (mode))))
5402     {
5403       if (GET_CODE (XEXP (x, 0)) == code)
5404         {
5405           rtx other = XEXP (XEXP (x, 0), 0);
5406           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5407           rtx inner_op1 = XEXP (x, 1);
5408           rtx inner;
5409
5410           /* Make sure we pass the constant operand if any as the second
5411              one if this is a commutative operation.  */
5412           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5413             {
5414               rtx tem = inner_op0;
5415               inner_op0 = inner_op1;
5416               inner_op1 = tem;
5417             }
5418           inner = simplify_binary_operation (code == MINUS ? PLUS
5419                                              : code == DIV ? MULT
5420                                              : code,
5421                                              mode, inner_op0, inner_op1);
5422
5423           /* For commutative operations, try the other pair if that one
5424              didn't simplify.  */
5425           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5426             {
5427               other = XEXP (XEXP (x, 0), 1);
5428               inner = simplify_binary_operation (code, mode,
5429                                                  XEXP (XEXP (x, 0), 0),
5430                                                  XEXP (x, 1));
5431             }
5432
5433           if (inner)
5434             return simplify_gen_binary (code, mode, other, inner);
5435         }
5436     }
5437
5438   /* A little bit of algebraic simplification here.  */
5439   switch (code)
5440     {
5441     case MEM:
5442       /* Ensure that our address has any ASHIFTs converted to MULT in case
5443          address-recognizing predicates are called later.  */
5444       temp = make_compound_operation (XEXP (x, 0), MEM);
5445       SUBST (XEXP (x, 0), temp);
5446       break;
5447
5448     case SUBREG:
5449       if (op0_mode == VOIDmode)
5450         op0_mode = GET_MODE (SUBREG_REG (x));
5451
5452       /* See if this can be moved to simplify_subreg.  */
5453       if (CONSTANT_P (SUBREG_REG (x))
5454           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5455              /* Don't call gen_lowpart if the inner mode
5456                 is VOIDmode and we cannot simplify it, as SUBREG without
5457                 inner mode is invalid.  */
5458           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5459               || gen_lowpart_common (mode, SUBREG_REG (x))))
5460         return gen_lowpart (mode, SUBREG_REG (x));
5461
5462       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5463         break;
5464       {
5465         rtx temp;
5466         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5467                                 SUBREG_BYTE (x));
5468         if (temp)
5469           return temp;
5470
5471         /* If op is known to have all lower bits zero, the result is zero.  */
5472         if (!in_dest
5473             && SCALAR_INT_MODE_P (mode)
5474             && SCALAR_INT_MODE_P (op0_mode)
5475             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5476             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5477             && HWI_COMPUTABLE_MODE_P (op0_mode)
5478             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5479                 & GET_MODE_MASK (mode)) == 0)
5480           return CONST0_RTX (mode);
5481       }
5482
5483       /* Don't change the mode of the MEM if that would change the meaning
5484          of the address.  */
5485       if (MEM_P (SUBREG_REG (x))
5486           && (MEM_VOLATILE_P (SUBREG_REG (x))
5487               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5488                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5489         return gen_rtx_CLOBBER (mode, const0_rtx);
5490
5491       /* Note that we cannot do any narrowing for non-constants since
5492          we might have been counting on using the fact that some bits were
5493          zero.  We now do this in the SET.  */
5494
5495       break;
5496
5497     case NEG:
5498       temp = expand_compound_operation (XEXP (x, 0));
5499
5500       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5501          replaced by (lshiftrt X C).  This will convert
5502          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5503
5504       if (GET_CODE (temp) == ASHIFTRT
5505           && CONST_INT_P (XEXP (temp, 1))
5506           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5507         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5508                                      INTVAL (XEXP (temp, 1)));
5509
5510       /* If X has only a single bit that might be nonzero, say, bit I, convert
5511          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5512          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5513          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5514          or a SUBREG of one since we'd be making the expression more
5515          complex if it was just a register.  */
5516
5517       if (!REG_P (temp)
5518           && ! (GET_CODE (temp) == SUBREG
5519                 && REG_P (SUBREG_REG (temp)))
5520           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5521         {
5522           rtx temp1 = simplify_shift_const
5523             (NULL_RTX, ASHIFTRT, mode,
5524              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5525                                    GET_MODE_PRECISION (mode) - 1 - i),
5526              GET_MODE_PRECISION (mode) - 1 - i);
5527
5528           /* If all we did was surround TEMP with the two shifts, we
5529              haven't improved anything, so don't use it.  Otherwise,
5530              we are better off with TEMP1.  */
5531           if (GET_CODE (temp1) != ASHIFTRT
5532               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5533               || XEXP (XEXP (temp1, 0), 0) != temp)
5534             return temp1;
5535         }
5536       break;
5537
5538     case TRUNCATE:
5539       /* We can't handle truncation to a partial integer mode here
5540          because we don't know the real bitsize of the partial
5541          integer mode.  */
5542       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5543         break;
5544
5545       if (HWI_COMPUTABLE_MODE_P (mode))
5546         SUBST (XEXP (x, 0),
5547                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5548                               GET_MODE_MASK (mode), 0));
5549
5550       /* We can truncate a constant value and return it.  */
5551       if (CONST_INT_P (XEXP (x, 0)))
5552         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5553
5554       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5555          whose value is a comparison can be replaced with a subreg if
5556          STORE_FLAG_VALUE permits.  */
5557       if (HWI_COMPUTABLE_MODE_P (mode)
5558           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5559           && (temp = get_last_value (XEXP (x, 0)))
5560           && COMPARISON_P (temp))
5561         return gen_lowpart (mode, XEXP (x, 0));
5562       break;
5563
5564     case CONST:
5565       /* (const (const X)) can become (const X).  Do it this way rather than
5566          returning the inner CONST since CONST can be shared with a
5567          REG_EQUAL note.  */
5568       if (GET_CODE (XEXP (x, 0)) == CONST)
5569         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5570       break;
5571
5572 #ifdef HAVE_lo_sum
5573     case LO_SUM:
5574       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5575          can add in an offset.  find_split_point will split this address up
5576          again if it doesn't match.  */
5577       if (GET_CODE (XEXP (x, 0)) == HIGH
5578           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5579         return XEXP (x, 1);
5580       break;
5581 #endif
5582
5583     case PLUS:
5584       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5585          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5586          bit-field and can be replaced by either a sign_extend or a
5587          sign_extract.  The `and' may be a zero_extend and the two
5588          <c>, -<c> constants may be reversed.  */
5589       if (GET_CODE (XEXP (x, 0)) == XOR
5590           && CONST_INT_P (XEXP (x, 1))
5591           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5592           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5593           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5594               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5595           && HWI_COMPUTABLE_MODE_P (mode)
5596           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5597                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5598                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5599                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5600               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5601                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5602                       == (unsigned int) i + 1))))
5603         return simplify_shift_const
5604           (NULL_RTX, ASHIFTRT, mode,
5605            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5606                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5607                                  GET_MODE_PRECISION (mode) - (i + 1)),
5608            GET_MODE_PRECISION (mode) - (i + 1));
5609
5610       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5611          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5612          the bitsize of the mode - 1.  This allows simplification of
5613          "a = (b & 8) == 0;"  */
5614       if (XEXP (x, 1) == constm1_rtx
5615           && !REG_P (XEXP (x, 0))
5616           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5617                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5618           && nonzero_bits (XEXP (x, 0), mode) == 1)
5619         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5620            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5621                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5622                                  GET_MODE_PRECISION (mode) - 1),
5623            GET_MODE_PRECISION (mode) - 1);
5624
5625       /* If we are adding two things that have no bits in common, convert
5626          the addition into an IOR.  This will often be further simplified,
5627          for example in cases like ((a & 1) + (a & 2)), which can
5628          become a & 3.  */
5629
5630       if (HWI_COMPUTABLE_MODE_P (mode)
5631           && (nonzero_bits (XEXP (x, 0), mode)
5632               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5633         {
5634           /* Try to simplify the expression further.  */
5635           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5636           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5637
5638           /* If we could, great.  If not, do not go ahead with the IOR
5639              replacement, since PLUS appears in many special purpose
5640              address arithmetic instructions.  */
5641           if (GET_CODE (temp) != CLOBBER
5642               && (GET_CODE (temp) != IOR
5643                   || ((XEXP (temp, 0) != XEXP (x, 0)
5644                        || XEXP (temp, 1) != XEXP (x, 1))
5645                       && (XEXP (temp, 0) != XEXP (x, 1)
5646                           || XEXP (temp, 1) != XEXP (x, 0)))))
5647             return temp;
5648         }
5649       break;
5650
5651     case MINUS:
5652       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5653          (and <foo> (const_int pow2-1))  */
5654       if (GET_CODE (XEXP (x, 1)) == AND
5655           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5656           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5657           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5658         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5659                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5660       break;
5661
5662     case MULT:
5663       /* If we have (mult (plus A B) C), apply the distributive law and then
5664          the inverse distributive law to see if things simplify.  This
5665          occurs mostly in addresses, often when unrolling loops.  */
5666
5667       if (GET_CODE (XEXP (x, 0)) == PLUS)
5668         {
5669           rtx result = distribute_and_simplify_rtx (x, 0);
5670           if (result)
5671             return result;
5672         }
5673
5674       /* Try simplify a*(b/c) as (a*b)/c.  */
5675       if (FLOAT_MODE_P (mode) && flag_associative_math
5676           && GET_CODE (XEXP (x, 0)) == DIV)
5677         {
5678           rtx tem = simplify_binary_operation (MULT, mode,
5679                                                XEXP (XEXP (x, 0), 0),
5680                                                XEXP (x, 1));
5681           if (tem)
5682             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5683         }
5684       break;
5685
5686     case UDIV:
5687       /* If this is a divide by a power of two, treat it as a shift if
5688          its first operand is a shift.  */
5689       if (CONST_INT_P (XEXP (x, 1))
5690           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5691           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5692               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5693               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5694               || GET_CODE (XEXP (x, 0)) == ROTATE
5695               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5696         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5697       break;
5698
5699     case EQ:  case NE:
5700     case GT:  case GTU:  case GE:  case GEU:
5701     case LT:  case LTU:  case LE:  case LEU:
5702     case UNEQ:  case LTGT:
5703     case UNGT:  case UNGE:
5704     case UNLT:  case UNLE:
5705     case UNORDERED: case ORDERED:
5706       /* If the first operand is a condition code, we can't do anything
5707          with it.  */
5708       if (GET_CODE (XEXP (x, 0)) == COMPARE
5709           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5710               && ! CC0_P (XEXP (x, 0))))
5711         {
5712           rtx op0 = XEXP (x, 0);
5713           rtx op1 = XEXP (x, 1);
5714           enum rtx_code new_code;
5715
5716           if (GET_CODE (op0) == COMPARE)
5717             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5718
5719           /* Simplify our comparison, if possible.  */
5720           new_code = simplify_comparison (code, &op0, &op1);
5721
5722           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5723              if only the low-order bit is possibly nonzero in X (such as when
5724              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5725              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5726              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5727              (plus X 1).
5728
5729              Remove any ZERO_EXTRACT we made when thinking this was a
5730              comparison.  It may now be simpler to use, e.g., an AND.  If a
5731              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5732              the call to make_compound_operation in the SET case.
5733
5734              Don't apply these optimizations if the caller would
5735              prefer a comparison rather than a value.
5736              E.g., for the condition in an IF_THEN_ELSE most targets need
5737              an explicit comparison.  */
5738
5739           if (in_cond)
5740             ;
5741
5742           else if (STORE_FLAG_VALUE == 1
5743               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5744               && op1 == const0_rtx
5745               && mode == GET_MODE (op0)
5746               && nonzero_bits (op0, mode) == 1)
5747             return gen_lowpart (mode,
5748                                 expand_compound_operation (op0));
5749
5750           else if (STORE_FLAG_VALUE == 1
5751                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5752                    && op1 == const0_rtx
5753                    && mode == GET_MODE (op0)
5754                    && (num_sign_bit_copies (op0, mode)
5755                        == GET_MODE_PRECISION (mode)))
5756             {
5757               op0 = expand_compound_operation (op0);
5758               return simplify_gen_unary (NEG, mode,
5759                                          gen_lowpart (mode, op0),
5760                                          mode);
5761             }
5762
5763           else if (STORE_FLAG_VALUE == 1
5764                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5765                    && op1 == const0_rtx
5766                    && mode == GET_MODE (op0)
5767                    && nonzero_bits (op0, mode) == 1)
5768             {
5769               op0 = expand_compound_operation (op0);
5770               return simplify_gen_binary (XOR, mode,
5771                                           gen_lowpart (mode, op0),
5772                                           const1_rtx);
5773             }
5774
5775           else if (STORE_FLAG_VALUE == 1
5776                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5777                    && op1 == const0_rtx
5778                    && mode == GET_MODE (op0)
5779                    && (num_sign_bit_copies (op0, mode)
5780                        == GET_MODE_PRECISION (mode)))
5781             {
5782               op0 = expand_compound_operation (op0);
5783               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5784             }
5785
5786           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5787              those above.  */
5788           if (in_cond)
5789             ;
5790
5791           else if (STORE_FLAG_VALUE == -1
5792               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5793               && op1 == const0_rtx
5794               && (num_sign_bit_copies (op0, mode)
5795                   == GET_MODE_PRECISION (mode)))
5796             return gen_lowpart (mode,
5797                                 expand_compound_operation (op0));
5798
5799           else if (STORE_FLAG_VALUE == -1
5800                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5801                    && op1 == const0_rtx
5802                    && mode == GET_MODE (op0)
5803                    && nonzero_bits (op0, mode) == 1)
5804             {
5805               op0 = expand_compound_operation (op0);
5806               return simplify_gen_unary (NEG, mode,
5807                                          gen_lowpart (mode, op0),
5808                                          mode);
5809             }
5810
5811           else if (STORE_FLAG_VALUE == -1
5812                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5813                    && op1 == const0_rtx
5814                    && mode == GET_MODE (op0)
5815                    && (num_sign_bit_copies (op0, mode)
5816                        == GET_MODE_PRECISION (mode)))
5817             {
5818               op0 = expand_compound_operation (op0);
5819               return simplify_gen_unary (NOT, mode,
5820                                          gen_lowpart (mode, op0),
5821                                          mode);
5822             }
5823
5824           /* If X is 0/1, (eq X 0) is X-1.  */
5825           else if (STORE_FLAG_VALUE == -1
5826                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5827                    && op1 == const0_rtx
5828                    && mode == GET_MODE (op0)
5829                    && nonzero_bits (op0, mode) == 1)
5830             {
5831               op0 = expand_compound_operation (op0);
5832               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5833             }
5834
5835           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5836              one bit that might be nonzero, we can convert (ne x 0) to
5837              (ashift x c) where C puts the bit in the sign bit.  Remove any
5838              AND with STORE_FLAG_VALUE when we are done, since we are only
5839              going to test the sign bit.  */
5840           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5841               && HWI_COMPUTABLE_MODE_P (mode)
5842               && val_signbit_p (mode, STORE_FLAG_VALUE)
5843               && op1 == const0_rtx
5844               && mode == GET_MODE (op0)
5845               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5846             {
5847               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5848                                         expand_compound_operation (op0),
5849                                         GET_MODE_PRECISION (mode) - 1 - i);
5850               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5851                 return XEXP (x, 0);
5852               else
5853                 return x;
5854             }
5855
5856           /* If the code changed, return a whole new comparison.
5857              We also need to avoid using SUBST in cases where
5858              simplify_comparison has widened a comparison with a CONST_INT,
5859              since in that case the wider CONST_INT may fail the sanity
5860              checks in do_SUBST.  */
5861           if (new_code != code
5862               || (CONST_INT_P (op1)
5863                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5864                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5865             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5866
5867           /* Otherwise, keep this operation, but maybe change its operands.
5868              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5869           SUBST (XEXP (x, 0), op0);
5870           SUBST (XEXP (x, 1), op1);
5871         }
5872       break;
5873
5874     case IF_THEN_ELSE:
5875       return simplify_if_then_else (x);
5876
5877     case ZERO_EXTRACT:
5878     case SIGN_EXTRACT:
5879     case ZERO_EXTEND:
5880     case SIGN_EXTEND:
5881       /* If we are processing SET_DEST, we are done.  */
5882       if (in_dest)
5883         return x;
5884
5885       return expand_compound_operation (x);
5886
5887     case SET:
5888       return simplify_set (x);
5889
5890     case AND:
5891     case IOR:
5892       return simplify_logical (x);
5893
5894     case ASHIFT:
5895     case LSHIFTRT:
5896     case ASHIFTRT:
5897     case ROTATE:
5898     case ROTATERT:
5899       /* If this is a shift by a constant amount, simplify it.  */
5900       if (CONST_INT_P (XEXP (x, 1)))
5901         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5902                                      INTVAL (XEXP (x, 1)));
5903
5904       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5905         SUBST (XEXP (x, 1),
5906                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5907                               ((unsigned HOST_WIDE_INT) 1
5908                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5909                               - 1,
5910                               0));
5911       break;
5912
5913     default:
5914       break;
5915     }
5916
5917   return x;
5918 }
5919 \f
5920 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5921
5922 static rtx
5923 simplify_if_then_else (rtx x)
5924 {
5925   enum machine_mode mode = GET_MODE (x);
5926   rtx cond = XEXP (x, 0);
5927   rtx true_rtx = XEXP (x, 1);
5928   rtx false_rtx = XEXP (x, 2);
5929   enum rtx_code true_code = GET_CODE (cond);
5930   int comparison_p = COMPARISON_P (cond);
5931   rtx temp;
5932   int i;
5933   enum rtx_code false_code;
5934   rtx reversed;
5935
5936   /* Simplify storing of the truth value.  */
5937   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5938     return simplify_gen_relational (true_code, mode, VOIDmode,
5939                                     XEXP (cond, 0), XEXP (cond, 1));
5940
5941   /* Also when the truth value has to be reversed.  */
5942   if (comparison_p
5943       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5944       && (reversed = reversed_comparison (cond, mode)))
5945     return reversed;
5946
5947   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5948      in it is being compared against certain values.  Get the true and false
5949      comparisons and see if that says anything about the value of each arm.  */
5950
5951   if (comparison_p
5952       && ((false_code = reversed_comparison_code (cond, NULL))
5953           != UNKNOWN)
5954       && REG_P (XEXP (cond, 0)))
5955     {
5956       HOST_WIDE_INT nzb;
5957       rtx from = XEXP (cond, 0);
5958       rtx true_val = XEXP (cond, 1);
5959       rtx false_val = true_val;
5960       int swapped = 0;
5961
5962       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5963
5964       if (false_code == EQ)
5965         {
5966           swapped = 1, true_code = EQ, false_code = NE;
5967           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5968         }
5969
5970       /* If we are comparing against zero and the expression being tested has
5971          only a single bit that might be nonzero, that is its value when it is
5972          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5973
5974       if (true_code == EQ && true_val == const0_rtx
5975           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5976         {
5977           false_code = EQ;
5978           false_val = gen_int_mode (nzb, GET_MODE (from));
5979         }
5980       else if (true_code == EQ && true_val == const0_rtx
5981                && (num_sign_bit_copies (from, GET_MODE (from))
5982                    == GET_MODE_PRECISION (GET_MODE (from))))
5983         {
5984           false_code = EQ;
5985           false_val = constm1_rtx;
5986         }
5987
5988       /* Now simplify an arm if we know the value of the register in the
5989          branch and it is used in the arm.  Be careful due to the potential
5990          of locally-shared RTL.  */
5991
5992       if (reg_mentioned_p (from, true_rtx))
5993         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5994                                       from, true_val),
5995                           pc_rtx, pc_rtx, 0, 0, 0);
5996       if (reg_mentioned_p (from, false_rtx))
5997         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5998                                    from, false_val),
5999                            pc_rtx, pc_rtx, 0, 0, 0);
6000
6001       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6002       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6003
6004       true_rtx = XEXP (x, 1);
6005       false_rtx = XEXP (x, 2);
6006       true_code = GET_CODE (cond);
6007     }
6008
6009   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6010      reversed, do so to avoid needing two sets of patterns for
6011      subtract-and-branch insns.  Similarly if we have a constant in the true
6012      arm, the false arm is the same as the first operand of the comparison, or
6013      the false arm is more complicated than the true arm.  */
6014
6015   if (comparison_p
6016       && reversed_comparison_code (cond, NULL) != UNKNOWN
6017       && (true_rtx == pc_rtx
6018           || (CONSTANT_P (true_rtx)
6019               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6020           || true_rtx == const0_rtx
6021           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6022           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6023               && !OBJECT_P (false_rtx))
6024           || reg_mentioned_p (true_rtx, false_rtx)
6025           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6026     {
6027       true_code = reversed_comparison_code (cond, NULL);
6028       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6029       SUBST (XEXP (x, 1), false_rtx);
6030       SUBST (XEXP (x, 2), true_rtx);
6031
6032       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6033       cond = XEXP (x, 0);
6034
6035       /* It is possible that the conditional has been simplified out.  */
6036       true_code = GET_CODE (cond);
6037       comparison_p = COMPARISON_P (cond);
6038     }
6039
6040   /* If the two arms are identical, we don't need the comparison.  */
6041
6042   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6043     return true_rtx;
6044
6045   /* Convert a == b ? b : a to "a".  */
6046   if (true_code == EQ && ! side_effects_p (cond)
6047       && !HONOR_NANS (mode)
6048       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6049       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6050     return false_rtx;
6051   else if (true_code == NE && ! side_effects_p (cond)
6052            && !HONOR_NANS (mode)
6053            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6054            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6055     return true_rtx;
6056
6057   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6058
6059   if (GET_MODE_CLASS (mode) == MODE_INT
6060       && comparison_p
6061       && XEXP (cond, 1) == const0_rtx
6062       && GET_CODE (false_rtx) == NEG
6063       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6064       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6065       && ! side_effects_p (true_rtx))
6066     switch (true_code)
6067       {
6068       case GT:
6069       case GE:
6070         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6071       case LT:
6072       case LE:
6073         return
6074           simplify_gen_unary (NEG, mode,
6075                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6076                               mode);
6077       default:
6078         break;
6079       }
6080
6081   /* Look for MIN or MAX.  */
6082
6083   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6084       && comparison_p
6085       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6086       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6087       && ! side_effects_p (cond))
6088     switch (true_code)
6089       {
6090       case GE:
6091       case GT:
6092         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6093       case LE:
6094       case LT:
6095         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6096       case GEU:
6097       case GTU:
6098         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6099       case LEU:
6100       case LTU:
6101         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6102       default:
6103         break;
6104       }
6105
6106   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6107      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6108      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6109      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6110      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6111      neither 1 or -1, but it isn't worth checking for.  */
6112
6113   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6114       && comparison_p
6115       && GET_MODE_CLASS (mode) == MODE_INT
6116       && ! side_effects_p (x))
6117     {
6118       rtx t = make_compound_operation (true_rtx, SET);
6119       rtx f = make_compound_operation (false_rtx, SET);
6120       rtx cond_op0 = XEXP (cond, 0);
6121       rtx cond_op1 = XEXP (cond, 1);
6122       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6123       enum machine_mode m = mode;
6124       rtx z = 0, c1 = NULL_RTX;
6125
6126       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6127            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6128            || GET_CODE (t) == ASHIFT
6129            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6130           && rtx_equal_p (XEXP (t, 0), f))
6131         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6132
6133       /* If an identity-zero op is commutative, check whether there
6134          would be a match if we swapped the operands.  */
6135       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6136                 || GET_CODE (t) == XOR)
6137                && rtx_equal_p (XEXP (t, 1), f))
6138         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6139       else if (GET_CODE (t) == SIGN_EXTEND
6140                && (GET_CODE (XEXP (t, 0)) == PLUS
6141                    || GET_CODE (XEXP (t, 0)) == MINUS
6142                    || GET_CODE (XEXP (t, 0)) == IOR
6143                    || GET_CODE (XEXP (t, 0)) == XOR
6144                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6145                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6146                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6147                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6148                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6149                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6150                && (num_sign_bit_copies (f, GET_MODE (f))
6151                    > (unsigned int)
6152                      (GET_MODE_PRECISION (mode)
6153                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6154         {
6155           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6156           extend_op = SIGN_EXTEND;
6157           m = GET_MODE (XEXP (t, 0));
6158         }
6159       else if (GET_CODE (t) == SIGN_EXTEND
6160                && (GET_CODE (XEXP (t, 0)) == PLUS
6161                    || GET_CODE (XEXP (t, 0)) == IOR
6162                    || GET_CODE (XEXP (t, 0)) == XOR)
6163                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6164                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6165                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6166                && (num_sign_bit_copies (f, GET_MODE (f))
6167                    > (unsigned int)
6168                      (GET_MODE_PRECISION (mode)
6169                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6170         {
6171           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6172           extend_op = SIGN_EXTEND;
6173           m = GET_MODE (XEXP (t, 0));
6174         }
6175       else if (GET_CODE (t) == ZERO_EXTEND
6176                && (GET_CODE (XEXP (t, 0)) == PLUS
6177                    || GET_CODE (XEXP (t, 0)) == MINUS
6178                    || GET_CODE (XEXP (t, 0)) == IOR
6179                    || GET_CODE (XEXP (t, 0)) == XOR
6180                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6181                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6182                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6183                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6184                && HWI_COMPUTABLE_MODE_P (mode)
6185                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6186                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6187                && ((nonzero_bits (f, GET_MODE (f))
6188                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6189                    == 0))
6190         {
6191           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6192           extend_op = ZERO_EXTEND;
6193           m = GET_MODE (XEXP (t, 0));
6194         }
6195       else if (GET_CODE (t) == ZERO_EXTEND
6196                && (GET_CODE (XEXP (t, 0)) == PLUS
6197                    || GET_CODE (XEXP (t, 0)) == IOR
6198                    || GET_CODE (XEXP (t, 0)) == XOR)
6199                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6200                && HWI_COMPUTABLE_MODE_P (mode)
6201                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6202                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6203                && ((nonzero_bits (f, GET_MODE (f))
6204                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6205                    == 0))
6206         {
6207           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6208           extend_op = ZERO_EXTEND;
6209           m = GET_MODE (XEXP (t, 0));
6210         }
6211
6212       if (z)
6213         {
6214           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6215                                                  cond_op0, cond_op1),
6216                         pc_rtx, pc_rtx, 0, 0, 0);
6217           temp = simplify_gen_binary (MULT, m, temp,
6218                                       simplify_gen_binary (MULT, m, c1,
6219                                                            const_true_rtx));
6220           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6221           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6222
6223           if (extend_op != UNKNOWN)
6224             temp = simplify_gen_unary (extend_op, mode, temp, m);
6225
6226           return temp;
6227         }
6228     }
6229
6230   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6231      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6232      negation of a single bit, we can convert this operation to a shift.  We
6233      can actually do this more generally, but it doesn't seem worth it.  */
6234
6235   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6236       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6237       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6238            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6239           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6240                == GET_MODE_PRECISION (mode))
6241               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6242     return
6243       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6244                             gen_lowpart (mode, XEXP (cond, 0)), i);
6245
6246   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6247   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6248       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6249       && GET_MODE (XEXP (cond, 0)) == mode
6250       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6251           == nonzero_bits (XEXP (cond, 0), mode)
6252       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6253     return XEXP (cond, 0);
6254
6255   return x;
6256 }
6257 \f
6258 /* Simplify X, a SET expression.  Return the new expression.  */
6259
6260 static rtx
6261 simplify_set (rtx x)
6262 {
6263   rtx src = SET_SRC (x);
6264   rtx dest = SET_DEST (x);
6265   enum machine_mode mode
6266     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6267   rtx other_insn;
6268   rtx *cc_use;
6269
6270   /* (set (pc) (return)) gets written as (return).  */
6271   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6272     return src;
6273
6274   /* Now that we know for sure which bits of SRC we are using, see if we can
6275      simplify the expression for the object knowing that we only need the
6276      low-order bits.  */
6277
6278   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6279     {
6280       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6281       SUBST (SET_SRC (x), src);
6282     }
6283
6284   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6285      the comparison result and try to simplify it unless we already have used
6286      undobuf.other_insn.  */
6287   if ((GET_MODE_CLASS (mode) == MODE_CC
6288        || GET_CODE (src) == COMPARE
6289        || CC0_P (dest))
6290       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6291       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6292       && COMPARISON_P (*cc_use)
6293       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6294     {
6295       enum rtx_code old_code = GET_CODE (*cc_use);
6296       enum rtx_code new_code;
6297       rtx op0, op1, tmp;
6298       int other_changed = 0;
6299       rtx inner_compare = NULL_RTX;
6300       enum machine_mode compare_mode = GET_MODE (dest);
6301
6302       if (GET_CODE (src) == COMPARE)
6303         {
6304           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6305           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6306             {
6307               inner_compare = op0;
6308               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6309             }
6310         }
6311       else
6312         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6313
6314       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6315                                            op0, op1);
6316       if (!tmp)
6317         new_code = old_code;
6318       else if (!CONSTANT_P (tmp))
6319         {
6320           new_code = GET_CODE (tmp);
6321           op0 = XEXP (tmp, 0);
6322           op1 = XEXP (tmp, 1);
6323         }
6324       else
6325         {
6326           rtx pat = PATTERN (other_insn);
6327           undobuf.other_insn = other_insn;
6328           SUBST (*cc_use, tmp);
6329
6330           /* Attempt to simplify CC user.  */
6331           if (GET_CODE (pat) == SET)
6332             {
6333               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6334               if (new_rtx != NULL_RTX)
6335                 SUBST (SET_SRC (pat), new_rtx);
6336             }
6337
6338           /* Convert X into a no-op move.  */
6339           SUBST (SET_DEST (x), pc_rtx);
6340           SUBST (SET_SRC (x), pc_rtx);
6341           return x;
6342         }
6343
6344       /* Simplify our comparison, if possible.  */
6345       new_code = simplify_comparison (new_code, &op0, &op1);
6346
6347 #ifdef SELECT_CC_MODE
6348       /* If this machine has CC modes other than CCmode, check to see if we
6349          need to use a different CC mode here.  */
6350       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6351         compare_mode = GET_MODE (op0);
6352       else if (inner_compare
6353                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6354                && new_code == old_code
6355                && op0 == XEXP (inner_compare, 0)
6356                && op1 == XEXP (inner_compare, 1))
6357         compare_mode = GET_MODE (inner_compare);
6358       else
6359         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6360
6361 #ifndef HAVE_cc0
6362       /* If the mode changed, we have to change SET_DEST, the mode in the
6363          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6364          a hard register, just build new versions with the proper mode.  If it
6365          is a pseudo, we lose unless it is only time we set the pseudo, in
6366          which case we can safely change its mode.  */
6367       if (compare_mode != GET_MODE (dest))
6368         {
6369           if (can_change_dest_mode (dest, 0, compare_mode))
6370             {
6371               unsigned int regno = REGNO (dest);
6372               rtx new_dest;
6373
6374               if (regno < FIRST_PSEUDO_REGISTER)
6375                 new_dest = gen_rtx_REG (compare_mode, regno);
6376               else
6377                 {
6378                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6379                   new_dest = regno_reg_rtx[regno];
6380                 }
6381
6382               SUBST (SET_DEST (x), new_dest);
6383               SUBST (XEXP (*cc_use, 0), new_dest);
6384               other_changed = 1;
6385
6386               dest = new_dest;
6387             }
6388         }
6389 #endif  /* cc0 */
6390 #endif  /* SELECT_CC_MODE */
6391
6392       /* If the code changed, we have to build a new comparison in
6393          undobuf.other_insn.  */
6394       if (new_code != old_code)
6395         {
6396           int other_changed_previously = other_changed;
6397           unsigned HOST_WIDE_INT mask;
6398           rtx old_cc_use = *cc_use;
6399
6400           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6401                                           dest, const0_rtx));
6402           other_changed = 1;
6403
6404           /* If the only change we made was to change an EQ into an NE or
6405              vice versa, OP0 has only one bit that might be nonzero, and OP1
6406              is zero, check if changing the user of the condition code will
6407              produce a valid insn.  If it won't, we can keep the original code
6408              in that insn by surrounding our operation with an XOR.  */
6409
6410           if (((old_code == NE && new_code == EQ)
6411                || (old_code == EQ && new_code == NE))
6412               && ! other_changed_previously && op1 == const0_rtx
6413               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6414               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6415             {
6416               rtx pat = PATTERN (other_insn), note = 0;
6417
6418               if ((recog_for_combine (&pat, other_insn, &note) < 0
6419                    && ! check_asm_operands (pat)))
6420                 {
6421                   *cc_use = old_cc_use;
6422                   other_changed = 0;
6423
6424                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6425                                              gen_int_mode (mask,
6426                                                            GET_MODE (op0)));
6427                 }
6428             }
6429         }
6430
6431       if (other_changed)
6432         undobuf.other_insn = other_insn;
6433
6434       /* Otherwise, if we didn't previously have a COMPARE in the
6435          correct mode, we need one.  */
6436       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6437         {
6438           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6439           src = SET_SRC (x);
6440         }
6441       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6442         {
6443           SUBST (SET_SRC (x), op0);
6444           src = SET_SRC (x);
6445         }
6446       /* Otherwise, update the COMPARE if needed.  */
6447       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6448         {
6449           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6450           src = SET_SRC (x);
6451         }
6452     }
6453   else
6454     {
6455       /* Get SET_SRC in a form where we have placed back any
6456          compound expressions.  Then do the checks below.  */
6457       src = make_compound_operation (src, SET);
6458       SUBST (SET_SRC (x), src);
6459     }
6460
6461   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6462      and X being a REG or (subreg (reg)), we may be able to convert this to
6463      (set (subreg:m2 x) (op)).
6464
6465      We can always do this if M1 is narrower than M2 because that means that
6466      we only care about the low bits of the result.
6467
6468      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6469      perform a narrower operation than requested since the high-order bits will
6470      be undefined.  On machine where it is defined, this transformation is safe
6471      as long as M1 and M2 have the same number of words.  */
6472
6473   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6474       && !OBJECT_P (SUBREG_REG (src))
6475       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6476            / UNITS_PER_WORD)
6477           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6478                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6479 #ifndef WORD_REGISTER_OPERATIONS
6480       && (GET_MODE_SIZE (GET_MODE (src))
6481         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6482 #endif
6483 #ifdef CANNOT_CHANGE_MODE_CLASS
6484       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6485             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6486                                          GET_MODE (SUBREG_REG (src)),
6487                                          GET_MODE (src)))
6488 #endif
6489       && (REG_P (dest)
6490           || (GET_CODE (dest) == SUBREG
6491               && REG_P (SUBREG_REG (dest)))))
6492     {
6493       SUBST (SET_DEST (x),
6494              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6495                                       dest));
6496       SUBST (SET_SRC (x), SUBREG_REG (src));
6497
6498       src = SET_SRC (x), dest = SET_DEST (x);
6499     }
6500
6501 #ifdef HAVE_cc0
6502   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6503      in SRC.  */
6504   if (dest == cc0_rtx
6505       && GET_CODE (src) == SUBREG
6506       && subreg_lowpart_p (src)
6507       && (GET_MODE_PRECISION (GET_MODE (src))
6508           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6509     {
6510       rtx inner = SUBREG_REG (src);
6511       enum machine_mode inner_mode = GET_MODE (inner);
6512
6513       /* Here we make sure that we don't have a sign bit on.  */
6514       if (val_signbit_known_clear_p (GET_MODE (src),
6515                                      nonzero_bits (inner, inner_mode)))
6516         {
6517           SUBST (SET_SRC (x), inner);
6518           src = SET_SRC (x);
6519         }
6520     }
6521 #endif
6522
6523 #ifdef LOAD_EXTEND_OP
6524   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6525      would require a paradoxical subreg.  Replace the subreg with a
6526      zero_extend to avoid the reload that would otherwise be required.  */
6527
6528   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6529       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6530       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6531       && SUBREG_BYTE (src) == 0
6532       && paradoxical_subreg_p (src)
6533       && MEM_P (SUBREG_REG (src)))
6534     {
6535       SUBST (SET_SRC (x),
6536              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6537                             GET_MODE (src), SUBREG_REG (src)));
6538
6539       src = SET_SRC (x);
6540     }
6541 #endif
6542
6543   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6544      are comparing an item known to be 0 or -1 against 0, use a logical
6545      operation instead. Check for one of the arms being an IOR of the other
6546      arm with some value.  We compute three terms to be IOR'ed together.  In
6547      practice, at most two will be nonzero.  Then we do the IOR's.  */
6548
6549   if (GET_CODE (dest) != PC
6550       && GET_CODE (src) == IF_THEN_ELSE
6551       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6552       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6553       && XEXP (XEXP (src, 0), 1) == const0_rtx
6554       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6555 #ifdef HAVE_conditional_move
6556       && ! can_conditionally_move_p (GET_MODE (src))
6557 #endif
6558       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6559                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6560           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6561       && ! side_effects_p (src))
6562     {
6563       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6564                       ? XEXP (src, 1) : XEXP (src, 2));
6565       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6566                    ? XEXP (src, 2) : XEXP (src, 1));
6567       rtx term1 = const0_rtx, term2, term3;
6568
6569       if (GET_CODE (true_rtx) == IOR
6570           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6571         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6572       else if (GET_CODE (true_rtx) == IOR
6573                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6574         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6575       else if (GET_CODE (false_rtx) == IOR
6576                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6577         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6578       else if (GET_CODE (false_rtx) == IOR
6579                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6580         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6581
6582       term2 = simplify_gen_binary (AND, GET_MODE (src),
6583                                    XEXP (XEXP (src, 0), 0), true_rtx);
6584       term3 = simplify_gen_binary (AND, GET_MODE (src),
6585                                    simplify_gen_unary (NOT, GET_MODE (src),
6586                                                        XEXP (XEXP (src, 0), 0),
6587                                                        GET_MODE (src)),
6588                                    false_rtx);
6589
6590       SUBST (SET_SRC (x),
6591              simplify_gen_binary (IOR, GET_MODE (src),
6592                                   simplify_gen_binary (IOR, GET_MODE (src),
6593                                                        term1, term2),
6594                                   term3));
6595
6596       src = SET_SRC (x);
6597     }
6598
6599   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6600      whole thing fail.  */
6601   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6602     return src;
6603   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6604     return dest;
6605   else
6606     /* Convert this into a field assignment operation, if possible.  */
6607     return make_field_assignment (x);
6608 }
6609 \f
6610 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6611    result.  */
6612
6613 static rtx
6614 simplify_logical (rtx x)
6615 {
6616   enum machine_mode mode = GET_MODE (x);
6617   rtx op0 = XEXP (x, 0);
6618   rtx op1 = XEXP (x, 1);
6619
6620   switch (GET_CODE (x))
6621     {
6622     case AND:
6623       /* We can call simplify_and_const_int only if we don't lose
6624          any (sign) bits when converting INTVAL (op1) to
6625          "unsigned HOST_WIDE_INT".  */
6626       if (CONST_INT_P (op1)
6627           && (HWI_COMPUTABLE_MODE_P (mode)
6628               || INTVAL (op1) > 0))
6629         {
6630           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6631           if (GET_CODE (x) != AND)
6632             return x;
6633
6634           op0 = XEXP (x, 0);
6635           op1 = XEXP (x, 1);
6636         }
6637
6638       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6639          apply the distributive law and then the inverse distributive
6640          law to see if things simplify.  */
6641       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6642         {
6643           rtx result = distribute_and_simplify_rtx (x, 0);
6644           if (result)
6645             return result;
6646         }
6647       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6648         {
6649           rtx result = distribute_and_simplify_rtx (x, 1);
6650           if (result)
6651             return result;
6652         }
6653       break;
6654
6655     case IOR:
6656       /* If we have (ior (and A B) C), apply the distributive law and then
6657          the inverse distributive law to see if things simplify.  */
6658
6659       if (GET_CODE (op0) == AND)
6660         {
6661           rtx result = distribute_and_simplify_rtx (x, 0);
6662           if (result)
6663             return result;
6664         }
6665
6666       if (GET_CODE (op1) == AND)
6667         {
6668           rtx result = distribute_and_simplify_rtx (x, 1);
6669           if (result)
6670             return result;
6671         }
6672       break;
6673
6674     default:
6675       gcc_unreachable ();
6676     }
6677
6678   return x;
6679 }
6680 \f
6681 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6682    operations" because they can be replaced with two more basic operations.
6683    ZERO_EXTEND is also considered "compound" because it can be replaced with
6684    an AND operation, which is simpler, though only one operation.
6685
6686    The function expand_compound_operation is called with an rtx expression
6687    and will convert it to the appropriate shifts and AND operations,
6688    simplifying at each stage.
6689
6690    The function make_compound_operation is called to convert an expression
6691    consisting of shifts and ANDs into the equivalent compound expression.
6692    It is the inverse of this function, loosely speaking.  */
6693
6694 static rtx
6695 expand_compound_operation (rtx x)
6696 {
6697   unsigned HOST_WIDE_INT pos = 0, len;
6698   int unsignedp = 0;
6699   unsigned int modewidth;
6700   rtx tem;
6701
6702   switch (GET_CODE (x))
6703     {
6704     case ZERO_EXTEND:
6705       unsignedp = 1;
6706     case SIGN_EXTEND:
6707       /* We can't necessarily use a const_int for a multiword mode;
6708          it depends on implicitly extending the value.
6709          Since we don't know the right way to extend it,
6710          we can't tell whether the implicit way is right.
6711
6712          Even for a mode that is no wider than a const_int,
6713          we can't win, because we need to sign extend one of its bits through
6714          the rest of it, and we don't know which bit.  */
6715       if (CONST_INT_P (XEXP (x, 0)))
6716         return x;
6717
6718       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6719          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6720          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6721          reloaded. If not for that, MEM's would very rarely be safe.
6722
6723          Reject MODEs bigger than a word, because we might not be able
6724          to reference a two-register group starting with an arbitrary register
6725          (and currently gen_lowpart might crash for a SUBREG).  */
6726
6727       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6728         return x;
6729
6730       /* Reject MODEs that aren't scalar integers because turning vector
6731          or complex modes into shifts causes problems.  */
6732
6733       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6734         return x;
6735
6736       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6737       /* If the inner object has VOIDmode (the only way this can happen
6738          is if it is an ASM_OPERANDS), we can't do anything since we don't
6739          know how much masking to do.  */
6740       if (len == 0)
6741         return x;
6742
6743       break;
6744
6745     case ZERO_EXTRACT:
6746       unsignedp = 1;
6747
6748       /* ... fall through ...  */
6749
6750     case SIGN_EXTRACT:
6751       /* If the operand is a CLOBBER, just return it.  */
6752       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6753         return XEXP (x, 0);
6754
6755       if (!CONST_INT_P (XEXP (x, 1))
6756           || !CONST_INT_P (XEXP (x, 2))
6757           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6758         return x;
6759
6760       /* Reject MODEs that aren't scalar integers because turning vector
6761          or complex modes into shifts causes problems.  */
6762
6763       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6764         return x;
6765
6766       len = INTVAL (XEXP (x, 1));
6767       pos = INTVAL (XEXP (x, 2));
6768
6769       /* This should stay within the object being extracted, fail otherwise.  */
6770       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6771         return x;
6772
6773       if (BITS_BIG_ENDIAN)
6774         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6775
6776       break;
6777
6778     default:
6779       return x;
6780     }
6781   /* Convert sign extension to zero extension, if we know that the high
6782      bit is not set, as this is easier to optimize.  It will be converted
6783      back to cheaper alternative in make_extraction.  */
6784   if (GET_CODE (x) == SIGN_EXTEND
6785       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6786           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6787                 & ~(((unsigned HOST_WIDE_INT)
6788                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6789                      >> 1))
6790                == 0)))
6791     {
6792       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6793       rtx temp2 = expand_compound_operation (temp);
6794
6795       /* Make sure this is a profitable operation.  */
6796       if (set_src_cost (x, optimize_this_for_speed_p)
6797           > set_src_cost (temp2, optimize_this_for_speed_p))
6798        return temp2;
6799       else if (set_src_cost (x, optimize_this_for_speed_p)
6800                > set_src_cost (temp, optimize_this_for_speed_p))
6801        return temp;
6802       else
6803        return x;
6804     }
6805
6806   /* We can optimize some special cases of ZERO_EXTEND.  */
6807   if (GET_CODE (x) == ZERO_EXTEND)
6808     {
6809       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6810          know that the last value didn't have any inappropriate bits
6811          set.  */
6812       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6813           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6814           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6815           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6816               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6817         return XEXP (XEXP (x, 0), 0);
6818
6819       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6820       if (GET_CODE (XEXP (x, 0)) == SUBREG
6821           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6822           && subreg_lowpart_p (XEXP (x, 0))
6823           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6824           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6825               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6826         return SUBREG_REG (XEXP (x, 0));
6827
6828       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6829          is a comparison and STORE_FLAG_VALUE permits.  This is like
6830          the first case, but it works even when GET_MODE (x) is larger
6831          than HOST_WIDE_INT.  */
6832       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6833           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6834           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6835           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6836               <= HOST_BITS_PER_WIDE_INT)
6837           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6838         return XEXP (XEXP (x, 0), 0);
6839
6840       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6841       if (GET_CODE (XEXP (x, 0)) == SUBREG
6842           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6843           && subreg_lowpart_p (XEXP (x, 0))
6844           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6845           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6846               <= HOST_BITS_PER_WIDE_INT)
6847           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6848         return SUBREG_REG (XEXP (x, 0));
6849
6850     }
6851
6852   /* If we reach here, we want to return a pair of shifts.  The inner
6853      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6854      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6855      logical depending on the value of UNSIGNEDP.
6856
6857      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6858      converted into an AND of a shift.
6859
6860      We must check for the case where the left shift would have a negative
6861      count.  This can happen in a case like (x >> 31) & 255 on machines
6862      that can't shift by a constant.  On those machines, we would first
6863      combine the shift with the AND to produce a variable-position
6864      extraction.  Then the constant of 31 would be substituted in
6865      to produce such a position.  */
6866
6867   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6868   if (modewidth >= pos + len)
6869     {
6870       enum machine_mode mode = GET_MODE (x);
6871       tem = gen_lowpart (mode, XEXP (x, 0));
6872       if (!tem || GET_CODE (tem) == CLOBBER)
6873         return x;
6874       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6875                                   tem, modewidth - pos - len);
6876       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6877                                   mode, tem, modewidth - len);
6878     }
6879   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6880     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6881                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6882                                                         GET_MODE (x),
6883                                                         XEXP (x, 0), pos),
6884                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6885   else
6886     /* Any other cases we can't handle.  */
6887     return x;
6888
6889   /* If we couldn't do this for some reason, return the original
6890      expression.  */
6891   if (GET_CODE (tem) == CLOBBER)
6892     return x;
6893
6894   return tem;
6895 }
6896 \f
6897 /* X is a SET which contains an assignment of one object into
6898    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6899    or certain SUBREGS). If possible, convert it into a series of
6900    logical operations.
6901
6902    We half-heartedly support variable positions, but do not at all
6903    support variable lengths.  */
6904
6905 static const_rtx
6906 expand_field_assignment (const_rtx x)
6907 {
6908   rtx inner;
6909   rtx pos;                      /* Always counts from low bit.  */
6910   int len;
6911   rtx mask, cleared, masked;
6912   enum machine_mode compute_mode;
6913
6914   /* Loop until we find something we can't simplify.  */
6915   while (1)
6916     {
6917       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6918           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6919         {
6920           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6921           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6922           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6923         }
6924       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6925                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6926         {
6927           inner = XEXP (SET_DEST (x), 0);
6928           len = INTVAL (XEXP (SET_DEST (x), 1));
6929           pos = XEXP (SET_DEST (x), 2);
6930
6931           /* A constant position should stay within the width of INNER.  */
6932           if (CONST_INT_P (pos)
6933               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6934             break;
6935
6936           if (BITS_BIG_ENDIAN)
6937             {
6938               if (CONST_INT_P (pos))
6939                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6940                                - INTVAL (pos));
6941               else if (GET_CODE (pos) == MINUS
6942                        && CONST_INT_P (XEXP (pos, 1))
6943                        && (INTVAL (XEXP (pos, 1))
6944                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6945                 /* If position is ADJUST - X, new position is X.  */
6946                 pos = XEXP (pos, 0);
6947               else
6948                 {
6949                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6950                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6951                                              gen_int_mode (prec - len,
6952                                                            GET_MODE (pos)),
6953                                              pos);
6954                 }
6955             }
6956         }
6957
6958       /* A SUBREG between two modes that occupy the same numbers of words
6959          can be done by moving the SUBREG to the source.  */
6960       else if (GET_CODE (SET_DEST (x)) == SUBREG
6961                /* We need SUBREGs to compute nonzero_bits properly.  */
6962                && nonzero_sign_valid
6963                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6964                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6965                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6966                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6967         {
6968           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6969                            gen_lowpart
6970                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6971                             SET_SRC (x)));
6972           continue;
6973         }
6974       else
6975         break;
6976
6977       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6978         inner = SUBREG_REG (inner);
6979
6980       compute_mode = GET_MODE (inner);
6981
6982       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6983       if (! SCALAR_INT_MODE_P (compute_mode))
6984         {
6985           enum machine_mode imode;
6986
6987           /* Don't do anything for vector or complex integral types.  */
6988           if (! FLOAT_MODE_P (compute_mode))
6989             break;
6990
6991           /* Try to find an integral mode to pun with.  */
6992           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6993           if (imode == BLKmode)
6994             break;
6995
6996           compute_mode = imode;
6997           inner = gen_lowpart (imode, inner);
6998         }
6999
7000       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7001       if (len >= HOST_BITS_PER_WIDE_INT)
7002         break;
7003
7004       /* Now compute the equivalent expression.  Make a copy of INNER
7005          for the SET_DEST in case it is a MEM into which we will substitute;
7006          we don't want shared RTL in that case.  */
7007       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
7008                            compute_mode);
7009       cleared = simplify_gen_binary (AND, compute_mode,
7010                                      simplify_gen_unary (NOT, compute_mode,
7011                                        simplify_gen_binary (ASHIFT,
7012                                                             compute_mode,
7013                                                             mask, pos),
7014                                        compute_mode),
7015                                      inner);
7016       masked = simplify_gen_binary (ASHIFT, compute_mode,
7017                                     simplify_gen_binary (
7018                                       AND, compute_mode,
7019                                       gen_lowpart (compute_mode, SET_SRC (x)),
7020                                       mask),
7021                                     pos);
7022
7023       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7024                        simplify_gen_binary (IOR, compute_mode,
7025                                             cleared, masked));
7026     }
7027
7028   return x;
7029 }
7030 \f
7031 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7032    it is an RTX that represents the (variable) starting position; otherwise,
7033    POS is the (constant) starting bit position.  Both are counted from the LSB.
7034
7035    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7036
7037    IN_DEST is nonzero if this is a reference in the destination of a SET.
7038    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7039    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7040    be used.
7041
7042    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7043    ZERO_EXTRACT should be built even for bits starting at bit 0.
7044
7045    MODE is the desired mode of the result (if IN_DEST == 0).
7046
7047    The result is an RTX for the extraction or NULL_RTX if the target
7048    can't handle it.  */
7049
7050 static rtx
7051 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7052                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7053                  int in_dest, int in_compare)
7054 {
7055   /* This mode describes the size of the storage area
7056      to fetch the overall value from.  Within that, we
7057      ignore the POS lowest bits, etc.  */
7058   enum machine_mode is_mode = GET_MODE (inner);
7059   enum machine_mode inner_mode;
7060   enum machine_mode wanted_inner_mode;
7061   enum machine_mode wanted_inner_reg_mode = word_mode;
7062   enum machine_mode pos_mode = word_mode;
7063   enum machine_mode extraction_mode = word_mode;
7064   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7065   rtx new_rtx = 0;
7066   rtx orig_pos_rtx = pos_rtx;
7067   HOST_WIDE_INT orig_pos;
7068
7069   if (pos_rtx && CONST_INT_P (pos_rtx))
7070     pos = INTVAL (pos_rtx), pos_rtx = 0;
7071
7072   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7073     {
7074       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7075          consider just the QI as the memory to extract from.
7076          The subreg adds or removes high bits; its mode is
7077          irrelevant to the meaning of this extraction,
7078          since POS and LEN count from the lsb.  */
7079       if (MEM_P (SUBREG_REG (inner)))
7080         is_mode = GET_MODE (SUBREG_REG (inner));
7081       inner = SUBREG_REG (inner);
7082     }
7083   else if (GET_CODE (inner) == ASHIFT
7084            && CONST_INT_P (XEXP (inner, 1))
7085            && pos_rtx == 0 && pos == 0
7086            && len > UINTVAL (XEXP (inner, 1)))
7087     {
7088       /* We're extracting the least significant bits of an rtx
7089          (ashift X (const_int C)), where LEN > C.  Extract the
7090          least significant (LEN - C) bits of X, giving an rtx
7091          whose mode is MODE, then shift it left C times.  */
7092       new_rtx = make_extraction (mode, XEXP (inner, 0),
7093                              0, 0, len - INTVAL (XEXP (inner, 1)),
7094                              unsignedp, in_dest, in_compare);
7095       if (new_rtx != 0)
7096         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7097     }
7098   else if (GET_CODE (inner) == TRUNCATE)
7099     inner = XEXP (inner, 0);
7100
7101   inner_mode = GET_MODE (inner);
7102
7103   /* See if this can be done without an extraction.  We never can if the
7104      width of the field is not the same as that of some integer mode. For
7105      registers, we can only avoid the extraction if the position is at the
7106      low-order bit and this is either not in the destination or we have the
7107      appropriate STRICT_LOW_PART operation available.
7108
7109      For MEM, we can avoid an extract if the field starts on an appropriate
7110      boundary and we can change the mode of the memory reference.  */
7111
7112   if (tmode != BLKmode
7113       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7114            && !MEM_P (inner)
7115            && (inner_mode == tmode
7116                || !REG_P (inner)
7117                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7118                || reg_truncated_to_mode (tmode, inner))
7119            && (! in_dest
7120                || (REG_P (inner)
7121                    && have_insn_for (STRICT_LOW_PART, tmode))))
7122           || (MEM_P (inner) && pos_rtx == 0
7123               && (pos
7124                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7125                      : BITS_PER_UNIT)) == 0
7126               /* We can't do this if we are widening INNER_MODE (it
7127                  may not be aligned, for one thing).  */
7128               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7129               && (inner_mode == tmode
7130                   || (! mode_dependent_address_p (XEXP (inner, 0),
7131                                                   MEM_ADDR_SPACE (inner))
7132                       && ! MEM_VOLATILE_P (inner))))))
7133     {
7134       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7135          field.  If the original and current mode are the same, we need not
7136          adjust the offset.  Otherwise, we do if bytes big endian.
7137
7138          If INNER is not a MEM, get a piece consisting of just the field
7139          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7140
7141       if (MEM_P (inner))
7142         {
7143           HOST_WIDE_INT offset;
7144
7145           /* POS counts from lsb, but make OFFSET count in memory order.  */
7146           if (BYTES_BIG_ENDIAN)
7147             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7148           else
7149             offset = pos / BITS_PER_UNIT;
7150
7151           new_rtx = adjust_address_nv (inner, tmode, offset);
7152         }
7153       else if (REG_P (inner))
7154         {
7155           if (tmode != inner_mode)
7156             {
7157               /* We can't call gen_lowpart in a DEST since we
7158                  always want a SUBREG (see below) and it would sometimes
7159                  return a new hard register.  */
7160               if (pos || in_dest)
7161                 {
7162                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7163
7164                   if (WORDS_BIG_ENDIAN
7165                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7166                     final_word = ((GET_MODE_SIZE (inner_mode)
7167                                    - GET_MODE_SIZE (tmode))
7168                                   / UNITS_PER_WORD) - final_word;
7169
7170                   final_word *= UNITS_PER_WORD;
7171                   if (BYTES_BIG_ENDIAN &&
7172                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7173                     final_word += (GET_MODE_SIZE (inner_mode)
7174                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7175
7176                   /* Avoid creating invalid subregs, for example when
7177                      simplifying (x>>32)&255.  */
7178                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7179                     return NULL_RTX;
7180
7181                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7182                 }
7183               else
7184                 new_rtx = gen_lowpart (tmode, inner);
7185             }
7186           else
7187             new_rtx = inner;
7188         }
7189       else
7190         new_rtx = force_to_mode (inner, tmode,
7191                              len >= HOST_BITS_PER_WIDE_INT
7192                              ? ~(unsigned HOST_WIDE_INT) 0
7193                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7194                              0);
7195
7196       /* If this extraction is going into the destination of a SET,
7197          make a STRICT_LOW_PART unless we made a MEM.  */
7198
7199       if (in_dest)
7200         return (MEM_P (new_rtx) ? new_rtx
7201                 : (GET_CODE (new_rtx) != SUBREG
7202                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7203                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7204
7205       if (mode == tmode)
7206         return new_rtx;
7207
7208       if (CONST_SCALAR_INT_P (new_rtx))
7209         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7210                                          mode, new_rtx, tmode);
7211
7212       /* If we know that no extraneous bits are set, and that the high
7213          bit is not set, convert the extraction to the cheaper of
7214          sign and zero extension, that are equivalent in these cases.  */
7215       if (flag_expensive_optimizations
7216           && (HWI_COMPUTABLE_MODE_P (tmode)
7217               && ((nonzero_bits (new_rtx, tmode)
7218                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7219                   == 0)))
7220         {
7221           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7222           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7223
7224           /* Prefer ZERO_EXTENSION, since it gives more information to
7225              backends.  */
7226           if (set_src_cost (temp, optimize_this_for_speed_p)
7227               <= set_src_cost (temp1, optimize_this_for_speed_p))
7228             return temp;
7229           return temp1;
7230         }
7231
7232       /* Otherwise, sign- or zero-extend unless we already are in the
7233          proper mode.  */
7234
7235       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7236                              mode, new_rtx));
7237     }
7238
7239   /* Unless this is a COMPARE or we have a funny memory reference,
7240      don't do anything with zero-extending field extracts starting at
7241      the low-order bit since they are simple AND operations.  */
7242   if (pos_rtx == 0 && pos == 0 && ! in_dest
7243       && ! in_compare && unsignedp)
7244     return 0;
7245
7246   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7247      if the position is not a constant and the length is not 1.  In all
7248      other cases, we would only be going outside our object in cases when
7249      an original shift would have been undefined.  */
7250   if (MEM_P (inner)
7251       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7252           || (pos_rtx != 0 && len != 1)))
7253     return 0;
7254
7255   enum extraction_pattern pattern = (in_dest ? EP_insv
7256                                      : unsignedp ? EP_extzv : EP_extv);
7257
7258   /* If INNER is not from memory, we want it to have the mode of a register
7259      extraction pattern's structure operand, or word_mode if there is no
7260      such pattern.  The same applies to extraction_mode and pos_mode
7261      and their respective operands.
7262
7263      For memory, assume that the desired extraction_mode and pos_mode
7264      are the same as for a register operation, since at present we don't
7265      have named patterns for aligned memory structures.  */
7266   struct extraction_insn insn;
7267   if (get_best_reg_extraction_insn (&insn, pattern,
7268                                     GET_MODE_BITSIZE (inner_mode), mode))
7269     {
7270       wanted_inner_reg_mode = insn.struct_mode;
7271       pos_mode = insn.pos_mode;
7272       extraction_mode = insn.field_mode;
7273     }
7274
7275   /* Never narrow an object, since that might not be safe.  */
7276
7277   if (mode != VOIDmode
7278       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7279     extraction_mode = mode;
7280
7281   if (!MEM_P (inner))
7282     wanted_inner_mode = wanted_inner_reg_mode;
7283   else
7284     {
7285       /* Be careful not to go beyond the extracted object and maintain the
7286          natural alignment of the memory.  */
7287       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7288       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7289              > GET_MODE_BITSIZE (wanted_inner_mode))
7290         {
7291           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7292           gcc_assert (wanted_inner_mode != VOIDmode);
7293         }
7294     }
7295
7296   orig_pos = pos;
7297
7298   if (BITS_BIG_ENDIAN)
7299     {
7300       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7301          BITS_BIG_ENDIAN style.  If position is constant, compute new
7302          position.  Otherwise, build subtraction.
7303          Note that POS is relative to the mode of the original argument.
7304          If it's a MEM we need to recompute POS relative to that.
7305          However, if we're extracting from (or inserting into) a register,
7306          we want to recompute POS relative to wanted_inner_mode.  */
7307       int width = (MEM_P (inner)
7308                    ? GET_MODE_BITSIZE (is_mode)
7309                    : GET_MODE_BITSIZE (wanted_inner_mode));
7310
7311       if (pos_rtx == 0)
7312         pos = width - len - pos;
7313       else
7314         pos_rtx
7315           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7316                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7317                            pos_rtx);
7318       /* POS may be less than 0 now, but we check for that below.
7319          Note that it can only be less than 0 if !MEM_P (inner).  */
7320     }
7321
7322   /* If INNER has a wider mode, and this is a constant extraction, try to
7323      make it smaller and adjust the byte to point to the byte containing
7324      the value.  */
7325   if (wanted_inner_mode != VOIDmode
7326       && inner_mode != wanted_inner_mode
7327       && ! pos_rtx
7328       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7329       && MEM_P (inner)
7330       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7331       && ! MEM_VOLATILE_P (inner))
7332     {
7333       int offset = 0;
7334
7335       /* The computations below will be correct if the machine is big
7336          endian in both bits and bytes or little endian in bits and bytes.
7337          If it is mixed, we must adjust.  */
7338
7339       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7340          adjust OFFSET to compensate.  */
7341       if (BYTES_BIG_ENDIAN
7342           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7343         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7344
7345       /* We can now move to the desired byte.  */
7346       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7347                 * GET_MODE_SIZE (wanted_inner_mode);
7348       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7349
7350       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7351           && is_mode != wanted_inner_mode)
7352         offset = (GET_MODE_SIZE (is_mode)
7353                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7354
7355       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7356     }
7357
7358   /* If INNER is not memory, get it into the proper mode.  If we are changing
7359      its mode, POS must be a constant and smaller than the size of the new
7360      mode.  */
7361   else if (!MEM_P (inner))
7362     {
7363       /* On the LHS, don't create paradoxical subregs implicitely truncating
7364          the register unless TRULY_NOOP_TRUNCATION.  */
7365       if (in_dest
7366           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7367                                              wanted_inner_mode))
7368         return NULL_RTX;
7369
7370       if (GET_MODE (inner) != wanted_inner_mode
7371           && (pos_rtx != 0
7372               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7373         return NULL_RTX;
7374
7375       if (orig_pos < 0)
7376         return NULL_RTX;
7377
7378       inner = force_to_mode (inner, wanted_inner_mode,
7379                              pos_rtx
7380                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7381                              ? ~(unsigned HOST_WIDE_INT) 0
7382                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7383                                 << orig_pos),
7384                              0);
7385     }
7386
7387   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7388      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7389   if (pos_rtx != 0
7390       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7391     {
7392       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7393                                      GET_MODE (pos_rtx));
7394
7395       /* If we know that no extraneous bits are set, and that the high
7396          bit is not set, convert extraction to cheaper one - either
7397          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7398          cases.  */
7399       if (flag_expensive_optimizations
7400           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7401               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7402                    & ~(((unsigned HOST_WIDE_INT)
7403                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7404                        >> 1))
7405                   == 0)))
7406         {
7407           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7408                                           GET_MODE (pos_rtx));
7409
7410           /* Prefer ZERO_EXTENSION, since it gives more information to
7411              backends.  */
7412           if (set_src_cost (temp1, optimize_this_for_speed_p)
7413               < set_src_cost (temp, optimize_this_for_speed_p))
7414             temp = temp1;
7415         }
7416       pos_rtx = temp;
7417     }
7418
7419   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7420      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7421      be a CONST_INT.  */
7422   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7423     pos_rtx = orig_pos_rtx;
7424
7425   else if (pos_rtx == 0)
7426     pos_rtx = GEN_INT (pos);
7427
7428   /* Make the required operation.  See if we can use existing rtx.  */
7429   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7430                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7431   if (! in_dest)
7432     new_rtx = gen_lowpart (mode, new_rtx);
7433
7434   return new_rtx;
7435 }
7436 \f
7437 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7438    with any other operations in X.  Return X without that shift if so.  */
7439
7440 static rtx
7441 extract_left_shift (rtx x, int count)
7442 {
7443   enum rtx_code code = GET_CODE (x);
7444   enum machine_mode mode = GET_MODE (x);
7445   rtx tem;
7446
7447   switch (code)
7448     {
7449     case ASHIFT:
7450       /* This is the shift itself.  If it is wide enough, we will return
7451          either the value being shifted if the shift count is equal to
7452          COUNT or a shift for the difference.  */
7453       if (CONST_INT_P (XEXP (x, 1))
7454           && INTVAL (XEXP (x, 1)) >= count)
7455         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7456                                      INTVAL (XEXP (x, 1)) - count);
7457       break;
7458
7459     case NEG:  case NOT:
7460       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7461         return simplify_gen_unary (code, mode, tem, mode);
7462
7463       break;
7464
7465     case PLUS:  case IOR:  case XOR:  case AND:
7466       /* If we can safely shift this constant and we find the inner shift,
7467          make a new operation.  */
7468       if (CONST_INT_P (XEXP (x, 1))
7469           && (UINTVAL (XEXP (x, 1))
7470               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7471           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7472         {
7473           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7474           return simplify_gen_binary (code, mode, tem,
7475                                       gen_int_mode (val, mode));
7476         }
7477       break;
7478
7479     default:
7480       break;
7481     }
7482
7483   return 0;
7484 }
7485 \f
7486 /* Look at the expression rooted at X.  Look for expressions
7487    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7488    Form these expressions.
7489
7490    Return the new rtx, usually just X.
7491
7492    Also, for machines like the VAX that don't have logical shift insns,
7493    try to convert logical to arithmetic shift operations in cases where
7494    they are equivalent.  This undoes the canonicalizations to logical
7495    shifts done elsewhere.
7496
7497    We try, as much as possible, to re-use rtl expressions to save memory.
7498
7499    IN_CODE says what kind of expression we are processing.  Normally, it is
7500    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7501    being kludges), it is MEM.  When processing the arguments of a comparison
7502    or a COMPARE against zero, it is COMPARE.  */
7503
7504 rtx
7505 make_compound_operation (rtx x, enum rtx_code in_code)
7506 {
7507   enum rtx_code code = GET_CODE (x);
7508   enum machine_mode mode = GET_MODE (x);
7509   int mode_width = GET_MODE_PRECISION (mode);
7510   rtx rhs, lhs;
7511   enum rtx_code next_code;
7512   int i, j;
7513   rtx new_rtx = 0;
7514   rtx tem;
7515   const char *fmt;
7516
7517   /* Select the code to be used in recursive calls.  Once we are inside an
7518      address, we stay there.  If we have a comparison, set to COMPARE,
7519      but once inside, go back to our default of SET.  */
7520
7521   next_code = (code == MEM ? MEM
7522                : ((code == PLUS || code == MINUS)
7523                   && SCALAR_INT_MODE_P (mode)) ? MEM
7524                : ((code == COMPARE || COMPARISON_P (x))
7525                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7526                : in_code == COMPARE ? SET : in_code);
7527
7528   /* Process depending on the code of this operation.  If NEW is set
7529      nonzero, it will be returned.  */
7530
7531   switch (code)
7532     {
7533     case ASHIFT:
7534       /* Convert shifts by constants into multiplications if inside
7535          an address.  */
7536       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7537           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7538           && INTVAL (XEXP (x, 1)) >= 0
7539           && SCALAR_INT_MODE_P (mode))
7540         {
7541           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7542           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7543
7544           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7545           if (GET_CODE (new_rtx) == NEG)
7546             {
7547               new_rtx = XEXP (new_rtx, 0);
7548               multval = -multval;
7549             }
7550           multval = trunc_int_for_mode (multval, mode);
7551           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7552         }
7553       break;
7554
7555     case PLUS:
7556       lhs = XEXP (x, 0);
7557       rhs = XEXP (x, 1);
7558       lhs = make_compound_operation (lhs, next_code);
7559       rhs = make_compound_operation (rhs, next_code);
7560       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7561           && SCALAR_INT_MODE_P (mode))
7562         {
7563           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7564                                      XEXP (lhs, 1));
7565           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7566         }
7567       else if (GET_CODE (lhs) == MULT
7568                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7569         {
7570           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7571                                      simplify_gen_unary (NEG, mode,
7572                                                          XEXP (lhs, 1),
7573                                                          mode));
7574           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7575         }
7576       else
7577         {
7578           SUBST (XEXP (x, 0), lhs);
7579           SUBST (XEXP (x, 1), rhs);
7580           goto maybe_swap;
7581         }
7582       x = gen_lowpart (mode, new_rtx);
7583       goto maybe_swap;
7584
7585     case MINUS:
7586       lhs = XEXP (x, 0);
7587       rhs = XEXP (x, 1);
7588       lhs = make_compound_operation (lhs, next_code);
7589       rhs = make_compound_operation (rhs, next_code);
7590       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7591           && SCALAR_INT_MODE_P (mode))
7592         {
7593           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7594                                      XEXP (rhs, 1));
7595           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7596         }
7597       else if (GET_CODE (rhs) == MULT
7598                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7599         {
7600           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7601                                      simplify_gen_unary (NEG, mode,
7602                                                          XEXP (rhs, 1),
7603                                                          mode));
7604           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7605         }
7606       else
7607         {
7608           SUBST (XEXP (x, 0), lhs);
7609           SUBST (XEXP (x, 1), rhs);
7610           return x;
7611         }
7612       return gen_lowpart (mode, new_rtx);
7613
7614     case AND:
7615       /* If the second operand is not a constant, we can't do anything
7616          with it.  */
7617       if (!CONST_INT_P (XEXP (x, 1)))
7618         break;
7619
7620       /* If the constant is a power of two minus one and the first operand
7621          is a logical right shift, make an extraction.  */
7622       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7623           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7624         {
7625           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7626           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7627                                  0, in_code == COMPARE);
7628         }
7629
7630       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7631       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7632                && subreg_lowpart_p (XEXP (x, 0))
7633                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7634                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7635         {
7636           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7637                                          next_code);
7638           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7639                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7640                                  0, in_code == COMPARE);
7641         }
7642       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7643       else if ((GET_CODE (XEXP (x, 0)) == XOR
7644                 || GET_CODE (XEXP (x, 0)) == IOR)
7645                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7646                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7647                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7648         {
7649           /* Apply the distributive law, and then try to make extractions.  */
7650           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7651                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7652                                              XEXP (x, 1)),
7653                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7654                                              XEXP (x, 1)));
7655           new_rtx = make_compound_operation (new_rtx, in_code);
7656         }
7657
7658       /* If we are have (and (rotate X C) M) and C is larger than the number
7659          of bits in M, this is an extraction.  */
7660
7661       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7662                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7663                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7664                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7665         {
7666           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7667           new_rtx = make_extraction (mode, new_rtx,
7668                                  (GET_MODE_PRECISION (mode)
7669                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7670                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7671         }
7672
7673       /* On machines without logical shifts, if the operand of the AND is
7674          a logical shift and our mask turns off all the propagated sign
7675          bits, we can replace the logical shift with an arithmetic shift.  */
7676       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7677                && !have_insn_for (LSHIFTRT, mode)
7678                && have_insn_for (ASHIFTRT, mode)
7679                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7680                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7681                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7682                && mode_width <= HOST_BITS_PER_WIDE_INT)
7683         {
7684           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7685
7686           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7687           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7688             SUBST (XEXP (x, 0),
7689                    gen_rtx_ASHIFTRT (mode,
7690                                      make_compound_operation
7691                                      (XEXP (XEXP (x, 0), 0), next_code),
7692                                      XEXP (XEXP (x, 0), 1)));
7693         }
7694
7695       /* If the constant is one less than a power of two, this might be
7696          representable by an extraction even if no shift is present.
7697          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7698          we are in a COMPARE.  */
7699       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7700         new_rtx = make_extraction (mode,
7701                                make_compound_operation (XEXP (x, 0),
7702                                                         next_code),
7703                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7704
7705       /* If we are in a comparison and this is an AND with a power of two,
7706          convert this into the appropriate bit extract.  */
7707       else if (in_code == COMPARE
7708                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7709         new_rtx = make_extraction (mode,
7710                                make_compound_operation (XEXP (x, 0),
7711                                                         next_code),
7712                                i, NULL_RTX, 1, 1, 0, 1);
7713
7714       break;
7715
7716     case LSHIFTRT:
7717       /* If the sign bit is known to be zero, replace this with an
7718          arithmetic shift.  */
7719       if (have_insn_for (ASHIFTRT, mode)
7720           && ! have_insn_for (LSHIFTRT, mode)
7721           && mode_width <= HOST_BITS_PER_WIDE_INT
7722           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7723         {
7724           new_rtx = gen_rtx_ASHIFTRT (mode,
7725                                   make_compound_operation (XEXP (x, 0),
7726                                                            next_code),
7727                                   XEXP (x, 1));
7728           break;
7729         }
7730
7731       /* ... fall through ...  */
7732
7733     case ASHIFTRT:
7734       lhs = XEXP (x, 0);
7735       rhs = XEXP (x, 1);
7736
7737       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7738          this is a SIGN_EXTRACT.  */
7739       if (CONST_INT_P (rhs)
7740           && GET_CODE (lhs) == ASHIFT
7741           && CONST_INT_P (XEXP (lhs, 1))
7742           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7743           && INTVAL (XEXP (lhs, 1)) >= 0
7744           && INTVAL (rhs) < mode_width)
7745         {
7746           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7747           new_rtx = make_extraction (mode, new_rtx,
7748                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7749                                  NULL_RTX, mode_width - INTVAL (rhs),
7750                                  code == LSHIFTRT, 0, in_code == COMPARE);
7751           break;
7752         }
7753
7754       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7755          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7756          also do this for some cases of SIGN_EXTRACT, but it doesn't
7757          seem worth the effort; the case checked for occurs on Alpha.  */
7758
7759       if (!OBJECT_P (lhs)
7760           && ! (GET_CODE (lhs) == SUBREG
7761                 && (OBJECT_P (SUBREG_REG (lhs))))
7762           && CONST_INT_P (rhs)
7763           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7764           && INTVAL (rhs) < mode_width
7765           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7766         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7767                                0, NULL_RTX, mode_width - INTVAL (rhs),
7768                                code == LSHIFTRT, 0, in_code == COMPARE);
7769
7770       break;
7771
7772     case SUBREG:
7773       /* Call ourselves recursively on the inner expression.  If we are
7774          narrowing the object and it has a different RTL code from
7775          what it originally did, do this SUBREG as a force_to_mode.  */
7776       {
7777         rtx inner = SUBREG_REG (x), simplified;
7778         enum rtx_code subreg_code = in_code;
7779
7780         /* If in_code is COMPARE, it isn't always safe to pass it through
7781            to the recursive make_compound_operation call.  */
7782         if (subreg_code == COMPARE
7783             && (!subreg_lowpart_p (x)
7784                 || GET_CODE (inner) == SUBREG
7785                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7786                    is (const_int 0), rather than
7787                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7788                 || (GET_CODE (inner) == AND
7789                     && CONST_INT_P (XEXP (inner, 1))
7790                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7791                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7792                        >= GET_MODE_BITSIZE (mode))))
7793           subreg_code = SET;
7794
7795         tem = make_compound_operation (inner, subreg_code);
7796
7797         simplified
7798           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7799         if (simplified)
7800           tem = simplified;
7801
7802         if (GET_CODE (tem) != GET_CODE (inner)
7803             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7804             && subreg_lowpart_p (x))
7805           {
7806             rtx newer
7807               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7808
7809             /* If we have something other than a SUBREG, we might have
7810                done an expansion, so rerun ourselves.  */
7811             if (GET_CODE (newer) != SUBREG)
7812               newer = make_compound_operation (newer, in_code);
7813
7814             /* force_to_mode can expand compounds.  If it just re-expanded the
7815                compound, use gen_lowpart to convert to the desired mode.  */
7816             if (rtx_equal_p (newer, x)
7817                 /* Likewise if it re-expanded the compound only partially.
7818                    This happens for SUBREG of ZERO_EXTRACT if they extract
7819                    the same number of bits.  */
7820                 || (GET_CODE (newer) == SUBREG
7821                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7822                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7823                     && GET_CODE (inner) == AND
7824                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7825               return gen_lowpart (GET_MODE (x), tem);
7826
7827             return newer;
7828           }
7829
7830         if (simplified)
7831           return tem;
7832       }
7833       break;
7834
7835     default:
7836       break;
7837     }
7838
7839   if (new_rtx)
7840     {
7841       x = gen_lowpart (mode, new_rtx);
7842       code = GET_CODE (x);
7843     }
7844
7845   /* Now recursively process each operand of this operation.  We need to
7846      handle ZERO_EXTEND specially so that we don't lose track of the
7847      inner mode.  */
7848   if (GET_CODE (x) == ZERO_EXTEND)
7849     {
7850       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7851       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7852                                             new_rtx, GET_MODE (XEXP (x, 0)));
7853       if (tem)
7854         return tem;
7855       SUBST (XEXP (x, 0), new_rtx);
7856       return x;
7857     }
7858
7859   fmt = GET_RTX_FORMAT (code);
7860   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7861     if (fmt[i] == 'e')
7862       {
7863         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7864         SUBST (XEXP (x, i), new_rtx);
7865       }
7866     else if (fmt[i] == 'E')
7867       for (j = 0; j < XVECLEN (x, i); j++)
7868         {
7869           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7870           SUBST (XVECEXP (x, i, j), new_rtx);
7871         }
7872
7873  maybe_swap:
7874   /* If this is a commutative operation, the changes to the operands
7875      may have made it noncanonical.  */
7876   if (COMMUTATIVE_ARITH_P (x)
7877       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7878     {
7879       tem = XEXP (x, 0);
7880       SUBST (XEXP (x, 0), XEXP (x, 1));
7881       SUBST (XEXP (x, 1), tem);
7882     }
7883
7884   return x;
7885 }
7886 \f
7887 /* Given M see if it is a value that would select a field of bits
7888    within an item, but not the entire word.  Return -1 if not.
7889    Otherwise, return the starting position of the field, where 0 is the
7890    low-order bit.
7891
7892    *PLEN is set to the length of the field.  */
7893
7894 static int
7895 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7896 {
7897   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7898   int pos = m ? ctz_hwi (m) : -1;
7899   int len = 0;
7900
7901   if (pos >= 0)
7902     /* Now shift off the low-order zero bits and see if we have a
7903        power of two minus 1.  */
7904     len = exact_log2 ((m >> pos) + 1);
7905
7906   if (len <= 0)
7907     pos = -1;
7908
7909   *plen = len;
7910   return pos;
7911 }
7912 \f
7913 /* If X refers to a register that equals REG in value, replace these
7914    references with REG.  */
7915 static rtx
7916 canon_reg_for_combine (rtx x, rtx reg)
7917 {
7918   rtx op0, op1, op2;
7919   const char *fmt;
7920   int i;
7921   bool copied;
7922
7923   enum rtx_code code = GET_CODE (x);
7924   switch (GET_RTX_CLASS (code))
7925     {
7926     case RTX_UNARY:
7927       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7928       if (op0 != XEXP (x, 0))
7929         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7930                                    GET_MODE (reg));
7931       break;
7932
7933     case RTX_BIN_ARITH:
7934     case RTX_COMM_ARITH:
7935       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7936       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7937       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7938         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7939       break;
7940
7941     case RTX_COMPARE:
7942     case RTX_COMM_COMPARE:
7943       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7944       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7945       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7946         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7947                                         GET_MODE (op0), op0, op1);
7948       break;
7949
7950     case RTX_TERNARY:
7951     case RTX_BITFIELD_OPS:
7952       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7953       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7954       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7955       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7956         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7957                                      GET_MODE (op0), op0, op1, op2);
7958
7959     case RTX_OBJ:
7960       if (REG_P (x))
7961         {
7962           if (rtx_equal_p (get_last_value (reg), x)
7963               || rtx_equal_p (reg, get_last_value (x)))
7964             return reg;
7965           else
7966             break;
7967         }
7968
7969       /* fall through */
7970
7971     default:
7972       fmt = GET_RTX_FORMAT (code);
7973       copied = false;
7974       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7975         if (fmt[i] == 'e')
7976           {
7977             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7978             if (op != XEXP (x, i))
7979               {
7980                 if (!copied)
7981                   {
7982                     copied = true;
7983                     x = copy_rtx (x);
7984                   }
7985                 XEXP (x, i) = op;
7986               }
7987           }
7988         else if (fmt[i] == 'E')
7989           {
7990             int j;
7991             for (j = 0; j < XVECLEN (x, i); j++)
7992               {
7993                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7994                 if (op != XVECEXP (x, i, j))
7995                   {
7996                     if (!copied)
7997                       {
7998                         copied = true;
7999                         x = copy_rtx (x);
8000                       }
8001                     XVECEXP (x, i, j) = op;
8002                   }
8003               }
8004           }
8005
8006       break;
8007     }
8008
8009   return x;
8010 }
8011
8012 /* Return X converted to MODE.  If the value is already truncated to
8013    MODE we can just return a subreg even though in the general case we
8014    would need an explicit truncation.  */
8015
8016 static rtx
8017 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8018 {
8019   if (!CONST_INT_P (x)
8020       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8021       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8022       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8023     {
8024       /* Bit-cast X into an integer mode.  */
8025       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8026         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8027       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8028                               x, GET_MODE (x));
8029     }
8030
8031   return gen_lowpart (mode, x);
8032 }
8033
8034 /* See if X can be simplified knowing that we will only refer to it in
8035    MODE and will only refer to those bits that are nonzero in MASK.
8036    If other bits are being computed or if masking operations are done
8037    that select a superset of the bits in MASK, they can sometimes be
8038    ignored.
8039
8040    Return a possibly simplified expression, but always convert X to
8041    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8042
8043    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8044    are all off in X.  This is used when X will be complemented, by either
8045    NOT, NEG, or XOR.  */
8046
8047 static rtx
8048 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8049                int just_select)
8050 {
8051   enum rtx_code code = GET_CODE (x);
8052   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8053   enum machine_mode op_mode;
8054   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8055   rtx op0, op1, temp;
8056
8057   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8058      code below will do the wrong thing since the mode of such an
8059      expression is VOIDmode.
8060
8061      Also do nothing if X is a CLOBBER; this can happen if X was
8062      the return value from a call to gen_lowpart.  */
8063   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8064     return x;
8065
8066   /* We want to perform the operation in its present mode unless we know
8067      that the operation is valid in MODE, in which case we do the operation
8068      in MODE.  */
8069   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8070               && have_insn_for (code, mode))
8071              ? mode : GET_MODE (x));
8072
8073   /* It is not valid to do a right-shift in a narrower mode
8074      than the one it came in with.  */
8075   if ((code == LSHIFTRT || code == ASHIFTRT)
8076       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8077     op_mode = GET_MODE (x);
8078
8079   /* Truncate MASK to fit OP_MODE.  */
8080   if (op_mode)
8081     mask &= GET_MODE_MASK (op_mode);
8082
8083   /* When we have an arithmetic operation, or a shift whose count we
8084      do not know, we need to assume that all bits up to the highest-order
8085      bit in MASK will be needed.  This is how we form such a mask.  */
8086   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8087     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8088   else
8089     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8090                    - 1);
8091
8092   /* Determine what bits of X are guaranteed to be (non)zero.  */
8093   nonzero = nonzero_bits (x, mode);
8094
8095   /* If none of the bits in X are needed, return a zero.  */
8096   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8097     x = const0_rtx;
8098
8099   /* If X is a CONST_INT, return a new one.  Do this here since the
8100      test below will fail.  */
8101   if (CONST_INT_P (x))
8102     {
8103       if (SCALAR_INT_MODE_P (mode))
8104         return gen_int_mode (INTVAL (x) & mask, mode);
8105       else
8106         {
8107           x = GEN_INT (INTVAL (x) & mask);
8108           return gen_lowpart_common (mode, x);
8109         }
8110     }
8111
8112   /* If X is narrower than MODE and we want all the bits in X's mode, just
8113      get X in the proper mode.  */
8114   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8115       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8116     return gen_lowpart (mode, x);
8117
8118   /* We can ignore the effect of a SUBREG if it narrows the mode or
8119      if the constant masks to zero all the bits the mode doesn't have.  */
8120   if (GET_CODE (x) == SUBREG
8121       && subreg_lowpart_p (x)
8122       && ((GET_MODE_SIZE (GET_MODE (x))
8123            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8124           || (0 == (mask
8125                     & GET_MODE_MASK (GET_MODE (x))
8126                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8127     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8128
8129   /* The arithmetic simplifications here only work for scalar integer modes.  */
8130   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8131     return gen_lowpart_or_truncate (mode, x);
8132
8133   switch (code)
8134     {
8135     case CLOBBER:
8136       /* If X is a (clobber (const_int)), return it since we know we are
8137          generating something that won't match.  */
8138       return x;
8139
8140     case SIGN_EXTEND:
8141     case ZERO_EXTEND:
8142     case ZERO_EXTRACT:
8143     case SIGN_EXTRACT:
8144       x = expand_compound_operation (x);
8145       if (GET_CODE (x) != code)
8146         return force_to_mode (x, mode, mask, next_select);
8147       break;
8148
8149     case TRUNCATE:
8150       /* Similarly for a truncate.  */
8151       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8152
8153     case AND:
8154       /* If this is an AND with a constant, convert it into an AND
8155          whose constant is the AND of that constant with MASK.  If it
8156          remains an AND of MASK, delete it since it is redundant.  */
8157
8158       if (CONST_INT_P (XEXP (x, 1)))
8159         {
8160           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8161                                       mask & INTVAL (XEXP (x, 1)));
8162
8163           /* If X is still an AND, see if it is an AND with a mask that
8164              is just some low-order bits.  If so, and it is MASK, we don't
8165              need it.  */
8166
8167           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8168               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8169                   == mask))
8170             x = XEXP (x, 0);
8171
8172           /* If it remains an AND, try making another AND with the bits
8173              in the mode mask that aren't in MASK turned on.  If the
8174              constant in the AND is wide enough, this might make a
8175              cheaper constant.  */
8176
8177           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8178               && GET_MODE_MASK (GET_MODE (x)) != mask
8179               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8180             {
8181               unsigned HOST_WIDE_INT cval
8182                 = UINTVAL (XEXP (x, 1))
8183                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8184               rtx y;
8185
8186               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8187                                        gen_int_mode (cval, GET_MODE (x)));
8188               if (set_src_cost (y, optimize_this_for_speed_p)
8189                   < set_src_cost (x, optimize_this_for_speed_p))
8190                 x = y;
8191             }
8192
8193           break;
8194         }
8195
8196       goto binop;
8197
8198     case PLUS:
8199       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8200          low-order bits (as in an alignment operation) and FOO is already
8201          aligned to that boundary, mask C1 to that boundary as well.
8202          This may eliminate that PLUS and, later, the AND.  */
8203
8204       {
8205         unsigned int width = GET_MODE_PRECISION (mode);
8206         unsigned HOST_WIDE_INT smask = mask;
8207
8208         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8209            number, sign extend it.  */
8210
8211         if (width < HOST_BITS_PER_WIDE_INT
8212             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8213           smask |= HOST_WIDE_INT_M1U << width;
8214
8215         if (CONST_INT_P (XEXP (x, 1))
8216             && exact_log2 (- smask) >= 0
8217             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8218             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8219           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8220                                                (INTVAL (XEXP (x, 1)) & smask)),
8221                                 mode, smask, next_select);
8222       }
8223
8224       /* ... fall through ...  */
8225
8226     case MULT:
8227       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8228          most significant bit in MASK since carries from those bits will
8229          affect the bits we are interested in.  */
8230       mask = fuller_mask;
8231       goto binop;
8232
8233     case MINUS:
8234       /* If X is (minus C Y) where C's least set bit is larger than any bit
8235          in the mask, then we may replace with (neg Y).  */
8236       if (CONST_INT_P (XEXP (x, 0))
8237           && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8238         {
8239           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8240                                   GET_MODE (x));
8241           return force_to_mode (x, mode, mask, next_select);
8242         }
8243
8244       /* Similarly, if C contains every bit in the fuller_mask, then we may
8245          replace with (not Y).  */
8246       if (CONST_INT_P (XEXP (x, 0))
8247           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8248         {
8249           x = simplify_gen_unary (NOT, GET_MODE (x),
8250                                   XEXP (x, 1), GET_MODE (x));
8251           return force_to_mode (x, mode, mask, next_select);
8252         }
8253
8254       mask = fuller_mask;
8255       goto binop;
8256
8257     case IOR:
8258     case XOR:
8259       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8260          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8261          operation which may be a bitfield extraction.  Ensure that the
8262          constant we form is not wider than the mode of X.  */
8263
8264       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8265           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8266           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8267           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8268           && CONST_INT_P (XEXP (x, 1))
8269           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8270                + floor_log2 (INTVAL (XEXP (x, 1))))
8271               < GET_MODE_PRECISION (GET_MODE (x)))
8272           && (UINTVAL (XEXP (x, 1))
8273               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8274         {
8275           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8276                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8277                                GET_MODE (x));
8278           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8279                                       XEXP (XEXP (x, 0), 0), temp);
8280           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8281                                    XEXP (XEXP (x, 0), 1));
8282           return force_to_mode (x, mode, mask, next_select);
8283         }
8284
8285     binop:
8286       /* For most binary operations, just propagate into the operation and
8287          change the mode if we have an operation of that mode.  */
8288
8289       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8290       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8291
8292       /* If we ended up truncating both operands, truncate the result of the
8293          operation instead.  */
8294       if (GET_CODE (op0) == TRUNCATE
8295           && GET_CODE (op1) == TRUNCATE)
8296         {
8297           op0 = XEXP (op0, 0);
8298           op1 = XEXP (op1, 0);
8299         }
8300
8301       op0 = gen_lowpart_or_truncate (op_mode, op0);
8302       op1 = gen_lowpart_or_truncate (op_mode, op1);
8303
8304       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8305         x = simplify_gen_binary (code, op_mode, op0, op1);
8306       break;
8307
8308     case ASHIFT:
8309       /* For left shifts, do the same, but just for the first operand.
8310          However, we cannot do anything with shifts where we cannot
8311          guarantee that the counts are smaller than the size of the mode
8312          because such a count will have a different meaning in a
8313          wider mode.  */
8314
8315       if (! (CONST_INT_P (XEXP (x, 1))
8316              && INTVAL (XEXP (x, 1)) >= 0
8317              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8318           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8319                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8320                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8321         break;
8322
8323       /* If the shift count is a constant and we can do arithmetic in
8324          the mode of the shift, refine which bits we need.  Otherwise, use the
8325          conservative form of the mask.  */
8326       if (CONST_INT_P (XEXP (x, 1))
8327           && INTVAL (XEXP (x, 1)) >= 0
8328           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8329           && HWI_COMPUTABLE_MODE_P (op_mode))
8330         mask >>= INTVAL (XEXP (x, 1));
8331       else
8332         mask = fuller_mask;
8333
8334       op0 = gen_lowpart_or_truncate (op_mode,
8335                                      force_to_mode (XEXP (x, 0), op_mode,
8336                                                     mask, next_select));
8337
8338       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8339         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8340       break;
8341
8342     case LSHIFTRT:
8343       /* Here we can only do something if the shift count is a constant,
8344          this shift constant is valid for the host, and we can do arithmetic
8345          in OP_MODE.  */
8346
8347       if (CONST_INT_P (XEXP (x, 1))
8348           && INTVAL (XEXP (x, 1)) >= 0
8349           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8350           && HWI_COMPUTABLE_MODE_P (op_mode))
8351         {
8352           rtx inner = XEXP (x, 0);
8353           unsigned HOST_WIDE_INT inner_mask;
8354
8355           /* Select the mask of the bits we need for the shift operand.  */
8356           inner_mask = mask << INTVAL (XEXP (x, 1));
8357
8358           /* We can only change the mode of the shift if we can do arithmetic
8359              in the mode of the shift and INNER_MASK is no wider than the
8360              width of X's mode.  */
8361           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8362             op_mode = GET_MODE (x);
8363
8364           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8365
8366           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8367             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8368         }
8369
8370       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8371          shift and AND produces only copies of the sign bit (C2 is one less
8372          than a power of two), we can do this with just a shift.  */
8373
8374       if (GET_CODE (x) == LSHIFTRT
8375           && CONST_INT_P (XEXP (x, 1))
8376           /* The shift puts one of the sign bit copies in the least significant
8377              bit.  */
8378           && ((INTVAL (XEXP (x, 1))
8379                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8380               >= GET_MODE_PRECISION (GET_MODE (x)))
8381           && exact_log2 (mask + 1) >= 0
8382           /* Number of bits left after the shift must be more than the mask
8383              needs.  */
8384           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8385               <= GET_MODE_PRECISION (GET_MODE (x)))
8386           /* Must be more sign bit copies than the mask needs.  */
8387           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8388               >= exact_log2 (mask + 1)))
8389         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8390                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8391                                           - exact_log2 (mask + 1)));
8392
8393       goto shiftrt;
8394
8395     case ASHIFTRT:
8396       /* If we are just looking for the sign bit, we don't need this shift at
8397          all, even if it has a variable count.  */
8398       if (val_signbit_p (GET_MODE (x), mask))
8399         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8400
8401       /* If this is a shift by a constant, get a mask that contains those bits
8402          that are not copies of the sign bit.  We then have two cases:  If
8403          MASK only includes those bits, this can be a logical shift, which may
8404          allow simplifications.  If MASK is a single-bit field not within
8405          those bits, we are requesting a copy of the sign bit and hence can
8406          shift the sign bit to the appropriate location.  */
8407
8408       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8409           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8410         {
8411           int i;
8412
8413           /* If the considered data is wider than HOST_WIDE_INT, we can't
8414              represent a mask for all its bits in a single scalar.
8415              But we only care about the lower bits, so calculate these.  */
8416
8417           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8418             {
8419               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8420
8421               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8422                  is the number of bits a full-width mask would have set.
8423                  We need only shift if these are fewer than nonzero can
8424                  hold.  If not, we must keep all bits set in nonzero.  */
8425
8426               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8427                   < HOST_BITS_PER_WIDE_INT)
8428                 nonzero >>= INTVAL (XEXP (x, 1))
8429                             + HOST_BITS_PER_WIDE_INT
8430                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8431             }
8432           else
8433             {
8434               nonzero = GET_MODE_MASK (GET_MODE (x));
8435               nonzero >>= INTVAL (XEXP (x, 1));
8436             }
8437
8438           if ((mask & ~nonzero) == 0)
8439             {
8440               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8441                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8442               if (GET_CODE (x) != ASHIFTRT)
8443                 return force_to_mode (x, mode, mask, next_select);
8444             }
8445
8446           else if ((i = exact_log2 (mask)) >= 0)
8447             {
8448               x = simplify_shift_const
8449                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8450                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8451
8452               if (GET_CODE (x) != ASHIFTRT)
8453                 return force_to_mode (x, mode, mask, next_select);
8454             }
8455         }
8456
8457       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8458          even if the shift count isn't a constant.  */
8459       if (mask == 1)
8460         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8461                                  XEXP (x, 0), XEXP (x, 1));
8462
8463     shiftrt:
8464
8465       /* If this is a zero- or sign-extension operation that just affects bits
8466          we don't care about, remove it.  Be sure the call above returned
8467          something that is still a shift.  */
8468
8469       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8470           && CONST_INT_P (XEXP (x, 1))
8471           && INTVAL (XEXP (x, 1)) >= 0
8472           && (INTVAL (XEXP (x, 1))
8473               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8474           && GET_CODE (XEXP (x, 0)) == ASHIFT
8475           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8476         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8477                               next_select);
8478
8479       break;
8480
8481     case ROTATE:
8482     case ROTATERT:
8483       /* If the shift count is constant and we can do computations
8484          in the mode of X, compute where the bits we care about are.
8485          Otherwise, we can't do anything.  Don't change the mode of
8486          the shift or propagate MODE into the shift, though.  */
8487       if (CONST_INT_P (XEXP (x, 1))
8488           && INTVAL (XEXP (x, 1)) >= 0)
8489         {
8490           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8491                                             GET_MODE (x),
8492                                             gen_int_mode (mask, GET_MODE (x)),
8493                                             XEXP (x, 1));
8494           if (temp && CONST_INT_P (temp))
8495             x = simplify_gen_binary (code, GET_MODE (x),
8496                                      force_to_mode (XEXP (x, 0), GET_MODE (x),
8497                                                     INTVAL (temp), next_select),
8498                                      XEXP (x, 1));
8499         }
8500       break;
8501
8502     case NEG:
8503       /* If we just want the low-order bit, the NEG isn't needed since it
8504          won't change the low-order bit.  */
8505       if (mask == 1)
8506         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8507
8508       /* We need any bits less significant than the most significant bit in
8509          MASK since carries from those bits will affect the bits we are
8510          interested in.  */
8511       mask = fuller_mask;
8512       goto unop;
8513
8514     case NOT:
8515       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8516          same as the XOR case above.  Ensure that the constant we form is not
8517          wider than the mode of X.  */
8518
8519       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8520           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8521           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8522           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8523               < GET_MODE_PRECISION (GET_MODE (x)))
8524           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8525         {
8526           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8527                                GET_MODE (x));
8528           temp = simplify_gen_binary (XOR, GET_MODE (x),
8529                                       XEXP (XEXP (x, 0), 0), temp);
8530           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8531                                    temp, XEXP (XEXP (x, 0), 1));
8532
8533           return force_to_mode (x, mode, mask, next_select);
8534         }
8535
8536       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8537          use the full mask inside the NOT.  */
8538       mask = fuller_mask;
8539
8540     unop:
8541       op0 = gen_lowpart_or_truncate (op_mode,
8542                                      force_to_mode (XEXP (x, 0), mode, mask,
8543                                                     next_select));
8544       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8545         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8546       break;
8547
8548     case NE:
8549       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8550          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8551          which is equal to STORE_FLAG_VALUE.  */
8552       if ((mask & ~STORE_FLAG_VALUE) == 0
8553           && XEXP (x, 1) == const0_rtx
8554           && GET_MODE (XEXP (x, 0)) == mode
8555           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8556           && (nonzero_bits (XEXP (x, 0), mode)
8557               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8558         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8559
8560       break;
8561
8562     case IF_THEN_ELSE:
8563       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8564          written in a narrower mode.  We play it safe and do not do so.  */
8565
8566       op0 = gen_lowpart_or_truncate (GET_MODE (x),
8567                                      force_to_mode (XEXP (x, 1), mode,
8568                                                     mask, next_select));
8569       op1 = gen_lowpart_or_truncate (GET_MODE (x),
8570                                      force_to_mode (XEXP (x, 2), mode,
8571                                                     mask, next_select));
8572       if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8573         x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8574                                   GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8575                                   op0, op1);
8576       break;
8577
8578     default:
8579       break;
8580     }
8581
8582   /* Ensure we return a value of the proper mode.  */
8583   return gen_lowpart_or_truncate (mode, x);
8584 }
8585 \f
8586 /* Return nonzero if X is an expression that has one of two values depending on
8587    whether some other value is zero or nonzero.  In that case, we return the
8588    value that is being tested, *PTRUE is set to the value if the rtx being
8589    returned has a nonzero value, and *PFALSE is set to the other alternative.
8590
8591    If we return zero, we set *PTRUE and *PFALSE to X.  */
8592
8593 static rtx
8594 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8595 {
8596   enum machine_mode mode = GET_MODE (x);
8597   enum rtx_code code = GET_CODE (x);
8598   rtx cond0, cond1, true0, true1, false0, false1;
8599   unsigned HOST_WIDE_INT nz;
8600
8601   /* If we are comparing a value against zero, we are done.  */
8602   if ((code == NE || code == EQ)
8603       && XEXP (x, 1) == const0_rtx)
8604     {
8605       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8606       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8607       return XEXP (x, 0);
8608     }
8609
8610   /* If this is a unary operation whose operand has one of two values, apply
8611      our opcode to compute those values.  */
8612   else if (UNARY_P (x)
8613            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8614     {
8615       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8616       *pfalse = simplify_gen_unary (code, mode, false0,
8617                                     GET_MODE (XEXP (x, 0)));
8618       return cond0;
8619     }
8620
8621   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8622      make can't possibly match and would suppress other optimizations.  */
8623   else if (code == COMPARE)
8624     ;
8625
8626   /* If this is a binary operation, see if either side has only one of two
8627      values.  If either one does or if both do and they are conditional on
8628      the same value, compute the new true and false values.  */
8629   else if (BINARY_P (x))
8630     {
8631       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8632       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8633
8634       if ((cond0 != 0 || cond1 != 0)
8635           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8636         {
8637           /* If if_then_else_cond returned zero, then true/false are the
8638              same rtl.  We must copy one of them to prevent invalid rtl
8639              sharing.  */
8640           if (cond0 == 0)
8641             true0 = copy_rtx (true0);
8642           else if (cond1 == 0)
8643             true1 = copy_rtx (true1);
8644
8645           if (COMPARISON_P (x))
8646             {
8647               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8648                                                 true0, true1);
8649               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8650                                                  false0, false1);
8651              }
8652           else
8653             {
8654               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8655               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8656             }
8657
8658           return cond0 ? cond0 : cond1;
8659         }
8660
8661       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8662          operands is zero when the other is nonzero, and vice-versa,
8663          and STORE_FLAG_VALUE is 1 or -1.  */
8664
8665       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8666           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8667               || code == UMAX)
8668           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8669         {
8670           rtx op0 = XEXP (XEXP (x, 0), 1);
8671           rtx op1 = XEXP (XEXP (x, 1), 1);
8672
8673           cond0 = XEXP (XEXP (x, 0), 0);
8674           cond1 = XEXP (XEXP (x, 1), 0);
8675
8676           if (COMPARISON_P (cond0)
8677               && COMPARISON_P (cond1)
8678               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8679                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8680                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8681                   || ((swap_condition (GET_CODE (cond0))
8682                        == reversed_comparison_code (cond1, NULL))
8683                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8684                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8685               && ! side_effects_p (x))
8686             {
8687               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8688               *pfalse = simplify_gen_binary (MULT, mode,
8689                                              (code == MINUS
8690                                               ? simplify_gen_unary (NEG, mode,
8691                                                                     op1, mode)
8692                                               : op1),
8693                                               const_true_rtx);
8694               return cond0;
8695             }
8696         }
8697
8698       /* Similarly for MULT, AND and UMIN, except that for these the result
8699          is always zero.  */
8700       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8701           && (code == MULT || code == AND || code == UMIN)
8702           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8703         {
8704           cond0 = XEXP (XEXP (x, 0), 0);
8705           cond1 = XEXP (XEXP (x, 1), 0);
8706
8707           if (COMPARISON_P (cond0)
8708               && COMPARISON_P (cond1)
8709               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8710                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8711                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8712                   || ((swap_condition (GET_CODE (cond0))
8713                        == reversed_comparison_code (cond1, NULL))
8714                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8715                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8716               && ! side_effects_p (x))
8717             {
8718               *ptrue = *pfalse = const0_rtx;
8719               return cond0;
8720             }
8721         }
8722     }
8723
8724   else if (code == IF_THEN_ELSE)
8725     {
8726       /* If we have IF_THEN_ELSE already, extract the condition and
8727          canonicalize it if it is NE or EQ.  */
8728       cond0 = XEXP (x, 0);
8729       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8730       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8731         return XEXP (cond0, 0);
8732       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8733         {
8734           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8735           return XEXP (cond0, 0);
8736         }
8737       else
8738         return cond0;
8739     }
8740
8741   /* If X is a SUBREG, we can narrow both the true and false values
8742      if the inner expression, if there is a condition.  */
8743   else if (code == SUBREG
8744            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8745                                                &true0, &false0)))
8746     {
8747       true0 = simplify_gen_subreg (mode, true0,
8748                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8749       false0 = simplify_gen_subreg (mode, false0,
8750                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8751       if (true0 && false0)
8752         {
8753           *ptrue = true0;
8754           *pfalse = false0;
8755           return cond0;
8756         }
8757     }
8758
8759   /* If X is a constant, this isn't special and will cause confusions
8760      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8761   else if (CONSTANT_P (x)
8762            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8763     ;
8764
8765   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8766      will be least confusing to the rest of the compiler.  */
8767   else if (mode == BImode)
8768     {
8769       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8770       return x;
8771     }
8772
8773   /* If X is known to be either 0 or -1, those are the true and
8774      false values when testing X.  */
8775   else if (x == constm1_rtx || x == const0_rtx
8776            || (mode != VOIDmode
8777                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8778     {
8779       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8780       return x;
8781     }
8782
8783   /* Likewise for 0 or a single bit.  */
8784   else if (HWI_COMPUTABLE_MODE_P (mode)
8785            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8786     {
8787       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8788       return x;
8789     }
8790
8791   /* Otherwise fail; show no condition with true and false values the same.  */
8792   *ptrue = *pfalse = x;
8793   return 0;
8794 }
8795 \f
8796 /* Return the value of expression X given the fact that condition COND
8797    is known to be true when applied to REG as its first operand and VAL
8798    as its second.  X is known to not be shared and so can be modified in
8799    place.
8800
8801    We only handle the simplest cases, and specifically those cases that
8802    arise with IF_THEN_ELSE expressions.  */
8803
8804 static rtx
8805 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8806 {
8807   enum rtx_code code = GET_CODE (x);
8808   rtx temp;
8809   const char *fmt;
8810   int i, j;
8811
8812   if (side_effects_p (x))
8813     return x;
8814
8815   /* If either operand of the condition is a floating point value,
8816      then we have to avoid collapsing an EQ comparison.  */
8817   if (cond == EQ
8818       && rtx_equal_p (x, reg)
8819       && ! FLOAT_MODE_P (GET_MODE (x))
8820       && ! FLOAT_MODE_P (GET_MODE (val)))
8821     return val;
8822
8823   if (cond == UNEQ && rtx_equal_p (x, reg))
8824     return val;
8825
8826   /* If X is (abs REG) and we know something about REG's relationship
8827      with zero, we may be able to simplify this.  */
8828
8829   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8830     switch (cond)
8831       {
8832       case GE:  case GT:  case EQ:
8833         return XEXP (x, 0);
8834       case LT:  case LE:
8835         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8836                                    XEXP (x, 0),
8837                                    GET_MODE (XEXP (x, 0)));
8838       default:
8839         break;
8840       }
8841
8842   /* The only other cases we handle are MIN, MAX, and comparisons if the
8843      operands are the same as REG and VAL.  */
8844
8845   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8846     {
8847       if (rtx_equal_p (XEXP (x, 0), val))
8848         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8849
8850       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8851         {
8852           if (COMPARISON_P (x))
8853             {
8854               if (comparison_dominates_p (cond, code))
8855                 return const_true_rtx;
8856
8857               code = reversed_comparison_code (x, NULL);
8858               if (code != UNKNOWN
8859                   && comparison_dominates_p (cond, code))
8860                 return const0_rtx;
8861               else
8862                 return x;
8863             }
8864           else if (code == SMAX || code == SMIN
8865                    || code == UMIN || code == UMAX)
8866             {
8867               int unsignedp = (code == UMIN || code == UMAX);
8868
8869               /* Do not reverse the condition when it is NE or EQ.
8870                  This is because we cannot conclude anything about
8871                  the value of 'SMAX (x, y)' when x is not equal to y,
8872                  but we can when x equals y.  */
8873               if ((code == SMAX || code == UMAX)
8874                   && ! (cond == EQ || cond == NE))
8875                 cond = reverse_condition (cond);
8876
8877               switch (cond)
8878                 {
8879                 case GE:   case GT:
8880                   return unsignedp ? x : XEXP (x, 1);
8881                 case LE:   case LT:
8882                   return unsignedp ? x : XEXP (x, 0);
8883                 case GEU:  case GTU:
8884                   return unsignedp ? XEXP (x, 1) : x;
8885                 case LEU:  case LTU:
8886                   return unsignedp ? XEXP (x, 0) : x;
8887                 default:
8888                   break;
8889                 }
8890             }
8891         }
8892     }
8893   else if (code == SUBREG)
8894     {
8895       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8896       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8897
8898       if (SUBREG_REG (x) != r)
8899         {
8900           /* We must simplify subreg here, before we lose track of the
8901              original inner_mode.  */
8902           new_rtx = simplify_subreg (GET_MODE (x), r,
8903                                  inner_mode, SUBREG_BYTE (x));
8904           if (new_rtx)
8905             return new_rtx;
8906           else
8907             SUBST (SUBREG_REG (x), r);
8908         }
8909
8910       return x;
8911     }
8912   /* We don't have to handle SIGN_EXTEND here, because even in the
8913      case of replacing something with a modeless CONST_INT, a
8914      CONST_INT is already (supposed to be) a valid sign extension for
8915      its narrower mode, which implies it's already properly
8916      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8917      story is different.  */
8918   else if (code == ZERO_EXTEND)
8919     {
8920       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8921       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8922
8923       if (XEXP (x, 0) != r)
8924         {
8925           /* We must simplify the zero_extend here, before we lose
8926              track of the original inner_mode.  */
8927           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8928                                           r, inner_mode);
8929           if (new_rtx)
8930             return new_rtx;
8931           else
8932             SUBST (XEXP (x, 0), r);
8933         }
8934
8935       return x;
8936     }
8937
8938   fmt = GET_RTX_FORMAT (code);
8939   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8940     {
8941       if (fmt[i] == 'e')
8942         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8943       else if (fmt[i] == 'E')
8944         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8945           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8946                                                 cond, reg, val));
8947     }
8948
8949   return x;
8950 }
8951 \f
8952 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8953    assignment as a field assignment.  */
8954
8955 static int
8956 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8957 {
8958   if (x == y || rtx_equal_p (x, y))
8959     return 1;
8960
8961   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8962     return 0;
8963
8964   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8965      Note that all SUBREGs of MEM are paradoxical; otherwise they
8966      would have been rewritten.  */
8967   if (MEM_P (x) && GET_CODE (y) == SUBREG
8968       && MEM_P (SUBREG_REG (y))
8969       && rtx_equal_p (SUBREG_REG (y),
8970                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8971     return 1;
8972
8973   if (MEM_P (y) && GET_CODE (x) == SUBREG
8974       && MEM_P (SUBREG_REG (x))
8975       && rtx_equal_p (SUBREG_REG (x),
8976                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8977     return 1;
8978
8979   /* We used to see if get_last_value of X and Y were the same but that's
8980      not correct.  In one direction, we'll cause the assignment to have
8981      the wrong destination and in the case, we'll import a register into this
8982      insn that might have already have been dead.   So fail if none of the
8983      above cases are true.  */
8984   return 0;
8985 }
8986 \f
8987 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8988    Return that assignment if so.
8989
8990    We only handle the most common cases.  */
8991
8992 static rtx
8993 make_field_assignment (rtx x)
8994 {
8995   rtx dest = SET_DEST (x);
8996   rtx src = SET_SRC (x);
8997   rtx assign;
8998   rtx rhs, lhs;
8999   HOST_WIDE_INT c1;
9000   HOST_WIDE_INT pos;
9001   unsigned HOST_WIDE_INT len;
9002   rtx other;
9003   enum machine_mode mode;
9004
9005   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9006      a clear of a one-bit field.  We will have changed it to
9007      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9008      for a SUBREG.  */
9009
9010   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9011       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9012       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9013       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9014     {
9015       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9016                                 1, 1, 1, 0);
9017       if (assign != 0)
9018         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9019       return x;
9020     }
9021
9022   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9023       && subreg_lowpart_p (XEXP (src, 0))
9024       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9025           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9026       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9027       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9028       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9029       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9030     {
9031       assign = make_extraction (VOIDmode, dest, 0,
9032                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9033                                 1, 1, 1, 0);
9034       if (assign != 0)
9035         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9036       return x;
9037     }
9038
9039   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9040      one-bit field.  */
9041   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9042       && XEXP (XEXP (src, 0), 0) == const1_rtx
9043       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9044     {
9045       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9046                                 1, 1, 1, 0);
9047       if (assign != 0)
9048         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9049       return x;
9050     }
9051
9052   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9053      SRC is an AND with all bits of that field set, then we can discard
9054      the AND.  */
9055   if (GET_CODE (dest) == ZERO_EXTRACT
9056       && CONST_INT_P (XEXP (dest, 1))
9057       && GET_CODE (src) == AND
9058       && CONST_INT_P (XEXP (src, 1)))
9059     {
9060       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9061       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9062       unsigned HOST_WIDE_INT ze_mask;
9063
9064       if (width >= HOST_BITS_PER_WIDE_INT)
9065         ze_mask = -1;
9066       else
9067         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9068
9069       /* Complete overlap.  We can remove the source AND.  */
9070       if ((and_mask & ze_mask) == ze_mask)
9071         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9072
9073       /* Partial overlap.  We can reduce the source AND.  */
9074       if ((and_mask & ze_mask) != and_mask)
9075         {
9076           mode = GET_MODE (src);
9077           src = gen_rtx_AND (mode, XEXP (src, 0),
9078                              gen_int_mode (and_mask & ze_mask, mode));
9079           return gen_rtx_SET (VOIDmode, dest, src);
9080         }
9081     }
9082
9083   /* The other case we handle is assignments into a constant-position
9084      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9085      a mask that has all one bits except for a group of zero bits and
9086      OTHER is known to have zeros where C1 has ones, this is such an
9087      assignment.  Compute the position and length from C1.  Shift OTHER
9088      to the appropriate position, force it to the required mode, and
9089      make the extraction.  Check for the AND in both operands.  */
9090
9091   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9092     return x;
9093
9094   rhs = expand_compound_operation (XEXP (src, 0));
9095   lhs = expand_compound_operation (XEXP (src, 1));
9096
9097   if (GET_CODE (rhs) == AND
9098       && CONST_INT_P (XEXP (rhs, 1))
9099       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9100     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9101   else if (GET_CODE (lhs) == AND
9102            && CONST_INT_P (XEXP (lhs, 1))
9103            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9104     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9105   else
9106     return x;
9107
9108   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9109   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9110       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9111       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9112     return x;
9113
9114   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9115   if (assign == 0)
9116     return x;
9117
9118   /* The mode to use for the source is the mode of the assignment, or of
9119      what is inside a possible STRICT_LOW_PART.  */
9120   mode = (GET_CODE (assign) == STRICT_LOW_PART
9121           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9122
9123   /* Shift OTHER right POS places and make it the source, restricting it
9124      to the proper length and mode.  */
9125
9126   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9127                                                      GET_MODE (src),
9128                                                      other, pos),
9129                                dest);
9130   src = force_to_mode (src, mode,
9131                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9132                        ? ~(unsigned HOST_WIDE_INT) 0
9133                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9134                        0);
9135
9136   /* If SRC is masked by an AND that does not make a difference in
9137      the value being stored, strip it.  */
9138   if (GET_CODE (assign) == ZERO_EXTRACT
9139       && CONST_INT_P (XEXP (assign, 1))
9140       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9141       && GET_CODE (src) == AND
9142       && CONST_INT_P (XEXP (src, 1))
9143       && UINTVAL (XEXP (src, 1))
9144          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9145     src = XEXP (src, 0);
9146
9147   return gen_rtx_SET (VOIDmode, assign, src);
9148 }
9149 \f
9150 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9151    if so.  */
9152
9153 static rtx
9154 apply_distributive_law (rtx x)
9155 {
9156   enum rtx_code code = GET_CODE (x);
9157   enum rtx_code inner_code;
9158   rtx lhs, rhs, other;
9159   rtx tem;
9160
9161   /* Distributivity is not true for floating point as it can change the
9162      value.  So we don't do it unless -funsafe-math-optimizations.  */
9163   if (FLOAT_MODE_P (GET_MODE (x))
9164       && ! flag_unsafe_math_optimizations)
9165     return x;
9166
9167   /* The outer operation can only be one of the following:  */
9168   if (code != IOR && code != AND && code != XOR
9169       && code != PLUS && code != MINUS)
9170     return x;
9171
9172   lhs = XEXP (x, 0);
9173   rhs = XEXP (x, 1);
9174
9175   /* If either operand is a primitive we can't do anything, so get out
9176      fast.  */
9177   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9178     return x;
9179
9180   lhs = expand_compound_operation (lhs);
9181   rhs = expand_compound_operation (rhs);
9182   inner_code = GET_CODE (lhs);
9183   if (inner_code != GET_CODE (rhs))
9184     return x;
9185
9186   /* See if the inner and outer operations distribute.  */
9187   switch (inner_code)
9188     {
9189     case LSHIFTRT:
9190     case ASHIFTRT:
9191     case AND:
9192     case IOR:
9193       /* These all distribute except over PLUS.  */
9194       if (code == PLUS || code == MINUS)
9195         return x;
9196       break;
9197
9198     case MULT:
9199       if (code != PLUS && code != MINUS)
9200         return x;
9201       break;
9202
9203     case ASHIFT:
9204       /* This is also a multiply, so it distributes over everything.  */
9205       break;
9206
9207     /* This used to handle SUBREG, but this turned out to be counter-
9208        productive, since (subreg (op ...)) usually is not handled by
9209        insn patterns, and this "optimization" therefore transformed
9210        recognizable patterns into unrecognizable ones.  Therefore the
9211        SUBREG case was removed from here.
9212
9213        It is possible that distributing SUBREG over arithmetic operations
9214        leads to an intermediate result than can then be optimized further,
9215        e.g. by moving the outer SUBREG to the other side of a SET as done
9216        in simplify_set.  This seems to have been the original intent of
9217        handling SUBREGs here.
9218
9219        However, with current GCC this does not appear to actually happen,
9220        at least on major platforms.  If some case is found where removing
9221        the SUBREG case here prevents follow-on optimizations, distributing
9222        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9223
9224     default:
9225       return x;
9226     }
9227
9228   /* Set LHS and RHS to the inner operands (A and B in the example
9229      above) and set OTHER to the common operand (C in the example).
9230      There is only one way to do this unless the inner operation is
9231      commutative.  */
9232   if (COMMUTATIVE_ARITH_P (lhs)
9233       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9234     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9235   else if (COMMUTATIVE_ARITH_P (lhs)
9236            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9237     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9238   else if (COMMUTATIVE_ARITH_P (lhs)
9239            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9240     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9241   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9242     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9243   else
9244     return x;
9245
9246   /* Form the new inner operation, seeing if it simplifies first.  */
9247   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9248
9249   /* There is one exception to the general way of distributing:
9250      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9251   if (code == XOR && inner_code == IOR)
9252     {
9253       inner_code = AND;
9254       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9255     }
9256
9257   /* We may be able to continuing distributing the result, so call
9258      ourselves recursively on the inner operation before forming the
9259      outer operation, which we return.  */
9260   return simplify_gen_binary (inner_code, GET_MODE (x),
9261                               apply_distributive_law (tem), other);
9262 }
9263
9264 /* See if X is of the form (* (+ A B) C), and if so convert to
9265    (+ (* A C) (* B C)) and try to simplify.
9266
9267    Most of the time, this results in no change.  However, if some of
9268    the operands are the same or inverses of each other, simplifications
9269    will result.
9270
9271    For example, (and (ior A B) (not B)) can occur as the result of
9272    expanding a bit field assignment.  When we apply the distributive
9273    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9274    which then simplifies to (and (A (not B))).
9275
9276    Note that no checks happen on the validity of applying the inverse
9277    distributive law.  This is pointless since we can do it in the
9278    few places where this routine is called.
9279
9280    N is the index of the term that is decomposed (the arithmetic operation,
9281    i.e. (+ A B) in the first example above).  !N is the index of the term that
9282    is distributed, i.e. of C in the first example above.  */
9283 static rtx
9284 distribute_and_simplify_rtx (rtx x, int n)
9285 {
9286   enum machine_mode mode;
9287   enum rtx_code outer_code, inner_code;
9288   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9289
9290   /* Distributivity is not true for floating point as it can change the
9291      value.  So we don't do it unless -funsafe-math-optimizations.  */
9292   if (FLOAT_MODE_P (GET_MODE (x))
9293       && ! flag_unsafe_math_optimizations)
9294     return NULL_RTX;
9295
9296   decomposed = XEXP (x, n);
9297   if (!ARITHMETIC_P (decomposed))
9298     return NULL_RTX;
9299
9300   mode = GET_MODE (x);
9301   outer_code = GET_CODE (x);
9302   distributed = XEXP (x, !n);
9303
9304   inner_code = GET_CODE (decomposed);
9305   inner_op0 = XEXP (decomposed, 0);
9306   inner_op1 = XEXP (decomposed, 1);
9307
9308   /* Special case (and (xor B C) (not A)), which is equivalent to
9309      (xor (ior A B) (ior A C))  */
9310   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9311     {
9312       distributed = XEXP (distributed, 0);
9313       outer_code = IOR;
9314     }
9315
9316   if (n == 0)
9317     {
9318       /* Distribute the second term.  */
9319       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9320       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9321     }
9322   else
9323     {
9324       /* Distribute the first term.  */
9325       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9326       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9327     }
9328
9329   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9330                                                      new_op0, new_op1));
9331   if (GET_CODE (tmp) != outer_code
9332       && (set_src_cost (tmp, optimize_this_for_speed_p)
9333           < set_src_cost (x, optimize_this_for_speed_p)))
9334     return tmp;
9335
9336   return NULL_RTX;
9337 }
9338 \f
9339 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9340    in MODE.  Return an equivalent form, if different from (and VAROP
9341    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9342
9343 static rtx
9344 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9345                           unsigned HOST_WIDE_INT constop)
9346 {
9347   unsigned HOST_WIDE_INT nonzero;
9348   unsigned HOST_WIDE_INT orig_constop;
9349   rtx orig_varop;
9350   int i;
9351
9352   orig_varop = varop;
9353   orig_constop = constop;
9354   if (GET_CODE (varop) == CLOBBER)
9355     return NULL_RTX;
9356
9357   /* Simplify VAROP knowing that we will be only looking at some of the
9358      bits in it.
9359
9360      Note by passing in CONSTOP, we guarantee that the bits not set in
9361      CONSTOP are not significant and will never be examined.  We must
9362      ensure that is the case by explicitly masking out those bits
9363      before returning.  */
9364   varop = force_to_mode (varop, mode, constop, 0);
9365
9366   /* If VAROP is a CLOBBER, we will fail so return it.  */
9367   if (GET_CODE (varop) == CLOBBER)
9368     return varop;
9369
9370   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9371      to VAROP and return the new constant.  */
9372   if (CONST_INT_P (varop))
9373     return gen_int_mode (INTVAL (varop) & constop, mode);
9374
9375   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9376      a call to nonzero_bits, here we don't care about bits outside
9377      MODE.  */
9378
9379   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9380
9381   /* Turn off all bits in the constant that are known to already be zero.
9382      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9383      which is tested below.  */
9384
9385   constop &= nonzero;
9386
9387   /* If we don't have any bits left, return zero.  */
9388   if (constop == 0)
9389     return const0_rtx;
9390
9391   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9392      a power of two, we can replace this with an ASHIFT.  */
9393   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9394       && (i = exact_log2 (constop)) >= 0)
9395     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9396
9397   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9398      or XOR, then try to apply the distributive law.  This may eliminate
9399      operations if either branch can be simplified because of the AND.
9400      It may also make some cases more complex, but those cases probably
9401      won't match a pattern either with or without this.  */
9402
9403   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9404     return
9405       gen_lowpart
9406         (mode,
9407          apply_distributive_law
9408          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9409                                simplify_and_const_int (NULL_RTX,
9410                                                        GET_MODE (varop),
9411                                                        XEXP (varop, 0),
9412                                                        constop),
9413                                simplify_and_const_int (NULL_RTX,
9414                                                        GET_MODE (varop),
9415                                                        XEXP (varop, 1),
9416                                                        constop))));
9417
9418   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9419      the AND and see if one of the operands simplifies to zero.  If so, we
9420      may eliminate it.  */
9421
9422   if (GET_CODE (varop) == PLUS
9423       && exact_log2 (constop + 1) >= 0)
9424     {
9425       rtx o0, o1;
9426
9427       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9428       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9429       if (o0 == const0_rtx)
9430         return o1;
9431       if (o1 == const0_rtx)
9432         return o0;
9433     }
9434
9435   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9436   varop = gen_lowpart (mode, varop);
9437   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9438     return NULL_RTX;
9439
9440   /* If we are only masking insignificant bits, return VAROP.  */
9441   if (constop == nonzero)
9442     return varop;
9443
9444   if (varop == orig_varop && constop == orig_constop)
9445     return NULL_RTX;
9446
9447   /* Otherwise, return an AND.  */
9448   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9449 }
9450
9451
9452 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9453    in MODE.
9454
9455    Return an equivalent form, if different from X.  Otherwise, return X.  If
9456    X is zero, we are to always construct the equivalent form.  */
9457
9458 static rtx
9459 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9460                         unsigned HOST_WIDE_INT constop)
9461 {
9462   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9463   if (tem)
9464     return tem;
9465
9466   if (!x)
9467     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9468                              gen_int_mode (constop, mode));
9469   if (GET_MODE (x) != mode)
9470     x = gen_lowpart (mode, x);
9471   return x;
9472 }
9473 \f
9474 /* Given a REG, X, compute which bits in X can be nonzero.
9475    We don't care about bits outside of those defined in MODE.
9476
9477    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9478    a shift, AND, or zero_extract, we can do better.  */
9479
9480 static rtx
9481 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9482                               const_rtx known_x ATTRIBUTE_UNUSED,
9483                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9484                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9485                               unsigned HOST_WIDE_INT *nonzero)
9486 {
9487   rtx tem;
9488   reg_stat_type *rsp;
9489
9490   /* If X is a register whose nonzero bits value is current, use it.
9491      Otherwise, if X is a register whose value we can find, use that
9492      value.  Otherwise, use the previously-computed global nonzero bits
9493      for this register.  */
9494
9495   rsp = &reg_stat[REGNO (x)];
9496   if (rsp->last_set_value != 0
9497       && (rsp->last_set_mode == mode
9498           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9499               && GET_MODE_CLASS (mode) == MODE_INT))
9500       && ((rsp->last_set_label >= label_tick_ebb_start
9501            && rsp->last_set_label < label_tick)
9502           || (rsp->last_set_label == label_tick
9503               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9504           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9505               && REG_N_SETS (REGNO (x)) == 1
9506               && !REGNO_REG_SET_P
9507                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9508                    REGNO (x)))))
9509     {
9510       unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9511
9512       if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9513         /* We don't know anything about the upper bits.  */
9514         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9515
9516       *nonzero &= mask;
9517       return NULL;
9518     }
9519
9520   tem = get_last_value (x);
9521
9522   if (tem)
9523     {
9524 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9525       /* If X is narrower than MODE and TEM is a non-negative
9526          constant that would appear negative in the mode of X,
9527          sign-extend it for use in reg_nonzero_bits because some
9528          machines (maybe most) will actually do the sign-extension
9529          and this is the conservative approach.
9530
9531          ??? For 2.5, try to tighten up the MD files in this regard
9532          instead of this kludge.  */
9533
9534       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9535           && CONST_INT_P (tem)
9536           && INTVAL (tem) > 0
9537           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9538         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9539 #endif
9540       return tem;
9541     }
9542   else if (nonzero_sign_valid && rsp->nonzero_bits)
9543     {
9544       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9545
9546       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9547         /* We don't know anything about the upper bits.  */
9548         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9549
9550       *nonzero &= mask;
9551     }
9552
9553   return NULL;
9554 }
9555
9556 /* Return the number of bits at the high-order end of X that are known to
9557    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9558    VOIDmode, X will be used in its own mode.  The returned value  will always
9559    be between 1 and the number of bits in MODE.  */
9560
9561 static rtx
9562 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9563                                      const_rtx known_x ATTRIBUTE_UNUSED,
9564                                      enum machine_mode known_mode
9565                                      ATTRIBUTE_UNUSED,
9566                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9567                                      unsigned int *result)
9568 {
9569   rtx tem;
9570   reg_stat_type *rsp;
9571
9572   rsp = &reg_stat[REGNO (x)];
9573   if (rsp->last_set_value != 0
9574       && rsp->last_set_mode == mode
9575       && ((rsp->last_set_label >= label_tick_ebb_start
9576            && rsp->last_set_label < label_tick)
9577           || (rsp->last_set_label == label_tick
9578               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9579           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9580               && REG_N_SETS (REGNO (x)) == 1
9581               && !REGNO_REG_SET_P
9582                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9583                    REGNO (x)))))
9584     {
9585       *result = rsp->last_set_sign_bit_copies;
9586       return NULL;
9587     }
9588
9589   tem = get_last_value (x);
9590   if (tem != 0)
9591     return tem;
9592
9593   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9594       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9595     *result = rsp->sign_bit_copies;
9596
9597   return NULL;
9598 }
9599 \f
9600 /* Return the number of "extended" bits there are in X, when interpreted
9601    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9602    unsigned quantities, this is the number of high-order zero bits.
9603    For signed quantities, this is the number of copies of the sign bit
9604    minus 1.  In both case, this function returns the number of "spare"
9605    bits.  For example, if two quantities for which this function returns
9606    at least 1 are added, the addition is known not to overflow.
9607
9608    This function will always return 0 unless called during combine, which
9609    implies that it must be called from a define_split.  */
9610
9611 unsigned int
9612 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9613 {
9614   if (nonzero_sign_valid == 0)
9615     return 0;
9616
9617   return (unsignedp
9618           ? (HWI_COMPUTABLE_MODE_P (mode)
9619              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9620                                - floor_log2 (nonzero_bits (x, mode)))
9621              : 0)
9622           : num_sign_bit_copies (x, mode) - 1);
9623 }
9624
9625 /* This function is called from `simplify_shift_const' to merge two
9626    outer operations.  Specifically, we have already found that we need
9627    to perform operation *POP0 with constant *PCONST0 at the outermost
9628    position.  We would now like to also perform OP1 with constant CONST1
9629    (with *POP0 being done last).
9630
9631    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9632    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9633    complement the innermost operand, otherwise it is unchanged.
9634
9635    MODE is the mode in which the operation will be done.  No bits outside
9636    the width of this mode matter.  It is assumed that the width of this mode
9637    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9638
9639    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9640    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9641    result is simply *PCONST0.
9642
9643    If the resulting operation cannot be expressed as one operation, we
9644    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9645
9646 static int
9647 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9648 {
9649   enum rtx_code op0 = *pop0;
9650   HOST_WIDE_INT const0 = *pconst0;
9651
9652   const0 &= GET_MODE_MASK (mode);
9653   const1 &= GET_MODE_MASK (mode);
9654
9655   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9656   if (op0 == AND)
9657     const1 &= const0;
9658
9659   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9660      if OP0 is SET.  */
9661
9662   if (op1 == UNKNOWN || op0 == SET)
9663     return 1;
9664
9665   else if (op0 == UNKNOWN)
9666     op0 = op1, const0 = const1;
9667
9668   else if (op0 == op1)
9669     {
9670       switch (op0)
9671         {
9672         case AND:
9673           const0 &= const1;
9674           break;
9675         case IOR:
9676           const0 |= const1;
9677           break;
9678         case XOR:
9679           const0 ^= const1;
9680           break;
9681         case PLUS:
9682           const0 += const1;
9683           break;
9684         case NEG:
9685           op0 = UNKNOWN;
9686           break;
9687         default:
9688           break;
9689         }
9690     }
9691
9692   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9693   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9694     return 0;
9695
9696   /* If the two constants aren't the same, we can't do anything.  The
9697      remaining six cases can all be done.  */
9698   else if (const0 != const1)
9699     return 0;
9700
9701   else
9702     switch (op0)
9703       {
9704       case IOR:
9705         if (op1 == AND)
9706           /* (a & b) | b == b */
9707           op0 = SET;
9708         else /* op1 == XOR */
9709           /* (a ^ b) | b == a | b */
9710           {;}
9711         break;
9712
9713       case XOR:
9714         if (op1 == AND)
9715           /* (a & b) ^ b == (~a) & b */
9716           op0 = AND, *pcomp_p = 1;
9717         else /* op1 == IOR */
9718           /* (a | b) ^ b == a & ~b */
9719           op0 = AND, const0 = ~const0;
9720         break;
9721
9722       case AND:
9723         if (op1 == IOR)
9724           /* (a | b) & b == b */
9725         op0 = SET;
9726         else /* op1 == XOR */
9727           /* (a ^ b) & b) == (~a) & b */
9728           *pcomp_p = 1;
9729         break;
9730       default:
9731         break;
9732       }
9733
9734   /* Check for NO-OP cases.  */
9735   const0 &= GET_MODE_MASK (mode);
9736   if (const0 == 0
9737       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9738     op0 = UNKNOWN;
9739   else if (const0 == 0 && op0 == AND)
9740     op0 = SET;
9741   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9742            && op0 == AND)
9743     op0 = UNKNOWN;
9744
9745   *pop0 = op0;
9746
9747   /* ??? Slightly redundant with the above mask, but not entirely.
9748      Moving this above means we'd have to sign-extend the mode mask
9749      for the final test.  */
9750   if (op0 != UNKNOWN && op0 != NEG)
9751     *pconst0 = trunc_int_for_mode (const0, mode);
9752
9753   return 1;
9754 }
9755 \f
9756 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9757    the shift in.  The original shift operation CODE is performed on OP in
9758    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9759    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9760    result of the shift is subject to operation OUTER_CODE with operand
9761    OUTER_CONST.  */
9762
9763 static enum machine_mode
9764 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9765                       enum machine_mode orig_mode, enum machine_mode mode,
9766                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9767 {
9768   if (orig_mode == mode)
9769     return mode;
9770   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9771
9772   /* In general we can't perform in wider mode for right shift and rotate.  */
9773   switch (code)
9774     {
9775     case ASHIFTRT:
9776       /* We can still widen if the bits brought in from the left are identical
9777          to the sign bit of ORIG_MODE.  */
9778       if (num_sign_bit_copies (op, mode)
9779           > (unsigned) (GET_MODE_PRECISION (mode)
9780                         - GET_MODE_PRECISION (orig_mode)))
9781         return mode;
9782       return orig_mode;
9783
9784     case LSHIFTRT:
9785       /* Similarly here but with zero bits.  */
9786       if (HWI_COMPUTABLE_MODE_P (mode)
9787           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9788         return mode;
9789
9790       /* We can also widen if the bits brought in will be masked off.  This
9791          operation is performed in ORIG_MODE.  */
9792       if (outer_code == AND)
9793         {
9794           int care_bits = low_bitmask_len (orig_mode, outer_const);
9795
9796           if (care_bits >= 0
9797               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9798             return mode;
9799         }
9800       /* fall through */
9801
9802     case ROTATE:
9803       return orig_mode;
9804
9805     case ROTATERT:
9806       gcc_unreachable ();
9807
9808     default:
9809       return mode;
9810     }
9811 }
9812
9813 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9814    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9815    if we cannot simplify it.  Otherwise, return a simplified value.
9816
9817    The shift is normally computed in the widest mode we find in VAROP, as
9818    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9819    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9820
9821 static rtx
9822 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9823                         rtx varop, int orig_count)
9824 {
9825   enum rtx_code orig_code = code;
9826   rtx orig_varop = varop;
9827   int count;
9828   enum machine_mode mode = result_mode;
9829   enum machine_mode shift_mode, tmode;
9830   unsigned int mode_words
9831     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9832   /* We form (outer_op (code varop count) (outer_const)).  */
9833   enum rtx_code outer_op = UNKNOWN;
9834   HOST_WIDE_INT outer_const = 0;
9835   int complement_p = 0;
9836   rtx new_rtx, x;
9837
9838   /* Make sure and truncate the "natural" shift on the way in.  We don't
9839      want to do this inside the loop as it makes it more difficult to
9840      combine shifts.  */
9841   if (SHIFT_COUNT_TRUNCATED)
9842     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9843
9844   /* If we were given an invalid count, don't do anything except exactly
9845      what was requested.  */
9846
9847   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9848     return NULL_RTX;
9849
9850   count = orig_count;
9851
9852   /* Unless one of the branches of the `if' in this loop does a `continue',
9853      we will `break' the loop after the `if'.  */
9854
9855   while (count != 0)
9856     {
9857       /* If we have an operand of (clobber (const_int 0)), fail.  */
9858       if (GET_CODE (varop) == CLOBBER)
9859         return NULL_RTX;
9860
9861       /* Convert ROTATERT to ROTATE.  */
9862       if (code == ROTATERT)
9863         {
9864           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9865           code = ROTATE;
9866           if (VECTOR_MODE_P (result_mode))
9867             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9868           else
9869             count = bitsize - count;
9870         }
9871
9872       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9873                                          mode, outer_op, outer_const);
9874
9875       /* Handle cases where the count is greater than the size of the mode
9876          minus 1.  For ASHIFT, use the size minus one as the count (this can
9877          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9878          take the count modulo the size.  For other shifts, the result is
9879          zero.
9880
9881          Since these shifts are being produced by the compiler by combining
9882          multiple operations, each of which are defined, we know what the
9883          result is supposed to be.  */
9884
9885       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9886         {
9887           if (code == ASHIFTRT)
9888             count = GET_MODE_PRECISION (shift_mode) - 1;
9889           else if (code == ROTATE || code == ROTATERT)
9890             count %= GET_MODE_PRECISION (shift_mode);
9891           else
9892             {
9893               /* We can't simply return zero because there may be an
9894                  outer op.  */
9895               varop = const0_rtx;
9896               count = 0;
9897               break;
9898             }
9899         }
9900
9901       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9902          here would cause an infinite loop.  */
9903       if (complement_p)
9904         break;
9905
9906       /* An arithmetic right shift of a quantity known to be -1 or 0
9907          is a no-op.  */
9908       if (code == ASHIFTRT
9909           && (num_sign_bit_copies (varop, shift_mode)
9910               == GET_MODE_PRECISION (shift_mode)))
9911         {
9912           count = 0;
9913           break;
9914         }
9915
9916       /* If we are doing an arithmetic right shift and discarding all but
9917          the sign bit copies, this is equivalent to doing a shift by the
9918          bitsize minus one.  Convert it into that shift because it will often
9919          allow other simplifications.  */
9920
9921       if (code == ASHIFTRT
9922           && (count + num_sign_bit_copies (varop, shift_mode)
9923               >= GET_MODE_PRECISION (shift_mode)))
9924         count = GET_MODE_PRECISION (shift_mode) - 1;
9925
9926       /* We simplify the tests below and elsewhere by converting
9927          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9928          `make_compound_operation' will convert it to an ASHIFTRT for
9929          those machines (such as VAX) that don't have an LSHIFTRT.  */
9930       if (code == ASHIFTRT
9931           && val_signbit_known_clear_p (shift_mode,
9932                                         nonzero_bits (varop, shift_mode)))
9933         code = LSHIFTRT;
9934
9935       if (((code == LSHIFTRT
9936             && HWI_COMPUTABLE_MODE_P (shift_mode)
9937             && !(nonzero_bits (varop, shift_mode) >> count))
9938            || (code == ASHIFT
9939                && HWI_COMPUTABLE_MODE_P (shift_mode)
9940                && !((nonzero_bits (varop, shift_mode) << count)
9941                     & GET_MODE_MASK (shift_mode))))
9942           && !side_effects_p (varop))
9943         varop = const0_rtx;
9944
9945       switch (GET_CODE (varop))
9946         {
9947         case SIGN_EXTEND:
9948         case ZERO_EXTEND:
9949         case SIGN_EXTRACT:
9950         case ZERO_EXTRACT:
9951           new_rtx = expand_compound_operation (varop);
9952           if (new_rtx != varop)
9953             {
9954               varop = new_rtx;
9955               continue;
9956             }
9957           break;
9958
9959         case MEM:
9960           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9961              minus the width of a smaller mode, we can do this with a
9962              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9963           if ((code == ASHIFTRT || code == LSHIFTRT)
9964               && ! mode_dependent_address_p (XEXP (varop, 0),
9965                                              MEM_ADDR_SPACE (varop))
9966               && ! MEM_VOLATILE_P (varop)
9967               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9968                                          MODE_INT, 1)) != BLKmode)
9969             {
9970               new_rtx = adjust_address_nv (varop, tmode,
9971                                        BYTES_BIG_ENDIAN ? 0
9972                                        : count / BITS_PER_UNIT);
9973
9974               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9975                                      : ZERO_EXTEND, mode, new_rtx);
9976               count = 0;
9977               continue;
9978             }
9979           break;
9980
9981         case SUBREG:
9982           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9983              the same number of words as what we've seen so far.  Then store
9984              the widest mode in MODE.  */
9985           if (subreg_lowpart_p (varop)
9986               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9987                   > GET_MODE_SIZE (GET_MODE (varop)))
9988               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9989                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9990                  == mode_words
9991               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9992               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9993             {
9994               varop = SUBREG_REG (varop);
9995               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9996                 mode = GET_MODE (varop);
9997               continue;
9998             }
9999           break;
10000
10001         case MULT:
10002           /* Some machines use MULT instead of ASHIFT because MULT
10003              is cheaper.  But it is still better on those machines to
10004              merge two shifts into one.  */
10005           if (CONST_INT_P (XEXP (varop, 1))
10006               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10007             {
10008               varop
10009                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10010                                        XEXP (varop, 0),
10011                                        GEN_INT (exact_log2 (
10012                                                 UINTVAL (XEXP (varop, 1)))));
10013               continue;
10014             }
10015           break;
10016
10017         case UDIV:
10018           /* Similar, for when divides are cheaper.  */
10019           if (CONST_INT_P (XEXP (varop, 1))
10020               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10021             {
10022               varop
10023                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10024                                        XEXP (varop, 0),
10025                                        GEN_INT (exact_log2 (
10026                                                 UINTVAL (XEXP (varop, 1)))));
10027               continue;
10028             }
10029           break;
10030
10031         case ASHIFTRT:
10032           /* If we are extracting just the sign bit of an arithmetic
10033              right shift, that shift is not needed.  However, the sign
10034              bit of a wider mode may be different from what would be
10035              interpreted as the sign bit in a narrower mode, so, if
10036              the result is narrower, don't discard the shift.  */
10037           if (code == LSHIFTRT
10038               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10039               && (GET_MODE_BITSIZE (result_mode)
10040                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10041             {
10042               varop = XEXP (varop, 0);
10043               continue;
10044             }
10045
10046           /* ... fall through ...  */
10047
10048         case LSHIFTRT:
10049         case ASHIFT:
10050         case ROTATE:
10051           /* Here we have two nested shifts.  The result is usually the
10052              AND of a new shift with a mask.  We compute the result below.  */
10053           if (CONST_INT_P (XEXP (varop, 1))
10054               && INTVAL (XEXP (varop, 1)) >= 0
10055               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10056               && HWI_COMPUTABLE_MODE_P (result_mode)
10057               && HWI_COMPUTABLE_MODE_P (mode)
10058               && !VECTOR_MODE_P (result_mode))
10059             {
10060               enum rtx_code first_code = GET_CODE (varop);
10061               unsigned int first_count = INTVAL (XEXP (varop, 1));
10062               unsigned HOST_WIDE_INT mask;
10063               rtx mask_rtx;
10064
10065               /* We have one common special case.  We can't do any merging if
10066                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10067                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10068                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10069                  we can convert it to
10070                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10071                  This simplifies certain SIGN_EXTEND operations.  */
10072               if (code == ASHIFT && first_code == ASHIFTRT
10073                   && count == (GET_MODE_PRECISION (result_mode)
10074                                - GET_MODE_PRECISION (GET_MODE (varop))))
10075                 {
10076                   /* C3 has the low-order C1 bits zero.  */
10077
10078                   mask = GET_MODE_MASK (mode)
10079                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10080
10081                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10082                                                   XEXP (varop, 0), mask);
10083                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10084                                                 varop, count);
10085                   count = first_count;
10086                   code = ASHIFTRT;
10087                   continue;
10088                 }
10089
10090               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10091                  than C1 high-order bits equal to the sign bit, we can convert
10092                  this to either an ASHIFT or an ASHIFTRT depending on the
10093                  two counts.
10094
10095                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10096
10097               if (code == ASHIFTRT && first_code == ASHIFT
10098                   && GET_MODE (varop) == shift_mode
10099                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10100                       > first_count))
10101                 {
10102                   varop = XEXP (varop, 0);
10103                   count -= first_count;
10104                   if (count < 0)
10105                     {
10106                       count = -count;
10107                       code = ASHIFT;
10108                     }
10109
10110                   continue;
10111                 }
10112
10113               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10114                  we can only do this if FIRST_CODE is also ASHIFTRT.
10115
10116                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10117                  ASHIFTRT.
10118
10119                  If the mode of this shift is not the mode of the outer shift,
10120                  we can't do this if either shift is a right shift or ROTATE.
10121
10122                  Finally, we can't do any of these if the mode is too wide
10123                  unless the codes are the same.
10124
10125                  Handle the case where the shift codes are the same
10126                  first.  */
10127
10128               if (code == first_code)
10129                 {
10130                   if (GET_MODE (varop) != result_mode
10131                       && (code == ASHIFTRT || code == LSHIFTRT
10132                           || code == ROTATE))
10133                     break;
10134
10135                   count += first_count;
10136                   varop = XEXP (varop, 0);
10137                   continue;
10138                 }
10139
10140               if (code == ASHIFTRT
10141                   || (code == ROTATE && first_code == ASHIFTRT)
10142                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10143                   || (GET_MODE (varop) != result_mode
10144                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10145                           || first_code == ROTATE
10146                           || code == ROTATE)))
10147                 break;
10148
10149               /* To compute the mask to apply after the shift, shift the
10150                  nonzero bits of the inner shift the same way the
10151                  outer shift will.  */
10152
10153               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10154                                        result_mode);
10155
10156               mask_rtx
10157                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10158                                                    GEN_INT (count));
10159
10160               /* Give up if we can't compute an outer operation to use.  */
10161               if (mask_rtx == 0
10162                   || !CONST_INT_P (mask_rtx)
10163                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10164                                         INTVAL (mask_rtx),
10165                                         result_mode, &complement_p))
10166                 break;
10167
10168               /* If the shifts are in the same direction, we add the
10169                  counts.  Otherwise, we subtract them.  */
10170               if ((code == ASHIFTRT || code == LSHIFTRT)
10171                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10172                 count += first_count;
10173               else
10174                 count -= first_count;
10175
10176               /* If COUNT is positive, the new shift is usually CODE,
10177                  except for the two exceptions below, in which case it is
10178                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10179                  always be used  */
10180               if (count > 0
10181                   && ((first_code == ROTATE && code == ASHIFT)
10182                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10183                 code = first_code;
10184               else if (count < 0)
10185                 code = first_code, count = -count;
10186
10187               varop = XEXP (varop, 0);
10188               continue;
10189             }
10190
10191           /* If we have (A << B << C) for any shift, we can convert this to
10192              (A << C << B).  This wins if A is a constant.  Only try this if
10193              B is not a constant.  */
10194
10195           else if (GET_CODE (varop) == code
10196                    && CONST_INT_P (XEXP (varop, 0))
10197                    && !CONST_INT_P (XEXP (varop, 1)))
10198             {
10199               rtx new_rtx = simplify_const_binary_operation (code, mode,
10200                                                          XEXP (varop, 0),
10201                                                          GEN_INT (count));
10202               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10203               count = 0;
10204               continue;
10205             }
10206           break;
10207
10208         case NOT:
10209           if (VECTOR_MODE_P (mode))
10210             break;
10211
10212           /* Make this fit the case below.  */
10213           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10214           continue;
10215
10216         case IOR:
10217         case AND:
10218         case XOR:
10219           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10220              with C the size of VAROP - 1 and the shift is logical if
10221              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10222              we have an (le X 0) operation.   If we have an arithmetic shift
10223              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10224              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10225
10226           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10227               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10228               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10229               && (code == LSHIFTRT || code == ASHIFTRT)
10230               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10231               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10232             {
10233               count = 0;
10234               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10235                                   const0_rtx);
10236
10237               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10238                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10239
10240               continue;
10241             }
10242
10243           /* If we have (shift (logical)), move the logical to the outside
10244              to allow it to possibly combine with another logical and the
10245              shift to combine with another shift.  This also canonicalizes to
10246              what a ZERO_EXTRACT looks like.  Also, some machines have
10247              (and (shift)) insns.  */
10248
10249           if (CONST_INT_P (XEXP (varop, 1))
10250               /* We can't do this if we have (ashiftrt (xor))  and the
10251                  constant has its sign bit set in shift_mode.  */
10252               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10253                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10254                                               shift_mode))
10255               && (new_rtx = simplify_const_binary_operation
10256                   (code, result_mode,
10257                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10258                    GEN_INT (count))) != 0
10259               && CONST_INT_P (new_rtx)
10260               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10261                                   INTVAL (new_rtx), result_mode, &complement_p))
10262             {
10263               varop = XEXP (varop, 0);
10264               continue;
10265             }
10266
10267           /* If we can't do that, try to simplify the shift in each arm of the
10268              logical expression, make a new logical expression, and apply
10269              the inverse distributive law.  This also can't be done
10270              for some (ashiftrt (xor)).  */
10271           if (CONST_INT_P (XEXP (varop, 1))
10272              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10273                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10274                                              shift_mode)))
10275             {
10276               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10277                                               XEXP (varop, 0), count);
10278               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10279                                               XEXP (varop, 1), count);
10280
10281               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10282                                            lhs, rhs);
10283               varop = apply_distributive_law (varop);
10284
10285               count = 0;
10286               continue;
10287             }
10288           break;
10289
10290         case EQ:
10291           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10292              says that the sign bit can be tested, FOO has mode MODE, C is
10293              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10294              that may be nonzero.  */
10295           if (code == LSHIFTRT
10296               && XEXP (varop, 1) == const0_rtx
10297               && GET_MODE (XEXP (varop, 0)) == result_mode
10298               && count == (GET_MODE_PRECISION (result_mode) - 1)
10299               && HWI_COMPUTABLE_MODE_P (result_mode)
10300               && STORE_FLAG_VALUE == -1
10301               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10302               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10303                                   &complement_p))
10304             {
10305               varop = XEXP (varop, 0);
10306               count = 0;
10307               continue;
10308             }
10309           break;
10310
10311         case NEG:
10312           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10313              than the number of bits in the mode is equivalent to A.  */
10314           if (code == LSHIFTRT
10315               && count == (GET_MODE_PRECISION (result_mode) - 1)
10316               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10317             {
10318               varop = XEXP (varop, 0);
10319               count = 0;
10320               continue;
10321             }
10322
10323           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10324              NEG outside to allow shifts to combine.  */
10325           if (code == ASHIFT
10326               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10327                                   &complement_p))
10328             {
10329               varop = XEXP (varop, 0);
10330               continue;
10331             }
10332           break;
10333
10334         case PLUS:
10335           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10336              is one less than the number of bits in the mode is
10337              equivalent to (xor A 1).  */
10338           if (code == LSHIFTRT
10339               && count == (GET_MODE_PRECISION (result_mode) - 1)
10340               && XEXP (varop, 1) == constm1_rtx
10341               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10342               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10343                                   &complement_p))
10344             {
10345               count = 0;
10346               varop = XEXP (varop, 0);
10347               continue;
10348             }
10349
10350           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10351              that might be nonzero in BAR are those being shifted out and those
10352              bits are known zero in FOO, we can replace the PLUS with FOO.
10353              Similarly in the other operand order.  This code occurs when
10354              we are computing the size of a variable-size array.  */
10355
10356           if ((code == ASHIFTRT || code == LSHIFTRT)
10357               && count < HOST_BITS_PER_WIDE_INT
10358               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10359               && (nonzero_bits (XEXP (varop, 1), result_mode)
10360                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10361             {
10362               varop = XEXP (varop, 0);
10363               continue;
10364             }
10365           else if ((code == ASHIFTRT || code == LSHIFTRT)
10366                    && count < HOST_BITS_PER_WIDE_INT
10367                    && HWI_COMPUTABLE_MODE_P (result_mode)
10368                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10369                             >> count)
10370                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10371                             & nonzero_bits (XEXP (varop, 1),
10372                                                  result_mode)))
10373             {
10374               varop = XEXP (varop, 1);
10375               continue;
10376             }
10377
10378           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10379           if (code == ASHIFT
10380               && CONST_INT_P (XEXP (varop, 1))
10381               && (new_rtx = simplify_const_binary_operation
10382                   (ASHIFT, result_mode,
10383                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10384                    GEN_INT (count))) != 0
10385               && CONST_INT_P (new_rtx)
10386               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10387                                   INTVAL (new_rtx), result_mode, &complement_p))
10388             {
10389               varop = XEXP (varop, 0);
10390               continue;
10391             }
10392
10393           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10394              signbit', and attempt to change the PLUS to an XOR and move it to
10395              the outer operation as is done above in the AND/IOR/XOR case
10396              leg for shift(logical). See details in logical handling above
10397              for reasoning in doing so.  */
10398           if (code == LSHIFTRT
10399               && CONST_INT_P (XEXP (varop, 1))
10400               && mode_signbit_p (result_mode, XEXP (varop, 1))
10401               && (new_rtx = simplify_const_binary_operation
10402                   (code, result_mode,
10403                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10404                    GEN_INT (count))) != 0
10405               && CONST_INT_P (new_rtx)
10406               && merge_outer_ops (&outer_op, &outer_const, XOR,
10407                                   INTVAL (new_rtx), result_mode, &complement_p))
10408             {
10409               varop = XEXP (varop, 0);
10410               continue;
10411             }
10412
10413           break;
10414
10415         case MINUS:
10416           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10417              with C the size of VAROP - 1 and the shift is logical if
10418              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10419              we have a (gt X 0) operation.  If the shift is arithmetic with
10420              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10421              we have a (neg (gt X 0)) operation.  */
10422
10423           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10424               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10425               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10426               && (code == LSHIFTRT || code == ASHIFTRT)
10427               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10428               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10429               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10430             {
10431               count = 0;
10432               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10433                                   const0_rtx);
10434
10435               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10436                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10437
10438               continue;
10439             }
10440           break;
10441
10442         case TRUNCATE:
10443           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10444              if the truncate does not affect the value.  */
10445           if (code == LSHIFTRT
10446               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10447               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10448               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10449                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10450                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10451             {
10452               rtx varop_inner = XEXP (varop, 0);
10453
10454               varop_inner
10455                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10456                                     XEXP (varop_inner, 0),
10457                                     GEN_INT
10458                                     (count + INTVAL (XEXP (varop_inner, 1))));
10459               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10460               count = 0;
10461               continue;
10462             }
10463           break;
10464
10465         default:
10466           break;
10467         }
10468
10469       break;
10470     }
10471
10472   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10473                                      outer_op, outer_const);
10474
10475   /* We have now finished analyzing the shift.  The result should be
10476      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10477      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10478      to the result of the shift.  OUTER_CONST is the relevant constant,
10479      but we must turn off all bits turned off in the shift.  */
10480
10481   if (outer_op == UNKNOWN
10482       && orig_code == code && orig_count == count
10483       && varop == orig_varop
10484       && shift_mode == GET_MODE (varop))
10485     return NULL_RTX;
10486
10487   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10488   varop = gen_lowpart (shift_mode, varop);
10489   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10490     return NULL_RTX;
10491
10492   /* If we have an outer operation and we just made a shift, it is
10493      possible that we could have simplified the shift were it not
10494      for the outer operation.  So try to do the simplification
10495      recursively.  */
10496
10497   if (outer_op != UNKNOWN)
10498     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10499   else
10500     x = NULL_RTX;
10501
10502   if (x == NULL_RTX)
10503     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10504
10505   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10506      turn off all the bits that the shift would have turned off.  */
10507   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10508     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10509                                 GET_MODE_MASK (result_mode) >> orig_count);
10510
10511   /* Do the remainder of the processing in RESULT_MODE.  */
10512   x = gen_lowpart_or_truncate (result_mode, x);
10513
10514   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10515      operation.  */
10516   if (complement_p)
10517     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10518
10519   if (outer_op != UNKNOWN)
10520     {
10521       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10522           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10523         outer_const = trunc_int_for_mode (outer_const, result_mode);
10524
10525       if (outer_op == AND)
10526         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10527       else if (outer_op == SET)
10528         {
10529           /* This means that we have determined that the result is
10530              equivalent to a constant.  This should be rare.  */
10531           if (!side_effects_p (x))
10532             x = GEN_INT (outer_const);
10533         }
10534       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10535         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10536       else
10537         x = simplify_gen_binary (outer_op, result_mode, x,
10538                                  GEN_INT (outer_const));
10539     }
10540
10541   return x;
10542 }
10543
10544 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10545    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10546    return X or, if it is NULL, synthesize the expression with
10547    simplify_gen_binary.  Otherwise, return a simplified value.
10548
10549    The shift is normally computed in the widest mode we find in VAROP, as
10550    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10551    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10552
10553 static rtx
10554 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10555                       rtx varop, int count)
10556 {
10557   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10558   if (tem)
10559     return tem;
10560
10561   if (!x)
10562     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10563   if (GET_MODE (x) != result_mode)
10564     x = gen_lowpart (result_mode, x);
10565   return x;
10566 }
10567
10568 \f
10569 /* Like recog, but we receive the address of a pointer to a new pattern.
10570    We try to match the rtx that the pointer points to.
10571    If that fails, we may try to modify or replace the pattern,
10572    storing the replacement into the same pointer object.
10573
10574    Modifications include deletion or addition of CLOBBERs.
10575
10576    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10577    the CLOBBERs are placed.
10578
10579    The value is the final insn code from the pattern ultimately matched,
10580    or -1.  */
10581
10582 static int
10583 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10584 {
10585   rtx pat = *pnewpat;
10586   rtx pat_without_clobbers;
10587   int insn_code_number;
10588   int num_clobbers_to_add = 0;
10589   int i;
10590   rtx notes = NULL_RTX;
10591   rtx old_notes, old_pat;
10592   int old_icode;
10593
10594   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10595      we use to indicate that something didn't match.  If we find such a
10596      thing, force rejection.  */
10597   if (GET_CODE (pat) == PARALLEL)
10598     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10599       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10600           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10601         return -1;
10602
10603   old_pat = PATTERN (insn);
10604   old_notes = REG_NOTES (insn);
10605   PATTERN (insn) = pat;
10606   REG_NOTES (insn) = NULL_RTX;
10607
10608   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10609   if (dump_file && (dump_flags & TDF_DETAILS))
10610     {
10611       if (insn_code_number < 0)
10612         fputs ("Failed to match this instruction:\n", dump_file);
10613       else
10614         fputs ("Successfully matched this instruction:\n", dump_file);
10615       print_rtl_single (dump_file, pat);
10616     }
10617
10618   /* If it isn't, there is the possibility that we previously had an insn
10619      that clobbered some register as a side effect, but the combined
10620      insn doesn't need to do that.  So try once more without the clobbers
10621      unless this represents an ASM insn.  */
10622
10623   if (insn_code_number < 0 && ! check_asm_operands (pat)
10624       && GET_CODE (pat) == PARALLEL)
10625     {
10626       int pos;
10627
10628       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10629         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10630           {
10631             if (i != pos)
10632               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10633             pos++;
10634           }
10635
10636       SUBST_INT (XVECLEN (pat, 0), pos);
10637
10638       if (pos == 1)
10639         pat = XVECEXP (pat, 0, 0);
10640
10641       PATTERN (insn) = pat;
10642       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10643       if (dump_file && (dump_flags & TDF_DETAILS))
10644         {
10645           if (insn_code_number < 0)
10646             fputs ("Failed to match this instruction:\n", dump_file);
10647           else
10648             fputs ("Successfully matched this instruction:\n", dump_file);
10649           print_rtl_single (dump_file, pat);
10650         }
10651     }
10652
10653   pat_without_clobbers = pat;
10654
10655   PATTERN (insn) = old_pat;
10656   REG_NOTES (insn) = old_notes;
10657
10658   /* Recognize all noop sets, these will be killed by followup pass.  */
10659   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10660     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10661
10662   /* If we had any clobbers to add, make a new pattern than contains
10663      them.  Then check to make sure that all of them are dead.  */
10664   if (num_clobbers_to_add)
10665     {
10666       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10667                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10668                                                   ? (XVECLEN (pat, 0)
10669                                                      + num_clobbers_to_add)
10670                                                   : num_clobbers_to_add + 1));
10671
10672       if (GET_CODE (pat) == PARALLEL)
10673         for (i = 0; i < XVECLEN (pat, 0); i++)
10674           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10675       else
10676         XVECEXP (newpat, 0, 0) = pat;
10677
10678       add_clobbers (newpat, insn_code_number);
10679
10680       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10681            i < XVECLEN (newpat, 0); i++)
10682         {
10683           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10684               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10685             return -1;
10686           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10687             {
10688               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10689               notes = alloc_reg_note (REG_UNUSED,
10690                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10691             }
10692         }
10693       pat = newpat;
10694     }
10695
10696   if (insn_code_number >= 0
10697       && insn_code_number != NOOP_MOVE_INSN_CODE)
10698     {
10699       old_pat = PATTERN (insn);
10700       old_notes = REG_NOTES (insn);
10701       old_icode = INSN_CODE (insn);
10702       PATTERN (insn) = pat;
10703       REG_NOTES (insn) = notes;
10704
10705       /* Allow targets to reject combined insn.  */
10706       if (!targetm.legitimate_combined_insn (insn))
10707         {
10708           if (dump_file && (dump_flags & TDF_DETAILS))
10709             fputs ("Instruction not appropriate for target.",
10710                    dump_file);
10711
10712           /* Callers expect recog_for_combine to strip
10713              clobbers from the pattern on failure.  */
10714           pat = pat_without_clobbers;
10715           notes = NULL_RTX;
10716
10717           insn_code_number = -1;
10718         }
10719
10720       PATTERN (insn) = old_pat;
10721       REG_NOTES (insn) = old_notes;
10722       INSN_CODE (insn) = old_icode;
10723     }
10724
10725   *pnewpat = pat;
10726   *pnotes = notes;
10727
10728   return insn_code_number;
10729 }
10730 \f
10731 /* Like gen_lowpart_general but for use by combine.  In combine it
10732    is not possible to create any new pseudoregs.  However, it is
10733    safe to create invalid memory addresses, because combine will
10734    try to recognize them and all they will do is make the combine
10735    attempt fail.
10736
10737    If for some reason this cannot do its job, an rtx
10738    (clobber (const_int 0)) is returned.
10739    An insn containing that will not be recognized.  */
10740
10741 static rtx
10742 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10743 {
10744   enum machine_mode imode = GET_MODE (x);
10745   unsigned int osize = GET_MODE_SIZE (omode);
10746   unsigned int isize = GET_MODE_SIZE (imode);
10747   rtx result;
10748
10749   if (omode == imode)
10750     return x;
10751
10752   /* We can only support MODE being wider than a word if X is a
10753      constant integer or has a mode the same size.  */
10754   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10755       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10756     goto fail;
10757
10758   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10759      won't know what to do.  So we will strip off the SUBREG here and
10760      process normally.  */
10761   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10762     {
10763       x = SUBREG_REG (x);
10764
10765       /* For use in case we fall down into the address adjustments
10766          further below, we need to adjust the known mode and size of
10767          x; imode and isize, since we just adjusted x.  */
10768       imode = GET_MODE (x);
10769
10770       if (imode == omode)
10771         return x;
10772
10773       isize = GET_MODE_SIZE (imode);
10774     }
10775
10776   result = gen_lowpart_common (omode, x);
10777
10778   if (result)
10779     return result;
10780
10781   if (MEM_P (x))
10782     {
10783       int offset = 0;
10784
10785       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10786          address.  */
10787       if (MEM_VOLATILE_P (x)
10788           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10789         goto fail;
10790
10791       /* If we want to refer to something bigger than the original memref,
10792          generate a paradoxical subreg instead.  That will force a reload
10793          of the original memref X.  */
10794       if (isize < osize)
10795         return gen_rtx_SUBREG (omode, x, 0);
10796
10797       if (WORDS_BIG_ENDIAN)
10798         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10799
10800       /* Adjust the address so that the address-after-the-data is
10801          unchanged.  */
10802       if (BYTES_BIG_ENDIAN)
10803         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10804
10805       return adjust_address_nv (x, omode, offset);
10806     }
10807
10808   /* If X is a comparison operator, rewrite it in a new mode.  This
10809      probably won't match, but may allow further simplifications.  */
10810   else if (COMPARISON_P (x))
10811     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10812
10813   /* If we couldn't simplify X any other way, just enclose it in a
10814      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10815      include an explicit SUBREG or we may simplify it further in combine.  */
10816   else
10817     {
10818       int offset = 0;
10819       rtx res;
10820
10821       offset = subreg_lowpart_offset (omode, imode);
10822       if (imode == VOIDmode)
10823         {
10824           imode = int_mode_for_mode (omode);
10825           x = gen_lowpart_common (imode, x);
10826           if (x == NULL)
10827             goto fail;
10828         }
10829       res = simplify_gen_subreg (omode, x, imode, offset);
10830       if (res)
10831         return res;
10832     }
10833
10834  fail:
10835   return gen_rtx_CLOBBER (omode, const0_rtx);
10836 }
10837 \f
10838 /* Try to simplify a comparison between OP0 and a constant OP1,
10839    where CODE is the comparison code that will be tested, into a
10840    (CODE OP0 const0_rtx) form.
10841
10842    The result is a possibly different comparison code to use.
10843    *POP1 may be updated.  */
10844
10845 static enum rtx_code
10846 simplify_compare_const (enum rtx_code code, enum machine_mode mode,
10847                         rtx op0, rtx *pop1)
10848 {
10849   unsigned int mode_width = GET_MODE_PRECISION (mode);
10850   HOST_WIDE_INT const_op = INTVAL (*pop1);
10851
10852   /* Get the constant we are comparing against and turn off all bits
10853      not on in our mode.  */
10854   if (mode != VOIDmode)
10855     const_op = trunc_int_for_mode (const_op, mode);
10856
10857   /* If we are comparing against a constant power of two and the value
10858      being compared can only have that single bit nonzero (e.g., it was
10859      `and'ed with that bit), we can replace this with a comparison
10860      with zero.  */
10861   if (const_op
10862       && (code == EQ || code == NE || code == GE || code == GEU
10863           || code == LT || code == LTU)
10864       && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10865       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10866       && (nonzero_bits (op0, mode)
10867           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10868     {
10869       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10870       const_op = 0;
10871     }
10872
10873   /* Similarly, if we are comparing a value known to be either -1 or
10874      0 with -1, change it to the opposite comparison against zero.  */
10875   if (const_op == -1
10876       && (code == EQ || code == NE || code == GT || code == LE
10877           || code == GEU || code == LTU)
10878       && num_sign_bit_copies (op0, mode) == mode_width)
10879     {
10880       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10881       const_op = 0;
10882     }
10883
10884   /* Do some canonicalizations based on the comparison code.  We prefer
10885      comparisons against zero and then prefer equality comparisons.
10886      If we can reduce the size of a constant, we will do that too.  */
10887   switch (code)
10888     {
10889     case LT:
10890       /* < C is equivalent to <= (C - 1) */
10891       if (const_op > 0)
10892         {
10893           const_op -= 1;
10894           code = LE;
10895           /* ... fall through to LE case below.  */
10896         }
10897       else
10898         break;
10899
10900     case LE:
10901       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10902       if (const_op < 0)
10903         {
10904           const_op += 1;
10905           code = LT;
10906         }
10907
10908       /* If we are doing a <= 0 comparison on a value known to have
10909          a zero sign bit, we can replace this with == 0.  */
10910       else if (const_op == 0
10911                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10912                && (nonzero_bits (op0, mode)
10913                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10914                == 0)
10915         code = EQ;
10916       break;
10917
10918     case GE:
10919       /* >= C is equivalent to > (C - 1).  */
10920       if (const_op > 0)
10921         {
10922           const_op -= 1;
10923           code = GT;
10924           /* ... fall through to GT below.  */
10925         }
10926       else
10927         break;
10928
10929     case GT:
10930       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10931       if (const_op < 0)
10932         {
10933           const_op += 1;
10934           code = GE;
10935         }
10936
10937       /* If we are doing a > 0 comparison on a value known to have
10938          a zero sign bit, we can replace this with != 0.  */
10939       else if (const_op == 0
10940                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10941                && (nonzero_bits (op0, mode)
10942                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10943                == 0)
10944         code = NE;
10945       break;
10946
10947     case LTU:
10948       /* < C is equivalent to <= (C - 1).  */
10949       if (const_op > 0)
10950         {
10951           const_op -= 1;
10952           code = LEU;
10953           /* ... fall through ...  */
10954         }
10955       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10956       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10957                && (unsigned HOST_WIDE_INT) const_op
10958                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10959         {
10960           const_op = 0;
10961           code = GE;
10962           break;
10963         }
10964       else
10965         break;
10966
10967     case LEU:
10968       /* unsigned <= 0 is equivalent to == 0 */
10969       if (const_op == 0)
10970         code = EQ;
10971       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10972       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10973                && (unsigned HOST_WIDE_INT) const_op
10974                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10975         {
10976           const_op = 0;
10977           code = GE;
10978         }
10979       break;
10980
10981     case GEU:
10982       /* >= C is equivalent to > (C - 1).  */
10983       if (const_op > 1)
10984         {
10985           const_op -= 1;
10986           code = GTU;
10987           /* ... fall through ...  */
10988         }
10989
10990       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10991       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10992                && (unsigned HOST_WIDE_INT) const_op
10993                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10994         {
10995           const_op = 0;
10996           code = LT;
10997           break;
10998         }
10999       else
11000         break;
11001
11002     case GTU:
11003       /* unsigned > 0 is equivalent to != 0 */
11004       if (const_op == 0)
11005         code = NE;
11006       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
11007       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11008                && (unsigned HOST_WIDE_INT) const_op
11009                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11010         {
11011           const_op = 0;
11012           code = LT;
11013         }
11014       break;
11015
11016     default:
11017       break;
11018     }
11019
11020   *pop1 = GEN_INT (const_op);
11021   return code;
11022 }
11023 \f
11024 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11025    comparison code that will be tested.
11026
11027    The result is a possibly different comparison code to use.  *POP0 and
11028    *POP1 may be updated.
11029
11030    It is possible that we might detect that a comparison is either always
11031    true or always false.  However, we do not perform general constant
11032    folding in combine, so this knowledge isn't useful.  Such tautologies
11033    should have been detected earlier.  Hence we ignore all such cases.  */
11034
11035 static enum rtx_code
11036 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11037 {
11038   rtx op0 = *pop0;
11039   rtx op1 = *pop1;
11040   rtx tem, tem1;
11041   int i;
11042   enum machine_mode mode, tmode;
11043
11044   /* Try a few ways of applying the same transformation to both operands.  */
11045   while (1)
11046     {
11047 #ifndef WORD_REGISTER_OPERATIONS
11048       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11049          so check specially.  */
11050       if (code != GTU && code != GEU && code != LTU && code != LEU
11051           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11052           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11053           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11054           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11055           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11056           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11057               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11058           && CONST_INT_P (XEXP (op0, 1))
11059           && XEXP (op0, 1) == XEXP (op1, 1)
11060           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11061           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11062           && (INTVAL (XEXP (op0, 1))
11063               == (GET_MODE_PRECISION (GET_MODE (op0))
11064                   - (GET_MODE_PRECISION
11065                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11066         {
11067           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11068           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11069         }
11070 #endif
11071
11072       /* If both operands are the same constant shift, see if we can ignore the
11073          shift.  We can if the shift is a rotate or if the bits shifted out of
11074          this shift are known to be zero for both inputs and if the type of
11075          comparison is compatible with the shift.  */
11076       if (GET_CODE (op0) == GET_CODE (op1)
11077           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11078           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11079               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11080                   && (code != GT && code != LT && code != GE && code != LE))
11081               || (GET_CODE (op0) == ASHIFTRT
11082                   && (code != GTU && code != LTU
11083                       && code != GEU && code != LEU)))
11084           && CONST_INT_P (XEXP (op0, 1))
11085           && INTVAL (XEXP (op0, 1)) >= 0
11086           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11087           && XEXP (op0, 1) == XEXP (op1, 1))
11088         {
11089           enum machine_mode mode = GET_MODE (op0);
11090           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11091           int shift_count = INTVAL (XEXP (op0, 1));
11092
11093           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11094             mask &= (mask >> shift_count) << shift_count;
11095           else if (GET_CODE (op0) == ASHIFT)
11096             mask = (mask & (mask << shift_count)) >> shift_count;
11097
11098           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11099               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11100             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11101           else
11102             break;
11103         }
11104
11105       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11106          SUBREGs are of the same mode, and, in both cases, the AND would
11107          be redundant if the comparison was done in the narrower mode,
11108          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11109          and the operand's possibly nonzero bits are 0xffffff01; in that case
11110          if we only care about QImode, we don't need the AND).  This case
11111          occurs if the output mode of an scc insn is not SImode and
11112          STORE_FLAG_VALUE == 1 (e.g., the 386).
11113
11114          Similarly, check for a case where the AND's are ZERO_EXTEND
11115          operations from some narrower mode even though a SUBREG is not
11116          present.  */
11117
11118       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11119                && CONST_INT_P (XEXP (op0, 1))
11120                && CONST_INT_P (XEXP (op1, 1)))
11121         {
11122           rtx inner_op0 = XEXP (op0, 0);
11123           rtx inner_op1 = XEXP (op1, 0);
11124           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11125           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11126           int changed = 0;
11127
11128           if (paradoxical_subreg_p (inner_op0)
11129               && GET_CODE (inner_op1) == SUBREG
11130               && (GET_MODE (SUBREG_REG (inner_op0))
11131                   == GET_MODE (SUBREG_REG (inner_op1)))
11132               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11133                   <= HOST_BITS_PER_WIDE_INT)
11134               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11135                                              GET_MODE (SUBREG_REG (inner_op0)))))
11136               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11137                                              GET_MODE (SUBREG_REG (inner_op1))))))
11138             {
11139               op0 = SUBREG_REG (inner_op0);
11140               op1 = SUBREG_REG (inner_op1);
11141
11142               /* The resulting comparison is always unsigned since we masked
11143                  off the original sign bit.  */
11144               code = unsigned_condition (code);
11145
11146               changed = 1;
11147             }
11148
11149           else if (c0 == c1)
11150             for (tmode = GET_CLASS_NARROWEST_MODE
11151                  (GET_MODE_CLASS (GET_MODE (op0)));
11152                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11153               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11154                 {
11155                   op0 = gen_lowpart (tmode, inner_op0);
11156                   op1 = gen_lowpart (tmode, inner_op1);
11157                   code = unsigned_condition (code);
11158                   changed = 1;
11159                   break;
11160                 }
11161
11162           if (! changed)
11163             break;
11164         }
11165
11166       /* If both operands are NOT, we can strip off the outer operation
11167          and adjust the comparison code for swapped operands; similarly for
11168          NEG, except that this must be an equality comparison.  */
11169       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11170                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11171                    && (code == EQ || code == NE)))
11172         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11173
11174       else
11175         break;
11176     }
11177
11178   /* If the first operand is a constant, swap the operands and adjust the
11179      comparison code appropriately, but don't do this if the second operand
11180      is already a constant integer.  */
11181   if (swap_commutative_operands_p (op0, op1))
11182     {
11183       tem = op0, op0 = op1, op1 = tem;
11184       code = swap_condition (code);
11185     }
11186
11187   /* We now enter a loop during which we will try to simplify the comparison.
11188      For the most part, we only are concerned with comparisons with zero,
11189      but some things may really be comparisons with zero but not start
11190      out looking that way.  */
11191
11192   while (CONST_INT_P (op1))
11193     {
11194       enum machine_mode mode = GET_MODE (op0);
11195       unsigned int mode_width = GET_MODE_PRECISION (mode);
11196       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11197       int equality_comparison_p;
11198       int sign_bit_comparison_p;
11199       int unsigned_comparison_p;
11200       HOST_WIDE_INT const_op;
11201
11202       /* We only want to handle integral modes.  This catches VOIDmode,
11203          CCmode, and the floating-point modes.  An exception is that we
11204          can handle VOIDmode if OP0 is a COMPARE or a comparison
11205          operation.  */
11206
11207       if (GET_MODE_CLASS (mode) != MODE_INT
11208           && ! (mode == VOIDmode
11209                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11210         break;
11211
11212       /* Try to simplify the compare to constant, possibly changing the
11213          comparison op, and/or changing op1 to zero.  */
11214       code = simplify_compare_const (code, mode, op0, &op1);
11215       const_op = INTVAL (op1);
11216
11217       /* Compute some predicates to simplify code below.  */
11218
11219       equality_comparison_p = (code == EQ || code == NE);
11220       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11221       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11222                                || code == GEU);
11223
11224       /* If this is a sign bit comparison and we can do arithmetic in
11225          MODE, say that we will only be needing the sign bit of OP0.  */
11226       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11227         op0 = force_to_mode (op0, mode,
11228                              (unsigned HOST_WIDE_INT) 1
11229                              << (GET_MODE_PRECISION (mode) - 1),
11230                              0);
11231
11232       /* Now try cases based on the opcode of OP0.  If none of the cases
11233          does a "continue", we exit this loop immediately after the
11234          switch.  */
11235
11236       switch (GET_CODE (op0))
11237         {
11238         case ZERO_EXTRACT:
11239           /* If we are extracting a single bit from a variable position in
11240              a constant that has only a single bit set and are comparing it
11241              with zero, we can convert this into an equality comparison
11242              between the position and the location of the single bit.  */
11243           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11244              have already reduced the shift count modulo the word size.  */
11245           if (!SHIFT_COUNT_TRUNCATED
11246               && CONST_INT_P (XEXP (op0, 0))
11247               && XEXP (op0, 1) == const1_rtx
11248               && equality_comparison_p && const_op == 0
11249               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11250             {
11251               if (BITS_BIG_ENDIAN)
11252                 i = BITS_PER_WORD - 1 - i;
11253
11254               op0 = XEXP (op0, 2);
11255               op1 = GEN_INT (i);
11256               const_op = i;
11257
11258               /* Result is nonzero iff shift count is equal to I.  */
11259               code = reverse_condition (code);
11260               continue;
11261             }
11262
11263           /* ... fall through ...  */
11264
11265         case SIGN_EXTRACT:
11266           tem = expand_compound_operation (op0);
11267           if (tem != op0)
11268             {
11269               op0 = tem;
11270               continue;
11271             }
11272           break;
11273
11274         case NOT:
11275           /* If testing for equality, we can take the NOT of the constant.  */
11276           if (equality_comparison_p
11277               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11278             {
11279               op0 = XEXP (op0, 0);
11280               op1 = tem;
11281               continue;
11282             }
11283
11284           /* If just looking at the sign bit, reverse the sense of the
11285              comparison.  */
11286           if (sign_bit_comparison_p)
11287             {
11288               op0 = XEXP (op0, 0);
11289               code = (code == GE ? LT : GE);
11290               continue;
11291             }
11292           break;
11293
11294         case NEG:
11295           /* If testing for equality, we can take the NEG of the constant.  */
11296           if (equality_comparison_p
11297               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11298             {
11299               op0 = XEXP (op0, 0);
11300               op1 = tem;
11301               continue;
11302             }
11303
11304           /* The remaining cases only apply to comparisons with zero.  */
11305           if (const_op != 0)
11306             break;
11307
11308           /* When X is ABS or is known positive,
11309              (neg X) is < 0 if and only if X != 0.  */
11310
11311           if (sign_bit_comparison_p
11312               && (GET_CODE (XEXP (op0, 0)) == ABS
11313                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11314                       && (nonzero_bits (XEXP (op0, 0), mode)
11315                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11316                          == 0)))
11317             {
11318               op0 = XEXP (op0, 0);
11319               code = (code == LT ? NE : EQ);
11320               continue;
11321             }
11322
11323           /* If we have NEG of something whose two high-order bits are the
11324              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11325           if (num_sign_bit_copies (op0, mode) >= 2)
11326             {
11327               op0 = XEXP (op0, 0);
11328               code = swap_condition (code);
11329               continue;
11330             }
11331           break;
11332
11333         case ROTATE:
11334           /* If we are testing equality and our count is a constant, we
11335              can perform the inverse operation on our RHS.  */
11336           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11337               && (tem = simplify_binary_operation (ROTATERT, mode,
11338                                                    op1, XEXP (op0, 1))) != 0)
11339             {
11340               op0 = XEXP (op0, 0);
11341               op1 = tem;
11342               continue;
11343             }
11344
11345           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11346              a particular bit.  Convert it to an AND of a constant of that
11347              bit.  This will be converted into a ZERO_EXTRACT.  */
11348           if (const_op == 0 && sign_bit_comparison_p
11349               && CONST_INT_P (XEXP (op0, 1))
11350               && mode_width <= HOST_BITS_PER_WIDE_INT)
11351             {
11352               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11353                                             ((unsigned HOST_WIDE_INT) 1
11354                                              << (mode_width - 1
11355                                                  - INTVAL (XEXP (op0, 1)))));
11356               code = (code == LT ? NE : EQ);
11357               continue;
11358             }
11359
11360           /* Fall through.  */
11361
11362         case ABS:
11363           /* ABS is ignorable inside an equality comparison with zero.  */
11364           if (const_op == 0 && equality_comparison_p)
11365             {
11366               op0 = XEXP (op0, 0);
11367               continue;
11368             }
11369           break;
11370
11371         case SIGN_EXTEND:
11372           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11373              (compare FOO CONST) if CONST fits in FOO's mode and we
11374              are either testing inequality or have an unsigned
11375              comparison with ZERO_EXTEND or a signed comparison with
11376              SIGN_EXTEND.  But don't do it if we don't have a compare
11377              insn of the given mode, since we'd have to revert it
11378              later on, and then we wouldn't know whether to sign- or
11379              zero-extend.  */
11380           mode = GET_MODE (XEXP (op0, 0));
11381           if (GET_MODE_CLASS (mode) == MODE_INT
11382               && ! unsigned_comparison_p
11383               && HWI_COMPUTABLE_MODE_P (mode)
11384               && trunc_int_for_mode (const_op, mode) == const_op
11385               && have_insn_for (COMPARE, mode))
11386             {
11387               op0 = XEXP (op0, 0);
11388               continue;
11389             }
11390           break;
11391
11392         case SUBREG:
11393           /* Check for the case where we are comparing A - C1 with C2, that is
11394
11395                (subreg:MODE (plus (A) (-C1))) op (C2)
11396
11397              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11398              comparison in the wider mode.  One of the following two conditions
11399              must be true in order for this to be valid:
11400
11401                1. The mode extension results in the same bit pattern being added
11402                   on both sides and the comparison is equality or unsigned.  As
11403                   C2 has been truncated to fit in MODE, the pattern can only be
11404                   all 0s or all 1s.
11405
11406                2. The mode extension results in the sign bit being copied on
11407                   each side.
11408
11409              The difficulty here is that we have predicates for A but not for
11410              (A - C1) so we need to check that C1 is within proper bounds so
11411              as to perturbate A as little as possible.  */
11412
11413           if (mode_width <= HOST_BITS_PER_WIDE_INT
11414               && subreg_lowpart_p (op0)
11415               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11416               && GET_CODE (SUBREG_REG (op0)) == PLUS
11417               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11418             {
11419               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11420               rtx a = XEXP (SUBREG_REG (op0), 0);
11421               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11422
11423               if ((c1 > 0
11424                    && (unsigned HOST_WIDE_INT) c1
11425                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11426                    && (equality_comparison_p || unsigned_comparison_p)
11427                    /* (A - C1) zero-extends if it is positive and sign-extends
11428                       if it is negative, C2 both zero- and sign-extends.  */
11429                    && ((0 == (nonzero_bits (a, inner_mode)
11430                               & ~GET_MODE_MASK (mode))
11431                         && const_op >= 0)
11432                        /* (A - C1) sign-extends if it is positive and 1-extends
11433                           if it is negative, C2 both sign- and 1-extends.  */
11434                        || (num_sign_bit_copies (a, inner_mode)
11435                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11436                                              - mode_width)
11437                            && const_op < 0)))
11438                   || ((unsigned HOST_WIDE_INT) c1
11439                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11440                       /* (A - C1) always sign-extends, like C2.  */
11441                       && num_sign_bit_copies (a, inner_mode)
11442                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11443                                            - (mode_width - 1))))
11444                 {
11445                   op0 = SUBREG_REG (op0);
11446                   continue;
11447                 }
11448             }
11449
11450           /* If the inner mode is narrower and we are extracting the low part,
11451              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11452           if (subreg_lowpart_p (op0)
11453               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11454             /* Fall through */ ;
11455           else
11456             break;
11457
11458           /* ... fall through ...  */
11459
11460         case ZERO_EXTEND:
11461           mode = GET_MODE (XEXP (op0, 0));
11462           if (GET_MODE_CLASS (mode) == MODE_INT
11463               && (unsigned_comparison_p || equality_comparison_p)
11464               && HWI_COMPUTABLE_MODE_P (mode)
11465               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11466               && const_op >= 0
11467               && have_insn_for (COMPARE, mode))
11468             {
11469               op0 = XEXP (op0, 0);
11470               continue;
11471             }
11472           break;
11473
11474         case PLUS:
11475           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11476              this for equality comparisons due to pathological cases involving
11477              overflows.  */
11478           if (equality_comparison_p
11479               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11480                                                         op1, XEXP (op0, 1))))
11481             {
11482               op0 = XEXP (op0, 0);
11483               op1 = tem;
11484               continue;
11485             }
11486
11487           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11488           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11489               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11490             {
11491               op0 = XEXP (XEXP (op0, 0), 0);
11492               code = (code == LT ? EQ : NE);
11493               continue;
11494             }
11495           break;
11496
11497         case MINUS:
11498           /* We used to optimize signed comparisons against zero, but that
11499              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11500              arrive here as equality comparisons, or (GEU, LTU) are
11501              optimized away.  No need to special-case them.  */
11502
11503           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11504              (eq B (minus A C)), whichever simplifies.  We can only do
11505              this for equality comparisons due to pathological cases involving
11506              overflows.  */
11507           if (equality_comparison_p
11508               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11509                                                         XEXP (op0, 1), op1)))
11510             {
11511               op0 = XEXP (op0, 0);
11512               op1 = tem;
11513               continue;
11514             }
11515
11516           if (equality_comparison_p
11517               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11518                                                         XEXP (op0, 0), op1)))
11519             {
11520               op0 = XEXP (op0, 1);
11521               op1 = tem;
11522               continue;
11523             }
11524
11525           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11526              of bits in X minus 1, is one iff X > 0.  */
11527           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11528               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11529               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11530               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11531             {
11532               op0 = XEXP (op0, 1);
11533               code = (code == GE ? LE : GT);
11534               continue;
11535             }
11536           break;
11537
11538         case XOR:
11539           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11540              if C is zero or B is a constant.  */
11541           if (equality_comparison_p
11542               && 0 != (tem = simplify_binary_operation (XOR, mode,
11543                                                         XEXP (op0, 1), op1)))
11544             {
11545               op0 = XEXP (op0, 0);
11546               op1 = tem;
11547               continue;
11548             }
11549           break;
11550
11551         case EQ:  case NE:
11552         case UNEQ:  case LTGT:
11553         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11554         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11555         case UNORDERED: case ORDERED:
11556           /* We can't do anything if OP0 is a condition code value, rather
11557              than an actual data value.  */
11558           if (const_op != 0
11559               || CC0_P (XEXP (op0, 0))
11560               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11561             break;
11562
11563           /* Get the two operands being compared.  */
11564           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11565             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11566           else
11567             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11568
11569           /* Check for the cases where we simply want the result of the
11570              earlier test or the opposite of that result.  */
11571           if (code == NE || code == EQ
11572               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11573                   && (code == LT || code == GE)))
11574             {
11575               enum rtx_code new_code;
11576               if (code == LT || code == NE)
11577                 new_code = GET_CODE (op0);
11578               else
11579                 new_code = reversed_comparison_code (op0, NULL);
11580
11581               if (new_code != UNKNOWN)
11582                 {
11583                   code = new_code;
11584                   op0 = tem;
11585                   op1 = tem1;
11586                   continue;
11587                 }
11588             }
11589           break;
11590
11591         case IOR:
11592           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11593              iff X <= 0.  */
11594           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11595               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11596               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11597             {
11598               op0 = XEXP (op0, 1);
11599               code = (code == GE ? GT : LE);
11600               continue;
11601             }
11602           break;
11603
11604         case AND:
11605           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11606              will be converted to a ZERO_EXTRACT later.  */
11607           if (const_op == 0 && equality_comparison_p
11608               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11609               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11610             {
11611               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11612                                       XEXP (XEXP (op0, 0), 1));
11613               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11614               continue;
11615             }
11616
11617           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11618              zero and X is a comparison and C1 and C2 describe only bits set
11619              in STORE_FLAG_VALUE, we can compare with X.  */
11620           if (const_op == 0 && equality_comparison_p
11621               && mode_width <= HOST_BITS_PER_WIDE_INT
11622               && CONST_INT_P (XEXP (op0, 1))
11623               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11624               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11625               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11626               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11627             {
11628               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11629                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11630               if ((~STORE_FLAG_VALUE & mask) == 0
11631                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11632                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11633                           && COMPARISON_P (tem))))
11634                 {
11635                   op0 = XEXP (XEXP (op0, 0), 0);
11636                   continue;
11637                 }
11638             }
11639
11640           /* If we are doing an equality comparison of an AND of a bit equal
11641              to the sign bit, replace this with a LT or GE comparison of
11642              the underlying value.  */
11643           if (equality_comparison_p
11644               && const_op == 0
11645               && CONST_INT_P (XEXP (op0, 1))
11646               && mode_width <= HOST_BITS_PER_WIDE_INT
11647               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11648                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11649             {
11650               op0 = XEXP (op0, 0);
11651               code = (code == EQ ? GE : LT);
11652               continue;
11653             }
11654
11655           /* If this AND operation is really a ZERO_EXTEND from a narrower
11656              mode, the constant fits within that mode, and this is either an
11657              equality or unsigned comparison, try to do this comparison in
11658              the narrower mode.
11659
11660              Note that in:
11661
11662              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11663              -> (ne:DI (reg:SI 4) (const_int 0))
11664
11665              unless TRULY_NOOP_TRUNCATION allows it or the register is
11666              known to hold a value of the required mode the
11667              transformation is invalid.  */
11668           if ((equality_comparison_p || unsigned_comparison_p)
11669               && CONST_INT_P (XEXP (op0, 1))
11670               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11671                                    & GET_MODE_MASK (mode))
11672                                   + 1)) >= 0
11673               && const_op >> i == 0
11674               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11675               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11676                   || (REG_P (XEXP (op0, 0))
11677                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11678             {
11679               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11680               continue;
11681             }
11682
11683           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11684              fits in both M1 and M2 and the SUBREG is either paradoxical
11685              or represents the low part, permute the SUBREG and the AND
11686              and try again.  */
11687           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11688             {
11689               unsigned HOST_WIDE_INT c1;
11690               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11691               /* Require an integral mode, to avoid creating something like
11692                  (AND:SF ...).  */
11693               if (SCALAR_INT_MODE_P (tmode)
11694                   /* It is unsafe to commute the AND into the SUBREG if the
11695                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11696                      not defined.  As originally written the upper bits
11697                      have a defined value due to the AND operation.
11698                      However, if we commute the AND inside the SUBREG then
11699                      they no longer have defined values and the meaning of
11700                      the code has been changed.  */
11701                   && (0
11702 #ifdef WORD_REGISTER_OPERATIONS
11703                       || (mode_width > GET_MODE_PRECISION (tmode)
11704                           && mode_width <= BITS_PER_WORD)
11705 #endif
11706                       || (mode_width <= GET_MODE_PRECISION (tmode)
11707                           && subreg_lowpart_p (XEXP (op0, 0))))
11708                   && CONST_INT_P (XEXP (op0, 1))
11709                   && mode_width <= HOST_BITS_PER_WIDE_INT
11710                   && HWI_COMPUTABLE_MODE_P (tmode)
11711                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11712                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11713                   && c1 != mask
11714                   && c1 != GET_MODE_MASK (tmode))
11715                 {
11716                   op0 = simplify_gen_binary (AND, tmode,
11717                                              SUBREG_REG (XEXP (op0, 0)),
11718                                              gen_int_mode (c1, tmode));
11719                   op0 = gen_lowpart (mode, op0);
11720                   continue;
11721                 }
11722             }
11723
11724           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11725           if (const_op == 0 && equality_comparison_p
11726               && XEXP (op0, 1) == const1_rtx
11727               && GET_CODE (XEXP (op0, 0)) == NOT)
11728             {
11729               op0 = simplify_and_const_int (NULL_RTX, mode,
11730                                             XEXP (XEXP (op0, 0), 0), 1);
11731               code = (code == NE ? EQ : NE);
11732               continue;
11733             }
11734
11735           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11736              (eq (and (lshiftrt X) 1) 0).
11737              Also handle the case where (not X) is expressed using xor.  */
11738           if (const_op == 0 && equality_comparison_p
11739               && XEXP (op0, 1) == const1_rtx
11740               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11741             {
11742               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11743               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11744
11745               if (GET_CODE (shift_op) == NOT
11746                   || (GET_CODE (shift_op) == XOR
11747                       && CONST_INT_P (XEXP (shift_op, 1))
11748                       && CONST_INT_P (shift_count)
11749                       && HWI_COMPUTABLE_MODE_P (mode)
11750                       && (UINTVAL (XEXP (shift_op, 1))
11751                           == (unsigned HOST_WIDE_INT) 1
11752                                << INTVAL (shift_count))))
11753                 {
11754                   op0
11755                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11756                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11757                   code = (code == NE ? EQ : NE);
11758                   continue;
11759                 }
11760             }
11761           break;
11762
11763         case ASHIFT:
11764           /* If we have (compare (ashift FOO N) (const_int C)) and
11765              the high order N bits of FOO (N+1 if an inequality comparison)
11766              are known to be zero, we can do this by comparing FOO with C
11767              shifted right N bits so long as the low-order N bits of C are
11768              zero.  */
11769           if (CONST_INT_P (XEXP (op0, 1))
11770               && INTVAL (XEXP (op0, 1)) >= 0
11771               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11772                   < HOST_BITS_PER_WIDE_INT)
11773               && (((unsigned HOST_WIDE_INT) const_op
11774                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11775                       - 1)) == 0)
11776               && mode_width <= HOST_BITS_PER_WIDE_INT
11777               && (nonzero_bits (XEXP (op0, 0), mode)
11778                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11779                                + ! equality_comparison_p))) == 0)
11780             {
11781               /* We must perform a logical shift, not an arithmetic one,
11782                  as we want the top N bits of C to be zero.  */
11783               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11784
11785               temp >>= INTVAL (XEXP (op0, 1));
11786               op1 = gen_int_mode (temp, mode);
11787               op0 = XEXP (op0, 0);
11788               continue;
11789             }
11790
11791           /* If we are doing a sign bit comparison, it means we are testing
11792              a particular bit.  Convert it to the appropriate AND.  */
11793           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11794               && mode_width <= HOST_BITS_PER_WIDE_INT)
11795             {
11796               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11797                                             ((unsigned HOST_WIDE_INT) 1
11798                                              << (mode_width - 1
11799                                                  - INTVAL (XEXP (op0, 1)))));
11800               code = (code == LT ? NE : EQ);
11801               continue;
11802             }
11803
11804           /* If this an equality comparison with zero and we are shifting
11805              the low bit to the sign bit, we can convert this to an AND of the
11806              low-order bit.  */
11807           if (const_op == 0 && equality_comparison_p
11808               && CONST_INT_P (XEXP (op0, 1))
11809               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11810             {
11811               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11812               continue;
11813             }
11814           break;
11815
11816         case ASHIFTRT:
11817           /* If this is an equality comparison with zero, we can do this
11818              as a logical shift, which might be much simpler.  */
11819           if (equality_comparison_p && const_op == 0
11820               && CONST_INT_P (XEXP (op0, 1)))
11821             {
11822               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11823                                           XEXP (op0, 0),
11824                                           INTVAL (XEXP (op0, 1)));
11825               continue;
11826             }
11827
11828           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11829              do the comparison in a narrower mode.  */
11830           if (! unsigned_comparison_p
11831               && CONST_INT_P (XEXP (op0, 1))
11832               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11833               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11834               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11835                                          MODE_INT, 1)) != BLKmode
11836               && (((unsigned HOST_WIDE_INT) const_op
11837                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11838                   <= GET_MODE_MASK (tmode)))
11839             {
11840               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11841               continue;
11842             }
11843
11844           /* Likewise if OP0 is a PLUS of a sign extension with a
11845              constant, which is usually represented with the PLUS
11846              between the shifts.  */
11847           if (! unsigned_comparison_p
11848               && CONST_INT_P (XEXP (op0, 1))
11849               && GET_CODE (XEXP (op0, 0)) == PLUS
11850               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11851               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11852               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11853               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11854                                          MODE_INT, 1)) != BLKmode
11855               && (((unsigned HOST_WIDE_INT) const_op
11856                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11857                   <= GET_MODE_MASK (tmode)))
11858             {
11859               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11860               rtx add_const = XEXP (XEXP (op0, 0), 1);
11861               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11862                                                    add_const, XEXP (op0, 1));
11863
11864               op0 = simplify_gen_binary (PLUS, tmode,
11865                                          gen_lowpart (tmode, inner),
11866                                          new_const);
11867               continue;
11868             }
11869
11870           /* ... fall through ...  */
11871         case LSHIFTRT:
11872           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11873              the low order N bits of FOO are known to be zero, we can do this
11874              by comparing FOO with C shifted left N bits so long as no
11875              overflow occurs.  Even if the low order N bits of FOO aren't known
11876              to be zero, if the comparison is >= or < we can use the same
11877              optimization and for > or <= by setting all the low
11878              order N bits in the comparison constant.  */
11879           if (CONST_INT_P (XEXP (op0, 1))
11880               && INTVAL (XEXP (op0, 1)) > 0
11881               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11882               && mode_width <= HOST_BITS_PER_WIDE_INT
11883               && (((unsigned HOST_WIDE_INT) const_op
11884                    + (GET_CODE (op0) != LSHIFTRT
11885                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11886                          + 1)
11887                       : 0))
11888                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11889             {
11890               unsigned HOST_WIDE_INT low_bits
11891                 = (nonzero_bits (XEXP (op0, 0), mode)
11892                    & (((unsigned HOST_WIDE_INT) 1
11893                        << INTVAL (XEXP (op0, 1))) - 1));
11894               if (low_bits == 0 || !equality_comparison_p)
11895                 {
11896                   /* If the shift was logical, then we must make the condition
11897                      unsigned.  */
11898                   if (GET_CODE (op0) == LSHIFTRT)
11899                     code = unsigned_condition (code);
11900
11901                   const_op <<= INTVAL (XEXP (op0, 1));
11902                   if (low_bits != 0
11903                       && (code == GT || code == GTU
11904                           || code == LE || code == LEU))
11905                     const_op
11906                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11907                   op1 = GEN_INT (const_op);
11908                   op0 = XEXP (op0, 0);
11909                   continue;
11910                 }
11911             }
11912
11913           /* If we are using this shift to extract just the sign bit, we
11914              can replace this with an LT or GE comparison.  */
11915           if (const_op == 0
11916               && (equality_comparison_p || sign_bit_comparison_p)
11917               && CONST_INT_P (XEXP (op0, 1))
11918               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11919             {
11920               op0 = XEXP (op0, 0);
11921               code = (code == NE || code == GT ? LT : GE);
11922               continue;
11923             }
11924           break;
11925
11926         default:
11927           break;
11928         }
11929
11930       break;
11931     }
11932
11933   /* Now make any compound operations involved in this comparison.  Then,
11934      check for an outmost SUBREG on OP0 that is not doing anything or is
11935      paradoxical.  The latter transformation must only be performed when
11936      it is known that the "extra" bits will be the same in op0 and op1 or
11937      that they don't matter.  There are three cases to consider:
11938
11939      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11940      care bits and we can assume they have any convenient value.  So
11941      making the transformation is safe.
11942
11943      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11944      In this case the upper bits of op0 are undefined.  We should not make
11945      the simplification in that case as we do not know the contents of
11946      those bits.
11947
11948      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11949      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11950      also be sure that they are the same as the upper bits of op1.
11951
11952      We can never remove a SUBREG for a non-equality comparison because
11953      the sign bit is in a different place in the underlying object.  */
11954
11955   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11956   op1 = make_compound_operation (op1, SET);
11957
11958   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11959       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11960       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11961       && (code == NE || code == EQ))
11962     {
11963       if (paradoxical_subreg_p (op0))
11964         {
11965           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11966              implemented.  */
11967           if (REG_P (SUBREG_REG (op0)))
11968             {
11969               op0 = SUBREG_REG (op0);
11970               op1 = gen_lowpart (GET_MODE (op0), op1);
11971             }
11972         }
11973       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11974                 <= HOST_BITS_PER_WIDE_INT)
11975                && (nonzero_bits (SUBREG_REG (op0),
11976                                  GET_MODE (SUBREG_REG (op0)))
11977                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11978         {
11979           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11980
11981           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11982                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11983             op0 = SUBREG_REG (op0), op1 = tem;
11984         }
11985     }
11986
11987   /* We now do the opposite procedure: Some machines don't have compare
11988      insns in all modes.  If OP0's mode is an integer mode smaller than a
11989      word and we can't do a compare in that mode, see if there is a larger
11990      mode for which we can do the compare.  There are a number of cases in
11991      which we can use the wider mode.  */
11992
11993   mode = GET_MODE (op0);
11994   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11995       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11996       && ! have_insn_for (COMPARE, mode))
11997     for (tmode = GET_MODE_WIDER_MODE (mode);
11998          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11999          tmode = GET_MODE_WIDER_MODE (tmode))
12000       if (have_insn_for (COMPARE, tmode))
12001         {
12002           int zero_extended;
12003
12004           /* If this is a test for negative, we can make an explicit
12005              test of the sign bit.  Test this first so we can use
12006              a paradoxical subreg to extend OP0.  */
12007
12008           if (op1 == const0_rtx && (code == LT || code == GE)
12009               && HWI_COMPUTABLE_MODE_P (mode))
12010             {
12011               unsigned HOST_WIDE_INT sign
12012                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
12013               op0 = simplify_gen_binary (AND, tmode,
12014                                          gen_lowpart (tmode, op0),
12015                                          gen_int_mode (sign, tmode));
12016               code = (code == LT) ? NE : EQ;
12017               break;
12018             }
12019
12020           /* If the only nonzero bits in OP0 and OP1 are those in the
12021              narrower mode and this is an equality or unsigned comparison,
12022              we can use the wider mode.  Similarly for sign-extended
12023              values, in which case it is true for all comparisons.  */
12024           zero_extended = ((code == EQ || code == NE
12025                             || code == GEU || code == GTU
12026                             || code == LEU || code == LTU)
12027                            && (nonzero_bits (op0, tmode)
12028                                & ~GET_MODE_MASK (mode)) == 0
12029                            && ((CONST_INT_P (op1)
12030                                 || (nonzero_bits (op1, tmode)
12031                                     & ~GET_MODE_MASK (mode)) == 0)));
12032
12033           if (zero_extended
12034               || ((num_sign_bit_copies (op0, tmode)
12035                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12036                                      - GET_MODE_PRECISION (mode)))
12037                   && (num_sign_bit_copies (op1, tmode)
12038                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12039                                         - GET_MODE_PRECISION (mode)))))
12040             {
12041               /* If OP0 is an AND and we don't have an AND in MODE either,
12042                  make a new AND in the proper mode.  */
12043               if (GET_CODE (op0) == AND
12044                   && !have_insn_for (AND, mode))
12045                 op0 = simplify_gen_binary (AND, tmode,
12046                                            gen_lowpart (tmode,
12047                                                         XEXP (op0, 0)),
12048                                            gen_lowpart (tmode,
12049                                                         XEXP (op0, 1)));
12050               else
12051                 {
12052                   if (zero_extended)
12053                     {
12054                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12055                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12056                     }
12057                   else
12058                     {
12059                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12060                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12061                     }
12062                   break;
12063                 }
12064             }
12065         }
12066
12067   /* We may have changed the comparison operands.  Re-canonicalize.  */
12068   if (swap_commutative_operands_p (op0, op1))
12069     {
12070       tem = op0, op0 = op1, op1 = tem;
12071       code = swap_condition (code);
12072     }
12073
12074   /* If this machine only supports a subset of valid comparisons, see if we
12075      can convert an unsupported one into a supported one.  */
12076   target_canonicalize_comparison (&code, &op0, &op1, 0);
12077
12078   *pop0 = op0;
12079   *pop1 = op1;
12080
12081   return code;
12082 }
12083 \f
12084 /* Utility function for record_value_for_reg.  Count number of
12085    rtxs in X.  */
12086 static int
12087 count_rtxs (rtx x)
12088 {
12089   enum rtx_code code = GET_CODE (x);
12090   const char *fmt;
12091   int i, j, ret = 1;
12092
12093   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12094       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12095     {
12096       rtx x0 = XEXP (x, 0);
12097       rtx x1 = XEXP (x, 1);
12098
12099       if (x0 == x1)
12100         return 1 + 2 * count_rtxs (x0);
12101
12102       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12103            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12104           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12105         return 2 + 2 * count_rtxs (x0)
12106                + count_rtxs (x == XEXP (x1, 0)
12107                              ? XEXP (x1, 1) : XEXP (x1, 0));
12108
12109       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12110            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12111           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12112         return 2 + 2 * count_rtxs (x1)
12113                + count_rtxs (x == XEXP (x0, 0)
12114                              ? XEXP (x0, 1) : XEXP (x0, 0));
12115     }
12116
12117   fmt = GET_RTX_FORMAT (code);
12118   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12119     if (fmt[i] == 'e')
12120       ret += count_rtxs (XEXP (x, i));
12121     else if (fmt[i] == 'E')
12122       for (j = 0; j < XVECLEN (x, i); j++)
12123         ret += count_rtxs (XVECEXP (x, i, j));
12124
12125   return ret;
12126 }
12127 \f
12128 /* Utility function for following routine.  Called when X is part of a value
12129    being stored into last_set_value.  Sets last_set_table_tick
12130    for each register mentioned.  Similar to mention_regs in cse.c  */
12131
12132 static void
12133 update_table_tick (rtx x)
12134 {
12135   enum rtx_code code = GET_CODE (x);
12136   const char *fmt = GET_RTX_FORMAT (code);
12137   int i, j;
12138
12139   if (code == REG)
12140     {
12141       unsigned int regno = REGNO (x);
12142       unsigned int endregno = END_REGNO (x);
12143       unsigned int r;
12144
12145       for (r = regno; r < endregno; r++)
12146         {
12147           reg_stat_type *rsp = &reg_stat[r];
12148           rsp->last_set_table_tick = label_tick;
12149         }
12150
12151       return;
12152     }
12153
12154   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12155     if (fmt[i] == 'e')
12156       {
12157         /* Check for identical subexpressions.  If x contains
12158            identical subexpression we only have to traverse one of
12159            them.  */
12160         if (i == 0 && ARITHMETIC_P (x))
12161           {
12162             /* Note that at this point x1 has already been
12163                processed.  */
12164             rtx x0 = XEXP (x, 0);
12165             rtx x1 = XEXP (x, 1);
12166
12167             /* If x0 and x1 are identical then there is no need to
12168                process x0.  */
12169             if (x0 == x1)
12170               break;
12171
12172             /* If x0 is identical to a subexpression of x1 then while
12173                processing x1, x0 has already been processed.  Thus we
12174                are done with x.  */
12175             if (ARITHMETIC_P (x1)
12176                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12177               break;
12178
12179             /* If x1 is identical to a subexpression of x0 then we
12180                still have to process the rest of x0.  */
12181             if (ARITHMETIC_P (x0)
12182                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12183               {
12184                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12185                 break;
12186               }
12187           }
12188
12189         update_table_tick (XEXP (x, i));
12190       }
12191     else if (fmt[i] == 'E')
12192       for (j = 0; j < XVECLEN (x, i); j++)
12193         update_table_tick (XVECEXP (x, i, j));
12194 }
12195
12196 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12197    are saying that the register is clobbered and we no longer know its
12198    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12199    only permitted with VALUE also zero and is used to invalidate the
12200    register.  */
12201
12202 static void
12203 record_value_for_reg (rtx reg, rtx insn, rtx value)
12204 {
12205   unsigned int regno = REGNO (reg);
12206   unsigned int endregno = END_REGNO (reg);
12207   unsigned int i;
12208   reg_stat_type *rsp;
12209
12210   /* If VALUE contains REG and we have a previous value for REG, substitute
12211      the previous value.  */
12212   if (value && insn && reg_overlap_mentioned_p (reg, value))
12213     {
12214       rtx tem;
12215
12216       /* Set things up so get_last_value is allowed to see anything set up to
12217          our insn.  */
12218       subst_low_luid = DF_INSN_LUID (insn);
12219       tem = get_last_value (reg);
12220
12221       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12222          it isn't going to be useful and will take a lot of time to process,
12223          so just use the CLOBBER.  */
12224
12225       if (tem)
12226         {
12227           if (ARITHMETIC_P (tem)
12228               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12229               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12230             tem = XEXP (tem, 0);
12231           else if (count_occurrences (value, reg, 1) >= 2)
12232             {
12233               /* If there are two or more occurrences of REG in VALUE,
12234                  prevent the value from growing too much.  */
12235               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12236                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12237             }
12238
12239           value = replace_rtx (copy_rtx (value), reg, tem);
12240         }
12241     }
12242
12243   /* For each register modified, show we don't know its value, that
12244      we don't know about its bitwise content, that its value has been
12245      updated, and that we don't know the location of the death of the
12246      register.  */
12247   for (i = regno; i < endregno; i++)
12248     {
12249       rsp = &reg_stat[i];
12250
12251       if (insn)
12252         rsp->last_set = insn;
12253
12254       rsp->last_set_value = 0;
12255       rsp->last_set_mode = VOIDmode;
12256       rsp->last_set_nonzero_bits = 0;
12257       rsp->last_set_sign_bit_copies = 0;
12258       rsp->last_death = 0;
12259       rsp->truncated_to_mode = VOIDmode;
12260     }
12261
12262   /* Mark registers that are being referenced in this value.  */
12263   if (value)
12264     update_table_tick (value);
12265
12266   /* Now update the status of each register being set.
12267      If someone is using this register in this block, set this register
12268      to invalid since we will get confused between the two lives in this
12269      basic block.  This makes using this register always invalid.  In cse, we
12270      scan the table to invalidate all entries using this register, but this
12271      is too much work for us.  */
12272
12273   for (i = regno; i < endregno; i++)
12274     {
12275       rsp = &reg_stat[i];
12276       rsp->last_set_label = label_tick;
12277       if (!insn
12278           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12279         rsp->last_set_invalid = 1;
12280       else
12281         rsp->last_set_invalid = 0;
12282     }
12283
12284   /* The value being assigned might refer to X (like in "x++;").  In that
12285      case, we must replace it with (clobber (const_int 0)) to prevent
12286      infinite loops.  */
12287   rsp = &reg_stat[regno];
12288   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12289     {
12290       value = copy_rtx (value);
12291       if (!get_last_value_validate (&value, insn, label_tick, 1))
12292         value = 0;
12293     }
12294
12295   /* For the main register being modified, update the value, the mode, the
12296      nonzero bits, and the number of sign bit copies.  */
12297
12298   rsp->last_set_value = value;
12299
12300   if (value)
12301     {
12302       enum machine_mode mode = GET_MODE (reg);
12303       subst_low_luid = DF_INSN_LUID (insn);
12304       rsp->last_set_mode = mode;
12305       if (GET_MODE_CLASS (mode) == MODE_INT
12306           && HWI_COMPUTABLE_MODE_P (mode))
12307         mode = nonzero_bits_mode;
12308       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12309       rsp->last_set_sign_bit_copies
12310         = num_sign_bit_copies (value, GET_MODE (reg));
12311     }
12312 }
12313
12314 /* Called via note_stores from record_dead_and_set_regs to handle one
12315    SET or CLOBBER in an insn.  DATA is the instruction in which the
12316    set is occurring.  */
12317
12318 static void
12319 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12320 {
12321   rtx record_dead_insn = (rtx) data;
12322
12323   if (GET_CODE (dest) == SUBREG)
12324     dest = SUBREG_REG (dest);
12325
12326   if (!record_dead_insn)
12327     {
12328       if (REG_P (dest))
12329         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12330       return;
12331     }
12332
12333   if (REG_P (dest))
12334     {
12335       /* If we are setting the whole register, we know its value.  Otherwise
12336          show that we don't know the value.  We can handle SUBREG in
12337          some cases.  */
12338       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12339         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12340       else if (GET_CODE (setter) == SET
12341                && GET_CODE (SET_DEST (setter)) == SUBREG
12342                && SUBREG_REG (SET_DEST (setter)) == dest
12343                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12344                && subreg_lowpart_p (SET_DEST (setter)))
12345         record_value_for_reg (dest, record_dead_insn,
12346                               gen_lowpart (GET_MODE (dest),
12347                                                        SET_SRC (setter)));
12348       else
12349         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12350     }
12351   else if (MEM_P (dest)
12352            /* Ignore pushes, they clobber nothing.  */
12353            && ! push_operand (dest, GET_MODE (dest)))
12354     mem_last_set = DF_INSN_LUID (record_dead_insn);
12355 }
12356
12357 /* Update the records of when each REG was most recently set or killed
12358    for the things done by INSN.  This is the last thing done in processing
12359    INSN in the combiner loop.
12360
12361    We update reg_stat[], in particular fields last_set, last_set_value,
12362    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12363    last_death, and also the similar information mem_last_set (which insn
12364    most recently modified memory) and last_call_luid (which insn was the
12365    most recent subroutine call).  */
12366
12367 static void
12368 record_dead_and_set_regs (rtx insn)
12369 {
12370   rtx link;
12371   unsigned int i;
12372
12373   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12374     {
12375       if (REG_NOTE_KIND (link) == REG_DEAD
12376           && REG_P (XEXP (link, 0)))
12377         {
12378           unsigned int regno = REGNO (XEXP (link, 0));
12379           unsigned int endregno = END_REGNO (XEXP (link, 0));
12380
12381           for (i = regno; i < endregno; i++)
12382             {
12383               reg_stat_type *rsp;
12384
12385               rsp = &reg_stat[i];
12386               rsp->last_death = insn;
12387             }
12388         }
12389       else if (REG_NOTE_KIND (link) == REG_INC)
12390         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12391     }
12392
12393   if (CALL_P (insn))
12394     {
12395       hard_reg_set_iterator hrsi;
12396       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12397         {
12398           reg_stat_type *rsp;
12399
12400           rsp = &reg_stat[i];
12401           rsp->last_set_invalid = 1;
12402           rsp->last_set = insn;
12403           rsp->last_set_value = 0;
12404           rsp->last_set_mode = VOIDmode;
12405           rsp->last_set_nonzero_bits = 0;
12406           rsp->last_set_sign_bit_copies = 0;
12407           rsp->last_death = 0;
12408           rsp->truncated_to_mode = VOIDmode;
12409         }
12410
12411       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12412
12413       /* We can't combine into a call pattern.  Remember, though, that
12414          the return value register is set at this LUID.  We could
12415          still replace a register with the return value from the
12416          wrong subroutine call!  */
12417       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12418     }
12419   else
12420     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12421 }
12422
12423 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12424    register present in the SUBREG, so for each such SUBREG go back and
12425    adjust nonzero and sign bit information of the registers that are
12426    known to have some zero/sign bits set.
12427
12428    This is needed because when combine blows the SUBREGs away, the
12429    information on zero/sign bits is lost and further combines can be
12430    missed because of that.  */
12431
12432 static void
12433 record_promoted_value (rtx insn, rtx subreg)
12434 {
12435   struct insn_link *links;
12436   rtx set;
12437   unsigned int regno = REGNO (SUBREG_REG (subreg));
12438   enum machine_mode mode = GET_MODE (subreg);
12439
12440   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12441     return;
12442
12443   for (links = LOG_LINKS (insn); links;)
12444     {
12445       reg_stat_type *rsp;
12446
12447       insn = links->insn;
12448       set = single_set (insn);
12449
12450       if (! set || !REG_P (SET_DEST (set))
12451           || REGNO (SET_DEST (set)) != regno
12452           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12453         {
12454           links = links->next;
12455           continue;
12456         }
12457
12458       rsp = &reg_stat[regno];
12459       if (rsp->last_set == insn)
12460         {
12461           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12462             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12463         }
12464
12465       if (REG_P (SET_SRC (set)))
12466         {
12467           regno = REGNO (SET_SRC (set));
12468           links = LOG_LINKS (insn);
12469         }
12470       else
12471         break;
12472     }
12473 }
12474
12475 /* Check if X, a register, is known to contain a value already
12476    truncated to MODE.  In this case we can use a subreg to refer to
12477    the truncated value even though in the generic case we would need
12478    an explicit truncation.  */
12479
12480 static bool
12481 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12482 {
12483   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12484   enum machine_mode truncated = rsp->truncated_to_mode;
12485
12486   if (truncated == 0
12487       || rsp->truncation_label < label_tick_ebb_start)
12488     return false;
12489   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12490     return true;
12491   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12492     return true;
12493   return false;
12494 }
12495
12496 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12497    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12498    might be able to turn a truncate into a subreg using this information.
12499    Return -1 if traversing *P is complete or 0 otherwise.  */
12500
12501 static int
12502 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12503 {
12504   rtx x = *p;
12505   enum machine_mode truncated_mode;
12506   reg_stat_type *rsp;
12507
12508   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12509     {
12510       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12511       truncated_mode = GET_MODE (x);
12512
12513       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12514         return -1;
12515
12516       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12517         return -1;
12518
12519       x = SUBREG_REG (x);
12520     }
12521   /* ??? For hard-regs we now record everything.  We might be able to
12522      optimize this using last_set_mode.  */
12523   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12524     truncated_mode = GET_MODE (x);
12525   else
12526     return 0;
12527
12528   rsp = &reg_stat[REGNO (x)];
12529   if (rsp->truncated_to_mode == 0
12530       || rsp->truncation_label < label_tick_ebb_start
12531       || (GET_MODE_SIZE (truncated_mode)
12532           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12533     {
12534       rsp->truncated_to_mode = truncated_mode;
12535       rsp->truncation_label = label_tick;
12536     }
12537
12538   return -1;
12539 }
12540
12541 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12542    the modes they are used in.  This can help truning TRUNCATEs into
12543    SUBREGs.  */
12544
12545 static void
12546 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12547 {
12548   for_each_rtx (x, record_truncated_value, NULL);
12549 }
12550
12551 /* Scan X for promoted SUBREGs.  For each one found,
12552    note what it implies to the registers used in it.  */
12553
12554 static void
12555 check_promoted_subreg (rtx insn, rtx x)
12556 {
12557   if (GET_CODE (x) == SUBREG
12558       && SUBREG_PROMOTED_VAR_P (x)
12559       && REG_P (SUBREG_REG (x)))
12560     record_promoted_value (insn, x);
12561   else
12562     {
12563       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12564       int i, j;
12565
12566       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12567         switch (format[i])
12568           {
12569           case 'e':
12570             check_promoted_subreg (insn, XEXP (x, i));
12571             break;
12572           case 'V':
12573           case 'E':
12574             if (XVEC (x, i) != 0)
12575               for (j = 0; j < XVECLEN (x, i); j++)
12576                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12577             break;
12578           }
12579     }
12580 }
12581 \f
12582 /* Verify that all the registers and memory references mentioned in *LOC are
12583    still valid.  *LOC was part of a value set in INSN when label_tick was
12584    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12585    the invalid references with (clobber (const_int 0)) and return 1.  This
12586    replacement is useful because we often can get useful information about
12587    the form of a value (e.g., if it was produced by a shift that always
12588    produces -1 or 0) even though we don't know exactly what registers it
12589    was produced from.  */
12590
12591 static int
12592 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12593 {
12594   rtx x = *loc;
12595   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12596   int len = GET_RTX_LENGTH (GET_CODE (x));
12597   int i, j;
12598
12599   if (REG_P (x))
12600     {
12601       unsigned int regno = REGNO (x);
12602       unsigned int endregno = END_REGNO (x);
12603       unsigned int j;
12604
12605       for (j = regno; j < endregno; j++)
12606         {
12607           reg_stat_type *rsp = &reg_stat[j];
12608           if (rsp->last_set_invalid
12609               /* If this is a pseudo-register that was only set once and not
12610                  live at the beginning of the function, it is always valid.  */
12611               || (! (regno >= FIRST_PSEUDO_REGISTER
12612                      && REG_N_SETS (regno) == 1
12613                      && (!REGNO_REG_SET_P
12614                          (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
12615                           regno)))
12616                   && rsp->last_set_label > tick))
12617           {
12618             if (replace)
12619               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12620             return replace;
12621           }
12622         }
12623
12624       return 1;
12625     }
12626   /* If this is a memory reference, make sure that there were no stores after
12627      it that might have clobbered the value.  We don't have alias info, so we
12628      assume any store invalidates it.  Moreover, we only have local UIDs, so
12629      we also assume that there were stores in the intervening basic blocks.  */
12630   else if (MEM_P (x) && !MEM_READONLY_P (x)
12631            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12632     {
12633       if (replace)
12634         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12635       return replace;
12636     }
12637
12638   for (i = 0; i < len; i++)
12639     {
12640       if (fmt[i] == 'e')
12641         {
12642           /* Check for identical subexpressions.  If x contains
12643              identical subexpression we only have to traverse one of
12644              them.  */
12645           if (i == 1 && ARITHMETIC_P (x))
12646             {
12647               /* Note that at this point x0 has already been checked
12648                  and found valid.  */
12649               rtx x0 = XEXP (x, 0);
12650               rtx x1 = XEXP (x, 1);
12651
12652               /* If x0 and x1 are identical then x is also valid.  */
12653               if (x0 == x1)
12654                 return 1;
12655
12656               /* If x1 is identical to a subexpression of x0 then
12657                  while checking x0, x1 has already been checked.  Thus
12658                  it is valid and so as x.  */
12659               if (ARITHMETIC_P (x0)
12660                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12661                 return 1;
12662
12663               /* If x0 is identical to a subexpression of x1 then x is
12664                  valid iff the rest of x1 is valid.  */
12665               if (ARITHMETIC_P (x1)
12666                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12667                 return
12668                   get_last_value_validate (&XEXP (x1,
12669                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12670                                            insn, tick, replace);
12671             }
12672
12673           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12674                                        replace) == 0)
12675             return 0;
12676         }
12677       else if (fmt[i] == 'E')
12678         for (j = 0; j < XVECLEN (x, i); j++)
12679           if (get_last_value_validate (&XVECEXP (x, i, j),
12680                                        insn, tick, replace) == 0)
12681             return 0;
12682     }
12683
12684   /* If we haven't found a reason for it to be invalid, it is valid.  */
12685   return 1;
12686 }
12687
12688 /* Get the last value assigned to X, if known.  Some registers
12689    in the value may be replaced with (clobber (const_int 0)) if their value
12690    is known longer known reliably.  */
12691
12692 static rtx
12693 get_last_value (const_rtx x)
12694 {
12695   unsigned int regno;
12696   rtx value;
12697   reg_stat_type *rsp;
12698
12699   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12700      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12701      we cannot predict what values the "extra" bits might have.  */
12702   if (GET_CODE (x) == SUBREG
12703       && subreg_lowpart_p (x)
12704       && !paradoxical_subreg_p (x)
12705       && (value = get_last_value (SUBREG_REG (x))) != 0)
12706     return gen_lowpart (GET_MODE (x), value);
12707
12708   if (!REG_P (x))
12709     return 0;
12710
12711   regno = REGNO (x);
12712   rsp = &reg_stat[regno];
12713   value = rsp->last_set_value;
12714
12715   /* If we don't have a value, or if it isn't for this basic block and
12716      it's either a hard register, set more than once, or it's a live
12717      at the beginning of the function, return 0.
12718
12719      Because if it's not live at the beginning of the function then the reg
12720      is always set before being used (is never used without being set).
12721      And, if it's set only once, and it's always set before use, then all
12722      uses must have the same last value, even if it's not from this basic
12723      block.  */
12724
12725   if (value == 0
12726       || (rsp->last_set_label < label_tick_ebb_start
12727           && (regno < FIRST_PSEUDO_REGISTER
12728               || REG_N_SETS (regno) != 1
12729               || REGNO_REG_SET_P
12730                  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
12731     return 0;
12732
12733   /* If the value was set in a later insn than the ones we are processing,
12734      we can't use it even if the register was only set once.  */
12735   if (rsp->last_set_label == label_tick
12736       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12737     return 0;
12738
12739   /* If the value has all its registers valid, return it.  */
12740   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12741     return value;
12742
12743   /* Otherwise, make a copy and replace any invalid register with
12744      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12745
12746   value = copy_rtx (value);
12747   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12748     return value;
12749
12750   return 0;
12751 }
12752 \f
12753 /* Return nonzero if expression X refers to a REG or to memory
12754    that is set in an instruction more recent than FROM_LUID.  */
12755
12756 static int
12757 use_crosses_set_p (const_rtx x, int from_luid)
12758 {
12759   const char *fmt;
12760   int i;
12761   enum rtx_code code = GET_CODE (x);
12762
12763   if (code == REG)
12764     {
12765       unsigned int regno = REGNO (x);
12766       unsigned endreg = END_REGNO (x);
12767
12768 #ifdef PUSH_ROUNDING
12769       /* Don't allow uses of the stack pointer to be moved,
12770          because we don't know whether the move crosses a push insn.  */
12771       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12772         return 1;
12773 #endif
12774       for (; regno < endreg; regno++)
12775         {
12776           reg_stat_type *rsp = &reg_stat[regno];
12777           if (rsp->last_set
12778               && rsp->last_set_label == label_tick
12779               && DF_INSN_LUID (rsp->last_set) > from_luid)
12780             return 1;
12781         }
12782       return 0;
12783     }
12784
12785   if (code == MEM && mem_last_set > from_luid)
12786     return 1;
12787
12788   fmt = GET_RTX_FORMAT (code);
12789
12790   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12791     {
12792       if (fmt[i] == 'E')
12793         {
12794           int j;
12795           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12796             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12797               return 1;
12798         }
12799       else if (fmt[i] == 'e'
12800                && use_crosses_set_p (XEXP (x, i), from_luid))
12801         return 1;
12802     }
12803   return 0;
12804 }
12805 \f
12806 /* Define three variables used for communication between the following
12807    routines.  */
12808
12809 static unsigned int reg_dead_regno, reg_dead_endregno;
12810 static int reg_dead_flag;
12811
12812 /* Function called via note_stores from reg_dead_at_p.
12813
12814    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12815    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12816
12817 static void
12818 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12819 {
12820   unsigned int regno, endregno;
12821
12822   if (!REG_P (dest))
12823     return;
12824
12825   regno = REGNO (dest);
12826   endregno = END_REGNO (dest);
12827   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12828     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12829 }
12830
12831 /* Return nonzero if REG is known to be dead at INSN.
12832
12833    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12834    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12835    live.  Otherwise, see if it is live or dead at the start of the basic
12836    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12837    must be assumed to be always live.  */
12838
12839 static int
12840 reg_dead_at_p (rtx reg, rtx insn)
12841 {
12842   basic_block block;
12843   unsigned int i;
12844
12845   /* Set variables for reg_dead_at_p_1.  */
12846   reg_dead_regno = REGNO (reg);
12847   reg_dead_endregno = END_REGNO (reg);
12848
12849   reg_dead_flag = 0;
12850
12851   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12852      we allow the machine description to decide whether use-and-clobber
12853      patterns are OK.  */
12854   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12855     {
12856       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12857         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12858           return 0;
12859     }
12860
12861   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12862      beginning of basic block.  */
12863   block = BLOCK_FOR_INSN (insn);
12864   for (;;)
12865     {
12866       if (INSN_P (insn))
12867         {
12868           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12869           if (reg_dead_flag)
12870             return reg_dead_flag == 1 ? 1 : 0;
12871
12872           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12873             return 1;
12874         }
12875
12876       if (insn == BB_HEAD (block))
12877         break;
12878
12879       insn = PREV_INSN (insn);
12880     }
12881
12882   /* Look at live-in sets for the basic block that we were in.  */
12883   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12884     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12885       return 0;
12886
12887   return 1;
12888 }
12889 \f
12890 /* Note hard registers in X that are used.  */
12891
12892 static void
12893 mark_used_regs_combine (rtx x)
12894 {
12895   RTX_CODE code = GET_CODE (x);
12896   unsigned int regno;
12897   int i;
12898
12899   switch (code)
12900     {
12901     case LABEL_REF:
12902     case SYMBOL_REF:
12903     case CONST:
12904     CASE_CONST_ANY:
12905     case PC:
12906     case ADDR_VEC:
12907     case ADDR_DIFF_VEC:
12908     case ASM_INPUT:
12909 #ifdef HAVE_cc0
12910     /* CC0 must die in the insn after it is set, so we don't need to take
12911        special note of it here.  */
12912     case CC0:
12913 #endif
12914       return;
12915
12916     case CLOBBER:
12917       /* If we are clobbering a MEM, mark any hard registers inside the
12918          address as used.  */
12919       if (MEM_P (XEXP (x, 0)))
12920         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12921       return;
12922
12923     case REG:
12924       regno = REGNO (x);
12925       /* A hard reg in a wide mode may really be multiple registers.
12926          If so, mark all of them just like the first.  */
12927       if (regno < FIRST_PSEUDO_REGISTER)
12928         {
12929           /* None of this applies to the stack, frame or arg pointers.  */
12930           if (regno == STACK_POINTER_REGNUM
12931 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12932               || regno == HARD_FRAME_POINTER_REGNUM
12933 #endif
12934 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12935               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12936 #endif
12937               || regno == FRAME_POINTER_REGNUM)
12938             return;
12939
12940           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12941         }
12942       return;
12943
12944     case SET:
12945       {
12946         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12947            the address.  */
12948         rtx testreg = SET_DEST (x);
12949
12950         while (GET_CODE (testreg) == SUBREG
12951                || GET_CODE (testreg) == ZERO_EXTRACT
12952                || GET_CODE (testreg) == STRICT_LOW_PART)
12953           testreg = XEXP (testreg, 0);
12954
12955         if (MEM_P (testreg))
12956           mark_used_regs_combine (XEXP (testreg, 0));
12957
12958         mark_used_regs_combine (SET_SRC (x));
12959       }
12960       return;
12961
12962     default:
12963       break;
12964     }
12965
12966   /* Recursively scan the operands of this expression.  */
12967
12968   {
12969     const char *fmt = GET_RTX_FORMAT (code);
12970
12971     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12972       {
12973         if (fmt[i] == 'e')
12974           mark_used_regs_combine (XEXP (x, i));
12975         else if (fmt[i] == 'E')
12976           {
12977             int j;
12978
12979             for (j = 0; j < XVECLEN (x, i); j++)
12980               mark_used_regs_combine (XVECEXP (x, i, j));
12981           }
12982       }
12983   }
12984 }
12985 \f
12986 /* Remove register number REGNO from the dead registers list of INSN.
12987
12988    Return the note used to record the death, if there was one.  */
12989
12990 rtx
12991 remove_death (unsigned int regno, rtx insn)
12992 {
12993   rtx note = find_regno_note (insn, REG_DEAD, regno);
12994
12995   if (note)
12996     remove_note (insn, note);
12997
12998   return note;
12999 }
13000
13001 /* For each register (hardware or pseudo) used within expression X, if its
13002    death is in an instruction with luid between FROM_LUID (inclusive) and
13003    TO_INSN (exclusive), put a REG_DEAD note for that register in the
13004    list headed by PNOTES.
13005
13006    That said, don't move registers killed by maybe_kill_insn.
13007
13008    This is done when X is being merged by combination into TO_INSN.  These
13009    notes will then be distributed as needed.  */
13010
13011 static void
13012 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13013              rtx *pnotes)
13014 {
13015   const char *fmt;
13016   int len, i;
13017   enum rtx_code code = GET_CODE (x);
13018
13019   if (code == REG)
13020     {
13021       unsigned int regno = REGNO (x);
13022       rtx where_dead = reg_stat[regno].last_death;
13023
13024       /* Don't move the register if it gets killed in between from and to.  */
13025       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13026           && ! reg_referenced_p (x, maybe_kill_insn))
13027         return;
13028
13029       if (where_dead
13030           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13031           && DF_INSN_LUID (where_dead) >= from_luid
13032           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13033         {
13034           rtx note = remove_death (regno, where_dead);
13035
13036           /* It is possible for the call above to return 0.  This can occur
13037              when last_death points to I2 or I1 that we combined with.
13038              In that case make a new note.
13039
13040              We must also check for the case where X is a hard register
13041              and NOTE is a death note for a range of hard registers
13042              including X.  In that case, we must put REG_DEAD notes for
13043              the remaining registers in place of NOTE.  */
13044
13045           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13046               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13047                   > GET_MODE_SIZE (GET_MODE (x))))
13048             {
13049               unsigned int deadregno = REGNO (XEXP (note, 0));
13050               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13051               unsigned int ourend = END_HARD_REGNO (x);
13052               unsigned int i;
13053
13054               for (i = deadregno; i < deadend; i++)
13055                 if (i < regno || i >= ourend)
13056                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13057             }
13058
13059           /* If we didn't find any note, or if we found a REG_DEAD note that
13060              covers only part of the given reg, and we have a multi-reg hard
13061              register, then to be safe we must check for REG_DEAD notes
13062              for each register other than the first.  They could have
13063              their own REG_DEAD notes lying around.  */
13064           else if ((note == 0
13065                     || (note != 0
13066                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13067                             < GET_MODE_SIZE (GET_MODE (x)))))
13068                    && regno < FIRST_PSEUDO_REGISTER
13069                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13070             {
13071               unsigned int ourend = END_HARD_REGNO (x);
13072               unsigned int i, offset;
13073               rtx oldnotes = 0;
13074
13075               if (note)
13076                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13077               else
13078                 offset = 1;
13079
13080               for (i = regno + offset; i < ourend; i++)
13081                 move_deaths (regno_reg_rtx[i],
13082                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13083             }
13084
13085           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13086             {
13087               XEXP (note, 1) = *pnotes;
13088               *pnotes = note;
13089             }
13090           else
13091             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13092         }
13093
13094       return;
13095     }
13096
13097   else if (GET_CODE (x) == SET)
13098     {
13099       rtx dest = SET_DEST (x);
13100
13101       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13102
13103       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13104          that accesses one word of a multi-word item, some
13105          piece of everything register in the expression is used by
13106          this insn, so remove any old death.  */
13107       /* ??? So why do we test for equality of the sizes?  */
13108
13109       if (GET_CODE (dest) == ZERO_EXTRACT
13110           || GET_CODE (dest) == STRICT_LOW_PART
13111           || (GET_CODE (dest) == SUBREG
13112               && (((GET_MODE_SIZE (GET_MODE (dest))
13113                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13114                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13115                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13116         {
13117           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13118           return;
13119         }
13120
13121       /* If this is some other SUBREG, we know it replaces the entire
13122          value, so use that as the destination.  */
13123       if (GET_CODE (dest) == SUBREG)
13124         dest = SUBREG_REG (dest);
13125
13126       /* If this is a MEM, adjust deaths of anything used in the address.
13127          For a REG (the only other possibility), the entire value is
13128          being replaced so the old value is not used in this insn.  */
13129
13130       if (MEM_P (dest))
13131         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13132                      to_insn, pnotes);
13133       return;
13134     }
13135
13136   else if (GET_CODE (x) == CLOBBER)
13137     return;
13138
13139   len = GET_RTX_LENGTH (code);
13140   fmt = GET_RTX_FORMAT (code);
13141
13142   for (i = 0; i < len; i++)
13143     {
13144       if (fmt[i] == 'E')
13145         {
13146           int j;
13147           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13148             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13149                          to_insn, pnotes);
13150         }
13151       else if (fmt[i] == 'e')
13152         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13153     }
13154 }
13155 \f
13156 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13157    pattern of an insn.  X must be a REG.  */
13158
13159 static int
13160 reg_bitfield_target_p (rtx x, rtx body)
13161 {
13162   int i;
13163
13164   if (GET_CODE (body) == SET)
13165     {
13166       rtx dest = SET_DEST (body);
13167       rtx target;
13168       unsigned int regno, tregno, endregno, endtregno;
13169
13170       if (GET_CODE (dest) == ZERO_EXTRACT)
13171         target = XEXP (dest, 0);
13172       else if (GET_CODE (dest) == STRICT_LOW_PART)
13173         target = SUBREG_REG (XEXP (dest, 0));
13174       else
13175         return 0;
13176
13177       if (GET_CODE (target) == SUBREG)
13178         target = SUBREG_REG (target);
13179
13180       if (!REG_P (target))
13181         return 0;
13182
13183       tregno = REGNO (target), regno = REGNO (x);
13184       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13185         return target == x;
13186
13187       endtregno = end_hard_regno (GET_MODE (target), tregno);
13188       endregno = end_hard_regno (GET_MODE (x), regno);
13189
13190       return endregno > tregno && regno < endtregno;
13191     }
13192
13193   else if (GET_CODE (body) == PARALLEL)
13194     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13195       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13196         return 1;
13197
13198   return 0;
13199 }
13200 \f
13201 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13202    as appropriate.  I3 and I2 are the insns resulting from the combination
13203    insns including FROM (I2 may be zero).
13204
13205    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13206    not need REG_DEAD notes because they are being substituted for.  This
13207    saves searching in the most common cases.
13208
13209    Each note in the list is either ignored or placed on some insns, depending
13210    on the type of note.  */
13211
13212 static void
13213 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13214                   rtx elim_i1, rtx elim_i0)
13215 {
13216   rtx note, next_note;
13217   rtx tem;
13218
13219   for (note = notes; note; note = next_note)
13220     {
13221       rtx place = 0, place2 = 0;
13222
13223       next_note = XEXP (note, 1);
13224       switch (REG_NOTE_KIND (note))
13225         {
13226         case REG_BR_PROB:
13227         case REG_BR_PRED:
13228           /* Doesn't matter much where we put this, as long as it's somewhere.
13229              It is preferable to keep these notes on branches, which is most
13230              likely to be i3.  */
13231           place = i3;
13232           break;
13233
13234         case REG_NON_LOCAL_GOTO:
13235           if (JUMP_P (i3))
13236             place = i3;
13237           else
13238             {
13239               gcc_assert (i2 && JUMP_P (i2));
13240               place = i2;
13241             }
13242           break;
13243
13244         case REG_EH_REGION:
13245           /* These notes must remain with the call or trapping instruction.  */
13246           if (CALL_P (i3))
13247             place = i3;
13248           else if (i2 && CALL_P (i2))
13249             place = i2;
13250           else
13251             {
13252               gcc_assert (cfun->can_throw_non_call_exceptions);
13253               if (may_trap_p (i3))
13254                 place = i3;
13255               else if (i2 && may_trap_p (i2))
13256                 place = i2;
13257               /* ??? Otherwise assume we've combined things such that we
13258                  can now prove that the instructions can't trap.  Drop the
13259                  note in this case.  */
13260             }
13261           break;
13262
13263         case REG_ARGS_SIZE:
13264           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13265              entire adjustment.  Assert i3 contains at least some adjust.  */
13266           if (!noop_move_p (i3))
13267             {
13268               int old_size, args_size = INTVAL (XEXP (note, 0));
13269               /* fixup_args_size_notes looks at REG_NORETURN note,
13270                  so ensure the note is placed there first.  */
13271               if (CALL_P (i3))
13272                 {
13273                   rtx *np;
13274                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13275                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13276                       {
13277                         rtx n = *np;
13278                         *np = XEXP (n, 1);
13279                         XEXP (n, 1) = REG_NOTES (i3);
13280                         REG_NOTES (i3) = n;
13281                         break;
13282                       }
13283                 }
13284               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13285               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13286                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13287               gcc_assert (old_size != args_size
13288                           || (CALL_P (i3)
13289                               && !ACCUMULATE_OUTGOING_ARGS
13290                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13291             }
13292           break;
13293
13294         case REG_NORETURN:
13295         case REG_SETJMP:
13296         case REG_TM:
13297         case REG_CALL_DECL:
13298           /* These notes must remain with the call.  It should not be
13299              possible for both I2 and I3 to be a call.  */
13300           if (CALL_P (i3))
13301             place = i3;
13302           else
13303             {
13304               gcc_assert (i2 && CALL_P (i2));
13305               place = i2;
13306             }
13307           break;
13308
13309         case REG_UNUSED:
13310           /* Any clobbers for i3 may still exist, and so we must process
13311              REG_UNUSED notes from that insn.
13312
13313              Any clobbers from i2 or i1 can only exist if they were added by
13314              recog_for_combine.  In that case, recog_for_combine created the
13315              necessary REG_UNUSED notes.  Trying to keep any original
13316              REG_UNUSED notes from these insns can cause incorrect output
13317              if it is for the same register as the original i3 dest.
13318              In that case, we will notice that the register is set in i3,
13319              and then add a REG_UNUSED note for the destination of i3, which
13320              is wrong.  However, it is possible to have REG_UNUSED notes from
13321              i2 or i1 for register which were both used and clobbered, so
13322              we keep notes from i2 or i1 if they will turn into REG_DEAD
13323              notes.  */
13324
13325           /* If this register is set or clobbered in I3, put the note there
13326              unless there is one already.  */
13327           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13328             {
13329               if (from_insn != i3)
13330                 break;
13331
13332               if (! (REG_P (XEXP (note, 0))
13333                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13334                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13335                 place = i3;
13336             }
13337           /* Otherwise, if this register is used by I3, then this register
13338              now dies here, so we must put a REG_DEAD note here unless there
13339              is one already.  */
13340           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13341                    && ! (REG_P (XEXP (note, 0))
13342                          ? find_regno_note (i3, REG_DEAD,
13343                                             REGNO (XEXP (note, 0)))
13344                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13345             {
13346               PUT_REG_NOTE_KIND (note, REG_DEAD);
13347               place = i3;
13348             }
13349           break;
13350
13351         case REG_EQUAL:
13352         case REG_EQUIV:
13353         case REG_NOALIAS:
13354           /* These notes say something about results of an insn.  We can
13355              only support them if they used to be on I3 in which case they
13356              remain on I3.  Otherwise they are ignored.
13357
13358              If the note refers to an expression that is not a constant, we
13359              must also ignore the note since we cannot tell whether the
13360              equivalence is still true.  It might be possible to do
13361              slightly better than this (we only have a problem if I2DEST
13362              or I1DEST is present in the expression), but it doesn't
13363              seem worth the trouble.  */
13364
13365           if (from_insn == i3
13366               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13367             place = i3;
13368           break;
13369
13370         case REG_INC:
13371           /* These notes say something about how a register is used.  They must
13372              be present on any use of the register in I2 or I3.  */
13373           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13374             place = i3;
13375
13376           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13377             {
13378               if (place)
13379                 place2 = i2;
13380               else
13381                 place = i2;
13382             }
13383           break;
13384
13385         case REG_LABEL_TARGET:
13386         case REG_LABEL_OPERAND:
13387           /* This can show up in several ways -- either directly in the
13388              pattern, or hidden off in the constant pool with (or without?)
13389              a REG_EQUAL note.  */
13390           /* ??? Ignore the without-reg_equal-note problem for now.  */
13391           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13392               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13393                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13394                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13395             place = i3;
13396
13397           if (i2
13398               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13399                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13400                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13401                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13402             {
13403               if (place)
13404                 place2 = i2;
13405               else
13406                 place = i2;
13407             }
13408
13409           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13410              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13411              there.  */
13412           if (place && JUMP_P (place)
13413               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13414               && (JUMP_LABEL (place) == NULL
13415                   || JUMP_LABEL (place) == XEXP (note, 0)))
13416             {
13417               rtx label = JUMP_LABEL (place);
13418
13419               if (!label)
13420                 JUMP_LABEL (place) = XEXP (note, 0);
13421               else if (LABEL_P (label))
13422                 LABEL_NUSES (label)--;
13423             }
13424
13425           if (place2 && JUMP_P (place2)
13426               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13427               && (JUMP_LABEL (place2) == NULL
13428                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13429             {
13430               rtx label = JUMP_LABEL (place2);
13431
13432               if (!label)
13433                 JUMP_LABEL (place2) = XEXP (note, 0);
13434               else if (LABEL_P (label))
13435                 LABEL_NUSES (label)--;
13436               place2 = 0;
13437             }
13438           break;
13439
13440         case REG_NONNEG:
13441           /* This note says something about the value of a register prior
13442              to the execution of an insn.  It is too much trouble to see
13443              if the note is still correct in all situations.  It is better
13444              to simply delete it.  */
13445           break;
13446
13447         case REG_DEAD:
13448           /* If we replaced the right hand side of FROM_INSN with a
13449              REG_EQUAL note, the original use of the dying register
13450              will not have been combined into I3 and I2.  In such cases,
13451              FROM_INSN is guaranteed to be the first of the combined
13452              instructions, so we simply need to search back before
13453              FROM_INSN for the previous use or set of this register,
13454              then alter the notes there appropriately.
13455
13456              If the register is used as an input in I3, it dies there.
13457              Similarly for I2, if it is nonzero and adjacent to I3.
13458
13459              If the register is not used as an input in either I3 or I2
13460              and it is not one of the registers we were supposed to eliminate,
13461              there are two possibilities.  We might have a non-adjacent I2
13462              or we might have somehow eliminated an additional register
13463              from a computation.  For example, we might have had A & B where
13464              we discover that B will always be zero.  In this case we will
13465              eliminate the reference to A.
13466
13467              In both cases, we must search to see if we can find a previous
13468              use of A and put the death note there.  */
13469
13470           if (from_insn
13471               && from_insn == i2mod
13472               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13473             tem = from_insn;
13474           else
13475             {
13476               if (from_insn
13477                   && CALL_P (from_insn)
13478                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13479                 place = from_insn;
13480               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13481                 place = i3;
13482               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13483                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13484                 place = i2;
13485               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13486                         && !(i2mod
13487                              && reg_overlap_mentioned_p (XEXP (note, 0),
13488                                                          i2mod_old_rhs)))
13489                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13490                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13491                 break;
13492               tem = i3;
13493             }
13494
13495           if (place == 0)
13496             {
13497               basic_block bb = this_basic_block;
13498
13499               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13500                 {
13501                   if (!NONDEBUG_INSN_P (tem))
13502                     {
13503                       if (tem == BB_HEAD (bb))
13504                         break;
13505                       continue;
13506                     }
13507
13508                   /* If the register is being set at TEM, see if that is all
13509                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13510                      into a REG_UNUSED note instead. Don't delete sets to
13511                      global register vars.  */
13512                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13513                        || !global_regs[REGNO (XEXP (note, 0))])
13514                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13515                     {
13516                       rtx set = single_set (tem);
13517                       rtx inner_dest = 0;
13518 #ifdef HAVE_cc0
13519                       rtx cc0_setter = NULL_RTX;
13520 #endif
13521
13522                       if (set != 0)
13523                         for (inner_dest = SET_DEST (set);
13524                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13525                               || GET_CODE (inner_dest) == SUBREG
13526                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13527                              inner_dest = XEXP (inner_dest, 0))
13528                           ;
13529
13530                       /* Verify that it was the set, and not a clobber that
13531                          modified the register.
13532
13533                          CC0 targets must be careful to maintain setter/user
13534                          pairs.  If we cannot delete the setter due to side
13535                          effects, mark the user with an UNUSED note instead
13536                          of deleting it.  */
13537
13538                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13539                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13540 #ifdef HAVE_cc0
13541                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13542                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13543                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13544 #endif
13545                           )
13546                         {
13547                           /* Move the notes and links of TEM elsewhere.
13548                              This might delete other dead insns recursively.
13549                              First set the pattern to something that won't use
13550                              any register.  */
13551                           rtx old_notes = REG_NOTES (tem);
13552
13553                           PATTERN (tem) = pc_rtx;
13554                           REG_NOTES (tem) = NULL;
13555
13556                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13557                                             NULL_RTX, NULL_RTX, NULL_RTX);
13558                           distribute_links (LOG_LINKS (tem));
13559
13560                           SET_INSN_DELETED (tem);
13561                           if (tem == i2)
13562                             i2 = NULL_RTX;
13563
13564 #ifdef HAVE_cc0
13565                           /* Delete the setter too.  */
13566                           if (cc0_setter)
13567                             {
13568                               PATTERN (cc0_setter) = pc_rtx;
13569                               old_notes = REG_NOTES (cc0_setter);
13570                               REG_NOTES (cc0_setter) = NULL;
13571
13572                               distribute_notes (old_notes, cc0_setter,
13573                                                 cc0_setter, NULL_RTX,
13574                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13575                               distribute_links (LOG_LINKS (cc0_setter));
13576
13577                               SET_INSN_DELETED (cc0_setter);
13578                               if (cc0_setter == i2)
13579                                 i2 = NULL_RTX;
13580                             }
13581 #endif
13582                         }
13583                       else
13584                         {
13585                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13586
13587                           /*  If there isn't already a REG_UNUSED note, put one
13588                               here.  Do not place a REG_DEAD note, even if
13589                               the register is also used here; that would not
13590                               match the algorithm used in lifetime analysis
13591                               and can cause the consistency check in the
13592                               scheduler to fail.  */
13593                           if (! find_regno_note (tem, REG_UNUSED,
13594                                                  REGNO (XEXP (note, 0))))
13595                             place = tem;
13596                           break;
13597                         }
13598                     }
13599                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13600                            || (CALL_P (tem)
13601                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13602                     {
13603                       place = tem;
13604
13605                       /* If we are doing a 3->2 combination, and we have a
13606                          register which formerly died in i3 and was not used
13607                          by i2, which now no longer dies in i3 and is used in
13608                          i2 but does not die in i2, and place is between i2
13609                          and i3, then we may need to move a link from place to
13610                          i2.  */
13611                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13612                           && from_insn
13613                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13614                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13615                         {
13616                           struct insn_link *links = LOG_LINKS (place);
13617                           LOG_LINKS (place) = NULL;
13618                           distribute_links (links);
13619                         }
13620                       break;
13621                     }
13622
13623                   if (tem == BB_HEAD (bb))
13624                     break;
13625                 }
13626
13627             }
13628
13629           /* If the register is set or already dead at PLACE, we needn't do
13630              anything with this note if it is still a REG_DEAD note.
13631              We check here if it is set at all, not if is it totally replaced,
13632              which is what `dead_or_set_p' checks, so also check for it being
13633              set partially.  */
13634
13635           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13636             {
13637               unsigned int regno = REGNO (XEXP (note, 0));
13638               reg_stat_type *rsp = &reg_stat[regno];
13639
13640               if (dead_or_set_p (place, XEXP (note, 0))
13641                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13642                 {
13643                   /* Unless the register previously died in PLACE, clear
13644                      last_death.  [I no longer understand why this is
13645                      being done.] */
13646                   if (rsp->last_death != place)
13647                     rsp->last_death = 0;
13648                   place = 0;
13649                 }
13650               else
13651                 rsp->last_death = place;
13652
13653               /* If this is a death note for a hard reg that is occupying
13654                  multiple registers, ensure that we are still using all
13655                  parts of the object.  If we find a piece of the object
13656                  that is unused, we must arrange for an appropriate REG_DEAD
13657                  note to be added for it.  However, we can't just emit a USE
13658                  and tag the note to it, since the register might actually
13659                  be dead; so we recourse, and the recursive call then finds
13660                  the previous insn that used this register.  */
13661
13662               if (place && regno < FIRST_PSEUDO_REGISTER
13663                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13664                 {
13665                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13666                   bool all_used = true;
13667                   unsigned int i;
13668
13669                   for (i = regno; i < endregno; i++)
13670                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13671                          && ! find_regno_fusage (place, USE, i))
13672                         || dead_or_set_regno_p (place, i))
13673                       {
13674                         all_used = false;
13675                         break;
13676                       }
13677
13678                   if (! all_used)
13679                     {
13680                       /* Put only REG_DEAD notes for pieces that are
13681                          not already dead or set.  */
13682
13683                       for (i = regno; i < endregno;
13684                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13685                         {
13686                           rtx piece = regno_reg_rtx[i];
13687                           basic_block bb = this_basic_block;
13688
13689                           if (! dead_or_set_p (place, piece)
13690                               && ! reg_bitfield_target_p (piece,
13691                                                           PATTERN (place)))
13692                             {
13693                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13694                                                              NULL_RTX);
13695
13696                               distribute_notes (new_note, place, place,
13697                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13698                                                 NULL_RTX);
13699                             }
13700                           else if (! refers_to_regno_p (i, i + 1,
13701                                                         PATTERN (place), 0)
13702                                    && ! find_regno_fusage (place, USE, i))
13703                             for (tem = PREV_INSN (place); ;
13704                                  tem = PREV_INSN (tem))
13705                               {
13706                                 if (!NONDEBUG_INSN_P (tem))
13707                                   {
13708                                     if (tem == BB_HEAD (bb))
13709                                       break;
13710                                     continue;
13711                                   }
13712                                 if (dead_or_set_p (tem, piece)
13713                                     || reg_bitfield_target_p (piece,
13714                                                               PATTERN (tem)))
13715                                   {
13716                                     add_reg_note (tem, REG_UNUSED, piece);
13717                                     break;
13718                                   }
13719                               }
13720                         }
13721
13722                       place = 0;
13723                     }
13724                 }
13725             }
13726           break;
13727
13728         default:
13729           /* Any other notes should not be present at this point in the
13730              compilation.  */
13731           gcc_unreachable ();
13732         }
13733
13734       if (place)
13735         {
13736           XEXP (note, 1) = REG_NOTES (place);
13737           REG_NOTES (place) = note;
13738         }
13739
13740       if (place2)
13741         add_shallow_copy_of_reg_note (place2, note);
13742     }
13743 }
13744 \f
13745 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13746    I3, I2, and I1 to new locations.  This is also called to add a link
13747    pointing at I3 when I3's destination is changed.  */
13748
13749 static void
13750 distribute_links (struct insn_link *links)
13751 {
13752   struct insn_link *link, *next_link;
13753
13754   for (link = links; link; link = next_link)
13755     {
13756       rtx place = 0;
13757       rtx insn;
13758       rtx set, reg;
13759
13760       next_link = link->next;
13761
13762       /* If the insn that this link points to is a NOTE or isn't a single
13763          set, ignore it.  In the latter case, it isn't clear what we
13764          can do other than ignore the link, since we can't tell which
13765          register it was for.  Such links wouldn't be used by combine
13766          anyway.
13767
13768          It is not possible for the destination of the target of the link to
13769          have been changed by combine.  The only potential of this is if we
13770          replace I3, I2, and I1 by I3 and I2.  But in that case the
13771          destination of I2 also remains unchanged.  */
13772
13773       if (NOTE_P (link->insn)
13774           || (set = single_set (link->insn)) == 0)
13775         continue;
13776
13777       reg = SET_DEST (set);
13778       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13779              || GET_CODE (reg) == STRICT_LOW_PART)
13780         reg = XEXP (reg, 0);
13781
13782       /* A LOG_LINK is defined as being placed on the first insn that uses
13783          a register and points to the insn that sets the register.  Start
13784          searching at the next insn after the target of the link and stop
13785          when we reach a set of the register or the end of the basic block.
13786
13787          Note that this correctly handles the link that used to point from
13788          I3 to I2.  Also note that not much searching is typically done here
13789          since most links don't point very far away.  */
13790
13791       for (insn = NEXT_INSN (link->insn);
13792            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
13793                      || BB_HEAD (this_basic_block->next_bb) != insn));
13794            insn = NEXT_INSN (insn))
13795         if (DEBUG_INSN_P (insn))
13796           continue;
13797         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13798           {
13799             if (reg_referenced_p (reg, PATTERN (insn)))
13800               place = insn;
13801             break;
13802           }
13803         else if (CALL_P (insn)
13804                  && find_reg_fusage (insn, USE, reg))
13805           {
13806             place = insn;
13807             break;
13808           }
13809         else if (INSN_P (insn) && reg_set_p (reg, insn))
13810           break;
13811
13812       /* If we found a place to put the link, place it there unless there
13813          is already a link to the same insn as LINK at that point.  */
13814
13815       if (place)
13816         {
13817           struct insn_link *link2;
13818
13819           FOR_EACH_LOG_LINK (link2, place)
13820             if (link2->insn == link->insn)
13821               break;
13822
13823           if (link2 == NULL)
13824             {
13825               link->next = LOG_LINKS (place);
13826               LOG_LINKS (place) = link;
13827
13828               /* Set added_links_insn to the earliest insn we added a
13829                  link to.  */
13830               if (added_links_insn == 0
13831                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13832                 added_links_insn = place;
13833             }
13834         }
13835     }
13836 }
13837 \f
13838 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13839    Check whether the expression pointer to by LOC is a register or
13840    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13841    Otherwise return zero.  */
13842
13843 static int
13844 unmentioned_reg_p_1 (rtx *loc, void *expr)
13845 {
13846   rtx x = *loc;
13847
13848   if (x != NULL_RTX
13849       && (REG_P (x) || MEM_P (x))
13850       && ! reg_mentioned_p (x, (rtx) expr))
13851     return 1;
13852   return 0;
13853 }
13854
13855 /* Check for any register or memory mentioned in EQUIV that is not
13856    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13857    of EXPR where some registers may have been replaced by constants.  */
13858
13859 static bool
13860 unmentioned_reg_p (rtx equiv, rtx expr)
13861 {
13862   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13863 }
13864 \f
13865 DEBUG_FUNCTION void
13866 dump_combine_stats (FILE *file)
13867 {
13868   fprintf
13869     (file,
13870      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13871      combine_attempts, combine_merges, combine_extras, combine_successes);
13872 }
13873
13874 void
13875 dump_combine_total_stats (FILE *file)
13876 {
13877   fprintf
13878     (file,
13879      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13880      total_attempts, total_merges, total_extras, total_successes);
13881 }
13882 \f
13883 /* Try combining insns through substitution.  */
13884 static unsigned int
13885 rest_of_handle_combine (void)
13886 {
13887   int rebuild_jump_labels_after_combine;
13888
13889   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13890   df_note_add_problem ();
13891   df_analyze ();
13892
13893   regstat_init_n_sets_and_refs ();
13894
13895   rebuild_jump_labels_after_combine
13896     = combine_instructions (get_insns (), max_reg_num ());
13897
13898   /* Combining insns may have turned an indirect jump into a
13899      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13900      instructions.  */
13901   if (rebuild_jump_labels_after_combine)
13902     {
13903       timevar_push (TV_JUMP);
13904       rebuild_jump_labels (get_insns ());
13905       cleanup_cfg (0);
13906       timevar_pop (TV_JUMP);
13907     }
13908
13909   regstat_free_n_sets_and_refs ();
13910   return 0;
13911 }
13912
13913 namespace {
13914
13915 const pass_data pass_data_combine =
13916 {
13917   RTL_PASS, /* type */
13918   "combine", /* name */
13919   OPTGROUP_NONE, /* optinfo_flags */
13920   TV_COMBINE, /* tv_id */
13921   PROP_cfglayout, /* properties_required */
13922   0, /* properties_provided */
13923   0, /* properties_destroyed */
13924   0, /* todo_flags_start */
13925   TODO_df_finish, /* todo_flags_finish */
13926 };
13927
13928 class pass_combine : public rtl_opt_pass
13929 {
13930 public:
13931   pass_combine (gcc::context *ctxt)
13932     : rtl_opt_pass (pass_data_combine, ctxt)
13933   {}
13934
13935   /* opt_pass methods: */
13936   virtual bool gate (function *) { return (optimize > 0); }
13937   virtual unsigned int execute (function *)
13938     {
13939       return rest_of_handle_combine ();
13940     }
13941
13942 }; // class pass_combine
13943
13944 } // anon namespace
13945
13946 rtl_opt_pass *
13947 make_pass_combine (gcc::context *ctxt)
13948 {
13949   return new pass_combine (ctxt);
13950 }